1 /* 2 * Performance events x86 architecture header 3 * 4 * Copyright (C) 2008 Linutronix GmbH, Thomas Gleixner <tglx@kernel.org> 5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2009 Jaswinder Singh Rajput 7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> 10 * Copyright (C) 2009 Google, Inc., Stephane Eranian 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 15 #include <linux/perf_event.h> 16 17 #include <asm/fpu/xstate.h> 18 #include <asm/intel_ds.h> 19 #include <asm/cpu.h> 20 #include <asm/msr.h> 21 22 /* To enable MSR tracing please use the generic trace points. */ 23 24 /* 25 * | NHM/WSM | SNB | 26 * register ------------------------------- 27 * | HT | no HT | HT | no HT | 28 *----------------------------------------- 29 * offcore | core | core | cpu | core | 30 * lbr_sel | core | core | cpu | core | 31 * ld_lat | cpu | core | cpu | core | 32 *----------------------------------------- 33 * 34 * Given that there is a small number of shared regs, 35 * we can pre-allocate their slot in the per-cpu 36 * per-core reg tables. 37 */ 38 enum extra_reg_type { 39 EXTRA_REG_NONE = -1, /* not used */ 40 41 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ 42 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ 43 EXTRA_REG_LBR = 2, /* lbr_select */ 44 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ 45 EXTRA_REG_FE = 4, /* fe_* */ 46 EXTRA_REG_SNOOP_0 = 5, /* snoop response 0 */ 47 EXTRA_REG_SNOOP_1 = 6, /* snoop response 1 */ 48 EXTRA_REG_OMR_0 = 7, /* OMR 0 */ 49 EXTRA_REG_OMR_1 = 8, /* OMR 1 */ 50 EXTRA_REG_OMR_2 = 9, /* OMR 2 */ 51 EXTRA_REG_OMR_3 = 10, /* OMR 3 */ 52 53 EXTRA_REG_MAX /* number of entries needed */ 54 }; 55 56 struct event_constraint { 57 union { 58 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 59 u64 idxmsk64; 60 }; 61 u64 code; 62 u64 cmask; 63 int weight; 64 int overlap; 65 int flags; 66 unsigned int size; 67 }; 68 69 static inline bool constraint_match(struct event_constraint *c, u64 ecode) 70 { 71 return ((ecode & c->cmask) - c->code) <= (u64)c->size; 72 } 73 74 #define PERF_ARCH(name, val) \ 75 PERF_X86_EVENT_##name = val, 76 77 /* 78 * struct hw_perf_event.flags flags 79 */ 80 enum { 81 #include "perf_event_flags.h" 82 }; 83 84 #undef PERF_ARCH 85 86 #define PERF_ARCH(name, val) \ 87 static_assert((PERF_X86_EVENT_##name & PERF_EVENT_FLAG_ARCH) == \ 88 PERF_X86_EVENT_##name); 89 90 #include "perf_event_flags.h" 91 92 #undef PERF_ARCH 93 94 static inline bool is_topdown_count(struct perf_event *event) 95 { 96 return event->hw.flags & PERF_X86_EVENT_TOPDOWN; 97 } 98 99 static inline bool is_metric_event(struct perf_event *event) 100 { 101 u64 config = event->attr.config; 102 103 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) && 104 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) && 105 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX); 106 } 107 108 static inline bool is_slots_event(struct perf_event *event) 109 { 110 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS; 111 } 112 113 static inline bool is_topdown_event(struct perf_event *event) 114 { 115 return is_metric_event(event) || is_slots_event(event); 116 } 117 118 int is_x86_event(struct perf_event *event); 119 120 static inline bool check_leader_group(struct perf_event *leader, int flags) 121 { 122 return is_x86_event(leader) ? !!(leader->hw.flags & flags) : false; 123 } 124 125 static inline bool is_branch_counters_group(struct perf_event *event) 126 { 127 return check_leader_group(event->group_leader, PERF_X86_EVENT_BRANCH_COUNTERS); 128 } 129 130 static inline bool is_pebs_counter_event_group(struct perf_event *event) 131 { 132 return check_leader_group(event->group_leader, PERF_X86_EVENT_PEBS_CNTR); 133 } 134 135 static inline bool is_acr_event_group(struct perf_event *event) 136 { 137 return check_leader_group(event->group_leader, PERF_X86_EVENT_ACR); 138 } 139 140 static inline bool is_acr_self_reload_event(struct perf_event *event) 141 { 142 struct hw_perf_event *hwc = &event->hw; 143 144 if (hwc->idx < 0 || !is_acr_event_group(event)) 145 return false; 146 147 return test_bit(hwc->idx, (unsigned long *)&hwc->config1); 148 } 149 150 struct amd_nb { 151 int nb_id; /* NorthBridge id */ 152 int refcnt; /* reference count */ 153 struct perf_event *owners[X86_PMC_IDX_MAX]; 154 struct event_constraint event_constraints[X86_PMC_IDX_MAX]; 155 }; 156 157 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1) 158 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60) 159 #define PEBS_OUTPUT_OFFSET 61 160 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET) 161 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET) 162 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD) 163 164 /* 165 * Flags PEBS can handle without an PMI. 166 * 167 * TID can only be handled by flushing at context switch. 168 * REGS_USER can be handled for events limited to ring 3. 169 * 170 */ 171 #define LARGE_PEBS_FLAGS \ 172 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 173 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 174 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ 175 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ 176 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \ 177 PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE | \ 178 PERF_SAMPLE_WEIGHT_TYPE) 179 180 #define PEBS_GP_REGS \ 181 ((1ULL << PERF_REG_X86_AX) | \ 182 (1ULL << PERF_REG_X86_BX) | \ 183 (1ULL << PERF_REG_X86_CX) | \ 184 (1ULL << PERF_REG_X86_DX) | \ 185 (1ULL << PERF_REG_X86_DI) | \ 186 (1ULL << PERF_REG_X86_SI) | \ 187 (1ULL << PERF_REG_X86_SP) | \ 188 (1ULL << PERF_REG_X86_BP) | \ 189 (1ULL << PERF_REG_X86_IP) | \ 190 (1ULL << PERF_REG_X86_FLAGS) | \ 191 (1ULL << PERF_REG_X86_R8) | \ 192 (1ULL << PERF_REG_X86_R9) | \ 193 (1ULL << PERF_REG_X86_R10) | \ 194 (1ULL << PERF_REG_X86_R11) | \ 195 (1ULL << PERF_REG_X86_R12) | \ 196 (1ULL << PERF_REG_X86_R13) | \ 197 (1ULL << PERF_REG_X86_R14) | \ 198 (1ULL << PERF_REG_X86_R15)) 199 200 /* user space rdpmc control values */ 201 enum { 202 X86_USER_RDPMC_NEVER_ENABLE = 0, 203 X86_USER_RDPMC_CONDITIONAL_ENABLE = 1, 204 X86_USER_RDPMC_ALWAYS_ENABLE = 2, 205 }; 206 207 /* 208 * Per register state. 209 */ 210 struct er_account { 211 raw_spinlock_t lock; /* per-core: protect structure */ 212 u64 config; /* extra MSR config */ 213 u64 reg; /* extra MSR number */ 214 atomic_t ref; /* reference count */ 215 }; 216 217 /* 218 * Per core/cpu state 219 * 220 * Used to coordinate shared registers between HT threads or 221 * among events on a single PMU. 222 */ 223 struct intel_shared_regs { 224 struct er_account regs[EXTRA_REG_MAX]; 225 int refcnt; /* per-core: #HT threads */ 226 unsigned core_id; /* per-core: core id */ 227 }; 228 229 enum intel_excl_state_type { 230 INTEL_EXCL_UNUSED = 0, /* counter is unused */ 231 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */ 232 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */ 233 }; 234 235 struct intel_excl_states { 236 enum intel_excl_state_type state[X86_PMC_IDX_MAX]; 237 bool sched_started; /* true if scheduling has started */ 238 }; 239 240 struct intel_excl_cntrs { 241 raw_spinlock_t lock; 242 243 struct intel_excl_states states[2]; 244 245 union { 246 u16 has_exclusive[2]; 247 u32 exclusive_present; 248 }; 249 250 int refcnt; /* per-core: #HT threads */ 251 unsigned core_id; /* per-core: core id */ 252 }; 253 254 struct x86_perf_task_context; 255 #define MAX_LBR_ENTRIES 32 256 257 enum { 258 LBR_FORMAT_32 = 0x00, 259 LBR_FORMAT_LIP = 0x01, 260 LBR_FORMAT_EIP = 0x02, 261 LBR_FORMAT_EIP_FLAGS = 0x03, 262 LBR_FORMAT_EIP_FLAGS2 = 0x04, 263 LBR_FORMAT_INFO = 0x05, 264 LBR_FORMAT_TIME = 0x06, 265 LBR_FORMAT_INFO2 = 0x07, 266 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_INFO2, 267 }; 268 269 enum { 270 X86_PERF_KFREE_SHARED = 0, 271 X86_PERF_KFREE_EXCL = 1, 272 X86_PERF_KFREE_MAX 273 }; 274 275 struct cpu_hw_events { 276 /* 277 * Generic x86 PMC bits 278 */ 279 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ 280 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 281 unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 282 int enabled; 283 284 int n_events; /* the # of events in the below arrays */ 285 int n_added; /* the # last events in the below arrays; 286 they've never been enabled yet */ 287 int n_txn; /* the # last events in the below arrays; 288 added in the current transaction */ 289 int n_txn_pair; 290 int n_txn_metric; 291 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ 292 u64 tags[X86_PMC_IDX_MAX]; 293 294 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ 295 struct event_constraint *event_constraint[X86_PMC_IDX_MAX]; 296 297 int n_excl; /* the number of exclusive events */ 298 int n_late_setup; /* the num of events needs late setup */ 299 300 unsigned int txn_flags; 301 int is_fake; 302 303 /* 304 * Intel DebugStore bits 305 */ 306 struct debug_store *ds; 307 void *ds_bts_vaddr; 308 /* DS based PEBS or arch-PEBS buffer address */ 309 void *pebs_vaddr; 310 u64 pebs_enabled; 311 int n_pebs; 312 int n_large_pebs; 313 int n_pebs_via_pt; 314 int pebs_output; 315 316 /* Current super set of events hardware configuration */ 317 u64 pebs_data_cfg; 318 u64 active_pebs_data_cfg; 319 int pebs_record_size; 320 321 /* Intel Fixed counter configuration */ 322 u64 fixed_ctrl_val; 323 u64 active_fixed_ctrl_val; 324 325 /* Intel ACR/arch-PEBS configuration */ 326 u64 acr_cfg_b[X86_PMC_IDX_MAX]; 327 u64 cfg_c_val[X86_PMC_IDX_MAX]; 328 329 /* 330 * Intel LBR bits 331 */ 332 int lbr_users; 333 int lbr_pebs_users; 334 struct perf_branch_stack lbr_stack; 335 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; 336 u64 lbr_counters[MAX_LBR_ENTRIES]; /* branch stack extra */ 337 union { 338 struct er_account *lbr_sel; 339 struct er_account *lbr_ctl; 340 }; 341 u64 br_sel; 342 void *last_task_ctx; 343 int last_log_id; 344 int lbr_select; 345 void *lbr_xsave; 346 347 /* 348 * Intel host/guest exclude bits 349 */ 350 u64 intel_ctrl_guest_mask; 351 u64 intel_ctrl_host_mask; 352 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX]; 353 354 /* 355 * Intel checkpoint mask 356 */ 357 u64 intel_cp_status; 358 359 /* 360 * manage shared (per-core, per-cpu) registers 361 * used on Intel NHM/WSM/SNB 362 */ 363 struct intel_shared_regs *shared_regs; 364 /* 365 * manage exclusive counter access between hyperthread 366 */ 367 struct event_constraint *constraint_list; /* in enable order */ 368 struct intel_excl_cntrs *excl_cntrs; 369 int excl_thread_id; /* 0 or 1 */ 370 371 /* 372 * SKL TSX_FORCE_ABORT shadow 373 */ 374 u64 tfa_shadow; 375 376 /* 377 * Perf Metrics 378 */ 379 /* number of accepted metrics events */ 380 int n_metric; 381 382 /* 383 * AMD specific bits 384 */ 385 struct amd_nb *amd_nb; 386 int brs_active; /* BRS is enabled */ 387 388 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ 389 u64 perf_ctr_virt_mask; 390 int n_pair; /* Large increment events */ 391 392 void *kfree_on_online[X86_PERF_KFREE_MAX]; 393 394 struct pmu *pmu; 395 }; 396 397 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \ 398 { .idxmsk64 = (n) }, \ 399 .code = (c), \ 400 .size = (e) - (c), \ 401 .cmask = (m), \ 402 .weight = (w), \ 403 .overlap = (o), \ 404 .flags = f, \ 405 } 406 407 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \ 408 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f) 409 410 #define EVENT_CONSTRAINT(c, n, m) \ 411 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0) 412 413 /* 414 * The constraint_match() function only works for 'simple' event codes 415 * and not for extended (AMD64_EVENTSEL_EVENT) events codes. 416 */ 417 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \ 418 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0) 419 420 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \ 421 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\ 422 0, PERF_X86_EVENT_EXCL) 423 424 /* 425 * The overlap flag marks event constraints with overlapping counter 426 * masks. This is the case if the counter mask of such an event is not 427 * a subset of any other counter mask of a constraint with an equal or 428 * higher weight, e.g.: 429 * 430 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); 431 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0); 432 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0); 433 * 434 * The event scheduler may not select the correct counter in the first 435 * cycle because it needs to know which subsequent events will be 436 * scheduled. It may fail to schedule the events then. So we set the 437 * overlap flag for such constraints to give the scheduler a hint which 438 * events to select for counter rescheduling. 439 * 440 * Care must be taken as the rescheduling algorithm is O(n!) which 441 * will increase scheduling cycles for an over-committed system 442 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros 443 * and its counter masks must be kept at a minimum. 444 */ 445 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \ 446 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0) 447 448 /* 449 * Constraint on the Event code. 450 */ 451 #define INTEL_EVENT_CONSTRAINT(c, n) \ 452 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) 453 454 /* 455 * Constraint on a range of Event codes 456 */ 457 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \ 458 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT) 459 460 /* 461 * Constraint on the Event code + UMask + fixed-mask 462 * 463 * filter mask to validate fixed counter events. 464 * the following filters disqualify for fixed counters: 465 * - inv 466 * - edge 467 * - cnt-mask 468 * - in_tx 469 * - in_tx_checkpointed 470 * The other filters are supported by fixed counters. 471 * The any-thread option is supported starting with v3. 472 */ 473 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED) 474 #define FIXED_EVENT_CONSTRAINT(c, n) \ 475 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS) 476 477 /* 478 * The special metric counters do not actually exist. They are calculated from 479 * the combination of the FxCtr3 + MSR_PERF_METRICS. 480 * 481 * The special metric counters are mapped to a dummy offset for the scheduler. 482 * The sharing between multiple users of the same metric without multiplexing 483 * is not allowed, even though the hardware supports that in principle. 484 */ 485 486 #define METRIC_EVENT_CONSTRAINT(c, n) \ 487 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \ 488 INTEL_ARCH_EVENT_MASK) 489 490 /* 491 * Constraint on the Event code + UMask 492 */ 493 #define INTEL_UEVENT_CONSTRAINT(c, n) \ 494 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) 495 496 /* Constraint on specific umask bit only + event */ 497 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \ 498 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c)) 499 500 /* Like UEVENT_CONSTRAINT, but match flags too */ 501 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \ 502 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) 503 504 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \ 505 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \ 506 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL) 507 508 #define INTEL_PLD_CONSTRAINT(c, n) \ 509 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 510 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT) 511 512 #define INTEL_PSD_CONSTRAINT(c, n) \ 513 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 514 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT) 515 516 #define INTEL_PST_CONSTRAINT(c, n) \ 517 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 518 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) 519 520 #define INTEL_HYBRID_LDLAT_CONSTRAINT(c, n) \ 521 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 522 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_LD_HSW) 523 524 #define INTEL_HYBRID_STLAT_CONSTRAINT(c, n) \ 525 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 526 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_ST_HSW) 527 528 /* Event constraint, but match on all event flags too. */ 529 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \ 530 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 531 532 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ 533 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) 534 535 /* Check only flags, but allow all event/umask */ 536 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ 537 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) 538 539 /* Check flags and event code, and set the HSW store flag */ 540 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \ 541 __EVENT_CONSTRAINT(code, n, \ 542 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 543 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 544 545 /* Check flags and event code, and set the HSW load flag */ 546 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ 547 __EVENT_CONSTRAINT(code, n, \ 548 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 549 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 550 551 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \ 552 __EVENT_CONSTRAINT_RANGE(code, end, n, \ 553 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 554 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 555 556 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \ 557 __EVENT_CONSTRAINT(code, n, \ 558 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 559 HWEIGHT(n), 0, \ 560 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 561 562 /* Check flags and event code/umask, and set the HSW store flag */ 563 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ 564 __EVENT_CONSTRAINT(code, n, \ 565 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 566 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 567 568 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \ 569 __EVENT_CONSTRAINT(code, n, \ 570 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 571 HWEIGHT(n), 0, \ 572 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL) 573 574 /* Check flags and event code/umask, and set the HSW load flag */ 575 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ 576 __EVENT_CONSTRAINT(code, n, \ 577 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 578 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 579 580 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \ 581 __EVENT_CONSTRAINT(code, n, \ 582 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 583 HWEIGHT(n), 0, \ 584 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL) 585 586 /* Check flags and event code/umask, and set the HSW N/A flag */ 587 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ 588 __EVENT_CONSTRAINT(code, n, \ 589 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 590 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW) 591 592 593 /* 594 * We define the end marker as having a weight of -1 595 * to enable blacklisting of events using a counter bitmask 596 * of zero and thus a weight of zero. 597 * The end marker has a weight that cannot possibly be 598 * obtained from counting the bits in the bitmask. 599 */ 600 #define EVENT_CONSTRAINT_END { .weight = -1 } 601 602 /* 603 * Check for end marker with weight == -1 604 */ 605 #define for_each_event_constraint(e, c) \ 606 for ((e) = (c); (e)->weight != -1; (e)++) 607 608 /* 609 * Extra registers for specific events. 610 * 611 * Some events need large masks and require external MSRs. 612 * Those extra MSRs end up being shared for all events on 613 * a PMU and sometimes between PMU of sibling HT threads. 614 * In either case, the kernel needs to handle conflicting 615 * accesses to those extra, shared, regs. The data structure 616 * to manage those registers is stored in cpu_hw_event. 617 */ 618 struct extra_reg { 619 unsigned int event; 620 unsigned int msr; 621 u64 config_mask; 622 u64 valid_mask; 623 int idx; /* per_xxx->regs[] reg index */ 624 bool extra_msr_access; 625 }; 626 627 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ 628 .event = (e), \ 629 .msr = (ms), \ 630 .config_mask = (m), \ 631 .valid_mask = (vm), \ 632 .idx = EXTRA_REG_##i, \ 633 .extra_msr_access = true, \ 634 } 635 636 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ 637 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) 638 639 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \ 640 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \ 641 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx) 642 643 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \ 644 INTEL_UEVENT_EXTRA_REG(c, \ 645 MSR_PEBS_LD_LAT_THRESHOLD, \ 646 0xffff, \ 647 LDLAT) 648 649 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) 650 651 union perf_capabilities { 652 struct { 653 u64 lbr_format:6; 654 u64 pebs_trap:1; 655 u64 pebs_arch_reg:1; 656 u64 pebs_format:4; 657 u64 smm_freeze:1; 658 /* 659 * PMU supports separate counter range for writing 660 * values > 32bit. 661 */ 662 u64 full_width_write:1; 663 u64 pebs_baseline:1; 664 u64 perf_metrics:1; 665 u64 pebs_output_pt_available:1; 666 u64 pebs_timing_info:1; 667 u64 __reserved:1; 668 u64 rdpmc_metrics_clear:1; 669 }; 670 u64 capabilities; 671 }; 672 673 struct x86_pmu_quirk { 674 struct x86_pmu_quirk *next; 675 void (*func)(void); 676 }; 677 678 union x86_pmu_config { 679 struct { 680 u64 event:8, 681 umask:8, 682 usr:1, 683 os:1, 684 edge:1, 685 pc:1, 686 interrupt:1, 687 __reserved1:1, 688 en:1, 689 inv:1, 690 cmask:8, 691 event2:4, 692 __reserved2:4, 693 go:1, 694 ho:1; 695 } bits; 696 u64 value; 697 }; 698 699 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value 700 701 enum { 702 x86_lbr_exclusive_lbr, 703 x86_lbr_exclusive_bts, 704 x86_lbr_exclusive_pt, 705 x86_lbr_exclusive_max, 706 }; 707 708 #define PERF_PEBS_DATA_SOURCE_MAX 0x100 709 #define PERF_PEBS_DATA_SOURCE_MASK (PERF_PEBS_DATA_SOURCE_MAX - 1) 710 #define PERF_PEBS_DATA_SOURCE_GRT_MAX 0x10 711 #define PERF_PEBS_DATA_SOURCE_GRT_MASK (PERF_PEBS_DATA_SOURCE_GRT_MAX - 1) 712 713 #define X86_HYBRID_PMU_ATOM_IDX 0 714 #define X86_HYBRID_PMU_CORE_IDX 1 715 #define X86_HYBRID_PMU_TINY_IDX 2 716 717 enum hybrid_pmu_type { 718 not_hybrid, 719 hybrid_small = BIT(X86_HYBRID_PMU_ATOM_IDX), 720 hybrid_big = BIT(X86_HYBRID_PMU_CORE_IDX), 721 hybrid_tiny = BIT(X86_HYBRID_PMU_TINY_IDX), 722 723 /* The belows are only used for matching */ 724 hybrid_big_small = hybrid_big | hybrid_small, 725 hybrid_small_tiny = hybrid_small | hybrid_tiny, 726 hybrid_big_small_tiny = hybrid_big | hybrid_small_tiny, 727 }; 728 729 struct arch_pebs_cap { 730 u64 caps; 731 u64 counters; 732 u64 pdists; 733 }; 734 735 struct x86_hybrid_pmu { 736 struct pmu pmu; 737 const char *name; 738 enum hybrid_pmu_type pmu_type; 739 cpumask_t supported_cpus; 740 union perf_capabilities intel_cap; 741 u64 intel_ctrl; 742 u64 pebs_events_mask; 743 u64 config_mask; 744 union { 745 u64 cntr_mask64; 746 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 747 }; 748 union { 749 u64 fixed_cntr_mask64; 750 unsigned long fixed_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 751 }; 752 753 union { 754 u64 acr_cntr_mask64; 755 unsigned long acr_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 756 }; 757 union { 758 u64 acr_cause_mask64; 759 unsigned long acr_cause_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 760 }; 761 struct event_constraint unconstrained; 762 763 u64 hw_cache_event_ids 764 [PERF_COUNT_HW_CACHE_MAX] 765 [PERF_COUNT_HW_CACHE_OP_MAX] 766 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 767 u64 hw_cache_extra_regs 768 [PERF_COUNT_HW_CACHE_MAX] 769 [PERF_COUNT_HW_CACHE_OP_MAX] 770 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 771 struct event_constraint *event_constraints; 772 struct event_constraint *pebs_constraints; 773 struct extra_reg *extra_regs; 774 775 unsigned int late_ack :1, 776 mid_ack :1, 777 enabled_ack :1; 778 779 struct arch_pebs_cap arch_pebs_cap; 780 781 u64 pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX]; 782 }; 783 784 static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu) 785 { 786 return container_of(pmu, struct x86_hybrid_pmu, pmu); 787 } 788 789 extern struct static_key_false perf_is_hybrid; 790 #define is_hybrid() static_branch_unlikely(&perf_is_hybrid) 791 792 #define hybrid(_pmu, _field) \ 793 (*({ \ 794 typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \ 795 \ 796 if (is_hybrid() && (_pmu)) \ 797 __Fp = &hybrid_pmu(_pmu)->_field; \ 798 \ 799 __Fp; \ 800 })) 801 802 #define hybrid_var(_pmu, _var) \ 803 (*({ \ 804 typeof(&_var) __Fp = &_var; \ 805 \ 806 if (is_hybrid() && (_pmu)) \ 807 __Fp = &hybrid_pmu(_pmu)->_var; \ 808 \ 809 __Fp; \ 810 })) 811 812 #define hybrid_bit(_pmu, _field) \ 813 ({ \ 814 bool __Fp = x86_pmu._field; \ 815 \ 816 if (is_hybrid() && (_pmu)) \ 817 __Fp = hybrid_pmu(_pmu)->_field; \ 818 \ 819 __Fp; \ 820 }) 821 822 /* 823 * struct x86_pmu - generic x86 pmu 824 */ 825 struct x86_pmu { 826 /* 827 * Generic x86 PMC bits 828 */ 829 const char *name; 830 int version; 831 int (*handle_irq)(struct pt_regs *); 832 void (*disable_all)(void); 833 void (*enable_all)(int added); 834 void (*enable)(struct perf_event *); 835 void (*disable)(struct perf_event *); 836 void (*assign)(struct perf_event *event, int idx); 837 void (*add)(struct perf_event *); 838 void (*del)(struct perf_event *); 839 void (*read)(struct perf_event *event); 840 int (*set_period)(struct perf_event *event); 841 u64 (*update)(struct perf_event *event); 842 int (*hw_config)(struct perf_event *event); 843 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); 844 void (*late_setup)(void); 845 void (*pebs_enable)(struct perf_event *event); 846 void (*pebs_disable)(struct perf_event *event); 847 void (*pebs_enable_all)(void); 848 void (*pebs_disable_all)(void); 849 unsigned eventsel; 850 unsigned perfctr; 851 unsigned fixedctr; 852 int (*addr_offset)(int index, bool eventsel); 853 int (*rdpmc_index)(int index); 854 u64 (*event_map)(int); 855 int max_events; 856 u64 config_mask; 857 union { 858 u64 cntr_mask64; 859 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 860 }; 861 union { 862 u64 fixed_cntr_mask64; 863 unsigned long fixed_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 864 }; 865 union { 866 u64 acr_cntr_mask64; 867 unsigned long acr_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 868 }; 869 union { 870 u64 acr_cause_mask64; 871 unsigned long acr_cause_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 872 }; 873 int cntval_bits; 874 u64 cntval_mask; 875 union { 876 unsigned long events_maskl; 877 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)]; 878 }; 879 int events_mask_len; 880 int apic; 881 u64 max_period; 882 struct event_constraint * 883 (*get_event_constraints)(struct cpu_hw_events *cpuc, 884 int idx, 885 struct perf_event *event); 886 887 void (*put_event_constraints)(struct cpu_hw_events *cpuc, 888 struct perf_event *event); 889 890 void (*start_scheduling)(struct cpu_hw_events *cpuc); 891 892 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr); 893 894 void (*stop_scheduling)(struct cpu_hw_events *cpuc); 895 896 struct event_constraint *event_constraints; 897 struct x86_pmu_quirk *quirks; 898 void (*limit_period)(struct perf_event *event, s64 *l); 899 900 /* PMI handler bits */ 901 unsigned int late_ack :1, 902 mid_ack :1, 903 enabled_ack :1; 904 /* 905 * sysfs attrs 906 */ 907 int attr_rdpmc_broken; 908 int attr_rdpmc; 909 struct attribute **format_attrs; 910 911 ssize_t (*events_sysfs_show)(char *page, u64 config); 912 const struct attribute_group **attr_update; 913 914 unsigned long attr_freeze_on_smi; 915 916 /* 917 * CPU Hotplug hooks 918 */ 919 int (*cpu_prepare)(int cpu); 920 void (*cpu_starting)(int cpu); 921 void (*cpu_dying)(int cpu); 922 void (*cpu_dead)(int cpu); 923 924 void (*check_microcode)(void); 925 void (*sched_task)(struct perf_event_pmu_context *pmu_ctx, 926 struct task_struct *task, bool sched_in); 927 928 /* 929 * Intel Arch Perfmon v2+ 930 */ 931 u64 intel_ctrl; 932 union perf_capabilities intel_cap; 933 934 /* 935 * Intel DebugStore and PEBS bits 936 */ 937 unsigned int bts :1, 938 bts_active :1, 939 ds_pebs :1, 940 pebs_active :1, 941 pebs_broken :1, 942 pebs_prec_dist :1, 943 pebs_no_tlb :1, 944 pebs_no_isolation :1, 945 pebs_block :1, 946 pebs_ept :1, 947 arch_pebs :1; 948 int pebs_record_size; 949 int pebs_buffer_size; 950 u64 pebs_events_mask; 951 void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data); 952 struct event_constraint *pebs_constraints; 953 void (*pebs_aliases)(struct perf_event *event); 954 u64 (*pebs_latency_data)(struct perf_event *event, u64 status); 955 unsigned long large_pebs_flags; 956 u64 rtm_abort_event; 957 u64 pebs_capable; 958 959 /* 960 * Intel Architectural PEBS 961 */ 962 struct arch_pebs_cap arch_pebs_cap; 963 964 /* 965 * Intel LBR 966 */ 967 unsigned int lbr_tos, lbr_from, lbr_to, 968 lbr_info, lbr_nr; /* LBR base regs and size */ 969 union { 970 u64 lbr_sel_mask; /* LBR_SELECT valid bits */ 971 u64 lbr_ctl_mask; /* LBR_CTL valid bits */ 972 }; 973 union { 974 const int *lbr_sel_map; /* lbr_select mappings */ 975 int *lbr_ctl_map; /* LBR_CTL mappings */ 976 }; 977 u64 lbr_callstack_users; /* lbr callstack system wide users */ 978 bool lbr_double_abort; /* duplicated lbr aborts */ 979 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */ 980 981 unsigned int lbr_has_info:1; 982 unsigned int lbr_has_tsx:1; 983 unsigned int lbr_from_flags:1; 984 unsigned int lbr_to_cycles:1; 985 986 /* 987 * Intel Architectural LBR CPUID Enumeration 988 */ 989 unsigned int lbr_depth_mask:8; 990 unsigned int lbr_deep_c_reset:1; 991 unsigned int lbr_lip:1; 992 unsigned int lbr_cpl:1; 993 unsigned int lbr_filter:1; 994 unsigned int lbr_call_stack:1; 995 unsigned int lbr_mispred:1; 996 unsigned int lbr_timed_lbr:1; 997 unsigned int lbr_br_type:1; 998 unsigned int lbr_counters:4; 999 1000 void (*lbr_reset)(void); 1001 void (*lbr_read)(struct cpu_hw_events *cpuc); 1002 void (*lbr_save)(void *ctx); 1003 void (*lbr_restore)(void *ctx); 1004 1005 /* 1006 * Intel PT/LBR/BTS are exclusive 1007 */ 1008 atomic_t lbr_exclusive[x86_lbr_exclusive_max]; 1009 1010 /* 1011 * Intel perf metrics 1012 */ 1013 int num_topdown_events; 1014 1015 /* 1016 * AMD bits 1017 */ 1018 unsigned int amd_nb_constraints : 1; 1019 u64 perf_ctr_pair_en; 1020 1021 /* 1022 * Extra registers for events 1023 */ 1024 struct extra_reg *extra_regs; 1025 unsigned int flags; 1026 1027 /* 1028 * Intel host/guest support (KVM) 1029 */ 1030 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr, void *data); 1031 1032 /* 1033 * Check period value for PERF_EVENT_IOC_PERIOD ioctl. 1034 */ 1035 int (*check_period) (struct perf_event *event, u64 period); 1036 1037 int (*aux_output_match) (struct perf_event *event); 1038 1039 void (*filter)(struct pmu *pmu, int cpu, bool *ret); 1040 /* 1041 * Hybrid support 1042 * 1043 * Most PMU capabilities are the same among different hybrid PMUs. 1044 * The global x86_pmu saves the architecture capabilities, which 1045 * are available for all PMUs. The hybrid_pmu only includes the 1046 * unique capabilities. 1047 */ 1048 int num_hybrid_pmus; 1049 struct x86_hybrid_pmu *hybrid_pmu; 1050 enum intel_cpu_type (*get_hybrid_cpu_type) (void); 1051 }; 1052 1053 struct x86_perf_task_context_opt { 1054 int lbr_callstack_users; 1055 int lbr_stack_state; 1056 int log_id; 1057 }; 1058 1059 struct x86_perf_task_context { 1060 u64 lbr_sel; 1061 int tos; 1062 int valid_lbrs; 1063 struct x86_perf_task_context_opt opt; 1064 struct lbr_entry lbr[MAX_LBR_ENTRIES]; 1065 }; 1066 1067 struct x86_perf_task_context_arch_lbr { 1068 struct x86_perf_task_context_opt opt; 1069 struct lbr_entry entries[]; 1070 }; 1071 1072 /* 1073 * Add padding to guarantee the 64-byte alignment of the state buffer. 1074 * 1075 * The structure is dynamically allocated. The size of the LBR state may vary 1076 * based on the number of LBR registers. 1077 * 1078 * Do not put anything after the LBR state. 1079 */ 1080 struct x86_perf_task_context_arch_lbr_xsave { 1081 struct x86_perf_task_context_opt opt; 1082 1083 union { 1084 struct xregs_state xsave; 1085 struct { 1086 struct fxregs_state i387; 1087 struct xstate_header header; 1088 struct arch_lbr_state lbr; 1089 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT))); 1090 }; 1091 }; 1092 1093 #define x86_add_quirk(func_) \ 1094 do { \ 1095 static struct x86_pmu_quirk __quirk __initdata = { \ 1096 .func = func_, \ 1097 }; \ 1098 __quirk.next = x86_pmu.quirks; \ 1099 x86_pmu.quirks = &__quirk; \ 1100 } while (0) 1101 1102 /* 1103 * x86_pmu flags 1104 */ 1105 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */ 1106 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */ 1107 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */ 1108 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */ 1109 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */ 1110 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */ 1111 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */ 1112 #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */ 1113 #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */ 1114 #define PMU_FL_RETIRE_LATENCY 0x200 /* Support Retire Latency in PEBS */ 1115 #define PMU_FL_BR_CNTR 0x400 /* Support branch counter logging */ 1116 #define PMU_FL_DYN_CONSTRAINT 0x800 /* Needs dynamic constraint */ 1117 #define PMU_FL_HAS_OMR 0x1000 /* has 4 equivalent OMR regs */ 1118 1119 #define EVENT_VAR(_id) event_attr_##_id 1120 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr 1121 1122 #define EVENT_ATTR(_name, _id) \ 1123 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \ 1124 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 1125 .id = PERF_COUNT_HW_##_id, \ 1126 .event_str = NULL, \ 1127 }; 1128 1129 #define EVENT_ATTR_STR(_name, v, str) \ 1130 static struct perf_pmu_events_attr event_attr_##v = { \ 1131 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \ 1132 .id = 0, \ 1133 .event_str = str, \ 1134 }; 1135 1136 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \ 1137 static struct perf_pmu_events_ht_attr event_attr_##v = { \ 1138 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\ 1139 .id = 0, \ 1140 .event_str_noht = noht, \ 1141 .event_str_ht = ht, \ 1142 } 1143 1144 #define EVENT_ATTR_STR_HYBRID(_name, v, str, _pmu) \ 1145 static struct perf_pmu_events_hybrid_attr event_attr_##v = { \ 1146 .attr = __ATTR(_name, 0444, events_hybrid_sysfs_show, NULL),\ 1147 .id = 0, \ 1148 .event_str = str, \ 1149 .pmu_type = _pmu, \ 1150 } 1151 1152 #define FORMAT_HYBRID_PTR(_id) (&format_attr_hybrid_##_id.attr.attr) 1153 1154 #define FORMAT_ATTR_HYBRID(_name, _pmu) \ 1155 static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\ 1156 .attr = __ATTR_RO(_name), \ 1157 .pmu_type = _pmu, \ 1158 } 1159 1160 struct pmu *x86_get_static_pmu(void); 1161 struct pmu *x86_get_pmu(unsigned int cpu); 1162 extern struct x86_pmu x86_pmu __read_mostly; 1163 1164 DECLARE_STATIC_CALL(x86_pmu_set_period, *x86_pmu.set_period); 1165 DECLARE_STATIC_CALL(x86_pmu_update, *x86_pmu.update); 1166 DECLARE_STATIC_CALL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs); 1167 DECLARE_STATIC_CALL(x86_pmu_late_setup, *x86_pmu.late_setup); 1168 DECLARE_STATIC_CALL(x86_pmu_pebs_enable, *x86_pmu.pebs_enable); 1169 DECLARE_STATIC_CALL(x86_pmu_pebs_disable, *x86_pmu.pebs_disable); 1170 DECLARE_STATIC_CALL(x86_pmu_pebs_enable_all, *x86_pmu.pebs_enable_all); 1171 DECLARE_STATIC_CALL(x86_pmu_pebs_disable_all, *x86_pmu.pebs_disable_all); 1172 1173 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx) 1174 { 1175 if (cpu_feature_enabled(X86_FEATURE_ARCH_LBR)) 1176 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt; 1177 1178 return &((struct x86_perf_task_context *)ctx)->opt; 1179 } 1180 1181 static inline bool x86_pmu_has_lbr_callstack(void) 1182 { 1183 return x86_pmu.lbr_sel_map && 1184 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; 1185 } 1186 1187 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 1188 DECLARE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); 1189 1190 int x86_perf_event_set_period(struct perf_event *event); 1191 1192 /* 1193 * Generalized hw caching related hw_event table, filled 1194 * in on a per model basis. A value of 0 means 1195 * 'not supported', -1 means 'hw_event makes no sense on 1196 * this CPU', any other value means the raw hw_event 1197 * ID. 1198 */ 1199 1200 #define C(x) PERF_COUNT_HW_CACHE_##x 1201 1202 extern u64 __read_mostly hw_cache_event_ids 1203 [PERF_COUNT_HW_CACHE_MAX] 1204 [PERF_COUNT_HW_CACHE_OP_MAX] 1205 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 1206 extern u64 __read_mostly hw_cache_extra_regs 1207 [PERF_COUNT_HW_CACHE_MAX] 1208 [PERF_COUNT_HW_CACHE_OP_MAX] 1209 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 1210 1211 u64 x86_perf_event_update(struct perf_event *event); 1212 1213 static inline u64 intel_pmu_topdown_event_update(struct perf_event *event, u64 *val) 1214 { 1215 return x86_perf_event_update(event); 1216 } 1217 DECLARE_STATIC_CALL(intel_pmu_update_topdown_event, intel_pmu_topdown_event_update); 1218 1219 static inline unsigned int x86_pmu_config_addr(int index) 1220 { 1221 return x86_pmu.eventsel + (x86_pmu.addr_offset ? 1222 x86_pmu.addr_offset(index, true) : index); 1223 } 1224 1225 static inline unsigned int x86_pmu_event_addr(int index) 1226 { 1227 return x86_pmu.perfctr + (x86_pmu.addr_offset ? 1228 x86_pmu.addr_offset(index, false) : index); 1229 } 1230 1231 static inline unsigned int x86_pmu_fixed_ctr_addr(int index) 1232 { 1233 return x86_pmu.fixedctr + (x86_pmu.addr_offset ? 1234 x86_pmu.addr_offset(index, false) : index); 1235 } 1236 1237 static inline int x86_pmu_rdpmc_index(int index) 1238 { 1239 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; 1240 } 1241 1242 bool check_hw_exists(unsigned long *cntr_mask, 1243 unsigned long *fixed_cntr_mask); 1244 1245 int x86_add_exclusive(unsigned int what); 1246 1247 void x86_del_exclusive(unsigned int what); 1248 1249 int x86_reserve_hardware(void); 1250 1251 void x86_release_hardware(void); 1252 1253 int x86_pmu_max_precise(struct pmu *pmu); 1254 1255 void hw_perf_lbr_event_destroy(struct perf_event *event); 1256 1257 int x86_setup_perfctr(struct perf_event *event); 1258 1259 int x86_pmu_hw_config(struct perf_event *event); 1260 1261 void x86_pmu_disable_all(void); 1262 1263 static inline bool has_amd_brs(struct hw_perf_event *hwc) 1264 { 1265 return hwc->flags & PERF_X86_EVENT_AMD_BRS; 1266 } 1267 1268 static inline bool is_counter_pair(struct hw_perf_event *hwc) 1269 { 1270 return hwc->flags & PERF_X86_EVENT_PAIR; 1271 } 1272 1273 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, 1274 u64 enable_mask) 1275 { 1276 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1277 1278 if (hwc->extra_reg.reg) 1279 wrmsrq(hwc->extra_reg.reg, hwc->extra_reg.config); 1280 1281 /* 1282 * Add enabled Merge event on next counter 1283 * if large increment event being enabled on this counter 1284 */ 1285 if (is_counter_pair(hwc)) 1286 wrmsrq(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); 1287 1288 wrmsrq(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); 1289 } 1290 1291 void x86_pmu_enable_all(int added); 1292 1293 int perf_assign_events(struct event_constraint **constraints, int n, 1294 int wmin, int wmax, int gpmax, int *assign); 1295 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); 1296 1297 void x86_pmu_stop(struct perf_event *event, int flags); 1298 1299 static inline void x86_pmu_disable_event(struct perf_event *event) 1300 { 1301 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1302 struct hw_perf_event *hwc = &event->hw; 1303 1304 wrmsrq(hwc->config_base, hwc->config & ~disable_mask); 1305 1306 if (is_counter_pair(hwc)) 1307 wrmsrq(x86_pmu_config_addr(hwc->idx + 1), 0); 1308 } 1309 1310 void x86_pmu_enable_event(struct perf_event *event); 1311 1312 int x86_pmu_handle_irq(struct pt_regs *regs); 1313 1314 void x86_pmu_show_pmu_cap(struct pmu *pmu); 1315 1316 static inline int x86_pmu_num_counters(struct pmu *pmu) 1317 { 1318 return hweight64(hybrid(pmu, cntr_mask64)); 1319 } 1320 1321 static inline int x86_pmu_max_num_counters(struct pmu *pmu) 1322 { 1323 return fls64(hybrid(pmu, cntr_mask64)); 1324 } 1325 1326 static inline int x86_pmu_num_counters_fixed(struct pmu *pmu) 1327 { 1328 return hweight64(hybrid(pmu, fixed_cntr_mask64)); 1329 } 1330 1331 static inline int x86_pmu_max_num_counters_fixed(struct pmu *pmu) 1332 { 1333 return fls64(hybrid(pmu, fixed_cntr_mask64)); 1334 } 1335 1336 static inline u64 x86_pmu_get_event_config(struct perf_event *event) 1337 { 1338 return event->attr.config & hybrid(event->pmu, config_mask); 1339 } 1340 1341 static inline bool x86_pmu_has_rdpmc_user_disable(struct pmu *pmu) 1342 { 1343 return !!(hybrid(pmu, config_mask) & 1344 ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE); 1345 } 1346 1347 extern struct event_constraint emptyconstraint; 1348 1349 extern struct event_constraint unconstrained; 1350 1351 static inline bool kernel_ip(unsigned long ip) 1352 { 1353 #ifdef CONFIG_X86_32 1354 return ip > PAGE_OFFSET; 1355 #else 1356 return (long)ip < 0; 1357 #endif 1358 } 1359 1360 /* 1361 * Not all PMUs provide the right context information to place the reported IP 1362 * into full context. Specifically segment registers are typically not 1363 * supplied. 1364 * 1365 * Assuming the address is a linear address (it is for IBS), we fake the CS and 1366 * vm86 mode using the known zero-based code segment and 'fix up' the registers 1367 * to reflect this. 1368 * 1369 * Intel PEBS/LBR appear to typically provide the effective address, nothing 1370 * much we can do about that but pray and treat it like a linear address. 1371 */ 1372 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) 1373 { 1374 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; 1375 if (regs->flags & X86_VM_MASK) 1376 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); 1377 regs->ip = ip; 1378 } 1379 1380 /* 1381 * x86control flow change classification 1382 * x86control flow changes include branches, interrupts, traps, faults 1383 */ 1384 enum { 1385 X86_BR_NONE = 0, /* unknown */ 1386 1387 X86_BR_USER = 1 << 0, /* branch target is user */ 1388 X86_BR_KERNEL = 1 << 1, /* branch target is kernel */ 1389 1390 X86_BR_CALL = 1 << 2, /* call */ 1391 X86_BR_RET = 1 << 3, /* return */ 1392 X86_BR_SYSCALL = 1 << 4, /* syscall */ 1393 X86_BR_SYSRET = 1 << 5, /* syscall return */ 1394 X86_BR_INT = 1 << 6, /* sw interrupt */ 1395 X86_BR_IRET = 1 << 7, /* return from interrupt */ 1396 X86_BR_JCC = 1 << 8, /* conditional */ 1397 X86_BR_JMP = 1 << 9, /* jump */ 1398 X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */ 1399 X86_BR_IND_CALL = 1 << 11,/* indirect calls */ 1400 X86_BR_ABORT = 1 << 12,/* transaction abort */ 1401 X86_BR_IN_TX = 1 << 13,/* in transaction */ 1402 X86_BR_NO_TX = 1 << 14,/* not in transaction */ 1403 X86_BR_ZERO_CALL = 1 << 15,/* zero length call */ 1404 X86_BR_CALL_STACK = 1 << 16,/* call stack */ 1405 X86_BR_IND_JMP = 1 << 17,/* indirect jump */ 1406 1407 X86_BR_TYPE_SAVE = 1 << 18,/* indicate to save branch type */ 1408 1409 }; 1410 1411 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL) 1412 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX) 1413 1414 #define X86_BR_ANY \ 1415 (X86_BR_CALL |\ 1416 X86_BR_RET |\ 1417 X86_BR_SYSCALL |\ 1418 X86_BR_SYSRET |\ 1419 X86_BR_INT |\ 1420 X86_BR_IRET |\ 1421 X86_BR_JCC |\ 1422 X86_BR_JMP |\ 1423 X86_BR_IRQ |\ 1424 X86_BR_ABORT |\ 1425 X86_BR_IND_CALL |\ 1426 X86_BR_IND_JMP |\ 1427 X86_BR_ZERO_CALL) 1428 1429 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY) 1430 1431 #define X86_BR_ANY_CALL \ 1432 (X86_BR_CALL |\ 1433 X86_BR_IND_CALL |\ 1434 X86_BR_ZERO_CALL |\ 1435 X86_BR_SYSCALL |\ 1436 X86_BR_IRQ |\ 1437 X86_BR_INT) 1438 1439 int common_branch_type(int type); 1440 int branch_type(unsigned long from, unsigned long to, int abort); 1441 int branch_type_fused(unsigned long from, unsigned long to, int abort, 1442 int *offset); 1443 1444 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event); 1445 ssize_t intel_event_sysfs_show(char *page, u64 config); 1446 1447 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, 1448 char *page); 1449 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, 1450 char *page); 1451 ssize_t events_hybrid_sysfs_show(struct device *dev, 1452 struct device_attribute *attr, 1453 char *page); 1454 1455 #ifdef CONFIG_CPU_SUP_AMD 1456 1457 int amd_pmu_init(void); 1458 1459 int amd_pmu_lbr_init(void); 1460 void amd_pmu_lbr_reset(void); 1461 void amd_pmu_lbr_read(void); 1462 void amd_pmu_lbr_add(struct perf_event *event); 1463 void amd_pmu_lbr_del(struct perf_event *event); 1464 void amd_pmu_lbr_sched_task(struct perf_event_pmu_context *pmu_ctx, 1465 struct task_struct *task, bool sched_in); 1466 void amd_pmu_lbr_enable_all(void); 1467 void amd_pmu_lbr_disable_all(void); 1468 int amd_pmu_lbr_hw_config(struct perf_event *event); 1469 1470 static __always_inline void __amd_pmu_lbr_disable(void) 1471 { 1472 u64 dbg_ctl, dbg_extn_cfg; 1473 1474 rdmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg); 1475 wrmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN); 1476 1477 if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) { 1478 rdmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl); 1479 wrmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 1480 } 1481 } 1482 1483 #ifdef CONFIG_PERF_EVENTS_AMD_BRS 1484 1485 #define AMD_FAM19H_BRS_EVENT 0xc4 /* RETIRED_TAKEN_BRANCH_INSTRUCTIONS */ 1486 1487 int amd_brs_init(void); 1488 void amd_brs_disable(void); 1489 void amd_brs_enable(void); 1490 void amd_brs_enable_all(void); 1491 void amd_brs_disable_all(void); 1492 void amd_brs_drain(void); 1493 void amd_brs_lopwr_init(void); 1494 int amd_brs_hw_config(struct perf_event *event); 1495 void amd_brs_reset(void); 1496 1497 static inline void amd_pmu_brs_add(struct perf_event *event) 1498 { 1499 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1500 1501 perf_sched_cb_inc(event->pmu); 1502 cpuc->lbr_users++; 1503 /* 1504 * No need to reset BRS because it is reset 1505 * on brs_enable() and it is saturating 1506 */ 1507 } 1508 1509 static inline void amd_pmu_brs_del(struct perf_event *event) 1510 { 1511 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1512 1513 cpuc->lbr_users--; 1514 WARN_ON_ONCE(cpuc->lbr_users < 0); 1515 1516 perf_sched_cb_dec(event->pmu); 1517 } 1518 1519 void amd_pmu_brs_sched_task(struct perf_event_pmu_context *pmu_ctx, 1520 struct task_struct *task, bool sched_in); 1521 #else 1522 static inline int amd_brs_init(void) 1523 { 1524 return 0; 1525 } 1526 static inline void amd_brs_disable(void) {} 1527 static inline void amd_brs_enable(void) {} 1528 static inline void amd_brs_drain(void) {} 1529 static inline void amd_brs_lopwr_init(void) {} 1530 static inline void amd_brs_disable_all(void) {} 1531 static inline int amd_brs_hw_config(struct perf_event *event) 1532 { 1533 return 0; 1534 } 1535 static inline void amd_brs_reset(void) {} 1536 1537 static inline void amd_pmu_brs_add(struct perf_event *event) 1538 { 1539 } 1540 1541 static inline void amd_pmu_brs_del(struct perf_event *event) 1542 { 1543 } 1544 1545 static inline void amd_pmu_brs_sched_task(struct perf_event_pmu_context *pmu_ctx, 1546 struct task_struct *task, bool sched_in) 1547 { 1548 } 1549 1550 static inline void amd_brs_enable_all(void) 1551 { 1552 } 1553 1554 #endif 1555 1556 #else /* CONFIG_CPU_SUP_AMD */ 1557 1558 static inline int amd_pmu_init(void) 1559 { 1560 return 0; 1561 } 1562 1563 static inline int amd_brs_init(void) 1564 { 1565 return -EOPNOTSUPP; 1566 } 1567 1568 static inline void amd_brs_drain(void) 1569 { 1570 } 1571 1572 static inline void amd_brs_enable_all(void) 1573 { 1574 } 1575 1576 static inline void amd_brs_disable_all(void) 1577 { 1578 } 1579 #endif /* CONFIG_CPU_SUP_AMD */ 1580 1581 static inline int is_pebs_pt(struct perf_event *event) 1582 { 1583 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT); 1584 } 1585 1586 #ifdef CONFIG_CPU_SUP_INTEL 1587 1588 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period) 1589 { 1590 struct hw_perf_event *hwc = &event->hw; 1591 unsigned int hw_event, bts_event; 1592 1593 /* 1594 * Only use BTS for fixed rate period==1 events. 1595 */ 1596 if (event->attr.freq || period != 1) 1597 return false; 1598 1599 /* 1600 * BTS doesn't virtualize. 1601 */ 1602 if (event->attr.exclude_host) 1603 return false; 1604 1605 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; 1606 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 1607 1608 return hw_event == bts_event; 1609 } 1610 1611 static inline bool intel_pmu_has_bts(struct perf_event *event) 1612 { 1613 struct hw_perf_event *hwc = &event->hw; 1614 1615 return intel_pmu_has_bts_period(event, hwc->sample_period); 1616 } 1617 1618 static __always_inline void __intel_pmu_pebs_disable_all(void) 1619 { 1620 wrmsrq(MSR_IA32_PEBS_ENABLE, 0); 1621 } 1622 1623 static __always_inline void __intel_pmu_arch_lbr_disable(void) 1624 { 1625 wrmsrq(MSR_ARCH_LBR_CTL, 0); 1626 } 1627 1628 static __always_inline void __intel_pmu_lbr_disable(void) 1629 { 1630 u64 debugctl; 1631 1632 rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 1633 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 1634 wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 1635 } 1636 1637 extern int __intel_pmu_quiesce(void); 1638 extern void __intel_pmu_resume(int pmu_enabled); 1639 1640 int intel_pmu_save_and_restart(struct perf_event *event); 1641 1642 struct event_constraint * 1643 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 1644 struct perf_event *event); 1645 1646 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu); 1647 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc); 1648 1649 int intel_pmu_init(void); 1650 1651 int alloc_arch_pebs_buf_on_cpu(int cpu); 1652 1653 void release_arch_pebs_buf_on_cpu(int cpu); 1654 1655 void init_arch_pebs_on_cpu(int cpu); 1656 1657 void fini_arch_pebs_on_cpu(int cpu); 1658 1659 void init_debug_store_on_cpu(int cpu); 1660 1661 void fini_debug_store_on_cpu(int cpu); 1662 1663 void release_ds_buffers(void); 1664 1665 void reserve_ds_buffers(void); 1666 1667 void release_lbr_buffers(void); 1668 1669 void reserve_lbr_buffers(void); 1670 1671 extern struct event_constraint bts_constraint; 1672 extern struct event_constraint vlbr_constraint; 1673 1674 void intel_pmu_enable_bts(u64 config); 1675 1676 void intel_pmu_disable_bts(void); 1677 1678 int intel_pmu_drain_bts_buffer(void); 1679 1680 void intel_pmu_late_setup(void); 1681 1682 u64 grt_latency_data(struct perf_event *event, u64 status); 1683 1684 u64 cmt_latency_data(struct perf_event *event, u64 status); 1685 1686 u64 lnl_latency_data(struct perf_event *event, u64 status); 1687 1688 u64 arl_h_latency_data(struct perf_event *event, u64 status); 1689 1690 u64 pnc_latency_data(struct perf_event *event, u64 status); 1691 1692 u64 nvl_latency_data(struct perf_event *event, u64 status); 1693 1694 extern struct event_constraint intel_core2_pebs_event_constraints[]; 1695 1696 extern struct event_constraint intel_atom_pebs_event_constraints[]; 1697 1698 extern struct event_constraint intel_slm_pebs_event_constraints[]; 1699 1700 extern struct event_constraint intel_glm_pebs_event_constraints[]; 1701 1702 extern struct event_constraint intel_glp_pebs_event_constraints[]; 1703 1704 extern struct event_constraint intel_grt_pebs_event_constraints[]; 1705 1706 extern struct event_constraint intel_cmt_pebs_event_constraints[]; 1707 1708 extern struct event_constraint intel_dkt_pebs_event_constraints[]; 1709 1710 extern struct event_constraint intel_nehalem_pebs_event_constraints[]; 1711 1712 extern struct event_constraint intel_westmere_pebs_event_constraints[]; 1713 1714 extern struct event_constraint intel_snb_pebs_event_constraints[]; 1715 1716 extern struct event_constraint intel_ivb_pebs_event_constraints[]; 1717 1718 extern struct event_constraint intel_hsw_pebs_event_constraints[]; 1719 1720 extern struct event_constraint intel_bdw_pebs_event_constraints[]; 1721 1722 extern struct event_constraint intel_skl_pebs_event_constraints[]; 1723 1724 extern struct event_constraint intel_icl_pebs_event_constraints[]; 1725 1726 extern struct event_constraint intel_glc_pebs_event_constraints[]; 1727 1728 extern struct event_constraint intel_lnc_pebs_event_constraints[]; 1729 1730 extern struct event_constraint intel_pnc_pebs_event_constraints[]; 1731 1732 struct event_constraint *intel_pebs_constraints(struct perf_event *event); 1733 1734 void intel_pmu_pebs_add(struct perf_event *event); 1735 1736 void intel_pmu_pebs_del(struct perf_event *event); 1737 1738 void intel_pmu_pebs_enable(struct perf_event *event); 1739 1740 void intel_pmu_pebs_disable(struct perf_event *event); 1741 1742 void intel_pmu_pebs_enable_all(void); 1743 1744 void intel_pmu_pebs_disable_all(void); 1745 1746 void intel_pmu_pebs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in); 1747 1748 void intel_pmu_pebs_late_setup(struct cpu_hw_events *cpuc); 1749 1750 void intel_pmu_drain_pebs_buffer(void); 1751 1752 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr); 1753 1754 void intel_pebs_init(void); 1755 1756 void intel_pmu_lbr_save_brstack(struct perf_sample_data *data, 1757 struct cpu_hw_events *cpuc, 1758 struct perf_event *event); 1759 1760 void intel_pmu_lbr_sched_task(struct perf_event_pmu_context *pmu_ctx, 1761 struct task_struct *task, bool sched_in); 1762 1763 u64 lbr_from_signext_quirk_wr(u64 val); 1764 1765 void intel_pmu_lbr_reset(void); 1766 1767 void intel_pmu_lbr_reset_32(void); 1768 1769 void intel_pmu_lbr_reset_64(void); 1770 1771 void intel_pmu_lbr_add(struct perf_event *event); 1772 1773 void intel_pmu_lbr_del(struct perf_event *event); 1774 1775 void intel_pmu_lbr_enable_all(bool pmi); 1776 1777 void intel_pmu_lbr_disable_all(void); 1778 1779 void intel_pmu_lbr_read(void); 1780 1781 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc); 1782 1783 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc); 1784 1785 void intel_pmu_lbr_save(void *ctx); 1786 1787 void intel_pmu_lbr_restore(void *ctx); 1788 1789 void intel_pmu_lbr_init_core(void); 1790 1791 void intel_pmu_lbr_init_nhm(void); 1792 1793 void intel_pmu_lbr_init_atom(void); 1794 1795 void intel_pmu_lbr_init_slm(void); 1796 1797 void intel_pmu_lbr_init_snb(void); 1798 1799 void intel_pmu_lbr_init_hsw(void); 1800 1801 void intel_pmu_lbr_init_skl(void); 1802 1803 void intel_pmu_lbr_init_knl(void); 1804 1805 void intel_pmu_lbr_init(void); 1806 1807 void intel_pmu_arch_lbr_init(void); 1808 1809 void intel_pmu_pebs_data_source_nhm(void); 1810 1811 void intel_pmu_pebs_data_source_skl(bool pmem); 1812 1813 void intel_pmu_pebs_data_source_adl(void); 1814 1815 void intel_pmu_pebs_data_source_grt(void); 1816 1817 void intel_pmu_pebs_data_source_mtl(void); 1818 1819 void intel_pmu_pebs_data_source_arl_h(void); 1820 1821 void intel_pmu_pebs_data_source_cmt(void); 1822 1823 void intel_pmu_pebs_data_source_lnl(void); 1824 1825 u64 intel_get_arch_pebs_data_config(struct perf_event *event); 1826 1827 int intel_pmu_setup_lbr_filter(struct perf_event *event); 1828 1829 void intel_pt_interrupt(void); 1830 1831 int intel_bts_interrupt(void); 1832 1833 void intel_bts_enable_local(void); 1834 1835 void intel_bts_disable_local(void); 1836 1837 int p4_pmu_init(void); 1838 1839 int p6_pmu_init(void); 1840 1841 int knc_pmu_init(void); 1842 1843 static inline int is_ht_workaround_enabled(void) 1844 { 1845 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); 1846 } 1847 1848 static inline u64 intel_pmu_pebs_mask(u64 cntr_mask) 1849 { 1850 return MAX_PEBS_EVENTS_MASK & cntr_mask; 1851 } 1852 1853 static inline int intel_pmu_max_num_pebs(struct pmu *pmu) 1854 { 1855 static_assert(MAX_PEBS_EVENTS == 32); 1856 return fls((u32)hybrid(pmu, pebs_events_mask)); 1857 } 1858 1859 static inline bool intel_pmu_has_pebs(void) 1860 { 1861 return x86_pmu.ds_pebs || x86_pmu.arch_pebs; 1862 } 1863 1864 #else /* CONFIG_CPU_SUP_INTEL */ 1865 1866 static inline void reserve_ds_buffers(void) 1867 { 1868 } 1869 1870 static inline void release_ds_buffers(void) 1871 { 1872 } 1873 1874 static inline void release_lbr_buffers(void) 1875 { 1876 } 1877 1878 static inline void reserve_lbr_buffers(void) 1879 { 1880 } 1881 1882 static inline int intel_pmu_init(void) 1883 { 1884 return 0; 1885 } 1886 1887 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 1888 { 1889 return 0; 1890 } 1891 1892 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc) 1893 { 1894 } 1895 1896 static inline int is_ht_workaround_enabled(void) 1897 { 1898 return 0; 1899 } 1900 #endif /* CONFIG_CPU_SUP_INTEL */ 1901 1902 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN)) 1903 int zhaoxin_pmu_init(void); 1904 #else 1905 static inline int zhaoxin_pmu_init(void) 1906 { 1907 return 0; 1908 } 1909 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/ 1910