1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-sc7280.h> 11#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 13#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 14#include <dt-bindings/clock/qcom,rpmh.h> 15#include <dt-bindings/clock/qcom,videocc-sc7280.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/firmware/qcom,scm.h> 18#include <dt-bindings/gpio/gpio.h> 19#include <dt-bindings/interconnect/qcom,icc.h> 20#include <dt-bindings/interconnect/qcom,osm-l3.h> 21#include <dt-bindings/interconnect/qcom,sc7280.h> 22#include <dt-bindings/interrupt-controller/arm-gic.h> 23#include <dt-bindings/mailbox/qcom-ipcc.h> 24#include <dt-bindings/phy/phy-qcom-qmp.h> 25#include <dt-bindings/power/qcom-rpmpd.h> 26#include <dt-bindings/reset/qcom,sdm845-aoss.h> 27#include <dt-bindings/reset/qcom,sdm845-pdc.h> 28#include <dt-bindings/soc/qcom,apr.h> 29#include <dt-bindings/soc/qcom,rpmh-rsc.h> 30#include <dt-bindings/sound/qcom,lpass.h> 31#include <dt-bindings/sound/qcom,q6asm.h> 32#include <dt-bindings/thermal/thermal.h> 33 34/ { 35 interrupt-parent = <&intc>; 36 37 #address-cells = <2>; 38 #size-cells = <2>; 39 40 chosen { }; 41 42 aliases { 43 i2c0 = &i2c0; 44 i2c1 = &i2c1; 45 i2c2 = &i2c2; 46 i2c3 = &i2c3; 47 i2c4 = &i2c4; 48 i2c5 = &i2c5; 49 i2c6 = &i2c6; 50 i2c7 = &i2c7; 51 i2c8 = &i2c8; 52 i2c9 = &i2c9; 53 i2c10 = &i2c10; 54 i2c11 = &i2c11; 55 i2c12 = &i2c12; 56 i2c13 = &i2c13; 57 i2c14 = &i2c14; 58 i2c15 = &i2c15; 59 mmc1 = &sdhc_1; 60 mmc2 = &sdhc_2; 61 spi0 = &spi0; 62 spi1 = &spi1; 63 spi2 = &spi2; 64 spi3 = &spi3; 65 spi4 = &spi4; 66 spi5 = &spi5; 67 spi6 = &spi6; 68 spi7 = &spi7; 69 spi8 = &spi8; 70 spi9 = &spi9; 71 spi10 = &spi10; 72 spi11 = &spi11; 73 spi12 = &spi12; 74 spi13 = &spi13; 75 spi14 = &spi14; 76 spi15 = &spi15; 77 }; 78 79 clocks { 80 xo_board: xo-board { 81 compatible = "fixed-clock"; 82 clock-frequency = <76800000>; 83 #clock-cells = <0>; 84 }; 85 86 sleep_clk: sleep-clk { 87 compatible = "fixed-clock"; 88 clock-frequency = <32764>; 89 #clock-cells = <0>; 90 }; 91 }; 92 93 reserved-memory { 94 #address-cells = <2>; 95 #size-cells = <2>; 96 ranges; 97 98 wlan_ce_mem: wlan-ce@4cd000 { 99 no-map; 100 reg = <0x0 0x004cd000 0x0 0x1000>; 101 }; 102 103 hyp_mem: hyp@80000000 { 104 reg = <0x0 0x80000000 0x0 0x600000>; 105 no-map; 106 }; 107 108 xbl_mem: xbl@80600000 { 109 reg = <0x0 0x80600000 0x0 0x200000>; 110 no-map; 111 }; 112 113 aop_mem: aop@80800000 { 114 reg = <0x0 0x80800000 0x0 0x60000>; 115 no-map; 116 }; 117 118 aop_cmd_db_mem: aop-cmd-db@80860000 { 119 reg = <0x0 0x80860000 0x0 0x20000>; 120 compatible = "qcom,cmd-db"; 121 no-map; 122 }; 123 124 reserved_xbl_uefi_log: xbl-uefi-res@80880000 { 125 reg = <0x0 0x80884000 0x0 0x10000>; 126 no-map; 127 }; 128 129 sec_apps_mem: sec-apps@808ff000 { 130 reg = <0x0 0x808ff000 0x0 0x1000>; 131 no-map; 132 }; 133 134 smem_mem: smem@80900000 { 135 reg = <0x0 0x80900000 0x0 0x200000>; 136 no-map; 137 }; 138 139 cpucp_mem: cpucp@80b00000 { 140 no-map; 141 reg = <0x0 0x80b00000 0x0 0x100000>; 142 }; 143 144 wlan_fw_mem: wlan-fw@80c00000 { 145 reg = <0x0 0x80c00000 0x0 0xc00000>; 146 no-map; 147 }; 148 149 adsp_mem: adsp@86700000 { 150 reg = <0x0 0x86700000 0x0 0x2800000>; 151 no-map; 152 }; 153 154 video_mem: video@8b200000 { 155 reg = <0x0 0x8b200000 0x0 0x500000>; 156 no-map; 157 }; 158 159 cdsp_mem: cdsp@88f00000 { 160 reg = <0x0 0x88f00000 0x0 0x1e00000>; 161 no-map; 162 }; 163 164 ipa_fw_mem: ipa-fw@8b700000 { 165 reg = <0 0x8b700000 0 0x10000>; 166 no-map; 167 }; 168 169 gpu_zap_mem: zap@8b71a000 { 170 reg = <0 0x8b71a000 0 0x2000>; 171 no-map; 172 }; 173 174 mpss_mem: mpss@8b800000 { 175 reg = <0x0 0x8b800000 0x0 0xf600000>; 176 no-map; 177 }; 178 179 wpss_mem: wpss@9ae00000 { 180 reg = <0x0 0x9ae00000 0x0 0x1900000>; 181 no-map; 182 }; 183 184 rmtfs_mem: rmtfs@9c900000 { 185 compatible = "qcom,rmtfs-mem"; 186 reg = <0x0 0x9c900000 0x0 0x280000>; 187 no-map; 188 189 qcom,client-id = <1>; 190 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 191 }; 192 }; 193 194 cpus { 195 #address-cells = <2>; 196 #size-cells = <0>; 197 198 cpu0: cpu@0 { 199 device_type = "cpu"; 200 compatible = "qcom,kryo"; 201 reg = <0x0 0x0>; 202 clocks = <&cpufreq_hw 0>; 203 enable-method = "psci"; 204 power-domains = <&cpu_pd0>; 205 power-domain-names = "psci"; 206 next-level-cache = <&l2_0>; 207 operating-points-v2 = <&cpu0_opp_table>; 208 capacity-dmips-mhz = <1024>; 209 dynamic-power-coefficient = <100>; 210 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 211 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 212 qcom,freq-domain = <&cpufreq_hw 0>; 213 #cooling-cells = <2>; 214 l2_0: l2-cache { 215 compatible = "cache"; 216 cache-level = <2>; 217 cache-unified; 218 next-level-cache = <&l3_0>; 219 l3_0: l3-cache { 220 compatible = "cache"; 221 cache-level = <3>; 222 cache-unified; 223 }; 224 }; 225 }; 226 227 cpu1: cpu@100 { 228 device_type = "cpu"; 229 compatible = "qcom,kryo"; 230 reg = <0x0 0x100>; 231 clocks = <&cpufreq_hw 0>; 232 enable-method = "psci"; 233 power-domains = <&cpu_pd1>; 234 power-domain-names = "psci"; 235 next-level-cache = <&l2_100>; 236 operating-points-v2 = <&cpu0_opp_table>; 237 capacity-dmips-mhz = <1024>; 238 dynamic-power-coefficient = <100>; 239 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 240 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 241 qcom,freq-domain = <&cpufreq_hw 0>; 242 #cooling-cells = <2>; 243 l2_100: l2-cache { 244 compatible = "cache"; 245 cache-level = <2>; 246 cache-unified; 247 next-level-cache = <&l3_0>; 248 }; 249 }; 250 251 cpu2: cpu@200 { 252 device_type = "cpu"; 253 compatible = "qcom,kryo"; 254 reg = <0x0 0x200>; 255 clocks = <&cpufreq_hw 0>; 256 enable-method = "psci"; 257 power-domains = <&cpu_pd2>; 258 power-domain-names = "psci"; 259 next-level-cache = <&l2_200>; 260 operating-points-v2 = <&cpu0_opp_table>; 261 capacity-dmips-mhz = <1024>; 262 dynamic-power-coefficient = <100>; 263 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 264 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 265 qcom,freq-domain = <&cpufreq_hw 0>; 266 #cooling-cells = <2>; 267 l2_200: l2-cache { 268 compatible = "cache"; 269 cache-level = <2>; 270 cache-unified; 271 next-level-cache = <&l3_0>; 272 }; 273 }; 274 275 cpu3: cpu@300 { 276 device_type = "cpu"; 277 compatible = "qcom,kryo"; 278 reg = <0x0 0x300>; 279 clocks = <&cpufreq_hw 0>; 280 enable-method = "psci"; 281 power-domains = <&cpu_pd3>; 282 power-domain-names = "psci"; 283 next-level-cache = <&l2_300>; 284 operating-points-v2 = <&cpu0_opp_table>; 285 capacity-dmips-mhz = <1024>; 286 dynamic-power-coefficient = <100>; 287 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 288 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 289 qcom,freq-domain = <&cpufreq_hw 0>; 290 #cooling-cells = <2>; 291 l2_300: l2-cache { 292 compatible = "cache"; 293 cache-level = <2>; 294 cache-unified; 295 next-level-cache = <&l3_0>; 296 }; 297 }; 298 299 cpu4: cpu@400 { 300 device_type = "cpu"; 301 compatible = "qcom,kryo"; 302 reg = <0x0 0x400>; 303 clocks = <&cpufreq_hw 1>; 304 enable-method = "psci"; 305 power-domains = <&cpu_pd4>; 306 power-domain-names = "psci"; 307 next-level-cache = <&l2_400>; 308 operating-points-v2 = <&cpu4_opp_table>; 309 capacity-dmips-mhz = <1946>; 310 dynamic-power-coefficient = <520>; 311 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 312 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 313 qcom,freq-domain = <&cpufreq_hw 1>; 314 #cooling-cells = <2>; 315 l2_400: l2-cache { 316 compatible = "cache"; 317 cache-level = <2>; 318 cache-unified; 319 next-level-cache = <&l3_0>; 320 }; 321 }; 322 323 cpu5: cpu@500 { 324 device_type = "cpu"; 325 compatible = "qcom,kryo"; 326 reg = <0x0 0x500>; 327 clocks = <&cpufreq_hw 1>; 328 enable-method = "psci"; 329 power-domains = <&cpu_pd5>; 330 power-domain-names = "psci"; 331 next-level-cache = <&l2_500>; 332 operating-points-v2 = <&cpu4_opp_table>; 333 capacity-dmips-mhz = <1946>; 334 dynamic-power-coefficient = <520>; 335 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 336 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 337 qcom,freq-domain = <&cpufreq_hw 1>; 338 #cooling-cells = <2>; 339 l2_500: l2-cache { 340 compatible = "cache"; 341 cache-level = <2>; 342 cache-unified; 343 next-level-cache = <&l3_0>; 344 }; 345 }; 346 347 cpu6: cpu@600 { 348 device_type = "cpu"; 349 compatible = "qcom,kryo"; 350 reg = <0x0 0x600>; 351 clocks = <&cpufreq_hw 1>; 352 enable-method = "psci"; 353 power-domains = <&cpu_pd6>; 354 power-domain-names = "psci"; 355 next-level-cache = <&l2_600>; 356 operating-points-v2 = <&cpu4_opp_table>; 357 capacity-dmips-mhz = <1946>; 358 dynamic-power-coefficient = <520>; 359 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 360 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 361 qcom,freq-domain = <&cpufreq_hw 1>; 362 #cooling-cells = <2>; 363 l2_600: l2-cache { 364 compatible = "cache"; 365 cache-level = <2>; 366 cache-unified; 367 next-level-cache = <&l3_0>; 368 }; 369 }; 370 371 cpu7: cpu@700 { 372 device_type = "cpu"; 373 compatible = "qcom,kryo"; 374 reg = <0x0 0x700>; 375 clocks = <&cpufreq_hw 2>; 376 enable-method = "psci"; 377 power-domains = <&cpu_pd7>; 378 power-domain-names = "psci"; 379 next-level-cache = <&l2_700>; 380 operating-points-v2 = <&cpu7_opp_table>; 381 capacity-dmips-mhz = <1985>; 382 dynamic-power-coefficient = <552>; 383 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 384 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 385 qcom,freq-domain = <&cpufreq_hw 2>; 386 #cooling-cells = <2>; 387 l2_700: l2-cache { 388 compatible = "cache"; 389 cache-level = <2>; 390 cache-unified; 391 next-level-cache = <&l3_0>; 392 }; 393 }; 394 395 cpu-map { 396 cluster0 { 397 core0 { 398 cpu = <&cpu0>; 399 }; 400 401 core1 { 402 cpu = <&cpu1>; 403 }; 404 405 core2 { 406 cpu = <&cpu2>; 407 }; 408 409 core3 { 410 cpu = <&cpu3>; 411 }; 412 413 core4 { 414 cpu = <&cpu4>; 415 }; 416 417 core5 { 418 cpu = <&cpu5>; 419 }; 420 421 core6 { 422 cpu = <&cpu6>; 423 }; 424 425 core7 { 426 cpu = <&cpu7>; 427 }; 428 }; 429 }; 430 431 idle-states { 432 entry-method = "psci"; 433 434 little_cpu_sleep_0: cpu-sleep-0-0 { 435 compatible = "arm,idle-state"; 436 idle-state-name = "little-power-down"; 437 arm,psci-suspend-param = <0x40000003>; 438 entry-latency-us = <549>; 439 exit-latency-us = <901>; 440 min-residency-us = <1774>; 441 local-timer-stop; 442 }; 443 444 little_cpu_sleep_1: cpu-sleep-0-1 { 445 compatible = "arm,idle-state"; 446 idle-state-name = "little-rail-power-down"; 447 arm,psci-suspend-param = <0x40000004>; 448 entry-latency-us = <702>; 449 exit-latency-us = <915>; 450 min-residency-us = <4001>; 451 local-timer-stop; 452 }; 453 454 big_cpu_sleep_0: cpu-sleep-1-0 { 455 compatible = "arm,idle-state"; 456 idle-state-name = "big-power-down"; 457 arm,psci-suspend-param = <0x40000003>; 458 entry-latency-us = <523>; 459 exit-latency-us = <1244>; 460 min-residency-us = <2207>; 461 local-timer-stop; 462 }; 463 464 big_cpu_sleep_1: cpu-sleep-1-1 { 465 compatible = "arm,idle-state"; 466 idle-state-name = "big-rail-power-down"; 467 arm,psci-suspend-param = <0x40000004>; 468 entry-latency-us = <526>; 469 exit-latency-us = <1854>; 470 min-residency-us = <5555>; 471 local-timer-stop; 472 }; 473 }; 474 475 domain_idle_states: domain-idle-states { 476 cluster_sleep_apss_off: cluster-sleep-0 { 477 compatible = "domain-idle-state"; 478 arm,psci-suspend-param = <0x41000044>; 479 entry-latency-us = <2752>; 480 exit-latency-us = <3048>; 481 min-residency-us = <6118>; 482 }; 483 484 cluster_sleep_cx_ret: cluster-sleep-1 { 485 compatible = "domain-idle-state"; 486 arm,psci-suspend-param = <0x41001344>; 487 entry-latency-us = <3263>; 488 exit-latency-us = <4562>; 489 min-residency-us = <8467>; 490 }; 491 492 cluster_sleep_llcc_off: cluster-sleep-2 { 493 compatible = "domain-idle-state"; 494 arm,psci-suspend-param = <0x4100b344>; 495 entry-latency-us = <3638>; 496 exit-latency-us = <6562>; 497 min-residency-us = <9826>; 498 }; 499 }; 500 }; 501 502 cpu0_opp_table: opp-table-cpu0 { 503 compatible = "operating-points-v2"; 504 opp-shared; 505 506 cpu0_opp_300mhz: opp-300000000 { 507 opp-hz = /bits/ 64 <300000000>; 508 opp-peak-kBps = <800000 9600000>; 509 }; 510 511 cpu0_opp_691mhz: opp-691200000 { 512 opp-hz = /bits/ 64 <691200000>; 513 opp-peak-kBps = <800000 17817600>; 514 }; 515 516 cpu0_opp_806mhz: opp-806400000 { 517 opp-hz = /bits/ 64 <806400000>; 518 opp-peak-kBps = <800000 20889600>; 519 }; 520 521 cpu0_opp_941mhz: opp-940800000 { 522 opp-hz = /bits/ 64 <940800000>; 523 opp-peak-kBps = <1804000 24576000>; 524 }; 525 526 cpu0_opp_1152mhz: opp-1152000000 { 527 opp-hz = /bits/ 64 <1152000000>; 528 opp-peak-kBps = <2188000 27033600>; 529 }; 530 531 cpu0_opp_1325mhz: opp-1324800000 { 532 opp-hz = /bits/ 64 <1324800000>; 533 opp-peak-kBps = <2188000 33792000>; 534 }; 535 536 cpu0_opp_1517mhz: opp-1516800000 { 537 opp-hz = /bits/ 64 <1516800000>; 538 opp-peak-kBps = <3072000 38092800>; 539 }; 540 541 cpu0_opp_1651mhz: opp-1651200000 { 542 opp-hz = /bits/ 64 <1651200000>; 543 opp-peak-kBps = <3072000 41779200>; 544 }; 545 546 cpu0_opp_1805mhz: opp-1804800000 { 547 opp-hz = /bits/ 64 <1804800000>; 548 opp-peak-kBps = <4068000 48537600>; 549 }; 550 551 cpu0_opp_1958mhz: opp-1958400000 { 552 opp-hz = /bits/ 64 <1958400000>; 553 opp-peak-kBps = <4068000 48537600>; 554 }; 555 556 cpu0_opp_2016mhz: opp-2016000000 { 557 opp-hz = /bits/ 64 <2016000000>; 558 opp-peak-kBps = <6220000 48537600>; 559 }; 560 }; 561 562 cpu4_opp_table: opp-table-cpu4 { 563 compatible = "operating-points-v2"; 564 opp-shared; 565 566 cpu4_opp_691mhz: opp-691200000 { 567 opp-hz = /bits/ 64 <691200000>; 568 opp-peak-kBps = <1804000 9600000>; 569 }; 570 571 cpu4_opp_941mhz: opp-940800000 { 572 opp-hz = /bits/ 64 <940800000>; 573 opp-peak-kBps = <2188000 17817600>; 574 }; 575 576 cpu4_opp_1229mhz: opp-1228800000 { 577 opp-hz = /bits/ 64 <1228800000>; 578 opp-peak-kBps = <4068000 24576000>; 579 }; 580 581 cpu4_opp_1344mhz: opp-1344000000 { 582 opp-hz = /bits/ 64 <1344000000>; 583 opp-peak-kBps = <4068000 24576000>; 584 }; 585 586 cpu4_opp_1517mhz: opp-1516800000 { 587 opp-hz = /bits/ 64 <1516800000>; 588 opp-peak-kBps = <4068000 24576000>; 589 }; 590 591 cpu4_opp_1651mhz: opp-1651200000 { 592 opp-hz = /bits/ 64 <1651200000>; 593 opp-peak-kBps = <6220000 38092800>; 594 }; 595 596 cpu4_opp_1901mhz: opp-1900800000 { 597 opp-hz = /bits/ 64 <1900800000>; 598 opp-peak-kBps = <6220000 44851200>; 599 }; 600 601 cpu4_opp_2054mhz: opp-2054400000 { 602 opp-hz = /bits/ 64 <2054400000>; 603 opp-peak-kBps = <6220000 44851200>; 604 }; 605 606 cpu4_opp_2112mhz: opp-2112000000 { 607 opp-hz = /bits/ 64 <2112000000>; 608 opp-peak-kBps = <6220000 44851200>; 609 }; 610 611 cpu4_opp_2131mhz: opp-2131200000 { 612 opp-hz = /bits/ 64 <2131200000>; 613 opp-peak-kBps = <6220000 44851200>; 614 }; 615 616 cpu4_opp_2208mhz: opp-2208000000 { 617 opp-hz = /bits/ 64 <2208000000>; 618 opp-peak-kBps = <6220000 44851200>; 619 }; 620 621 cpu4_opp_2400mhz: opp-2400000000 { 622 opp-hz = /bits/ 64 <2400000000>; 623 opp-peak-kBps = <8532000 48537600>; 624 }; 625 626 cpu4_opp_2611mhz: opp-2611200000 { 627 opp-hz = /bits/ 64 <2611200000>; 628 opp-peak-kBps = <8532000 48537600>; 629 }; 630 }; 631 632 cpu7_opp_table: opp-table-cpu7 { 633 compatible = "operating-points-v2"; 634 opp-shared; 635 636 cpu7_opp_806mhz: opp-806400000 { 637 opp-hz = /bits/ 64 <806400000>; 638 opp-peak-kBps = <1804000 9600000>; 639 }; 640 641 cpu7_opp_1056mhz: opp-1056000000 { 642 opp-hz = /bits/ 64 <1056000000>; 643 opp-peak-kBps = <2188000 17817600>; 644 }; 645 646 cpu7_opp_1325mhz: opp-1324800000 { 647 opp-hz = /bits/ 64 <1324800000>; 648 opp-peak-kBps = <4068000 24576000>; 649 }; 650 651 cpu7_opp_1517mhz: opp-1516800000 { 652 opp-hz = /bits/ 64 <1516800000>; 653 opp-peak-kBps = <4068000 24576000>; 654 }; 655 656 cpu7_opp_1766mhz: opp-1766400000 { 657 opp-hz = /bits/ 64 <1766400000>; 658 opp-peak-kBps = <6220000 38092800>; 659 }; 660 661 cpu7_opp_1862mhz: opp-1862400000 { 662 opp-hz = /bits/ 64 <1862400000>; 663 opp-peak-kBps = <6220000 38092800>; 664 }; 665 666 cpu7_opp_2035mhz: opp-2035200000 { 667 opp-hz = /bits/ 64 <2035200000>; 668 opp-peak-kBps = <6220000 38092800>; 669 }; 670 671 cpu7_opp_2112mhz: opp-2112000000 { 672 opp-hz = /bits/ 64 <2112000000>; 673 opp-peak-kBps = <6220000 44851200>; 674 }; 675 676 cpu7_opp_2208mhz: opp-2208000000 { 677 opp-hz = /bits/ 64 <2208000000>; 678 opp-peak-kBps = <6220000 44851200>; 679 }; 680 681 cpu7_opp_2381mhz: opp-2380800000 { 682 opp-hz = /bits/ 64 <2380800000>; 683 opp-peak-kBps = <6832000 44851200>; 684 }; 685 686 cpu7_opp_2400mhz: opp-2400000000 { 687 opp-hz = /bits/ 64 <2400000000>; 688 opp-peak-kBps = <8532000 48537600>; 689 }; 690 691 cpu7_opp_2515mhz: opp-2515200000 { 692 opp-hz = /bits/ 64 <2515200000>; 693 opp-peak-kBps = <8532000 48537600>; 694 }; 695 696 cpu7_opp_2707mhz: opp-2707200000 { 697 opp-hz = /bits/ 64 <2707200000>; 698 opp-peak-kBps = <8532000 48537600>; 699 }; 700 701 cpu7_opp_3014mhz: opp-3014400000 { 702 opp-hz = /bits/ 64 <3014400000>; 703 opp-peak-kBps = <8532000 48537600>; 704 }; 705 }; 706 707 memory@80000000 { 708 device_type = "memory"; 709 /* We expect the bootloader to fill in the size */ 710 reg = <0 0x80000000 0 0>; 711 }; 712 713 firmware { 714 scm: scm { 715 compatible = "qcom,scm-sc7280", "qcom,scm"; 716 qcom,dload-mode = <&tcsr_2 0x13000>; 717 }; 718 }; 719 720 clk_virt: interconnect { 721 compatible = "qcom,sc7280-clk-virt"; 722 #interconnect-cells = <2>; 723 qcom,bcm-voters = <&apps_bcm_voter>; 724 }; 725 726 smem { 727 compatible = "qcom,smem"; 728 memory-region = <&smem_mem>; 729 hwlocks = <&tcsr_mutex 3>; 730 }; 731 732 smp2p-adsp { 733 compatible = "qcom,smp2p"; 734 qcom,smem = <443>, <429>; 735 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 736 IPCC_MPROC_SIGNAL_SMP2P 737 IRQ_TYPE_EDGE_RISING>; 738 mboxes = <&ipcc IPCC_CLIENT_LPASS 739 IPCC_MPROC_SIGNAL_SMP2P>; 740 741 qcom,local-pid = <0>; 742 qcom,remote-pid = <2>; 743 744 adsp_smp2p_out: master-kernel { 745 qcom,entry-name = "master-kernel"; 746 #qcom,smem-state-cells = <1>; 747 }; 748 749 adsp_smp2p_in: slave-kernel { 750 qcom,entry-name = "slave-kernel"; 751 interrupt-controller; 752 #interrupt-cells = <2>; 753 }; 754 }; 755 756 smp2p-cdsp { 757 compatible = "qcom,smp2p"; 758 qcom,smem = <94>, <432>; 759 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 760 IPCC_MPROC_SIGNAL_SMP2P 761 IRQ_TYPE_EDGE_RISING>; 762 mboxes = <&ipcc IPCC_CLIENT_CDSP 763 IPCC_MPROC_SIGNAL_SMP2P>; 764 765 qcom,local-pid = <0>; 766 qcom,remote-pid = <5>; 767 768 cdsp_smp2p_out: master-kernel { 769 qcom,entry-name = "master-kernel"; 770 #qcom,smem-state-cells = <1>; 771 }; 772 773 cdsp_smp2p_in: slave-kernel { 774 qcom,entry-name = "slave-kernel"; 775 interrupt-controller; 776 #interrupt-cells = <2>; 777 }; 778 }; 779 780 smp2p-mpss { 781 compatible = "qcom,smp2p"; 782 qcom,smem = <435>, <428>; 783 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 784 IPCC_MPROC_SIGNAL_SMP2P 785 IRQ_TYPE_EDGE_RISING>; 786 mboxes = <&ipcc IPCC_CLIENT_MPSS 787 IPCC_MPROC_SIGNAL_SMP2P>; 788 789 qcom,local-pid = <0>; 790 qcom,remote-pid = <1>; 791 792 modem_smp2p_out: master-kernel { 793 qcom,entry-name = "master-kernel"; 794 #qcom,smem-state-cells = <1>; 795 }; 796 797 modem_smp2p_in: slave-kernel { 798 qcom,entry-name = "slave-kernel"; 799 interrupt-controller; 800 #interrupt-cells = <2>; 801 }; 802 803 ipa_smp2p_out: ipa-ap-to-modem { 804 qcom,entry-name = "ipa"; 805 #qcom,smem-state-cells = <1>; 806 }; 807 808 ipa_smp2p_in: ipa-modem-to-ap { 809 qcom,entry-name = "ipa"; 810 interrupt-controller; 811 #interrupt-cells = <2>; 812 }; 813 }; 814 815 smp2p-wpss { 816 compatible = "qcom,smp2p"; 817 qcom,smem = <617>, <616>; 818 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 819 IPCC_MPROC_SIGNAL_SMP2P 820 IRQ_TYPE_EDGE_RISING>; 821 mboxes = <&ipcc IPCC_CLIENT_WPSS 822 IPCC_MPROC_SIGNAL_SMP2P>; 823 824 qcom,local-pid = <0>; 825 qcom,remote-pid = <13>; 826 827 wpss_smp2p_out: master-kernel { 828 qcom,entry-name = "master-kernel"; 829 #qcom,smem-state-cells = <1>; 830 }; 831 832 wpss_smp2p_in: slave-kernel { 833 qcom,entry-name = "slave-kernel"; 834 interrupt-controller; 835 #interrupt-cells = <2>; 836 }; 837 838 wlan_smp2p_out: wlan-ap-to-wpss { 839 qcom,entry-name = "wlan"; 840 #qcom,smem-state-cells = <1>; 841 }; 842 843 wlan_smp2p_in: wlan-wpss-to-ap { 844 qcom,entry-name = "wlan"; 845 interrupt-controller; 846 #interrupt-cells = <2>; 847 }; 848 }; 849 850 pmu-a55 { 851 compatible = "arm,cortex-a55-pmu"; 852 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 853 }; 854 855 pmu-a78 { 856 compatible = "arm,cortex-a78-pmu"; 857 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 858 }; 859 860 psci { 861 compatible = "arm,psci-1.0"; 862 method = "smc"; 863 864 cpu_pd0: power-domain-cpu0 { 865 #power-domain-cells = <0>; 866 power-domains = <&cluster_pd>; 867 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 868 }; 869 870 cpu_pd1: power-domain-cpu1 { 871 #power-domain-cells = <0>; 872 power-domains = <&cluster_pd>; 873 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 874 }; 875 876 cpu_pd2: power-domain-cpu2 { 877 #power-domain-cells = <0>; 878 power-domains = <&cluster_pd>; 879 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 880 }; 881 882 cpu_pd3: power-domain-cpu3 { 883 #power-domain-cells = <0>; 884 power-domains = <&cluster_pd>; 885 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 886 }; 887 888 cpu_pd4: power-domain-cpu4 { 889 #power-domain-cells = <0>; 890 power-domains = <&cluster_pd>; 891 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 892 }; 893 894 cpu_pd5: power-domain-cpu5 { 895 #power-domain-cells = <0>; 896 power-domains = <&cluster_pd>; 897 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 898 }; 899 900 cpu_pd6: power-domain-cpu6 { 901 #power-domain-cells = <0>; 902 power-domains = <&cluster_pd>; 903 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 904 }; 905 906 cpu_pd7: power-domain-cpu7 { 907 #power-domain-cells = <0>; 908 power-domains = <&cluster_pd>; 909 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 910 }; 911 912 cluster_pd: power-domain-cluster { 913 #power-domain-cells = <0>; 914 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_cx_ret &cluster_sleep_llcc_off>; 915 }; 916 }; 917 918 qspi_opp_table: opp-table-qspi { 919 compatible = "operating-points-v2"; 920 921 opp-75000000 { 922 opp-hz = /bits/ 64 <75000000>; 923 required-opps = <&rpmhpd_opp_low_svs>; 924 }; 925 926 opp-150000000 { 927 opp-hz = /bits/ 64 <150000000>; 928 required-opps = <&rpmhpd_opp_svs>; 929 }; 930 931 opp-200000000 { 932 opp-hz = /bits/ 64 <200000000>; 933 required-opps = <&rpmhpd_opp_svs_l1>; 934 }; 935 936 opp-300000000 { 937 opp-hz = /bits/ 64 <300000000>; 938 required-opps = <&rpmhpd_opp_nom>; 939 }; 940 }; 941 942 qup_opp_table: opp-table-qup { 943 compatible = "operating-points-v2"; 944 945 opp-75000000 { 946 opp-hz = /bits/ 64 <75000000>; 947 required-opps = <&rpmhpd_opp_low_svs>; 948 }; 949 950 opp-100000000 { 951 opp-hz = /bits/ 64 <100000000>; 952 required-opps = <&rpmhpd_opp_svs>; 953 }; 954 955 opp-128000000 { 956 opp-hz = /bits/ 64 <128000000>; 957 required-opps = <&rpmhpd_opp_nom>; 958 }; 959 }; 960 961 soc: soc@0 { 962 #address-cells = <2>; 963 #size-cells = <2>; 964 ranges = <0 0 0 0 0x10 0>; 965 dma-ranges = <0 0 0 0 0x10 0>; 966 compatible = "simple-bus"; 967 968 gcc: clock-controller@100000 { 969 compatible = "qcom,gcc-sc7280"; 970 reg = <0 0x00100000 0 0x1f0000>; 971 clocks = <&rpmhcc RPMH_CXO_CLK>, 972 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 973 <0>, <&pcie1_phy>, 974 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, 975 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 976 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 977 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 978 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 979 "ufs_phy_tx_symbol_0_clk", 980 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 981 #clock-cells = <1>; 982 #reset-cells = <1>; 983 #power-domain-cells = <1>; 984 power-domains = <&rpmhpd SC7280_CX>; 985 }; 986 987 ipcc: mailbox@408000 { 988 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 989 reg = <0 0x00408000 0 0x1000>; 990 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 991 interrupt-controller; 992 #interrupt-cells = <3>; 993 #mbox-cells = <2>; 994 }; 995 996 qfprom: efuse@784000 { 997 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 998 reg = <0 0x00784000 0 0xa20>, 999 <0 0x00780000 0 0xa20>, 1000 <0 0x00782000 0 0x120>, 1001 <0 0x00786000 0 0x1fff>; 1002 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 1003 clock-names = "core"; 1004 power-domains = <&rpmhpd SC7280_MX>; 1005 #address-cells = <1>; 1006 #size-cells = <1>; 1007 1008 gpu_speed_bin: gpu-speed-bin@1e9 { 1009 reg = <0x1e9 0x2>; 1010 bits = <5 8>; 1011 }; 1012 }; 1013 1014 sdhc_1: mmc@7c4000 { 1015 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1016 pinctrl-names = "default", "sleep"; 1017 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 1018 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 1019 status = "disabled"; 1020 1021 reg = <0 0x007c4000 0 0x1000>, 1022 <0 0x007c5000 0 0x1000>; 1023 reg-names = "hc", "cqhci"; 1024 1025 iommus = <&apps_smmu 0xc0 0x0>; 1026 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 1028 interrupt-names = "hc_irq", "pwr_irq"; 1029 1030 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1031 <&gcc GCC_SDCC1_APPS_CLK>, 1032 <&rpmhcc RPMH_CXO_CLK>; 1033 clock-names = "iface", "core", "xo"; 1034 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 1035 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 1036 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1037 power-domains = <&rpmhpd SC7280_CX>; 1038 operating-points-v2 = <&sdhc1_opp_table>; 1039 1040 bus-width = <8>; 1041 supports-cqe; 1042 dma-coherent; 1043 1044 qcom,dll-config = <0x0007642c>; 1045 qcom,ddr-config = <0x80040868>; 1046 1047 mmc-ddr-1_8v; 1048 mmc-hs200-1_8v; 1049 mmc-hs400-1_8v; 1050 mmc-hs400-enhanced-strobe; 1051 1052 resets = <&gcc GCC_SDCC1_BCR>; 1053 1054 sdhc1_opp_table: opp-table { 1055 compatible = "operating-points-v2"; 1056 1057 opp-100000000 { 1058 opp-hz = /bits/ 64 <100000000>; 1059 required-opps = <&rpmhpd_opp_low_svs>; 1060 opp-peak-kBps = <1800000 400000>; 1061 opp-avg-kBps = <100000 0>; 1062 }; 1063 1064 opp-384000000 { 1065 opp-hz = /bits/ 64 <384000000>; 1066 required-opps = <&rpmhpd_opp_nom>; 1067 opp-peak-kBps = <5400000 1600000>; 1068 opp-avg-kBps = <390000 0>; 1069 }; 1070 }; 1071 }; 1072 1073 gpi_dma0: dma-controller@900000 { 1074 #dma-cells = <3>; 1075 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1076 reg = <0 0x00900000 0 0x60000>; 1077 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1089 dma-channels = <12>; 1090 dma-channel-mask = <0x7f>; 1091 iommus = <&apps_smmu 0x0136 0x0>; 1092 status = "disabled"; 1093 }; 1094 1095 qupv3_id_0: geniqup@9c0000 { 1096 compatible = "qcom,geni-se-qup"; 1097 reg = <0 0x009c0000 0 0x2000>; 1098 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1099 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1100 clock-names = "m-ahb", "s-ahb"; 1101 #address-cells = <2>; 1102 #size-cells = <2>; 1103 ranges; 1104 iommus = <&apps_smmu 0x123 0x0>; 1105 status = "disabled"; 1106 1107 i2c0: i2c@980000 { 1108 compatible = "qcom,geni-i2c"; 1109 reg = <0 0x00980000 0 0x4000>; 1110 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1111 clock-names = "se"; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&qup_i2c0_data_clk>; 1114 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1118 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1119 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1120 interconnect-names = "qup-core", "qup-config", 1121 "qup-memory"; 1122 power-domains = <&rpmhpd SC7280_CX>; 1123 required-opps = <&rpmhpd_opp_low_svs>; 1124 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1125 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1126 dma-names = "tx", "rx"; 1127 status = "disabled"; 1128 }; 1129 1130 spi0: spi@980000 { 1131 compatible = "qcom,geni-spi"; 1132 reg = <0 0x00980000 0 0x4000>; 1133 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1134 clock-names = "se"; 1135 pinctrl-names = "default"; 1136 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1137 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 power-domains = <&rpmhpd SC7280_CX>; 1141 operating-points-v2 = <&qup_opp_table>; 1142 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1143 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1144 interconnect-names = "qup-core", "qup-config"; 1145 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1146 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1147 dma-names = "tx", "rx"; 1148 status = "disabled"; 1149 }; 1150 1151 uart0: serial@980000 { 1152 compatible = "qcom,geni-uart"; 1153 reg = <0 0x00980000 0 0x4000>; 1154 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1155 clock-names = "se"; 1156 pinctrl-names = "default"; 1157 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1158 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1159 power-domains = <&rpmhpd SC7280_CX>; 1160 operating-points-v2 = <&qup_opp_table>; 1161 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1162 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1163 interconnect-names = "qup-core", "qup-config"; 1164 status = "disabled"; 1165 }; 1166 1167 i2c1: i2c@984000 { 1168 compatible = "qcom,geni-i2c"; 1169 reg = <0 0x00984000 0 0x4000>; 1170 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1171 clock-names = "se"; 1172 pinctrl-names = "default"; 1173 pinctrl-0 = <&qup_i2c1_data_clk>; 1174 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1178 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1179 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1180 interconnect-names = "qup-core", "qup-config", 1181 "qup-memory"; 1182 power-domains = <&rpmhpd SC7280_CX>; 1183 required-opps = <&rpmhpd_opp_low_svs>; 1184 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1185 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1186 dma-names = "tx", "rx"; 1187 status = "disabled"; 1188 }; 1189 1190 spi1: spi@984000 { 1191 compatible = "qcom,geni-spi"; 1192 reg = <0 0x00984000 0 0x4000>; 1193 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1194 clock-names = "se"; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1197 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 power-domains = <&rpmhpd SC7280_CX>; 1201 operating-points-v2 = <&qup_opp_table>; 1202 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1203 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1204 interconnect-names = "qup-core", "qup-config"; 1205 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1206 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1207 dma-names = "tx", "rx"; 1208 status = "disabled"; 1209 }; 1210 1211 uart1: serial@984000 { 1212 compatible = "qcom,geni-uart"; 1213 reg = <0 0x00984000 0 0x4000>; 1214 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1215 clock-names = "se"; 1216 pinctrl-names = "default"; 1217 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1218 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1219 power-domains = <&rpmhpd SC7280_CX>; 1220 operating-points-v2 = <&qup_opp_table>; 1221 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1222 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1223 interconnect-names = "qup-core", "qup-config"; 1224 status = "disabled"; 1225 }; 1226 1227 i2c2: i2c@988000 { 1228 compatible = "qcom,geni-i2c"; 1229 reg = <0 0x00988000 0 0x4000>; 1230 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1231 clock-names = "se"; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&qup_i2c2_data_clk>; 1234 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1235 #address-cells = <1>; 1236 #size-cells = <0>; 1237 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1238 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1239 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1240 interconnect-names = "qup-core", "qup-config", 1241 "qup-memory"; 1242 power-domains = <&rpmhpd SC7280_CX>; 1243 required-opps = <&rpmhpd_opp_low_svs>; 1244 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1245 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1246 dma-names = "tx", "rx"; 1247 status = "disabled"; 1248 }; 1249 1250 spi2: spi@988000 { 1251 compatible = "qcom,geni-spi"; 1252 reg = <0 0x00988000 0 0x4000>; 1253 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1254 clock-names = "se"; 1255 pinctrl-names = "default"; 1256 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1257 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 power-domains = <&rpmhpd SC7280_CX>; 1261 operating-points-v2 = <&qup_opp_table>; 1262 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1263 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1264 interconnect-names = "qup-core", "qup-config"; 1265 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1266 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1267 dma-names = "tx", "rx"; 1268 status = "disabled"; 1269 }; 1270 1271 uart2: serial@988000 { 1272 compatible = "qcom,geni-uart"; 1273 reg = <0 0x00988000 0 0x4000>; 1274 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1275 clock-names = "se"; 1276 pinctrl-names = "default"; 1277 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1278 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1279 power-domains = <&rpmhpd SC7280_CX>; 1280 operating-points-v2 = <&qup_opp_table>; 1281 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1282 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1283 interconnect-names = "qup-core", "qup-config"; 1284 status = "disabled"; 1285 }; 1286 1287 i2c3: i2c@98c000 { 1288 compatible = "qcom,geni-i2c"; 1289 reg = <0 0x0098c000 0 0x4000>; 1290 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1291 clock-names = "se"; 1292 pinctrl-names = "default"; 1293 pinctrl-0 = <&qup_i2c3_data_clk>; 1294 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1298 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1299 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1300 interconnect-names = "qup-core", "qup-config", 1301 "qup-memory"; 1302 power-domains = <&rpmhpd SC7280_CX>; 1303 required-opps = <&rpmhpd_opp_low_svs>; 1304 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1305 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1306 dma-names = "tx", "rx"; 1307 status = "disabled"; 1308 }; 1309 1310 spi3: spi@98c000 { 1311 compatible = "qcom,geni-spi"; 1312 reg = <0 0x0098c000 0 0x4000>; 1313 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1314 clock-names = "se"; 1315 pinctrl-names = "default"; 1316 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1317 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 power-domains = <&rpmhpd SC7280_CX>; 1321 operating-points-v2 = <&qup_opp_table>; 1322 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1323 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1324 interconnect-names = "qup-core", "qup-config"; 1325 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1326 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1327 dma-names = "tx", "rx"; 1328 status = "disabled"; 1329 }; 1330 1331 uart3: serial@98c000 { 1332 compatible = "qcom,geni-uart"; 1333 reg = <0 0x0098c000 0 0x4000>; 1334 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1335 clock-names = "se"; 1336 pinctrl-names = "default"; 1337 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1338 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1339 power-domains = <&rpmhpd SC7280_CX>; 1340 operating-points-v2 = <&qup_opp_table>; 1341 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1342 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1343 interconnect-names = "qup-core", "qup-config"; 1344 status = "disabled"; 1345 }; 1346 1347 i2c4: i2c@990000 { 1348 compatible = "qcom,geni-i2c"; 1349 reg = <0 0x00990000 0 0x4000>; 1350 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1351 clock-names = "se"; 1352 pinctrl-names = "default"; 1353 pinctrl-0 = <&qup_i2c4_data_clk>; 1354 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1358 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1359 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1360 interconnect-names = "qup-core", "qup-config", 1361 "qup-memory"; 1362 power-domains = <&rpmhpd SC7280_CX>; 1363 required-opps = <&rpmhpd_opp_low_svs>; 1364 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1365 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1366 dma-names = "tx", "rx"; 1367 status = "disabled"; 1368 }; 1369 1370 spi4: spi@990000 { 1371 compatible = "qcom,geni-spi"; 1372 reg = <0 0x00990000 0 0x4000>; 1373 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1374 clock-names = "se"; 1375 pinctrl-names = "default"; 1376 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1377 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 power-domains = <&rpmhpd SC7280_CX>; 1381 operating-points-v2 = <&qup_opp_table>; 1382 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1383 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1384 interconnect-names = "qup-core", "qup-config"; 1385 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1386 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1387 dma-names = "tx", "rx"; 1388 status = "disabled"; 1389 }; 1390 1391 uart4: serial@990000 { 1392 compatible = "qcom,geni-uart"; 1393 reg = <0 0x00990000 0 0x4000>; 1394 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1395 clock-names = "se"; 1396 pinctrl-names = "default"; 1397 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1398 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1399 power-domains = <&rpmhpd SC7280_CX>; 1400 operating-points-v2 = <&qup_opp_table>; 1401 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1402 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1403 interconnect-names = "qup-core", "qup-config"; 1404 status = "disabled"; 1405 }; 1406 1407 i2c5: i2c@994000 { 1408 compatible = "qcom,geni-i2c"; 1409 reg = <0 0x00994000 0 0x4000>; 1410 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1411 clock-names = "se"; 1412 pinctrl-names = "default"; 1413 pinctrl-0 = <&qup_i2c5_data_clk>; 1414 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1415 #address-cells = <1>; 1416 #size-cells = <0>; 1417 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1418 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1419 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1420 interconnect-names = "qup-core", "qup-config", 1421 "qup-memory"; 1422 power-domains = <&rpmhpd SC7280_CX>; 1423 required-opps = <&rpmhpd_opp_low_svs>; 1424 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1425 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1426 dma-names = "tx", "rx"; 1427 status = "disabled"; 1428 }; 1429 1430 spi5: spi@994000 { 1431 compatible = "qcom,geni-spi"; 1432 reg = <0 0x00994000 0 0x4000>; 1433 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1434 clock-names = "se"; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1437 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 power-domains = <&rpmhpd SC7280_CX>; 1441 operating-points-v2 = <&qup_opp_table>; 1442 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1443 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1444 interconnect-names = "qup-core", "qup-config"; 1445 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1446 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1447 dma-names = "tx", "rx"; 1448 status = "disabled"; 1449 }; 1450 1451 uart5: serial@994000 { 1452 compatible = "qcom,geni-debug-uart"; 1453 reg = <0 0x00994000 0 0x4000>; 1454 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1455 clock-names = "se"; 1456 pinctrl-names = "default"; 1457 pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; 1458 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1459 power-domains = <&rpmhpd SC7280_CX>; 1460 operating-points-v2 = <&qup_opp_table>; 1461 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1462 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1463 interconnect-names = "qup-core", "qup-config"; 1464 status = "disabled"; 1465 }; 1466 1467 i2c6: i2c@998000 { 1468 compatible = "qcom,geni-i2c"; 1469 reg = <0 0x00998000 0 0x4000>; 1470 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1471 clock-names = "se"; 1472 pinctrl-names = "default"; 1473 pinctrl-0 = <&qup_i2c6_data_clk>; 1474 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1475 #address-cells = <1>; 1476 #size-cells = <0>; 1477 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1478 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1479 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1480 interconnect-names = "qup-core", "qup-config", 1481 "qup-memory"; 1482 power-domains = <&rpmhpd SC7280_CX>; 1483 required-opps = <&rpmhpd_opp_low_svs>; 1484 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1485 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1486 dma-names = "tx", "rx"; 1487 status = "disabled"; 1488 }; 1489 1490 spi6: spi@998000 { 1491 compatible = "qcom,geni-spi"; 1492 reg = <0 0x00998000 0 0x4000>; 1493 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1494 clock-names = "se"; 1495 pinctrl-names = "default"; 1496 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1497 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1498 #address-cells = <1>; 1499 #size-cells = <0>; 1500 power-domains = <&rpmhpd SC7280_CX>; 1501 operating-points-v2 = <&qup_opp_table>; 1502 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1503 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1504 interconnect-names = "qup-core", "qup-config"; 1505 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1506 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1507 dma-names = "tx", "rx"; 1508 status = "disabled"; 1509 }; 1510 1511 uart6: serial@998000 { 1512 compatible = "qcom,geni-uart"; 1513 reg = <0 0x00998000 0 0x4000>; 1514 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1515 clock-names = "se"; 1516 pinctrl-names = "default"; 1517 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1518 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1519 power-domains = <&rpmhpd SC7280_CX>; 1520 operating-points-v2 = <&qup_opp_table>; 1521 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1522 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1523 interconnect-names = "qup-core", "qup-config"; 1524 status = "disabled"; 1525 }; 1526 1527 i2c7: i2c@99c000 { 1528 compatible = "qcom,geni-i2c"; 1529 reg = <0 0x0099c000 0 0x4000>; 1530 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1531 clock-names = "se"; 1532 pinctrl-names = "default"; 1533 pinctrl-0 = <&qup_i2c7_data_clk>; 1534 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1535 #address-cells = <1>; 1536 #size-cells = <0>; 1537 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1538 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1539 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1540 interconnect-names = "qup-core", "qup-config", 1541 "qup-memory"; 1542 power-domains = <&rpmhpd SC7280_CX>; 1543 required-opps = <&rpmhpd_opp_low_svs>; 1544 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1545 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1546 dma-names = "tx", "rx"; 1547 status = "disabled"; 1548 }; 1549 1550 spi7: spi@99c000 { 1551 compatible = "qcom,geni-spi"; 1552 reg = <0 0x0099c000 0 0x4000>; 1553 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1554 clock-names = "se"; 1555 pinctrl-names = "default"; 1556 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1557 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1558 #address-cells = <1>; 1559 #size-cells = <0>; 1560 power-domains = <&rpmhpd SC7280_CX>; 1561 operating-points-v2 = <&qup_opp_table>; 1562 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1563 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1564 interconnect-names = "qup-core", "qup-config"; 1565 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1566 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1567 dma-names = "tx", "rx"; 1568 status = "disabled"; 1569 }; 1570 1571 uart7: serial@99c000 { 1572 compatible = "qcom,geni-uart"; 1573 reg = <0 0x0099c000 0 0x4000>; 1574 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1575 clock-names = "se"; 1576 pinctrl-names = "default"; 1577 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1578 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1579 power-domains = <&rpmhpd SC7280_CX>; 1580 operating-points-v2 = <&qup_opp_table>; 1581 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1582 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1583 interconnect-names = "qup-core", "qup-config"; 1584 status = "disabled"; 1585 }; 1586 }; 1587 1588 gpi_dma1: dma-controller@a00000 { 1589 #dma-cells = <3>; 1590 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1591 reg = <0 0x00a00000 0 0x60000>; 1592 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1604 dma-channels = <12>; 1605 dma-channel-mask = <0x1e>; 1606 iommus = <&apps_smmu 0x56 0x0>; 1607 status = "disabled"; 1608 }; 1609 1610 qupv3_id_1: geniqup@ac0000 { 1611 compatible = "qcom,geni-se-qup"; 1612 reg = <0 0x00ac0000 0 0x2000>; 1613 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1614 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1615 clock-names = "m-ahb", "s-ahb"; 1616 #address-cells = <2>; 1617 #size-cells = <2>; 1618 ranges; 1619 iommus = <&apps_smmu 0x43 0x0>; 1620 status = "disabled"; 1621 1622 i2c8: i2c@a80000 { 1623 compatible = "qcom,geni-i2c"; 1624 reg = <0 0x00a80000 0 0x4000>; 1625 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1626 clock-names = "se"; 1627 pinctrl-names = "default"; 1628 pinctrl-0 = <&qup_i2c8_data_clk>; 1629 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1630 #address-cells = <1>; 1631 #size-cells = <0>; 1632 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1633 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1634 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1635 interconnect-names = "qup-core", "qup-config", 1636 "qup-memory"; 1637 power-domains = <&rpmhpd SC7280_CX>; 1638 required-opps = <&rpmhpd_opp_low_svs>; 1639 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1640 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1641 dma-names = "tx", "rx"; 1642 status = "disabled"; 1643 }; 1644 1645 spi8: spi@a80000 { 1646 compatible = "qcom,geni-spi"; 1647 reg = <0 0x00a80000 0 0x4000>; 1648 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1649 clock-names = "se"; 1650 pinctrl-names = "default"; 1651 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1652 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1653 #address-cells = <1>; 1654 #size-cells = <0>; 1655 power-domains = <&rpmhpd SC7280_CX>; 1656 operating-points-v2 = <&qup_opp_table>; 1657 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1658 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1659 interconnect-names = "qup-core", "qup-config"; 1660 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1661 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1662 dma-names = "tx", "rx"; 1663 status = "disabled"; 1664 }; 1665 1666 uart8: serial@a80000 { 1667 compatible = "qcom,geni-uart"; 1668 reg = <0 0x00a80000 0 0x4000>; 1669 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1670 clock-names = "se"; 1671 pinctrl-names = "default"; 1672 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1673 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1674 power-domains = <&rpmhpd SC7280_CX>; 1675 operating-points-v2 = <&qup_opp_table>; 1676 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1677 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1678 interconnect-names = "qup-core", "qup-config"; 1679 status = "disabled"; 1680 }; 1681 1682 i2c9: i2c@a84000 { 1683 compatible = "qcom,geni-i2c"; 1684 reg = <0 0x00a84000 0 0x4000>; 1685 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1686 clock-names = "se"; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&qup_i2c9_data_clk>; 1689 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1693 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1694 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1695 interconnect-names = "qup-core", "qup-config", 1696 "qup-memory"; 1697 power-domains = <&rpmhpd SC7280_CX>; 1698 required-opps = <&rpmhpd_opp_low_svs>; 1699 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1700 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1701 dma-names = "tx", "rx"; 1702 status = "disabled"; 1703 }; 1704 1705 spi9: spi@a84000 { 1706 compatible = "qcom,geni-spi"; 1707 reg = <0 0x00a84000 0 0x4000>; 1708 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1709 clock-names = "se"; 1710 pinctrl-names = "default"; 1711 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1712 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 power-domains = <&rpmhpd SC7280_CX>; 1716 operating-points-v2 = <&qup_opp_table>; 1717 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1718 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1719 interconnect-names = "qup-core", "qup-config"; 1720 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1721 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1722 dma-names = "tx", "rx"; 1723 status = "disabled"; 1724 }; 1725 1726 uart9: serial@a84000 { 1727 compatible = "qcom,geni-uart"; 1728 reg = <0 0x00a84000 0 0x4000>; 1729 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1730 clock-names = "se"; 1731 pinctrl-names = "default"; 1732 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1733 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1734 power-domains = <&rpmhpd SC7280_CX>; 1735 operating-points-v2 = <&qup_opp_table>; 1736 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1737 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1738 interconnect-names = "qup-core", "qup-config"; 1739 status = "disabled"; 1740 }; 1741 1742 i2c10: i2c@a88000 { 1743 compatible = "qcom,geni-i2c"; 1744 reg = <0 0x00a88000 0 0x4000>; 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1746 clock-names = "se"; 1747 pinctrl-names = "default"; 1748 pinctrl-0 = <&qup_i2c10_data_clk>; 1749 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1753 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1754 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1755 interconnect-names = "qup-core", "qup-config", 1756 "qup-memory"; 1757 power-domains = <&rpmhpd SC7280_CX>; 1758 required-opps = <&rpmhpd_opp_low_svs>; 1759 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1760 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1761 dma-names = "tx", "rx"; 1762 status = "disabled"; 1763 }; 1764 1765 spi10: spi@a88000 { 1766 compatible = "qcom,geni-spi"; 1767 reg = <0 0x00a88000 0 0x4000>; 1768 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1769 clock-names = "se"; 1770 pinctrl-names = "default"; 1771 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1772 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1773 #address-cells = <1>; 1774 #size-cells = <0>; 1775 power-domains = <&rpmhpd SC7280_CX>; 1776 operating-points-v2 = <&qup_opp_table>; 1777 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1778 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1779 interconnect-names = "qup-core", "qup-config"; 1780 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1781 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1782 dma-names = "tx", "rx"; 1783 status = "disabled"; 1784 }; 1785 1786 uart10: serial@a88000 { 1787 compatible = "qcom,geni-uart"; 1788 reg = <0 0x00a88000 0 0x4000>; 1789 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1790 clock-names = "se"; 1791 pinctrl-names = "default"; 1792 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1793 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1794 power-domains = <&rpmhpd SC7280_CX>; 1795 operating-points-v2 = <&qup_opp_table>; 1796 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1797 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1798 interconnect-names = "qup-core", "qup-config"; 1799 status = "disabled"; 1800 }; 1801 1802 i2c11: i2c@a8c000 { 1803 compatible = "qcom,geni-i2c"; 1804 reg = <0 0x00a8c000 0 0x4000>; 1805 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1806 clock-names = "se"; 1807 pinctrl-names = "default"; 1808 pinctrl-0 = <&qup_i2c11_data_clk>; 1809 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1810 #address-cells = <1>; 1811 #size-cells = <0>; 1812 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1813 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1814 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1815 interconnect-names = "qup-core", "qup-config", 1816 "qup-memory"; 1817 power-domains = <&rpmhpd SC7280_CX>; 1818 required-opps = <&rpmhpd_opp_low_svs>; 1819 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1820 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1821 dma-names = "tx", "rx"; 1822 status = "disabled"; 1823 }; 1824 1825 spi11: spi@a8c000 { 1826 compatible = "qcom,geni-spi"; 1827 reg = <0 0x00a8c000 0 0x4000>; 1828 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1829 clock-names = "se"; 1830 pinctrl-names = "default"; 1831 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1832 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1833 #address-cells = <1>; 1834 #size-cells = <0>; 1835 power-domains = <&rpmhpd SC7280_CX>; 1836 operating-points-v2 = <&qup_opp_table>; 1837 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1838 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1839 interconnect-names = "qup-core", "qup-config"; 1840 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1841 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1842 dma-names = "tx", "rx"; 1843 status = "disabled"; 1844 }; 1845 1846 uart11: serial@a8c000 { 1847 compatible = "qcom,geni-uart"; 1848 reg = <0 0x00a8c000 0 0x4000>; 1849 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1850 clock-names = "se"; 1851 pinctrl-names = "default"; 1852 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1853 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1854 power-domains = <&rpmhpd SC7280_CX>; 1855 operating-points-v2 = <&qup_opp_table>; 1856 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1857 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1858 interconnect-names = "qup-core", "qup-config"; 1859 status = "disabled"; 1860 }; 1861 1862 i2c12: i2c@a90000 { 1863 compatible = "qcom,geni-i2c"; 1864 reg = <0 0x00a90000 0 0x4000>; 1865 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1866 clock-names = "se"; 1867 pinctrl-names = "default"; 1868 pinctrl-0 = <&qup_i2c12_data_clk>; 1869 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1870 #address-cells = <1>; 1871 #size-cells = <0>; 1872 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1873 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1874 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1875 interconnect-names = "qup-core", "qup-config", 1876 "qup-memory"; 1877 power-domains = <&rpmhpd SC7280_CX>; 1878 required-opps = <&rpmhpd_opp_low_svs>; 1879 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1880 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1881 dma-names = "tx", "rx"; 1882 status = "disabled"; 1883 }; 1884 1885 spi12: spi@a90000 { 1886 compatible = "qcom,geni-spi"; 1887 reg = <0 0x00a90000 0 0x4000>; 1888 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1889 clock-names = "se"; 1890 pinctrl-names = "default"; 1891 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1892 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1893 #address-cells = <1>; 1894 #size-cells = <0>; 1895 power-domains = <&rpmhpd SC7280_CX>; 1896 operating-points-v2 = <&qup_opp_table>; 1897 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1898 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1899 interconnect-names = "qup-core", "qup-config"; 1900 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1901 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1902 dma-names = "tx", "rx"; 1903 status = "disabled"; 1904 }; 1905 1906 uart12: serial@a90000 { 1907 compatible = "qcom,geni-uart"; 1908 reg = <0 0x00a90000 0 0x4000>; 1909 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1910 clock-names = "se"; 1911 pinctrl-names = "default"; 1912 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1913 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1914 power-domains = <&rpmhpd SC7280_CX>; 1915 operating-points-v2 = <&qup_opp_table>; 1916 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1917 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1918 interconnect-names = "qup-core", "qup-config"; 1919 status = "disabled"; 1920 }; 1921 1922 i2c13: i2c@a94000 { 1923 compatible = "qcom,geni-i2c"; 1924 reg = <0 0x00a94000 0 0x4000>; 1925 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1926 clock-names = "se"; 1927 pinctrl-names = "default"; 1928 pinctrl-0 = <&qup_i2c13_data_clk>; 1929 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1930 #address-cells = <1>; 1931 #size-cells = <0>; 1932 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1933 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1934 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1935 interconnect-names = "qup-core", "qup-config", 1936 "qup-memory"; 1937 power-domains = <&rpmhpd SC7280_CX>; 1938 required-opps = <&rpmhpd_opp_low_svs>; 1939 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1940 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1941 dma-names = "tx", "rx"; 1942 status = "disabled"; 1943 }; 1944 1945 spi13: spi@a94000 { 1946 compatible = "qcom,geni-spi"; 1947 reg = <0 0x00a94000 0 0x4000>; 1948 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1949 clock-names = "se"; 1950 pinctrl-names = "default"; 1951 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1952 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1953 #address-cells = <1>; 1954 #size-cells = <0>; 1955 power-domains = <&rpmhpd SC7280_CX>; 1956 operating-points-v2 = <&qup_opp_table>; 1957 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1958 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1959 interconnect-names = "qup-core", "qup-config"; 1960 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1961 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1962 dma-names = "tx", "rx"; 1963 status = "disabled"; 1964 }; 1965 1966 uart13: serial@a94000 { 1967 compatible = "qcom,geni-uart"; 1968 reg = <0 0x00a94000 0 0x4000>; 1969 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1970 clock-names = "se"; 1971 pinctrl-names = "default"; 1972 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1973 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1974 power-domains = <&rpmhpd SC7280_CX>; 1975 operating-points-v2 = <&qup_opp_table>; 1976 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1977 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1978 interconnect-names = "qup-core", "qup-config"; 1979 status = "disabled"; 1980 }; 1981 1982 i2c14: i2c@a98000 { 1983 compatible = "qcom,geni-i2c"; 1984 reg = <0 0x00a98000 0 0x4000>; 1985 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1986 clock-names = "se"; 1987 pinctrl-names = "default"; 1988 pinctrl-0 = <&qup_i2c14_data_clk>; 1989 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1990 #address-cells = <1>; 1991 #size-cells = <0>; 1992 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1993 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1994 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1995 interconnect-names = "qup-core", "qup-config", 1996 "qup-memory"; 1997 power-domains = <&rpmhpd SC7280_CX>; 1998 required-opps = <&rpmhpd_opp_low_svs>; 1999 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2000 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2001 dma-names = "tx", "rx"; 2002 status = "disabled"; 2003 }; 2004 2005 spi14: spi@a98000 { 2006 compatible = "qcom,geni-spi"; 2007 reg = <0 0x00a98000 0 0x4000>; 2008 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2009 clock-names = "se"; 2010 pinctrl-names = "default"; 2011 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2012 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2013 #address-cells = <1>; 2014 #size-cells = <0>; 2015 power-domains = <&rpmhpd SC7280_CX>; 2016 operating-points-v2 = <&qup_opp_table>; 2017 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2018 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2019 interconnect-names = "qup-core", "qup-config"; 2020 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2021 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2022 dma-names = "tx", "rx"; 2023 status = "disabled"; 2024 }; 2025 2026 uart14: serial@a98000 { 2027 compatible = "qcom,geni-uart"; 2028 reg = <0 0x00a98000 0 0x4000>; 2029 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2030 clock-names = "se"; 2031 pinctrl-names = "default"; 2032 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 2033 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2034 power-domains = <&rpmhpd SC7280_CX>; 2035 operating-points-v2 = <&qup_opp_table>; 2036 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2037 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2038 interconnect-names = "qup-core", "qup-config"; 2039 status = "disabled"; 2040 }; 2041 2042 i2c15: i2c@a9c000 { 2043 compatible = "qcom,geni-i2c"; 2044 reg = <0 0x00a9c000 0 0x4000>; 2045 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2046 clock-names = "se"; 2047 pinctrl-names = "default"; 2048 pinctrl-0 = <&qup_i2c15_data_clk>; 2049 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2050 #address-cells = <1>; 2051 #size-cells = <0>; 2052 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2053 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 2054 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2055 interconnect-names = "qup-core", "qup-config", 2056 "qup-memory"; 2057 power-domains = <&rpmhpd SC7280_CX>; 2058 required-opps = <&rpmhpd_opp_low_svs>; 2059 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2060 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2061 dma-names = "tx", "rx"; 2062 status = "disabled"; 2063 }; 2064 2065 spi15: spi@a9c000 { 2066 compatible = "qcom,geni-spi"; 2067 reg = <0 0x00a9c000 0 0x4000>; 2068 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2069 clock-names = "se"; 2070 pinctrl-names = "default"; 2071 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2072 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2073 #address-cells = <1>; 2074 #size-cells = <0>; 2075 power-domains = <&rpmhpd SC7280_CX>; 2076 operating-points-v2 = <&qup_opp_table>; 2077 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2078 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2079 interconnect-names = "qup-core", "qup-config"; 2080 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2081 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2082 dma-names = "tx", "rx"; 2083 status = "disabled"; 2084 }; 2085 2086 uart15: serial@a9c000 { 2087 compatible = "qcom,geni-uart"; 2088 reg = <0 0x00a9c000 0 0x4000>; 2089 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2090 clock-names = "se"; 2091 pinctrl-names = "default"; 2092 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 2093 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2094 power-domains = <&rpmhpd SC7280_CX>; 2095 operating-points-v2 = <&qup_opp_table>; 2096 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2097 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2098 interconnect-names = "qup-core", "qup-config"; 2099 status = "disabled"; 2100 }; 2101 }; 2102 2103 rng: rng@10d3000 { 2104 compatible = "qcom,sc7280-trng", "qcom,trng"; 2105 reg = <0 0x010d3000 0 0x1000>; 2106 }; 2107 2108 cnoc2: interconnect@1500000 { 2109 reg = <0 0x01500000 0 0x1000>; 2110 compatible = "qcom,sc7280-cnoc2"; 2111 #interconnect-cells = <2>; 2112 qcom,bcm-voters = <&apps_bcm_voter>; 2113 }; 2114 2115 cnoc3: interconnect@1502000 { 2116 reg = <0 0x01502000 0 0x1000>; 2117 compatible = "qcom,sc7280-cnoc3"; 2118 #interconnect-cells = <2>; 2119 qcom,bcm-voters = <&apps_bcm_voter>; 2120 }; 2121 2122 mc_virt: interconnect@1580000 { 2123 reg = <0 0x01580000 0 0x4>; 2124 compatible = "qcom,sc7280-mc-virt"; 2125 #interconnect-cells = <2>; 2126 qcom,bcm-voters = <&apps_bcm_voter>; 2127 }; 2128 2129 system_noc: interconnect@1680000 { 2130 reg = <0 0x01680000 0 0x15480>; 2131 compatible = "qcom,sc7280-system-noc"; 2132 #interconnect-cells = <2>; 2133 qcom,bcm-voters = <&apps_bcm_voter>; 2134 }; 2135 2136 aggre1_noc: interconnect@16e0000 { 2137 compatible = "qcom,sc7280-aggre1-noc"; 2138 reg = <0 0x016e0000 0 0x1c080>; 2139 #interconnect-cells = <2>; 2140 qcom,bcm-voters = <&apps_bcm_voter>; 2141 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2142 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2143 }; 2144 2145 aggre2_noc: interconnect@1700000 { 2146 reg = <0 0x01700000 0 0x2b080>; 2147 compatible = "qcom,sc7280-aggre2-noc"; 2148 #interconnect-cells = <2>; 2149 qcom,bcm-voters = <&apps_bcm_voter>; 2150 clocks = <&rpmhcc RPMH_IPA_CLK>; 2151 }; 2152 2153 mmss_noc: interconnect@1740000 { 2154 reg = <0 0x01740000 0 0x1e080>; 2155 compatible = "qcom,sc7280-mmss-noc"; 2156 #interconnect-cells = <2>; 2157 qcom,bcm-voters = <&apps_bcm_voter>; 2158 }; 2159 2160 wifi: wifi@17a10040 { 2161 compatible = "qcom,wcn6750-wifi"; 2162 reg = <0 0x17a10040 0 0x0>; 2163 iommus = <&apps_smmu 0x1c00 0x1>; 2164 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2165 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2166 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2167 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2168 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2169 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2170 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2171 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2172 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2173 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2174 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2175 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2176 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2177 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2178 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2179 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2180 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2181 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2182 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2183 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2184 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2185 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2186 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2187 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2188 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2189 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2190 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2191 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2192 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2193 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2194 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2195 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2196 qcom,rproc = <&remoteproc_wpss>; 2197 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2198 status = "disabled"; 2199 qcom,smem-states = <&wlan_smp2p_out 0>; 2200 qcom,smem-state-names = "wlan-smp2p-out"; 2201 }; 2202 2203 pcie1: pcie@1c08000 { 2204 compatible = "qcom,pcie-sc7280"; 2205 reg = <0 0x01c08000 0 0x3000>, 2206 <0 0x40000000 0 0xf1d>, 2207 <0 0x40000f20 0 0xa8>, 2208 <0 0x40001000 0 0x1000>, 2209 <0 0x40100000 0 0x100000>; 2210 2211 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2212 device_type = "pci"; 2213 linux,pci-domain = <1>; 2214 bus-range = <0x00 0xff>; 2215 num-lanes = <2>; 2216 2217 #address-cells = <3>; 2218 #size-cells = <2>; 2219 2220 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2221 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2222 2223 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2224 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2228 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2229 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2230 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2231 interrupt-names = "msi0", "msi1", "msi2", "msi3", 2232 "msi4", "msi5", "msi6", "msi7"; 2233 #interrupt-cells = <1>; 2234 interrupt-map-mask = <0 0 0 0x7>; 2235 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2236 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2237 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2238 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2239 2240 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2241 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2242 <&pcie1_phy>, 2243 <&rpmhcc RPMH_CXO_CLK>, 2244 <&gcc GCC_PCIE_1_AUX_CLK>, 2245 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2246 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2247 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2248 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2249 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2250 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2251 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2252 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2253 2254 clock-names = "pipe", 2255 "pipe_mux", 2256 "phy_pipe", 2257 "ref", 2258 "aux", 2259 "cfg", 2260 "bus_master", 2261 "bus_slave", 2262 "slave_q2a", 2263 "tbu", 2264 "ddrss_sf_tbu", 2265 "aggre0", 2266 "aggre1"; 2267 2268 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2269 assigned-clock-rates = <19200000>; 2270 2271 resets = <&gcc GCC_PCIE_1_BCR>; 2272 reset-names = "pci"; 2273 2274 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2275 2276 phys = <&pcie1_phy>; 2277 phy-names = "pciephy"; 2278 2279 pinctrl-names = "default"; 2280 pinctrl-0 = <&pcie1_clkreq_n>; 2281 2282 dma-coherent; 2283 2284 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2285 <0x100 &apps_smmu 0x1c81 0x1>; 2286 2287 status = "disabled"; 2288 2289 pcie@0 { 2290 device_type = "pci"; 2291 reg = <0x0 0x0 0x0 0x0 0x0>; 2292 bus-range = <0x01 0xff>; 2293 2294 #address-cells = <3>; 2295 #size-cells = <2>; 2296 ranges; 2297 }; 2298 }; 2299 2300 pcie1_phy: phy@1c0e000 { 2301 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2302 reg = <0 0x01c0e000 0 0x1000>; 2303 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2304 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2305 <&gcc GCC_PCIE_CLKREF_EN>, 2306 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 2307 <&gcc GCC_PCIE_1_PIPE_CLK>; 2308 clock-names = "aux", 2309 "cfg_ahb", 2310 "ref", 2311 "refgen", 2312 "pipe"; 2313 2314 clock-output-names = "pcie_1_pipe_clk"; 2315 #clock-cells = <0>; 2316 2317 #phy-cells = <0>; 2318 2319 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2320 reset-names = "phy"; 2321 2322 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2323 assigned-clock-rates = <100000000>; 2324 2325 status = "disabled"; 2326 }; 2327 2328 ufs_mem_hc: ufshc@1d84000 { 2329 compatible = "qcom,sc7280-ufshc", "qcom,ufshc", 2330 "jedec,ufs-2.0"; 2331 reg = <0x0 0x01d84000 0x0 0x3000>; 2332 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2333 phys = <&ufs_mem_phy>; 2334 phy-names = "ufsphy"; 2335 lanes-per-direction = <2>; 2336 #reset-cells = <1>; 2337 resets = <&gcc GCC_UFS_PHY_BCR>; 2338 reset-names = "rst"; 2339 2340 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2341 required-opps = <&rpmhpd_opp_nom>; 2342 2343 iommus = <&apps_smmu 0x80 0x0>; 2344 dma-coherent; 2345 2346 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2347 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2348 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2349 &cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2350 interconnect-names = "ufs-ddr", "cpu-ufs"; 2351 2352 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2353 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2354 <&gcc GCC_UFS_PHY_AHB_CLK>, 2355 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2356 <&rpmhcc RPMH_CXO_CLK>, 2357 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2358 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2359 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2360 clock-names = "core_clk", 2361 "bus_aggr_clk", 2362 "iface_clk", 2363 "core_clk_unipro", 2364 "ref_clk", 2365 "tx_lane0_sync_clk", 2366 "rx_lane0_sync_clk", 2367 "rx_lane1_sync_clk"; 2368 2369 operating-points-v2 = <&ufs_opp_table>; 2370 2371 qcom,ice = <&ice>; 2372 2373 status = "disabled"; 2374 2375 ufs_opp_table: opp-table { 2376 compatible = "operating-points-v2"; 2377 2378 opp-75000000 { 2379 opp-hz = /bits/ 64 <75000000>, 2380 /bits/ 64 <0>, 2381 /bits/ 64 <0>, 2382 /bits/ 64 <75000000>, 2383 /bits/ 64 <0>, 2384 /bits/ 64 <0>, 2385 /bits/ 64 <0>, 2386 /bits/ 64 <0>; 2387 required-opps = <&rpmhpd_opp_low_svs>; 2388 }; 2389 2390 opp-150000000 { 2391 opp-hz = /bits/ 64 <150000000>, 2392 /bits/ 64 <0>, 2393 /bits/ 64 <0>, 2394 /bits/ 64 <150000000>, 2395 /bits/ 64 <0>, 2396 /bits/ 64 <0>, 2397 /bits/ 64 <0>, 2398 /bits/ 64 <0>; 2399 required-opps = <&rpmhpd_opp_svs>; 2400 }; 2401 2402 opp-300000000 { 2403 opp-hz = /bits/ 64 <300000000>, 2404 /bits/ 64 <0>, 2405 /bits/ 64 <0>, 2406 /bits/ 64 <300000000>, 2407 /bits/ 64 <0>, 2408 /bits/ 64 <0>, 2409 /bits/ 64 <0>, 2410 /bits/ 64 <0>; 2411 required-opps = <&rpmhpd_opp_nom>; 2412 }; 2413 }; 2414 }; 2415 2416 ufs_mem_phy: phy@1d87000 { 2417 compatible = "qcom,sc7280-qmp-ufs-phy"; 2418 reg = <0x0 0x01d87000 0x0 0xe00>; 2419 clocks = <&rpmhcc RPMH_CXO_CLK>, 2420 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2421 <&gcc GCC_UFS_1_CLKREF_EN>; 2422 clock-names = "ref", "ref_aux", "qref"; 2423 2424 power-domains = <&rpmhpd SC7280_MX>; 2425 2426 resets = <&ufs_mem_hc 0>; 2427 reset-names = "ufsphy"; 2428 2429 #clock-cells = <1>; 2430 #phy-cells = <0>; 2431 2432 status = "disabled"; 2433 }; 2434 2435 ice: crypto@1d88000 { 2436 compatible = "qcom,sc7280-inline-crypto-engine", 2437 "qcom,inline-crypto-engine"; 2438 reg = <0 0x01d88000 0 0x8000>; 2439 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2440 }; 2441 2442 cryptobam: dma-controller@1dc4000 { 2443 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2444 reg = <0x0 0x01dc4000 0x0 0x28000>; 2445 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2446 #dma-cells = <1>; 2447 iommus = <&apps_smmu 0x4e4 0x0011>, 2448 <&apps_smmu 0x4e6 0x0011>; 2449 qcom,ee = <0>; 2450 qcom,controlled-remotely; 2451 num-channels = <16>; 2452 qcom,num-ees = <4>; 2453 }; 2454 2455 crypto: crypto@1dfa000 { 2456 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce"; 2457 reg = <0x0 0x01dfa000 0x0 0x6000>; 2458 dmas = <&cryptobam 4>, <&cryptobam 5>; 2459 dma-names = "rx", "tx"; 2460 iommus = <&apps_smmu 0x4e4 0x0011>, 2461 <&apps_smmu 0x4e4 0x0011>; 2462 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 2463 interconnect-names = "memory"; 2464 }; 2465 2466 ipa: ipa@1e40000 { 2467 compatible = "qcom,sc7280-ipa"; 2468 2469 iommus = <&apps_smmu 0x480 0x0>, 2470 <&apps_smmu 0x482 0x0>; 2471 reg = <0 0x01e40000 0 0x8000>, 2472 <0 0x01e50000 0 0x4ad0>, 2473 <0 0x01e04000 0 0x23000>; 2474 reg-names = "ipa-reg", 2475 "ipa-shared", 2476 "gsi"; 2477 2478 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2479 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2480 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2481 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2482 interrupt-names = "ipa", 2483 "gsi", 2484 "ipa-clock-query", 2485 "ipa-setup-ready"; 2486 2487 clocks = <&rpmhcc RPMH_IPA_CLK>; 2488 clock-names = "core"; 2489 2490 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2491 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2492 interconnect-names = "memory", 2493 "config"; 2494 2495 qcom,qmp = <&aoss_qmp>; 2496 2497 qcom,smem-states = <&ipa_smp2p_out 0>, 2498 <&ipa_smp2p_out 1>; 2499 qcom,smem-state-names = "ipa-clock-enabled-valid", 2500 "ipa-clock-enabled"; 2501 2502 status = "disabled"; 2503 }; 2504 2505 tcsr_mutex: hwlock@1f40000 { 2506 compatible = "qcom,tcsr-mutex"; 2507 reg = <0 0x01f40000 0 0x20000>; 2508 #hwlock-cells = <1>; 2509 }; 2510 2511 tcsr_1: syscon@1f60000 { 2512 compatible = "qcom,sc7280-tcsr", "syscon"; 2513 reg = <0 0x01f60000 0 0x20000>; 2514 }; 2515 2516 tcsr_2: syscon@1fc0000 { 2517 compatible = "qcom,sc7280-tcsr", "syscon"; 2518 reg = <0 0x01fc0000 0 0x30000>; 2519 }; 2520 2521 lpasscc: lpasscc@3000000 { 2522 compatible = "qcom,sc7280-lpasscc"; 2523 reg = <0 0x03000000 0 0x40>, 2524 <0 0x03c04000 0 0x4>; 2525 reg-names = "qdsp6ss", "top_cc"; 2526 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2527 clock-names = "iface"; 2528 #clock-cells = <1>; 2529 status = "reserved"; /* Owned by ADSP firmware */ 2530 }; 2531 2532 lpass_rx_macro: codec@3200000 { 2533 compatible = "qcom,sc7280-lpass-rx-macro"; 2534 reg = <0 0x03200000 0 0x1000>; 2535 2536 pinctrl-names = "default"; 2537 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2538 2539 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2540 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2541 <&lpass_va_macro>; 2542 clock-names = "mclk", "npl", "fsgen"; 2543 2544 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2545 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2546 power-domain-names = "macro", "dcodec"; 2547 2548 #clock-cells = <0>; 2549 #sound-dai-cells = <1>; 2550 2551 status = "disabled"; 2552 }; 2553 2554 swr0: soundwire@3210000 { 2555 compatible = "qcom,soundwire-v1.6.0"; 2556 reg = <0 0x03210000 0 0x2000>; 2557 2558 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2559 clocks = <&lpass_rx_macro>; 2560 clock-names = "iface"; 2561 2562 qcom,din-ports = <0>; 2563 qcom,dout-ports = <5>; 2564 2565 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2566 reset-names = "swr_audio_cgcr"; 2567 2568 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2569 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2570 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2571 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2572 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2573 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2574 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2575 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2576 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2577 2578 #sound-dai-cells = <1>; 2579 #address-cells = <2>; 2580 #size-cells = <0>; 2581 2582 status = "disabled"; 2583 }; 2584 2585 lpass_tx_macro: codec@3220000 { 2586 compatible = "qcom,sc7280-lpass-tx-macro"; 2587 reg = <0 0x03220000 0 0x1000>; 2588 2589 pinctrl-names = "default"; 2590 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2591 2592 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2593 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2594 <&lpass_va_macro>; 2595 clock-names = "mclk", "npl", "fsgen"; 2596 2597 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2598 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2599 power-domain-names = "macro", "dcodec"; 2600 2601 #clock-cells = <0>; 2602 #sound-dai-cells = <1>; 2603 2604 status = "disabled"; 2605 }; 2606 2607 swr1: soundwire@3230000 { 2608 compatible = "qcom,soundwire-v1.6.0"; 2609 reg = <0 0x03230000 0 0x2000>; 2610 2611 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2612 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2613 clocks = <&lpass_tx_macro>; 2614 clock-names = "iface"; 2615 2616 qcom,din-ports = <3>; 2617 qcom,dout-ports = <0>; 2618 2619 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2620 reset-names = "swr_audio_cgcr"; 2621 2622 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2623 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2624 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2625 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2626 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2627 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2628 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2629 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2630 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2631 2632 #sound-dai-cells = <1>; 2633 #address-cells = <2>; 2634 #size-cells = <0>; 2635 2636 status = "disabled"; 2637 }; 2638 2639 lpass_audiocc: clock-controller@3300000 { 2640 compatible = "qcom,sc7280-lpassaudiocc"; 2641 reg = <0 0x03300000 0 0x30000>, 2642 <0 0x032a9000 0 0x1000>; 2643 clocks = <&rpmhcc RPMH_CXO_CLK>, 2644 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2645 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2646 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2647 #clock-cells = <1>; 2648 #power-domain-cells = <1>; 2649 #reset-cells = <1>; 2650 }; 2651 2652 lpass_va_macro: codec@3370000 { 2653 compatible = "qcom,sc7280-lpass-va-macro"; 2654 reg = <0 0x03370000 0 0x1000>; 2655 2656 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2657 clock-names = "mclk"; 2658 2659 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2660 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2661 power-domain-names = "macro", "dcodec"; 2662 2663 #clock-cells = <0>; 2664 #sound-dai-cells = <1>; 2665 2666 status = "disabled"; 2667 }; 2668 2669 lpass_aon: clock-controller@3380000 { 2670 compatible = "qcom,sc7280-lpassaoncc"; 2671 reg = <0 0x03380000 0 0x30000>; 2672 clocks = <&rpmhcc RPMH_CXO_CLK>, 2673 <&rpmhcc RPMH_CXO_CLK_A>, 2674 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2675 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2676 #clock-cells = <1>; 2677 #power-domain-cells = <1>; 2678 status = "reserved"; /* Owned by ADSP firmware */ 2679 }; 2680 2681 lpass_core: clock-controller@3900000 { 2682 compatible = "qcom,sc7280-lpasscorecc"; 2683 reg = <0 0x03900000 0 0x50000>; 2684 clocks = <&rpmhcc RPMH_CXO_CLK>; 2685 clock-names = "bi_tcxo"; 2686 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2687 #clock-cells = <1>; 2688 #power-domain-cells = <1>; 2689 status = "reserved"; /* Owned by ADSP firmware */ 2690 }; 2691 2692 lpass_cpu: audio@3987000 { 2693 compatible = "qcom,sc7280-lpass-cpu"; 2694 2695 reg = <0 0x03987000 0 0x68000>, 2696 <0 0x03b00000 0 0x29000>, 2697 <0 0x03260000 0 0xc000>, 2698 <0 0x03280000 0 0x29000>, 2699 <0 0x03340000 0 0x29000>, 2700 <0 0x0336c000 0 0x3000>; 2701 reg-names = "lpass-hdmiif", 2702 "lpass-lpaif", 2703 "lpass-rxtx-cdc-dma-lpm", 2704 "lpass-rxtx-lpaif", 2705 "lpass-va-lpaif", 2706 "lpass-va-cdc-dma-lpm"; 2707 2708 iommus = <&apps_smmu 0x1820 0>, 2709 <&apps_smmu 0x1821 0>, 2710 <&apps_smmu 0x1832 0>; 2711 2712 power-domains = <&rpmhpd SC7280_LCX>; 2713 power-domain-names = "lcx"; 2714 required-opps = <&rpmhpd_opp_nom>; 2715 2716 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2717 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2718 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2719 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2720 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2721 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2722 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2723 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2724 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2725 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2726 clock-names = "aon_cc_audio_hm_h", 2727 "audio_cc_ext_mclk0", 2728 "core_cc_sysnoc_mport_core", 2729 "core_cc_ext_if0_ibit", 2730 "core_cc_ext_if1_ibit", 2731 "audio_cc_codec_mem", 2732 "audio_cc_codec_mem0", 2733 "audio_cc_codec_mem1", 2734 "audio_cc_codec_mem2", 2735 "aon_cc_va_mem0"; 2736 2737 #sound-dai-cells = <1>; 2738 #address-cells = <1>; 2739 #size-cells = <0>; 2740 2741 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2742 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2743 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2744 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2745 interrupt-names = "lpass-irq-lpaif", 2746 "lpass-irq-hdmi", 2747 "lpass-irq-vaif", 2748 "lpass-irq-rxtxif"; 2749 2750 status = "disabled"; 2751 }; 2752 2753 slimbam: dma-controller@3a84000 { 2754 compatible = "qcom,bam-v1.7.0"; 2755 reg = <0 0x03a84000 0 0x20000>; 2756 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 2757 #dma-cells = <1>; 2758 qcom,controlled-remotely; 2759 num-channels = <31>; 2760 qcom,ee = <1>; 2761 qcom,num-ees = <2>; 2762 iommus = <&apps_smmu 0x1826 0x0>; 2763 status = "disabled"; 2764 }; 2765 2766 slim: slim-ngd@3ac0000 { 2767 compatible = "qcom,slim-ngd-v1.5.0"; 2768 reg = <0 0x03ac0000 0 0x2c000>; 2769 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 2770 dmas = <&slimbam 3>, <&slimbam 4>; 2771 dma-names = "rx", "tx"; 2772 iommus = <&apps_smmu 0x1826 0x0>; 2773 #address-cells = <1>; 2774 #size-cells = <0>; 2775 status = "disabled"; 2776 }; 2777 2778 lpass_hm: clock-controller@3c00000 { 2779 compatible = "qcom,sc7280-lpasshm"; 2780 reg = <0 0x03c00000 0 0x28>; 2781 clocks = <&rpmhcc RPMH_CXO_CLK>; 2782 clock-names = "bi_tcxo"; 2783 #clock-cells = <1>; 2784 #power-domain-cells = <1>; 2785 status = "reserved"; /* Owned by ADSP firmware */ 2786 }; 2787 2788 lpass_ag_noc: interconnect@3c40000 { 2789 reg = <0 0x03c40000 0 0xf080>; 2790 compatible = "qcom,sc7280-lpass-ag-noc"; 2791 #interconnect-cells = <2>; 2792 qcom,bcm-voters = <&apps_bcm_voter>; 2793 }; 2794 2795 lpass_tlmm: pinctrl@33c0000 { 2796 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2797 reg = <0 0x033c0000 0x0 0x20000>, 2798 <0 0x03550000 0x0 0x10000>; 2799 gpio-controller; 2800 #gpio-cells = <2>; 2801 gpio-ranges = <&lpass_tlmm 0 0 15>; 2802 2803 lpass_dmic01_clk: dmic01-clk-state { 2804 pins = "gpio6"; 2805 function = "dmic1_clk"; 2806 }; 2807 2808 lpass_dmic01_data: dmic01-data-state { 2809 pins = "gpio7"; 2810 function = "dmic1_data"; 2811 }; 2812 2813 lpass_dmic23_clk: dmic23-clk-state { 2814 pins = "gpio8"; 2815 function = "dmic2_clk"; 2816 }; 2817 2818 lpass_dmic23_data: dmic23-data-state { 2819 pins = "gpio9"; 2820 function = "dmic2_data"; 2821 }; 2822 2823 lpass_rx_swr_clk: rx-swr-clk-state { 2824 pins = "gpio3"; 2825 function = "swr_rx_clk"; 2826 }; 2827 2828 lpass_rx_swr_data: rx-swr-data-state { 2829 pins = "gpio4", "gpio5"; 2830 function = "swr_rx_data"; 2831 }; 2832 2833 lpass_tx_swr_clk: tx-swr-clk-state { 2834 pins = "gpio0"; 2835 function = "swr_tx_clk"; 2836 }; 2837 2838 lpass_tx_swr_data: tx-swr-data-state { 2839 pins = "gpio1", "gpio2", "gpio14"; 2840 function = "swr_tx_data"; 2841 }; 2842 }; 2843 2844 gpu: gpu@3d00000 { 2845 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2846 reg = <0 0x03d00000 0 0x40000>, 2847 <0 0x03d9e000 0 0x1000>, 2848 <0 0x03d61000 0 0x800>; 2849 reg-names = "kgsl_3d0_reg_memory", 2850 "cx_mem", 2851 "cx_dbgc"; 2852 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2853 iommus = <&adreno_smmu 0 0x400>, 2854 <&adreno_smmu 1 0x400>; 2855 operating-points-v2 = <&gpu_opp_table>; 2856 qcom,gmu = <&gmu>; 2857 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2858 interconnect-names = "gfx-mem"; 2859 #cooling-cells = <2>; 2860 2861 nvmem-cells = <&gpu_speed_bin>; 2862 nvmem-cell-names = "speed_bin"; 2863 2864 status = "disabled"; 2865 2866 gpu_zap_shader: zap-shader { 2867 memory-region = <&gpu_zap_mem>; 2868 }; 2869 2870 gpu_opp_table: opp-table { 2871 compatible = "operating-points-v2"; 2872 2873 opp-315000000 { 2874 opp-hz = /bits/ 64 <315000000>; 2875 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2876 opp-peak-kBps = <1804000>; 2877 opp-supported-hw = <0x17>; 2878 }; 2879 2880 opp-450000000 { 2881 opp-hz = /bits/ 64 <450000000>; 2882 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2883 opp-peak-kBps = <4068000>; 2884 opp-supported-hw = <0x17>; 2885 }; 2886 2887 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2888 opp-550000000-0 { 2889 opp-hz = /bits/ 64 <550000000>; 2890 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2891 opp-peak-kBps = <8368000>; 2892 opp-supported-hw = <0x01>; 2893 }; 2894 2895 opp-550000000-1 { 2896 opp-hz = /bits/ 64 <550000000>; 2897 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2898 opp-peak-kBps = <6832000>; 2899 opp-supported-hw = <0x16>; 2900 }; 2901 2902 opp-608000000 { 2903 opp-hz = /bits/ 64 <608000000>; 2904 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2905 opp-peak-kBps = <8368000>; 2906 opp-supported-hw = <0x16>; 2907 }; 2908 2909 opp-700000000 { 2910 opp-hz = /bits/ 64 <700000000>; 2911 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2912 opp-peak-kBps = <8532000>; 2913 opp-supported-hw = <0x06>; 2914 }; 2915 2916 opp-812000000 { 2917 opp-hz = /bits/ 64 <812000000>; 2918 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2919 opp-peak-kBps = <8532000>; 2920 opp-supported-hw = <0x06>; 2921 }; 2922 2923 opp-840000000 { 2924 opp-hz = /bits/ 64 <840000000>; 2925 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2926 opp-peak-kBps = <8532000>; 2927 opp-supported-hw = <0x02>; 2928 }; 2929 2930 opp-900000000 { 2931 opp-hz = /bits/ 64 <900000000>; 2932 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2933 opp-peak-kBps = <8532000>; 2934 opp-supported-hw = <0x02>; 2935 }; 2936 }; 2937 }; 2938 2939 gmu: gmu@3d6a000 { 2940 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2941 reg = <0 0x03d6a000 0 0x34000>, 2942 <0 0x3de0000 0 0x10000>, 2943 <0 0x0b290000 0 0x10000>; 2944 reg-names = "gmu", "rscc", "gmu_pdc"; 2945 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2946 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2947 interrupt-names = "hfi", "gmu"; 2948 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2949 <&gpucc GPU_CC_CXO_CLK>, 2950 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2951 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2952 <&gpucc GPU_CC_AHB_CLK>, 2953 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2954 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2955 clock-names = "gmu", 2956 "cxo", 2957 "axi", 2958 "memnoc", 2959 "ahb", 2960 "hub", 2961 "smmu_vote"; 2962 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2963 <&gpucc GPU_CC_GX_GDSC>; 2964 power-domain-names = "cx", 2965 "gx"; 2966 iommus = <&adreno_smmu 5 0x400>; 2967 operating-points-v2 = <&gmu_opp_table>; 2968 2969 gmu_opp_table: opp-table { 2970 compatible = "operating-points-v2"; 2971 2972 opp-200000000 { 2973 opp-hz = /bits/ 64 <200000000>; 2974 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2975 }; 2976 }; 2977 }; 2978 2979 gpucc: clock-controller@3d90000 { 2980 compatible = "qcom,sc7280-gpucc"; 2981 reg = <0 0x03d90000 0 0x9000>; 2982 clocks = <&rpmhcc RPMH_CXO_CLK>, 2983 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2984 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2985 clock-names = "bi_tcxo", 2986 "gcc_gpu_gpll0_clk_src", 2987 "gcc_gpu_gpll0_div_clk_src"; 2988 #clock-cells = <1>; 2989 #reset-cells = <1>; 2990 #power-domain-cells = <1>; 2991 }; 2992 2993 dma@117f000 { 2994 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2995 reg = <0x0 0x0117f000 0x0 0x1000>, 2996 <0x0 0x01112000 0x0 0x6000>; 2997 }; 2998 2999 adreno_smmu: iommu@3da0000 { 3000 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 3001 "qcom,smmu-500", "arm,mmu-500"; 3002 reg = <0 0x03da0000 0 0x20000>; 3003 #iommu-cells = <2>; 3004 #global-interrupts = <2>; 3005 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3006 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 3007 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3008 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3009 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3010 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3011 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3012 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3013 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3014 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3015 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3016 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 3017 3018 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3019 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3020 <&gpucc GPU_CC_AHB_CLK>, 3021 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3022 <&gpucc GPU_CC_CX_GMU_CLK>, 3023 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3024 <&gpucc GPU_CC_HUB_AON_CLK>; 3025 clock-names = "gcc_gpu_memnoc_gfx_clk", 3026 "gcc_gpu_snoc_dvm_gfx_clk", 3027 "gpu_cc_ahb_clk", 3028 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3029 "gpu_cc_cx_gmu_clk", 3030 "gpu_cc_hub_cx_int_clk", 3031 "gpu_cc_hub_aon_clk"; 3032 3033 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3034 dma-coherent; 3035 }; 3036 3037 gfx_0_tbu: tbu@3dd9000 { 3038 compatible = "qcom,sc7280-tbu"; 3039 reg = <0x0 0x3dd9000 0x0 0x1000>; 3040 qcom,stream-id-range = <&adreno_smmu 0x0 0x400>; 3041 }; 3042 3043 gfx_1_tbu: tbu@3ddd000 { 3044 compatible = "qcom,sc7280-tbu"; 3045 reg = <0x0 0x3ddd000 0x0 0x1000>; 3046 qcom,stream-id-range = <&adreno_smmu 0x400 0x400>; 3047 }; 3048 3049 remoteproc_mpss: remoteproc@4080000 { 3050 compatible = "qcom,sc7280-mpss-pas"; 3051 reg = <0 0x04080000 0 0x10000>; 3052 3053 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 3054 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3055 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3056 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3057 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3058 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3059 interrupt-names = "wdog", "fatal", "ready", "handover", 3060 "stop-ack", "shutdown-ack"; 3061 3062 clocks = <&rpmhcc RPMH_CXO_CLK>; 3063 clock-names = "xo"; 3064 3065 power-domains = <&rpmhpd SC7280_CX>, 3066 <&rpmhpd SC7280_MSS>; 3067 power-domain-names = "cx", "mss"; 3068 3069 memory-region = <&mpss_mem>; 3070 3071 qcom,qmp = <&aoss_qmp>; 3072 3073 qcom,smem-states = <&modem_smp2p_out 0>; 3074 qcom,smem-state-names = "stop"; 3075 3076 status = "disabled"; 3077 3078 glink-edge { 3079 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 3080 IPCC_MPROC_SIGNAL_GLINK_QMP 3081 IRQ_TYPE_EDGE_RISING>; 3082 mboxes = <&ipcc IPCC_CLIENT_MPSS 3083 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3084 label = "modem"; 3085 qcom,remote-pid = <1>; 3086 }; 3087 }; 3088 3089 stm@6002000 { 3090 compatible = "arm,coresight-stm", "arm,primecell"; 3091 reg = <0 0x06002000 0 0x1000>, 3092 <0 0x16280000 0 0x180000>; 3093 reg-names = "stm-base", "stm-stimulus-base"; 3094 3095 clocks = <&aoss_qmp>; 3096 clock-names = "apb_pclk"; 3097 3098 out-ports { 3099 port { 3100 stm_out: endpoint { 3101 remote-endpoint = <&funnel0_in7>; 3102 }; 3103 }; 3104 }; 3105 }; 3106 3107 funnel@6041000 { 3108 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3109 reg = <0 0x06041000 0 0x1000>; 3110 3111 clocks = <&aoss_qmp>; 3112 clock-names = "apb_pclk"; 3113 3114 out-ports { 3115 port { 3116 funnel0_out: endpoint { 3117 remote-endpoint = <&merge_funnel_in0>; 3118 }; 3119 }; 3120 }; 3121 3122 in-ports { 3123 #address-cells = <1>; 3124 #size-cells = <0>; 3125 3126 port@7 { 3127 reg = <7>; 3128 funnel0_in7: endpoint { 3129 remote-endpoint = <&stm_out>; 3130 }; 3131 }; 3132 }; 3133 }; 3134 3135 funnel@6042000 { 3136 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3137 reg = <0 0x06042000 0 0x1000>; 3138 3139 clocks = <&aoss_qmp>; 3140 clock-names = "apb_pclk"; 3141 3142 out-ports { 3143 port { 3144 funnel1_out: endpoint { 3145 remote-endpoint = <&merge_funnel_in1>; 3146 }; 3147 }; 3148 }; 3149 3150 in-ports { 3151 #address-cells = <1>; 3152 #size-cells = <0>; 3153 3154 port@4 { 3155 reg = <4>; 3156 funnel1_in4: endpoint { 3157 remote-endpoint = <&apss_merge_funnel_out>; 3158 }; 3159 }; 3160 }; 3161 }; 3162 3163 funnel@6045000 { 3164 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3165 reg = <0 0x06045000 0 0x1000>; 3166 3167 clocks = <&aoss_qmp>; 3168 clock-names = "apb_pclk"; 3169 3170 out-ports { 3171 port { 3172 merge_funnel_out: endpoint { 3173 remote-endpoint = <&swao_funnel_in>; 3174 }; 3175 }; 3176 }; 3177 3178 in-ports { 3179 #address-cells = <1>; 3180 #size-cells = <0>; 3181 3182 port@0 { 3183 reg = <0>; 3184 merge_funnel_in0: endpoint { 3185 remote-endpoint = <&funnel0_out>; 3186 }; 3187 }; 3188 3189 port@1 { 3190 reg = <1>; 3191 merge_funnel_in1: endpoint { 3192 remote-endpoint = <&funnel1_out>; 3193 }; 3194 }; 3195 }; 3196 }; 3197 3198 replicator@6046000 { 3199 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3200 reg = <0 0x06046000 0 0x1000>; 3201 3202 clocks = <&aoss_qmp>; 3203 clock-names = "apb_pclk"; 3204 3205 out-ports { 3206 port { 3207 replicator_out: endpoint { 3208 remote-endpoint = <&etr_in>; 3209 }; 3210 }; 3211 }; 3212 3213 in-ports { 3214 port { 3215 replicator_in: endpoint { 3216 remote-endpoint = <&swao_replicator_out>; 3217 }; 3218 }; 3219 }; 3220 }; 3221 3222 etr@6048000 { 3223 compatible = "arm,coresight-tmc", "arm,primecell"; 3224 reg = <0 0x06048000 0 0x1000>; 3225 iommus = <&apps_smmu 0x04c0 0>; 3226 3227 clocks = <&aoss_qmp>; 3228 clock-names = "apb_pclk"; 3229 arm,scatter-gather; 3230 3231 in-ports { 3232 port { 3233 etr_in: endpoint { 3234 remote-endpoint = <&replicator_out>; 3235 }; 3236 }; 3237 }; 3238 }; 3239 3240 funnel@6b04000 { 3241 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3242 reg = <0 0x06b04000 0 0x1000>; 3243 3244 clocks = <&aoss_qmp>; 3245 clock-names = "apb_pclk"; 3246 3247 out-ports { 3248 port { 3249 swao_funnel_out: endpoint { 3250 remote-endpoint = <&etf_in>; 3251 }; 3252 }; 3253 }; 3254 3255 in-ports { 3256 #address-cells = <1>; 3257 #size-cells = <0>; 3258 3259 port@7 { 3260 reg = <7>; 3261 swao_funnel_in: endpoint { 3262 remote-endpoint = <&merge_funnel_out>; 3263 }; 3264 }; 3265 }; 3266 }; 3267 3268 etf@6b05000 { 3269 compatible = "arm,coresight-tmc", "arm,primecell"; 3270 reg = <0 0x06b05000 0 0x1000>; 3271 3272 clocks = <&aoss_qmp>; 3273 clock-names = "apb_pclk"; 3274 3275 out-ports { 3276 port { 3277 etf_out: endpoint { 3278 remote-endpoint = <&swao_replicator_in>; 3279 }; 3280 }; 3281 }; 3282 3283 in-ports { 3284 port { 3285 etf_in: endpoint { 3286 remote-endpoint = <&swao_funnel_out>; 3287 }; 3288 }; 3289 }; 3290 }; 3291 3292 replicator@6b06000 { 3293 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3294 reg = <0 0x06b06000 0 0x1000>; 3295 3296 clocks = <&aoss_qmp>; 3297 clock-names = "apb_pclk"; 3298 qcom,replicator-loses-context; 3299 3300 out-ports { 3301 port { 3302 swao_replicator_out: endpoint { 3303 remote-endpoint = <&replicator_in>; 3304 }; 3305 }; 3306 }; 3307 3308 in-ports { 3309 port { 3310 swao_replicator_in: endpoint { 3311 remote-endpoint = <&etf_out>; 3312 }; 3313 }; 3314 }; 3315 }; 3316 3317 etm@7040000 { 3318 compatible = "arm,coresight-etm4x", "arm,primecell"; 3319 reg = <0 0x07040000 0 0x1000>; 3320 3321 cpu = <&cpu0>; 3322 3323 clocks = <&aoss_qmp>; 3324 clock-names = "apb_pclk"; 3325 arm,coresight-loses-context-with-cpu; 3326 qcom,skip-power-up; 3327 3328 out-ports { 3329 port { 3330 etm0_out: endpoint { 3331 remote-endpoint = <&apss_funnel_in0>; 3332 }; 3333 }; 3334 }; 3335 }; 3336 3337 etm@7140000 { 3338 compatible = "arm,coresight-etm4x", "arm,primecell"; 3339 reg = <0 0x07140000 0 0x1000>; 3340 3341 cpu = <&cpu1>; 3342 3343 clocks = <&aoss_qmp>; 3344 clock-names = "apb_pclk"; 3345 arm,coresight-loses-context-with-cpu; 3346 qcom,skip-power-up; 3347 3348 out-ports { 3349 port { 3350 etm1_out: endpoint { 3351 remote-endpoint = <&apss_funnel_in1>; 3352 }; 3353 }; 3354 }; 3355 }; 3356 3357 etm@7240000 { 3358 compatible = "arm,coresight-etm4x", "arm,primecell"; 3359 reg = <0 0x07240000 0 0x1000>; 3360 3361 cpu = <&cpu2>; 3362 3363 clocks = <&aoss_qmp>; 3364 clock-names = "apb_pclk"; 3365 arm,coresight-loses-context-with-cpu; 3366 qcom,skip-power-up; 3367 3368 out-ports { 3369 port { 3370 etm2_out: endpoint { 3371 remote-endpoint = <&apss_funnel_in2>; 3372 }; 3373 }; 3374 }; 3375 }; 3376 3377 etm@7340000 { 3378 compatible = "arm,coresight-etm4x", "arm,primecell"; 3379 reg = <0 0x07340000 0 0x1000>; 3380 3381 cpu = <&cpu3>; 3382 3383 clocks = <&aoss_qmp>; 3384 clock-names = "apb_pclk"; 3385 arm,coresight-loses-context-with-cpu; 3386 qcom,skip-power-up; 3387 3388 out-ports { 3389 port { 3390 etm3_out: endpoint { 3391 remote-endpoint = <&apss_funnel_in3>; 3392 }; 3393 }; 3394 }; 3395 }; 3396 3397 etm@7440000 { 3398 compatible = "arm,coresight-etm4x", "arm,primecell"; 3399 reg = <0 0x07440000 0 0x1000>; 3400 3401 cpu = <&cpu4>; 3402 3403 clocks = <&aoss_qmp>; 3404 clock-names = "apb_pclk"; 3405 arm,coresight-loses-context-with-cpu; 3406 qcom,skip-power-up; 3407 3408 out-ports { 3409 port { 3410 etm4_out: endpoint { 3411 remote-endpoint = <&apss_funnel_in4>; 3412 }; 3413 }; 3414 }; 3415 }; 3416 3417 etm@7540000 { 3418 compatible = "arm,coresight-etm4x", "arm,primecell"; 3419 reg = <0 0x07540000 0 0x1000>; 3420 3421 cpu = <&cpu5>; 3422 3423 clocks = <&aoss_qmp>; 3424 clock-names = "apb_pclk"; 3425 arm,coresight-loses-context-with-cpu; 3426 qcom,skip-power-up; 3427 3428 out-ports { 3429 port { 3430 etm5_out: endpoint { 3431 remote-endpoint = <&apss_funnel_in5>; 3432 }; 3433 }; 3434 }; 3435 }; 3436 3437 etm@7640000 { 3438 compatible = "arm,coresight-etm4x", "arm,primecell"; 3439 reg = <0 0x07640000 0 0x1000>; 3440 3441 cpu = <&cpu6>; 3442 3443 clocks = <&aoss_qmp>; 3444 clock-names = "apb_pclk"; 3445 arm,coresight-loses-context-with-cpu; 3446 qcom,skip-power-up; 3447 3448 out-ports { 3449 port { 3450 etm6_out: endpoint { 3451 remote-endpoint = <&apss_funnel_in6>; 3452 }; 3453 }; 3454 }; 3455 }; 3456 3457 etm@7740000 { 3458 compatible = "arm,coresight-etm4x", "arm,primecell"; 3459 reg = <0 0x07740000 0 0x1000>; 3460 3461 cpu = <&cpu7>; 3462 3463 clocks = <&aoss_qmp>; 3464 clock-names = "apb_pclk"; 3465 arm,coresight-loses-context-with-cpu; 3466 qcom,skip-power-up; 3467 3468 out-ports { 3469 port { 3470 etm7_out: endpoint { 3471 remote-endpoint = <&apss_funnel_in7>; 3472 }; 3473 }; 3474 }; 3475 }; 3476 3477 funnel@7800000 { /* APSS Funnel */ 3478 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3479 reg = <0 0x07800000 0 0x1000>; 3480 3481 clocks = <&aoss_qmp>; 3482 clock-names = "apb_pclk"; 3483 3484 out-ports { 3485 port { 3486 apss_funnel_out: endpoint { 3487 remote-endpoint = <&apss_merge_funnel_in>; 3488 }; 3489 }; 3490 }; 3491 3492 in-ports { 3493 #address-cells = <1>; 3494 #size-cells = <0>; 3495 3496 port@0 { 3497 reg = <0>; 3498 apss_funnel_in0: endpoint { 3499 remote-endpoint = <&etm0_out>; 3500 }; 3501 }; 3502 3503 port@1 { 3504 reg = <1>; 3505 apss_funnel_in1: endpoint { 3506 remote-endpoint = <&etm1_out>; 3507 }; 3508 }; 3509 3510 port@2 { 3511 reg = <2>; 3512 apss_funnel_in2: endpoint { 3513 remote-endpoint = <&etm2_out>; 3514 }; 3515 }; 3516 3517 port@3 { 3518 reg = <3>; 3519 apss_funnel_in3: endpoint { 3520 remote-endpoint = <&etm3_out>; 3521 }; 3522 }; 3523 3524 port@4 { 3525 reg = <4>; 3526 apss_funnel_in4: endpoint { 3527 remote-endpoint = <&etm4_out>; 3528 }; 3529 }; 3530 3531 port@5 { 3532 reg = <5>; 3533 apss_funnel_in5: endpoint { 3534 remote-endpoint = <&etm5_out>; 3535 }; 3536 }; 3537 3538 port@6 { 3539 reg = <6>; 3540 apss_funnel_in6: endpoint { 3541 remote-endpoint = <&etm6_out>; 3542 }; 3543 }; 3544 3545 port@7 { 3546 reg = <7>; 3547 apss_funnel_in7: endpoint { 3548 remote-endpoint = <&etm7_out>; 3549 }; 3550 }; 3551 }; 3552 }; 3553 3554 funnel@7810000 { 3555 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3556 reg = <0 0x07810000 0 0x1000>; 3557 3558 clocks = <&aoss_qmp>; 3559 clock-names = "apb_pclk"; 3560 3561 out-ports { 3562 port { 3563 apss_merge_funnel_out: endpoint { 3564 remote-endpoint = <&funnel1_in4>; 3565 }; 3566 }; 3567 }; 3568 3569 in-ports { 3570 port { 3571 apss_merge_funnel_in: endpoint { 3572 remote-endpoint = <&apss_funnel_out>; 3573 }; 3574 }; 3575 }; 3576 }; 3577 3578 sdhc_2: mmc@8804000 { 3579 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3580 pinctrl-names = "default", "sleep"; 3581 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3582 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3583 status = "disabled"; 3584 3585 reg = <0 0x08804000 0 0x1000>; 3586 3587 iommus = <&apps_smmu 0x100 0x0>; 3588 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3589 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3590 interrupt-names = "hc_irq", "pwr_irq"; 3591 3592 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3593 <&gcc GCC_SDCC2_APPS_CLK>, 3594 <&rpmhcc RPMH_CXO_CLK>; 3595 clock-names = "iface", "core", "xo"; 3596 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3597 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3598 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3599 power-domains = <&rpmhpd SC7280_CX>; 3600 operating-points-v2 = <&sdhc2_opp_table>; 3601 3602 bus-width = <4>; 3603 dma-coherent; 3604 3605 qcom,dll-config = <0x0007642c>; 3606 3607 resets = <&gcc GCC_SDCC2_BCR>; 3608 3609 sdhc2_opp_table: opp-table { 3610 compatible = "operating-points-v2"; 3611 3612 opp-100000000 { 3613 opp-hz = /bits/ 64 <100000000>; 3614 required-opps = <&rpmhpd_opp_low_svs>; 3615 opp-peak-kBps = <1800000 400000>; 3616 opp-avg-kBps = <100000 0>; 3617 }; 3618 3619 opp-202000000 { 3620 opp-hz = /bits/ 64 <202000000>; 3621 required-opps = <&rpmhpd_opp_nom>; 3622 opp-peak-kBps = <5400000 1600000>; 3623 opp-avg-kBps = <200000 0>; 3624 }; 3625 }; 3626 }; 3627 3628 usb_1_hsphy: phy@88e3000 { 3629 compatible = "qcom,sc7280-usb-hs-phy", 3630 "qcom,usb-snps-hs-7nm-phy"; 3631 reg = <0 0x088e3000 0 0x400>; 3632 status = "disabled"; 3633 #phy-cells = <0>; 3634 3635 clocks = <&rpmhcc RPMH_CXO_CLK>; 3636 clock-names = "ref"; 3637 3638 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3639 }; 3640 3641 usb_2_hsphy: phy@88e4000 { 3642 compatible = "qcom,sc7280-usb-hs-phy", 3643 "qcom,usb-snps-hs-7nm-phy"; 3644 reg = <0 0x088e4000 0 0x400>; 3645 status = "disabled"; 3646 #phy-cells = <0>; 3647 3648 clocks = <&rpmhcc RPMH_CXO_CLK>; 3649 clock-names = "ref"; 3650 3651 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3652 }; 3653 3654 usb_1_qmpphy: phy@88e8000 { 3655 compatible = "qcom,sc7280-qmp-usb3-dp-phy"; 3656 reg = <0 0x088e8000 0 0x3000>; 3657 status = "disabled"; 3658 3659 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3660 <&rpmhcc RPMH_CXO_CLK>, 3661 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3662 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3663 clock-names = "aux", 3664 "ref", 3665 "com_aux", 3666 "usb3_pipe"; 3667 3668 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3669 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3670 reset-names = "phy", "common"; 3671 3672 #clock-cells = <1>; 3673 #phy-cells = <1>; 3674 3675 orientation-switch; 3676 3677 ports { 3678 #address-cells = <1>; 3679 #size-cells = <0>; 3680 3681 port@0 { 3682 reg = <0>; 3683 3684 usb_dp_qmpphy_out: endpoint { 3685 }; 3686 }; 3687 3688 port@1 { 3689 reg = <1>; 3690 3691 usb_dp_qmpphy_usb_ss_in: endpoint { 3692 remote-endpoint = <&usb_1_dwc3_ss>; 3693 }; 3694 }; 3695 3696 port@2 { 3697 reg = <2>; 3698 3699 usb_dp_qmpphy_dp_in: endpoint { 3700 remote-endpoint = <&mdss_dp_out>; 3701 }; 3702 }; 3703 }; 3704 }; 3705 3706 usb_2: usb@8cf8800 { 3707 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3708 reg = <0 0x08cf8800 0 0x400>; 3709 status = "disabled"; 3710 #address-cells = <2>; 3711 #size-cells = <2>; 3712 ranges; 3713 dma-ranges; 3714 3715 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3716 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3717 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3718 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3719 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3720 clock-names = "cfg_noc", 3721 "core", 3722 "iface", 3723 "sleep", 3724 "mock_utmi"; 3725 3726 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3727 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3728 assigned-clock-rates = <19200000>, <200000000>; 3729 3730 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 3731 <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3732 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3733 <&pdc 13 IRQ_TYPE_EDGE_BOTH>; 3734 interrupt-names = "pwr_event", 3735 "hs_phy_irq", 3736 "dp_hs_phy_irq", 3737 "dm_hs_phy_irq"; 3738 3739 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3740 required-opps = <&rpmhpd_opp_nom>; 3741 3742 resets = <&gcc GCC_USB30_SEC_BCR>; 3743 3744 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3745 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3746 interconnect-names = "usb-ddr", "apps-usb"; 3747 3748 usb_2_dwc3: usb@8c00000 { 3749 compatible = "snps,dwc3"; 3750 reg = <0 0x08c00000 0 0xe000>; 3751 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3752 iommus = <&apps_smmu 0xa0 0x0>; 3753 snps,dis_u2_susphy_quirk; 3754 snps,dis_enblslpm_quirk; 3755 snps,dis-u1-entry-quirk; 3756 snps,dis-u2-entry-quirk; 3757 phys = <&usb_2_hsphy>; 3758 phy-names = "usb2-phy"; 3759 maximum-speed = "high-speed"; 3760 usb-role-switch; 3761 3762 port { 3763 usb2_role_switch: endpoint { 3764 remote-endpoint = <&eud_ep>; 3765 }; 3766 }; 3767 }; 3768 }; 3769 3770 qspi: spi@88dc000 { 3771 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3772 reg = <0 0x088dc000 0 0x1000>; 3773 iommus = <&apps_smmu 0x20 0x0>; 3774 #address-cells = <1>; 3775 #size-cells = <0>; 3776 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3777 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3778 <&gcc GCC_QSPI_CORE_CLK>; 3779 clock-names = "iface", "core"; 3780 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3781 &cnoc2 SLAVE_QSPI_0 0>; 3782 interconnect-names = "qspi-config"; 3783 power-domains = <&rpmhpd SC7280_CX>; 3784 operating-points-v2 = <&qspi_opp_table>; 3785 status = "disabled"; 3786 }; 3787 3788 remoteproc_adsp: remoteproc@3700000 { 3789 compatible = "qcom,sc7280-adsp-pas"; 3790 reg = <0 0x03700000 0 0x100>; 3791 3792 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3793 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3794 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3795 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3796 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3797 <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3798 interrupt-names = "wdog", "fatal", "ready", "handover", 3799 "stop-ack", "shutdown-ack"; 3800 3801 clocks = <&rpmhcc RPMH_CXO_CLK>; 3802 clock-names = "xo"; 3803 3804 power-domains = <&rpmhpd SC7280_LCX>, 3805 <&rpmhpd SC7280_LMX>; 3806 power-domain-names = "lcx", "lmx"; 3807 3808 memory-region = <&adsp_mem>; 3809 3810 qcom,qmp = <&aoss_qmp>; 3811 3812 qcom,smem-states = <&adsp_smp2p_out 0>; 3813 qcom,smem-state-names = "stop"; 3814 3815 status = "disabled"; 3816 3817 glink-edge { 3818 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3819 IPCC_MPROC_SIGNAL_GLINK_QMP 3820 IRQ_TYPE_EDGE_RISING>; 3821 3822 mboxes = <&ipcc IPCC_CLIENT_LPASS 3823 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3824 3825 label = "lpass"; 3826 qcom,remote-pid = <2>; 3827 3828 apr { 3829 compatible = "qcom,apr-v2"; 3830 qcom,glink-channels = "apr_audio_svc"; 3831 qcom,domain = <APR_DOMAIN_ADSP>; 3832 #address-cells = <1>; 3833 #size-cells = <0>; 3834 3835 service@3 { 3836 reg = <APR_SVC_ADSP_CORE>; 3837 compatible = "qcom,q6core"; 3838 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3839 }; 3840 3841 q6afe: service@4 { 3842 compatible = "qcom,q6afe"; 3843 reg = <APR_SVC_AFE>; 3844 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3845 3846 q6afedai: dais { 3847 compatible = "qcom,q6afe-dais"; 3848 #address-cells = <1>; 3849 #size-cells = <0>; 3850 #sound-dai-cells = <1>; 3851 }; 3852 3853 q6afecc: clock-controller { 3854 compatible = "qcom,q6afe-clocks"; 3855 #clock-cells = <2>; 3856 }; 3857 }; 3858 3859 q6asm: service@7 { 3860 compatible = "qcom,q6asm"; 3861 reg = <APR_SVC_ASM>; 3862 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3863 3864 q6asmdai: dais { 3865 compatible = "qcom,q6asm-dais"; 3866 #address-cells = <1>; 3867 #size-cells = <0>; 3868 #sound-dai-cells = <1>; 3869 iommus = <&apps_smmu 0x1801 0x0>; 3870 3871 dai@0 { 3872 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 3873 }; 3874 3875 dai@1 { 3876 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 3877 }; 3878 3879 dai@2 { 3880 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 3881 }; 3882 }; 3883 }; 3884 3885 q6adm: service@8 { 3886 compatible = "qcom,q6adm"; 3887 reg = <APR_SVC_ADM>; 3888 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3889 3890 q6routing: routing { 3891 compatible = "qcom,q6adm-routing"; 3892 #sound-dai-cells = <0>; 3893 }; 3894 }; 3895 }; 3896 3897 fastrpc { 3898 compatible = "qcom,fastrpc"; 3899 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3900 label = "adsp"; 3901 qcom,non-secure-domain; 3902 #address-cells = <1>; 3903 #size-cells = <0>; 3904 3905 compute-cb@3 { 3906 compatible = "qcom,fastrpc-compute-cb"; 3907 reg = <3>; 3908 iommus = <&apps_smmu 0x1803 0x0>; 3909 dma-coherent; 3910 }; 3911 3912 compute-cb@4 { 3913 compatible = "qcom,fastrpc-compute-cb"; 3914 reg = <4>; 3915 iommus = <&apps_smmu 0x1804 0x0>; 3916 dma-coherent; 3917 }; 3918 3919 compute-cb@5 { 3920 compatible = "qcom,fastrpc-compute-cb"; 3921 reg = <5>; 3922 iommus = <&apps_smmu 0x1805 0x0>; 3923 dma-coherent; 3924 }; 3925 }; 3926 }; 3927 }; 3928 3929 remoteproc_wpss: remoteproc@8a00000 { 3930 compatible = "qcom,sc7280-wpss-pas"; 3931 reg = <0 0x08a00000 0 0x10000>; 3932 3933 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3934 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3935 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3936 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3937 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3938 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3939 interrupt-names = "wdog", "fatal", "ready", "handover", 3940 "stop-ack", "shutdown-ack"; 3941 3942 clocks = <&rpmhcc RPMH_CXO_CLK>; 3943 clock-names = "xo"; 3944 3945 power-domains = <&rpmhpd SC7280_CX>, 3946 <&rpmhpd SC7280_MX>; 3947 power-domain-names = "cx", "mx"; 3948 3949 memory-region = <&wpss_mem>; 3950 3951 qcom,qmp = <&aoss_qmp>; 3952 3953 qcom,smem-states = <&wpss_smp2p_out 0>; 3954 qcom,smem-state-names = "stop"; 3955 3956 3957 status = "disabled"; 3958 3959 glink-edge { 3960 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3961 IPCC_MPROC_SIGNAL_GLINK_QMP 3962 IRQ_TYPE_EDGE_RISING>; 3963 mboxes = <&ipcc IPCC_CLIENT_WPSS 3964 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3965 3966 label = "wpss"; 3967 qcom,remote-pid = <13>; 3968 }; 3969 }; 3970 3971 pmu@9091000 { 3972 compatible = "qcom,sc7280-llcc-bwmon"; 3973 reg = <0 0x09091000 0 0x1000>; 3974 3975 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3976 3977 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3978 3979 operating-points-v2 = <&llcc_bwmon_opp_table>; 3980 3981 llcc_bwmon_opp_table: opp-table { 3982 compatible = "operating-points-v2"; 3983 3984 opp-0 { 3985 opp-peak-kBps = <800000>; 3986 }; 3987 opp-1 { 3988 opp-peak-kBps = <1804000>; 3989 }; 3990 opp-2 { 3991 opp-peak-kBps = <2188000>; 3992 }; 3993 opp-3 { 3994 opp-peak-kBps = <3072000>; 3995 }; 3996 opp-4 { 3997 opp-peak-kBps = <4068000>; 3998 }; 3999 opp-5 { 4000 opp-peak-kBps = <6220000>; 4001 }; 4002 opp-6 { 4003 opp-peak-kBps = <6832000>; 4004 }; 4005 opp-7 { 4006 opp-peak-kBps = <8532000>; 4007 }; 4008 }; 4009 }; 4010 4011 pmu@90b6400 { 4012 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 4013 reg = <0 0x090b6400 0 0x600>; 4014 4015 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4016 4017 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 4018 operating-points-v2 = <&cpu_bwmon_opp_table>; 4019 4020 cpu_bwmon_opp_table: opp-table { 4021 compatible = "operating-points-v2"; 4022 4023 opp-0 { 4024 opp-peak-kBps = <2400000>; 4025 }; 4026 opp-1 { 4027 opp-peak-kBps = <4800000>; 4028 }; 4029 opp-2 { 4030 opp-peak-kBps = <7456000>; 4031 }; 4032 opp-3 { 4033 opp-peak-kBps = <9600000>; 4034 }; 4035 opp-4 { 4036 opp-peak-kBps = <12896000>; 4037 }; 4038 opp-5 { 4039 opp-peak-kBps = <14928000>; 4040 }; 4041 opp-6 { 4042 opp-peak-kBps = <17056000>; 4043 }; 4044 }; 4045 }; 4046 4047 dc_noc: interconnect@90e0000 { 4048 reg = <0 0x090e0000 0 0x5080>; 4049 compatible = "qcom,sc7280-dc-noc"; 4050 #interconnect-cells = <2>; 4051 qcom,bcm-voters = <&apps_bcm_voter>; 4052 }; 4053 4054 gem_noc: interconnect@9100000 { 4055 reg = <0 0x09100000 0 0xe2200>; 4056 compatible = "qcom,sc7280-gem-noc"; 4057 #interconnect-cells = <2>; 4058 qcom,bcm-voters = <&apps_bcm_voter>; 4059 }; 4060 4061 system-cache-controller@9200000 { 4062 compatible = "qcom,sc7280-llcc"; 4063 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 4064 <0 0x09600000 0 0x58000>; 4065 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 4066 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 4067 }; 4068 4069 eud: eud@88e0000 { 4070 compatible = "qcom,sc7280-eud", "qcom,eud"; 4071 reg = <0 0x88e0000 0 0x2000>, 4072 <0 0x88e2000 0 0x1000>; 4073 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 4074 4075 status = "disabled"; 4076 4077 ports { 4078 #address-cells = <1>; 4079 #size-cells = <0>; 4080 4081 port@0 { 4082 reg = <0>; 4083 eud_ep: endpoint { 4084 remote-endpoint = <&usb2_role_switch>; 4085 }; 4086 }; 4087 }; 4088 }; 4089 4090 nsp_noc: interconnect@a0c0000 { 4091 reg = <0 0x0a0c0000 0 0x10000>; 4092 compatible = "qcom,sc7280-nsp-noc"; 4093 #interconnect-cells = <2>; 4094 qcom,bcm-voters = <&apps_bcm_voter>; 4095 }; 4096 4097 remoteproc_cdsp: remoteproc@a300000 { 4098 compatible = "qcom,sc7280-cdsp-pas"; 4099 reg = <0 0x0a300000 0 0x10000>; 4100 4101 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4102 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4103 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4104 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4105 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 4106 <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 4107 interrupt-names = "wdog", "fatal", "ready", "handover", 4108 "stop-ack", "shutdown-ack"; 4109 4110 clocks = <&rpmhcc RPMH_CXO_CLK>; 4111 clock-names = "xo"; 4112 4113 power-domains = <&rpmhpd SC7280_CX>, 4114 <&rpmhpd SC7280_MX>; 4115 power-domain-names = "cx", "mx"; 4116 4117 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4118 4119 memory-region = <&cdsp_mem>; 4120 4121 qcom,qmp = <&aoss_qmp>; 4122 4123 qcom,smem-states = <&cdsp_smp2p_out 0>; 4124 qcom,smem-state-names = "stop"; 4125 4126 status = "disabled"; 4127 4128 glink-edge { 4129 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4130 IPCC_MPROC_SIGNAL_GLINK_QMP 4131 IRQ_TYPE_EDGE_RISING>; 4132 mboxes = <&ipcc IPCC_CLIENT_CDSP 4133 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4134 4135 label = "cdsp"; 4136 qcom,remote-pid = <5>; 4137 4138 fastrpc { 4139 compatible = "qcom,fastrpc"; 4140 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4141 label = "cdsp"; 4142 qcom,non-secure-domain; 4143 #address-cells = <1>; 4144 #size-cells = <0>; 4145 4146 compute-cb@1 { 4147 compatible = "qcom,fastrpc-compute-cb"; 4148 reg = <1>; 4149 iommus = <&apps_smmu 0x11a1 0x0420>, 4150 <&apps_smmu 0x1181 0x0420>; 4151 dma-coherent; 4152 }; 4153 4154 compute-cb@2 { 4155 compatible = "qcom,fastrpc-compute-cb"; 4156 reg = <2>; 4157 iommus = <&apps_smmu 0x11a2 0x0420>, 4158 <&apps_smmu 0x1182 0x0420>; 4159 dma-coherent; 4160 }; 4161 4162 compute-cb@3 { 4163 compatible = "qcom,fastrpc-compute-cb"; 4164 reg = <3>; 4165 iommus = <&apps_smmu 0x11a3 0x0420>, 4166 <&apps_smmu 0x1183 0x0420>; 4167 dma-coherent; 4168 }; 4169 4170 compute-cb@4 { 4171 compatible = "qcom,fastrpc-compute-cb"; 4172 reg = <4>; 4173 iommus = <&apps_smmu 0x11a4 0x0420>, 4174 <&apps_smmu 0x1184 0x0420>; 4175 dma-coherent; 4176 }; 4177 4178 compute-cb@5 { 4179 compatible = "qcom,fastrpc-compute-cb"; 4180 reg = <5>; 4181 iommus = <&apps_smmu 0x11a5 0x0420>, 4182 <&apps_smmu 0x1185 0x0420>; 4183 dma-coherent; 4184 }; 4185 4186 compute-cb@6 { 4187 compatible = "qcom,fastrpc-compute-cb"; 4188 reg = <6>; 4189 iommus = <&apps_smmu 0x11a6 0x0420>, 4190 <&apps_smmu 0x1186 0x0420>; 4191 dma-coherent; 4192 }; 4193 4194 compute-cb@7 { 4195 compatible = "qcom,fastrpc-compute-cb"; 4196 reg = <7>; 4197 iommus = <&apps_smmu 0x11a7 0x0420>, 4198 <&apps_smmu 0x1187 0x0420>; 4199 dma-coherent; 4200 }; 4201 4202 compute-cb@8 { 4203 compatible = "qcom,fastrpc-compute-cb"; 4204 reg = <8>; 4205 iommus = <&apps_smmu 0x11a8 0x0420>, 4206 <&apps_smmu 0x1188 0x0420>; 4207 dma-coherent; 4208 }; 4209 4210 /* note: secure cb9 in downstream */ 4211 4212 compute-cb@11 { 4213 compatible = "qcom,fastrpc-compute-cb"; 4214 reg = <11>; 4215 iommus = <&apps_smmu 0x11ab 0x0420>, 4216 <&apps_smmu 0x118b 0x0420>; 4217 dma-coherent; 4218 }; 4219 4220 compute-cb@12 { 4221 compatible = "qcom,fastrpc-compute-cb"; 4222 reg = <12>; 4223 iommus = <&apps_smmu 0x11ac 0x0420>, 4224 <&apps_smmu 0x118c 0x0420>; 4225 dma-coherent; 4226 }; 4227 4228 compute-cb@13 { 4229 compatible = "qcom,fastrpc-compute-cb"; 4230 reg = <13>; 4231 iommus = <&apps_smmu 0x11ad 0x0420>, 4232 <&apps_smmu 0x118d 0x0420>; 4233 dma-coherent; 4234 }; 4235 4236 compute-cb@14 { 4237 compatible = "qcom,fastrpc-compute-cb"; 4238 reg = <14>; 4239 iommus = <&apps_smmu 0x11ae 0x0420>, 4240 <&apps_smmu 0x118e 0x0420>; 4241 dma-coherent; 4242 }; 4243 }; 4244 }; 4245 }; 4246 4247 usb_1: usb@a6f8800 { 4248 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 4249 reg = <0 0x0a6f8800 0 0x400>; 4250 status = "disabled"; 4251 #address-cells = <2>; 4252 #size-cells = <2>; 4253 ranges; 4254 dma-ranges; 4255 4256 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4257 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4258 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4259 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4260 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4261 clock-names = "cfg_noc", 4262 "core", 4263 "iface", 4264 "sleep", 4265 "mock_utmi"; 4266 4267 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4268 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4269 assigned-clock-rates = <19200000>, <200000000>; 4270 4271 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4272 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4273 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4274 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4275 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4276 interrupt-names = "pwr_event", 4277 "hs_phy_irq", 4278 "dp_hs_phy_irq", 4279 "dm_hs_phy_irq", 4280 "ss_phy_irq"; 4281 4282 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4283 required-opps = <&rpmhpd_opp_nom>; 4284 4285 resets = <&gcc GCC_USB30_PRIM_BCR>; 4286 4287 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4288 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 4289 interconnect-names = "usb-ddr", "apps-usb"; 4290 4291 wakeup-source; 4292 4293 usb_1_dwc3: usb@a600000 { 4294 compatible = "snps,dwc3"; 4295 reg = <0 0x0a600000 0 0xe000>; 4296 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4297 iommus = <&apps_smmu 0xe0 0x0>; 4298 snps,dis_u2_susphy_quirk; 4299 snps,dis_enblslpm_quirk; 4300 snps,parkmode-disable-ss-quirk; 4301 snps,dis-u1-entry-quirk; 4302 snps,dis-u2-entry-quirk; 4303 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4304 phy-names = "usb2-phy", "usb3-phy"; 4305 maximum-speed = "super-speed"; 4306 4307 ports { 4308 #address-cells = <1>; 4309 #size-cells = <0>; 4310 4311 port@0 { 4312 reg = <0>; 4313 4314 usb_1_dwc3_hs: endpoint { 4315 }; 4316 }; 4317 4318 port@1 { 4319 reg = <1>; 4320 4321 usb_1_dwc3_ss: endpoint { 4322 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 4323 }; 4324 }; 4325 }; 4326 }; 4327 }; 4328 4329 venus: video-codec@aa00000 { 4330 compatible = "qcom,sc7280-venus"; 4331 reg = <0 0x0aa00000 0 0xd0600>; 4332 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4333 4334 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 4335 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 4336 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4337 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 4338 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 4339 clock-names = "core", "bus", "iface", 4340 "vcodec_core", "vcodec_bus"; 4341 4342 power-domains = <&videocc MVSC_GDSC>, 4343 <&videocc MVS0_GDSC>, 4344 <&rpmhpd SC7280_CX>; 4345 power-domain-names = "venus", "vcodec0", "cx"; 4346 operating-points-v2 = <&venus_opp_table>; 4347 4348 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 4349 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 4350 interconnect-names = "cpu-cfg", "video-mem"; 4351 4352 iommus = <&apps_smmu 0x2180 0x20>; 4353 memory-region = <&video_mem>; 4354 4355 status = "disabled"; 4356 4357 venus_opp_table: opp-table { 4358 compatible = "operating-points-v2"; 4359 4360 opp-133330000 { 4361 opp-hz = /bits/ 64 <133330000>; 4362 required-opps = <&rpmhpd_opp_low_svs>; 4363 }; 4364 4365 opp-240000000 { 4366 opp-hz = /bits/ 64 <240000000>; 4367 required-opps = <&rpmhpd_opp_svs>; 4368 }; 4369 4370 opp-335000000 { 4371 opp-hz = /bits/ 64 <335000000>; 4372 required-opps = <&rpmhpd_opp_svs_l1>; 4373 }; 4374 4375 opp-424000000 { 4376 opp-hz = /bits/ 64 <424000000>; 4377 required-opps = <&rpmhpd_opp_nom>; 4378 }; 4379 4380 opp-460000048 { 4381 opp-hz = /bits/ 64 <460000048>; 4382 required-opps = <&rpmhpd_opp_turbo>; 4383 }; 4384 }; 4385 }; 4386 4387 videocc: clock-controller@aaf0000 { 4388 compatible = "qcom,sc7280-videocc"; 4389 reg = <0 0x0aaf0000 0 0x10000>; 4390 clocks = <&rpmhcc RPMH_CXO_CLK>, 4391 <&rpmhcc RPMH_CXO_CLK_A>; 4392 clock-names = "bi_tcxo", "bi_tcxo_ao"; 4393 #clock-cells = <1>; 4394 #reset-cells = <1>; 4395 #power-domain-cells = <1>; 4396 }; 4397 4398 cci0: cci@ac4a000 { 4399 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4400 reg = <0 0x0ac4a000 0 0x1000>; 4401 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4402 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4403 4404 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4405 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4406 <&camcc CAM_CC_CPAS_AHB_CLK>, 4407 <&camcc CAM_CC_CCI_0_CLK>, 4408 <&camcc CAM_CC_CCI_0_CLK_SRC>; 4409 clock-names = "camnoc_axi", 4410 "slow_ahb_src", 4411 "cpas_ahb", 4412 "cci", 4413 "cci_src"; 4414 pinctrl-0 = <&cci0_default &cci1_default>; 4415 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4416 pinctrl-names = "default", "sleep"; 4417 4418 #address-cells = <1>; 4419 #size-cells = <0>; 4420 4421 status = "disabled"; 4422 4423 cci0_i2c0: i2c-bus@0 { 4424 reg = <0>; 4425 clock-frequency = <1000000>; 4426 #address-cells = <1>; 4427 #size-cells = <0>; 4428 }; 4429 4430 cci0_i2c1: i2c-bus@1 { 4431 reg = <1>; 4432 clock-frequency = <1000000>; 4433 #address-cells = <1>; 4434 #size-cells = <0>; 4435 }; 4436 }; 4437 4438 cci1: cci@ac4b000 { 4439 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4440 reg = <0 0x0ac4b000 0 0x1000>; 4441 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4442 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4443 4444 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4445 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4446 <&camcc CAM_CC_CPAS_AHB_CLK>, 4447 <&camcc CAM_CC_CCI_1_CLK>, 4448 <&camcc CAM_CC_CCI_1_CLK_SRC>; 4449 clock-names = "camnoc_axi", 4450 "slow_ahb_src", 4451 "cpas_ahb", 4452 "cci", 4453 "cci_src"; 4454 pinctrl-0 = <&cci2_default &cci3_default>; 4455 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 4456 pinctrl-names = "default", "sleep"; 4457 4458 #address-cells = <1>; 4459 #size-cells = <0>; 4460 4461 status = "disabled"; 4462 4463 cci1_i2c0: i2c-bus@0 { 4464 reg = <0>; 4465 clock-frequency = <1000000>; 4466 #address-cells = <1>; 4467 #size-cells = <0>; 4468 }; 4469 4470 cci1_i2c1: i2c-bus@1 { 4471 reg = <1>; 4472 clock-frequency = <1000000>; 4473 #address-cells = <1>; 4474 #size-cells = <0>; 4475 }; 4476 }; 4477 4478 camss: isp@acb3000 { 4479 compatible = "qcom,sc7280-camss"; 4480 4481 reg = <0x0 0x0acb3000 0x0 0x1000>, 4482 <0x0 0x0acba000 0x0 0x1000>, 4483 <0x0 0x0acc1000 0x0 0x1000>, 4484 <0x0 0x0acc8000 0x0 0x1000>, 4485 <0x0 0x0accf000 0x0 0x1000>, 4486 <0x0 0x0ace0000 0x0 0x2000>, 4487 <0x0 0x0ace2000 0x0 0x2000>, 4488 <0x0 0x0ace4000 0x0 0x2000>, 4489 <0x0 0x0ace6000 0x0 0x2000>, 4490 <0x0 0x0ace8000 0x0 0x2000>, 4491 <0x0 0x0acaf000 0x0 0x4000>, 4492 <0x0 0x0acb6000 0x0 0x4000>, 4493 <0x0 0x0acbd000 0x0 0x4000>, 4494 <0x0 0x0acc4000 0x0 0x4000>, 4495 <0x0 0x0accb000 0x0 0x4000>; 4496 reg-names = "csid0", 4497 "csid1", 4498 "csid2", 4499 "csid_lite0", 4500 "csid_lite1", 4501 "csiphy0", 4502 "csiphy1", 4503 "csiphy2", 4504 "csiphy3", 4505 "csiphy4", 4506 "vfe0", 4507 "vfe1", 4508 "vfe2", 4509 "vfe_lite0", 4510 "vfe_lite1"; 4511 4512 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4513 <&camcc CAM_CC_CPAS_AHB_CLK>, 4514 <&camcc CAM_CC_CSIPHY0_CLK>, 4515 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4516 <&camcc CAM_CC_CSIPHY1_CLK>, 4517 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4518 <&camcc CAM_CC_CSIPHY2_CLK>, 4519 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4520 <&camcc CAM_CC_CSIPHY3_CLK>, 4521 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4522 <&camcc CAM_CC_CSIPHY4_CLK>, 4523 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 4524 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4525 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4526 <&camcc CAM_CC_ICP_AHB_CLK>, 4527 <&camcc CAM_CC_IFE_0_CLK>, 4528 <&camcc CAM_CC_IFE_0_AXI_CLK>, 4529 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4530 <&camcc CAM_CC_IFE_0_CSID_CLK>, 4531 <&camcc CAM_CC_IFE_1_CLK>, 4532 <&camcc CAM_CC_IFE_1_AXI_CLK>, 4533 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4534 <&camcc CAM_CC_IFE_1_CSID_CLK>, 4535 <&camcc CAM_CC_IFE_2_CLK>, 4536 <&camcc CAM_CC_IFE_2_AXI_CLK>, 4537 <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, 4538 <&camcc CAM_CC_IFE_2_CSID_CLK>, 4539 <&camcc CAM_CC_IFE_LITE_0_CLK>, 4540 <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, 4541 <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, 4542 <&camcc CAM_CC_IFE_LITE_1_CLK>, 4543 <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, 4544 <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>; 4545 clock-names = "camnoc_axi", 4546 "cpas_ahb", 4547 "csiphy0", 4548 "csiphy0_timer", 4549 "csiphy1", 4550 "csiphy1_timer", 4551 "csiphy2", 4552 "csiphy2_timer", 4553 "csiphy3", 4554 "csiphy3_timer", 4555 "csiphy4", 4556 "csiphy4_timer", 4557 "gcc_axi_hf", 4558 "gcc_axi_sf", 4559 "icp_ahb", 4560 "vfe0", 4561 "vfe0_axi", 4562 "vfe0_cphy_rx", 4563 "vfe0_csid", 4564 "vfe1", 4565 "vfe1_axi", 4566 "vfe1_cphy_rx", 4567 "vfe1_csid", 4568 "vfe2", 4569 "vfe2_axi", 4570 "vfe2_cphy_rx", 4571 "vfe2_csid", 4572 "vfe_lite0", 4573 "vfe_lite0_cphy_rx", 4574 "vfe_lite0_csid", 4575 "vfe_lite1", 4576 "vfe_lite1_cphy_rx", 4577 "vfe_lite1_csid"; 4578 4579 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4580 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4581 <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, 4582 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4583 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4584 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4585 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4586 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4587 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4588 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 4589 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4590 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4591 <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, 4592 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4593 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; 4594 interrupt-names = "csid0", 4595 "csid1", 4596 "csid2", 4597 "csid_lite0", 4598 "csid_lite1", 4599 "csiphy0", 4600 "csiphy1", 4601 "csiphy2", 4602 "csiphy3", 4603 "csiphy4", 4604 "vfe0", 4605 "vfe1", 4606 "vfe2", 4607 "vfe_lite0", 4608 "vfe_lite1"; 4609 4610 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4611 &cnoc2 SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4612 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 4613 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4614 interconnect-names = "ahb", 4615 "hf_0"; 4616 4617 iommus = <&apps_smmu 0x800 0x4e0>; 4618 4619 power-domains = <&camcc CAM_CC_IFE_0_GDSC>, 4620 <&camcc CAM_CC_IFE_1_GDSC>, 4621 <&camcc CAM_CC_IFE_2_GDSC>, 4622 <&camcc CAM_CC_TITAN_TOP_GDSC>; 4623 power-domain-names = "ife0", 4624 "ife1", 4625 "ife2", 4626 "top"; 4627 4628 status = "disabled"; 4629 4630 ports { 4631 #address-cells = <1>; 4632 #size-cells = <0>; 4633 4634 port@0 { 4635 reg = <0>; 4636 }; 4637 4638 port@1 { 4639 reg = <1>; 4640 }; 4641 4642 port@2 { 4643 reg = <2>; 4644 }; 4645 4646 port@3 { 4647 reg = <3>; 4648 }; 4649 4650 port@4 { 4651 reg = <4>; 4652 }; 4653 }; 4654 }; 4655 4656 camcc: clock-controller@ad00000 { 4657 compatible = "qcom,sc7280-camcc"; 4658 reg = <0 0x0ad00000 0 0x10000>; 4659 clocks = <&rpmhcc RPMH_CXO_CLK>, 4660 <&rpmhcc RPMH_CXO_CLK_A>, 4661 <&sleep_clk>; 4662 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4663 #clock-cells = <1>; 4664 #reset-cells = <1>; 4665 #power-domain-cells = <1>; 4666 }; 4667 4668 dispcc: clock-controller@af00000 { 4669 compatible = "qcom,sc7280-dispcc"; 4670 reg = <0 0x0af00000 0 0x20000>; 4671 clocks = <&rpmhcc RPMH_CXO_CLK>, 4672 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4673 <&mdss_dsi_phy DSI_BYTE_PLL_CLK>, 4674 <&mdss_dsi_phy DSI_PIXEL_PLL_CLK>, 4675 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4676 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4677 <&mdss_edp_phy 0>, 4678 <&mdss_edp_phy 1>; 4679 clock-names = "bi_tcxo", 4680 "gcc_disp_gpll0_clk", 4681 "dsi0_phy_pll_out_byteclk", 4682 "dsi0_phy_pll_out_dsiclk", 4683 "dp_phy_pll_link_clk", 4684 "dp_phy_pll_vco_div_clk", 4685 "edp_phy_pll_link_clk", 4686 "edp_phy_pll_vco_div_clk"; 4687 #clock-cells = <1>; 4688 #reset-cells = <1>; 4689 #power-domain-cells = <1>; 4690 }; 4691 4692 mdss: display-subsystem@ae00000 { 4693 compatible = "qcom,sc7280-mdss"; 4694 reg = <0 0x0ae00000 0 0x1000>; 4695 reg-names = "mdss"; 4696 4697 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 4698 4699 clocks = <&gcc GCC_DISP_AHB_CLK>, 4700 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4701 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4702 clock-names = "iface", 4703 "ahb", 4704 "core"; 4705 4706 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4707 interrupt-controller; 4708 #interrupt-cells = <1>; 4709 4710 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 4711 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4712 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4713 &cnoc2 SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 4714 interconnect-names = "mdp0-mem", 4715 "cpu-cfg"; 4716 4717 iommus = <&apps_smmu 0x900 0x402>; 4718 4719 #address-cells = <2>; 4720 #size-cells = <2>; 4721 ranges; 4722 4723 status = "disabled"; 4724 4725 mdss_mdp: display-controller@ae01000 { 4726 compatible = "qcom,sc7280-dpu"; 4727 reg = <0 0x0ae01000 0 0x8f030>, 4728 <0 0x0aeb0000 0 0x3000>; 4729 reg-names = "mdp", "vbif"; 4730 4731 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4732 <&gcc GCC_DISP_SF_AXI_CLK>, 4733 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4734 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 4735 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4736 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4737 clock-names = "bus", 4738 "nrt_bus", 4739 "iface", 4740 "lut", 4741 "core", 4742 "vsync"; 4743 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 4744 <&dispcc DISP_CC_MDSS_AHB_CLK>; 4745 assigned-clock-rates = <19200000>, 4746 <19200000>; 4747 operating-points-v2 = <&mdp_opp_table>; 4748 power-domains = <&rpmhpd SC7280_CX>; 4749 4750 interrupt-parent = <&mdss>; 4751 interrupts = <0>; 4752 4753 ports { 4754 #address-cells = <1>; 4755 #size-cells = <0>; 4756 4757 port@0 { 4758 reg = <0>; 4759 dpu_intf1_out: endpoint { 4760 remote-endpoint = <&mdss_dsi0_in>; 4761 }; 4762 }; 4763 4764 port@1 { 4765 reg = <1>; 4766 dpu_intf5_out: endpoint { 4767 remote-endpoint = <&edp_in>; 4768 }; 4769 }; 4770 4771 port@2 { 4772 reg = <2>; 4773 dpu_intf0_out: endpoint { 4774 remote-endpoint = <&dp_in>; 4775 }; 4776 }; 4777 }; 4778 4779 mdp_opp_table: opp-table { 4780 compatible = "operating-points-v2"; 4781 4782 opp-200000000 { 4783 opp-hz = /bits/ 64 <200000000>; 4784 required-opps = <&rpmhpd_opp_low_svs>; 4785 }; 4786 4787 opp-300000000 { 4788 opp-hz = /bits/ 64 <300000000>; 4789 required-opps = <&rpmhpd_opp_svs>; 4790 }; 4791 4792 opp-380000000 { 4793 opp-hz = /bits/ 64 <380000000>; 4794 required-opps = <&rpmhpd_opp_svs_l1>; 4795 }; 4796 4797 opp-506666667 { 4798 opp-hz = /bits/ 64 <506666667>; 4799 required-opps = <&rpmhpd_opp_nom>; 4800 }; 4801 4802 opp-608000000 { 4803 opp-hz = /bits/ 64 <608000000>; 4804 required-opps = <&rpmhpd_opp_turbo>; 4805 }; 4806 }; 4807 }; 4808 4809 mdss_dsi: dsi@ae94000 { 4810 compatible = "qcom,sc7280-dsi-ctrl", 4811 "qcom,mdss-dsi-ctrl"; 4812 reg = <0 0x0ae94000 0 0x400>; 4813 reg-names = "dsi_ctrl"; 4814 4815 interrupt-parent = <&mdss>; 4816 interrupts = <4>; 4817 4818 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4819 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4820 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4821 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4822 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4823 <&gcc GCC_DISP_HF_AXI_CLK>; 4824 clock-names = "byte", 4825 "byte_intf", 4826 "pixel", 4827 "core", 4828 "iface", 4829 "bus"; 4830 4831 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 4832 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4833 assigned-clock-parents = <&mdss_dsi_phy DSI_BYTE_PLL_CLK>, 4834 <&mdss_dsi_phy DSI_PIXEL_PLL_CLK>; 4835 4836 operating-points-v2 = <&dsi_opp_table>; 4837 power-domains = <&rpmhpd SC7280_CX>; 4838 4839 phys = <&mdss_dsi_phy>; 4840 4841 #address-cells = <1>; 4842 #size-cells = <0>; 4843 4844 status = "disabled"; 4845 4846 ports { 4847 #address-cells = <1>; 4848 #size-cells = <0>; 4849 4850 port@0 { 4851 reg = <0>; 4852 mdss_dsi0_in: endpoint { 4853 remote-endpoint = <&dpu_intf1_out>; 4854 }; 4855 }; 4856 4857 port@1 { 4858 reg = <1>; 4859 mdss_dsi0_out: endpoint { 4860 }; 4861 }; 4862 }; 4863 4864 dsi_opp_table: opp-table { 4865 compatible = "operating-points-v2"; 4866 4867 opp-187500000 { 4868 opp-hz = /bits/ 64 <187500000>; 4869 required-opps = <&rpmhpd_opp_low_svs>; 4870 }; 4871 4872 opp-300000000 { 4873 opp-hz = /bits/ 64 <300000000>; 4874 required-opps = <&rpmhpd_opp_svs>; 4875 }; 4876 4877 opp-358000000 { 4878 opp-hz = /bits/ 64 <358000000>; 4879 required-opps = <&rpmhpd_opp_svs_l1>; 4880 }; 4881 }; 4882 }; 4883 4884 mdss_dsi_phy: phy@ae94400 { 4885 compatible = "qcom,sc7280-dsi-phy-7nm"; 4886 reg = <0 0x0ae94400 0 0x200>, 4887 <0 0x0ae94600 0 0x280>, 4888 <0 0x0ae94900 0 0x280>; 4889 reg-names = "dsi_phy", 4890 "dsi_phy_lane", 4891 "dsi_pll"; 4892 4893 #clock-cells = <1>; 4894 #phy-cells = <0>; 4895 4896 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4897 <&rpmhcc RPMH_CXO_CLK>; 4898 clock-names = "iface", "ref"; 4899 4900 status = "disabled"; 4901 }; 4902 4903 mdss_edp: edp@aea0000 { 4904 compatible = "qcom,sc7280-edp"; 4905 pinctrl-names = "default"; 4906 pinctrl-0 = <&edp_hot_plug_det>; 4907 4908 reg = <0 0x0aea0000 0 0x200>, 4909 <0 0x0aea0200 0 0x200>, 4910 <0 0x0aea0400 0 0xc00>, 4911 <0 0x0aea1000 0 0x400>; 4912 4913 interrupt-parent = <&mdss>; 4914 interrupts = <14>; 4915 4916 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4917 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4918 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4919 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4920 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4921 clock-names = "core_iface", 4922 "core_aux", 4923 "ctrl_link", 4924 "ctrl_link_iface", 4925 "stream_pixel"; 4926 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4927 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4928 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4929 4930 phys = <&mdss_edp_phy>; 4931 phy-names = "dp"; 4932 4933 operating-points-v2 = <&edp_opp_table>; 4934 power-domains = <&rpmhpd SC7280_CX>; 4935 4936 status = "disabled"; 4937 4938 ports { 4939 #address-cells = <1>; 4940 #size-cells = <0>; 4941 4942 port@0 { 4943 reg = <0>; 4944 edp_in: endpoint { 4945 remote-endpoint = <&dpu_intf5_out>; 4946 }; 4947 }; 4948 4949 port@1 { 4950 reg = <1>; 4951 mdss_edp_out: endpoint { }; 4952 }; 4953 }; 4954 4955 edp_opp_table: opp-table { 4956 compatible = "operating-points-v2"; 4957 4958 opp-160000000 { 4959 opp-hz = /bits/ 64 <160000000>; 4960 required-opps = <&rpmhpd_opp_low_svs>; 4961 }; 4962 4963 opp-270000000 { 4964 opp-hz = /bits/ 64 <270000000>; 4965 required-opps = <&rpmhpd_opp_svs>; 4966 }; 4967 4968 opp-540000000 { 4969 opp-hz = /bits/ 64 <540000000>; 4970 required-opps = <&rpmhpd_opp_nom>; 4971 }; 4972 4973 opp-810000000 { 4974 opp-hz = /bits/ 64 <810000000>; 4975 required-opps = <&rpmhpd_opp_nom>; 4976 }; 4977 }; 4978 }; 4979 4980 mdss_edp_phy: phy@aec2a00 { 4981 compatible = "qcom,sc7280-edp-phy"; 4982 4983 reg = <0 0x0aec2a00 0 0x19c>, 4984 <0 0x0aec2200 0 0xa0>, 4985 <0 0x0aec2600 0 0xa0>, 4986 <0 0x0aec2000 0 0x1c0>; 4987 4988 clocks = <&rpmhcc RPMH_CXO_CLK>, 4989 <&gcc GCC_EDP_CLKREF_EN>; 4990 clock-names = "aux", 4991 "cfg_ahb"; 4992 4993 #clock-cells = <1>; 4994 #phy-cells = <0>; 4995 4996 status = "disabled"; 4997 }; 4998 4999 mdss_dp: displayport-controller@ae90000 { 5000 compatible = "qcom,sc7280-dp"; 5001 5002 reg = <0 0x0ae90000 0 0x200>, 5003 <0 0x0ae90200 0 0x200>, 5004 <0 0x0ae90400 0 0xc00>, 5005 <0 0x0ae91000 0 0x400>, 5006 <0 0x0ae91400 0 0x400>; 5007 5008 interrupt-parent = <&mdss>; 5009 interrupts = <12>; 5010 5011 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5012 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 5013 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 5014 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 5015 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 5016 clock-names = "core_iface", 5017 "core_aux", 5018 "ctrl_link", 5019 "ctrl_link_iface", 5020 "stream_pixel"; 5021 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 5022 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 5023 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5024 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5025 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 5026 phy-names = "dp"; 5027 5028 operating-points-v2 = <&dp_opp_table>; 5029 power-domains = <&rpmhpd SC7280_CX>; 5030 5031 #sound-dai-cells = <0>; 5032 5033 status = "disabled"; 5034 5035 ports { 5036 #address-cells = <1>; 5037 #size-cells = <0>; 5038 5039 port@0 { 5040 reg = <0>; 5041 dp_in: endpoint { 5042 remote-endpoint = <&dpu_intf0_out>; 5043 }; 5044 }; 5045 5046 port@1 { 5047 reg = <1>; 5048 mdss_dp_out: endpoint { 5049 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 5050 }; 5051 }; 5052 }; 5053 5054 dp_opp_table: opp-table { 5055 compatible = "operating-points-v2"; 5056 5057 opp-160000000 { 5058 opp-hz = /bits/ 64 <160000000>; 5059 required-opps = <&rpmhpd_opp_low_svs>; 5060 }; 5061 5062 opp-270000000 { 5063 opp-hz = /bits/ 64 <270000000>; 5064 required-opps = <&rpmhpd_opp_svs>; 5065 }; 5066 5067 opp-540000000 { 5068 opp-hz = /bits/ 64 <540000000>; 5069 required-opps = <&rpmhpd_opp_svs_l1>; 5070 }; 5071 5072 opp-810000000 { 5073 opp-hz = /bits/ 64 <810000000>; 5074 required-opps = <&rpmhpd_opp_nom>; 5075 }; 5076 }; 5077 }; 5078 }; 5079 5080 pdc: interrupt-controller@b220000 { 5081 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 5082 reg = <0 0x0b220000 0 0x30000>; 5083 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 5084 <55 306 4>, <59 312 3>, <62 374 2>, 5085 <64 434 2>, <66 438 3>, <69 86 1>, 5086 <70 520 54>, <124 609 31>, <155 63 1>, 5087 <156 716 12>; 5088 #interrupt-cells = <2>; 5089 interrupt-parent = <&intc>; 5090 interrupt-controller; 5091 }; 5092 5093 pdc_reset: reset-controller@b5e0000 { 5094 compatible = "qcom,sc7280-pdc-global"; 5095 reg = <0 0x0b5e0000 0 0x20000>; 5096 #reset-cells = <1>; 5097 status = "reserved"; /* Owned by firmware */ 5098 }; 5099 5100 tsens0: thermal-sensor@c263000 { 5101 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 5102 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5103 <0 0x0c222000 0 0x1ff>; /* SROT */ 5104 #qcom,sensors = <15>; 5105 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5107 interrupt-names = "uplow","critical"; 5108 #thermal-sensor-cells = <1>; 5109 }; 5110 5111 tsens1: thermal-sensor@c265000 { 5112 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 5113 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5114 <0 0x0c223000 0 0x1ff>; /* SROT */ 5115 #qcom,sensors = <12>; 5116 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5118 interrupt-names = "uplow","critical"; 5119 #thermal-sensor-cells = <1>; 5120 }; 5121 5122 aoss_reset: reset-controller@c2a0000 { 5123 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 5124 reg = <0 0x0c2a0000 0 0x31000>; 5125 #reset-cells = <1>; 5126 }; 5127 5128 aoss_qmp: power-management@c300000 { 5129 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 5130 reg = <0 0x0c300000 0 0x400>; 5131 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5132 IPCC_MPROC_SIGNAL_GLINK_QMP 5133 IRQ_TYPE_EDGE_RISING>; 5134 mboxes = <&ipcc IPCC_CLIENT_AOP 5135 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5136 5137 #clock-cells = <0>; 5138 }; 5139 5140 sram@c3f0000 { 5141 compatible = "qcom,rpmh-stats"; 5142 reg = <0 0x0c3f0000 0 0x400>; 5143 }; 5144 5145 spmi_bus: spmi@c440000 { 5146 compatible = "qcom,spmi-pmic-arb"; 5147 reg = <0 0x0c440000 0 0x1100>, 5148 <0 0x0c600000 0 0x2000000>, 5149 <0 0x0e600000 0 0x100000>, 5150 <0 0x0e700000 0 0xa0000>, 5151 <0 0x0c40a000 0 0x26000>; 5152 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5153 interrupt-names = "periph_irq"; 5154 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5155 qcom,ee = <0>; 5156 qcom,channel = <0>; 5157 #address-cells = <2>; 5158 #size-cells = <0>; 5159 interrupt-controller; 5160 #interrupt-cells = <4>; 5161 }; 5162 5163 tlmm: pinctrl@f100000 { 5164 compatible = "qcom,sc7280-pinctrl"; 5165 reg = <0 0x0f100000 0 0x300000>; 5166 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5167 gpio-controller; 5168 #gpio-cells = <2>; 5169 interrupt-controller; 5170 #interrupt-cells = <2>; 5171 gpio-ranges = <&tlmm 0 0 175>; 5172 wakeup-parent = <&pdc>; 5173 5174 cci0_default: cci0-default-state { 5175 pins = "gpio69", "gpio70"; 5176 function = "cci_i2c"; 5177 drive-strength = <2>; 5178 bias-pull-up; 5179 }; 5180 5181 cci0_sleep: cci0-sleep-state { 5182 pins = "gpio69", "gpio70"; 5183 function = "cci_i2c"; 5184 drive-strength = <2>; 5185 bias-pull-down; 5186 }; 5187 5188 cci1_default: cci1-default-state { 5189 pins = "gpio71", "gpio72"; 5190 function = "cci_i2c"; 5191 drive-strength = <2>; 5192 bias-pull-up; 5193 }; 5194 5195 cci1_sleep: cci1-sleep-state { 5196 pins = "gpio71", "gpio72"; 5197 function = "cci_i2c"; 5198 drive-strength = <2>; 5199 bias-pull-down; 5200 }; 5201 5202 cci2_default: cci2-default-state { 5203 pins = "gpio73", "gpio74"; 5204 function = "cci_i2c"; 5205 drive-strength = <2>; 5206 bias-pull-up; 5207 }; 5208 5209 cci2_sleep: cci2-sleep-state { 5210 pins = "gpio73", "gpio74"; 5211 function = "cci_i2c"; 5212 drive-strength = <2>; 5213 bias-pull-down; 5214 }; 5215 5216 cci3_default: cci3-default-state { 5217 pins = "gpio75", "gpio76"; 5218 function = "cci_i2c"; 5219 drive-strength = <2>; 5220 bias-pull-up; 5221 }; 5222 5223 cci3_sleep: cci3-sleep-state { 5224 pins = "gpio75", "gpio76"; 5225 function = "cci_i2c"; 5226 drive-strength = <2>; 5227 bias-pull-down; 5228 }; 5229 5230 dp_hot_plug_det: dp-hot-plug-det-state { 5231 pins = "gpio47"; 5232 function = "dp_hot"; 5233 }; 5234 5235 edp_hot_plug_det: edp-hot-plug-det-state { 5236 pins = "gpio60"; 5237 function = "edp_hot"; 5238 }; 5239 5240 mi2s0_data0: mi2s0-data0-state { 5241 pins = "gpio98"; 5242 function = "mi2s0_data0"; 5243 }; 5244 5245 mi2s0_data1: mi2s0-data1-state { 5246 pins = "gpio99"; 5247 function = "mi2s0_data1"; 5248 }; 5249 5250 mi2s0_mclk: mi2s0-mclk-state { 5251 pins = "gpio96"; 5252 function = "pri_mi2s"; 5253 }; 5254 5255 mi2s0_sclk: mi2s0-sclk-state { 5256 pins = "gpio97"; 5257 function = "mi2s0_sck"; 5258 }; 5259 5260 mi2s0_ws: mi2s0-ws-state { 5261 pins = "gpio100"; 5262 function = "mi2s0_ws"; 5263 }; 5264 5265 mi2s1_data0: mi2s1-data0-state { 5266 pins = "gpio107"; 5267 function = "mi2s1_data0"; 5268 }; 5269 5270 mi2s1_sclk: mi2s1-sclk-state { 5271 pins = "gpio106"; 5272 function = "mi2s1_sck"; 5273 }; 5274 5275 mi2s1_ws: mi2s1-ws-state { 5276 pins = "gpio108"; 5277 function = "mi2s1_ws"; 5278 }; 5279 5280 pcie1_clkreq_n: pcie1-clkreq-n-state { 5281 pins = "gpio79"; 5282 function = "pcie1_clkreqn"; 5283 }; 5284 5285 qspi_clk: qspi-clk-state { 5286 pins = "gpio14"; 5287 function = "qspi_clk"; 5288 }; 5289 5290 qspi_cs0: qspi-cs0-state { 5291 pins = "gpio15"; 5292 function = "qspi_cs"; 5293 }; 5294 5295 qspi_cs1: qspi-cs1-state { 5296 pins = "gpio19"; 5297 function = "qspi_cs"; 5298 }; 5299 5300 qspi_data0: qspi-data0-state { 5301 pins = "gpio12"; 5302 function = "qspi_data"; 5303 }; 5304 5305 qspi_data1: qspi-data1-state { 5306 pins = "gpio13"; 5307 function = "qspi_data"; 5308 }; 5309 5310 qspi_data23: qspi-data23-state { 5311 pins = "gpio16", "gpio17"; 5312 function = "qspi_data"; 5313 }; 5314 5315 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5316 pins = "gpio0", "gpio1"; 5317 function = "qup00"; 5318 }; 5319 5320 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5321 pins = "gpio4", "gpio5"; 5322 function = "qup01"; 5323 }; 5324 5325 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5326 pins = "gpio8", "gpio9"; 5327 function = "qup02"; 5328 }; 5329 5330 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5331 pins = "gpio12", "gpio13"; 5332 function = "qup03"; 5333 }; 5334 5335 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5336 pins = "gpio16", "gpio17"; 5337 function = "qup04"; 5338 }; 5339 5340 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5341 pins = "gpio20", "gpio21"; 5342 function = "qup05"; 5343 }; 5344 5345 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5346 pins = "gpio24", "gpio25"; 5347 function = "qup06"; 5348 }; 5349 5350 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5351 pins = "gpio28", "gpio29"; 5352 function = "qup07"; 5353 }; 5354 5355 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5356 pins = "gpio32", "gpio33"; 5357 function = "qup10"; 5358 }; 5359 5360 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5361 pins = "gpio36", "gpio37"; 5362 function = "qup11"; 5363 }; 5364 5365 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5366 pins = "gpio40", "gpio41"; 5367 function = "qup12"; 5368 }; 5369 5370 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5371 pins = "gpio44", "gpio45"; 5372 function = "qup13"; 5373 }; 5374 5375 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5376 pins = "gpio48", "gpio49"; 5377 function = "qup14"; 5378 }; 5379 5380 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5381 pins = "gpio52", "gpio53"; 5382 function = "qup15"; 5383 }; 5384 5385 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5386 pins = "gpio56", "gpio57"; 5387 function = "qup16"; 5388 }; 5389 5390 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5391 pins = "gpio60", "gpio61"; 5392 function = "qup17"; 5393 }; 5394 5395 qup_spi0_data_clk: qup-spi0-data-clk-state { 5396 pins = "gpio0", "gpio1", "gpio2"; 5397 function = "qup00"; 5398 }; 5399 5400 qup_spi0_cs: qup-spi0-cs-state { 5401 pins = "gpio3"; 5402 function = "qup00"; 5403 }; 5404 5405 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 5406 pins = "gpio3"; 5407 function = "gpio"; 5408 }; 5409 5410 qup_spi1_data_clk: qup-spi1-data-clk-state { 5411 pins = "gpio4", "gpio5", "gpio6"; 5412 function = "qup01"; 5413 }; 5414 5415 qup_spi1_cs: qup-spi1-cs-state { 5416 pins = "gpio7"; 5417 function = "qup01"; 5418 }; 5419 5420 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 5421 pins = "gpio7"; 5422 function = "gpio"; 5423 }; 5424 5425 qup_spi2_data_clk: qup-spi2-data-clk-state { 5426 pins = "gpio8", "gpio9", "gpio10"; 5427 function = "qup02"; 5428 }; 5429 5430 qup_spi2_cs: qup-spi2-cs-state { 5431 pins = "gpio11"; 5432 function = "qup02"; 5433 }; 5434 5435 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 5436 pins = "gpio11"; 5437 function = "gpio"; 5438 }; 5439 5440 qup_spi3_data_clk: qup-spi3-data-clk-state { 5441 pins = "gpio12", "gpio13", "gpio14"; 5442 function = "qup03"; 5443 }; 5444 5445 qup_spi3_cs: qup-spi3-cs-state { 5446 pins = "gpio15"; 5447 function = "qup03"; 5448 }; 5449 5450 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5451 pins = "gpio15"; 5452 function = "gpio"; 5453 }; 5454 5455 qup_spi4_data_clk: qup-spi4-data-clk-state { 5456 pins = "gpio16", "gpio17", "gpio18"; 5457 function = "qup04"; 5458 }; 5459 5460 qup_spi4_cs: qup-spi4-cs-state { 5461 pins = "gpio19"; 5462 function = "qup04"; 5463 }; 5464 5465 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 5466 pins = "gpio19"; 5467 function = "gpio"; 5468 }; 5469 5470 qup_spi5_data_clk: qup-spi5-data-clk-state { 5471 pins = "gpio20", "gpio21", "gpio22"; 5472 function = "qup05"; 5473 }; 5474 5475 qup_spi5_cs: qup-spi5-cs-state { 5476 pins = "gpio23"; 5477 function = "qup05"; 5478 }; 5479 5480 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 5481 pins = "gpio23"; 5482 function = "gpio"; 5483 }; 5484 5485 qup_spi6_data_clk: qup-spi6-data-clk-state { 5486 pins = "gpio24", "gpio25", "gpio26"; 5487 function = "qup06"; 5488 }; 5489 5490 qup_spi6_cs: qup-spi6-cs-state { 5491 pins = "gpio27"; 5492 function = "qup06"; 5493 }; 5494 5495 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 5496 pins = "gpio27"; 5497 function = "gpio"; 5498 }; 5499 5500 qup_spi7_data_clk: qup-spi7-data-clk-state { 5501 pins = "gpio28", "gpio29", "gpio30"; 5502 function = "qup07"; 5503 }; 5504 5505 qup_spi7_cs: qup-spi7-cs-state { 5506 pins = "gpio31"; 5507 function = "qup07"; 5508 }; 5509 5510 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 5511 pins = "gpio31"; 5512 function = "gpio"; 5513 }; 5514 5515 qup_spi8_data_clk: qup-spi8-data-clk-state { 5516 pins = "gpio32", "gpio33", "gpio34"; 5517 function = "qup10"; 5518 }; 5519 5520 qup_spi8_cs: qup-spi8-cs-state { 5521 pins = "gpio35"; 5522 function = "qup10"; 5523 }; 5524 5525 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 5526 pins = "gpio35"; 5527 function = "gpio"; 5528 }; 5529 5530 qup_spi9_data_clk: qup-spi9-data-clk-state { 5531 pins = "gpio36", "gpio37", "gpio38"; 5532 function = "qup11"; 5533 }; 5534 5535 qup_spi9_cs: qup-spi9-cs-state { 5536 pins = "gpio39"; 5537 function = "qup11"; 5538 }; 5539 5540 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 5541 pins = "gpio39"; 5542 function = "gpio"; 5543 }; 5544 5545 qup_spi10_data_clk: qup-spi10-data-clk-state { 5546 pins = "gpio40", "gpio41", "gpio42"; 5547 function = "qup12"; 5548 }; 5549 5550 qup_spi10_cs: qup-spi10-cs-state { 5551 pins = "gpio43"; 5552 function = "qup12"; 5553 }; 5554 5555 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5556 pins = "gpio43"; 5557 function = "gpio"; 5558 }; 5559 5560 qup_spi11_data_clk: qup-spi11-data-clk-state { 5561 pins = "gpio44", "gpio45", "gpio46"; 5562 function = "qup13"; 5563 }; 5564 5565 qup_spi11_cs: qup-spi11-cs-state { 5566 pins = "gpio47"; 5567 function = "qup13"; 5568 }; 5569 5570 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 5571 pins = "gpio47"; 5572 function = "gpio"; 5573 }; 5574 5575 qup_spi12_data_clk: qup-spi12-data-clk-state { 5576 pins = "gpio48", "gpio49", "gpio50"; 5577 function = "qup14"; 5578 }; 5579 5580 qup_spi12_cs: qup-spi12-cs-state { 5581 pins = "gpio51"; 5582 function = "qup14"; 5583 }; 5584 5585 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5586 pins = "gpio51"; 5587 function = "gpio"; 5588 }; 5589 5590 qup_spi13_data_clk: qup-spi13-data-clk-state { 5591 pins = "gpio52", "gpio53", "gpio54"; 5592 function = "qup15"; 5593 }; 5594 5595 qup_spi13_cs: qup-spi13-cs-state { 5596 pins = "gpio55"; 5597 function = "qup15"; 5598 }; 5599 5600 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5601 pins = "gpio55"; 5602 function = "gpio"; 5603 }; 5604 5605 qup_spi14_data_clk: qup-spi14-data-clk-state { 5606 pins = "gpio56", "gpio57", "gpio58"; 5607 function = "qup16"; 5608 }; 5609 5610 qup_spi14_cs: qup-spi14-cs-state { 5611 pins = "gpio59"; 5612 function = "qup16"; 5613 }; 5614 5615 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5616 pins = "gpio59"; 5617 function = "gpio"; 5618 }; 5619 5620 qup_spi15_data_clk: qup-spi15-data-clk-state { 5621 pins = "gpio60", "gpio61", "gpio62"; 5622 function = "qup17"; 5623 }; 5624 5625 qup_spi15_cs: qup-spi15-cs-state { 5626 pins = "gpio63"; 5627 function = "qup17"; 5628 }; 5629 5630 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5631 pins = "gpio63"; 5632 function = "gpio"; 5633 }; 5634 5635 qup_uart0_cts: qup-uart0-cts-state { 5636 pins = "gpio0"; 5637 function = "qup00"; 5638 }; 5639 5640 qup_uart0_rts: qup-uart0-rts-state { 5641 pins = "gpio1"; 5642 function = "qup00"; 5643 }; 5644 5645 qup_uart0_tx: qup-uart0-tx-state { 5646 pins = "gpio2"; 5647 function = "qup00"; 5648 }; 5649 5650 qup_uart0_rx: qup-uart0-rx-state { 5651 pins = "gpio3"; 5652 function = "qup00"; 5653 }; 5654 5655 qup_uart1_cts: qup-uart1-cts-state { 5656 pins = "gpio4"; 5657 function = "qup01"; 5658 }; 5659 5660 qup_uart1_rts: qup-uart1-rts-state { 5661 pins = "gpio5"; 5662 function = "qup01"; 5663 }; 5664 5665 qup_uart1_tx: qup-uart1-tx-state { 5666 pins = "gpio6"; 5667 function = "qup01"; 5668 }; 5669 5670 qup_uart1_rx: qup-uart1-rx-state { 5671 pins = "gpio7"; 5672 function = "qup01"; 5673 }; 5674 5675 qup_uart2_cts: qup-uart2-cts-state { 5676 pins = "gpio8"; 5677 function = "qup02"; 5678 }; 5679 5680 qup_uart2_rts: qup-uart2-rts-state { 5681 pins = "gpio9"; 5682 function = "qup02"; 5683 }; 5684 5685 qup_uart2_tx: qup-uart2-tx-state { 5686 pins = "gpio10"; 5687 function = "qup02"; 5688 }; 5689 5690 qup_uart2_rx: qup-uart2-rx-state { 5691 pins = "gpio11"; 5692 function = "qup02"; 5693 }; 5694 5695 qup_uart3_cts: qup-uart3-cts-state { 5696 pins = "gpio12"; 5697 function = "qup03"; 5698 }; 5699 5700 qup_uart3_rts: qup-uart3-rts-state { 5701 pins = "gpio13"; 5702 function = "qup03"; 5703 }; 5704 5705 qup_uart3_tx: qup-uart3-tx-state { 5706 pins = "gpio14"; 5707 function = "qup03"; 5708 }; 5709 5710 qup_uart3_rx: qup-uart3-rx-state { 5711 pins = "gpio15"; 5712 function = "qup03"; 5713 }; 5714 5715 qup_uart4_cts: qup-uart4-cts-state { 5716 pins = "gpio16"; 5717 function = "qup04"; 5718 }; 5719 5720 qup_uart4_rts: qup-uart4-rts-state { 5721 pins = "gpio17"; 5722 function = "qup04"; 5723 }; 5724 5725 qup_uart4_tx: qup-uart4-tx-state { 5726 pins = "gpio18"; 5727 function = "qup04"; 5728 }; 5729 5730 qup_uart4_rx: qup-uart4-rx-state { 5731 pins = "gpio19"; 5732 function = "qup04"; 5733 }; 5734 5735 qup_uart5_tx: qup-uart5-tx-state { 5736 pins = "gpio22"; 5737 function = "qup05"; 5738 }; 5739 5740 qup_uart5_rx: qup-uart5-rx-state { 5741 pins = "gpio23"; 5742 function = "qup05"; 5743 }; 5744 5745 qup_uart6_cts: qup-uart6-cts-state { 5746 pins = "gpio24"; 5747 function = "qup06"; 5748 }; 5749 5750 qup_uart6_rts: qup-uart6-rts-state { 5751 pins = "gpio25"; 5752 function = "qup06"; 5753 }; 5754 5755 qup_uart6_tx: qup-uart6-tx-state { 5756 pins = "gpio26"; 5757 function = "qup06"; 5758 }; 5759 5760 qup_uart6_rx: qup-uart6-rx-state { 5761 pins = "gpio27"; 5762 function = "qup06"; 5763 }; 5764 5765 qup_uart7_cts: qup-uart7-cts-state { 5766 pins = "gpio28"; 5767 function = "qup07"; 5768 }; 5769 5770 qup_uart7_rts: qup-uart7-rts-state { 5771 pins = "gpio29"; 5772 function = "qup07"; 5773 }; 5774 5775 qup_uart7_tx: qup-uart7-tx-state { 5776 pins = "gpio30"; 5777 function = "qup07"; 5778 }; 5779 5780 qup_uart7_rx: qup-uart7-rx-state { 5781 pins = "gpio31"; 5782 function = "qup07"; 5783 }; 5784 5785 qup_uart8_cts: qup-uart8-cts-state { 5786 pins = "gpio32"; 5787 function = "qup10"; 5788 }; 5789 5790 qup_uart8_rts: qup-uart8-rts-state { 5791 pins = "gpio33"; 5792 function = "qup10"; 5793 }; 5794 5795 qup_uart8_tx: qup-uart8-tx-state { 5796 pins = "gpio34"; 5797 function = "qup10"; 5798 }; 5799 5800 qup_uart8_rx: qup-uart8-rx-state { 5801 pins = "gpio35"; 5802 function = "qup10"; 5803 }; 5804 5805 qup_uart9_cts: qup-uart9-cts-state { 5806 pins = "gpio36"; 5807 function = "qup11"; 5808 }; 5809 5810 qup_uart9_rts: qup-uart9-rts-state { 5811 pins = "gpio37"; 5812 function = "qup11"; 5813 }; 5814 5815 qup_uart9_tx: qup-uart9-tx-state { 5816 pins = "gpio38"; 5817 function = "qup11"; 5818 }; 5819 5820 qup_uart9_rx: qup-uart9-rx-state { 5821 pins = "gpio39"; 5822 function = "qup11"; 5823 }; 5824 5825 qup_uart10_cts: qup-uart10-cts-state { 5826 pins = "gpio40"; 5827 function = "qup12"; 5828 }; 5829 5830 qup_uart10_rts: qup-uart10-rts-state { 5831 pins = "gpio41"; 5832 function = "qup12"; 5833 }; 5834 5835 qup_uart10_tx: qup-uart10-tx-state { 5836 pins = "gpio42"; 5837 function = "qup12"; 5838 }; 5839 5840 qup_uart10_rx: qup-uart10-rx-state { 5841 pins = "gpio43"; 5842 function = "qup12"; 5843 }; 5844 5845 qup_uart11_cts: qup-uart11-cts-state { 5846 pins = "gpio44"; 5847 function = "qup13"; 5848 }; 5849 5850 qup_uart11_rts: qup-uart11-rts-state { 5851 pins = "gpio45"; 5852 function = "qup13"; 5853 }; 5854 5855 qup_uart11_tx: qup-uart11-tx-state { 5856 pins = "gpio46"; 5857 function = "qup13"; 5858 }; 5859 5860 qup_uart11_rx: qup-uart11-rx-state { 5861 pins = "gpio47"; 5862 function = "qup13"; 5863 }; 5864 5865 qup_uart12_cts: qup-uart12-cts-state { 5866 pins = "gpio48"; 5867 function = "qup14"; 5868 }; 5869 5870 qup_uart12_rts: qup-uart12-rts-state { 5871 pins = "gpio49"; 5872 function = "qup14"; 5873 }; 5874 5875 qup_uart12_tx: qup-uart12-tx-state { 5876 pins = "gpio50"; 5877 function = "qup14"; 5878 }; 5879 5880 qup_uart12_rx: qup-uart12-rx-state { 5881 pins = "gpio51"; 5882 function = "qup14"; 5883 }; 5884 5885 qup_uart13_cts: qup-uart13-cts-state { 5886 pins = "gpio52"; 5887 function = "qup15"; 5888 }; 5889 5890 qup_uart13_rts: qup-uart13-rts-state { 5891 pins = "gpio53"; 5892 function = "qup15"; 5893 }; 5894 5895 qup_uart13_tx: qup-uart13-tx-state { 5896 pins = "gpio54"; 5897 function = "qup15"; 5898 }; 5899 5900 qup_uart13_rx: qup-uart13-rx-state { 5901 pins = "gpio55"; 5902 function = "qup15"; 5903 }; 5904 5905 qup_uart14_cts: qup-uart14-cts-state { 5906 pins = "gpio56"; 5907 function = "qup16"; 5908 }; 5909 5910 qup_uart14_rts: qup-uart14-rts-state { 5911 pins = "gpio57"; 5912 function = "qup16"; 5913 }; 5914 5915 qup_uart14_tx: qup-uart14-tx-state { 5916 pins = "gpio58"; 5917 function = "qup16"; 5918 }; 5919 5920 qup_uart14_rx: qup-uart14-rx-state { 5921 pins = "gpio59"; 5922 function = "qup16"; 5923 }; 5924 5925 qup_uart15_cts: qup-uart15-cts-state { 5926 pins = "gpio60"; 5927 function = "qup17"; 5928 }; 5929 5930 qup_uart15_rts: qup-uart15-rts-state { 5931 pins = "gpio61"; 5932 function = "qup17"; 5933 }; 5934 5935 qup_uart15_tx: qup-uart15-tx-state { 5936 pins = "gpio62"; 5937 function = "qup17"; 5938 }; 5939 5940 qup_uart15_rx: qup-uart15-rx-state { 5941 pins = "gpio63"; 5942 function = "qup17"; 5943 }; 5944 5945 sdc1_clk: sdc1-clk-state { 5946 pins = "sdc1_clk"; 5947 }; 5948 5949 sdc1_cmd: sdc1-cmd-state { 5950 pins = "sdc1_cmd"; 5951 }; 5952 5953 sdc1_data: sdc1-data-state { 5954 pins = "sdc1_data"; 5955 }; 5956 5957 sdc1_rclk: sdc1-rclk-state { 5958 pins = "sdc1_rclk"; 5959 }; 5960 5961 sdc1_clk_sleep: sdc1-clk-sleep-state { 5962 pins = "sdc1_clk"; 5963 drive-strength = <2>; 5964 bias-bus-hold; 5965 }; 5966 5967 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5968 pins = "sdc1_cmd"; 5969 drive-strength = <2>; 5970 bias-bus-hold; 5971 }; 5972 5973 sdc1_data_sleep: sdc1-data-sleep-state { 5974 pins = "sdc1_data"; 5975 drive-strength = <2>; 5976 bias-bus-hold; 5977 }; 5978 5979 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5980 pins = "sdc1_rclk"; 5981 drive-strength = <2>; 5982 bias-bus-hold; 5983 }; 5984 5985 sdc2_clk: sdc2-clk-state { 5986 pins = "sdc2_clk"; 5987 }; 5988 5989 sdc2_cmd: sdc2-cmd-state { 5990 pins = "sdc2_cmd"; 5991 }; 5992 5993 sdc2_data: sdc2-data-state { 5994 pins = "sdc2_data"; 5995 }; 5996 5997 sdc2_clk_sleep: sdc2-clk-sleep-state { 5998 pins = "sdc2_clk"; 5999 drive-strength = <2>; 6000 bias-bus-hold; 6001 }; 6002 6003 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 6004 pins = "sdc2_cmd"; 6005 drive-strength = <2>; 6006 bias-bus-hold; 6007 }; 6008 6009 sdc2_data_sleep: sdc2-data-sleep-state { 6010 pins = "sdc2_data"; 6011 drive-strength = <2>; 6012 bias-bus-hold; 6013 }; 6014 }; 6015 6016 sram@146a5000 { 6017 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 6018 reg = <0 0x146a5000 0 0x6000>; 6019 6020 #address-cells = <1>; 6021 #size-cells = <1>; 6022 6023 ranges = <0 0 0x146a5000 0x6000>; 6024 6025 pil-reloc@594c { 6026 compatible = "qcom,pil-reloc-info"; 6027 reg = <0x594c 0xc8>; 6028 }; 6029 }; 6030 6031 apps_smmu: iommu@15000000 { 6032 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 6033 reg = <0 0x15000000 0 0x100000>; 6034 #iommu-cells = <2>; 6035 #global-interrupts = <1>; 6036 dma-coherent; 6037 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 6038 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 6039 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 6040 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 6041 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 6042 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 6043 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 6044 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 6045 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6046 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6047 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6048 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 6049 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 6050 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 6051 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 6052 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 6053 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 6054 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 6055 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 6056 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 6057 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 6058 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 6059 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 6060 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 6061 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6062 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 6063 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6064 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6065 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6066 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 6067 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6068 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 6069 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6070 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 6071 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6072 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 6073 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 6074 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 6075 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 6076 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 6077 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 6078 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 6079 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 6080 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 6081 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 6082 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 6083 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 6084 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 6085 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 6086 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 6087 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 6088 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 6089 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 6090 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 6091 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 6092 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 6093 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 6094 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 6095 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 6096 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 6097 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 6098 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 6099 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 6100 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 6101 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 6102 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 6103 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 6104 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 6105 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 6106 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 6107 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 6108 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 6109 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 6110 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 6111 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 6112 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 6113 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 6114 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 6115 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 6116 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 6117 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 6118 }; 6119 6120 anoc_1_tbu: tbu@151dd000 { 6121 compatible = "qcom,sc7280-tbu"; 6122 reg = <0x0 0x151dd000 0x0 0x1000>; 6123 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6124 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6125 qcom,stream-id-range = <&apps_smmu 0x0 0x400>; 6126 }; 6127 6128 anoc_2_tbu: tbu@151e1000 { 6129 compatible = "qcom,sc7280-tbu"; 6130 reg = <0x0 0x151e1000 0x0 0x1000>; 6131 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6132 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6133 qcom,stream-id-range = <&apps_smmu 0x400 0x400>; 6134 }; 6135 6136 mnoc_hf_0_tbu: tbu@151e5000 { 6137 compatible = "qcom,sc7280-tbu"; 6138 reg = <0x0 0x151e5000 0x0 0x1000>; 6139 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 6140 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6141 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; 6142 qcom,stream-id-range = <&apps_smmu 0x800 0x400>; 6143 }; 6144 6145 mnoc_hf_1_tbu: tbu@151e9000 { 6146 compatible = "qcom,sc7280-tbu"; 6147 reg = <0x0 0x151e9000 0x0 0x1000>; 6148 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 6149 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6150 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; 6151 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; 6152 }; 6153 6154 compute_dsp_1_tbu: tbu@151ed000 { 6155 compatible = "qcom,sc7280-tbu"; 6156 reg = <0x0 0x151ed000 0x0 0x1000>; 6157 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6158 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6159 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>; 6160 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; 6161 }; 6162 6163 compute_dsp_0_tbu: tbu@151f1000 { 6164 compatible = "qcom,sc7280-tbu"; 6165 reg = <0x0 0x151f1000 0x0 0x1000>; 6166 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6167 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6168 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; 6169 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; 6170 }; 6171 6172 adsp_tbu: tbu@151f5000 { 6173 compatible = "qcom,sc7280-tbu"; 6174 reg = <0x0 0x151f5000 0x0 0x1000>; 6175 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6176 &lpass_ag_noc SLAVE_LPASS_CORE_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 6177 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; 6178 }; 6179 6180 anoc_1_pcie_tbu: tbu@151f9000 { 6181 compatible = "qcom,sc7280-tbu"; 6182 reg = <0x0 0x151f9000 0x0 0x1000>; 6183 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6184 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6185 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; 6186 }; 6187 6188 mnoc_sf_0_tbu: tbu@151fd000 { 6189 compatible = "qcom,sc7280-tbu"; 6190 reg = <0x0 0x151fd000 0x0 0x1000>; 6191 interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY 6192 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6193 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>; 6194 qcom,stream-id-range = <&apps_smmu 0x2000 0x400>; 6195 }; 6196 6197 intc: interrupt-controller@17a00000 { 6198 compatible = "arm,gic-v3"; 6199 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 6200 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 6201 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 6202 #interrupt-cells = <3>; 6203 interrupt-controller; 6204 #address-cells = <2>; 6205 #size-cells = <2>; 6206 ranges; 6207 6208 msi-controller@17a40000 { 6209 compatible = "arm,gic-v3-its"; 6210 reg = <0 0x17a40000 0 0x20000>; 6211 msi-controller; 6212 #msi-cells = <1>; 6213 status = "disabled"; 6214 }; 6215 }; 6216 6217 watchdog: watchdog@17c10000 { 6218 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 6219 reg = <0 0x17c10000 0 0x1000>; 6220 clocks = <&sleep_clk>; 6221 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6222 status = "reserved"; /* Owned by Gunyah hyp */ 6223 }; 6224 6225 timer@17c20000 { 6226 #address-cells = <1>; 6227 #size-cells = <1>; 6228 ranges = <0 0 0 0x20000000>; 6229 compatible = "arm,armv7-timer-mem"; 6230 reg = <0 0x17c20000 0 0x1000>; 6231 6232 frame@17c21000 { 6233 frame-number = <0>; 6234 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6235 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6236 reg = <0x17c21000 0x1000>, 6237 <0x17c22000 0x1000>; 6238 }; 6239 6240 frame@17c23000 { 6241 frame-number = <1>; 6242 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6243 reg = <0x17c23000 0x1000>; 6244 status = "disabled"; 6245 }; 6246 6247 frame@17c25000 { 6248 frame-number = <2>; 6249 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6250 reg = <0x17c25000 0x1000>; 6251 status = "disabled"; 6252 }; 6253 6254 frame@17c27000 { 6255 frame-number = <3>; 6256 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6257 reg = <0x17c27000 0x1000>; 6258 status = "disabled"; 6259 }; 6260 6261 frame@17c29000 { 6262 frame-number = <4>; 6263 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6264 reg = <0x17c29000 0x1000>; 6265 status = "disabled"; 6266 }; 6267 6268 frame@17c2b000 { 6269 frame-number = <5>; 6270 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6271 reg = <0x17c2b000 0x1000>; 6272 status = "disabled"; 6273 }; 6274 6275 frame@17c2d000 { 6276 frame-number = <6>; 6277 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6278 reg = <0x17c2d000 0x1000>; 6279 status = "disabled"; 6280 }; 6281 }; 6282 6283 apps_rsc: rsc@18200000 { 6284 compatible = "qcom,rpmh-rsc"; 6285 reg = <0 0x18200000 0 0x10000>, 6286 <0 0x18210000 0 0x10000>, 6287 <0 0x18220000 0 0x10000>; 6288 reg-names = "drv-0", "drv-1", "drv-2"; 6289 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6290 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6291 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6292 qcom,tcs-offset = <0xd00>; 6293 qcom,drv-id = <2>; 6294 qcom,tcs-config = <ACTIVE_TCS 2>, 6295 <SLEEP_TCS 3>, 6296 <WAKE_TCS 3>, 6297 <CONTROL_TCS 1>; 6298 power-domains = <&cluster_pd>; 6299 6300 apps_bcm_voter: bcm-voter { 6301 compatible = "qcom,bcm-voter"; 6302 }; 6303 6304 rpmhpd: power-controller { 6305 compatible = "qcom,sc7280-rpmhpd"; 6306 #power-domain-cells = <1>; 6307 operating-points-v2 = <&rpmhpd_opp_table>; 6308 6309 rpmhpd_opp_table: opp-table { 6310 compatible = "operating-points-v2"; 6311 6312 rpmhpd_opp_ret: opp1 { 6313 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6314 }; 6315 6316 rpmhpd_opp_low_svs: opp2 { 6317 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6318 }; 6319 6320 rpmhpd_opp_svs: opp3 { 6321 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6322 }; 6323 6324 rpmhpd_opp_svs_l1: opp4 { 6325 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6326 }; 6327 6328 rpmhpd_opp_svs_l2: opp5 { 6329 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 6330 }; 6331 6332 rpmhpd_opp_nom: opp6 { 6333 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6334 }; 6335 6336 rpmhpd_opp_nom_l1: opp7 { 6337 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6338 }; 6339 6340 rpmhpd_opp_turbo: opp8 { 6341 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6342 }; 6343 6344 rpmhpd_opp_turbo_l1: opp9 { 6345 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6346 }; 6347 }; 6348 }; 6349 6350 rpmhcc: clock-controller { 6351 compatible = "qcom,sc7280-rpmh-clk"; 6352 clocks = <&xo_board>; 6353 clock-names = "xo"; 6354 #clock-cells = <1>; 6355 }; 6356 }; 6357 6358 epss_l3: interconnect@18590000 { 6359 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 6360 reg = <0 0x18590000 0 0x1000>; 6361 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6362 clock-names = "xo", "alternate"; 6363 #interconnect-cells = <1>; 6364 }; 6365 6366 cpufreq_hw: cpufreq@18591000 { 6367 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 6368 reg = <0 0x18591000 0 0x1000>, 6369 <0 0x18592000 0 0x1000>, 6370 <0 0x18593000 0 0x1000>; 6371 6372 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 6373 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6374 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 6375 interrupt-names = "dcvsh-irq-0", 6376 "dcvsh-irq-1", 6377 "dcvsh-irq-2"; 6378 6379 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6380 clock-names = "xo", "alternate"; 6381 #freq-domain-cells = <1>; 6382 #clock-cells = <1>; 6383 }; 6384 }; 6385 6386 sound: sound { 6387 }; 6388 6389 thermal_zones: thermal-zones { 6390 cpu0-thermal { 6391 polling-delay-passive = <250>; 6392 6393 thermal-sensors = <&tsens0 1>; 6394 6395 trips { 6396 cpu0_alert0: trip-point0 { 6397 temperature = <90000>; 6398 hysteresis = <2000>; 6399 type = "passive"; 6400 }; 6401 6402 cpu0_alert1: trip-point1 { 6403 temperature = <95000>; 6404 hysteresis = <2000>; 6405 type = "passive"; 6406 }; 6407 6408 cpu0_crit: cpu-crit { 6409 temperature = <110000>; 6410 hysteresis = <0>; 6411 type = "critical"; 6412 }; 6413 }; 6414 6415 cooling-maps { 6416 map0 { 6417 trip = <&cpu0_alert0>; 6418 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6419 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6420 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6421 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6422 }; 6423 map1 { 6424 trip = <&cpu0_alert1>; 6425 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6426 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6427 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6428 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6429 }; 6430 }; 6431 }; 6432 6433 cpu1-thermal { 6434 polling-delay-passive = <250>; 6435 6436 thermal-sensors = <&tsens0 2>; 6437 6438 trips { 6439 cpu1_alert0: trip-point0 { 6440 temperature = <90000>; 6441 hysteresis = <2000>; 6442 type = "passive"; 6443 }; 6444 6445 cpu1_alert1: trip-point1 { 6446 temperature = <95000>; 6447 hysteresis = <2000>; 6448 type = "passive"; 6449 }; 6450 6451 cpu1_crit: cpu-crit { 6452 temperature = <110000>; 6453 hysteresis = <0>; 6454 type = "critical"; 6455 }; 6456 }; 6457 6458 cooling-maps { 6459 map0 { 6460 trip = <&cpu1_alert0>; 6461 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6462 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6463 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6464 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6465 }; 6466 map1 { 6467 trip = <&cpu1_alert1>; 6468 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6469 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6470 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6471 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6472 }; 6473 }; 6474 }; 6475 6476 cpu2-thermal { 6477 polling-delay-passive = <250>; 6478 6479 thermal-sensors = <&tsens0 3>; 6480 6481 trips { 6482 cpu2_alert0: trip-point0 { 6483 temperature = <90000>; 6484 hysteresis = <2000>; 6485 type = "passive"; 6486 }; 6487 6488 cpu2_alert1: trip-point1 { 6489 temperature = <95000>; 6490 hysteresis = <2000>; 6491 type = "passive"; 6492 }; 6493 6494 cpu2_crit: cpu-crit { 6495 temperature = <110000>; 6496 hysteresis = <0>; 6497 type = "critical"; 6498 }; 6499 }; 6500 6501 cooling-maps { 6502 map0 { 6503 trip = <&cpu2_alert0>; 6504 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6505 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6506 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6507 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6508 }; 6509 map1 { 6510 trip = <&cpu2_alert1>; 6511 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6512 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6513 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6514 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6515 }; 6516 }; 6517 }; 6518 6519 cpu3-thermal { 6520 polling-delay-passive = <250>; 6521 6522 thermal-sensors = <&tsens0 4>; 6523 6524 trips { 6525 cpu3_alert0: trip-point0 { 6526 temperature = <90000>; 6527 hysteresis = <2000>; 6528 type = "passive"; 6529 }; 6530 6531 cpu3_alert1: trip-point1 { 6532 temperature = <95000>; 6533 hysteresis = <2000>; 6534 type = "passive"; 6535 }; 6536 6537 cpu3_crit: cpu-crit { 6538 temperature = <110000>; 6539 hysteresis = <0>; 6540 type = "critical"; 6541 }; 6542 }; 6543 6544 cooling-maps { 6545 map0 { 6546 trip = <&cpu3_alert0>; 6547 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6548 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6549 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6550 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6551 }; 6552 map1 { 6553 trip = <&cpu3_alert1>; 6554 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6555 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6556 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6557 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6558 }; 6559 }; 6560 }; 6561 6562 cpu4-thermal { 6563 polling-delay-passive = <250>; 6564 6565 thermal-sensors = <&tsens0 7>; 6566 6567 trips { 6568 cpu4_alert0: trip-point0 { 6569 temperature = <90000>; 6570 hysteresis = <2000>; 6571 type = "passive"; 6572 }; 6573 6574 cpu4_alert1: trip-point1 { 6575 temperature = <95000>; 6576 hysteresis = <2000>; 6577 type = "passive"; 6578 }; 6579 6580 cpu4_crit: cpu-crit { 6581 temperature = <110000>; 6582 hysteresis = <0>; 6583 type = "critical"; 6584 }; 6585 }; 6586 6587 cooling-maps { 6588 map0 { 6589 trip = <&cpu4_alert0>; 6590 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6591 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6592 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6593 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6594 }; 6595 map1 { 6596 trip = <&cpu4_alert1>; 6597 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6598 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6599 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6600 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6601 }; 6602 }; 6603 }; 6604 6605 cpu5-thermal { 6606 polling-delay-passive = <250>; 6607 6608 thermal-sensors = <&tsens0 8>; 6609 6610 trips { 6611 cpu5_alert0: trip-point0 { 6612 temperature = <90000>; 6613 hysteresis = <2000>; 6614 type = "passive"; 6615 }; 6616 6617 cpu5_alert1: trip-point1 { 6618 temperature = <95000>; 6619 hysteresis = <2000>; 6620 type = "passive"; 6621 }; 6622 6623 cpu5_crit: cpu-crit { 6624 temperature = <110000>; 6625 hysteresis = <0>; 6626 type = "critical"; 6627 }; 6628 }; 6629 6630 cooling-maps { 6631 map0 { 6632 trip = <&cpu5_alert0>; 6633 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6634 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6635 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6636 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6637 }; 6638 map1 { 6639 trip = <&cpu5_alert1>; 6640 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6641 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6642 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6643 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6644 }; 6645 }; 6646 }; 6647 6648 cpu6-thermal { 6649 polling-delay-passive = <250>; 6650 6651 thermal-sensors = <&tsens0 9>; 6652 6653 trips { 6654 cpu6_alert0: trip-point0 { 6655 temperature = <90000>; 6656 hysteresis = <2000>; 6657 type = "passive"; 6658 }; 6659 6660 cpu6_alert1: trip-point1 { 6661 temperature = <95000>; 6662 hysteresis = <2000>; 6663 type = "passive"; 6664 }; 6665 6666 cpu6_crit: cpu-crit { 6667 temperature = <110000>; 6668 hysteresis = <0>; 6669 type = "critical"; 6670 }; 6671 }; 6672 6673 cooling-maps { 6674 map0 { 6675 trip = <&cpu6_alert0>; 6676 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6677 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6678 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6679 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6680 }; 6681 map1 { 6682 trip = <&cpu6_alert1>; 6683 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6684 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6685 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6686 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6687 }; 6688 }; 6689 }; 6690 6691 cpu7-thermal { 6692 polling-delay-passive = <250>; 6693 6694 thermal-sensors = <&tsens0 10>; 6695 6696 trips { 6697 cpu7_alert0: trip-point0 { 6698 temperature = <90000>; 6699 hysteresis = <2000>; 6700 type = "passive"; 6701 }; 6702 6703 cpu7_alert1: trip-point1 { 6704 temperature = <95000>; 6705 hysteresis = <2000>; 6706 type = "passive"; 6707 }; 6708 6709 cpu7_crit: cpu-crit { 6710 temperature = <110000>; 6711 hysteresis = <0>; 6712 type = "critical"; 6713 }; 6714 }; 6715 6716 cooling-maps { 6717 map0 { 6718 trip = <&cpu7_alert0>; 6719 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6720 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6721 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6722 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6723 }; 6724 map1 { 6725 trip = <&cpu7_alert1>; 6726 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6727 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6728 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6729 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6730 }; 6731 }; 6732 }; 6733 6734 cpu8-thermal { 6735 polling-delay-passive = <250>; 6736 6737 thermal-sensors = <&tsens0 11>; 6738 6739 trips { 6740 cpu8_alert0: trip-point0 { 6741 temperature = <90000>; 6742 hysteresis = <2000>; 6743 type = "passive"; 6744 }; 6745 6746 cpu8_alert1: trip-point1 { 6747 temperature = <95000>; 6748 hysteresis = <2000>; 6749 type = "passive"; 6750 }; 6751 6752 cpu8_crit: cpu-crit { 6753 temperature = <110000>; 6754 hysteresis = <0>; 6755 type = "critical"; 6756 }; 6757 }; 6758 6759 cooling-maps { 6760 map0 { 6761 trip = <&cpu8_alert0>; 6762 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6763 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6764 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6765 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6766 }; 6767 map1 { 6768 trip = <&cpu8_alert1>; 6769 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6770 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6771 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6772 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6773 }; 6774 }; 6775 }; 6776 6777 cpu9-thermal { 6778 polling-delay-passive = <250>; 6779 6780 thermal-sensors = <&tsens0 12>; 6781 6782 trips { 6783 cpu9_alert0: trip-point0 { 6784 temperature = <90000>; 6785 hysteresis = <2000>; 6786 type = "passive"; 6787 }; 6788 6789 cpu9_alert1: trip-point1 { 6790 temperature = <95000>; 6791 hysteresis = <2000>; 6792 type = "passive"; 6793 }; 6794 6795 cpu9_crit: cpu-crit { 6796 temperature = <110000>; 6797 hysteresis = <0>; 6798 type = "critical"; 6799 }; 6800 }; 6801 6802 cooling-maps { 6803 map0 { 6804 trip = <&cpu9_alert0>; 6805 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6806 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6807 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6808 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6809 }; 6810 map1 { 6811 trip = <&cpu9_alert1>; 6812 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6813 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6814 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6815 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6816 }; 6817 }; 6818 }; 6819 6820 cpu10-thermal { 6821 polling-delay-passive = <250>; 6822 6823 thermal-sensors = <&tsens0 13>; 6824 6825 trips { 6826 cpu10_alert0: trip-point0 { 6827 temperature = <90000>; 6828 hysteresis = <2000>; 6829 type = "passive"; 6830 }; 6831 6832 cpu10_alert1: trip-point1 { 6833 temperature = <95000>; 6834 hysteresis = <2000>; 6835 type = "passive"; 6836 }; 6837 6838 cpu10_crit: cpu-crit { 6839 temperature = <110000>; 6840 hysteresis = <0>; 6841 type = "critical"; 6842 }; 6843 }; 6844 6845 cooling-maps { 6846 map0 { 6847 trip = <&cpu10_alert0>; 6848 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6849 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6850 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6851 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6852 }; 6853 map1 { 6854 trip = <&cpu10_alert1>; 6855 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6856 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6857 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6858 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6859 }; 6860 }; 6861 }; 6862 6863 cpu11-thermal { 6864 polling-delay-passive = <250>; 6865 6866 thermal-sensors = <&tsens0 14>; 6867 6868 trips { 6869 cpu11_alert0: trip-point0 { 6870 temperature = <90000>; 6871 hysteresis = <2000>; 6872 type = "passive"; 6873 }; 6874 6875 cpu11_alert1: trip-point1 { 6876 temperature = <95000>; 6877 hysteresis = <2000>; 6878 type = "passive"; 6879 }; 6880 6881 cpu11_crit: cpu-crit { 6882 temperature = <110000>; 6883 hysteresis = <0>; 6884 type = "critical"; 6885 }; 6886 }; 6887 6888 cooling-maps { 6889 map0 { 6890 trip = <&cpu11_alert0>; 6891 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6892 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6893 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6894 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6895 }; 6896 map1 { 6897 trip = <&cpu11_alert1>; 6898 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6899 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6900 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6901 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6902 }; 6903 }; 6904 }; 6905 6906 aoss0-thermal { 6907 polling-delay-passive = <0>; 6908 6909 thermal-sensors = <&tsens0 0>; 6910 6911 trips { 6912 aoss0_alert0: trip-point0 { 6913 temperature = <90000>; 6914 hysteresis = <2000>; 6915 type = "hot"; 6916 }; 6917 6918 aoss0_crit: aoss0-crit { 6919 temperature = <110000>; 6920 hysteresis = <0>; 6921 type = "critical"; 6922 }; 6923 }; 6924 }; 6925 6926 aoss1-thermal { 6927 polling-delay-passive = <0>; 6928 6929 thermal-sensors = <&tsens1 0>; 6930 6931 trips { 6932 aoss1_alert0: trip-point0 { 6933 temperature = <90000>; 6934 hysteresis = <2000>; 6935 type = "hot"; 6936 }; 6937 6938 aoss1_crit: aoss1-crit { 6939 temperature = <110000>; 6940 hysteresis = <0>; 6941 type = "critical"; 6942 }; 6943 }; 6944 }; 6945 6946 cpuss0-thermal { 6947 polling-delay-passive = <0>; 6948 6949 thermal-sensors = <&tsens0 5>; 6950 6951 trips { 6952 cpuss0_alert0: trip-point0 { 6953 temperature = <90000>; 6954 hysteresis = <2000>; 6955 type = "hot"; 6956 }; 6957 cpuss0_crit: cluster0-crit { 6958 temperature = <110000>; 6959 hysteresis = <0>; 6960 type = "critical"; 6961 }; 6962 }; 6963 }; 6964 6965 cpuss1-thermal { 6966 polling-delay-passive = <0>; 6967 6968 thermal-sensors = <&tsens0 6>; 6969 6970 trips { 6971 cpuss1_alert0: trip-point0 { 6972 temperature = <90000>; 6973 hysteresis = <2000>; 6974 type = "hot"; 6975 }; 6976 cpuss1_crit: cluster0-crit { 6977 temperature = <110000>; 6978 hysteresis = <0>; 6979 type = "critical"; 6980 }; 6981 }; 6982 }; 6983 6984 gpuss0-thermal { 6985 polling-delay-passive = <100>; 6986 6987 thermal-sensors = <&tsens1 1>; 6988 6989 trips { 6990 gpuss0_alert0: trip-point0 { 6991 temperature = <95000>; 6992 hysteresis = <2000>; 6993 type = "passive"; 6994 }; 6995 6996 gpuss0_crit: gpuss0-crit { 6997 temperature = <110000>; 6998 hysteresis = <0>; 6999 type = "critical"; 7000 }; 7001 }; 7002 7003 cooling-maps { 7004 map0 { 7005 trip = <&gpuss0_alert0>; 7006 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7007 }; 7008 }; 7009 }; 7010 7011 gpuss1-thermal { 7012 polling-delay-passive = <100>; 7013 7014 thermal-sensors = <&tsens1 2>; 7015 7016 trips { 7017 gpuss1_alert0: trip-point0 { 7018 temperature = <95000>; 7019 hysteresis = <2000>; 7020 type = "passive"; 7021 }; 7022 7023 gpuss1_crit: gpuss1-crit { 7024 temperature = <110000>; 7025 hysteresis = <0>; 7026 type = "critical"; 7027 }; 7028 }; 7029 7030 cooling-maps { 7031 map0 { 7032 trip = <&gpuss1_alert0>; 7033 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7034 }; 7035 }; 7036 }; 7037 7038 nspss0-thermal { 7039 thermal-sensors = <&tsens1 3>; 7040 7041 trips { 7042 nspss0_alert0: trip-point0 { 7043 temperature = <90000>; 7044 hysteresis = <2000>; 7045 type = "hot"; 7046 }; 7047 7048 nspss0_crit: nspss0-crit { 7049 temperature = <110000>; 7050 hysteresis = <0>; 7051 type = "critical"; 7052 }; 7053 }; 7054 }; 7055 7056 nspss1-thermal { 7057 thermal-sensors = <&tsens1 4>; 7058 7059 trips { 7060 nspss1_alert0: trip-point0 { 7061 temperature = <90000>; 7062 hysteresis = <2000>; 7063 type = "hot"; 7064 }; 7065 7066 nspss1_crit: nspss1-crit { 7067 temperature = <110000>; 7068 hysteresis = <0>; 7069 type = "critical"; 7070 }; 7071 }; 7072 }; 7073 7074 video-thermal { 7075 thermal-sensors = <&tsens1 5>; 7076 7077 trips { 7078 video_alert0: trip-point0 { 7079 temperature = <90000>; 7080 hysteresis = <2000>; 7081 type = "hot"; 7082 }; 7083 7084 video_crit: video-crit { 7085 temperature = <110000>; 7086 hysteresis = <0>; 7087 type = "critical"; 7088 }; 7089 }; 7090 }; 7091 7092 ddr-thermal { 7093 thermal-sensors = <&tsens1 6>; 7094 7095 trips { 7096 ddr_alert0: trip-point0 { 7097 temperature = <90000>; 7098 hysteresis = <2000>; 7099 type = "hot"; 7100 }; 7101 7102 ddr_crit: ddr-crit { 7103 temperature = <110000>; 7104 hysteresis = <0>; 7105 type = "critical"; 7106 }; 7107 }; 7108 }; 7109 7110 mdmss0-thermal { 7111 thermal-sensors = <&tsens1 7>; 7112 7113 trips { 7114 mdmss0_alert0: trip-point0 { 7115 temperature = <90000>; 7116 hysteresis = <2000>; 7117 type = "hot"; 7118 }; 7119 7120 mdmss0_crit: mdmss0-crit { 7121 temperature = <110000>; 7122 hysteresis = <0>; 7123 type = "critical"; 7124 }; 7125 }; 7126 }; 7127 7128 mdmss1-thermal { 7129 thermal-sensors = <&tsens1 8>; 7130 7131 trips { 7132 mdmss1_alert0: trip-point0 { 7133 temperature = <90000>; 7134 hysteresis = <2000>; 7135 type = "hot"; 7136 }; 7137 7138 mdmss1_crit: mdmss1-crit { 7139 temperature = <110000>; 7140 hysteresis = <0>; 7141 type = "critical"; 7142 }; 7143 }; 7144 }; 7145 7146 mdmss2-thermal { 7147 thermal-sensors = <&tsens1 9>; 7148 7149 trips { 7150 mdmss2_alert0: trip-point0 { 7151 temperature = <90000>; 7152 hysteresis = <2000>; 7153 type = "hot"; 7154 }; 7155 7156 mdmss2_crit: mdmss2-crit { 7157 temperature = <110000>; 7158 hysteresis = <0>; 7159 type = "critical"; 7160 }; 7161 }; 7162 }; 7163 7164 mdmss3-thermal { 7165 thermal-sensors = <&tsens1 10>; 7166 7167 trips { 7168 mdmss3_alert0: trip-point0 { 7169 temperature = <90000>; 7170 hysteresis = <2000>; 7171 type = "hot"; 7172 }; 7173 7174 mdmss3_crit: mdmss3-crit { 7175 temperature = <110000>; 7176 hysteresis = <0>; 7177 type = "critical"; 7178 }; 7179 }; 7180 }; 7181 7182 camera0-thermal { 7183 thermal-sensors = <&tsens1 11>; 7184 7185 trips { 7186 camera0_alert0: trip-point0 { 7187 temperature = <90000>; 7188 hysteresis = <2000>; 7189 type = "hot"; 7190 }; 7191 7192 camera0_crit: camera0-crit { 7193 temperature = <110000>; 7194 hysteresis = <0>; 7195 type = "critical"; 7196 }; 7197 }; 7198 }; 7199 }; 7200 7201 timer { 7202 compatible = "arm,armv8-timer"; 7203 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 7204 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 7205 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 7206 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 7207 }; 7208}; 7209