1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2018-2021, Intel Corporation. */ 3 4 #ifndef _ICE_PTP_CONSTS_H_ 5 #define _ICE_PTP_CONSTS_H_ 6 7 /* Constant definitions related to the hardware clock used for PTP 1588 8 * features and functionality. 9 */ 10 /* Constants defined for the PTP 1588 clock hardware. */ 11 12 const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES] = { 13 [ETH56G_PHY_REG_PTP] = { 14 .base_addr = 0x092000, 15 .step = 0x98, 16 }, 17 [ETH56G_PHY_MEM_PTP] = { 18 .base_addr = 0x093000, 19 .step = 0x200, 20 }, 21 [ETH56G_PHY_REG_XPCS] = { 22 .base_addr = 0x000000, 23 .step = 0x21000, 24 }, 25 [ETH56G_PHY_REG_MAC] = { 26 .base_addr = 0x085000, 27 .step = 0x1000, 28 }, 29 [ETH56G_PHY_REG_GPCS] = { 30 .base_addr = 0x084000, 31 .step = 0x400, 32 }, 33 }; 34 35 const 36 struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD] = { 37 [ICE_ETH56G_LNK_SPD_1G] = { 38 .tx_mode = { .def = 6, }, 39 .rx_mode = { .def = 6, }, 40 .blks_per_clk = 1, 41 .blktime = 0x4000, /* 32 */ 42 .tx_offset = { 43 .serdes = 0x6666, /* 51.2 */ 44 .no_fec = 0xd066, /* 104.2 */ 45 .sfd = 0x3000, /* 24 */ 46 .onestep = 0x30000 /* 384 */ 47 }, 48 .rx_offset = { 49 .serdes = 0xffffc59a, /* -29.2 */ 50 .no_fec = 0xffff0a80, /* -122.75 */ 51 .sfd = 0x2c00, /* 22 */ 52 .bs_ds = 0x19a /* 0.8 */ 53 /* Dynamic bitslip 0 equals to 10 */ 54 } 55 }, 56 [ICE_ETH56G_LNK_SPD_2_5G] = { 57 .tx_mode = { .def = 6, }, 58 .rx_mode = { .def = 6, }, 59 .blks_per_clk = 1, 60 .blktime = 0x199a, /* 12.8 */ 61 .tx_offset = { 62 .serdes = 0x28f6, /* 20.48 */ 63 .no_fec = 0x53b8, /* 41.86 */ 64 .sfd = 0x1333, /* 9.6 */ 65 .onestep = 0x13333 /* 153.6 */ 66 }, 67 .rx_offset = { 68 .serdes = 0xffffe8a4, /* -11.68 */ 69 .no_fec = 0xffff9a76, /* -50.77 */ 70 .sfd = 0xf33, /* 7.6 */ 71 .bs_ds = 0xa4 /* 0.32 */ 72 } 73 }, 74 [ICE_ETH56G_LNK_SPD_10G] = { 75 .tx_mode = { .def = 1, }, 76 .rx_mode = { .def = 1, }, 77 .blks_per_clk = 1, 78 .blktime = 0x666, /* 3.2 */ 79 .tx_offset = { 80 .serdes = 0x234c, /* 17.6484848 */ 81 .no_fec = 0x8e80, /* 71.25 */ 82 .fc = 0xb4a4, /* 90.32 */ 83 .sfd = 0x4a4, /* 2.32 */ 84 .onestep = 0x4ccd /* 38.4 */ 85 }, 86 .rx_offset = { 87 .serdes = 0xffffeb27, /* -10.42424 */ 88 .no_fec = 0xffffcccd, /* -25.6 */ 89 .fc = 0xfffc557b, /* -469.26 */ 90 .sfd = 0x4a4, /* 2.32 */ 91 .bs_ds = 0x32 /* 0.0969697 */ 92 } 93 }, 94 [ICE_ETH56G_LNK_SPD_25G] = { 95 .tx_mode = { 96 .def = 1, 97 .rs = 4 98 }, 99 .tx_mk_dly = 4, 100 .tx_cw_dly = { 101 .def = 1, 102 .onestep = 6 103 }, 104 .rx_mode = { 105 .def = 1, 106 .rs = 4 107 }, 108 .rx_mk_dly = { 109 .def = 1, 110 .rs = 1 111 }, 112 .rx_cw_dly = { 113 .def = 1, 114 .rs = 1 115 }, 116 .blks_per_clk = 1, 117 .blktime = 0x28f, /* 1.28 */ 118 .mktime = 0x147b, /* 10.24, only if RS-FEC enabled */ 119 .tx_offset = { 120 .serdes = 0xe1e, /* 7.0593939 */ 121 .no_fec = 0x3857, /* 28.17 */ 122 .fc = 0x48c3, /* 36.38 */ 123 .rs = 0x8100, /* 64.5 */ 124 .sfd = 0x1dc, /* 0.93 */ 125 .onestep = 0x1eb8 /* 15.36 */ 126 }, 127 .rx_offset = { 128 .serdes = 0xfffff7a9, /* -4.1697 */ 129 .no_fec = 0xffffe71a, /* -12.45 */ 130 .fc = 0xfffe894d, /* -187.35 */ 131 .rs = 0xfffff8cd, /* -3.6 */ 132 .sfd = 0x1dc, /* 0.93 */ 133 .bs_ds = 0x14 /* 0.0387879, RS-FEC 0 */ 134 } 135 }, 136 [ICE_ETH56G_LNK_SPD_40G] = { 137 .tx_mode = { .def = 3 }, 138 .tx_mk_dly = 4, 139 .tx_cw_dly = { 140 .def = 1, 141 .onestep = 6 142 }, 143 .rx_mode = { .def = 4 }, 144 .rx_mk_dly = { .def = 1 }, 145 .rx_cw_dly = { .def = 1 }, 146 .blktime = 0x333, /* 1.6 */ 147 .mktime = 0xccd, /* 6.4 */ 148 .tx_offset = { 149 .serdes = 0x234c, /* 17.6484848 */ 150 .no_fec = 0x5a8a, /* 45.27 */ 151 .fc = 0x81b8, /* 64.86 */ 152 .sfd = 0x4a4, /* 2.32 */ 153 .onestep = 0x1333 /* 9.6 */ 154 }, 155 .rx_offset = { 156 .serdes = 0xffffeb27, /* -10.42424 */ 157 .no_fec = 0xfffff594, /* -5.21 */ 158 .fc = 0xfffe3080, /* -231.75 */ 159 .sfd = 0x4a4, /* 2.32 */ 160 .bs_ds = 0xccd /* 6.4 */ 161 } 162 }, 163 [ICE_ETH56G_LNK_SPD_50G] = { 164 .tx_mode = { .def = 5 }, 165 .tx_mk_dly = 4, 166 .tx_cw_dly = { 167 .def = 1, 168 .onestep = 6 169 }, 170 .rx_mode = { .def = 5 }, 171 .rx_mk_dly = { .def = 1 }, 172 .rx_cw_dly = { .def = 1 }, 173 .blktime = 0x28f, /* 1.28 */ 174 .mktime = 0xa3d, /* 5.12 */ 175 .tx_offset = { 176 .serdes = 0x13ba, /* 9.86353 */ 177 .rs = 0x5400, /* 42 */ 178 .sfd = 0xe6, /* 0.45 */ 179 .onestep = 0xf5c /* 7.68 */ 180 }, 181 .rx_offset = { 182 .serdes = 0xfffff7e8, /* -4.04706 */ 183 .rs = 0xfffff994, /* -3.21 */ 184 .sfd = 0xe6 /* 0.45 */ 185 } 186 }, 187 [ICE_ETH56G_LNK_SPD_50G2] = { 188 .tx_mode = { 189 .def = 3, 190 .rs = 2 191 }, 192 .tx_mk_dly = 4, 193 .tx_cw_dly = { 194 .def = 1, 195 .onestep = 6 196 }, 197 .rx_mode = { 198 .def = 4, 199 .rs = 1 200 }, 201 .rx_mk_dly = { .def = 1 }, 202 .rx_cw_dly = { .def = 1 }, 203 .blktime = 0x28f, /* 1.28 */ 204 .mktime = 0xa3d, /* 5.12 */ 205 .tx_offset = { 206 .serdes = 0xe1e, /* 7.0593939 */ 207 .no_fec = 0x3d33, /* 30.6 */ 208 .rs = 0x5057, /* 40.17 */ 209 .sfd = 0x1dc, /* 0.93 */ 210 .onestep = 0xf5c /* 7.68 */ 211 }, 212 .rx_offset = { 213 .serdes = 0xfffff7a9, /* -4.1697 */ 214 .no_fec = 0xfffff8cd, /* -3.6 */ 215 .rs = 0xfffff21a, /* -6.95 */ 216 .sfd = 0x1dc, /* 0.93 */ 217 .bs_ds = 0xa3d /* 5.12, RS-FEC 0x633 (3.1) */ 218 } 219 }, 220 [ICE_ETH56G_LNK_SPD_100G] = { 221 .tx_mode = { 222 .def = 3, 223 .rs = 2 224 }, 225 .tx_mk_dly = 10, 226 .tx_cw_dly = { 227 .def = 3, 228 .onestep = 6 229 }, 230 .rx_mode = { 231 .def = 4, 232 .rs = 1 233 }, 234 .rx_mk_dly = { .def = 5 }, 235 .rx_cw_dly = { .def = 5 }, 236 .blks_per_clk = 1, 237 .blktime = 0x148, /* 0.64 */ 238 .mktime = 0x199a, /* 12.8 */ 239 .tx_offset = { 240 .serdes = 0xe1e, /* 7.0593939 */ 241 .no_fec = 0x67ec, /* 51.96 */ 242 .rs = 0x44fb, /* 34.49 */ 243 .sfd = 0x1dc, /* 0.93 */ 244 .onestep = 0xf5c /* 7.68 */ 245 }, 246 .rx_offset = { 247 .serdes = 0xfffff7a9, /* -4.1697 */ 248 .no_fec = 0xfffff5a9, /* -5.17 */ 249 .rs = 0xfffff6e6, /* -4.55 */ 250 .sfd = 0x1dc, /* 0.93 */ 251 .bs_ds = 0x199a /* 12.8, RS-FEC 0x31b (1.552) */ 252 } 253 }, 254 [ICE_ETH56G_LNK_SPD_100G2] = { 255 .tx_mode = { .def = 5 }, 256 .tx_mk_dly = 10, 257 .tx_cw_dly = { 258 .def = 3, 259 .onestep = 6 260 }, 261 .rx_mode = { .def = 5 }, 262 .rx_mk_dly = { .def = 5 }, 263 .rx_cw_dly = { .def = 5 }, 264 .blks_per_clk = 1, 265 .blktime = 0x148, /* 0.64 */ 266 .mktime = 0x199a, /* 12.8 */ 267 .tx_offset = { 268 .serdes = 0x13ba, /* 9.86353 */ 269 .rs = 0x460a, /* 35.02 */ 270 .sfd = 0xe6, /* 0.45 */ 271 .onestep = 0xf5c /* 7.68 */ 272 }, 273 .rx_offset = { 274 .serdes = 0xfffff7e8, /* -4.04706 */ 275 .rs = 0xfffff548, /* -5.36 */ 276 .sfd = 0xe6, /* 0.45 */ 277 .bs_ds = 0x303 /* 1.506 */ 278 } 279 } 280 }; 281 282 /* struct ice_time_ref_info_e82x 283 * 284 * E82X hardware can use different sources as the reference for the PTP 285 * hardware clock. Each clock has different characteristics such as a slightly 286 * different frequency, etc. 287 * 288 * This lookup table defines several constants that depend on the current time 289 * reference. See the struct ice_time_ref_info_e82x for information about the 290 * meaning of each constant. 291 */ 292 const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TSPLL_FREQ] = { 293 /* ICE_TSPLL_FREQ_25_000 -> 25 MHz */ 294 { 295 /* pll_freq */ 296 823437500, /* 823.4375 MHz PLL */ 297 /* nominal_incval */ 298 0x136e44fabULL, 299 }, 300 301 /* ICE_TSPLL_FREQ_122_880 -> 122.88 MHz */ 302 { 303 /* pll_freq */ 304 783360000, /* 783.36 MHz */ 305 /* nominal_incval */ 306 0x146cc2177ULL, 307 }, 308 309 /* ICE_TSPLL_FREQ_125_000 -> 125 MHz */ 310 { 311 /* pll_freq */ 312 796875000, /* 796.875 MHz */ 313 /* nominal_incval */ 314 0x141414141ULL, 315 }, 316 317 /* ICE_TSPLL_FREQ_153_600 -> 153.6 MHz */ 318 { 319 /* pll_freq */ 320 816000000, /* 816 MHz */ 321 /* nominal_incval */ 322 0x139b9b9baULL, 323 }, 324 325 /* ICE_TSPLL_FREQ_156_250 -> 156.25 MHz */ 326 { 327 /* pll_freq */ 328 830078125, /* 830.78125 MHz */ 329 /* nominal_incval */ 330 0x134679aceULL, 331 }, 332 333 /* ICE_TSPLL_FREQ_245_760 -> 245.76 MHz */ 334 { 335 /* pll_freq */ 336 783360000, /* 783.36 MHz */ 337 /* nominal_incval */ 338 0x146cc2177ULL, 339 }, 340 }; 341 342 /* struct ice_vernier_info_e82x 343 * 344 * E822 hardware calibrates the delay of the timestamp indication from the 345 * actual packet transmission or reception during the initialization of the 346 * PHY. To do this, the hardware mechanism uses some conversions between the 347 * various clocks within the PHY block. This table defines constants used to 348 * calculate the correct conversion ratios in the PHY registers. 349 * 350 * Many of the values relate to the PAR/PCS clock conversion registers. For 351 * these registers, a value of 0 means that the associated register is not 352 * used by this link speed, and that the register should be cleared by writing 353 * 0. Other values specify the clock frequency in Hz. 354 */ 355 const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD] = { 356 /* ICE_PTP_LNK_SPD_1G */ 357 { 358 /* tx_par_clk */ 359 31250000, /* 31.25 MHz */ 360 /* rx_par_clk */ 361 31250000, /* 31.25 MHz */ 362 /* tx_pcs_clk */ 363 125000000, /* 125 MHz */ 364 /* rx_pcs_clk */ 365 125000000, /* 125 MHz */ 366 /* tx_desk_rsgb_par */ 367 0, /* unused */ 368 /* rx_desk_rsgb_par */ 369 0, /* unused */ 370 /* tx_desk_rsgb_pcs */ 371 0, /* unused */ 372 /* rx_desk_rsgb_pcs */ 373 0, /* unused */ 374 /* tx_fixed_delay */ 375 25140, 376 /* pmd_adj_divisor */ 377 10000000, 378 /* rx_fixed_delay */ 379 17372, 380 }, 381 /* ICE_PTP_LNK_SPD_10G */ 382 { 383 /* tx_par_clk */ 384 257812500, /* 257.8125 MHz */ 385 /* rx_par_clk */ 386 257812500, /* 257.8125 MHz */ 387 /* tx_pcs_clk */ 388 156250000, /* 156.25 MHz */ 389 /* rx_pcs_clk */ 390 156250000, /* 156.25 MHz */ 391 /* tx_desk_rsgb_par */ 392 0, /* unused */ 393 /* rx_desk_rsgb_par */ 394 0, /* unused */ 395 /* tx_desk_rsgb_pcs */ 396 0, /* unused */ 397 /* rx_desk_rsgb_pcs */ 398 0, /* unused */ 399 /* tx_fixed_delay */ 400 6938, 401 /* pmd_adj_divisor */ 402 82500000, 403 /* rx_fixed_delay */ 404 6212, 405 }, 406 /* ICE_PTP_LNK_SPD_25G */ 407 { 408 /* tx_par_clk */ 409 644531250, /* 644.53125 MHZ */ 410 /* rx_par_clk */ 411 644531250, /* 644.53125 MHz */ 412 /* tx_pcs_clk */ 413 390625000, /* 390.625 MHz */ 414 /* rx_pcs_clk */ 415 390625000, /* 390.625 MHz */ 416 /* tx_desk_rsgb_par */ 417 0, /* unused */ 418 /* rx_desk_rsgb_par */ 419 0, /* unused */ 420 /* tx_desk_rsgb_pcs */ 421 0, /* unused */ 422 /* rx_desk_rsgb_pcs */ 423 0, /* unused */ 424 /* tx_fixed_delay */ 425 2778, 426 /* pmd_adj_divisor */ 427 206250000, 428 /* rx_fixed_delay */ 429 2491, 430 }, 431 /* ICE_PTP_LNK_SPD_25G_RS */ 432 { 433 /* tx_par_clk */ 434 0, /* unused */ 435 /* rx_par_clk */ 436 0, /* unused */ 437 /* tx_pcs_clk */ 438 0, /* unused */ 439 /* rx_pcs_clk */ 440 0, /* unused */ 441 /* tx_desk_rsgb_par */ 442 161132812, /* 162.1328125 MHz Reed Solomon gearbox */ 443 /* rx_desk_rsgb_par */ 444 161132812, /* 162.1328125 MHz Reed Solomon gearbox */ 445 /* tx_desk_rsgb_pcs */ 446 97656250, /* 97.62625 MHz Reed Solomon gearbox */ 447 /* rx_desk_rsgb_pcs */ 448 97656250, /* 97.62625 MHz Reed Solomon gearbox */ 449 /* tx_fixed_delay */ 450 3928, 451 /* pmd_adj_divisor */ 452 206250000, 453 /* rx_fixed_delay */ 454 29535, 455 }, 456 /* ICE_PTP_LNK_SPD_40G */ 457 { 458 /* tx_par_clk */ 459 257812500, 460 /* rx_par_clk */ 461 257812500, 462 /* tx_pcs_clk */ 463 156250000, /* 156.25 MHz */ 464 /* rx_pcs_clk */ 465 156250000, /* 156.25 MHz */ 466 /* tx_desk_rsgb_par */ 467 0, /* unused */ 468 /* rx_desk_rsgb_par */ 469 156250000, /* 156.25 MHz deskew clock */ 470 /* tx_desk_rsgb_pcs */ 471 0, /* unused */ 472 /* rx_desk_rsgb_pcs */ 473 156250000, /* 156.25 MHz deskew clock */ 474 /* tx_fixed_delay */ 475 5666, 476 /* pmd_adj_divisor */ 477 82500000, 478 /* rx_fixed_delay */ 479 4244, 480 }, 481 /* ICE_PTP_LNK_SPD_50G */ 482 { 483 /* tx_par_clk */ 484 644531250, /* 644.53125 MHZ */ 485 /* rx_par_clk */ 486 644531250, /* 644.53125 MHZ */ 487 /* tx_pcs_clk */ 488 390625000, /* 390.625 MHz */ 489 /* rx_pcs_clk */ 490 390625000, /* 390.625 MHz */ 491 /* tx_desk_rsgb_par */ 492 0, /* unused */ 493 /* rx_desk_rsgb_par */ 494 195312500, /* 193.3125 MHz deskew clock */ 495 /* tx_desk_rsgb_pcs */ 496 0, /* unused */ 497 /* rx_desk_rsgb_pcs */ 498 195312500, /* 193.3125 MHz deskew clock */ 499 /* tx_fixed_delay */ 500 2778, 501 /* pmd_adj_divisor */ 502 206250000, 503 /* rx_fixed_delay */ 504 2868, 505 }, 506 /* ICE_PTP_LNK_SPD_50G_RS */ 507 { 508 /* tx_par_clk */ 509 0, /* unused */ 510 /* rx_par_clk */ 511 644531250, /* 644.53125 MHz */ 512 /* tx_pcs_clk */ 513 0, /* unused */ 514 /* rx_pcs_clk */ 515 644531250, /* 644.53125 MHz */ 516 /* tx_desk_rsgb_par */ 517 322265625, /* 322.265625 MHz Reed Solomon gearbox */ 518 /* rx_desk_rsgb_par */ 519 322265625, /* 322.265625 MHz Reed Solomon gearbox */ 520 /* tx_desk_rsgb_pcs */ 521 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 522 /* rx_desk_rsgb_pcs */ 523 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 524 /* tx_fixed_delay */ 525 2095, 526 /* pmd_adj_divisor */ 527 206250000, 528 /* rx_fixed_delay */ 529 14524, 530 }, 531 /* ICE_PTP_LNK_SPD_100G_RS */ 532 { 533 /* tx_par_clk */ 534 0, /* unused */ 535 /* rx_par_clk */ 536 644531250, /* 644.53125 MHz */ 537 /* tx_pcs_clk */ 538 0, /* unused */ 539 /* rx_pcs_clk */ 540 644531250, /* 644.53125 MHz */ 541 /* tx_desk_rsgb_par */ 542 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 543 /* rx_desk_rsgb_par */ 544 644531250, /* 644.53125 MHz Reed Solomon gearbox */ 545 /* tx_desk_rsgb_pcs */ 546 390625000, /* 390.625 MHz Reed Solomon gearbox */ 547 /* rx_desk_rsgb_pcs */ 548 390625000, /* 390.625 MHz Reed Solomon gearbox */ 549 /* tx_fixed_delay */ 550 1620, 551 /* pmd_adj_divisor */ 552 206250000, 553 /* rx_fixed_delay */ 554 7775, 555 }, 556 }; 557 558 #endif /* _ICE_PTP_CONSTS_H_ */ 559