1 /*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/etherdevice.h>
34 #include <linux/idr.h>
35 #include <linux/mlx5/driver.h>
36 #include <linux/mlx5/mlx5_ifc.h>
37 #include <linux/mlx5/vport.h>
38 #include <linux/mlx5/fs.h>
39 #include "mlx5_core.h"
40 #include "eswitch.h"
41 #include "esw/indir_table.h"
42 #include "esw/acl/ofld.h"
43 #include "rdma.h"
44 #include "en.h"
45 #include "fs_core.h"
46 #include "lib/mlx5.h"
47 #include "lib/devcom.h"
48 #include "lib/eq.h"
49 #include "lib/fs_chains.h"
50 #include "en_tc.h"
51 #include "en/mapping.h"
52 #include "devlink.h"
53 #include "lag/lag.h"
54 #include "en/tc/post_meter.h"
55
56 /* There are two match-all miss flows, one for unicast dst mac and
57 * one for multicast.
58 */
59 #define MLX5_ESW_MISS_FLOWS (2)
60 #define UPLINK_REP_INDEX 0
61
62 #define MLX5_ESW_VPORT_TBL_SIZE 128
63 #define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
64
65 #define MLX5_ESW_FT_OFFLOADS_DROP_RULE (1)
66
67 #define MLX5_ESW_MAX_CTRL_EQS 4
68 #define MLX5_ESW_DEFAULT_SF_COMP_EQS 8
69
70 static struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = {
71 .max_fte = MLX5_ESW_VPORT_TBL_SIZE,
72 .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS,
73 .flags = 0,
74 };
75
mlx5_eswitch_get_rep(struct mlx5_eswitch * esw,u16 vport_num)76 static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
77 u16 vport_num)
78 {
79 return xa_load(&esw->offloads.vport_reps, vport_num);
80 }
81
82 static void
mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch * esw,struct mlx5_flow_spec * spec,struct mlx5_esw_flow_attr * attr)83 mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
84 struct mlx5_flow_spec *spec,
85 struct mlx5_esw_flow_attr *attr)
86 {
87 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) || !attr || !attr->in_rep)
88 return;
89
90 if (attr->int_port) {
91 spec->flow_context.flow_source = mlx5e_tc_int_port_get_flow_source(attr->int_port);
92
93 return;
94 }
95
96 spec->flow_context.flow_source = (attr->in_rep->vport == MLX5_VPORT_UPLINK) ?
97 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
98 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
99 }
100
101 /* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits
102 * are not needed as well in the following process. So clear them all for simplicity.
103 */
104 void
mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch * esw,struct mlx5_flow_spec * spec)105 mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec)
106 {
107 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
108 void *misc2;
109
110 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
111 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
112
113 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
114 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
115
116 if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2)))
117 spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2;
118 }
119 }
120
121 static void
mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch * esw,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr,struct mlx5_eswitch * src_esw,u16 vport)122 mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
123 struct mlx5_flow_spec *spec,
124 struct mlx5_flow_attr *attr,
125 struct mlx5_eswitch *src_esw,
126 u16 vport)
127 {
128 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
129 u32 metadata;
130 void *misc2;
131 void *misc;
132
133 /* Use metadata matching because vport is not represented by single
134 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
135 */
136 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
137 if (mlx5_esw_indir_table_decap_vport(attr))
138 vport = mlx5_esw_indir_table_decap_vport(attr);
139
140 if (!attr->chain && esw_attr && esw_attr->int_port)
141 metadata =
142 mlx5e_tc_int_port_get_metadata_for_match(esw_attr->int_port);
143 else
144 metadata =
145 mlx5_eswitch_get_vport_metadata_for_match(src_esw, vport);
146
147 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
148 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, metadata);
149
150 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
151 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
152 mlx5_eswitch_get_vport_metadata_mask());
153
154 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
155 } else {
156 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
157 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
158
159 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
160 MLX5_SET(fte_match_set_misc, misc,
161 source_eswitch_owner_vhca_id,
162 MLX5_CAP_GEN(src_esw->dev, vhca_id));
163
164 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
165 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
166 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
167 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
168 source_eswitch_owner_vhca_id);
169
170 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
171 }
172 }
173
174 static int
esw_setup_decap_indir(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)175 esw_setup_decap_indir(struct mlx5_eswitch *esw,
176 struct mlx5_flow_attr *attr)
177 {
178 struct mlx5_flow_table *ft;
179
180 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
181 return -EOPNOTSUPP;
182
183 ft = mlx5_esw_indir_table_get(esw, attr,
184 mlx5_esw_indir_table_decap_vport(attr), true);
185 return PTR_ERR_OR_ZERO(ft);
186 }
187
188 static void
esw_cleanup_decap_indir(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)189 esw_cleanup_decap_indir(struct mlx5_eswitch *esw,
190 struct mlx5_flow_attr *attr)
191 {
192 if (mlx5_esw_indir_table_decap_vport(attr))
193 mlx5_esw_indir_table_put(esw,
194 mlx5_esw_indir_table_decap_vport(attr),
195 true);
196 }
197
198 static int
esw_setup_mtu_dest(struct mlx5_flow_destination * dest,struct mlx5e_meter_attr * meter,int i)199 esw_setup_mtu_dest(struct mlx5_flow_destination *dest,
200 struct mlx5e_meter_attr *meter,
201 int i)
202 {
203 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_RANGE;
204 dest[i].range.field = MLX5_FLOW_DEST_RANGE_FIELD_PKT_LEN;
205 dest[i].range.min = 0;
206 dest[i].range.max = meter->params.mtu;
207 dest[i].range.hit_ft = mlx5e_post_meter_get_mtu_true_ft(meter->post_meter);
208 dest[i].range.miss_ft = mlx5e_post_meter_get_mtu_false_ft(meter->post_meter);
209
210 return 0;
211 }
212
213 static int
esw_setup_sampler_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,u32 sampler_id,int i)214 esw_setup_sampler_dest(struct mlx5_flow_destination *dest,
215 struct mlx5_flow_act *flow_act,
216 u32 sampler_id,
217 int i)
218 {
219 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
220 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
221 dest[i].sampler_id = sampler_id;
222
223 return 0;
224 }
225
226 static int
esw_setup_ft_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr,int i)227 esw_setup_ft_dest(struct mlx5_flow_destination *dest,
228 struct mlx5_flow_act *flow_act,
229 struct mlx5_eswitch *esw,
230 struct mlx5_flow_attr *attr,
231 int i)
232 {
233 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
234 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
235 dest[i].ft = attr->dest_ft;
236
237 if (mlx5_esw_indir_table_decap_vport(attr))
238 return esw_setup_decap_indir(esw, attr);
239 return 0;
240 }
241
242 static void
esw_setup_accept_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_fs_chains * chains,int i)243 esw_setup_accept_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
244 struct mlx5_fs_chains *chains, int i)
245 {
246 if (mlx5_chains_ignore_flow_level_supported(chains))
247 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
248 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
249 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
250 }
251
252 static void
esw_setup_slow_path_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,int i)253 esw_setup_slow_path_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
254 struct mlx5_eswitch *esw, int i)
255 {
256 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level))
257 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
258 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
259 dest[i].ft = mlx5_eswitch_get_slow_fdb(esw);
260 }
261
262 static int
esw_setup_chain_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_fs_chains * chains,u32 chain,u32 prio,u32 level,int i)263 esw_setup_chain_dest(struct mlx5_flow_destination *dest,
264 struct mlx5_flow_act *flow_act,
265 struct mlx5_fs_chains *chains,
266 u32 chain, u32 prio, u32 level,
267 int i)
268 {
269 struct mlx5_flow_table *ft;
270
271 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
272 ft = mlx5_chains_get_table(chains, chain, prio, level);
273 if (IS_ERR(ft))
274 return PTR_ERR(ft);
275
276 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
277 dest[i].ft = ft;
278 return 0;
279 }
280
esw_put_dest_tables_loop(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr,int from,int to)281 static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr,
282 int from, int to)
283 {
284 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
285 struct mlx5_fs_chains *chains = esw_chains(esw);
286 int i;
287
288 for (i = from; i < to; i++)
289 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
290 mlx5_chains_put_table(chains, 0, 1, 0);
291 else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].vport,
292 esw_attr->dests[i].mdev))
293 mlx5_esw_indir_table_put(esw, esw_attr->dests[i].vport, false);
294 }
295
296 static bool
esw_is_chain_src_port_rewrite(struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr)297 esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr)
298 {
299 int i;
300
301 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
302 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
303 return true;
304 return false;
305 }
306
307 static int
esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_fs_chains * chains,struct mlx5_flow_attr * attr,int * i)308 esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest,
309 struct mlx5_flow_act *flow_act,
310 struct mlx5_eswitch *esw,
311 struct mlx5_fs_chains *chains,
312 struct mlx5_flow_attr *attr,
313 int *i)
314 {
315 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
316 int err;
317
318 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
319 return -EOPNOTSUPP;
320
321 /* flow steering cannot handle more than one dest with the same ft
322 * in a single flow
323 */
324 if (esw_attr->out_count - esw_attr->split_count > 1)
325 return -EOPNOTSUPP;
326
327 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i);
328 if (err)
329 return err;
330
331 if (esw_attr->dests[esw_attr->split_count].pkt_reformat) {
332 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
333 flow_act->pkt_reformat = esw_attr->dests[esw_attr->split_count].pkt_reformat;
334 }
335 (*i)++;
336
337 return 0;
338 }
339
esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)340 static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw,
341 struct mlx5_flow_attr *attr)
342 {
343 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
344
345 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
346 }
347
348 static bool
esw_is_indir_table(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)349 esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
350 {
351 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
352 bool result = false;
353 int i;
354
355 /* Indirect table is supported only for flows with in_port uplink
356 * and the destination is vport on the same eswitch as the uplink,
357 * return false in case at least one of destinations doesn't meet
358 * this criteria.
359 */
360 for (i = esw_attr->split_count; i < esw_attr->out_count; i++) {
361 if (esw_attr->dests[i].vport_valid &&
362 mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].vport,
363 esw_attr->dests[i].mdev)) {
364 result = true;
365 } else {
366 result = false;
367 break;
368 }
369 }
370 return result;
371 }
372
373 static int
esw_setup_indir_table(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr,int * i)374 esw_setup_indir_table(struct mlx5_flow_destination *dest,
375 struct mlx5_flow_act *flow_act,
376 struct mlx5_eswitch *esw,
377 struct mlx5_flow_attr *attr,
378 int *i)
379 {
380 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
381 int j, err;
382
383 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
384 return -EOPNOTSUPP;
385
386 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
387 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
388 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
389
390 dest[*i].ft = mlx5_esw_indir_table_get(esw, attr,
391 esw_attr->dests[j].vport, false);
392 if (IS_ERR(dest[*i].ft)) {
393 err = PTR_ERR(dest[*i].ft);
394 goto err_indir_tbl_get;
395 }
396 }
397
398 if (mlx5_esw_indir_table_decap_vport(attr)) {
399 err = esw_setup_decap_indir(esw, attr);
400 if (err)
401 goto err_indir_tbl_get;
402 }
403
404 return 0;
405
406 err_indir_tbl_get:
407 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
408 return err;
409 }
410
esw_cleanup_indir_table(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)411 static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
412 {
413 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
414
415 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
416 esw_cleanup_decap_indir(esw, attr);
417 }
418
419 static void
esw_cleanup_chain_dest(struct mlx5_fs_chains * chains,u32 chain,u32 prio,u32 level)420 esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level)
421 {
422 mlx5_chains_put_table(chains, chain, prio, level);
423 }
424
esw_same_vhca_id(struct mlx5_core_dev * mdev1,struct mlx5_core_dev * mdev2)425 static bool esw_same_vhca_id(struct mlx5_core_dev *mdev1, struct mlx5_core_dev *mdev2)
426 {
427 return MLX5_CAP_GEN(mdev1, vhca_id) == MLX5_CAP_GEN(mdev2, vhca_id);
428 }
429
esw_setup_uplink_fwd_ipsec_needed(struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr,int attr_idx)430 static bool esw_setup_uplink_fwd_ipsec_needed(struct mlx5_eswitch *esw,
431 struct mlx5_esw_flow_attr *esw_attr,
432 int attr_idx)
433 {
434 if (esw->offloads.ft_ipsec_tx_pol &&
435 esw_attr->dests[attr_idx].vport_valid &&
436 esw_attr->dests[attr_idx].vport == MLX5_VPORT_UPLINK &&
437 /* To be aligned with software, encryption is needed only for tunnel device */
438 (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) &&
439 esw_attr->dests[attr_idx].vport != esw_attr->in_rep->vport &&
440 esw_same_vhca_id(esw_attr->dests[attr_idx].mdev, esw->dev))
441 return true;
442
443 return false;
444 }
445
esw_flow_dests_fwd_ipsec_check(struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr)446 static bool esw_flow_dests_fwd_ipsec_check(struct mlx5_eswitch *esw,
447 struct mlx5_esw_flow_attr *esw_attr)
448 {
449 int i;
450
451 if (!esw->offloads.ft_ipsec_tx_pol)
452 return true;
453
454 for (i = 0; i < esw_attr->split_count; i++)
455 if (esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, i))
456 return false;
457
458 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
459 if (esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, i) &&
460 (esw_attr->out_count - esw_attr->split_count > 1))
461 return false;
462
463 return true;
464 }
465
466 static void
esw_setup_dest_fwd_vport(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr,int attr_idx,int dest_idx,bool pkt_reformat)467 esw_setup_dest_fwd_vport(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
468 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
469 int attr_idx, int dest_idx, bool pkt_reformat)
470 {
471 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
472 dest[dest_idx].vport.num = esw_attr->dests[attr_idx].vport;
473 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
474 dest[dest_idx].vport.vhca_id =
475 MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
476 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
477 if (dest[dest_idx].vport.num == MLX5_VPORT_UPLINK &&
478 mlx5_lag_is_mpesw(esw->dev))
479 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_UPLINK;
480 }
481 if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) {
482 if (pkt_reformat) {
483 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
484 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
485 }
486 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
487 dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
488 }
489 }
490
491 static void
esw_setup_dest_fwd_ipsec(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr,int attr_idx,int dest_idx,bool pkt_reformat)492 esw_setup_dest_fwd_ipsec(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
493 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
494 int attr_idx, int dest_idx, bool pkt_reformat)
495 {
496 dest[dest_idx].ft = esw->offloads.ft_ipsec_tx_pol;
497 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
498 if (pkt_reformat &&
499 esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) {
500 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
501 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
502 }
503 }
504
505 static void
esw_setup_vport_dest(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr,int attr_idx,int dest_idx,bool pkt_reformat)506 esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
507 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
508 int attr_idx, int dest_idx, bool pkt_reformat)
509 {
510 if (esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, attr_idx))
511 esw_setup_dest_fwd_ipsec(dest, flow_act, esw, esw_attr,
512 attr_idx, dest_idx, pkt_reformat);
513 else
514 esw_setup_dest_fwd_vport(dest, flow_act, esw, esw_attr,
515 attr_idx, dest_idx, pkt_reformat);
516 }
517
518 static int
esw_setup_vport_dests(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_esw_flow_attr * esw_attr,int i)519 esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
520 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
521 int i)
522 {
523 int j;
524
525 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++)
526 esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true);
527 return i;
528 }
529
530 static bool
esw_src_port_rewrite_supported(struct mlx5_eswitch * esw)531 esw_src_port_rewrite_supported(struct mlx5_eswitch *esw)
532 {
533 return MLX5_CAP_GEN(esw->dev, reg_c_preserve) &&
534 mlx5_eswitch_vport_match_metadata_enabled(esw) &&
535 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level);
536 }
537
538 static bool
esw_dests_to_int_external(struct mlx5_flow_destination * dests,int max_dest)539 esw_dests_to_int_external(struct mlx5_flow_destination *dests, int max_dest)
540 {
541 bool internal_dest = false, external_dest = false;
542 int i;
543
544 for (i = 0; i < max_dest; i++) {
545 if (dests[i].type != MLX5_FLOW_DESTINATION_TYPE_VPORT &&
546 dests[i].type != MLX5_FLOW_DESTINATION_TYPE_UPLINK)
547 continue;
548
549 /* Uplink dest is external, but considered as internal
550 * if there is reformat because firmware uses LB+hairpin to support it.
551 */
552 if (dests[i].vport.num == MLX5_VPORT_UPLINK &&
553 !(dests[i].vport.flags & MLX5_FLOW_DEST_VPORT_REFORMAT_ID))
554 external_dest = true;
555 else
556 internal_dest = true;
557
558 if (internal_dest && external_dest)
559 return true;
560 }
561
562 return false;
563 }
564
565 static int
esw_setup_dests(struct mlx5_flow_destination * dest,struct mlx5_flow_act * flow_act,struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr,struct mlx5_flow_spec * spec,int * i)566 esw_setup_dests(struct mlx5_flow_destination *dest,
567 struct mlx5_flow_act *flow_act,
568 struct mlx5_eswitch *esw,
569 struct mlx5_flow_attr *attr,
570 struct mlx5_flow_spec *spec,
571 int *i)
572 {
573 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
574 struct mlx5_fs_chains *chains = esw_chains(esw);
575 int err = 0;
576
577 if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) &&
578 esw_src_port_rewrite_supported(esw))
579 attr->flags |= MLX5_ATTR_FLAG_SRC_REWRITE;
580
581 if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH) {
582 esw_setup_slow_path_dest(dest, flow_act, esw, *i);
583 (*i)++;
584 goto out;
585 }
586
587 if (attr->flags & MLX5_ATTR_FLAG_SAMPLE) {
588 esw_setup_sampler_dest(dest, flow_act, attr->sample_attr.sampler_id, *i);
589 (*i)++;
590 } else if (attr->flags & MLX5_ATTR_FLAG_ACCEPT) {
591 esw_setup_accept_dest(dest, flow_act, chains, *i);
592 (*i)++;
593 } else if (attr->flags & MLX5_ATTR_FLAG_MTU) {
594 err = esw_setup_mtu_dest(dest, &attr->meter_attr, *i);
595 (*i)++;
596 } else if (esw_is_indir_table(esw, attr)) {
597 err = esw_setup_indir_table(dest, flow_act, esw, attr, i);
598 } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) {
599 err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i);
600 } else {
601 *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i);
602
603 if (attr->dest_ft) {
604 err = esw_setup_ft_dest(dest, flow_act, esw, attr, *i);
605 (*i)++;
606 } else if (attr->dest_chain) {
607 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain,
608 1, 0, *i);
609 (*i)++;
610 }
611 }
612
613 if (attr->extra_split_ft) {
614 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
615 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
616 dest[*i].ft = attr->extra_split_ft;
617 (*i)++;
618 }
619
620 out:
621 return err;
622 }
623
624 static void
esw_cleanup_dests(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)625 esw_cleanup_dests(struct mlx5_eswitch *esw,
626 struct mlx5_flow_attr *attr)
627 {
628 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
629 struct mlx5_fs_chains *chains = esw_chains(esw);
630
631 if (attr->dest_ft) {
632 esw_cleanup_decap_indir(esw, attr);
633 } else if (!mlx5e_tc_attr_flags_skip(attr->flags)) {
634 if (attr->dest_chain)
635 esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0);
636 else if (esw_is_indir_table(esw, attr))
637 esw_cleanup_indir_table(esw, attr);
638 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
639 esw_cleanup_chain_src_port_rewrite(esw, attr);
640 }
641 }
642
643 static void
esw_setup_meter(struct mlx5_flow_attr * attr,struct mlx5_flow_act * flow_act)644 esw_setup_meter(struct mlx5_flow_attr *attr, struct mlx5_flow_act *flow_act)
645 {
646 struct mlx5e_flow_meter_handle *meter;
647
648 meter = attr->meter_attr.meter;
649 flow_act->exe_aso.type = attr->exe_aso_type;
650 flow_act->exe_aso.object_id = meter->obj_id;
651 flow_act->exe_aso.flow_meter.meter_idx = meter->idx;
652 flow_act->exe_aso.flow_meter.init_color = MLX5_FLOW_METER_COLOR_GREEN;
653 /* use metadata reg 5 for packet color */
654 flow_act->exe_aso.return_reg_id = 5;
655 }
656
657 struct mlx5_flow_handle *
mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch * esw,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr)658 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
659 struct mlx5_flow_spec *spec,
660 struct mlx5_flow_attr *attr)
661 {
662 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
663 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
664 struct mlx5_fs_chains *chains = esw_chains(esw);
665 bool split = !!(esw_attr->split_count);
666 struct mlx5_vport_tbl_attr fwd_attr;
667 struct mlx5_flow_destination *dest;
668 struct mlx5_flow_handle *rule;
669 struct mlx5_flow_table *fdb;
670 int i = 0;
671
672 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
673 return ERR_PTR(-EOPNOTSUPP);
674
675 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
676 return ERR_PTR(-EOPNOTSUPP);
677
678 if (!esw_flow_dests_fwd_ipsec_check(esw, esw_attr))
679 return ERR_PTR(-EOPNOTSUPP);
680
681 dest = kcalloc(MLX5_MAX_FLOW_FWD_VPORTS + 1, sizeof(*dest), GFP_KERNEL);
682 if (!dest)
683 return ERR_PTR(-ENOMEM);
684
685 flow_act.action = attr->action;
686
687 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
688 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
689 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
690 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
691 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
692 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
693 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
694 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
695 }
696 }
697
698 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
699
700 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
701 int err;
702
703 err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i);
704 if (err) {
705 rule = ERR_PTR(err);
706 goto err_create_goto_table;
707 }
708
709 /* Header rewrite with combined wire+loopback in FDB is not allowed */
710 if ((flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) &&
711 esw_dests_to_int_external(dest, i)) {
712 esw_warn(esw->dev,
713 "FDB: Header rewrite with forwarding to both internal and external dests is not allowed\n");
714 rule = ERR_PTR(-EINVAL);
715 goto err_esw_get;
716 }
717 }
718
719 if (esw_attr->decap_pkt_reformat)
720 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
721
722 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
723 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
724 dest[i].counter_id = mlx5_fc_id(attr->counter);
725 i++;
726 }
727
728 if (attr->outer_match_level != MLX5_MATCH_NONE)
729 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
730 if (attr->inner_match_level != MLX5_MATCH_NONE)
731 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
732
733 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
734 flow_act.modify_hdr = attr->modify_hdr;
735
736 if ((flow_act.action & MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO) &&
737 attr->exe_aso_type == MLX5_EXE_ASO_FLOW_METER)
738 esw_setup_meter(attr, &flow_act);
739
740 if (split) {
741 fwd_attr.chain = attr->chain;
742 fwd_attr.prio = attr->prio;
743 fwd_attr.vport = esw_attr->in_rep->vport;
744 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
745
746 fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
747 } else {
748 if (attr->chain || attr->prio)
749 fdb = mlx5_chains_get_table(chains, attr->chain,
750 attr->prio, 0);
751 else
752 fdb = attr->ft;
753
754 if (!(attr->flags & MLX5_ATTR_FLAG_NO_IN_PORT))
755 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
756 esw_attr->in_mdev->priv.eswitch,
757 esw_attr->in_rep->vport);
758 }
759 if (IS_ERR(fdb)) {
760 rule = ERR_CAST(fdb);
761 goto err_esw_get;
762 }
763
764 if (!i) {
765 kfree(dest);
766 dest = NULL;
767 }
768
769 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
770 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
771 &flow_act, dest, i);
772 else
773 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
774 if (IS_ERR(rule))
775 goto err_add_rule;
776 else
777 atomic64_inc(&esw->offloads.num_flows);
778
779 kfree(dest);
780 return rule;
781
782 err_add_rule:
783 if (split)
784 mlx5_esw_vporttbl_put(esw, &fwd_attr);
785 else if (attr->chain || attr->prio)
786 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
787 err_esw_get:
788 esw_cleanup_dests(esw, attr);
789 err_create_goto_table:
790 kfree(dest);
791 return rule;
792 }
793
794 struct mlx5_flow_handle *
mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch * esw,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr)795 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
796 struct mlx5_flow_spec *spec,
797 struct mlx5_flow_attr *attr)
798 {
799 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
800 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
801 struct mlx5_fs_chains *chains = esw_chains(esw);
802 struct mlx5_vport_tbl_attr fwd_attr;
803 struct mlx5_flow_destination *dest;
804 struct mlx5_flow_table *fast_fdb;
805 struct mlx5_flow_table *fwd_fdb;
806 struct mlx5_flow_handle *rule;
807 int i, err = 0;
808
809 dest = kcalloc(MLX5_MAX_FLOW_FWD_VPORTS + 1, sizeof(*dest), GFP_KERNEL);
810 if (!dest)
811 return ERR_PTR(-ENOMEM);
812
813 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
814 if (IS_ERR(fast_fdb)) {
815 rule = ERR_CAST(fast_fdb);
816 goto err_get_fast;
817 }
818
819 fwd_attr.chain = attr->chain;
820 fwd_attr.prio = attr->prio;
821 fwd_attr.vport = esw_attr->in_rep->vport;
822 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
823 fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
824 if (IS_ERR(fwd_fdb)) {
825 rule = ERR_CAST(fwd_fdb);
826 goto err_get_fwd;
827 }
828
829 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
830 for (i = 0; i < esw_attr->split_count; i++) {
831 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
832 /* Source port rewrite (forward to ovs internal port or statck device) isn't
833 * supported in the rule of split action.
834 */
835 err = -EOPNOTSUPP;
836 else
837 esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false);
838
839 if (err) {
840 rule = ERR_PTR(err);
841 goto err_chain_src_rewrite;
842 }
843 }
844 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
845 dest[i].ft = fwd_fdb;
846 i++;
847
848 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
849 esw_attr->in_mdev->priv.eswitch,
850 esw_attr->in_rep->vport);
851
852 if (attr->outer_match_level != MLX5_MATCH_NONE)
853 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
854
855 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
856 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
857
858 if (IS_ERR(rule)) {
859 i = esw_attr->split_count;
860 goto err_chain_src_rewrite;
861 }
862
863 atomic64_inc(&esw->offloads.num_flows);
864
865 kfree(dest);
866 return rule;
867 err_chain_src_rewrite:
868 mlx5_esw_vporttbl_put(esw, &fwd_attr);
869 err_get_fwd:
870 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
871 err_get_fast:
872 kfree(dest);
873 return rule;
874 }
875
876 static void
__mlx5_eswitch_del_rule(struct mlx5_eswitch * esw,struct mlx5_flow_handle * rule,struct mlx5_flow_attr * attr,bool fwd_rule)877 __mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
878 struct mlx5_flow_handle *rule,
879 struct mlx5_flow_attr *attr,
880 bool fwd_rule)
881 {
882 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
883 struct mlx5_fs_chains *chains = esw_chains(esw);
884 bool split = (esw_attr->split_count > 0);
885 struct mlx5_vport_tbl_attr fwd_attr;
886 int i;
887
888 mlx5_del_flow_rules(rule);
889
890 if (!mlx5e_tc_attr_flags_skip(attr->flags)) {
891 /* unref the term table */
892 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
893 if (esw_attr->dests[i].termtbl)
894 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
895 }
896 }
897
898 atomic64_dec(&esw->offloads.num_flows);
899
900 if (fwd_rule || split) {
901 fwd_attr.chain = attr->chain;
902 fwd_attr.prio = attr->prio;
903 fwd_attr.vport = esw_attr->in_rep->vport;
904 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
905 }
906
907 if (fwd_rule) {
908 mlx5_esw_vporttbl_put(esw, &fwd_attr);
909 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
910 } else {
911 if (split)
912 mlx5_esw_vporttbl_put(esw, &fwd_attr);
913 else if (attr->chain || attr->prio)
914 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
915 esw_cleanup_dests(esw, attr);
916 }
917 }
918
919 void
mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch * esw,struct mlx5_flow_handle * rule,struct mlx5_flow_attr * attr)920 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
921 struct mlx5_flow_handle *rule,
922 struct mlx5_flow_attr *attr)
923 {
924 __mlx5_eswitch_del_rule(esw, rule, attr, false);
925 }
926
927 void
mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch * esw,struct mlx5_flow_handle * rule,struct mlx5_flow_attr * attr)928 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
929 struct mlx5_flow_handle *rule,
930 struct mlx5_flow_attr *attr)
931 {
932 __mlx5_eswitch_del_rule(esw, rule, attr, true);
933 }
934
935 struct mlx5_flow_handle *
mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch * on_esw,struct mlx5_eswitch * from_esw,struct mlx5_eswitch_rep * rep,u32 sqn)936 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
937 struct mlx5_eswitch *from_esw,
938 struct mlx5_eswitch_rep *rep,
939 u32 sqn)
940 {
941 struct mlx5_flow_act flow_act = {0};
942 struct mlx5_flow_destination dest = {};
943 struct mlx5_flow_handle *flow_rule;
944 struct mlx5_flow_spec *spec;
945 void *misc;
946 u16 vport;
947
948 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
949 if (!spec) {
950 flow_rule = ERR_PTR(-ENOMEM);
951 goto out;
952 }
953
954 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
955 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
956
957 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
958 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
959
960 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
961
962 /* source vport is the esw manager */
963 vport = from_esw->manager_vport;
964
965 if (mlx5_eswitch_vport_match_metadata_enabled(on_esw)) {
966 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
967 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
968 mlx5_eswitch_get_vport_metadata_for_match(from_esw, vport));
969
970 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
971 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
972 mlx5_eswitch_get_vport_metadata_mask());
973
974 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
975 } else {
976 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
977 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
978
979 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
980 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
981 MLX5_CAP_GEN(from_esw->dev, vhca_id));
982
983 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
984 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
985
986 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
987 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
988 source_eswitch_owner_vhca_id);
989
990 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
991 }
992
993 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
994 dest.vport.num = rep->vport;
995 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
996 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
997 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
998
999 if (rep->vport == MLX5_VPORT_UPLINK &&
1000 on_esw == from_esw && on_esw->offloads.ft_ipsec_tx_pol) {
1001 dest.ft = on_esw->offloads.ft_ipsec_tx_pol;
1002 flow_act.flags = FLOW_ACT_IGNORE_FLOW_LEVEL;
1003 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1004 } else {
1005 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1006 dest.vport.num = rep->vport;
1007 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
1008 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
1009 }
1010
1011 if (MLX5_CAP_ESW_FLOWTABLE(on_esw->dev, flow_source) &&
1012 rep->vport == MLX5_VPORT_UPLINK)
1013 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
1014
1015 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(on_esw),
1016 spec, &flow_act, &dest, 1);
1017 if (IS_ERR(flow_rule))
1018 esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %ld\n",
1019 PTR_ERR(flow_rule));
1020 out:
1021 kvfree(spec);
1022 return flow_rule;
1023 }
1024 EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
1025
mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle * rule)1026 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
1027 {
1028 mlx5_del_flow_rules(rule);
1029 }
1030
mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle * rule)1031 void mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle *rule)
1032 {
1033 if (rule)
1034 mlx5_del_flow_rules(rule);
1035 }
1036
1037 struct mlx5_flow_handle *
mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch * esw,u16 vport_num)1038 mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch *esw, u16 vport_num)
1039 {
1040 struct mlx5_flow_destination dest = {};
1041 struct mlx5_flow_act flow_act = {0};
1042 struct mlx5_flow_handle *flow_rule;
1043 struct mlx5_flow_spec *spec;
1044
1045 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1046 if (!spec)
1047 return ERR_PTR(-ENOMEM);
1048
1049 MLX5_SET(fte_match_param, spec->match_criteria,
1050 misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask());
1051 MLX5_SET(fte_match_param, spec->match_criteria,
1052 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1053 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1,
1054 ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK);
1055
1056 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1057 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1058 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1059
1060 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0,
1061 mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num));
1062 dest.vport.num = vport_num;
1063
1064 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1065 spec, &flow_act, &dest, 1);
1066 if (IS_ERR(flow_rule))
1067 esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule vport %d, err %ld\n",
1068 vport_num, PTR_ERR(flow_rule));
1069
1070 kvfree(spec);
1071 return flow_rule;
1072 }
1073
mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch * esw)1074 static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
1075 {
1076 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1077 MLX5_FDB_TO_VPORT_REG_C_1;
1078 }
1079
esw_set_passing_vport_metadata(struct mlx5_eswitch * esw,bool enable)1080 static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
1081 {
1082 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
1083 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
1084 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
1085 u8 curr, wanted;
1086 int err;
1087
1088 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
1089 !mlx5_eswitch_vport_match_metadata_enabled(esw))
1090 return 0;
1091
1092 MLX5_SET(query_esw_vport_context_in, in, opcode,
1093 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
1094 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
1095 if (err)
1096 return err;
1097
1098 curr = MLX5_GET(query_esw_vport_context_out, out,
1099 esw_vport_context.fdb_to_vport_reg_c_id);
1100 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
1101 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
1102 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
1103
1104 if (enable)
1105 curr |= wanted;
1106 else
1107 curr &= ~wanted;
1108
1109 MLX5_SET(modify_esw_vport_context_in, min,
1110 esw_vport_context.fdb_to_vport_reg_c_id, curr);
1111 MLX5_SET(modify_esw_vport_context_in, min,
1112 field_select.fdb_to_vport_reg_c_id, 1);
1113
1114 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
1115 if (!err) {
1116 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
1117 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1118 else
1119 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1120 }
1121
1122 return err;
1123 }
1124
peer_miss_rules_setup(struct mlx5_eswitch * esw,struct mlx5_core_dev * peer_dev,struct mlx5_flow_spec * spec,struct mlx5_flow_destination * dest)1125 static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
1126 struct mlx5_core_dev *peer_dev,
1127 struct mlx5_flow_spec *spec,
1128 struct mlx5_flow_destination *dest)
1129 {
1130 void *misc;
1131
1132 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1133 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1134 misc_parameters_2);
1135 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1136 mlx5_eswitch_get_vport_metadata_mask());
1137
1138 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1139 } else {
1140 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1141 misc_parameters);
1142
1143 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
1144 MLX5_CAP_GEN(peer_dev, vhca_id));
1145
1146 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1147
1148 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1149 misc_parameters);
1150 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1151 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
1152 source_eswitch_owner_vhca_id);
1153 }
1154
1155 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1156 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
1157 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
1158 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
1159 }
1160
esw_set_peer_miss_rule_source_port(struct mlx5_eswitch * esw,struct mlx5_eswitch * peer_esw,struct mlx5_flow_spec * spec,u16 vport)1161 static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
1162 struct mlx5_eswitch *peer_esw,
1163 struct mlx5_flow_spec *spec,
1164 u16 vport)
1165 {
1166 void *misc;
1167
1168 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1169 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1170 misc_parameters_2);
1171 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1172 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
1173 vport));
1174 } else {
1175 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1176 misc_parameters);
1177 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1178 }
1179 }
1180
esw_add_fdb_peer_miss_rules(struct mlx5_eswitch * esw,struct mlx5_core_dev * peer_dev)1181 static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1182 struct mlx5_core_dev *peer_dev)
1183 {
1184 struct mlx5_flow_destination dest = {};
1185 struct mlx5_flow_act flow_act = {0};
1186 struct mlx5_flow_handle **flows;
1187 /* total vports is the same for both e-switches */
1188 int nvports = esw->total_vports;
1189 struct mlx5_flow_handle *flow;
1190 struct mlx5_flow_spec *spec;
1191 struct mlx5_vport *vport;
1192 int err, pfindex;
1193 unsigned long i;
1194 void *misc;
1195
1196 if (!MLX5_VPORT_MANAGER(esw->dev) && !mlx5_core_is_ecpf_esw_manager(esw->dev))
1197 return 0;
1198
1199 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1200 if (!spec)
1201 return -ENOMEM;
1202
1203 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
1204
1205 flows = kvcalloc(nvports, sizeof(*flows), GFP_KERNEL);
1206 if (!flows) {
1207 err = -ENOMEM;
1208 goto alloc_flows_err;
1209 }
1210
1211 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1212 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1213 misc_parameters);
1214
1215 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1216 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1217 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1218 spec, MLX5_VPORT_PF);
1219
1220 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1221 spec, &flow_act, &dest, 1);
1222 if (IS_ERR(flow)) {
1223 err = PTR_ERR(flow);
1224 goto add_pf_flow_err;
1225 }
1226 flows[vport->index] = flow;
1227 }
1228
1229 if (mlx5_ecpf_vport_exists(esw->dev)) {
1230 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1231 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
1232 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1233 spec, &flow_act, &dest, 1);
1234 if (IS_ERR(flow)) {
1235 err = PTR_ERR(flow);
1236 goto add_ecpf_flow_err;
1237 }
1238 flows[vport->index] = flow;
1239 }
1240
1241 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1242 esw_set_peer_miss_rule_source_port(esw,
1243 peer_dev->priv.eswitch,
1244 spec, vport->vport);
1245
1246 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1247 spec, &flow_act, &dest, 1);
1248 if (IS_ERR(flow)) {
1249 err = PTR_ERR(flow);
1250 goto add_vf_flow_err;
1251 }
1252 flows[vport->index] = flow;
1253 }
1254
1255 if (mlx5_core_ec_sriov_enabled(esw->dev)) {
1256 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, mlx5_core_max_ec_vfs(esw->dev)) {
1257 if (i >= mlx5_core_max_ec_vfs(peer_dev))
1258 break;
1259 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1260 spec, vport->vport);
1261 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1262 spec, &flow_act, &dest, 1);
1263 if (IS_ERR(flow)) {
1264 err = PTR_ERR(flow);
1265 goto add_ec_vf_flow_err;
1266 }
1267 flows[vport->index] = flow;
1268 }
1269 }
1270
1271 pfindex = mlx5_get_dev_index(peer_dev);
1272 if (pfindex >= MLX5_MAX_PORTS) {
1273 esw_warn(esw->dev, "Peer dev index(%d) is over the max num defined(%d)\n",
1274 pfindex, MLX5_MAX_PORTS);
1275 err = -EINVAL;
1276 goto add_ec_vf_flow_err;
1277 }
1278 esw->fdb_table.offloads.peer_miss_rules[pfindex] = flows;
1279
1280 kvfree(spec);
1281 return 0;
1282
1283 add_ec_vf_flow_err:
1284 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, mlx5_core_max_ec_vfs(esw->dev)) {
1285 if (!flows[vport->index])
1286 continue;
1287 mlx5_del_flow_rules(flows[vport->index]);
1288 }
1289 add_vf_flow_err:
1290 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1291 if (!flows[vport->index])
1292 continue;
1293 mlx5_del_flow_rules(flows[vport->index]);
1294 }
1295 if (mlx5_ecpf_vport_exists(esw->dev)) {
1296 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1297 mlx5_del_flow_rules(flows[vport->index]);
1298 }
1299 add_ecpf_flow_err:
1300 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1301 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1302 mlx5_del_flow_rules(flows[vport->index]);
1303 }
1304 add_pf_flow_err:
1305 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
1306 kvfree(flows);
1307 alloc_flows_err:
1308 kvfree(spec);
1309 return err;
1310 }
1311
esw_del_fdb_peer_miss_rules(struct mlx5_eswitch * esw,struct mlx5_core_dev * peer_dev)1312 static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1313 struct mlx5_core_dev *peer_dev)
1314 {
1315 u16 peer_index = mlx5_get_dev_index(peer_dev);
1316 struct mlx5_flow_handle **flows;
1317 struct mlx5_vport *vport;
1318 unsigned long i;
1319
1320 flows = esw->fdb_table.offloads.peer_miss_rules[peer_index];
1321 if (!flows)
1322 return;
1323
1324 if (mlx5_core_ec_sriov_enabled(esw->dev)) {
1325 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, mlx5_core_max_ec_vfs(esw->dev)) {
1326 /* The flow for a particular vport could be NULL if the other ECPF
1327 * has fewer or no VFs enabled
1328 */
1329 if (!flows[vport->index])
1330 continue;
1331 mlx5_del_flow_rules(flows[vport->index]);
1332 }
1333 }
1334
1335 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev))
1336 mlx5_del_flow_rules(flows[vport->index]);
1337
1338 if (mlx5_ecpf_vport_exists(esw->dev)) {
1339 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1340 mlx5_del_flow_rules(flows[vport->index]);
1341 }
1342
1343 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1344 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1345 mlx5_del_flow_rules(flows[vport->index]);
1346 }
1347
1348 kvfree(flows);
1349 esw->fdb_table.offloads.peer_miss_rules[peer_index] = NULL;
1350 }
1351
esw_add_fdb_miss_rule(struct mlx5_eswitch * esw)1352 static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1353 {
1354 struct mlx5_flow_act flow_act = {0};
1355 struct mlx5_flow_destination dest = {};
1356 struct mlx5_flow_handle *flow_rule = NULL;
1357 struct mlx5_flow_spec *spec;
1358 void *headers_c;
1359 void *headers_v;
1360 int err = 0;
1361 u8 *dmac_c;
1362 u8 *dmac_v;
1363
1364 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1365 if (!spec) {
1366 err = -ENOMEM;
1367 goto out;
1368 }
1369
1370 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1371 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1372 outer_headers);
1373 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1374 outer_headers.dmac_47_16);
1375 dmac_c[0] = 0x01;
1376
1377 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1378 dest.vport.num = esw->manager_vport;
1379 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1380
1381 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1382 spec, &flow_act, &dest, 1);
1383 if (IS_ERR(flow_rule)) {
1384 err = PTR_ERR(flow_rule);
1385 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
1386 goto out;
1387 }
1388
1389 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1390
1391 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1392 outer_headers);
1393 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1394 outer_headers.dmac_47_16);
1395 dmac_v[0] = 0x01;
1396 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
1397 spec, &flow_act, &dest, 1);
1398 if (IS_ERR(flow_rule)) {
1399 err = PTR_ERR(flow_rule);
1400 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1401 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1402 goto out;
1403 }
1404
1405 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1406
1407 out:
1408 kvfree(spec);
1409 return err;
1410 }
1411
1412 struct mlx5_flow_handle *
esw_add_restore_rule(struct mlx5_eswitch * esw,u32 tag)1413 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1414 {
1415 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1416 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1417 struct mlx5_flow_context *flow_context;
1418 struct mlx5_flow_handle *flow_rule;
1419 struct mlx5_flow_destination dest;
1420 struct mlx5_flow_spec *spec;
1421 void *misc;
1422
1423 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1424 return ERR_PTR(-EOPNOTSUPP);
1425
1426 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1427 if (!spec)
1428 return ERR_PTR(-ENOMEM);
1429
1430 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1431 misc_parameters_2);
1432 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1433 ESW_REG_C0_USER_DATA_METADATA_MASK);
1434 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1435 misc_parameters_2);
1436 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1437 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1438 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1439 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1440 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
1441
1442 flow_context = &spec->flow_context;
1443 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1444 flow_context->flow_tag = tag;
1445 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1446 dest.ft = esw->offloads.ft_offloads;
1447
1448 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
1449 kvfree(spec);
1450
1451 if (IS_ERR(flow_rule))
1452 esw_warn(esw->dev,
1453 "Failed to create restore rule for tag: %d, err(%d)\n",
1454 tag, (int)PTR_ERR(flow_rule));
1455
1456 return flow_rule;
1457 }
1458
1459 #define MAX_PF_SQ 256
1460 #define MAX_SQ_NVPORTS 32
1461
1462 void
mlx5_esw_set_flow_group_source_port(struct mlx5_eswitch * esw,u32 * flow_group_in,int match_params)1463 mlx5_esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1464 u32 *flow_group_in,
1465 int match_params)
1466 {
1467 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1468 flow_group_in,
1469 match_criteria);
1470
1471 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1472 MLX5_SET(create_flow_group_in, flow_group_in,
1473 match_criteria_enable,
1474 MLX5_MATCH_MISC_PARAMETERS_2 | match_params);
1475
1476 MLX5_SET(fte_match_param, match_criteria,
1477 misc_parameters_2.metadata_reg_c_0,
1478 mlx5_eswitch_get_vport_metadata_mask());
1479 } else {
1480 MLX5_SET(create_flow_group_in, flow_group_in,
1481 match_criteria_enable,
1482 MLX5_MATCH_MISC_PARAMETERS | match_params);
1483
1484 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1485 misc_parameters.source_port);
1486 }
1487 }
1488
1489 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
esw_vport_tbl_put(struct mlx5_eswitch * esw)1490 static void esw_vport_tbl_put(struct mlx5_eswitch *esw)
1491 {
1492 struct mlx5_vport_tbl_attr attr;
1493 struct mlx5_vport *vport;
1494 unsigned long i;
1495
1496 attr.chain = 0;
1497 attr.prio = 1;
1498 mlx5_esw_for_each_vport(esw, i, vport) {
1499 attr.vport = vport->vport;
1500 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
1501 mlx5_esw_vporttbl_put(esw, &attr);
1502 }
1503 }
1504
esw_vport_tbl_get(struct mlx5_eswitch * esw)1505 static int esw_vport_tbl_get(struct mlx5_eswitch *esw)
1506 {
1507 struct mlx5_vport_tbl_attr attr;
1508 struct mlx5_flow_table *fdb;
1509 struct mlx5_vport *vport;
1510 unsigned long i;
1511
1512 attr.chain = 0;
1513 attr.prio = 1;
1514 mlx5_esw_for_each_vport(esw, i, vport) {
1515 attr.vport = vport->vport;
1516 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
1517 fdb = mlx5_esw_vporttbl_get(esw, &attr);
1518 if (IS_ERR(fdb))
1519 goto out;
1520 }
1521 return 0;
1522
1523 out:
1524 esw_vport_tbl_put(esw);
1525 return PTR_ERR(fdb);
1526 }
1527
1528 #define fdb_modify_header_fwd_to_table_supported(esw) \
1529 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
esw_init_chains_offload_flags(struct mlx5_eswitch * esw,u32 * flags)1530 static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1531 {
1532 struct mlx5_core_dev *dev = esw->dev;
1533
1534 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1535 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1536
1537 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1538 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1539 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1540 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1541 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1542 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1543 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1544 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1545 /* Disabled when ttl workaround is needed, e.g
1546 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1547 */
1548 esw_warn(dev,
1549 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1550 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1551 } else {
1552 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1553 esw_info(dev, "Supported tc chains and prios offload\n");
1554 }
1555
1556 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1557 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1558 }
1559
1560 static int
esw_chains_create(struct mlx5_eswitch * esw,struct mlx5_flow_table * miss_fdb)1561 esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1562 {
1563 struct mlx5_core_dev *dev = esw->dev;
1564 struct mlx5_flow_table *nf_ft, *ft;
1565 struct mlx5_chains_attr attr = {};
1566 struct mlx5_fs_chains *chains;
1567 int err;
1568
1569 esw_init_chains_offload_flags(esw, &attr.flags);
1570 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
1571 attr.max_grp_num = esw->params.large_group_num;
1572 attr.default_ft = miss_fdb;
1573 attr.mapping = esw->offloads.reg_c0_obj_pool;
1574
1575 chains = mlx5_chains_create(dev, &attr);
1576 if (IS_ERR(chains)) {
1577 err = PTR_ERR(chains);
1578 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1579 return err;
1580 }
1581 mlx5_chains_print_info(chains);
1582
1583 esw->fdb_table.offloads.esw_chains_priv = chains;
1584
1585 /* Create tc_end_ft which is the always created ft chain */
1586 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1587 1, 0);
1588 if (IS_ERR(nf_ft)) {
1589 err = PTR_ERR(nf_ft);
1590 goto nf_ft_err;
1591 }
1592
1593 /* Always open the root for fast path */
1594 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1595 if (IS_ERR(ft)) {
1596 err = PTR_ERR(ft);
1597 goto level_0_err;
1598 }
1599
1600 /* Open level 1 for split fdb rules now if prios isn't supported */
1601 if (!mlx5_chains_prios_supported(chains)) {
1602 err = esw_vport_tbl_get(esw);
1603 if (err)
1604 goto level_1_err;
1605 }
1606
1607 mlx5_chains_set_end_ft(chains, nf_ft);
1608
1609 return 0;
1610
1611 level_1_err:
1612 mlx5_chains_put_table(chains, 0, 1, 0);
1613 level_0_err:
1614 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1615 nf_ft_err:
1616 mlx5_chains_destroy(chains);
1617 esw->fdb_table.offloads.esw_chains_priv = NULL;
1618
1619 return err;
1620 }
1621
1622 static void
esw_chains_destroy(struct mlx5_eswitch * esw,struct mlx5_fs_chains * chains)1623 esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1624 {
1625 if (!mlx5_chains_prios_supported(chains))
1626 esw_vport_tbl_put(esw);
1627 mlx5_chains_put_table(chains, 0, 1, 0);
1628 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1629 mlx5_chains_destroy(chains);
1630 }
1631
1632 #else /* CONFIG_MLX5_CLS_ACT */
1633
1634 static int
esw_chains_create(struct mlx5_eswitch * esw,struct mlx5_flow_table * miss_fdb)1635 esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1636 { return 0; }
1637
1638 static void
esw_chains_destroy(struct mlx5_eswitch * esw,struct mlx5_fs_chains * chains)1639 esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1640 {}
1641
1642 #endif
1643
1644 static int
esw_create_send_to_vport_group(struct mlx5_eswitch * esw,struct mlx5_flow_table * fdb,u32 * flow_group_in,int * ix)1645 esw_create_send_to_vport_group(struct mlx5_eswitch *esw,
1646 struct mlx5_flow_table *fdb,
1647 u32 *flow_group_in,
1648 int *ix)
1649 {
1650 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1651 struct mlx5_flow_group *g;
1652 void *match_criteria;
1653 int count, err = 0;
1654
1655 memset(flow_group_in, 0, inlen);
1656
1657 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, MLX5_MATCH_MISC_PARAMETERS);
1658
1659 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1660 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1661
1662 if (!mlx5_eswitch_vport_match_metadata_enabled(esw) &&
1663 MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1664 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1665 misc_parameters.source_eswitch_owner_vhca_id);
1666 MLX5_SET(create_flow_group_in, flow_group_in,
1667 source_eswitch_owner_vhca_id_valid, 1);
1668 }
1669
1670 /* See comment at table_size calculation */
1671 count = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ);
1672 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1673 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, *ix + count - 1);
1674 *ix += count;
1675
1676 g = mlx5_create_flow_group(fdb, flow_group_in);
1677 if (IS_ERR(g)) {
1678 err = PTR_ERR(g);
1679 esw_warn(esw->dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1680 goto out;
1681 }
1682 esw->fdb_table.offloads.send_to_vport_grp = g;
1683
1684 out:
1685 return err;
1686 }
1687
1688 static int
esw_create_meta_send_to_vport_group(struct mlx5_eswitch * esw,struct mlx5_flow_table * fdb,u32 * flow_group_in,int * ix)1689 esw_create_meta_send_to_vport_group(struct mlx5_eswitch *esw,
1690 struct mlx5_flow_table *fdb,
1691 u32 *flow_group_in,
1692 int *ix)
1693 {
1694 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1695 struct mlx5_flow_group *g;
1696 void *match_criteria;
1697 int err = 0;
1698
1699 if (!esw_src_port_rewrite_supported(esw))
1700 return 0;
1701
1702 memset(flow_group_in, 0, inlen);
1703
1704 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1705 MLX5_MATCH_MISC_PARAMETERS_2);
1706
1707 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1708
1709 MLX5_SET(fte_match_param, match_criteria,
1710 misc_parameters_2.metadata_reg_c_0,
1711 mlx5_eswitch_get_vport_metadata_mask());
1712 MLX5_SET(fte_match_param, match_criteria,
1713 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1714
1715 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1716 MLX5_SET(create_flow_group_in, flow_group_in,
1717 end_flow_index, *ix + esw->total_vports - 1);
1718 *ix += esw->total_vports;
1719
1720 g = mlx5_create_flow_group(fdb, flow_group_in);
1721 if (IS_ERR(g)) {
1722 err = PTR_ERR(g);
1723 esw_warn(esw->dev,
1724 "Failed to create send-to-vport meta flow group err(%d)\n", err);
1725 goto send_vport_meta_err;
1726 }
1727 esw->fdb_table.offloads.send_to_vport_meta_grp = g;
1728
1729 return 0;
1730
1731 send_vport_meta_err:
1732 return err;
1733 }
1734
1735 static int
esw_create_peer_esw_miss_group(struct mlx5_eswitch * esw,struct mlx5_flow_table * fdb,u32 * flow_group_in,int * ix)1736 esw_create_peer_esw_miss_group(struct mlx5_eswitch *esw,
1737 struct mlx5_flow_table *fdb,
1738 u32 *flow_group_in,
1739 int *ix)
1740 {
1741 int max_peer_ports = (esw->total_vports - 1) * (MLX5_MAX_PORTS - 1);
1742 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1743 struct mlx5_flow_group *g;
1744 void *match_criteria;
1745 int err = 0;
1746
1747 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1748 return 0;
1749
1750 memset(flow_group_in, 0, inlen);
1751
1752 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, 0);
1753
1754 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1755 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1756 flow_group_in,
1757 match_criteria);
1758
1759 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1760 misc_parameters.source_eswitch_owner_vhca_id);
1761
1762 MLX5_SET(create_flow_group_in, flow_group_in,
1763 source_eswitch_owner_vhca_id_valid, 1);
1764 }
1765
1766 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1767 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1768 *ix + max_peer_ports);
1769 *ix += max_peer_ports + 1;
1770
1771 g = mlx5_create_flow_group(fdb, flow_group_in);
1772 if (IS_ERR(g)) {
1773 err = PTR_ERR(g);
1774 esw_warn(esw->dev, "Failed to create peer miss flow group err(%d)\n", err);
1775 goto out;
1776 }
1777 esw->fdb_table.offloads.peer_miss_grp = g;
1778
1779 out:
1780 return err;
1781 }
1782
1783 static int
esw_create_miss_group(struct mlx5_eswitch * esw,struct mlx5_flow_table * fdb,u32 * flow_group_in,int * ix)1784 esw_create_miss_group(struct mlx5_eswitch *esw,
1785 struct mlx5_flow_table *fdb,
1786 u32 *flow_group_in,
1787 int *ix)
1788 {
1789 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1790 struct mlx5_flow_group *g;
1791 void *match_criteria;
1792 int err = 0;
1793 u8 *dmac;
1794
1795 memset(flow_group_in, 0, inlen);
1796
1797 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1798 MLX5_MATCH_OUTER_HEADERS);
1799 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1800 match_criteria);
1801 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1802 outer_headers.dmac_47_16);
1803 dmac[0] = 0x01;
1804
1805 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1806 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1807 *ix + MLX5_ESW_MISS_FLOWS);
1808
1809 g = mlx5_create_flow_group(fdb, flow_group_in);
1810 if (IS_ERR(g)) {
1811 err = PTR_ERR(g);
1812 esw_warn(esw->dev, "Failed to create miss flow group err(%d)\n", err);
1813 goto miss_err;
1814 }
1815 esw->fdb_table.offloads.miss_grp = g;
1816
1817 err = esw_add_fdb_miss_rule(esw);
1818 if (err)
1819 goto miss_rule_err;
1820
1821 return 0;
1822
1823 miss_rule_err:
1824 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1825 miss_err:
1826 return err;
1827 }
1828
esw_create_offloads_fdb_tables(struct mlx5_eswitch * esw)1829 static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1830 {
1831 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1832 struct mlx5_flow_table_attr ft_attr = {};
1833 struct mlx5_core_dev *dev = esw->dev;
1834 struct mlx5_flow_namespace *root_ns;
1835 struct mlx5_flow_table *fdb = NULL;
1836 int table_size, ix = 0, err = 0;
1837 u32 flags = 0, *flow_group_in;
1838
1839 esw_debug(esw->dev, "Create offloads FDB Tables\n");
1840
1841 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1842 if (!flow_group_in)
1843 return -ENOMEM;
1844
1845 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1846 if (!root_ns) {
1847 esw_warn(dev, "Failed to get FDB flow namespace\n");
1848 err = -EOPNOTSUPP;
1849 goto ns_err;
1850 }
1851 esw->fdb_table.offloads.ns = root_ns;
1852 err = mlx5_flow_namespace_set_mode(root_ns,
1853 esw->dev->priv.steering->mode);
1854 if (err) {
1855 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1856 goto ns_err;
1857 }
1858
1859 /* To be strictly correct:
1860 * MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ)
1861 * should be:
1862 * esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
1863 * peer_esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ
1864 * but as the peer device might not be in switchdev mode it's not
1865 * possible. We use the fact that by default FW sets max vfs and max sfs
1866 * to the same value on both devices. If it needs to be changed in the future note
1867 * the peer miss group should also be created based on the number of
1868 * total vports of the peer (currently is also uses esw->total_vports).
1869 */
1870 table_size = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ) +
1871 esw->total_vports * MLX5_MAX_PORTS + MLX5_ESW_MISS_FLOWS;
1872
1873 /* create the slow path fdb with encap set, so further table instances
1874 * can be created at run time while VFs are probed if the FW allows that.
1875 */
1876 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1877 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1878 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1879
1880 ft_attr.flags = flags;
1881 ft_attr.max_fte = table_size;
1882 ft_attr.prio = FDB_SLOW_PATH;
1883
1884 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1885 if (IS_ERR(fdb)) {
1886 err = PTR_ERR(fdb);
1887 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1888 goto slow_fdb_err;
1889 }
1890 esw->fdb_table.offloads.slow_fdb = fdb;
1891
1892 /* Create empty TC-miss managed table. This allows plugging in following
1893 * priorities without directly exposing their level 0 table to
1894 * eswitch_offloads and passing it as miss_fdb to following call to
1895 * esw_chains_create().
1896 */
1897 memset(&ft_attr, 0, sizeof(ft_attr));
1898 ft_attr.prio = FDB_TC_MISS;
1899 esw->fdb_table.offloads.tc_miss_table = mlx5_create_flow_table(root_ns, &ft_attr);
1900 if (IS_ERR(esw->fdb_table.offloads.tc_miss_table)) {
1901 err = PTR_ERR(esw->fdb_table.offloads.tc_miss_table);
1902 esw_warn(dev, "Failed to create TC miss FDB Table err %d\n", err);
1903 goto tc_miss_table_err;
1904 }
1905
1906 err = esw_chains_create(esw, esw->fdb_table.offloads.tc_miss_table);
1907 if (err) {
1908 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
1909 goto fdb_chains_err;
1910 }
1911
1912 err = esw_create_send_to_vport_group(esw, fdb, flow_group_in, &ix);
1913 if (err)
1914 goto send_vport_err;
1915
1916 err = esw_create_meta_send_to_vport_group(esw, fdb, flow_group_in, &ix);
1917 if (err)
1918 goto send_vport_meta_err;
1919
1920 err = esw_create_peer_esw_miss_group(esw, fdb, flow_group_in, &ix);
1921 if (err)
1922 goto peer_miss_err;
1923
1924 err = esw_create_miss_group(esw, fdb, flow_group_in, &ix);
1925 if (err)
1926 goto miss_err;
1927
1928 kvfree(flow_group_in);
1929 return 0;
1930
1931 miss_err:
1932 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1933 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1934 peer_miss_err:
1935 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1936 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1937 send_vport_meta_err:
1938 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1939 send_vport_err:
1940 esw_chains_destroy(esw, esw_chains(esw));
1941 fdb_chains_err:
1942 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1943 tc_miss_table_err:
1944 mlx5_destroy_flow_table(mlx5_eswitch_get_slow_fdb(esw));
1945 slow_fdb_err:
1946 /* Holds true only as long as DMFS is the default */
1947 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
1948 ns_err:
1949 kvfree(flow_group_in);
1950 return err;
1951 }
1952
esw_destroy_offloads_fdb_tables(struct mlx5_eswitch * esw)1953 static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
1954 {
1955 if (!mlx5_eswitch_get_slow_fdb(esw))
1956 return;
1957
1958 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
1959 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1960 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1961 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1962 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1963 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1964 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1965 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1966 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1967
1968 esw_chains_destroy(esw, esw_chains(esw));
1969
1970 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1971 mlx5_destroy_flow_table(mlx5_eswitch_get_slow_fdb(esw));
1972 /* Holds true only as long as DMFS is the default */
1973 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1974 MLX5_FLOW_STEERING_MODE_DMFS);
1975 atomic64_set(&esw->user_count, 0);
1976 }
1977
esw_get_nr_ft_offloads_steering_src_ports(struct mlx5_eswitch * esw)1978 static int esw_get_nr_ft_offloads_steering_src_ports(struct mlx5_eswitch *esw)
1979 {
1980 int nvports;
1981
1982 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1983 if (mlx5e_tc_int_port_supported(esw))
1984 nvports += MLX5E_TC_MAX_INT_PORT_NUM;
1985
1986 return nvports;
1987 }
1988
esw_create_offloads_table(struct mlx5_eswitch * esw)1989 static int esw_create_offloads_table(struct mlx5_eswitch *esw)
1990 {
1991 struct mlx5_flow_table_attr ft_attr = {};
1992 struct mlx5_core_dev *dev = esw->dev;
1993 struct mlx5_flow_table *ft_offloads;
1994 struct mlx5_flow_namespace *ns;
1995 int err = 0;
1996
1997 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1998 if (!ns) {
1999 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2000 return -EOPNOTSUPP;
2001 }
2002
2003 ft_attr.max_fte = esw_get_nr_ft_offloads_steering_src_ports(esw) +
2004 MLX5_ESW_FT_OFFLOADS_DROP_RULE;
2005 ft_attr.prio = 1;
2006
2007 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
2008 if (IS_ERR(ft_offloads)) {
2009 err = PTR_ERR(ft_offloads);
2010 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
2011 return err;
2012 }
2013
2014 esw->offloads.ft_offloads = ft_offloads;
2015 return 0;
2016 }
2017
esw_destroy_offloads_table(struct mlx5_eswitch * esw)2018 static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
2019 {
2020 struct mlx5_esw_offload *offloads = &esw->offloads;
2021
2022 mlx5_destroy_flow_table(offloads->ft_offloads);
2023 }
2024
esw_create_vport_rx_group(struct mlx5_eswitch * esw)2025 static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
2026 {
2027 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2028 struct mlx5_flow_group *g;
2029 u32 *flow_group_in;
2030 int nvports;
2031 int err = 0;
2032
2033 nvports = esw_get_nr_ft_offloads_steering_src_ports(esw);
2034 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2035 if (!flow_group_in)
2036 return -ENOMEM;
2037
2038 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, 0);
2039
2040 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2041 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
2042
2043 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
2044
2045 if (IS_ERR(g)) {
2046 err = PTR_ERR(g);
2047 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
2048 goto out;
2049 }
2050
2051 esw->offloads.vport_rx_group = g;
2052 out:
2053 kvfree(flow_group_in);
2054 return err;
2055 }
2056
esw_destroy_vport_rx_group(struct mlx5_eswitch * esw)2057 static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
2058 {
2059 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
2060 }
2061
esw_create_vport_rx_drop_rule_index(struct mlx5_eswitch * esw)2062 static int esw_create_vport_rx_drop_rule_index(struct mlx5_eswitch *esw)
2063 {
2064 /* ft_offloads table is enlarged by MLX5_ESW_FT_OFFLOADS_DROP_RULE (1)
2065 * for the drop rule, which is placed at the end of the table.
2066 * So return the total of vport and int_port as rule index.
2067 */
2068 return esw_get_nr_ft_offloads_steering_src_ports(esw);
2069 }
2070
esw_create_vport_rx_drop_group(struct mlx5_eswitch * esw)2071 static int esw_create_vport_rx_drop_group(struct mlx5_eswitch *esw)
2072 {
2073 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2074 struct mlx5_flow_group *g;
2075 u32 *flow_group_in;
2076 int flow_index;
2077 int err = 0;
2078
2079 flow_index = esw_create_vport_rx_drop_rule_index(esw);
2080
2081 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2082 if (!flow_group_in)
2083 return -ENOMEM;
2084
2085 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, flow_index);
2086 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, flow_index);
2087
2088 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
2089
2090 if (IS_ERR(g)) {
2091 err = PTR_ERR(g);
2092 mlx5_core_warn(esw->dev, "Failed to create vport rx drop group err %d\n", err);
2093 goto out;
2094 }
2095
2096 esw->offloads.vport_rx_drop_group = g;
2097 out:
2098 kvfree(flow_group_in);
2099 return err;
2100 }
2101
esw_destroy_vport_rx_drop_group(struct mlx5_eswitch * esw)2102 static void esw_destroy_vport_rx_drop_group(struct mlx5_eswitch *esw)
2103 {
2104 if (esw->offloads.vport_rx_drop_group)
2105 mlx5_destroy_flow_group(esw->offloads.vport_rx_drop_group);
2106 }
2107
2108 void
mlx5_esw_set_spec_source_port(struct mlx5_eswitch * esw,u16 vport,struct mlx5_flow_spec * spec)2109 mlx5_esw_set_spec_source_port(struct mlx5_eswitch *esw,
2110 u16 vport,
2111 struct mlx5_flow_spec *spec)
2112 {
2113 void *misc;
2114
2115 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
2116 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
2117 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2118 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
2119
2120 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
2121 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2122 mlx5_eswitch_get_vport_metadata_mask());
2123
2124 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
2125 } else {
2126 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
2127 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
2128
2129 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
2130 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2131
2132 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
2133 }
2134 }
2135
2136 struct mlx5_flow_handle *
mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch * esw,u16 vport,struct mlx5_flow_destination * dest)2137 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
2138 struct mlx5_flow_destination *dest)
2139 {
2140 struct mlx5_flow_act flow_act = {0};
2141 struct mlx5_flow_handle *flow_rule;
2142 struct mlx5_flow_spec *spec;
2143
2144 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2145 if (!spec) {
2146 flow_rule = ERR_PTR(-ENOMEM);
2147 goto out;
2148 }
2149
2150 mlx5_esw_set_spec_source_port(esw, vport, spec);
2151
2152 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2153 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
2154 &flow_act, dest, 1);
2155 if (IS_ERR(flow_rule)) {
2156 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
2157 goto out;
2158 }
2159
2160 out:
2161 kvfree(spec);
2162 return flow_rule;
2163 }
2164
esw_create_vport_rx_drop_rule(struct mlx5_eswitch * esw)2165 static int esw_create_vport_rx_drop_rule(struct mlx5_eswitch *esw)
2166 {
2167 struct mlx5_flow_act flow_act = {};
2168 struct mlx5_flow_handle *flow_rule;
2169
2170 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2171 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, NULL,
2172 &flow_act, NULL, 0);
2173 if (IS_ERR(flow_rule)) {
2174 esw_warn(esw->dev,
2175 "fs offloads: Failed to add vport rx drop rule err %ld\n",
2176 PTR_ERR(flow_rule));
2177 return PTR_ERR(flow_rule);
2178 }
2179
2180 esw->offloads.vport_rx_drop_rule = flow_rule;
2181
2182 return 0;
2183 }
2184
esw_destroy_vport_rx_drop_rule(struct mlx5_eswitch * esw)2185 static void esw_destroy_vport_rx_drop_rule(struct mlx5_eswitch *esw)
2186 {
2187 if (esw->offloads.vport_rx_drop_rule)
2188 mlx5_del_flow_rules(esw->offloads.vport_rx_drop_rule);
2189 }
2190
mlx5_eswitch_inline_mode_get(struct mlx5_eswitch * esw,u8 * mode)2191 static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
2192 {
2193 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
2194 struct mlx5_core_dev *dev = esw->dev;
2195 struct mlx5_vport *vport;
2196 unsigned long i;
2197
2198 if (!MLX5_CAP_GEN(dev, vport_group_manager))
2199 return -EOPNOTSUPP;
2200
2201 if (!mlx5_esw_is_fdb_created(esw))
2202 return -EOPNOTSUPP;
2203
2204 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2205 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2206 mlx5_mode = MLX5_INLINE_MODE_NONE;
2207 goto out;
2208 case MLX5_CAP_INLINE_MODE_L2:
2209 mlx5_mode = MLX5_INLINE_MODE_L2;
2210 goto out;
2211 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2212 goto query_vports;
2213 }
2214
2215 query_vports:
2216 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
2217 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
2218 mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode);
2219 if (prev_mlx5_mode != mlx5_mode)
2220 return -EINVAL;
2221 prev_mlx5_mode = mlx5_mode;
2222 }
2223
2224 out:
2225 *mode = mlx5_mode;
2226 return 0;
2227 }
2228
esw_destroy_restore_table(struct mlx5_eswitch * esw)2229 static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
2230 {
2231 struct mlx5_esw_offload *offloads = &esw->offloads;
2232
2233 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2234 return;
2235
2236 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
2237 mlx5_destroy_flow_group(offloads->restore_group);
2238 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
2239 }
2240
esw_create_restore_table(struct mlx5_eswitch * esw)2241 static int esw_create_restore_table(struct mlx5_eswitch *esw)
2242 {
2243 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
2244 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2245 struct mlx5_flow_table_attr ft_attr = {};
2246 struct mlx5_core_dev *dev = esw->dev;
2247 struct mlx5_flow_namespace *ns;
2248 struct mlx5_modify_hdr *mod_hdr;
2249 void *match_criteria, *misc;
2250 struct mlx5_flow_table *ft;
2251 struct mlx5_flow_group *g;
2252 u32 *flow_group_in;
2253 int err = 0;
2254
2255 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2256 return 0;
2257
2258 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2259 if (!ns) {
2260 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2261 return -EOPNOTSUPP;
2262 }
2263
2264 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2265 if (!flow_group_in) {
2266 err = -ENOMEM;
2267 goto out_free;
2268 }
2269
2270 ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS;
2271 ft = mlx5_create_flow_table(ns, &ft_attr);
2272 if (IS_ERR(ft)) {
2273 err = PTR_ERR(ft);
2274 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
2275 err);
2276 goto out_free;
2277 }
2278
2279 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2280 match_criteria);
2281 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
2282 misc_parameters_2);
2283
2284 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2285 ESW_REG_C0_USER_DATA_METADATA_MASK);
2286 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2287 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
2288 ft_attr.max_fte - 1);
2289 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2290 MLX5_MATCH_MISC_PARAMETERS_2);
2291 g = mlx5_create_flow_group(ft, flow_group_in);
2292 if (IS_ERR(g)) {
2293 err = PTR_ERR(g);
2294 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
2295 err);
2296 goto err_group;
2297 }
2298
2299 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
2300 MLX5_SET(copy_action_in, modact, src_field,
2301 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
2302 MLX5_SET(copy_action_in, modact, dst_field,
2303 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
2304 mod_hdr = mlx5_modify_header_alloc(esw->dev,
2305 MLX5_FLOW_NAMESPACE_KERNEL, 1,
2306 modact);
2307 if (IS_ERR(mod_hdr)) {
2308 err = PTR_ERR(mod_hdr);
2309 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
2310 err);
2311 goto err_mod_hdr;
2312 }
2313
2314 esw->offloads.ft_offloads_restore = ft;
2315 esw->offloads.restore_group = g;
2316 esw->offloads.restore_copy_hdr_id = mod_hdr;
2317
2318 kvfree(flow_group_in);
2319
2320 return 0;
2321
2322 err_mod_hdr:
2323 mlx5_destroy_flow_group(g);
2324 err_group:
2325 mlx5_destroy_flow_table(ft);
2326 out_free:
2327 kvfree(flow_group_in);
2328
2329 return err;
2330 }
2331
esw_mode_change(struct mlx5_eswitch * esw,u16 mode)2332 static void esw_mode_change(struct mlx5_eswitch *esw, u16 mode)
2333 {
2334 mlx5_devcom_comp_lock(esw->dev->priv.hca_devcom_comp);
2335 if (esw->dev->priv.flags & MLX5_PRIV_FLAGS_DISABLE_IB_ADEV ||
2336 mlx5_core_mp_enabled(esw->dev)) {
2337 esw->mode = mode;
2338 mlx5_rescan_drivers_locked(esw->dev);
2339 mlx5_devcom_comp_unlock(esw->dev->priv.hca_devcom_comp);
2340 return;
2341 }
2342
2343 esw->dev->priv.flags |= MLX5_PRIV_FLAGS_DISABLE_IB_ADEV;
2344 mlx5_rescan_drivers_locked(esw->dev);
2345 esw->mode = mode;
2346 esw->dev->priv.flags &= ~MLX5_PRIV_FLAGS_DISABLE_IB_ADEV;
2347 mlx5_rescan_drivers_locked(esw->dev);
2348 mlx5_devcom_comp_unlock(esw->dev->priv.hca_devcom_comp);
2349 }
2350
esw_offloads_start(struct mlx5_eswitch * esw,struct netlink_ext_ack * extack)2351 static int esw_offloads_start(struct mlx5_eswitch *esw,
2352 struct netlink_ext_ack *extack)
2353 {
2354 int err;
2355
2356 esw_mode_change(esw, MLX5_ESWITCH_OFFLOADS);
2357 err = mlx5_eswitch_enable_locked(esw, esw->dev->priv.sriov.num_vfs);
2358 if (err) {
2359 NL_SET_ERR_MSG_MOD(extack,
2360 "Failed setting eswitch to offloads");
2361 esw_mode_change(esw, MLX5_ESWITCH_LEGACY);
2362 return err;
2363 }
2364 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
2365 if (mlx5_eswitch_inline_mode_get(esw,
2366 &esw->offloads.inline_mode)) {
2367 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
2368 NL_SET_ERR_MSG_MOD(extack,
2369 "Inline mode is different between vports");
2370 }
2371 }
2372 return 0;
2373 }
2374
mlx5_esw_offloads_rep_init(struct mlx5_eswitch * esw,const struct mlx5_vport * vport)2375 static int mlx5_esw_offloads_rep_init(struct mlx5_eswitch *esw, const struct mlx5_vport *vport)
2376 {
2377 struct mlx5_eswitch_rep *rep;
2378 int rep_type;
2379 int err;
2380
2381 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
2382 if (!rep)
2383 return -ENOMEM;
2384
2385 rep->vport = vport->vport;
2386 rep->vport_index = vport->index;
2387 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2388 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
2389
2390 err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL);
2391 if (err)
2392 goto insert_err;
2393
2394 return 0;
2395
2396 insert_err:
2397 kfree(rep);
2398 return err;
2399 }
2400
mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch * esw,struct mlx5_eswitch_rep * rep)2401 static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw,
2402 struct mlx5_eswitch_rep *rep)
2403 {
2404 xa_erase(&esw->offloads.vport_reps, rep->vport);
2405 kfree(rep);
2406 }
2407
esw_offloads_cleanup_reps(struct mlx5_eswitch * esw)2408 static void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
2409 {
2410 struct mlx5_eswitch_rep *rep;
2411 unsigned long i;
2412
2413 mlx5_esw_for_each_rep(esw, i, rep)
2414 mlx5_esw_offloads_rep_cleanup(esw, rep);
2415 xa_destroy(&esw->offloads.vport_reps);
2416 }
2417
esw_offloads_init_reps(struct mlx5_eswitch * esw)2418 static int esw_offloads_init_reps(struct mlx5_eswitch *esw)
2419 {
2420 struct mlx5_vport *vport;
2421 unsigned long i;
2422 int err;
2423
2424 xa_init(&esw->offloads.vport_reps);
2425
2426 mlx5_esw_for_each_vport(esw, i, vport) {
2427 err = mlx5_esw_offloads_rep_init(esw, vport);
2428 if (err)
2429 goto err;
2430 }
2431 return 0;
2432
2433 err:
2434 esw_offloads_cleanup_reps(esw);
2435 return err;
2436 }
2437
esw_port_metadata_set(struct devlink * devlink,u32 id,struct devlink_param_gset_ctx * ctx,struct netlink_ext_ack * extack)2438 static int esw_port_metadata_set(struct devlink *devlink, u32 id,
2439 struct devlink_param_gset_ctx *ctx,
2440 struct netlink_ext_ack *extack)
2441 {
2442 struct mlx5_core_dev *dev = devlink_priv(devlink);
2443 struct mlx5_eswitch *esw = dev->priv.eswitch;
2444 int err = 0;
2445
2446 down_write(&esw->mode_lock);
2447 if (mlx5_esw_is_fdb_created(esw)) {
2448 err = -EBUSY;
2449 goto done;
2450 }
2451 if (!mlx5_esw_vport_match_metadata_supported(esw)) {
2452 err = -EOPNOTSUPP;
2453 goto done;
2454 }
2455 if (ctx->val.vbool)
2456 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2457 else
2458 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2459 done:
2460 up_write(&esw->mode_lock);
2461 return err;
2462 }
2463
esw_port_metadata_get(struct devlink * devlink,u32 id,struct devlink_param_gset_ctx * ctx)2464 static int esw_port_metadata_get(struct devlink *devlink, u32 id,
2465 struct devlink_param_gset_ctx *ctx)
2466 {
2467 struct mlx5_core_dev *dev = devlink_priv(devlink);
2468
2469 ctx->val.vbool = mlx5_eswitch_vport_match_metadata_enabled(dev->priv.eswitch);
2470 return 0;
2471 }
2472
esw_port_metadata_validate(struct devlink * devlink,u32 id,union devlink_param_value val,struct netlink_ext_ack * extack)2473 static int esw_port_metadata_validate(struct devlink *devlink, u32 id,
2474 union devlink_param_value val,
2475 struct netlink_ext_ack *extack)
2476 {
2477 struct mlx5_core_dev *dev = devlink_priv(devlink);
2478 u8 esw_mode;
2479
2480 esw_mode = mlx5_eswitch_mode(dev);
2481 if (esw_mode == MLX5_ESWITCH_OFFLOADS) {
2482 NL_SET_ERR_MSG_MOD(extack,
2483 "E-Switch must either disabled or non switchdev mode");
2484 return -EBUSY;
2485 }
2486 return 0;
2487 }
2488
2489 static const struct devlink_param esw_devlink_params[] = {
2490 DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_ESW_PORT_METADATA,
2491 "esw_port_metadata", DEVLINK_PARAM_TYPE_BOOL,
2492 BIT(DEVLINK_PARAM_CMODE_RUNTIME),
2493 esw_port_metadata_get,
2494 esw_port_metadata_set,
2495 esw_port_metadata_validate),
2496 };
2497
esw_offloads_init(struct mlx5_eswitch * esw)2498 int esw_offloads_init(struct mlx5_eswitch *esw)
2499 {
2500 int err;
2501
2502 err = esw_offloads_init_reps(esw);
2503 if (err)
2504 return err;
2505
2506 if (MLX5_ESWITCH_MANAGER(esw->dev) &&
2507 mlx5_esw_vport_match_metadata_supported(esw))
2508 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2509
2510 err = devl_params_register(priv_to_devlink(esw->dev),
2511 esw_devlink_params,
2512 ARRAY_SIZE(esw_devlink_params));
2513 if (err)
2514 goto err_params;
2515
2516 return 0;
2517
2518 err_params:
2519 esw_offloads_cleanup_reps(esw);
2520 return err;
2521 }
2522
esw_offloads_cleanup(struct mlx5_eswitch * esw)2523 void esw_offloads_cleanup(struct mlx5_eswitch *esw)
2524 {
2525 devl_params_unregister(priv_to_devlink(esw->dev),
2526 esw_devlink_params,
2527 ARRAY_SIZE(esw_devlink_params));
2528 esw_offloads_cleanup_reps(esw);
2529 }
2530
__esw_offloads_load_rep(struct mlx5_eswitch * esw,struct mlx5_eswitch_rep * rep,u8 rep_type)2531 static int __esw_offloads_load_rep(struct mlx5_eswitch *esw,
2532 struct mlx5_eswitch_rep *rep, u8 rep_type)
2533 {
2534 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2535 REP_REGISTERED, REP_LOADED) == REP_REGISTERED)
2536 return esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
2537
2538 return 0;
2539 }
2540
__esw_offloads_unload_rep(struct mlx5_eswitch * esw,struct mlx5_eswitch_rep * rep,u8 rep_type)2541 static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
2542 struct mlx5_eswitch_rep *rep, u8 rep_type)
2543 {
2544 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2545 REP_LOADED, REP_REGISTERED) == REP_LOADED) {
2546 if (rep_type == REP_ETH)
2547 __esw_offloads_unload_rep(esw, rep, REP_IB);
2548 esw->offloads.rep_ops[rep_type]->unload(rep);
2549 }
2550 }
2551
__unload_reps_all_vport(struct mlx5_eswitch * esw,u8 rep_type)2552 static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
2553 {
2554 struct mlx5_eswitch_rep *rep;
2555 unsigned long i;
2556
2557 mlx5_esw_for_each_rep(esw, i, rep)
2558 __esw_offloads_unload_rep(esw, rep, rep_type);
2559 }
2560
mlx5_esw_offloads_rep_load(struct mlx5_eswitch * esw,u16 vport_num)2561 static int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
2562 {
2563 struct mlx5_eswitch_rep *rep;
2564 int rep_type;
2565 int err;
2566
2567 rep = mlx5_eswitch_get_rep(esw, vport_num);
2568 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
2569 err = __esw_offloads_load_rep(esw, rep, rep_type);
2570 if (err)
2571 goto err_reps;
2572 }
2573
2574 return 0;
2575
2576 err_reps:
2577 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2578 for (--rep_type; rep_type >= 0; rep_type--)
2579 __esw_offloads_unload_rep(esw, rep, rep_type);
2580 return err;
2581 }
2582
mlx5_esw_offloads_rep_unload(struct mlx5_eswitch * esw,u16 vport_num)2583 static void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
2584 {
2585 struct mlx5_eswitch_rep *rep;
2586 int rep_type;
2587
2588 rep = mlx5_eswitch_get_rep(esw, vport_num);
2589 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
2590 __esw_offloads_unload_rep(esw, rep, rep_type);
2591 }
2592
mlx5_esw_offloads_init_pf_vf_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport)2593 int mlx5_esw_offloads_init_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2594 {
2595 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2596 return 0;
2597
2598 return mlx5_esw_offloads_pf_vf_devlink_port_init(esw, vport);
2599 }
2600
mlx5_esw_offloads_cleanup_pf_vf_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport)2601 void mlx5_esw_offloads_cleanup_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2602 {
2603 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2604 return;
2605
2606 mlx5_esw_offloads_pf_vf_devlink_port_cleanup(esw, vport);
2607 }
2608
mlx5_esw_offloads_init_sf_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport,struct mlx5_devlink_port * dl_port,u32 controller,u32 sfnum)2609 int mlx5_esw_offloads_init_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport,
2610 struct mlx5_devlink_port *dl_port,
2611 u32 controller, u32 sfnum)
2612 {
2613 return mlx5_esw_offloads_sf_devlink_port_init(esw, vport, dl_port, controller, sfnum);
2614 }
2615
mlx5_esw_offloads_cleanup_sf_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport)2616 void mlx5_esw_offloads_cleanup_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2617 {
2618 mlx5_esw_offloads_sf_devlink_port_cleanup(esw, vport);
2619 }
2620
mlx5_esw_offloads_load_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport)2621 int mlx5_esw_offloads_load_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2622 {
2623 int err;
2624
2625 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2626 return 0;
2627
2628 err = mlx5_esw_offloads_devlink_port_register(esw, vport);
2629 if (err)
2630 return err;
2631
2632 err = mlx5_esw_offloads_rep_load(esw, vport->vport);
2633 if (err)
2634 goto load_err;
2635 return err;
2636
2637 load_err:
2638 mlx5_esw_offloads_devlink_port_unregister(vport);
2639 return err;
2640 }
2641
mlx5_esw_offloads_unload_rep(struct mlx5_eswitch * esw,struct mlx5_vport * vport)2642 void mlx5_esw_offloads_unload_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport)
2643 {
2644 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2645 return;
2646
2647 mlx5_esw_offloads_rep_unload(esw, vport->vport);
2648
2649 mlx5_esw_offloads_devlink_port_unregister(vport);
2650 }
2651
esw_set_slave_root_fdb(struct mlx5_core_dev * master,struct mlx5_core_dev * slave)2652 static int esw_set_slave_root_fdb(struct mlx5_core_dev *master,
2653 struct mlx5_core_dev *slave)
2654 {
2655 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {};
2656 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {};
2657 struct mlx5_flow_root_namespace *root;
2658 struct mlx5_flow_namespace *ns;
2659 int err;
2660
2661 MLX5_SET(set_flow_table_root_in, in, opcode,
2662 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT);
2663 MLX5_SET(set_flow_table_root_in, in, table_type,
2664 FS_FT_FDB);
2665
2666 if (master) {
2667 ns = mlx5_get_flow_namespace(master,
2668 MLX5_FLOW_NAMESPACE_FDB);
2669 root = find_root(&ns->node);
2670 mutex_lock(&root->chain_lock);
2671 MLX5_SET(set_flow_table_root_in, in,
2672 table_eswitch_owner_vhca_id_valid, 1);
2673 MLX5_SET(set_flow_table_root_in, in,
2674 table_eswitch_owner_vhca_id,
2675 MLX5_CAP_GEN(master, vhca_id));
2676 MLX5_SET(set_flow_table_root_in, in, table_id,
2677 root->root_ft->id);
2678 } else {
2679 ns = mlx5_get_flow_namespace(slave,
2680 MLX5_FLOW_NAMESPACE_FDB);
2681 root = find_root(&ns->node);
2682 mutex_lock(&root->chain_lock);
2683 MLX5_SET(set_flow_table_root_in, in, table_id,
2684 root->root_ft->id);
2685 }
2686
2687 err = mlx5_cmd_exec(slave, in, sizeof(in), out, sizeof(out));
2688 mutex_unlock(&root->chain_lock);
2689
2690 return err;
2691 }
2692
__esw_set_master_egress_rule(struct mlx5_core_dev * master,struct mlx5_core_dev * slave,struct mlx5_vport * vport,struct mlx5_flow_table * acl)2693 static int __esw_set_master_egress_rule(struct mlx5_core_dev *master,
2694 struct mlx5_core_dev *slave,
2695 struct mlx5_vport *vport,
2696 struct mlx5_flow_table *acl)
2697 {
2698 u16 slave_index = MLX5_CAP_GEN(slave, vhca_id);
2699 struct mlx5_flow_handle *flow_rule = NULL;
2700 struct mlx5_flow_destination dest = {};
2701 struct mlx5_flow_act flow_act = {};
2702 struct mlx5_flow_spec *spec;
2703 int err = 0;
2704 void *misc;
2705
2706 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2707 if (!spec)
2708 return -ENOMEM;
2709
2710 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
2711 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2712 misc_parameters);
2713 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_UPLINK);
2714 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id, slave_index);
2715
2716 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
2717 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2718 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
2719 source_eswitch_owner_vhca_id);
2720
2721 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2722 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
2723 dest.vport.num = slave->priv.eswitch->manager_vport;
2724 dest.vport.vhca_id = MLX5_CAP_GEN(slave, vhca_id);
2725 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
2726
2727 flow_rule = mlx5_add_flow_rules(acl, spec, &flow_act,
2728 &dest, 1);
2729 if (IS_ERR(flow_rule)) {
2730 err = PTR_ERR(flow_rule);
2731 } else {
2732 err = xa_insert(&vport->egress.offloads.bounce_rules,
2733 slave_index, flow_rule, GFP_KERNEL);
2734 if (err)
2735 mlx5_del_flow_rules(flow_rule);
2736 }
2737
2738 kvfree(spec);
2739 return err;
2740 }
2741
esw_master_egress_create_resources(struct mlx5_eswitch * esw,struct mlx5_flow_namespace * egress_ns,struct mlx5_vport * vport,size_t count)2742 static int esw_master_egress_create_resources(struct mlx5_eswitch *esw,
2743 struct mlx5_flow_namespace *egress_ns,
2744 struct mlx5_vport *vport, size_t count)
2745 {
2746 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2747 struct mlx5_flow_table_attr ft_attr = {
2748 .max_fte = count, .prio = 0, .level = 0,
2749 };
2750 struct mlx5_flow_table *acl;
2751 struct mlx5_flow_group *g;
2752 void *match_criteria;
2753 u32 *flow_group_in;
2754 int err;
2755
2756 if (vport->egress.acl)
2757 return 0;
2758
2759 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2760 if (!flow_group_in)
2761 return -ENOMEM;
2762
2763 if (vport->vport || mlx5_core_is_ecpf(esw->dev))
2764 ft_attr.flags = MLX5_FLOW_TABLE_OTHER_VPORT;
2765
2766 acl = mlx5_create_vport_flow_table(egress_ns, &ft_attr, vport->vport);
2767 if (IS_ERR(acl)) {
2768 err = PTR_ERR(acl);
2769 goto out;
2770 }
2771
2772 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2773 match_criteria);
2774 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2775 misc_parameters.source_port);
2776 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2777 misc_parameters.source_eswitch_owner_vhca_id);
2778 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2779 MLX5_MATCH_MISC_PARAMETERS);
2780
2781 MLX5_SET(create_flow_group_in, flow_group_in,
2782 source_eswitch_owner_vhca_id_valid, 1);
2783 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2784 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, count);
2785
2786 g = mlx5_create_flow_group(acl, flow_group_in);
2787 if (IS_ERR(g)) {
2788 err = PTR_ERR(g);
2789 goto err_group;
2790 }
2791
2792 vport->egress.acl = acl;
2793 vport->egress.offloads.bounce_grp = g;
2794 vport->egress.type = VPORT_EGRESS_ACL_TYPE_SHARED_FDB;
2795 xa_init_flags(&vport->egress.offloads.bounce_rules, XA_FLAGS_ALLOC);
2796
2797 kvfree(flow_group_in);
2798
2799 return 0;
2800
2801 err_group:
2802 mlx5_destroy_flow_table(acl);
2803 out:
2804 kvfree(flow_group_in);
2805 return err;
2806 }
2807
esw_master_egress_destroy_resources(struct mlx5_vport * vport)2808 static void esw_master_egress_destroy_resources(struct mlx5_vport *vport)
2809 {
2810 if (!xa_empty(&vport->egress.offloads.bounce_rules))
2811 return;
2812 mlx5_destroy_flow_group(vport->egress.offloads.bounce_grp);
2813 vport->egress.offloads.bounce_grp = NULL;
2814 mlx5_destroy_flow_table(vport->egress.acl);
2815 vport->egress.acl = NULL;
2816 }
2817
esw_set_master_egress_rule(struct mlx5_core_dev * master,struct mlx5_core_dev * slave,size_t count)2818 static int esw_set_master_egress_rule(struct mlx5_core_dev *master,
2819 struct mlx5_core_dev *slave, size_t count)
2820 {
2821 struct mlx5_eswitch *esw = master->priv.eswitch;
2822 u16 slave_index = MLX5_CAP_GEN(slave, vhca_id);
2823 struct mlx5_flow_namespace *egress_ns;
2824 struct mlx5_vport *vport;
2825 int err;
2826
2827 vport = mlx5_eswitch_get_vport(esw, esw->manager_vport);
2828 if (IS_ERR(vport))
2829 return PTR_ERR(vport);
2830
2831 egress_ns = mlx5_get_flow_vport_acl_namespace(master,
2832 MLX5_FLOW_NAMESPACE_ESW_EGRESS,
2833 vport->index);
2834 if (!egress_ns)
2835 return -EINVAL;
2836
2837 if (vport->egress.acl && vport->egress.type != VPORT_EGRESS_ACL_TYPE_SHARED_FDB)
2838 return 0;
2839
2840 err = esw_master_egress_create_resources(esw, egress_ns, vport, count);
2841 if (err)
2842 return err;
2843
2844 if (xa_load(&vport->egress.offloads.bounce_rules, slave_index))
2845 return -EINVAL;
2846
2847 err = __esw_set_master_egress_rule(master, slave, vport, vport->egress.acl);
2848 if (err)
2849 goto err_rule;
2850
2851 return 0;
2852
2853 err_rule:
2854 esw_master_egress_destroy_resources(vport);
2855 return err;
2856 }
2857
esw_unset_master_egress_rule(struct mlx5_core_dev * dev,struct mlx5_core_dev * slave_dev)2858 static void esw_unset_master_egress_rule(struct mlx5_core_dev *dev,
2859 struct mlx5_core_dev *slave_dev)
2860 {
2861 struct mlx5_vport *vport;
2862
2863 vport = mlx5_eswitch_get_vport(dev->priv.eswitch,
2864 dev->priv.eswitch->manager_vport);
2865
2866 esw_acl_egress_ofld_bounce_rule_destroy(vport, MLX5_CAP_GEN(slave_dev, vhca_id));
2867
2868 if (xa_empty(&vport->egress.offloads.bounce_rules)) {
2869 esw_acl_egress_ofld_cleanup(vport);
2870 xa_destroy(&vport->egress.offloads.bounce_rules);
2871 }
2872 }
2873
mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch * master_esw,struct mlx5_eswitch * slave_esw,int max_slaves)2874 int mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw,
2875 struct mlx5_eswitch *slave_esw, int max_slaves)
2876 {
2877 int err;
2878
2879 err = esw_set_slave_root_fdb(master_esw->dev,
2880 slave_esw->dev);
2881 if (err)
2882 return err;
2883
2884 err = esw_set_master_egress_rule(master_esw->dev,
2885 slave_esw->dev, max_slaves);
2886 if (err)
2887 goto err_acl;
2888
2889 return err;
2890
2891 err_acl:
2892 esw_set_slave_root_fdb(NULL, slave_esw->dev);
2893 return err;
2894 }
2895
mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch * master_esw,struct mlx5_eswitch * slave_esw)2896 void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw,
2897 struct mlx5_eswitch *slave_esw)
2898 {
2899 esw_set_slave_root_fdb(NULL, slave_esw->dev);
2900 esw_unset_master_egress_rule(master_esw->dev, slave_esw->dev);
2901 }
2902
2903 #define ESW_OFFLOADS_DEVCOM_PAIR (0)
2904 #define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
2905
mlx5_esw_offloads_rep_event_unpair(struct mlx5_eswitch * esw,struct mlx5_eswitch * peer_esw)2906 static void mlx5_esw_offloads_rep_event_unpair(struct mlx5_eswitch *esw,
2907 struct mlx5_eswitch *peer_esw)
2908 {
2909 const struct mlx5_eswitch_rep_ops *ops;
2910 struct mlx5_eswitch_rep *rep;
2911 unsigned long i;
2912 u8 rep_type;
2913
2914 mlx5_esw_for_each_rep(esw, i, rep) {
2915 rep_type = NUM_REP_TYPES;
2916 while (rep_type--) {
2917 ops = esw->offloads.rep_ops[rep_type];
2918 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2919 ops->event)
2920 ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_UNPAIR, peer_esw);
2921 }
2922 }
2923 }
2924
mlx5_esw_offloads_unpair(struct mlx5_eswitch * esw,struct mlx5_eswitch * peer_esw)2925 static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw,
2926 struct mlx5_eswitch *peer_esw)
2927 {
2928 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
2929 mlx5e_tc_clean_fdb_peer_flows(esw);
2930 #endif
2931 mlx5_esw_offloads_rep_event_unpair(esw, peer_esw);
2932 esw_del_fdb_peer_miss_rules(esw, peer_esw->dev);
2933 }
2934
mlx5_esw_offloads_pair(struct mlx5_eswitch * esw,struct mlx5_eswitch * peer_esw)2935 static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
2936 struct mlx5_eswitch *peer_esw)
2937 {
2938 const struct mlx5_eswitch_rep_ops *ops;
2939 struct mlx5_eswitch_rep *rep;
2940 unsigned long i;
2941 u8 rep_type;
2942 int err;
2943
2944 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
2945 if (err)
2946 return err;
2947
2948 mlx5_esw_for_each_rep(esw, i, rep) {
2949 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
2950 ops = esw->offloads.rep_ops[rep_type];
2951 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2952 ops->event) {
2953 err = ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_PAIR, peer_esw);
2954 if (err)
2955 goto err_out;
2956 }
2957 }
2958 }
2959
2960 return 0;
2961
2962 err_out:
2963 mlx5_esw_offloads_unpair(esw, peer_esw);
2964 return err;
2965 }
2966
mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch * esw,struct mlx5_eswitch * peer_esw,bool pair)2967 static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
2968 struct mlx5_eswitch *peer_esw,
2969 bool pair)
2970 {
2971 u16 peer_vhca_id = MLX5_CAP_GEN(peer_esw->dev, vhca_id);
2972 u16 vhca_id = MLX5_CAP_GEN(esw->dev, vhca_id);
2973 struct mlx5_flow_root_namespace *peer_ns;
2974 struct mlx5_flow_root_namespace *ns;
2975 int err;
2976
2977 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
2978 ns = esw->dev->priv.steering->fdb_root_ns;
2979
2980 if (pair) {
2981 err = mlx5_flow_namespace_set_peer(ns, peer_ns, peer_vhca_id);
2982 if (err)
2983 return err;
2984
2985 err = mlx5_flow_namespace_set_peer(peer_ns, ns, vhca_id);
2986 if (err) {
2987 mlx5_flow_namespace_set_peer(ns, NULL, peer_vhca_id);
2988 return err;
2989 }
2990 } else {
2991 mlx5_flow_namespace_set_peer(ns, NULL, peer_vhca_id);
2992 mlx5_flow_namespace_set_peer(peer_ns, NULL, vhca_id);
2993 }
2994
2995 return 0;
2996 }
2997
mlx5_esw_offloads_devcom_event(int event,void * my_data,void * event_data)2998 static int mlx5_esw_offloads_devcom_event(int event,
2999 void *my_data,
3000 void *event_data)
3001 {
3002 struct mlx5_eswitch *esw = my_data;
3003 struct mlx5_eswitch *peer_esw = event_data;
3004 u16 esw_i, peer_esw_i;
3005 bool esw_paired;
3006 int err;
3007
3008 peer_esw_i = MLX5_CAP_GEN(peer_esw->dev, vhca_id);
3009 esw_i = MLX5_CAP_GEN(esw->dev, vhca_id);
3010 esw_paired = !!xa_load(&esw->paired, peer_esw_i);
3011
3012 switch (event) {
3013 case ESW_OFFLOADS_DEVCOM_PAIR:
3014 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
3015 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
3016 break;
3017
3018 if (esw_paired)
3019 break;
3020
3021 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
3022 if (err)
3023 goto err_out;
3024
3025 err = mlx5_esw_offloads_pair(esw, peer_esw);
3026 if (err)
3027 goto err_peer;
3028
3029 err = mlx5_esw_offloads_pair(peer_esw, esw);
3030 if (err)
3031 goto err_pair;
3032
3033 err = xa_insert(&esw->paired, peer_esw_i, peer_esw, GFP_KERNEL);
3034 if (err)
3035 goto err_xa;
3036
3037 err = xa_insert(&peer_esw->paired, esw_i, esw, GFP_KERNEL);
3038 if (err)
3039 goto err_peer_xa;
3040
3041 esw->num_peers++;
3042 peer_esw->num_peers++;
3043 mlx5_devcom_comp_set_ready(esw->devcom, true);
3044 break;
3045
3046 case ESW_OFFLOADS_DEVCOM_UNPAIR:
3047 if (!esw_paired)
3048 break;
3049
3050 peer_esw->num_peers--;
3051 esw->num_peers--;
3052 if (!esw->num_peers && !peer_esw->num_peers)
3053 mlx5_devcom_comp_set_ready(esw->devcom, false);
3054 xa_erase(&peer_esw->paired, esw_i);
3055 xa_erase(&esw->paired, peer_esw_i);
3056 mlx5_esw_offloads_unpair(peer_esw, esw);
3057 mlx5_esw_offloads_unpair(esw, peer_esw);
3058 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
3059 break;
3060 }
3061
3062 return 0;
3063
3064 err_peer_xa:
3065 xa_erase(&esw->paired, peer_esw_i);
3066 err_xa:
3067 mlx5_esw_offloads_unpair(peer_esw, esw);
3068 err_pair:
3069 mlx5_esw_offloads_unpair(esw, peer_esw);
3070 err_peer:
3071 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
3072 err_out:
3073 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
3074 event, err);
3075 return err;
3076 }
3077
mlx5_esw_offloads_devcom_init(struct mlx5_eswitch * esw,u64 key)3078 void mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw, u64 key)
3079 {
3080 int i;
3081
3082 for (i = 0; i < MLX5_MAX_PORTS; i++)
3083 INIT_LIST_HEAD(&esw->offloads.peer_flows[i]);
3084 mutex_init(&esw->offloads.peer_mutex);
3085
3086 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
3087 return;
3088
3089 if ((MLX5_VPORT_MANAGER(esw->dev) || mlx5_core_is_ecpf_esw_manager(esw->dev)) &&
3090 !mlx5_lag_is_supported(esw->dev))
3091 return;
3092
3093 xa_init(&esw->paired);
3094 esw->num_peers = 0;
3095 esw->devcom = mlx5_devcom_register_component(esw->dev->priv.devc,
3096 MLX5_DEVCOM_ESW_OFFLOADS,
3097 key,
3098 mlx5_esw_offloads_devcom_event,
3099 esw);
3100 if (IS_ERR(esw->devcom))
3101 return;
3102
3103 mlx5_devcom_send_event(esw->devcom,
3104 ESW_OFFLOADS_DEVCOM_PAIR,
3105 ESW_OFFLOADS_DEVCOM_UNPAIR,
3106 esw);
3107 }
3108
mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch * esw)3109 void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
3110 {
3111 if (IS_ERR_OR_NULL(esw->devcom))
3112 return;
3113
3114 mlx5_devcom_send_event(esw->devcom,
3115 ESW_OFFLOADS_DEVCOM_UNPAIR,
3116 ESW_OFFLOADS_DEVCOM_UNPAIR,
3117 esw);
3118
3119 mlx5_devcom_unregister_component(esw->devcom);
3120 xa_destroy(&esw->paired);
3121 esw->devcom = NULL;
3122 }
3123
mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch * esw)3124 bool mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch *esw)
3125 {
3126 return mlx5_devcom_comp_is_ready(esw->devcom);
3127 }
3128
mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch * esw)3129 bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
3130 {
3131 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
3132 return false;
3133
3134 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
3135 MLX5_FDB_TO_VPORT_REG_C_0))
3136 return false;
3137
3138 return true;
3139 }
3140
3141 #define MLX5_ESW_METADATA_RSVD_UPLINK 1
3142
3143 /* Share the same metadata for uplink's. This is fine because:
3144 * (a) In shared FDB mode (LAG) both uplink's are treated the
3145 * same and tagged with the same metadata.
3146 * (b) In non shared FDB mode, packets from physical port0
3147 * cannot hit eswitch of PF1 and vice versa.
3148 */
mlx5_esw_match_metadata_reserved(struct mlx5_eswitch * esw)3149 static u32 mlx5_esw_match_metadata_reserved(struct mlx5_eswitch *esw)
3150 {
3151 return MLX5_ESW_METADATA_RSVD_UPLINK;
3152 }
3153
mlx5_esw_match_metadata_alloc(struct mlx5_eswitch * esw)3154 u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
3155 {
3156 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
3157 /* Reserve 0xf for internal port offload */
3158 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 2;
3159 u32 pf_num;
3160 int id;
3161
3162 /* Only 4 bits of pf_num */
3163 pf_num = mlx5_get_dev_index(esw->dev);
3164 if (pf_num > max_pf_num)
3165 return 0;
3166
3167 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
3168 /* Use only non-zero vport_id (2-4095) for all PF's */
3169 id = ida_alloc_range(&esw->offloads.vport_metadata_ida,
3170 MLX5_ESW_METADATA_RSVD_UPLINK + 1,
3171 vport_end_ida, GFP_KERNEL);
3172 if (id < 0)
3173 return 0;
3174 id = (pf_num << ESW_VPORT_BITS) | id;
3175 return id;
3176 }
3177
mlx5_esw_match_metadata_free(struct mlx5_eswitch * esw,u32 metadata)3178 void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
3179 {
3180 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
3181
3182 /* Metadata contains only 12 bits of actual ida id */
3183 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
3184 }
3185
esw_offloads_vport_metadata_setup(struct mlx5_eswitch * esw,struct mlx5_vport * vport)3186 static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
3187 struct mlx5_vport *vport)
3188 {
3189 if (vport->vport == MLX5_VPORT_UPLINK)
3190 vport->default_metadata = mlx5_esw_match_metadata_reserved(esw);
3191 else
3192 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
3193
3194 vport->metadata = vport->default_metadata;
3195 return vport->metadata ? 0 : -ENOSPC;
3196 }
3197
esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch * esw,struct mlx5_vport * vport)3198 static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
3199 struct mlx5_vport *vport)
3200 {
3201 if (!vport->default_metadata)
3202 return;
3203
3204 if (vport->vport == MLX5_VPORT_UPLINK)
3205 return;
3206
3207 WARN_ON(vport->metadata != vport->default_metadata);
3208 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
3209 }
3210
esw_offloads_metadata_uninit(struct mlx5_eswitch * esw)3211 static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
3212 {
3213 struct mlx5_vport *vport;
3214 unsigned long i;
3215
3216 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
3217 return;
3218
3219 mlx5_esw_for_each_vport(esw, i, vport)
3220 esw_offloads_vport_metadata_cleanup(esw, vport);
3221 }
3222
esw_offloads_metadata_init(struct mlx5_eswitch * esw)3223 static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
3224 {
3225 struct mlx5_vport *vport;
3226 unsigned long i;
3227 int err;
3228
3229 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
3230 return 0;
3231
3232 mlx5_esw_for_each_vport(esw, i, vport) {
3233 err = esw_offloads_vport_metadata_setup(esw, vport);
3234 if (err)
3235 goto metadata_err;
3236 }
3237
3238 return 0;
3239
3240 metadata_err:
3241 esw_offloads_metadata_uninit(esw);
3242 return err;
3243 }
3244
3245 int
esw_vport_create_offloads_acl_tables(struct mlx5_eswitch * esw,struct mlx5_vport * vport)3246 esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
3247 struct mlx5_vport *vport)
3248 {
3249 int err;
3250
3251 err = esw_acl_ingress_ofld_setup(esw, vport);
3252 if (err)
3253 return err;
3254
3255 err = esw_acl_egress_ofld_setup(esw, vport);
3256 if (err)
3257 goto egress_err;
3258
3259 return 0;
3260
3261 egress_err:
3262 esw_acl_ingress_ofld_cleanup(esw, vport);
3263 return err;
3264 }
3265
3266 void
esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch * esw,struct mlx5_vport * vport)3267 esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
3268 struct mlx5_vport *vport)
3269 {
3270 esw_acl_egress_ofld_cleanup(vport);
3271 esw_acl_ingress_ofld_cleanup(esw, vport);
3272 }
3273
esw_create_offloads_acl_tables(struct mlx5_eswitch * esw)3274 static int esw_create_offloads_acl_tables(struct mlx5_eswitch *esw)
3275 {
3276 struct mlx5_vport *uplink, *manager;
3277 int ret;
3278
3279 uplink = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
3280 if (IS_ERR(uplink))
3281 return PTR_ERR(uplink);
3282
3283 ret = esw_vport_create_offloads_acl_tables(esw, uplink);
3284 if (ret)
3285 return ret;
3286
3287 manager = mlx5_eswitch_get_vport(esw, esw->manager_vport);
3288 if (IS_ERR(manager)) {
3289 ret = PTR_ERR(manager);
3290 goto err_manager;
3291 }
3292
3293 ret = esw_vport_create_offloads_acl_tables(esw, manager);
3294 if (ret)
3295 goto err_manager;
3296
3297 return 0;
3298
3299 err_manager:
3300 esw_vport_destroy_offloads_acl_tables(esw, uplink);
3301 return ret;
3302 }
3303
esw_destroy_offloads_acl_tables(struct mlx5_eswitch * esw)3304 static void esw_destroy_offloads_acl_tables(struct mlx5_eswitch *esw)
3305 {
3306 struct mlx5_vport *vport;
3307
3308 vport = mlx5_eswitch_get_vport(esw, esw->manager_vport);
3309 if (!IS_ERR(vport))
3310 esw_vport_destroy_offloads_acl_tables(esw, vport);
3311
3312 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
3313 if (!IS_ERR(vport))
3314 esw_vport_destroy_offloads_acl_tables(esw, vport);
3315 }
3316
mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch * esw)3317 int mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch *esw)
3318 {
3319 struct mlx5_eswitch_rep *rep;
3320 unsigned long i;
3321 int ret;
3322
3323 if (!esw || esw->mode != MLX5_ESWITCH_OFFLOADS)
3324 return 0;
3325
3326 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
3327 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
3328 return 0;
3329
3330 ret = __esw_offloads_load_rep(esw, rep, REP_IB);
3331 if (ret)
3332 return ret;
3333
3334 mlx5_esw_for_each_rep(esw, i, rep) {
3335 if (atomic_read(&rep->rep_data[REP_ETH].state) == REP_LOADED)
3336 __esw_offloads_load_rep(esw, rep, REP_IB);
3337 }
3338
3339 return 0;
3340 }
3341
esw_offloads_steering_init(struct mlx5_eswitch * esw)3342 static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
3343 {
3344 struct mlx5_esw_indir_table *indir;
3345 int err;
3346
3347 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
3348 mutex_init(&esw->fdb_table.offloads.vports.lock);
3349 hash_init(esw->fdb_table.offloads.vports.table);
3350 atomic64_set(&esw->user_count, 0);
3351
3352 indir = mlx5_esw_indir_table_init();
3353 if (IS_ERR(indir)) {
3354 err = PTR_ERR(indir);
3355 goto create_indir_err;
3356 }
3357 esw->fdb_table.offloads.indir = indir;
3358
3359 err = esw_create_offloads_acl_tables(esw);
3360 if (err)
3361 goto create_acl_err;
3362
3363 err = esw_create_offloads_table(esw);
3364 if (err)
3365 goto create_offloads_err;
3366
3367 err = esw_create_restore_table(esw);
3368 if (err)
3369 goto create_restore_err;
3370
3371 err = esw_create_offloads_fdb_tables(esw);
3372 if (err)
3373 goto create_fdb_err;
3374
3375 err = esw_create_vport_rx_group(esw);
3376 if (err)
3377 goto create_fg_err;
3378
3379 err = esw_create_vport_rx_drop_group(esw);
3380 if (err)
3381 goto create_rx_drop_fg_err;
3382
3383 err = esw_create_vport_rx_drop_rule(esw);
3384 if (err)
3385 goto create_rx_drop_rule_err;
3386
3387 return 0;
3388
3389 create_rx_drop_rule_err:
3390 esw_destroy_vport_rx_drop_group(esw);
3391 create_rx_drop_fg_err:
3392 esw_destroy_vport_rx_group(esw);
3393 create_fg_err:
3394 esw_destroy_offloads_fdb_tables(esw);
3395 create_fdb_err:
3396 esw_destroy_restore_table(esw);
3397 create_restore_err:
3398 esw_destroy_offloads_table(esw);
3399 create_offloads_err:
3400 esw_destroy_offloads_acl_tables(esw);
3401 create_acl_err:
3402 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
3403 create_indir_err:
3404 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
3405 return err;
3406 }
3407
esw_offloads_steering_cleanup(struct mlx5_eswitch * esw)3408 static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
3409 {
3410 esw_destroy_vport_rx_drop_rule(esw);
3411 esw_destroy_vport_rx_drop_group(esw);
3412 esw_destroy_vport_rx_group(esw);
3413 esw_destroy_offloads_fdb_tables(esw);
3414 esw_destroy_restore_table(esw);
3415 esw_destroy_offloads_table(esw);
3416 esw_destroy_offloads_acl_tables(esw);
3417 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
3418 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
3419 }
3420
3421 static void
esw_vfs_changed_event_handler(struct mlx5_eswitch * esw,const u32 * out)3422 esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
3423 {
3424 struct devlink *devlink;
3425 bool host_pf_disabled;
3426 u16 new_num_vfs;
3427
3428 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
3429 host_params_context.host_num_of_vfs);
3430 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
3431 host_params_context.host_pf_disabled);
3432
3433 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
3434 return;
3435
3436 devlink = priv_to_devlink(esw->dev);
3437 devl_lock(devlink);
3438 /* Number of VFs can only change from "0 to x" or "x to 0". */
3439 if (esw->esw_funcs.num_vfs > 0) {
3440 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
3441 } else {
3442 int err;
3443
3444 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
3445 MLX5_VPORT_UC_ADDR_CHANGE);
3446 if (err) {
3447 devl_unlock(devlink);
3448 return;
3449 }
3450 }
3451 esw->esw_funcs.num_vfs = new_num_vfs;
3452 devl_unlock(devlink);
3453 }
3454
esw_functions_changed_event_handler(struct work_struct * work)3455 static void esw_functions_changed_event_handler(struct work_struct *work)
3456 {
3457 struct mlx5_host_work *host_work;
3458 struct mlx5_eswitch *esw;
3459 const u32 *out;
3460
3461 host_work = container_of(work, struct mlx5_host_work, work);
3462 esw = host_work->esw;
3463
3464 out = mlx5_esw_query_functions(esw->dev);
3465 if (IS_ERR(out))
3466 goto out;
3467
3468 esw_vfs_changed_event_handler(esw, out);
3469 kvfree(out);
3470 out:
3471 kfree(host_work);
3472 }
3473
mlx5_esw_funcs_changed_handler(struct notifier_block * nb,unsigned long type,void * data)3474 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
3475 {
3476 struct mlx5_esw_functions *esw_funcs;
3477 struct mlx5_host_work *host_work;
3478 struct mlx5_eswitch *esw;
3479
3480 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
3481 if (!host_work)
3482 return NOTIFY_DONE;
3483
3484 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
3485 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
3486
3487 host_work->esw = esw;
3488
3489 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
3490 queue_work(esw->work_queue, &host_work->work);
3491
3492 return NOTIFY_OK;
3493 }
3494
mlx5_esw_host_number_init(struct mlx5_eswitch * esw)3495 static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
3496 {
3497 const u32 *query_host_out;
3498
3499 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3500 return 0;
3501
3502 query_host_out = mlx5_esw_query_functions(esw->dev);
3503 if (IS_ERR(query_host_out))
3504 return PTR_ERR(query_host_out);
3505
3506 /* Mark non local controller with non zero controller number. */
3507 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
3508 host_params_context.host_number);
3509 kvfree(query_host_out);
3510 return 0;
3511 }
3512
mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch * esw,u32 controller)3513 bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller)
3514 {
3515 /* Local controller is always valid */
3516 if (controller == 0)
3517 return true;
3518
3519 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3520 return false;
3521
3522 /* External host number starts with zero in device */
3523 return (controller == esw->offloads.host_number + 1);
3524 }
3525
esw_offloads_enable(struct mlx5_eswitch * esw)3526 int esw_offloads_enable(struct mlx5_eswitch *esw)
3527 {
3528 struct mapping_ctx *reg_c0_obj_pool;
3529 struct mlx5_vport *vport;
3530 unsigned long i;
3531 u64 mapping_id;
3532 int err;
3533
3534 mutex_init(&esw->offloads.termtbl_mutex);
3535 mlx5_rdma_enable_roce(esw->dev);
3536
3537 err = mlx5_esw_host_number_init(esw);
3538 if (err)
3539 goto err_metadata;
3540
3541 err = esw_offloads_metadata_init(esw);
3542 if (err)
3543 goto err_metadata;
3544
3545 err = esw_set_passing_vport_metadata(esw, true);
3546 if (err)
3547 goto err_vport_metadata;
3548
3549 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
3550
3551 reg_c0_obj_pool = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
3552 sizeof(struct mlx5_mapped_obj),
3553 ESW_REG_C0_USER_DATA_METADATA_MASK,
3554 true);
3555
3556 if (IS_ERR(reg_c0_obj_pool)) {
3557 err = PTR_ERR(reg_c0_obj_pool);
3558 goto err_pool;
3559 }
3560 esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool;
3561
3562 err = esw_offloads_steering_init(esw);
3563 if (err)
3564 goto err_steering_init;
3565
3566 /* Representor will control the vport link state */
3567 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
3568 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3569 if (mlx5_core_ec_sriov_enabled(esw->dev))
3570 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs)
3571 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3572
3573 /* Uplink vport rep must load first. */
3574 err = mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK);
3575 if (err)
3576 goto err_uplink;
3577
3578 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
3579 if (err)
3580 goto err_vports;
3581
3582 return 0;
3583
3584 err_vports:
3585 mlx5_esw_offloads_rep_unload(esw, MLX5_VPORT_UPLINK);
3586 err_uplink:
3587 esw_offloads_steering_cleanup(esw);
3588 err_steering_init:
3589 mapping_destroy(reg_c0_obj_pool);
3590 err_pool:
3591 esw_set_passing_vport_metadata(esw, false);
3592 err_vport_metadata:
3593 esw_offloads_metadata_uninit(esw);
3594 err_metadata:
3595 mlx5_rdma_disable_roce(esw->dev);
3596 mutex_destroy(&esw->offloads.termtbl_mutex);
3597 return err;
3598 }
3599
esw_offloads_stop(struct mlx5_eswitch * esw,struct netlink_ext_ack * extack)3600 static int esw_offloads_stop(struct mlx5_eswitch *esw,
3601 struct netlink_ext_ack *extack)
3602 {
3603 int err;
3604
3605 esw_mode_change(esw, MLX5_ESWITCH_LEGACY);
3606
3607 /* If changing from switchdev to legacy mode without sriov enabled,
3608 * no need to create legacy fdb.
3609 */
3610 if (!mlx5_core_is_pf(esw->dev) || !mlx5_sriov_is_enabled(esw->dev))
3611 return 0;
3612
3613 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_IGNORE_NUM_VFS);
3614 if (err)
3615 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
3616
3617 return err;
3618 }
3619
esw_offloads_disable(struct mlx5_eswitch * esw)3620 void esw_offloads_disable(struct mlx5_eswitch *esw)
3621 {
3622 mlx5_eswitch_disable_pf_vf_vports(esw);
3623 mlx5_esw_offloads_rep_unload(esw, MLX5_VPORT_UPLINK);
3624 esw_set_passing_vport_metadata(esw, false);
3625 esw_offloads_steering_cleanup(esw);
3626 mapping_destroy(esw->offloads.reg_c0_obj_pool);
3627 esw_offloads_metadata_uninit(esw);
3628 mlx5_rdma_disable_roce(esw->dev);
3629 mutex_destroy(&esw->offloads.termtbl_mutex);
3630 }
3631
esw_mode_from_devlink(u16 mode,u16 * mlx5_mode)3632 static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
3633 {
3634 switch (mode) {
3635 case DEVLINK_ESWITCH_MODE_LEGACY:
3636 *mlx5_mode = MLX5_ESWITCH_LEGACY;
3637 break;
3638 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
3639 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
3640 break;
3641 default:
3642 return -EINVAL;
3643 }
3644
3645 return 0;
3646 }
3647
esw_mode_to_devlink(u16 mlx5_mode,u16 * mode)3648 static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
3649 {
3650 switch (mlx5_mode) {
3651 case MLX5_ESWITCH_LEGACY:
3652 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
3653 break;
3654 case MLX5_ESWITCH_OFFLOADS:
3655 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
3656 break;
3657 default:
3658 return -EINVAL;
3659 }
3660
3661 return 0;
3662 }
3663
esw_inline_mode_from_devlink(u8 mode,u8 * mlx5_mode)3664 static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
3665 {
3666 switch (mode) {
3667 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
3668 *mlx5_mode = MLX5_INLINE_MODE_NONE;
3669 break;
3670 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
3671 *mlx5_mode = MLX5_INLINE_MODE_L2;
3672 break;
3673 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
3674 *mlx5_mode = MLX5_INLINE_MODE_IP;
3675 break;
3676 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
3677 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
3678 break;
3679 default:
3680 return -EINVAL;
3681 }
3682
3683 return 0;
3684 }
3685
esw_inline_mode_to_devlink(u8 mlx5_mode,u8 * mode)3686 static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
3687 {
3688 switch (mlx5_mode) {
3689 case MLX5_INLINE_MODE_NONE:
3690 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
3691 break;
3692 case MLX5_INLINE_MODE_L2:
3693 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
3694 break;
3695 case MLX5_INLINE_MODE_IP:
3696 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
3697 break;
3698 case MLX5_INLINE_MODE_TCP_UDP:
3699 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
3700 break;
3701 default:
3702 return -EINVAL;
3703 }
3704
3705 return 0;
3706 }
3707
mlx5_eswitch_block_mode(struct mlx5_core_dev * dev)3708 int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev)
3709 {
3710 struct mlx5_eswitch *esw = dev->priv.eswitch;
3711 int err;
3712
3713 if (!mlx5_esw_allowed(esw))
3714 return 0;
3715
3716 /* Take TC into account */
3717 err = mlx5_esw_try_lock(esw);
3718 if (err < 0)
3719 return err;
3720
3721 esw->offloads.num_block_mode++;
3722 mlx5_esw_unlock(esw);
3723 return 0;
3724 }
3725
mlx5_eswitch_unblock_mode(struct mlx5_core_dev * dev)3726 void mlx5_eswitch_unblock_mode(struct mlx5_core_dev *dev)
3727 {
3728 struct mlx5_eswitch *esw = dev->priv.eswitch;
3729
3730 if (!mlx5_esw_allowed(esw))
3731 return;
3732
3733 down_write(&esw->mode_lock);
3734 esw->offloads.num_block_mode--;
3735 up_write(&esw->mode_lock);
3736 }
3737
mlx5_devlink_eswitch_mode_set(struct devlink * devlink,u16 mode,struct netlink_ext_ack * extack)3738 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
3739 struct netlink_ext_ack *extack)
3740 {
3741 u16 cur_mlx5_mode, mlx5_mode = 0;
3742 struct mlx5_eswitch *esw;
3743 int err = 0;
3744
3745 esw = mlx5_devlink_eswitch_get(devlink);
3746 if (IS_ERR(esw))
3747 return PTR_ERR(esw);
3748
3749 if (esw_mode_from_devlink(mode, &mlx5_mode))
3750 return -EINVAL;
3751
3752 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV && mlx5_get_sd(esw->dev)) {
3753 NL_SET_ERR_MSG_MOD(extack,
3754 "Can't change E-Switch mode to switchdev when multi-PF netdev (Socket Direct) is configured.");
3755 return -EPERM;
3756 }
3757
3758 mlx5_lag_disable_change(esw->dev);
3759 err = mlx5_esw_try_lock(esw);
3760 if (err < 0) {
3761 NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy");
3762 goto enable_lag;
3763 }
3764 cur_mlx5_mode = err;
3765 err = 0;
3766
3767 if (cur_mlx5_mode == mlx5_mode)
3768 goto unlock;
3769
3770 if (esw->offloads.num_block_mode) {
3771 NL_SET_ERR_MSG_MOD(extack,
3772 "Can't change eswitch mode when IPsec SA and/or policies are configured");
3773 err = -EOPNOTSUPP;
3774 goto unlock;
3775 }
3776
3777 esw->eswitch_operation_in_progress = true;
3778 up_write(&esw->mode_lock);
3779
3780 if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
3781 esw->dev->priv.flags |= MLX5_PRIV_FLAGS_SWITCH_LEGACY;
3782 mlx5_eswitch_disable_locked(esw);
3783 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV) {
3784 if (mlx5_devlink_trap_get_num_active(esw->dev)) {
3785 NL_SET_ERR_MSG_MOD(extack,
3786 "Can't change mode while devlink traps are active");
3787 err = -EOPNOTSUPP;
3788 goto skip;
3789 }
3790 err = esw_offloads_start(esw, extack);
3791 } else if (mode == DEVLINK_ESWITCH_MODE_LEGACY) {
3792 err = esw_offloads_stop(esw, extack);
3793 } else {
3794 err = -EINVAL;
3795 }
3796
3797 skip:
3798 down_write(&esw->mode_lock);
3799 esw->eswitch_operation_in_progress = false;
3800 unlock:
3801 mlx5_esw_unlock(esw);
3802 enable_lag:
3803 mlx5_lag_enable_change(esw->dev);
3804 return err;
3805 }
3806
mlx5_devlink_eswitch_mode_get(struct devlink * devlink,u16 * mode)3807 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
3808 {
3809 struct mlx5_eswitch *esw;
3810
3811 esw = mlx5_devlink_eswitch_get(devlink);
3812 if (IS_ERR(esw))
3813 return PTR_ERR(esw);
3814
3815 return esw_mode_to_devlink(esw->mode, mode);
3816 }
3817
mlx5_esw_vports_inline_set(struct mlx5_eswitch * esw,u8 mlx5_mode,struct netlink_ext_ack * extack)3818 static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode,
3819 struct netlink_ext_ack *extack)
3820 {
3821 struct mlx5_core_dev *dev = esw->dev;
3822 struct mlx5_vport *vport;
3823 u16 err_vport_num = 0;
3824 unsigned long i;
3825 int err = 0;
3826
3827 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3828 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3829 if (err) {
3830 err_vport_num = vport->vport;
3831 NL_SET_ERR_MSG_MOD(extack,
3832 "Failed to set min inline on vport");
3833 goto revert_inline_mode;
3834 }
3835 }
3836 if (mlx5_core_ec_sriov_enabled(esw->dev)) {
3837 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs) {
3838 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3839 if (err) {
3840 err_vport_num = vport->vport;
3841 NL_SET_ERR_MSG_MOD(extack,
3842 "Failed to set min inline on vport");
3843 goto revert_ec_vf_inline_mode;
3844 }
3845 }
3846 }
3847 return 0;
3848
3849 revert_ec_vf_inline_mode:
3850 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs) {
3851 if (vport->vport == err_vport_num)
3852 break;
3853 mlx5_modify_nic_vport_min_inline(dev,
3854 vport->vport,
3855 esw->offloads.inline_mode);
3856 }
3857 revert_inline_mode:
3858 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3859 if (vport->vport == err_vport_num)
3860 break;
3861 mlx5_modify_nic_vport_min_inline(dev,
3862 vport->vport,
3863 esw->offloads.inline_mode);
3864 }
3865 return err;
3866 }
3867
mlx5_devlink_eswitch_inline_mode_set(struct devlink * devlink,u8 mode,struct netlink_ext_ack * extack)3868 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
3869 struct netlink_ext_ack *extack)
3870 {
3871 struct mlx5_core_dev *dev = devlink_priv(devlink);
3872 struct mlx5_eswitch *esw;
3873 u8 mlx5_mode;
3874 int err;
3875
3876 esw = mlx5_devlink_eswitch_get(devlink);
3877 if (IS_ERR(esw))
3878 return PTR_ERR(esw);
3879
3880 down_write(&esw->mode_lock);
3881
3882 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
3883 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
3884 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE) {
3885 err = 0;
3886 goto out;
3887 }
3888
3889 fallthrough;
3890 case MLX5_CAP_INLINE_MODE_L2:
3891 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
3892 err = -EOPNOTSUPP;
3893 goto out;
3894 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3895 break;
3896 }
3897
3898 if (atomic64_read(&esw->offloads.num_flows) > 0) {
3899 NL_SET_ERR_MSG_MOD(extack,
3900 "Can't set inline mode when flows are configured");
3901 err = -EOPNOTSUPP;
3902 goto out;
3903 }
3904
3905 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
3906 if (err)
3907 goto out;
3908
3909 esw->eswitch_operation_in_progress = true;
3910 up_write(&esw->mode_lock);
3911
3912 err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack);
3913 if (!err)
3914 esw->offloads.inline_mode = mlx5_mode;
3915
3916 down_write(&esw->mode_lock);
3917 esw->eswitch_operation_in_progress = false;
3918 up_write(&esw->mode_lock);
3919 return 0;
3920
3921 out:
3922 up_write(&esw->mode_lock);
3923 return err;
3924 }
3925
mlx5_devlink_eswitch_inline_mode_get(struct devlink * devlink,u8 * mode)3926 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
3927 {
3928 struct mlx5_eswitch *esw;
3929
3930 esw = mlx5_devlink_eswitch_get(devlink);
3931 if (IS_ERR(esw))
3932 return PTR_ERR(esw);
3933
3934 return esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
3935 }
3936
mlx5_eswitch_block_encap(struct mlx5_core_dev * dev)3937 bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev)
3938 {
3939 struct mlx5_eswitch *esw = dev->priv.eswitch;
3940
3941 if (!mlx5_esw_allowed(esw))
3942 return true;
3943
3944 down_write(&esw->mode_lock);
3945 if (esw->mode != MLX5_ESWITCH_LEGACY &&
3946 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
3947 up_write(&esw->mode_lock);
3948 return false;
3949 }
3950
3951 esw->offloads.num_block_encap++;
3952 up_write(&esw->mode_lock);
3953 return true;
3954 }
3955
mlx5_eswitch_unblock_encap(struct mlx5_core_dev * dev)3956 void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev)
3957 {
3958 struct mlx5_eswitch *esw = dev->priv.eswitch;
3959
3960 if (!mlx5_esw_allowed(esw))
3961 return;
3962
3963 down_write(&esw->mode_lock);
3964 esw->offloads.num_block_encap--;
3965 up_write(&esw->mode_lock);
3966 }
3967
mlx5_devlink_eswitch_encap_mode_set(struct devlink * devlink,enum devlink_eswitch_encap_mode encap,struct netlink_ext_ack * extack)3968 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
3969 enum devlink_eswitch_encap_mode encap,
3970 struct netlink_ext_ack *extack)
3971 {
3972 struct mlx5_core_dev *dev = devlink_priv(devlink);
3973 struct mlx5_eswitch *esw;
3974 int err = 0;
3975
3976 esw = mlx5_devlink_eswitch_get(devlink);
3977 if (IS_ERR(esw))
3978 return PTR_ERR(esw);
3979
3980 down_write(&esw->mode_lock);
3981
3982 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
3983 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
3984 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
3985 err = -EOPNOTSUPP;
3986 goto unlock;
3987 }
3988
3989 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
3990 err = -EOPNOTSUPP;
3991 goto unlock;
3992 }
3993
3994 if (esw->mode == MLX5_ESWITCH_LEGACY) {
3995 esw->offloads.encap = encap;
3996 goto unlock;
3997 }
3998
3999 if (esw->offloads.encap == encap)
4000 goto unlock;
4001
4002 if (atomic64_read(&esw->offloads.num_flows) > 0) {
4003 NL_SET_ERR_MSG_MOD(extack,
4004 "Can't set encapsulation when flows are configured");
4005 err = -EOPNOTSUPP;
4006 goto unlock;
4007 }
4008
4009 if (esw->offloads.num_block_encap) {
4010 NL_SET_ERR_MSG_MOD(extack,
4011 "Can't set encapsulation when IPsec SA and/or policies are configured");
4012 err = -EOPNOTSUPP;
4013 goto unlock;
4014 }
4015
4016 esw->eswitch_operation_in_progress = true;
4017 up_write(&esw->mode_lock);
4018
4019 esw_destroy_offloads_fdb_tables(esw);
4020
4021 esw->offloads.encap = encap;
4022
4023 err = esw_create_offloads_fdb_tables(esw);
4024
4025 if (err) {
4026 NL_SET_ERR_MSG_MOD(extack,
4027 "Failed re-creating fast FDB table");
4028 esw->offloads.encap = !encap;
4029 (void)esw_create_offloads_fdb_tables(esw);
4030 }
4031
4032 down_write(&esw->mode_lock);
4033 esw->eswitch_operation_in_progress = false;
4034
4035 unlock:
4036 up_write(&esw->mode_lock);
4037 return err;
4038 }
4039
mlx5_devlink_eswitch_encap_mode_get(struct devlink * devlink,enum devlink_eswitch_encap_mode * encap)4040 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
4041 enum devlink_eswitch_encap_mode *encap)
4042 {
4043 struct mlx5_eswitch *esw;
4044
4045 esw = mlx5_devlink_eswitch_get(devlink);
4046 if (IS_ERR(esw))
4047 return PTR_ERR(esw);
4048
4049 *encap = esw->offloads.encap;
4050 return 0;
4051 }
4052
4053 static bool
mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch * esw,u16 vport_num)4054 mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
4055 {
4056 /* Currently, only ECPF based device has representor for host PF. */
4057 if (vport_num == MLX5_VPORT_PF &&
4058 !mlx5_core_is_ecpf_esw_manager(esw->dev))
4059 return false;
4060
4061 if (vport_num == MLX5_VPORT_ECPF &&
4062 !mlx5_ecpf_vport_exists(esw->dev))
4063 return false;
4064
4065 return true;
4066 }
4067
mlx5_eswitch_register_vport_reps(struct mlx5_eswitch * esw,const struct mlx5_eswitch_rep_ops * ops,u8 rep_type)4068 void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
4069 const struct mlx5_eswitch_rep_ops *ops,
4070 u8 rep_type)
4071 {
4072 struct mlx5_eswitch_rep_data *rep_data;
4073 struct mlx5_eswitch_rep *rep;
4074 unsigned long i;
4075
4076 esw->offloads.rep_ops[rep_type] = ops;
4077 mlx5_esw_for_each_rep(esw, i, rep) {
4078 if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) {
4079 rep->esw = esw;
4080 rep_data = &rep->rep_data[rep_type];
4081 atomic_set(&rep_data->state, REP_REGISTERED);
4082 }
4083 }
4084 }
4085 EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
4086
mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch * esw,u8 rep_type)4087 void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
4088 {
4089 struct mlx5_eswitch_rep *rep;
4090 unsigned long i;
4091
4092 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
4093 __unload_reps_all_vport(esw, rep_type);
4094
4095 mlx5_esw_for_each_rep(esw, i, rep)
4096 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
4097 }
4098 EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
4099
mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch * esw,u8 rep_type)4100 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
4101 {
4102 struct mlx5_eswitch_rep *rep;
4103
4104 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
4105 return rep->rep_data[rep_type].priv;
4106 }
4107
mlx5_eswitch_get_proto_dev(struct mlx5_eswitch * esw,u16 vport,u8 rep_type)4108 void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
4109 u16 vport,
4110 u8 rep_type)
4111 {
4112 struct mlx5_eswitch_rep *rep;
4113
4114 rep = mlx5_eswitch_get_rep(esw, vport);
4115
4116 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
4117 esw->offloads.rep_ops[rep_type]->get_proto_dev)
4118 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
4119 return NULL;
4120 }
4121 EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
4122
mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch * esw,u8 rep_type)4123 void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
4124 {
4125 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
4126 }
4127 EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
4128
mlx5_eswitch_vport_rep(struct mlx5_eswitch * esw,u16 vport)4129 struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
4130 u16 vport)
4131 {
4132 return mlx5_eswitch_get_rep(esw, vport);
4133 }
4134 EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
4135
mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch * esw)4136 bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
4137 {
4138 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
4139 }
4140 EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
4141
mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch * esw)4142 bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
4143 {
4144 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
4145 }
4146 EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
4147
mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch * esw,u16 vport_num)4148 u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
4149 u16 vport_num)
4150 {
4151 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
4152
4153 if (WARN_ON_ONCE(IS_ERR(vport)))
4154 return 0;
4155
4156 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
4157 }
4158 EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
4159
mlx5_esw_query_vport_vhca_id(struct mlx5_eswitch * esw,u16 vport_num,u16 * vhca_id)4160 static int mlx5_esw_query_vport_vhca_id(struct mlx5_eswitch *esw, u16 vport_num, u16 *vhca_id)
4161 {
4162 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4163 void *query_ctx;
4164 void *hca_caps;
4165 int err;
4166
4167 *vhca_id = 0;
4168
4169 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4170 if (!query_ctx)
4171 return -ENOMEM;
4172
4173 err = mlx5_vport_get_other_func_general_cap(esw->dev, vport_num, query_ctx);
4174 if (err)
4175 goto out_free;
4176
4177 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4178 *vhca_id = MLX5_GET(cmd_hca_cap, hca_caps, vhca_id);
4179
4180 out_free:
4181 kfree(query_ctx);
4182 return err;
4183 }
4184
mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch * esw,u16 vport_num)4185 int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num)
4186 {
4187 u16 *old_entry, *vhca_map_entry, vhca_id;
4188 int err;
4189
4190 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
4191 if (err) {
4192 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%u,err=%d)\n",
4193 vport_num, err);
4194 return err;
4195 }
4196
4197 vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL);
4198 if (!vhca_map_entry)
4199 return -ENOMEM;
4200
4201 *vhca_map_entry = vport_num;
4202 old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL);
4203 if (xa_is_err(old_entry)) {
4204 kfree(vhca_map_entry);
4205 return xa_err(old_entry);
4206 }
4207 kfree(old_entry);
4208 return 0;
4209 }
4210
mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch * esw,u16 vport_num)4211 void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num)
4212 {
4213 u16 *vhca_map_entry, vhca_id;
4214 int err;
4215
4216 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
4217 if (err)
4218 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%hu,err=%d)\n",
4219 vport_num, err);
4220
4221 vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vhca_id);
4222 kfree(vhca_map_entry);
4223 }
4224
mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch * esw,u16 vhca_id,u16 * vport_num)4225 int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num)
4226 {
4227 u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id);
4228
4229 if (!res)
4230 return -ENOENT;
4231
4232 *vport_num = *res;
4233 return 0;
4234 }
4235
mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch * esw,u16 vport_num)4236 u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
4237 u16 vport_num)
4238 {
4239 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
4240
4241 if (WARN_ON_ONCE(IS_ERR(vport)))
4242 return 0;
4243
4244 return vport->metadata;
4245 }
4246 EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set);
4247
mlx5_devlink_port_fn_hw_addr_get(struct devlink_port * port,u8 * hw_addr,int * hw_addr_len,struct netlink_ext_ack * extack)4248 int mlx5_devlink_port_fn_hw_addr_get(struct devlink_port *port,
4249 u8 *hw_addr, int *hw_addr_len,
4250 struct netlink_ext_ack *extack)
4251 {
4252 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4253 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4254
4255 mutex_lock(&esw->state_lock);
4256 ether_addr_copy(hw_addr, vport->info.mac);
4257 *hw_addr_len = ETH_ALEN;
4258 mutex_unlock(&esw->state_lock);
4259 return 0;
4260 }
4261
mlx5_devlink_port_fn_hw_addr_set(struct devlink_port * port,const u8 * hw_addr,int hw_addr_len,struct netlink_ext_ack * extack)4262 int mlx5_devlink_port_fn_hw_addr_set(struct devlink_port *port,
4263 const u8 *hw_addr, int hw_addr_len,
4264 struct netlink_ext_ack *extack)
4265 {
4266 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4267 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4268
4269 return mlx5_eswitch_set_vport_mac(esw, vport->vport, hw_addr);
4270 }
4271
mlx5_devlink_port_fn_migratable_get(struct devlink_port * port,bool * is_enabled,struct netlink_ext_ack * extack)4272 int mlx5_devlink_port_fn_migratable_get(struct devlink_port *port, bool *is_enabled,
4273 struct netlink_ext_ack *extack)
4274 {
4275 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4276 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4277
4278 if (!MLX5_CAP_GEN(esw->dev, migration)) {
4279 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support migration");
4280 return -EOPNOTSUPP;
4281 }
4282
4283 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4284 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support VHCA management");
4285 return -EOPNOTSUPP;
4286 }
4287
4288 mutex_lock(&esw->state_lock);
4289 *is_enabled = vport->info.mig_enabled;
4290 mutex_unlock(&esw->state_lock);
4291 return 0;
4292 }
4293
mlx5_devlink_port_fn_migratable_set(struct devlink_port * port,bool enable,struct netlink_ext_ack * extack)4294 int mlx5_devlink_port_fn_migratable_set(struct devlink_port *port, bool enable,
4295 struct netlink_ext_ack *extack)
4296 {
4297 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4298 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4299 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4300 void *query_ctx;
4301 void *hca_caps;
4302 int err;
4303
4304 if (!MLX5_CAP_GEN(esw->dev, migration)) {
4305 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support migration");
4306 return -EOPNOTSUPP;
4307 }
4308
4309 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4310 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support VHCA management");
4311 return -EOPNOTSUPP;
4312 }
4313
4314 mutex_lock(&esw->state_lock);
4315
4316 if (vport->info.mig_enabled == enable) {
4317 err = 0;
4318 goto out;
4319 }
4320
4321 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4322 if (!query_ctx) {
4323 err = -ENOMEM;
4324 goto out;
4325 }
4326
4327 err = mlx5_vport_get_other_func_cap(esw->dev, vport->vport, query_ctx,
4328 MLX5_CAP_GENERAL_2);
4329 if (err) {
4330 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4331 goto out_free;
4332 }
4333
4334 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4335 MLX5_SET(cmd_hca_cap_2, hca_caps, migratable, enable);
4336
4337 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport->vport,
4338 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2);
4339 if (err) {
4340 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA migratable cap");
4341 goto out_free;
4342 }
4343
4344 vport->info.mig_enabled = enable;
4345
4346 out_free:
4347 kfree(query_ctx);
4348 out:
4349 mutex_unlock(&esw->state_lock);
4350 return err;
4351 }
4352
mlx5_devlink_port_fn_roce_get(struct devlink_port * port,bool * is_enabled,struct netlink_ext_ack * extack)4353 int mlx5_devlink_port_fn_roce_get(struct devlink_port *port, bool *is_enabled,
4354 struct netlink_ext_ack *extack)
4355 {
4356 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4357 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4358
4359 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4360 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support VHCA management");
4361 return -EOPNOTSUPP;
4362 }
4363
4364 mutex_lock(&esw->state_lock);
4365 *is_enabled = vport->info.roce_enabled;
4366 mutex_unlock(&esw->state_lock);
4367 return 0;
4368 }
4369
mlx5_devlink_port_fn_roce_set(struct devlink_port * port,bool enable,struct netlink_ext_ack * extack)4370 int mlx5_devlink_port_fn_roce_set(struct devlink_port *port, bool enable,
4371 struct netlink_ext_ack *extack)
4372 {
4373 struct mlx5_eswitch *esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4374 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4375 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4376 u16 vport_num = vport->vport;
4377 void *query_ctx;
4378 void *hca_caps;
4379 int err;
4380
4381 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4382 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support VHCA management");
4383 return -EOPNOTSUPP;
4384 }
4385
4386 mutex_lock(&esw->state_lock);
4387
4388 if (vport->info.roce_enabled == enable) {
4389 err = 0;
4390 goto out;
4391 }
4392
4393 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4394 if (!query_ctx) {
4395 err = -ENOMEM;
4396 goto out;
4397 }
4398
4399 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx,
4400 MLX5_CAP_GENERAL);
4401 if (err) {
4402 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4403 goto out_free;
4404 }
4405
4406 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4407 MLX5_SET(cmd_hca_cap, hca_caps, roce, enable);
4408
4409 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport_num,
4410 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
4411 if (err) {
4412 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA roce cap");
4413 goto out_free;
4414 }
4415
4416 vport->info.roce_enabled = enable;
4417
4418 out_free:
4419 kfree(query_ctx);
4420 out:
4421 mutex_unlock(&esw->state_lock);
4422 return err;
4423 }
4424
4425 int
mlx5_eswitch_restore_ipsec_rule(struct mlx5_eswitch * esw,struct mlx5_flow_handle * rule,struct mlx5_esw_flow_attr * esw_attr,int attr_idx)4426 mlx5_eswitch_restore_ipsec_rule(struct mlx5_eswitch *esw, struct mlx5_flow_handle *rule,
4427 struct mlx5_esw_flow_attr *esw_attr, int attr_idx)
4428 {
4429 struct mlx5_flow_destination new_dest = {};
4430 struct mlx5_flow_destination old_dest = {};
4431
4432 if (!esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, attr_idx))
4433 return 0;
4434
4435 esw_setup_dest_fwd_ipsec(&old_dest, NULL, esw, esw_attr, attr_idx, 0, false);
4436 esw_setup_dest_fwd_vport(&new_dest, NULL, esw, esw_attr, attr_idx, 0, false);
4437
4438 return mlx5_modify_rule_destination(rule, &new_dest, &old_dest);
4439 }
4440
4441 #ifdef CONFIG_XFRM_OFFLOAD
mlx5_devlink_port_fn_ipsec_crypto_get(struct devlink_port * port,bool * is_enabled,struct netlink_ext_ack * extack)4442 int mlx5_devlink_port_fn_ipsec_crypto_get(struct devlink_port *port, bool *is_enabled,
4443 struct netlink_ext_ack *extack)
4444 {
4445 struct mlx5_eswitch *esw;
4446 struct mlx5_vport *vport;
4447 int err = 0;
4448
4449 esw = mlx5_devlink_eswitch_get(port->devlink);
4450 if (IS_ERR(esw))
4451 return PTR_ERR(esw);
4452
4453 if (!mlx5_esw_ipsec_vf_offload_supported(esw->dev)) {
4454 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support IPSec crypto");
4455 return -EOPNOTSUPP;
4456 }
4457
4458 vport = mlx5_devlink_port_vport_get(port);
4459
4460 mutex_lock(&esw->state_lock);
4461 if (!vport->enabled) {
4462 err = -EOPNOTSUPP;
4463 goto unlock;
4464 }
4465
4466 *is_enabled = vport->info.ipsec_crypto_enabled;
4467 unlock:
4468 mutex_unlock(&esw->state_lock);
4469 return err;
4470 }
4471
mlx5_devlink_port_fn_ipsec_crypto_set(struct devlink_port * port,bool enable,struct netlink_ext_ack * extack)4472 int mlx5_devlink_port_fn_ipsec_crypto_set(struct devlink_port *port, bool enable,
4473 struct netlink_ext_ack *extack)
4474 {
4475 struct mlx5_eswitch *esw;
4476 struct mlx5_vport *vport;
4477 u16 vport_num;
4478 int err;
4479
4480 esw = mlx5_devlink_eswitch_get(port->devlink);
4481 if (IS_ERR(esw))
4482 return PTR_ERR(esw);
4483
4484 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4485 err = mlx5_esw_ipsec_vf_crypto_offload_supported(esw->dev, vport_num);
4486 if (err) {
4487 NL_SET_ERR_MSG_MOD(extack,
4488 "Device doesn't support IPsec crypto");
4489 return err;
4490 }
4491
4492 vport = mlx5_devlink_port_vport_get(port);
4493
4494 mutex_lock(&esw->state_lock);
4495 if (!vport->enabled) {
4496 err = -EOPNOTSUPP;
4497 NL_SET_ERR_MSG_MOD(extack, "Eswitch vport is disabled");
4498 goto unlock;
4499 }
4500
4501 if (vport->info.ipsec_crypto_enabled == enable)
4502 goto unlock;
4503
4504 if (!esw->enabled_ipsec_vf_count && esw->dev->num_ipsec_offloads) {
4505 err = -EBUSY;
4506 goto unlock;
4507 }
4508
4509 err = mlx5_esw_ipsec_vf_crypto_offload_set(esw, vport, enable);
4510 if (err) {
4511 NL_SET_ERR_MSG_MOD(extack, "Failed to set IPsec crypto");
4512 goto unlock;
4513 }
4514
4515 vport->info.ipsec_crypto_enabled = enable;
4516 if (enable)
4517 esw->enabled_ipsec_vf_count++;
4518 else
4519 esw->enabled_ipsec_vf_count--;
4520 unlock:
4521 mutex_unlock(&esw->state_lock);
4522 return err;
4523 }
4524
mlx5_devlink_port_fn_ipsec_packet_get(struct devlink_port * port,bool * is_enabled,struct netlink_ext_ack * extack)4525 int mlx5_devlink_port_fn_ipsec_packet_get(struct devlink_port *port, bool *is_enabled,
4526 struct netlink_ext_ack *extack)
4527 {
4528 struct mlx5_eswitch *esw;
4529 struct mlx5_vport *vport;
4530 int err = 0;
4531
4532 esw = mlx5_devlink_eswitch_get(port->devlink);
4533 if (IS_ERR(esw))
4534 return PTR_ERR(esw);
4535
4536 if (!mlx5_esw_ipsec_vf_offload_supported(esw->dev)) {
4537 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support IPsec packet");
4538 return -EOPNOTSUPP;
4539 }
4540
4541 vport = mlx5_devlink_port_vport_get(port);
4542
4543 mutex_lock(&esw->state_lock);
4544 if (!vport->enabled) {
4545 err = -EOPNOTSUPP;
4546 goto unlock;
4547 }
4548
4549 *is_enabled = vport->info.ipsec_packet_enabled;
4550 unlock:
4551 mutex_unlock(&esw->state_lock);
4552 return err;
4553 }
4554
mlx5_devlink_port_fn_ipsec_packet_set(struct devlink_port * port,bool enable,struct netlink_ext_ack * extack)4555 int mlx5_devlink_port_fn_ipsec_packet_set(struct devlink_port *port,
4556 bool enable,
4557 struct netlink_ext_ack *extack)
4558 {
4559 struct mlx5_eswitch *esw;
4560 struct mlx5_vport *vport;
4561 u16 vport_num;
4562 int err;
4563
4564 esw = mlx5_devlink_eswitch_get(port->devlink);
4565 if (IS_ERR(esw))
4566 return PTR_ERR(esw);
4567
4568 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4569 err = mlx5_esw_ipsec_vf_packet_offload_supported(esw->dev, vport_num);
4570 if (err) {
4571 NL_SET_ERR_MSG_MOD(extack,
4572 "Device doesn't support IPsec packet mode");
4573 return err;
4574 }
4575
4576 vport = mlx5_devlink_port_vport_get(port);
4577 mutex_lock(&esw->state_lock);
4578 if (!vport->enabled) {
4579 err = -EOPNOTSUPP;
4580 NL_SET_ERR_MSG_MOD(extack, "Eswitch vport is disabled");
4581 goto unlock;
4582 }
4583
4584 if (vport->info.ipsec_packet_enabled == enable)
4585 goto unlock;
4586
4587 if (!esw->enabled_ipsec_vf_count && esw->dev->num_ipsec_offloads) {
4588 err = -EBUSY;
4589 goto unlock;
4590 }
4591
4592 err = mlx5_esw_ipsec_vf_packet_offload_set(esw, vport, enable);
4593 if (err) {
4594 NL_SET_ERR_MSG_MOD(extack,
4595 "Failed to set IPsec packet mode");
4596 goto unlock;
4597 }
4598
4599 vport->info.ipsec_packet_enabled = enable;
4600 if (enable)
4601 esw->enabled_ipsec_vf_count++;
4602 else
4603 esw->enabled_ipsec_vf_count--;
4604 unlock:
4605 mutex_unlock(&esw->state_lock);
4606 return err;
4607 }
4608 #endif /* CONFIG_XFRM_OFFLOAD */
4609
4610 int
mlx5_devlink_port_fn_max_io_eqs_get(struct devlink_port * port,u32 * max_io_eqs,struct netlink_ext_ack * extack)4611 mlx5_devlink_port_fn_max_io_eqs_get(struct devlink_port *port, u32 *max_io_eqs,
4612 struct netlink_ext_ack *extack)
4613 {
4614 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4615 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4616 u16 vport_num = vport->vport;
4617 struct mlx5_eswitch *esw;
4618 void *query_ctx;
4619 void *hca_caps;
4620 u32 max_eqs;
4621 int err;
4622
4623 esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4624 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4625 NL_SET_ERR_MSG_MOD(extack,
4626 "Device doesn't support VHCA management");
4627 return -EOPNOTSUPP;
4628 }
4629
4630 if (!MLX5_CAP_GEN_2(esw->dev, max_num_eqs_24b)) {
4631 NL_SET_ERR_MSG_MOD(extack,
4632 "Device doesn't support getting the max number of EQs");
4633 return -EOPNOTSUPP;
4634 }
4635
4636 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4637 if (!query_ctx)
4638 return -ENOMEM;
4639
4640 mutex_lock(&esw->state_lock);
4641 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx,
4642 MLX5_CAP_GENERAL_2);
4643 if (err) {
4644 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4645 goto out;
4646 }
4647
4648 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4649 max_eqs = MLX5_GET(cmd_hca_cap_2, hca_caps, max_num_eqs_24b);
4650 if (max_eqs < MLX5_ESW_MAX_CTRL_EQS)
4651 *max_io_eqs = 0;
4652 else
4653 *max_io_eqs = max_eqs - MLX5_ESW_MAX_CTRL_EQS;
4654 out:
4655 mutex_unlock(&esw->state_lock);
4656 kfree(query_ctx);
4657 return err;
4658 }
4659
4660 int
mlx5_devlink_port_fn_max_io_eqs_set(struct devlink_port * port,u32 max_io_eqs,struct netlink_ext_ack * extack)4661 mlx5_devlink_port_fn_max_io_eqs_set(struct devlink_port *port, u32 max_io_eqs,
4662 struct netlink_ext_ack *extack)
4663 {
4664 struct mlx5_vport *vport = mlx5_devlink_port_vport_get(port);
4665 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4666 u16 vport_num = vport->vport;
4667 struct mlx5_eswitch *esw;
4668 void *query_ctx;
4669 void *hca_caps;
4670 u16 max_eqs;
4671 int err;
4672
4673 esw = mlx5_devlink_eswitch_nocheck_get(port->devlink);
4674 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) {
4675 NL_SET_ERR_MSG_MOD(extack,
4676 "Device doesn't support VHCA management");
4677 return -EOPNOTSUPP;
4678 }
4679
4680 if (!MLX5_CAP_GEN_2(esw->dev, max_num_eqs_24b)) {
4681 NL_SET_ERR_MSG_MOD(extack,
4682 "Device doesn't support changing the max number of EQs");
4683 return -EOPNOTSUPP;
4684 }
4685
4686 if (check_add_overflow(max_io_eqs, MLX5_ESW_MAX_CTRL_EQS, &max_eqs)) {
4687 NL_SET_ERR_MSG_MOD(extack, "Supplied value out of range");
4688 return -EINVAL;
4689 }
4690
4691 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4692 if (!query_ctx)
4693 return -ENOMEM;
4694
4695 mutex_lock(&esw->state_lock);
4696 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx,
4697 MLX5_CAP_GENERAL_2);
4698 if (err) {
4699 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4700 goto out;
4701 }
4702
4703 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4704 MLX5_SET(cmd_hca_cap_2, hca_caps, max_num_eqs_24b, max_eqs);
4705
4706 if (mlx5_esw_is_sf_vport(esw, vport_num))
4707 MLX5_SET(cmd_hca_cap_2, hca_caps, sf_eq_usage, 1);
4708
4709 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport_num,
4710 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2);
4711 if (err)
4712 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA caps");
4713 vport->max_eqs_set = true;
4714 out:
4715 mutex_unlock(&esw->state_lock);
4716 kfree(query_ctx);
4717 return err;
4718 }
4719
4720 int
mlx5_devlink_port_fn_max_io_eqs_set_sf_default(struct devlink_port * port,struct netlink_ext_ack * extack)4721 mlx5_devlink_port_fn_max_io_eqs_set_sf_default(struct devlink_port *port,
4722 struct netlink_ext_ack *extack)
4723 {
4724 return mlx5_devlink_port_fn_max_io_eqs_set(port,
4725 MLX5_ESW_DEFAULT_SF_COMP_EQS,
4726 extack);
4727 }
4728