1 /*
2 * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef __MLX5_ESWITCH_H__
34 #define __MLX5_ESWITCH_H__
35
36 #include <linux/if_ether.h>
37 #include <linux/if_link.h>
38 #include <linux/atomic.h>
39 #include <linux/xarray.h>
40 #include <net/devlink.h>
41 #include <linux/mlx5/device.h>
42 #include <linux/mlx5/eswitch.h>
43 #include <linux/mlx5/vport.h>
44 #include <linux/mlx5/fs.h>
45 #include "lib/mpfs.h"
46 #include "lib/fs_chains.h"
47 #include "sf/sf.h"
48 #include "en/tc_ct.h"
49 #include "en/tc/sample.h"
50
51 enum mlx5_mapped_obj_type {
52 MLX5_MAPPED_OBJ_CHAIN,
53 MLX5_MAPPED_OBJ_SAMPLE,
54 MLX5_MAPPED_OBJ_INT_PORT_METADATA,
55 MLX5_MAPPED_OBJ_ACT_MISS,
56 };
57
58 struct mlx5_mapped_obj {
59 enum mlx5_mapped_obj_type type;
60 union {
61 u32 chain;
62 u64 act_miss_cookie;
63 struct {
64 u32 group_id;
65 u32 rate;
66 u32 trunc_size;
67 u32 tunnel_id;
68 } sample;
69 u32 int_port_metadata;
70 };
71 };
72
73 #ifdef CONFIG_MLX5_ESWITCH
74
75 #define ESW_OFFLOADS_DEFAULT_NUM_GROUPS 15
76
77 #define MLX5_MAX_UC_PER_VPORT(dev) \
78 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
79
80 #define MLX5_MAX_MC_PER_VPORT(dev) \
81 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
82
83 #define mlx5_esw_has_fwd_fdb(dev) \
84 MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)
85
86 #define esw_chains(esw) \
87 ((esw)->fdb_table.offloads.esw_chains_priv)
88
89 enum {
90 MAPPING_TYPE_CHAIN,
91 MAPPING_TYPE_TUNNEL,
92 MAPPING_TYPE_TUNNEL_ENC_OPTS,
93 MAPPING_TYPE_LABELS,
94 MAPPING_TYPE_ZONE,
95 MAPPING_TYPE_INT_PORT,
96 };
97
98 struct vport_ingress {
99 struct mlx5_flow_table *acl;
100 struct mlx5_flow_handle *allow_rule;
101 struct {
102 struct mlx5_flow_group *allow_spoofchk_only_grp;
103 struct mlx5_flow_group *allow_untagged_spoofchk_grp;
104 struct mlx5_flow_group *allow_untagged_only_grp;
105 struct mlx5_flow_group *drop_grp;
106 struct mlx5_flow_handle *drop_rule;
107 struct mlx5_fc *drop_counter;
108 } legacy;
109 struct {
110 /* Optional group to add an FTE to do internal priority
111 * tagging on ingress packets.
112 */
113 struct mlx5_flow_group *metadata_prio_tag_grp;
114 /* Group to add default match-all FTE entry to tag ingress
115 * packet with metadata.
116 */
117 struct mlx5_flow_group *metadata_allmatch_grp;
118 /* Optional group to add a drop all rule */
119 struct mlx5_flow_group *drop_grp;
120 struct mlx5_modify_hdr *modify_metadata;
121 struct mlx5_flow_handle *modify_metadata_rule;
122 struct mlx5_flow_handle *drop_rule;
123 } offloads;
124 };
125
126 enum vport_egress_acl_type {
127 VPORT_EGRESS_ACL_TYPE_DEFAULT,
128 VPORT_EGRESS_ACL_TYPE_SHARED_FDB,
129 };
130
131 struct vport_egress {
132 struct mlx5_flow_table *acl;
133 enum vport_egress_acl_type type;
134 struct mlx5_flow_handle *allowed_vlan;
135 struct mlx5_flow_group *vlan_grp;
136 union {
137 struct {
138 struct mlx5_flow_group *drop_grp;
139 struct mlx5_flow_handle *drop_rule;
140 struct mlx5_fc *drop_counter;
141 } legacy;
142 struct {
143 struct mlx5_flow_group *fwd_grp;
144 struct mlx5_flow_handle *fwd_rule;
145 struct xarray bounce_rules;
146 struct mlx5_flow_group *bounce_grp;
147 } offloads;
148 };
149 };
150
151 struct mlx5_vport_drop_stats {
152 u64 rx_dropped;
153 u64 tx_dropped;
154 };
155
156 struct mlx5_vport_info {
157 u8 mac[ETH_ALEN];
158 u16 vlan;
159 u64 node_guid;
160 int link_state;
161 u8 qos;
162 u8 spoofchk: 1;
163 u8 trusted: 1;
164 u8 roce_enabled: 1;
165 u8 mig_enabled: 1;
166 u8 ipsec_crypto_enabled: 1;
167 u8 ipsec_packet_enabled: 1;
168 };
169
170 /* Vport context events */
171 enum mlx5_eswitch_vport_event {
172 MLX5_VPORT_UC_ADDR_CHANGE = BIT(0),
173 MLX5_VPORT_MC_ADDR_CHANGE = BIT(1),
174 MLX5_VPORT_PROMISC_CHANGE = BIT(3),
175 };
176
177 struct mlx5_vport;
178
179 struct mlx5_devlink_port {
180 struct devlink_port dl_port;
181 struct mlx5_vport *vport;
182 };
183
mlx5_devlink_port_init(struct mlx5_devlink_port * dl_port,struct mlx5_vport * vport)184 static inline void mlx5_devlink_port_init(struct mlx5_devlink_port *dl_port,
185 struct mlx5_vport *vport)
186 {
187 dl_port->vport = vport;
188 }
189
mlx5_devlink_port_get(struct devlink_port * dl_port)190 static inline struct mlx5_devlink_port *mlx5_devlink_port_get(struct devlink_port *dl_port)
191 {
192 return container_of(dl_port, struct mlx5_devlink_port, dl_port);
193 }
194
mlx5_devlink_port_vport_get(struct devlink_port * dl_port)195 static inline struct mlx5_vport *mlx5_devlink_port_vport_get(struct devlink_port *dl_port)
196 {
197 return mlx5_devlink_port_get(dl_port)->vport;
198 }
199
200 #define MLX5_VHCA_ID_INVALID (-1)
201
202 #define MLX5_VPORT_INVAL_VHCA_ID(vport) \
203 ((vport)->vhca_id == MLX5_VHCA_ID_INVALID)
204
205 struct mlx5_vport {
206 struct mlx5_core_dev *dev;
207 struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
208 struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
209 struct mlx5_flow_handle *promisc_rule;
210 struct mlx5_flow_handle *allmulti_rule;
211 struct work_struct vport_change_handler;
212
213 struct vport_ingress ingress;
214 struct vport_egress egress;
215 u32 default_metadata;
216 u32 metadata;
217 int vhca_id;
218
219 bool adjacent; /* delegated vhca from adjacent function */
220 struct {
221 u16 parent_pci_devfn; /* Adjacent parent PCI device function */
222 u16 function_id; /* Function ID of the delegated VPort */
223 } adj_info;
224
225 struct mlx5_vport_info info;
226
227 /* Protected with the E-Switch qos domain lock. The Vport QoS can
228 * either be disabled (sched_node is NULL) or in one of three states:
229 * 1. Regular QoS (sched_node is a vport node).
230 * 2. TC QoS enabled on the vport (sched_node is a TC arbiter).
231 * 3. TC QoS enabled on the vport's parent node
232 * (sched_node is a rate limit node).
233 * When TC is enabled in either mode, the vport owns vport TC scheduling
234 * nodes.
235 */
236 struct {
237 /* Vport scheduling node. */
238 struct mlx5_esw_sched_node *sched_node;
239 /* Array of vport traffic class scheduling nodes. */
240 struct mlx5_esw_sched_node **sched_nodes;
241 } qos;
242
243 u16 vport;
244 bool enabled;
245 bool max_eqs_set;
246 bool pf_activated;
247 enum mlx5_eswitch_vport_event enabled_events;
248 int index;
249 struct mlx5_devlink_port *dl_port;
250 u32 agg_max_tx_speed;
251 };
252
253 struct mlx5_esw_indir_table;
254
255 struct mlx5_eswitch_fdb {
256 union {
257 struct legacy_fdb {
258 struct mlx5_flow_table *fdb;
259 struct mlx5_flow_group *addr_grp;
260 struct mlx5_flow_group *allmulti_grp;
261 struct mlx5_flow_group *promisc_grp;
262 struct mlx5_flow_table *vepa_fdb;
263 struct mlx5_flow_handle *vepa_uplink_rule;
264 struct mlx5_flow_handle *vepa_star_rule;
265 } legacy;
266
267 struct offloads_fdb {
268 struct mlx5_flow_namespace *ns;
269 struct mlx5_flow_table *drop_root;
270 struct mlx5_flow_handle *drop_root_rule;
271 struct mlx5_fc *drop_root_fc;
272 struct mlx5_flow_table *tc_miss_table;
273 struct mlx5_flow_table *slow_fdb;
274 struct mlx5_flow_group *send_to_vport_grp;
275 struct mlx5_flow_group *send_to_vport_meta_grp;
276 struct mlx5_flow_group *peer_miss_grp;
277 struct xarray peer_miss_rules;
278 struct mlx5_flow_group *miss_grp;
279 struct mlx5_flow_handle **send_to_vport_meta_rules;
280 struct mlx5_flow_handle *miss_rule_uni;
281 struct mlx5_flow_handle *miss_rule_multi;
282
283 struct mlx5_fs_chains *esw_chains_priv;
284 struct {
285 DECLARE_HASHTABLE(table, 8);
286 /* Protects vports.table */
287 struct mutex lock;
288 } vports;
289
290 struct mlx5_esw_indir_table *indir;
291
292 } offloads;
293 };
294 u32 flags;
295 };
296
297 struct mlx5_esw_offload {
298 struct mlx5_flow_table *ft_offloads_restore;
299 struct mlx5_flow_group *restore_group;
300 struct mlx5_modify_hdr *restore_copy_hdr_id;
301 struct mapping_ctx *reg_c0_obj_pool;
302
303 struct mlx5_flow_table *ft_offloads;
304 struct mlx5_flow_group *vport_rx_group;
305 struct mlx5_flow_group *vport_rx_drop_group;
306 struct mlx5_flow_handle *vport_rx_drop_rule;
307 struct mlx5_flow_table *ft_ipsec_tx_pol;
308 struct xarray vport_reps;
309 struct list_head peer_flows[MLX5_MAX_PORTS];
310 struct mutex peer_mutex;
311 struct mutex encap_tbl_lock; /* protects encap_tbl */
312 DECLARE_HASHTABLE(encap_tbl, 8);
313 struct mutex decap_tbl_lock; /* protects decap_tbl */
314 DECLARE_HASHTABLE(decap_tbl, 8);
315 struct mod_hdr_tbl mod_hdr;
316 DECLARE_HASHTABLE(termtbl_tbl, 8);
317 struct mutex termtbl_mutex; /* protects termtbl hash */
318 struct xarray vhca_map;
319 const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES];
320 u8 inline_mode;
321 atomic64_t num_flows;
322 u64 num_block_encap;
323 u64 num_block_mode;
324 enum devlink_eswitch_encap_mode encap;
325 struct ida vport_metadata_ida;
326 unsigned int host_number; /* ECPF supports one external host */
327 };
328
329 /* E-Switch MC FDB table hash node */
330 struct esw_mc_addr { /* SRIOV only */
331 struct l2addr_node node;
332 struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */
333 u32 refcnt;
334 };
335
336 struct mlx5_host_work {
337 struct work_struct work;
338 struct mlx5_eswitch *esw;
339 int work_gen;
340 };
341
342 struct mlx5_esw_functions {
343 struct mlx5_nb nb;
344 atomic_t generation;
345 bool host_funcs_disabled;
346 u16 num_vfs;
347 u16 num_ec_vfs;
348 };
349
350 enum {
351 MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0),
352 MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED = BIT(1),
353 MLX5_ESWITCH_VPORT_ACL_NS_CREATED = BIT(2),
354 };
355
356 struct mlx5_esw_bridge_offloads;
357
358 enum {
359 MLX5_ESW_FDB_CREATED = BIT(0),
360 };
361
362 struct dentry;
363 struct mlx5_qos_domain;
364
365 struct mlx5_eswitch {
366 struct mlx5_core_dev *dev;
367 struct mlx5_nb nb;
368 struct mlx5_eswitch_fdb fdb_table;
369 /* legacy data structures */
370 struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
371 struct esw_mc_addr mc_promisc;
372 /* end of legacy */
373 struct dentry *debugfs_root;
374 struct workqueue_struct *work_queue;
375 struct xarray vports;
376 u32 flags;
377 int total_vports;
378 int enabled_vports;
379 /* Synchronize between vport change events
380 * and async SRIOV admin state changes
381 */
382 struct mutex state_lock;
383
384 /* Protects eswitch mode change that occurs via one or more
385 * user commands, i.e. sriov state change, devlink commands.
386 */
387 struct rw_semaphore mode_lock;
388 atomic64_t user_count;
389
390 /* Protected with the E-Switch qos domain lock. */
391 struct {
392 /* Initially 0, meaning no QoS users and QoS is disabled. */
393 refcount_t refcnt;
394 u32 root_tsar_ix;
395 struct mlx5_qos_domain *domain;
396 } qos;
397
398 struct mlx5_esw_bridge_offloads *br_offloads;
399 struct mlx5_esw_offload offloads;
400 u32 last_vport_idx;
401 int mode;
402 bool offloads_inactive;
403 u16 manager_vport;
404 u16 first_host_vport;
405 u8 num_peers;
406 struct mlx5_esw_functions esw_funcs;
407 struct {
408 u32 large_group_num;
409 } params;
410 struct xarray paired;
411 struct mlx5_devcom_comp_dev *devcom;
412 u16 enabled_ipsec_vf_count;
413 bool eswitch_operation_in_progress;
414 };
415
416 void esw_offloads_disable(struct mlx5_eswitch *esw);
417 int esw_offloads_enable(struct mlx5_eswitch *esw);
418 void esw_offloads_cleanup(struct mlx5_eswitch *esw);
419 int esw_offloads_init(struct mlx5_eswitch *esw);
420
421 struct mlx5_flow_handle *
422 mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch *esw, u16 vport_num);
423 void mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle *rule);
424
425 bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw);
426 u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw);
427 void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata);
428
429 int mlx5_esw_qos_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num, u32 rate_mbps);
430
431 /* E-Switch API */
432 int mlx5_eswitch_init(struct mlx5_core_dev *dev);
433 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
434 int mlx5_esw_vport_alloc(struct mlx5_eswitch *esw, int index, u16 vport_num);
435 void mlx5_esw_vport_free(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
436
437 #define MLX5_ESWITCH_IGNORE_NUM_VFS (-1)
438 int mlx5_eswitch_enable_locked(struct mlx5_eswitch *esw, int num_vfs);
439 int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs);
440 void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw, bool clear_vf);
441 void mlx5_eswitch_disable_locked(struct mlx5_eswitch *esw);
442 void mlx5_eswitch_disable(struct mlx5_eswitch *esw);
443 void mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw,
444 const struct mlx5_devcom_match_attr *attr);
445 void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw);
446 bool mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch *esw);
447 int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
448 u16 vport, const u8 *mac);
449 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
450 u16 vport, int link_state);
451 int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
452 u16 vport, u16 vlan, u8 qos);
453 int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
454 u16 vport, bool spoofchk);
455 int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
456 u16 vport_num, bool setting);
457 int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport,
458 u32 max_rate, u32 min_rate);
459 int mlx5_esw_qos_vport_update_parent(struct mlx5_vport *vport, struct mlx5_esw_sched_node *node,
460 struct netlink_ext_ack *extack);
461 int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting);
462 int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting);
463 int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
464 u16 vport, struct ifla_vf_info *ivi);
465 int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
466 u16 vport,
467 struct ifla_vf_stats *vf_stats);
468 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
469
470 int mlx5_eswitch_modify_esw_vport_context(struct mlx5_core_dev *dev, u16 vport,
471 bool other_vport, void *in);
472
473 struct mlx5_flow_spec;
474 struct mlx5_esw_flow_attr;
475 struct mlx5_termtbl_handle;
476
477 bool
478 mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw,
479 struct mlx5_flow_attr *attr,
480 struct mlx5_flow_act *flow_act,
481 struct mlx5_flow_spec *spec);
482
483 struct mlx5_flow_handle *
484 mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw,
485 struct mlx5_flow_table *ft,
486 struct mlx5_flow_spec *spec,
487 struct mlx5_esw_flow_attr *attr,
488 struct mlx5_flow_act *flow_act,
489 struct mlx5_flow_destination *dest,
490 int num_dest);
491
492 void
493 mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw,
494 struct mlx5_termtbl_handle *tt);
495
496 void
497 mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec);
498
499 struct mlx5_flow_handle *
500 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
501 struct mlx5_flow_spec *spec,
502 struct mlx5_flow_attr *attr);
503 struct mlx5_flow_handle *
504 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
505 struct mlx5_flow_spec *spec,
506 struct mlx5_flow_attr *attr);
507 void
508 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
509 struct mlx5_flow_handle *rule,
510 struct mlx5_flow_attr *attr);
511 void
512 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
513 struct mlx5_flow_handle *rule,
514 struct mlx5_flow_attr *attr);
515
516 struct mlx5_flow_handle *
517 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
518 struct mlx5_flow_destination *dest);
519
520 enum {
521 SET_VLAN_STRIP = BIT(0),
522 SET_VLAN_INSERT = BIT(1)
523 };
524
525 enum mlx5_flow_match_level {
526 MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
527 MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2,
528 MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP,
529 MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP,
530 };
531
532 /* current maximum for flow based vport multicasting */
533 #define MLX5_MAX_FLOW_FWD_VPORTS 32
534
535 enum {
536 MLX5_ESW_DEST_ENCAP = BIT(0),
537 MLX5_ESW_DEST_ENCAP_VALID = BIT(1),
538 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE = BIT(2),
539 };
540
541 struct mlx5_esw_flow_attr {
542 struct mlx5_eswitch_rep *in_rep;
543 struct mlx5_core_dev *in_mdev;
544 struct mlx5_core_dev *counter_dev;
545 struct mlx5e_tc_int_port *dest_int_port;
546 struct mlx5e_tc_int_port *int_port;
547
548 int split_count;
549 int out_count;
550
551 __be16 vlan_proto[MLX5_FS_VLAN_DEPTH];
552 u16 vlan_vid[MLX5_FS_VLAN_DEPTH];
553 u8 vlan_prio[MLX5_FS_VLAN_DEPTH];
554 u8 total_vlan;
555 struct {
556 u32 flags;
557 bool vport_valid;
558 u16 vport;
559 struct mlx5_pkt_reformat *pkt_reformat;
560 struct mlx5_core_dev *mdev;
561 struct mlx5_termtbl_handle *termtbl;
562 int src_port_rewrite_act_id;
563 } dests[MLX5_MAX_FLOW_FWD_VPORTS];
564 struct mlx5_rx_tun_attr *rx_tun_attr;
565 struct ethhdr eth;
566 struct mlx5_pkt_reformat *decap_pkt_reformat;
567 };
568
569 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
570 struct netlink_ext_ack *extack);
571 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
572 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
573 struct netlink_ext_ack *extack);
574 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
575 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
576 enum devlink_eswitch_encap_mode encap,
577 struct netlink_ext_ack *extack);
578 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
579 enum devlink_eswitch_encap_mode *encap);
580 int mlx5_devlink_port_fn_hw_addr_get(struct devlink_port *port,
581 u8 *hw_addr, int *hw_addr_len,
582 struct netlink_ext_ack *extack);
583 int mlx5_devlink_port_fn_hw_addr_set(struct devlink_port *port,
584 const u8 *hw_addr, int hw_addr_len,
585 struct netlink_ext_ack *extack);
586 int mlx5_devlink_port_fn_roce_get(struct devlink_port *port, bool *is_enabled,
587 struct netlink_ext_ack *extack);
588 int mlx5_devlink_port_fn_roce_set(struct devlink_port *port, bool enable,
589 struct netlink_ext_ack *extack);
590 int mlx5_devlink_port_fn_migratable_get(struct devlink_port *port, bool *is_enabled,
591 struct netlink_ext_ack *extack);
592 int mlx5_devlink_port_fn_migratable_set(struct devlink_port *port, bool enable,
593 struct netlink_ext_ack *extack);
594 int mlx5_devlink_pf_port_fn_state_get(struct devlink_port *port,
595 enum devlink_port_fn_state *state,
596 enum devlink_port_fn_opstate *opstate,
597 struct netlink_ext_ack *extack);
598 int mlx5_devlink_pf_port_fn_state_set(struct devlink_port *port,
599 enum devlink_port_fn_state state,
600 struct netlink_ext_ack *extack);
601 #ifdef CONFIG_XFRM_OFFLOAD
602 int mlx5_devlink_port_fn_ipsec_crypto_get(struct devlink_port *port, bool *is_enabled,
603 struct netlink_ext_ack *extack);
604 int mlx5_devlink_port_fn_ipsec_crypto_set(struct devlink_port *port, bool enable,
605 struct netlink_ext_ack *extack);
606 int mlx5_devlink_port_fn_ipsec_packet_get(struct devlink_port *port, bool *is_enabled,
607 struct netlink_ext_ack *extack);
608 int mlx5_devlink_port_fn_ipsec_packet_set(struct devlink_port *port, bool enable,
609 struct netlink_ext_ack *extack);
610 #endif /* CONFIG_XFRM_OFFLOAD */
611 int mlx5_devlink_port_fn_max_io_eqs_get(struct devlink_port *port,
612 u32 *max_io_eqs,
613 struct netlink_ext_ack *extack);
614 int mlx5_devlink_port_fn_max_io_eqs_set(struct devlink_port *port,
615 u32 max_io_eqs,
616 struct netlink_ext_ack *extack);
617 int mlx5_devlink_port_fn_max_io_eqs_set_sf_default(struct devlink_port *port,
618 struct netlink_ext_ack *extack);
619
620 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);
621
622 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
623 u16 vport, u16 vlan, u8 qos, u8 set_flags);
624
esw_vst_mode_is_steering(struct mlx5_eswitch * esw)625 static inline bool esw_vst_mode_is_steering(struct mlx5_eswitch *esw)
626 {
627 return (MLX5_CAP_ESW_EGRESS_ACL(esw->dev, pop_vlan) &&
628 MLX5_CAP_ESW_INGRESS_ACL(esw->dev, push_vlan));
629 }
630
mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev * dev,u8 vlan_depth)631 static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
632 u8 vlan_depth)
633 {
634 bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
635 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);
636
637 if (vlan_depth == 1)
638 return ret;
639
640 return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
641 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
642 }
643
644 bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0,
645 struct mlx5_core_dev *dev1);
646
647 const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev);
648 int mlx5_esw_host_pf_enable_hca(struct mlx5_core_dev *dev);
649 int mlx5_esw_host_pf_disable_hca(struct mlx5_core_dev *dev);
650
651 void mlx5_esw_adjacent_vhcas_setup(struct mlx5_eswitch *esw);
652 void mlx5_esw_adjacent_vhcas_cleanup(struct mlx5_eswitch *esw);
653 int mlx5_esw_adj_vport_modify(struct mlx5_core_dev *dev, u16 vport,
654 bool connect);
655
656 #define MLX5_DEBUG_ESWITCH_MASK BIT(3)
657
658 #define esw_info(__dev, format, ...) \
659 dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
660
661 #define esw_warn(__dev, format, ...) \
662 dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
663
664 #define esw_debug(dev, format, ...) \
665 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
666
mlx5_esw_allowed(const struct mlx5_eswitch * esw)667 static inline bool mlx5_esw_allowed(const struct mlx5_eswitch *esw)
668 {
669 return esw && MLX5_ESWITCH_MANAGER(esw->dev);
670 }
671
672 static inline bool
mlx5_esw_is_manager_vport(const struct mlx5_eswitch * esw,u16 vport_num)673 mlx5_esw_is_manager_vport(const struct mlx5_eswitch *esw, u16 vport_num)
674 {
675 return esw->manager_vport == vport_num;
676 }
677
mlx5_esw_is_owner(struct mlx5_eswitch * esw,u16 vport_num,u16 esw_owner_vhca_id)678 static inline bool mlx5_esw_is_owner(struct mlx5_eswitch *esw, u16 vport_num,
679 u16 esw_owner_vhca_id)
680 {
681 return esw_owner_vhca_id == MLX5_CAP_GEN(esw->dev, vhca_id) ||
682 (vport_num == MLX5_VPORT_UPLINK && mlx5_lag_is_master(esw->dev));
683 }
684
mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev * dev)685 static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev)
686 {
687 return mlx5_core_is_ecpf_esw_manager(dev) ?
688 MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF;
689 }
690
mlx5_eswitch_is_funcs_handler(const struct mlx5_core_dev * dev)691 static inline bool mlx5_eswitch_is_funcs_handler(const struct mlx5_core_dev *dev)
692 {
693 return mlx5_core_is_ecpf_esw_manager(dev);
694 }
695
696 static inline unsigned int
mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev * dev,u16 vport_num)697 mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev,
698 u16 vport_num)
699 {
700 return (MLX5_CAP_GEN(dev, vhca_id) << 16) | vport_num;
701 }
702
703 static inline u16
mlx5_esw_devlink_port_index_to_vport_num(unsigned int dl_port_index)704 mlx5_esw_devlink_port_index_to_vport_num(unsigned int dl_port_index)
705 {
706 return dl_port_index & 0xffff;
707 }
708
mlx5_esw_is_fdb_created(struct mlx5_eswitch * esw)709 static inline bool mlx5_esw_is_fdb_created(struct mlx5_eswitch *esw)
710 {
711 return esw->fdb_table.flags & MLX5_ESW_FDB_CREATED;
712 }
713
714 /* TODO: This mlx5e_tc function shouldn't be called by eswitch */
715 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw);
716
717 /* Each mark identifies eswitch vport type.
718 * MLX5_ESW_VPT_HOST_FN is used to identify both PF and VF ports using
719 * a single mark.
720 * MLX5_ESW_VPT_VF identifies a SRIOV VF vport.
721 * MLX5_ESW_VPT_SF identifies SF vport.
722 */
723 #define MLX5_ESW_VPT_HOST_FN XA_MARK_0
724 #define MLX5_ESW_VPT_VF XA_MARK_1
725 #define MLX5_ESW_VPT_SF XA_MARK_2
726
727 /* The vport iterator is valid only after vport are initialized in mlx5_eswitch_init.
728 * Borrowed the idea from xa_for_each_marked() but with support for desired last element.
729 */
730
731 #define mlx5_esw_for_each_vport(esw, index, vport) \
732 xa_for_each(&((esw)->vports), index, vport)
733
734 #define mlx5_esw_for_each_entry_marked(xa, index, entry, last, filter) \
735 for (index = 0, entry = xa_find(xa, &index, last, filter); \
736 entry; entry = xa_find_after(xa, &index, last, filter))
737
738 #define mlx5_esw_for_each_vport_marked(esw, index, vport, last, filter) \
739 mlx5_esw_for_each_entry_marked(&((esw)->vports), index, vport, last, filter)
740
741 #define mlx5_esw_for_each_vf_vport(esw, index, vport, last) \
742 mlx5_esw_for_each_vport_marked(esw, index, vport, last, MLX5_ESW_VPT_VF)
743
744 #define mlx5_esw_for_each_host_func_vport(esw, index, vport, last) \
745 mlx5_esw_for_each_vport_marked(esw, index, vport, last, MLX5_ESW_VPT_HOST_FN)
746
747 /* This macro should only be used if EC SRIOV is enabled.
748 *
749 * Because there were no more marks available on the xarray this uses a
750 * for_each_range approach. The range is only valid when EC SRIOV is enabled
751 */
752 #define mlx5_esw_for_each_ec_vf_vport(esw, index, vport, last) \
753 xa_for_each_range(&((esw)->vports), \
754 index, \
755 vport, \
756 MLX5_CAP_GEN_2((esw->dev), ec_vf_vport_base), \
757 MLX5_CAP_GEN_2((esw->dev), ec_vf_vport_base) +\
758 (last) - 1)
759
760 #define mlx5_esw_for_each_rep(esw, i, rep) \
761 xa_for_each(&((esw)->offloads.vport_reps), i, rep)
762
763 struct mlx5_eswitch *__must_check
764 mlx5_devlink_eswitch_get(struct devlink *devlink);
765
766 struct mlx5_eswitch *mlx5_devlink_eswitch_nocheck_get(struct devlink *devlink);
767
768 struct mlx5_vport *__must_check
769 mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num);
770
771 bool mlx5_eswitch_is_vf_vport(struct mlx5_eswitch *esw, u16 vport_num);
772 bool mlx5_eswitch_is_pf_vf_vport(struct mlx5_eswitch *esw, u16 vport_num);
773 bool mlx5_esw_is_sf_vport(struct mlx5_eswitch *esw, u16 vport_num);
774
775 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data);
776
777 int
778 mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw,
779 enum mlx5_eswitch_vport_event enabled_events);
780 void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw);
781
782 int mlx5_esw_vport_enable(struct mlx5_eswitch *esw, struct mlx5_vport *vport,
783 enum mlx5_eswitch_vport_event enabled_events);
784 void mlx5_esw_vport_disable(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
785
786 int
787 esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
788 struct mlx5_vport *vport);
789 void
790 esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
791 struct mlx5_vport *vport);
792
793 struct esw_vport_tbl_namespace {
794 int max_fte;
795 int max_num_groups;
796 u32 flags;
797 };
798
799 struct mlx5_vport_tbl_attr {
800 u32 chain;
801 u16 prio;
802 u16 vport;
803 struct esw_vport_tbl_namespace *vport_ns;
804 };
805
806 struct mlx5_flow_table *
807 mlx5_esw_vporttbl_get(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr);
808 void
809 mlx5_esw_vporttbl_put(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr);
810
811 struct mlx5_flow_handle *
812 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag);
813
814 void mlx5_esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
815 u32 *flow_group_in,
816 int match_params);
817
818 void mlx5_esw_set_spec_source_port(struct mlx5_eswitch *esw,
819 u16 vport,
820 struct mlx5_flow_spec *spec);
821
822 int mlx5_esw_offloads_init_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
823 void mlx5_esw_offloads_cleanup_pf_vf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
824
825 int mlx5_esw_offloads_init_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport,
826 struct mlx5_devlink_port *dl_port,
827 u32 controller, u32 sfnum);
828 void mlx5_esw_offloads_cleanup_sf_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
829
830 int mlx5_esw_offloads_load_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
831 void mlx5_esw_offloads_unload_rep(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
832
833 int mlx5_eswitch_load_sf_vport(struct mlx5_eswitch *esw, u16 vport_num,
834 enum mlx5_eswitch_vport_event enabled_events,
835 struct mlx5_devlink_port *dl_port, u32 controller, u32 sfnum);
836 void mlx5_eswitch_unload_sf_vport(struct mlx5_eswitch *esw, u16 vport_num);
837
838 int mlx5_eswitch_load_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs,
839 enum mlx5_eswitch_vport_event enabled_events);
840 void mlx5_eswitch_unload_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs);
841
842 int mlx5_esw_offloads_pf_vf_devlink_port_init(struct mlx5_eswitch *esw,
843 struct mlx5_vport *vport);
844 void mlx5_esw_offloads_pf_vf_devlink_port_cleanup(struct mlx5_eswitch *esw,
845 struct mlx5_vport *vport);
846
847 int mlx5_esw_offloads_sf_devlink_port_init(struct mlx5_eswitch *esw, struct mlx5_vport *vport,
848 struct mlx5_devlink_port *dl_port,
849 u32 controller, u32 sfnum);
850 void mlx5_esw_offloads_sf_devlink_port_cleanup(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
851
852 int mlx5_esw_offloads_devlink_port_register(struct mlx5_eswitch *esw, struct mlx5_vport *vport);
853 void mlx5_esw_offloads_devlink_port_unregister(struct mlx5_vport *vport);
854 struct devlink_port *mlx5_esw_offloads_devlink_port(struct mlx5_eswitch *esw, u16 vport_num);
855
856 int mlx5_esw_sf_max_hpf_functions(struct mlx5_core_dev *dev, u16 *max_sfs, u16 *sf_base_id);
857
858 int mlx5_esw_vport_vhca_id_map(struct mlx5_eswitch *esw,
859 struct mlx5_vport *vport);
860 void mlx5_esw_vport_vhca_id_unmap(struct mlx5_eswitch *esw,
861 struct mlx5_vport *vport);
862 int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num);
863 bool mlx5_esw_vport_vhca_id(struct mlx5_eswitch *esw, u16 vportn, u16 *vhca_id);
864
865 void mlx5_esw_offloads_rep_remove(struct mlx5_eswitch *esw,
866 const struct mlx5_vport *vport);
867 int mlx5_esw_offloads_rep_add(struct mlx5_eswitch *esw,
868 const struct mlx5_vport *vport);
869
870 /**
871 * struct mlx5_esw_event_info - Indicates eswitch mode changed/changing.
872 *
873 * @new_mode: New mode of eswitch.
874 */
875 struct mlx5_esw_event_info {
876 u16 new_mode;
877 };
878
879 int mlx5_esw_event_notifier_register(struct mlx5_core_dev *dev,
880 struct notifier_block *n);
881 void mlx5_esw_event_notifier_unregister(struct mlx5_core_dev *dev,
882 struct notifier_block *n);
883
884 bool mlx5_esw_hold(struct mlx5_core_dev *dev);
885 void mlx5_esw_release(struct mlx5_core_dev *dev);
886 void mlx5_esw_get(struct mlx5_core_dev *dev);
887 void mlx5_esw_put(struct mlx5_core_dev *dev);
888 int mlx5_esw_try_lock(struct mlx5_eswitch *esw);
889 int mlx5_esw_lock(struct mlx5_eswitch *esw);
890 void mlx5_esw_unlock(struct mlx5_eswitch *esw);
891
892 void esw_vport_change_handle_locked(struct mlx5_vport *vport);
893
894 bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller);
895
896 int mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw,
897 struct mlx5_eswitch *slave_esw, int max_slaves);
898 void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw,
899 struct mlx5_eswitch *slave_esw);
900 int mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch *esw);
901
902 bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb);
903 void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev);
904
905 int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev);
906 void mlx5_eswitch_unblock_mode(struct mlx5_core_dev *dev);
907
mlx5_eswitch_num_vfs(struct mlx5_eswitch * esw)908 static inline int mlx5_eswitch_num_vfs(struct mlx5_eswitch *esw)
909 {
910 if (mlx5_esw_allowed(esw))
911 return esw->esw_funcs.num_vfs;
912
913 return 0;
914 }
915
mlx5_eswitch_get_npeers(struct mlx5_eswitch * esw)916 static inline int mlx5_eswitch_get_npeers(struct mlx5_eswitch *esw)
917 {
918 if (mlx5_esw_allowed(esw))
919 return esw->num_peers;
920 return 0;
921 }
922
923 static inline struct mlx5_flow_table *
mlx5_eswitch_get_slow_fdb(struct mlx5_eswitch * esw)924 mlx5_eswitch_get_slow_fdb(struct mlx5_eswitch *esw)
925 {
926 return esw->fdb_table.offloads.slow_fdb;
927 }
928
929 int mlx5_eswitch_restore_ipsec_rule(struct mlx5_eswitch *esw, struct mlx5_flow_handle *rule,
930 struct mlx5_esw_flow_attr *esw_attr, int attr_idx);
931 bool mlx5_eswitch_block_ipsec(struct mlx5_core_dev *dev);
932 void mlx5_eswitch_unblock_ipsec(struct mlx5_core_dev *dev);
933 bool mlx5_esw_ipsec_vf_offload_supported(struct mlx5_core_dev *dev);
934 int mlx5_esw_ipsec_vf_offload_get(struct mlx5_core_dev *dev,
935 struct mlx5_vport *vport);
936 int mlx5_esw_ipsec_vf_crypto_offload_supported(struct mlx5_core_dev *dev,
937 u16 vport_num);
938 int mlx5_esw_ipsec_vf_crypto_offload_set(struct mlx5_eswitch *esw, struct mlx5_vport *vport,
939 bool enable);
940 int mlx5_esw_ipsec_vf_packet_offload_set(struct mlx5_eswitch *esw, struct mlx5_vport *vport,
941 bool enable);
942 int mlx5_esw_ipsec_vf_packet_offload_supported(struct mlx5_core_dev *dev,
943 u16 vport_num);
944 bool mlx5_esw_host_functions_enabled(const struct mlx5_core_dev *dev);
945 void mlx5_eswitch_safe_aux_devs_remove(struct mlx5_core_dev *dev);
946 struct mlx5_flow_group *
947 mlx5_esw_lag_demux_fg_create(struct mlx5_eswitch *esw,
948 struct mlx5_flow_table *ft);
949 struct mlx5_flow_handle *
950 mlx5_esw_lag_demux_rule_create(struct mlx5_eswitch *esw, u16 vport_num,
951 struct mlx5_flow_table *lag_ft);
952 #else /* CONFIG_MLX5_ESWITCH */
953 /* eswitch API stubs */
mlx5_eswitch_init(struct mlx5_core_dev * dev)954 static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
mlx5_eswitch_cleanup(struct mlx5_eswitch * esw)955 static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
mlx5_eswitch_enable(struct mlx5_eswitch * esw,int num_vfs)956 static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs) { return 0; }
mlx5_eswitch_disable_sriov(struct mlx5_eswitch * esw,bool clear_vf)957 static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw, bool clear_vf) {}
mlx5_eswitch_disable(struct mlx5_eswitch * esw)958 static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw) {}
959 static inline void
mlx5_esw_offloads_devcom_init(struct mlx5_eswitch * esw,const struct mlx5_devcom_match_attr * attr)960 mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw,
961 const struct mlx5_devcom_match_attr *attr) {}
mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch * esw)962 static inline void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw) {}
mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch * esw)963 static inline bool mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch *esw) { return false; }
mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev * dev)964 static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; }
965 static inline
mlx5_eswitch_set_vport_state(struct mlx5_eswitch * esw,u16 vport,int link_state)966 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, u16 vport, int link_state) { return 0; }
mlx5_esw_query_functions(struct mlx5_core_dev * dev)967 static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev)
968 {
969 return ERR_PTR(-EOPNOTSUPP);
970 }
971
972 static inline struct mlx5_flow_handle *
esw_add_restore_rule(struct mlx5_eswitch * esw,u32 tag)973 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
974 {
975 return ERR_PTR(-EOPNOTSUPP);
976 }
977
978 static inline unsigned int
mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev * dev,u16 vport_num)979 mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev,
980 u16 vport_num)
981 {
982 return vport_num;
983 }
984
985 static inline int
mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch * master_esw,struct mlx5_eswitch * slave_esw,int max_slaves)986 mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw,
987 struct mlx5_eswitch *slave_esw, int max_slaves)
988 {
989 return 0;
990 }
991
992 static inline void
mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch * master_esw,struct mlx5_eswitch * slave_esw)993 mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw,
994 struct mlx5_eswitch *slave_esw) {}
995
mlx5_eswitch_get_npeers(struct mlx5_eswitch * esw)996 static inline int mlx5_eswitch_get_npeers(struct mlx5_eswitch *esw) { return 0; }
997
998 static inline int
mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch * esw)999 mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch *esw)
1000 {
1001 return 0;
1002 }
1003
1004 static inline bool
mlx5_eswitch_block_encap(struct mlx5_core_dev * dev,bool from_fdb)1005 mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb)
1006 {
1007 return true;
1008 }
1009
mlx5_eswitch_unblock_encap(struct mlx5_core_dev * dev)1010 static inline void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev)
1011 {
1012 }
1013
mlx5_eswitch_block_mode(struct mlx5_core_dev * dev)1014 static inline int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev) { return 0; }
mlx5_eswitch_unblock_mode(struct mlx5_core_dev * dev)1015 static inline void mlx5_eswitch_unblock_mode(struct mlx5_core_dev *dev) {}
mlx5_eswitch_block_ipsec(struct mlx5_core_dev * dev)1016 static inline bool mlx5_eswitch_block_ipsec(struct mlx5_core_dev *dev)
1017 {
1018 return false;
1019 }
1020
mlx5_eswitch_unblock_ipsec(struct mlx5_core_dev * dev)1021 static inline void mlx5_eswitch_unblock_ipsec(struct mlx5_core_dev *dev) {}
1022
1023 static inline bool
mlx5_esw_host_functions_enabled(const struct mlx5_core_dev * dev)1024 mlx5_esw_host_functions_enabled(const struct mlx5_core_dev *dev)
1025 {
1026 return true;
1027 }
1028
1029 static inline bool
mlx5_esw_vport_vhca_id(struct mlx5_eswitch * esw,u16 vportn,u16 * vhca_id)1030 mlx5_esw_vport_vhca_id(struct mlx5_eswitch *esw, u16 vportn, u16 *vhca_id)
1031 {
1032 return false;
1033 }
1034
1035 static inline void
mlx5_eswitch_safe_aux_devs_remove(struct mlx5_core_dev * dev)1036 mlx5_eswitch_safe_aux_devs_remove(struct mlx5_core_dev *dev) {}
1037 static inline struct mlx5_flow_handle *
mlx5_esw_lag_demux_rule_create(struct mlx5_eswitch * esw,u16 vport_num,struct mlx5_flow_table * lag_ft)1038 mlx5_esw_lag_demux_rule_create(struct mlx5_eswitch *esw, u16 vport_num,
1039 struct mlx5_flow_table *lag_ft)
1040 {
1041 return ERR_PTR(-EOPNOTSUPP);
1042 }
1043
1044 #endif /* CONFIG_MLX5_ESWITCH */
1045
1046 #endif /* __MLX5_ESWITCH_H__ */
1047