1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_smu.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "amdgpu_atombios.h"
32 #include "smu_v13_0_6_pmfw.h"
33 #include "smu13_driver_if_v13_0_6.h"
34 #include "smu_v13_0_6_ppsmc.h"
35 #include "soc15_common.h"
36 #include "atom.h"
37 #include "power_state.h"
38 #include "smu_v13_0.h"
39 #include "smu_v13_0_6_ppt.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/pci.h>
46 #include "amdgpu_ras.h"
47 #include "amdgpu_mca.h"
48 #include "amdgpu_aca.h"
49 #include "smu_cmn.h"
50 #include "mp/mp_13_0_6_offset.h"
51 #include "mp/mp_13_0_6_sh_mask.h"
52 #include "umc_v12_0.h"
53
54 #undef MP1_Public
55 #undef smnMP1_FIRMWARE_FLAGS
56
57 /* TODO: Check final register offsets */
58 #define MP1_Public 0x03b00000
59 #define smnMP1_FIRMWARE_FLAGS 0x3010028
60 /*
61 * DO NOT use these for err/warn/info/debug messages.
62 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
63 * They are more MGPU friendly.
64 */
65 #undef pr_err
66 #undef pr_warn
67 #undef pr_info
68 #undef pr_debug
69
70 MODULE_FIRMWARE("amdgpu/smu_13_0_6.bin");
71 MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin");
72
73 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
74
75 #define SMU_13_0_6_FEA_MAP(smu_feature, smu_13_0_6_feature) \
76 [smu_feature] = { 1, (smu_13_0_6_feature) }
77
78 #define FEATURE_MASK(feature) (1ULL << feature)
79 #define SMC_DPM_FEATURE \
80 (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \
81 FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_UCLK) | \
82 FEATURE_MASK(FEATURE_DPM_SOCCLK) | FEATURE_MASK(FEATURE_DPM_FCLK) | \
83 FEATURE_MASK(FEATURE_DPM_LCLK) | FEATURE_MASK(FEATURE_DPM_XGMI) | \
84 FEATURE_MASK(FEATURE_DPM_VCN))
85
86 /* possible frequency drift (1Mhz) */
87 #define EPSILON 1
88
89 #define smnPCIE_ESM_CTRL 0x93D0
90 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288
91 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
92 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
93 #define MAX_LINK_WIDTH 6
94
95 #define smnPCIE_LC_SPEED_CNTL 0x1a340290
96 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0
97 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
98 #define LINK_SPEED_MAX 4
99 #define SMU_13_0_6_DSCLK_THRESHOLD 140
100
101 #define MCA_BANK_IPID(_ip, _hwid, _type) \
102 [AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, }
103
104 struct mca_bank_ipid {
105 enum amdgpu_mca_ip ip;
106 uint16_t hwid;
107 uint16_t mcatype;
108 };
109
110 struct mca_ras_info {
111 enum amdgpu_ras_block blkid;
112 enum amdgpu_mca_ip ip;
113 int *err_code_array;
114 int err_code_count;
115 int (*get_err_count)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
116 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count);
117 bool (*bank_is_valid)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
118 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry);
119 };
120
121 #define P2S_TABLE_ID_A 0x50325341
122 #define P2S_TABLE_ID_X 0x50325358
123 #define P2S_TABLE_ID_3 0x50325303
124
125 // clang-format off
126 static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
127 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
128 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
129 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
130 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
131 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
132 MSG_MAP(RequestI2cTransaction, PPSMC_MSG_RequestI2cTransaction, 0),
133 MSG_MAP(GetMetricsTable, PPSMC_MSG_GetMetricsTable, 1),
134 MSG_MAP(GetMetricsVersion, PPSMC_MSG_GetMetricsVersion, 1),
135 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
136 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
137 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
138 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
139 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
140 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
141 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
142 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
143 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
144 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
145 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
146 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
147 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
148 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI),
149 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
150 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
151 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
152 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
153 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0),
154 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
155 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0),
156 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0),
157 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
158 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0),
159 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0),
160 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0),
161 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),
162 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
163 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxDpmFreq, 1),
164 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxDpmFreq, 1),
165 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxClk, 1),
166 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
167 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareForDriverUnload, 0),
168 MSG_MAP(GetCTFLimit, PPSMC_MSG_GetCTFLimit, 0),
169 MSG_MAP(GetThermalLimit, PPSMC_MSG_ReadThrottlerLimit, 0),
170 MSG_MAP(ClearMcaOnRead, PPSMC_MSG_ClearMcaOnRead, 0),
171 MSG_MAP(QueryValidMcaCount, PPSMC_MSG_QueryValidMcaCount, SMU_MSG_RAS_PRI),
172 MSG_MAP(QueryValidMcaCeCount, PPSMC_MSG_QueryValidMcaCeCount, SMU_MSG_RAS_PRI),
173 MSG_MAP(McaBankDumpDW, PPSMC_MSG_McaBankDumpDW, SMU_MSG_RAS_PRI),
174 MSG_MAP(McaBankCeDumpDW, PPSMC_MSG_McaBankCeDumpDW, SMU_MSG_RAS_PRI),
175 MSG_MAP(SelectPLPDMode, PPSMC_MSG_SelectPLPDMode, 0),
176 MSG_MAP(RmaDueToBadPageThreshold, PPSMC_MSG_RmaDueToBadPageThreshold, 0),
177 MSG_MAP(SetThrottlingPolicy, PPSMC_MSG_SetThrottlingPolicy, 0),
178 MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0),
179 MSG_MAP(ResetVCN, PPSMC_MSG_ResetVCN, 0),
180 MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 0),
181 };
182
183 // clang-format on
184 static const struct cmn2asic_mapping smu_v13_0_6_clk_map[SMU_CLK_COUNT] = {
185 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
186 CLK_MAP(FCLK, PPCLK_FCLK),
187 CLK_MAP(UCLK, PPCLK_UCLK),
188 CLK_MAP(MCLK, PPCLK_UCLK),
189 CLK_MAP(DCLK, PPCLK_DCLK),
190 CLK_MAP(VCLK, PPCLK_VCLK),
191 CLK_MAP(LCLK, PPCLK_LCLK),
192 };
193
194 static const struct cmn2asic_mapping smu_v13_0_6_feature_mask_map[SMU_FEATURE_COUNT] = {
195 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATION),
196 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK),
197 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK),
198 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK),
199 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK),
200 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK),
201 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_VCLK_BIT, FEATURE_DPM_VCN),
202 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_DCLK_BIT, FEATURE_DPM_VCN),
203 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI),
204 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK),
205 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK),
206 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK),
207 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK),
208 SMU_13_0_6_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN),
209 SMU_13_0_6_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT),
210 SMU_13_0_6_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC),
211 SMU_13_0_6_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL),
212 SMU_13_0_6_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_SMU_CG),
213 SMU_13_0_6_FEA_MAP(SMU_FEATURE_GFXOFF_BIT, FEATURE_GFXOFF),
214 SMU_13_0_6_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF),
215 SMU_13_0_6_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL),
216 SMU_13_0_6_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DOWN),
217 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE),
218 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_VCN_BIT, FEATURE_DS_VCN),
219 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_MP1CLK_BIT, FEATURE_DS_MP1CLK),
220 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_MPIOCLK_BIT, FEATURE_DS_MPIOCLK),
221 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_MP0CLK_BIT, FEATURE_DS_MP0CLK),
222 };
223
224 #define TABLE_PMSTATUSLOG 0
225 #define TABLE_SMU_METRICS 1
226 #define TABLE_I2C_COMMANDS 2
227 #define TABLE_COUNT 3
228
229 static const struct cmn2asic_mapping smu_v13_0_6_table_map[SMU_TABLE_COUNT] = {
230 TAB_MAP(PMSTATUSLOG),
231 TAB_MAP(SMU_METRICS),
232 TAB_MAP(I2C_COMMANDS),
233 };
234
235 static const uint8_t smu_v13_0_6_throttler_map[] = {
236 [THROTTLER_PPT_BIT] = (SMU_THROTTLER_PPT0_BIT),
237 [THROTTLER_THERMAL_SOCKET_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT),
238 [THROTTLER_THERMAL_HBM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
239 [THROTTLER_THERMAL_VR_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
240 [THROTTLER_PROCHOT_BIT] = (SMU_THROTTLER_PROCHOT_GFX_BIT),
241 };
242
243 #define GET_GPU_METRIC_FIELD(field, version) ((version == METRICS_VERSION_V0) ?\
244 (metrics_v0->field) : (metrics_v2->field))
245 #define GET_METRIC_FIELD(field, version) ((version == METRICS_VERSION_V1) ?\
246 (metrics_v1->field) : GET_GPU_METRIC_FIELD(field, version))
247 #define METRICS_TABLE_SIZE (max3(sizeof(MetricsTableV0_t),\
248 sizeof(MetricsTableV1_t),\
249 sizeof(MetricsTableV2_t)))
250
251 struct smu_v13_0_6_dpm_map {
252 enum smu_clk_type clk_type;
253 uint32_t feature_num;
254 struct smu_13_0_dpm_table *dpm_table;
255 uint32_t *freq_table;
256 };
257
smu_v13_0_6_get_metrics_version(struct smu_context * smu)258 static inline int smu_v13_0_6_get_metrics_version(struct smu_context *smu)
259 {
260 if ((smu->adev->flags & AMD_IS_APU) &&
261 smu->smc_fw_version <= 0x4556900)
262 return METRICS_VERSION_V1;
263 else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
264 IP_VERSION(13, 0, 12))
265 return METRICS_VERSION_V2;
266
267 return METRICS_VERSION_V0;
268 }
269
smu_v13_0_6_cap_set(struct smu_context * smu,enum smu_v13_0_6_caps cap)270 static inline void smu_v13_0_6_cap_set(struct smu_context *smu,
271 enum smu_v13_0_6_caps cap)
272 {
273 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
274
275 dpm_context->caps |= BIT_ULL(cap);
276 }
277
smu_v13_0_6_cap_clear(struct smu_context * smu,enum smu_v13_0_6_caps cap)278 static inline void smu_v13_0_6_cap_clear(struct smu_context *smu,
279 enum smu_v13_0_6_caps cap)
280 {
281 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
282
283 dpm_context->caps &= ~BIT_ULL(cap);
284 }
285
smu_v13_0_6_cap_supported(struct smu_context * smu,enum smu_v13_0_6_caps cap)286 bool smu_v13_0_6_cap_supported(struct smu_context *smu,
287 enum smu_v13_0_6_caps cap)
288 {
289 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
290
291 return !!(dpm_context->caps & BIT_ULL(cap));
292 }
293
smu_v13_0_14_init_caps(struct smu_context * smu)294 static void smu_v13_0_14_init_caps(struct smu_context *smu)
295 {
296 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
297 SMU_CAP(SET_UCLK_MAX),
298 SMU_CAP(DPM_POLICY),
299 SMU_CAP(PCIE_METRICS),
300 SMU_CAP(CTF_LIMIT),
301 SMU_CAP(MCA_DEBUG_MODE),
302 SMU_CAP(RMA_MSG),
303 SMU_CAP(ACA_SYND) };
304 uint32_t fw_ver = smu->smc_fw_version;
305
306 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
307 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
308
309 if (fw_ver >= 0x05550E00)
310 smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));
311 if (fw_ver >= 0x05550B00)
312 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
313 if (fw_ver >= 0x5551200)
314 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
315 if (fw_ver >= 0x5551600) {
316 smu_v13_0_6_cap_set(smu, SMU_CAP(STATIC_METRICS));
317 smu_v13_0_6_cap_set(smu, SMU_CAP(BOARD_VOLTAGE));
318 smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
319 }
320 }
321
smu_v13_0_12_init_caps(struct smu_context * smu)322 static void smu_v13_0_12_init_caps(struct smu_context *smu)
323 {
324 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
325 SMU_CAP(PCIE_METRICS),
326 SMU_CAP(CTF_LIMIT),
327 SMU_CAP(MCA_DEBUG_MODE),
328 SMU_CAP(RMA_MSG),
329 SMU_CAP(ACA_SYND),
330 SMU_CAP(OTHER_END_METRICS),
331 SMU_CAP(PER_INST_METRICS) };
332 uint32_t fw_ver = smu->smc_fw_version;
333
334 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
335 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
336
337 if (fw_ver < 0x00561900)
338 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM));
339
340 if (fw_ver >= 0x00561700)
341 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
342
343 if (fw_ver >= 0x00561E00)
344 smu_v13_0_6_cap_set(smu, SMU_CAP(STATIC_METRICS));
345
346 if (fw_ver >= 0x00562500)
347 smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
348 }
349
smu_v13_0_6_init_caps(struct smu_context * smu)350 static void smu_v13_0_6_init_caps(struct smu_context *smu)
351 {
352 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
353 SMU_CAP(SET_UCLK_MAX),
354 SMU_CAP(DPM_POLICY),
355 SMU_CAP(PCIE_METRICS),
356 SMU_CAP(CTF_LIMIT),
357 SMU_CAP(MCA_DEBUG_MODE),
358 SMU_CAP(RMA_MSG),
359 SMU_CAP(ACA_SYND) };
360 struct amdgpu_device *adev = smu->adev;
361 uint32_t fw_ver = smu->smc_fw_version;
362 uint32_t pgm = (fw_ver >> 24) & 0xFF;
363
364 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
365 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
366
367 if (fw_ver < 0x552F00)
368 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM));
369 if (fw_ver < 0x554500)
370 smu_v13_0_6_cap_clear(smu, SMU_CAP(CTF_LIMIT));
371
372 if (adev->flags & AMD_IS_APU) {
373 smu_v13_0_6_cap_clear(smu, SMU_CAP(PCIE_METRICS));
374 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM_POLICY));
375 smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
376 smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
377
378 if (fw_ver >= 0x04556A00)
379 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
380 } else {
381 if (fw_ver >= 0x557600)
382 smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));
383 if (fw_ver < 0x00556000)
384 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM_POLICY));
385 if (amdgpu_sriov_vf(adev) && (fw_ver < 0x556600))
386 smu_v13_0_6_cap_clear(smu, SMU_CAP(SET_UCLK_MAX));
387 if (fw_ver < 0x556300)
388 smu_v13_0_6_cap_clear(smu, SMU_CAP(PCIE_METRICS));
389 if (fw_ver < 0x554800)
390 smu_v13_0_6_cap_clear(smu, SMU_CAP(MCA_DEBUG_MODE));
391 if (fw_ver >= 0x556F00)
392 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
393 if (fw_ver < 0x00555a00)
394 smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
395 if (fw_ver < 0x00555600)
396 smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
397 if ((pgm == 7 && fw_ver >= 0x7550E00) ||
398 (pgm == 0 && fw_ver >= 0x00557E00))
399 smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
400 if ((pgm == 0 && fw_ver >= 0x00557F01) ||
401 (pgm == 7 && fw_ver >= 0x7551000)) {
402 smu_v13_0_6_cap_set(smu, SMU_CAP(STATIC_METRICS));
403 smu_v13_0_6_cap_set(smu, SMU_CAP(BOARD_VOLTAGE));
404 }
405 if ((pgm == 0 && fw_ver >= 0x00558000) ||
406 (pgm == 7 && fw_ver >= 0x7551000))
407 smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
408 }
409 if (((pgm == 7) && (fw_ver >= 0x7550700)) ||
410 ((pgm == 0) && (fw_ver >= 0x00557900)) ||
411 ((pgm == 4) && (fw_ver >= 0x4557000)))
412 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
413 }
414
smu_v13_0_x_init_caps(struct smu_context * smu)415 static void smu_v13_0_x_init_caps(struct smu_context *smu)
416 {
417 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
418 case IP_VERSION(13, 0, 12):
419 return smu_v13_0_12_init_caps(smu);
420 case IP_VERSION(13, 0, 14):
421 return smu_v13_0_14_init_caps(smu);
422 default:
423 return smu_v13_0_6_init_caps(smu);
424 }
425 }
426
smu_v13_0_6_check_fw_version(struct smu_context * smu)427 static int smu_v13_0_6_check_fw_version(struct smu_context *smu)
428 {
429 int r;
430
431 r = smu_v13_0_check_fw_version(smu);
432 /* Initialize caps flags once fw version is fetched */
433 if (!r)
434 smu_v13_0_x_init_caps(smu);
435
436 return r;
437 }
438
smu_v13_0_6_init_microcode(struct smu_context * smu)439 static int smu_v13_0_6_init_microcode(struct smu_context *smu)
440 {
441 const struct smc_firmware_header_v2_1 *v2_1;
442 const struct common_firmware_header *hdr;
443 struct amdgpu_firmware_info *ucode = NULL;
444 struct smc_soft_pptable_entry *entries;
445 struct amdgpu_device *adev = smu->adev;
446 uint32_t p2s_table_id = P2S_TABLE_ID_A;
447 int ret = 0, i, p2stable_count;
448 int var = (adev->pdev->device & 0xF);
449 char ucode_prefix[15];
450
451 /* No need to load P2S tables in IOV mode or for smu v13.0.12 */
452 if (amdgpu_sriov_vf(adev) ||
453 (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)))
454 return 0;
455
456 if (!(adev->flags & AMD_IS_APU)) {
457 p2s_table_id = P2S_TABLE_ID_X;
458 if (var == 0x5)
459 p2s_table_id = P2S_TABLE_ID_3;
460 }
461
462 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix,
463 sizeof(ucode_prefix));
464 ret = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
465 "amdgpu/%s.bin", ucode_prefix);
466 if (ret)
467 goto out;
468
469 hdr = (const struct common_firmware_header *)adev->pm.fw->data;
470 amdgpu_ucode_print_smc_hdr(hdr);
471
472 /* SMU v13.0.6 binary file doesn't carry pptables, instead the entries
473 * are used to carry p2s tables.
474 */
475 v2_1 = (const struct smc_firmware_header_v2_1 *)adev->pm.fw->data;
476 entries = (struct smc_soft_pptable_entry
477 *)((uint8_t *)v2_1 +
478 le32_to_cpu(v2_1->pptable_entry_offset));
479 p2stable_count = le32_to_cpu(v2_1->pptable_count);
480 for (i = 0; i < p2stable_count; i++) {
481 if (le32_to_cpu(entries[i].id) == p2s_table_id) {
482 smu->pptable_firmware.data =
483 ((uint8_t *)v2_1 +
484 le32_to_cpu(entries[i].ppt_offset_bytes));
485 smu->pptable_firmware.size =
486 le32_to_cpu(entries[i].ppt_size_bytes);
487 break;
488 }
489 }
490
491 if (smu->pptable_firmware.data && smu->pptable_firmware.size) {
492 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE];
493 ucode->ucode_id = AMDGPU_UCODE_ID_P2S_TABLE;
494 ucode->fw = &smu->pptable_firmware;
495 adev->firmware.fw_size += ALIGN(ucode->fw->size, PAGE_SIZE);
496 }
497
498 return 0;
499 out:
500 amdgpu_ucode_release(&adev->pm.fw);
501
502 return ret;
503 }
504
smu_v13_0_6_tables_init(struct smu_context * smu)505 static int smu_v13_0_6_tables_init(struct smu_context *smu)
506 {
507 struct smu_table_context *smu_table = &smu->smu_table;
508 struct smu_table *tables = smu_table->tables;
509 struct amdgpu_device *adev = smu->adev;
510 int gpu_metrcs_size = METRICS_TABLE_SIZE;
511
512 if (!(adev->flags & AMD_IS_APU))
513 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
514 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
515
516 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS,
517 max(gpu_metrcs_size,
518 smu_v13_0_12_get_max_metrics_size()),
519 PAGE_SIZE,
520 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
521
522 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
523 PAGE_SIZE,
524 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
525
526 smu_table->metrics_table = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
527 if (!smu_table->metrics_table)
528 return -ENOMEM;
529 smu_table->metrics_time = 0;
530
531 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_8);
532 smu_table->gpu_metrics_table =
533 kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
534 if (!smu_table->gpu_metrics_table) {
535 kfree(smu_table->metrics_table);
536 return -ENOMEM;
537 }
538
539 smu_table->driver_pptable =
540 kzalloc(sizeof(struct PPTable_t), GFP_KERNEL);
541 if (!smu_table->driver_pptable) {
542 kfree(smu_table->metrics_table);
543 kfree(smu_table->gpu_metrics_table);
544 return -ENOMEM;
545 }
546
547 return 0;
548 }
549
smu_v13_0_6_select_policy_soc_pstate(struct smu_context * smu,int policy)550 static int smu_v13_0_6_select_policy_soc_pstate(struct smu_context *smu,
551 int policy)
552 {
553 struct amdgpu_device *adev = smu->adev;
554 int ret, param;
555
556 switch (policy) {
557 case SOC_PSTATE_DEFAULT:
558 param = 0;
559 break;
560 case SOC_PSTATE_0:
561 param = 1;
562 break;
563 case SOC_PSTATE_1:
564 param = 2;
565 break;
566 case SOC_PSTATE_2:
567 param = 3;
568 break;
569 default:
570 return -EINVAL;
571 }
572
573 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetThrottlingPolicy,
574 param, NULL);
575
576 if (ret)
577 dev_err(adev->dev, "select soc pstate policy %d failed",
578 policy);
579
580 return ret;
581 }
582
smu_v13_0_6_select_plpd_policy(struct smu_context * smu,int level)583 static int smu_v13_0_6_select_plpd_policy(struct smu_context *smu, int level)
584 {
585 struct amdgpu_device *adev = smu->adev;
586 int ret, param;
587
588 switch (level) {
589 case XGMI_PLPD_DEFAULT:
590 param = PPSMC_PLPD_MODE_DEFAULT;
591 break;
592 case XGMI_PLPD_OPTIMIZED:
593 param = PPSMC_PLPD_MODE_OPTIMIZED;
594 break;
595 case XGMI_PLPD_DISALLOW:
596 param = 0;
597 break;
598 default:
599 return -EINVAL;
600 }
601
602 if (level == XGMI_PLPD_DISALLOW)
603 ret = smu_cmn_send_smc_msg_with_param(
604 smu, SMU_MSG_GmiPwrDnControl, param, NULL);
605 else
606 /* change xgmi per-link power down policy */
607 ret = smu_cmn_send_smc_msg_with_param(
608 smu, SMU_MSG_SelectPLPDMode, param, NULL);
609
610 if (ret)
611 dev_err(adev->dev,
612 "select xgmi per-link power down policy %d failed\n",
613 level);
614
615 return ret;
616 }
617
smu_v13_0_6_allocate_dpm_context(struct smu_context * smu)618 static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu)
619 {
620 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
621 struct smu_dpm_policy *policy;
622
623 smu_dpm->dpm_context =
624 kzalloc(sizeof(struct smu_13_0_dpm_context), GFP_KERNEL);
625 if (!smu_dpm->dpm_context)
626 return -ENOMEM;
627 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
628
629 smu_dpm->dpm_policies =
630 kzalloc(sizeof(struct smu_dpm_policy_ctxt), GFP_KERNEL);
631 if (!smu_dpm->dpm_policies) {
632 kfree(smu_dpm->dpm_context);
633 return -ENOMEM;
634 }
635
636 if (!(smu->adev->flags & AMD_IS_APU)) {
637 policy = &(smu_dpm->dpm_policies->policies[0]);
638
639 policy->policy_type = PP_PM_POLICY_SOC_PSTATE;
640 policy->level_mask = BIT(SOC_PSTATE_DEFAULT) |
641 BIT(SOC_PSTATE_0) | BIT(SOC_PSTATE_1) |
642 BIT(SOC_PSTATE_2);
643 policy->current_level = SOC_PSTATE_DEFAULT;
644 policy->set_policy = smu_v13_0_6_select_policy_soc_pstate;
645 smu_cmn_generic_soc_policy_desc(policy);
646 smu_dpm->dpm_policies->policy_mask |=
647 BIT(PP_PM_POLICY_SOC_PSTATE);
648 }
649 policy = &(smu_dpm->dpm_policies->policies[1]);
650
651 policy->policy_type = PP_PM_POLICY_XGMI_PLPD;
652 policy->level_mask = BIT(XGMI_PLPD_DISALLOW) | BIT(XGMI_PLPD_DEFAULT) |
653 BIT(XGMI_PLPD_OPTIMIZED);
654 policy->current_level = XGMI_PLPD_DEFAULT;
655 policy->set_policy = smu_v13_0_6_select_plpd_policy;
656 smu_cmn_generic_plpd_policy_desc(policy);
657 smu_dpm->dpm_policies->policy_mask |= BIT(PP_PM_POLICY_XGMI_PLPD);
658
659 return 0;
660 }
661
smu_v13_0_6_init_smc_tables(struct smu_context * smu)662 static int smu_v13_0_6_init_smc_tables(struct smu_context *smu)
663 {
664 int ret = 0;
665
666 ret = smu_v13_0_6_tables_init(smu);
667 if (ret)
668 return ret;
669
670 ret = smu_v13_0_6_allocate_dpm_context(smu);
671
672 return ret;
673 }
674
smu_v13_0_6_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)675 static int smu_v13_0_6_get_allowed_feature_mask(struct smu_context *smu,
676 uint32_t *feature_mask,
677 uint32_t num)
678 {
679 if (num > 2)
680 return -EINVAL;
681
682 /* pptable will handle the features to enable */
683 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
684
685 return 0;
686 }
687
smu_v13_0_6_get_metrics_table(struct smu_context * smu,void * metrics_table,bool bypass_cache)688 static int smu_v13_0_6_get_metrics_table(struct smu_context *smu,
689 void *metrics_table, bool bypass_cache)
690 {
691 struct smu_table_context *smu_table = &smu->smu_table;
692 uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size;
693 struct smu_table *table = &smu_table->driver_table;
694 int ret;
695
696 if (bypass_cache || !smu_table->metrics_time ||
697 time_after(jiffies,
698 smu_table->metrics_time + msecs_to_jiffies(1))) {
699 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsTable, NULL);
700 if (ret) {
701 dev_info(smu->adev->dev,
702 "Failed to export SMU metrics table!\n");
703 return ret;
704 }
705
706 amdgpu_asic_invalidate_hdp(smu->adev, NULL);
707 memcpy(smu_table->metrics_table, table->cpu_addr, table_size);
708
709 smu_table->metrics_time = jiffies;
710 }
711
712 if (metrics_table)
713 memcpy(metrics_table, smu_table->metrics_table, table_size);
714
715 return 0;
716 }
717
smu_v13_0_6_get_pm_metrics(struct smu_context * smu,void * metrics,size_t max_size)718 static ssize_t smu_v13_0_6_get_pm_metrics(struct smu_context *smu,
719 void *metrics, size_t max_size)
720 {
721 struct smu_table_context *smu_tbl_ctxt = &smu->smu_table;
722 uint32_t table_version = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].version;
723 uint32_t table_size = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].size;
724 struct amdgpu_pm_metrics *pm_metrics = metrics;
725 uint32_t pmfw_version;
726 int ret;
727
728 if (!pm_metrics || !max_size)
729 return -EINVAL;
730
731 if (max_size < (table_size + sizeof(pm_metrics->common_header)))
732 return -EOVERFLOW;
733
734 /* Don't use cached metrics data */
735 ret = smu_v13_0_6_get_metrics_table(smu, pm_metrics->data, true);
736 if (ret)
737 return ret;
738
739 smu_cmn_get_smc_version(smu, NULL, &pmfw_version);
740
741 memset(&pm_metrics->common_header, 0,
742 sizeof(pm_metrics->common_header));
743 pm_metrics->common_header.mp1_ip_discovery_version =
744 amdgpu_ip_version(smu->adev, MP1_HWIP, 0);
745 pm_metrics->common_header.pmfw_version = pmfw_version;
746 pm_metrics->common_header.pmmetrics_version = table_version;
747 pm_metrics->common_header.structure_size =
748 sizeof(pm_metrics->common_header) + table_size;
749
750 return pm_metrics->common_header.structure_size;
751 }
752
smu_v13_0_6_fill_static_metrics_table(struct smu_context * smu,StaticMetricsTable_t * static_metrics)753 static void smu_v13_0_6_fill_static_metrics_table(struct smu_context *smu,
754 StaticMetricsTable_t *static_metrics)
755 {
756 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
757
758 if (!static_metrics->InputTelemetryVoltageInmV) {
759 dev_warn(smu->adev->dev, "Invalid board voltage %d\n",
760 static_metrics->InputTelemetryVoltageInmV);
761 }
762
763 dpm_context->board_volt = static_metrics->InputTelemetryVoltageInmV;
764
765 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PLDM_VERSION)) &&
766 static_metrics->pldmVersion[0] != 0xFFFFFFFF)
767 smu->adev->firmware.pldm_version =
768 static_metrics->pldmVersion[0];
769 }
770
smu_v13_0_6_get_static_metrics_table(struct smu_context * smu)771 int smu_v13_0_6_get_static_metrics_table(struct smu_context *smu)
772 {
773 struct smu_table_context *smu_table = &smu->smu_table;
774 uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size;
775 struct smu_table *table = &smu_table->driver_table;
776 int ret;
777
778 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetStaticMetricsTable, NULL);
779 if (ret) {
780 dev_info(smu->adev->dev,
781 "Failed to export static metrics table!\n");
782 return ret;
783 }
784
785 amdgpu_asic_invalidate_hdp(smu->adev, NULL);
786 memcpy(smu_table->metrics_table, table->cpu_addr, table_size);
787
788 return 0;
789 }
790
smu_v13_0_6_setup_driver_pptable(struct smu_context * smu)791 static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
792 {
793 struct smu_table_context *smu_table = &smu->smu_table;
794 StaticMetricsTable_t *static_metrics = (StaticMetricsTable_t *)smu_table->metrics_table;
795 MetricsTableV0_t *metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
796 MetricsTableV1_t *metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
797 MetricsTableV2_t *metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table;
798 struct PPTable_t *pptable =
799 (struct PPTable_t *)smu_table->driver_pptable;
800 int version = smu_v13_0_6_get_metrics_version(smu);
801 int ret, i, retry = 100;
802 uint32_t table_version;
803
804 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) &&
805 smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
806 return smu_v13_0_12_setup_driver_pptable(smu);
807
808 /* Store one-time values in driver PPTable */
809 if (!pptable->Init) {
810 while (--retry) {
811 ret = smu_v13_0_6_get_metrics_table(smu, NULL, true);
812 if (ret)
813 return ret;
814
815 /* Ensure that metrics have been updated */
816 if (GET_METRIC_FIELD(AccumulationCounter, version))
817 break;
818
819 usleep_range(1000, 1100);
820 }
821
822 if (!retry)
823 return -ETIME;
824
825 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsVersion,
826 &table_version);
827 if (ret)
828 return ret;
829 smu_table->tables[SMU_TABLE_SMU_METRICS].version =
830 table_version;
831
832 pptable->MaxSocketPowerLimit =
833 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit, version));
834 pptable->MaxGfxclkFrequency =
835 SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency, version));
836 pptable->MinGfxclkFrequency =
837 SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency, version));
838
839 for (i = 0; i < 4; ++i) {
840 pptable->FclkFrequencyTable[i] =
841 SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable, version)[i]);
842 pptable->UclkFrequencyTable[i] =
843 SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable, version)[i]);
844 pptable->SocclkFrequencyTable[i] = SMUQ10_ROUND(
845 GET_METRIC_FIELD(SocclkFrequencyTable, version)[i]);
846 pptable->VclkFrequencyTable[i] =
847 SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable, version)[i]);
848 pptable->DclkFrequencyTable[i] =
849 SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable, version)[i]);
850 pptable->LclkFrequencyTable[i] =
851 SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable, version)[i]);
852 }
853
854 /* use AID0 serial number by default */
855 pptable->PublicSerialNumber_AID =
856 GET_METRIC_FIELD(PublicSerialNumber_AID, version)[0];
857
858 pptable->Init = true;
859 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) {
860 ret = smu_v13_0_6_get_static_metrics_table(smu);
861 if (ret)
862 return ret;
863 smu_v13_0_6_fill_static_metrics_table(smu, static_metrics);
864 }
865 }
866
867 return 0;
868 }
869
smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)870 static int smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context *smu,
871 enum smu_clk_type clk_type,
872 uint32_t *min, uint32_t *max)
873 {
874 struct smu_table_context *smu_table = &smu->smu_table;
875 struct PPTable_t *pptable =
876 (struct PPTable_t *)smu_table->driver_pptable;
877 uint32_t clock_limit = 0, param;
878 int ret = 0, clk_id = 0;
879
880 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
881 switch (clk_type) {
882 case SMU_MCLK:
883 case SMU_UCLK:
884 if (pptable->Init)
885 clock_limit = pptable->UclkFrequencyTable[0];
886 break;
887 case SMU_GFXCLK:
888 case SMU_SCLK:
889 if (pptable->Init)
890 clock_limit = pptable->MinGfxclkFrequency;
891 break;
892 case SMU_SOCCLK:
893 if (pptable->Init)
894 clock_limit = pptable->SocclkFrequencyTable[0];
895 break;
896 case SMU_FCLK:
897 if (pptable->Init)
898 clock_limit = pptable->FclkFrequencyTable[0];
899 break;
900 case SMU_VCLK:
901 if (pptable->Init)
902 clock_limit = pptable->VclkFrequencyTable[0];
903 break;
904 case SMU_DCLK:
905 if (pptable->Init)
906 clock_limit = pptable->DclkFrequencyTable[0];
907 break;
908 default:
909 break;
910 }
911
912 if (min)
913 *min = clock_limit;
914
915 if (max)
916 *max = clock_limit;
917
918 return 0;
919 }
920
921 if (!(clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)) {
922 clk_id = smu_cmn_to_asic_specific_index(
923 smu, CMN2ASIC_MAPPING_CLK, clk_type);
924 if (clk_id < 0) {
925 ret = -EINVAL;
926 goto failed;
927 }
928 param = (clk_id & 0xffff) << 16;
929 }
930
931 if (max) {
932 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
933 ret = smu_cmn_send_smc_msg(
934 smu, SMU_MSG_GetMaxGfxclkFrequency, max);
935 else
936 ret = smu_cmn_send_smc_msg_with_param(
937 smu, SMU_MSG_GetMaxDpmFreq, param, max);
938 if (ret)
939 goto failed;
940 }
941
942 if (min) {
943 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
944 ret = smu_cmn_send_smc_msg(
945 smu, SMU_MSG_GetMinGfxclkFrequency, min);
946 else
947 ret = smu_cmn_send_smc_msg_with_param(
948 smu, SMU_MSG_GetMinDpmFreq, param, min);
949 }
950
951 failed:
952 return ret;
953 }
954
smu_v13_0_6_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * levels)955 static int smu_v13_0_6_get_dpm_level_count(struct smu_context *smu,
956 enum smu_clk_type clk_type,
957 uint32_t *levels)
958 {
959 int ret;
960
961 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, levels);
962 if (!ret)
963 ++(*levels);
964
965 return ret;
966 }
967
smu_v13_0_6_pm_policy_init(struct smu_context * smu)968 static void smu_v13_0_6_pm_policy_init(struct smu_context *smu)
969 {
970 struct smu_dpm_policy *policy;
971
972 policy = smu_get_pm_policy(smu, PP_PM_POLICY_SOC_PSTATE);
973 if (policy)
974 policy->current_level = SOC_PSTATE_DEFAULT;
975 }
976
smu_v13_0_6_set_default_dpm_table(struct smu_context * smu)977 static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu)
978 {
979 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
980 struct smu_table_context *smu_table = &smu->smu_table;
981 struct smu_13_0_dpm_table *dpm_table = NULL;
982 struct PPTable_t *pptable =
983 (struct PPTable_t *)smu_table->driver_pptable;
984 uint32_t gfxclkmin, gfxclkmax, levels;
985 int ret = 0, i, j;
986 struct smu_v13_0_6_dpm_map dpm_map[] = {
987 { SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT,
988 &dpm_context->dpm_tables.soc_table,
989 pptable->SocclkFrequencyTable },
990 { SMU_UCLK, SMU_FEATURE_DPM_UCLK_BIT,
991 &dpm_context->dpm_tables.uclk_table,
992 pptable->UclkFrequencyTable },
993 { SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT,
994 &dpm_context->dpm_tables.fclk_table,
995 pptable->FclkFrequencyTable },
996 { SMU_VCLK, SMU_FEATURE_DPM_VCLK_BIT,
997 &dpm_context->dpm_tables.vclk_table,
998 pptable->VclkFrequencyTable },
999 { SMU_DCLK, SMU_FEATURE_DPM_DCLK_BIT,
1000 &dpm_context->dpm_tables.dclk_table,
1001 pptable->DclkFrequencyTable },
1002 };
1003
1004 smu_v13_0_6_setup_driver_pptable(smu);
1005
1006 /* DPM policy not supported in older firmwares */
1007 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM_POLICY))) {
1008 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1009
1010 smu_dpm->dpm_policies->policy_mask &=
1011 ~BIT(PP_PM_POLICY_SOC_PSTATE);
1012 }
1013
1014 smu_v13_0_6_pm_policy_init(smu);
1015 /* gfxclk dpm table setup */
1016 dpm_table = &dpm_context->dpm_tables.gfx_table;
1017 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
1018 /* In the case of gfxclk, only fine-grained dpm is honored.
1019 * Get min/max values from FW.
1020 */
1021 ret = smu_v13_0_6_get_dpm_ultimate_freq(smu, SMU_GFXCLK,
1022 &gfxclkmin, &gfxclkmax);
1023 if (ret)
1024 return ret;
1025
1026 dpm_table->count = 2;
1027 dpm_table->dpm_levels[0].value = gfxclkmin;
1028 dpm_table->dpm_levels[0].enabled = true;
1029 dpm_table->dpm_levels[1].value = gfxclkmax;
1030 dpm_table->dpm_levels[1].enabled = true;
1031 dpm_table->min = dpm_table->dpm_levels[0].value;
1032 dpm_table->max = dpm_table->dpm_levels[1].value;
1033 } else {
1034 dpm_table->count = 1;
1035 dpm_table->dpm_levels[0].value = pptable->MinGfxclkFrequency;
1036 dpm_table->dpm_levels[0].enabled = true;
1037 dpm_table->min = dpm_table->dpm_levels[0].value;
1038 dpm_table->max = dpm_table->dpm_levels[0].value;
1039 }
1040
1041 for (j = 0; j < ARRAY_SIZE(dpm_map); j++) {
1042 dpm_table = dpm_map[j].dpm_table;
1043 levels = 1;
1044 if (smu_cmn_feature_is_enabled(smu, dpm_map[j].feature_num)) {
1045 ret = smu_v13_0_6_get_dpm_level_count(
1046 smu, dpm_map[j].clk_type, &levels);
1047 if (ret)
1048 return ret;
1049 }
1050 dpm_table->count = levels;
1051 for (i = 0; i < dpm_table->count; ++i) {
1052 dpm_table->dpm_levels[i].value =
1053 dpm_map[j].freq_table[i];
1054 dpm_table->dpm_levels[i].enabled = true;
1055
1056 }
1057 dpm_table->min = dpm_table->dpm_levels[0].value;
1058 dpm_table->max = dpm_table->dpm_levels[levels - 1].value;
1059
1060 }
1061
1062 return 0;
1063 }
1064
smu_v13_0_6_setup_pptable(struct smu_context * smu)1065 static int smu_v13_0_6_setup_pptable(struct smu_context *smu)
1066 {
1067 struct smu_table_context *table_context = &smu->smu_table;
1068
1069 /* TODO: PPTable is not available.
1070 * 1) Find an alternate way to get 'PPTable values' here.
1071 * 2) Check if there is SW CTF
1072 */
1073 table_context->thermal_controller_type = 0;
1074
1075 return 0;
1076 }
1077
smu_v13_0_6_check_fw_status(struct smu_context * smu)1078 static int smu_v13_0_6_check_fw_status(struct smu_context *smu)
1079 {
1080 struct amdgpu_device *adev = smu->adev;
1081 uint32_t mp1_fw_flags;
1082
1083 mp1_fw_flags =
1084 RREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
1085
1086 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
1087 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
1088 return 0;
1089
1090 return -EIO;
1091 }
1092
smu_v13_0_6_populate_umd_state_clk(struct smu_context * smu)1093 static int smu_v13_0_6_populate_umd_state_clk(struct smu_context *smu)
1094 {
1095 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1096 struct smu_13_0_dpm_table *gfx_table =
1097 &dpm_context->dpm_tables.gfx_table;
1098 struct smu_13_0_dpm_table *mem_table =
1099 &dpm_context->dpm_tables.uclk_table;
1100 struct smu_13_0_dpm_table *soc_table =
1101 &dpm_context->dpm_tables.soc_table;
1102 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1103
1104 pstate_table->gfxclk_pstate.min = gfx_table->min;
1105 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1106 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
1107 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1108
1109 pstate_table->uclk_pstate.min = mem_table->min;
1110 pstate_table->uclk_pstate.peak = mem_table->max;
1111 pstate_table->uclk_pstate.curr.min = mem_table->min;
1112 pstate_table->uclk_pstate.curr.max = mem_table->max;
1113
1114 pstate_table->socclk_pstate.min = soc_table->min;
1115 pstate_table->socclk_pstate.peak = soc_table->max;
1116 pstate_table->socclk_pstate.curr.min = soc_table->min;
1117 pstate_table->socclk_pstate.curr.max = soc_table->max;
1118
1119 if (gfx_table->count > SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL &&
1120 mem_table->count > SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL &&
1121 soc_table->count > SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL) {
1122 pstate_table->gfxclk_pstate.standard =
1123 gfx_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL].value;
1124 pstate_table->uclk_pstate.standard =
1125 mem_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL].value;
1126 pstate_table->socclk_pstate.standard =
1127 soc_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL].value;
1128 } else {
1129 pstate_table->gfxclk_pstate.standard =
1130 pstate_table->gfxclk_pstate.min;
1131 pstate_table->uclk_pstate.standard =
1132 pstate_table->uclk_pstate.min;
1133 pstate_table->socclk_pstate.standard =
1134 pstate_table->socclk_pstate.min;
1135 }
1136
1137 return 0;
1138 }
1139
smu_v13_0_6_get_clk_table(struct smu_context * smu,struct pp_clock_levels_with_latency * clocks,struct smu_13_0_dpm_table * dpm_table)1140 static int smu_v13_0_6_get_clk_table(struct smu_context *smu,
1141 struct pp_clock_levels_with_latency *clocks,
1142 struct smu_13_0_dpm_table *dpm_table)
1143 {
1144 int i, count;
1145
1146 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS :
1147 dpm_table->count;
1148 clocks->num_levels = count;
1149
1150 for (i = 0; i < count; i++) {
1151 clocks->data[i].clocks_in_khz =
1152 dpm_table->dpm_levels[i].value * 1000;
1153 clocks->data[i].latency_in_us = 0;
1154 }
1155
1156 return 0;
1157 }
1158
smu_v13_0_6_freqs_in_same_level(int32_t frequency1,int32_t frequency2)1159 static int smu_v13_0_6_freqs_in_same_level(int32_t frequency1,
1160 int32_t frequency2)
1161 {
1162 return (abs(frequency1 - frequency2) <= EPSILON);
1163 }
1164
smu_v13_0_6_get_throttler_status(struct smu_context * smu)1165 static uint32_t smu_v13_0_6_get_throttler_status(struct smu_context *smu)
1166 {
1167 struct smu_power_context *smu_power = &smu->smu_power;
1168 struct smu_13_0_power_context *power_context = smu_power->power_context;
1169 uint32_t throttler_status = 0;
1170
1171 throttler_status = atomic_read(&power_context->throttle_status);
1172 dev_dbg(smu->adev->dev, "SMU Throttler status: %u", throttler_status);
1173
1174 return throttler_status;
1175 }
1176
smu_v13_0_6_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)1177 static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu,
1178 MetricsMember_t member,
1179 uint32_t *value)
1180 {
1181 struct smu_table_context *smu_table = &smu->smu_table;
1182 MetricsTableV0_t *metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
1183 MetricsTableV1_t *metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
1184 MetricsTableV2_t *metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table;
1185 int version = smu_v13_0_6_get_metrics_version(smu);
1186 struct amdgpu_device *adev = smu->adev;
1187 int ret = 0;
1188 int xcc_id;
1189
1190 ret = smu_v13_0_6_get_metrics_table(smu, NULL, false);
1191 if (ret)
1192 return ret;
1193
1194 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) &&
1195 smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
1196 return smu_v13_0_12_get_smu_metrics_data(smu, member, value);
1197
1198 /* For clocks with multiple instances, only report the first one */
1199 switch (member) {
1200 case METRICS_CURR_GFXCLK:
1201 case METRICS_AVERAGE_GFXCLK:
1202 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
1203 xcc_id = GET_INST(GC, 0);
1204 *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]);
1205 } else {
1206 *value = 0;
1207 }
1208 break;
1209 case METRICS_CURR_SOCCLK:
1210 case METRICS_AVERAGE_SOCCLK:
1211 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, version)[0]);
1212 break;
1213 case METRICS_CURR_UCLK:
1214 case METRICS_AVERAGE_UCLK:
1215 *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
1216 break;
1217 case METRICS_CURR_VCLK:
1218 *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, version)[0]);
1219 break;
1220 case METRICS_CURR_DCLK:
1221 *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, version)[0]);
1222 break;
1223 case METRICS_CURR_FCLK:
1224 *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency, version));
1225 break;
1226 case METRICS_AVERAGE_GFXACTIVITY:
1227 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, version));
1228 break;
1229 case METRICS_AVERAGE_MEMACTIVITY:
1230 *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, version));
1231 break;
1232 case METRICS_CURR_SOCKETPOWER:
1233 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, version)) << 8;
1234 break;
1235 case METRICS_TEMPERATURE_HOTSPOT:
1236 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version)) *
1237 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1238 break;
1239 case METRICS_TEMPERATURE_MEM:
1240 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, version)) *
1241 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1242 break;
1243 /* This is the max of all VRs and not just SOC VR.
1244 * No need to define another data type for the same.
1245 */
1246 case METRICS_TEMPERATURE_VRSOC:
1247 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, version)) *
1248 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1249 break;
1250 default:
1251 *value = UINT_MAX;
1252 break;
1253 }
1254
1255 return ret;
1256 }
1257
smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1258 static int smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context *smu,
1259 enum smu_clk_type clk_type,
1260 uint32_t *value)
1261 {
1262 MetricsMember_t member_type;
1263
1264 if (!value)
1265 return -EINVAL;
1266
1267 switch (clk_type) {
1268 case SMU_GFXCLK:
1269 member_type = METRICS_CURR_GFXCLK;
1270 break;
1271 case SMU_UCLK:
1272 member_type = METRICS_CURR_UCLK;
1273 break;
1274 case SMU_SOCCLK:
1275 member_type = METRICS_CURR_SOCCLK;
1276 break;
1277 case SMU_VCLK:
1278 member_type = METRICS_CURR_VCLK;
1279 break;
1280 case SMU_DCLK:
1281 member_type = METRICS_CURR_DCLK;
1282 break;
1283 case SMU_FCLK:
1284 member_type = METRICS_CURR_FCLK;
1285 break;
1286 default:
1287 return -EINVAL;
1288 }
1289
1290 return smu_v13_0_6_get_smu_metrics_data(smu, member_type, value);
1291 }
1292
smu_v13_0_6_print_clks(struct smu_context * smu,char * buf,int size,struct smu_13_0_dpm_table * single_dpm_table,uint32_t curr_clk,const char * clk_name)1293 static int smu_v13_0_6_print_clks(struct smu_context *smu, char *buf, int size,
1294 struct smu_13_0_dpm_table *single_dpm_table,
1295 uint32_t curr_clk, const char *clk_name)
1296 {
1297 struct pp_clock_levels_with_latency clocks;
1298 int i, ret, level = -1;
1299 uint32_t clk1, clk2;
1300
1301 ret = smu_v13_0_6_get_clk_table(smu, &clocks, single_dpm_table);
1302 if (ret) {
1303 dev_err(smu->adev->dev, "Attempt to get %s clk levels failed!",
1304 clk_name);
1305 return ret;
1306 }
1307
1308 if (!clocks.num_levels)
1309 return -EINVAL;
1310
1311 if (curr_clk < SMU_13_0_6_DSCLK_THRESHOLD) {
1312 size = sysfs_emit_at(buf, size, "S: %uMhz *\n", curr_clk);
1313 for (i = 0; i < clocks.num_levels; i++)
1314 size += sysfs_emit_at(buf, size, "%d: %uMhz\n", i,
1315 clocks.data[i].clocks_in_khz /
1316 1000);
1317
1318 } else {
1319 if ((clocks.num_levels == 1) ||
1320 (curr_clk < (clocks.data[0].clocks_in_khz / 1000)))
1321 level = 0;
1322 for (i = 0; i < clocks.num_levels; i++) {
1323 clk1 = clocks.data[i].clocks_in_khz / 1000;
1324
1325 if (i < (clocks.num_levels - 1))
1326 clk2 = clocks.data[i + 1].clocks_in_khz / 1000;
1327
1328 if (curr_clk == clk1) {
1329 level = i;
1330 } else if (curr_clk >= clk1 && curr_clk < clk2) {
1331 level = (curr_clk - clk1) <= (clk2 - curr_clk) ?
1332 i :
1333 i + 1;
1334 }
1335
1336 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
1337 clk1, (level == i) ? "*" : "");
1338 }
1339 }
1340
1341 return size;
1342 }
1343
smu_v13_0_6_print_clk_levels(struct smu_context * smu,enum smu_clk_type type,char * buf)1344 static int smu_v13_0_6_print_clk_levels(struct smu_context *smu,
1345 enum smu_clk_type type, char *buf)
1346 {
1347 int now, size = 0;
1348 int ret = 0;
1349 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1350 struct smu_13_0_dpm_table *single_dpm_table;
1351 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1352 struct smu_13_0_dpm_context *dpm_context = NULL;
1353 uint32_t min_clk, max_clk;
1354
1355 smu_cmn_get_sysfs_buf(&buf, &size);
1356
1357 if (amdgpu_ras_intr_triggered()) {
1358 size += sysfs_emit_at(buf, size, "unavailable\n");
1359 return size;
1360 }
1361
1362 dpm_context = smu_dpm->dpm_context;
1363
1364 switch (type) {
1365 case SMU_OD_SCLK:
1366 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
1367 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1368 pstate_table->gfxclk_pstate.curr.min,
1369 pstate_table->gfxclk_pstate.curr.max);
1370 break;
1371 case SMU_SCLK:
1372 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_GFXCLK,
1373 &now);
1374 if (ret) {
1375 dev_err(smu->adev->dev,
1376 "Attempt to get current gfx clk Failed!");
1377 return ret;
1378 }
1379
1380 min_clk = pstate_table->gfxclk_pstate.curr.min;
1381 max_clk = pstate_table->gfxclk_pstate.curr.max;
1382
1383 if (now < SMU_13_0_6_DSCLK_THRESHOLD) {
1384 size += sysfs_emit_at(buf, size, "S: %uMhz *\n",
1385 now);
1386 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1387 min_clk);
1388 size += sysfs_emit_at(buf, size, "1: %uMhz\n",
1389 max_clk);
1390
1391 } else if (!smu_v13_0_6_freqs_in_same_level(now, min_clk) &&
1392 !smu_v13_0_6_freqs_in_same_level(now, max_clk)) {
1393 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1394 min_clk);
1395 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1396 now);
1397 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1398 max_clk);
1399 } else {
1400 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1401 min_clk,
1402 smu_v13_0_6_freqs_in_same_level(now, min_clk) ? "*" : "");
1403 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1404 max_clk,
1405 smu_v13_0_6_freqs_in_same_level(now, max_clk) ? "*" : "");
1406 }
1407
1408 break;
1409
1410 case SMU_OD_MCLK:
1411 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SET_UCLK_MAX)))
1412 return 0;
1413
1414 size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK");
1415 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1416 pstate_table->uclk_pstate.curr.min,
1417 pstate_table->uclk_pstate.curr.max);
1418 break;
1419 case SMU_MCLK:
1420 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_UCLK,
1421 &now);
1422 if (ret) {
1423 dev_err(smu->adev->dev,
1424 "Attempt to get current mclk Failed!");
1425 return ret;
1426 }
1427
1428 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1429
1430 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1431 now, "mclk");
1432
1433 case SMU_SOCCLK:
1434 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_SOCCLK,
1435 &now);
1436 if (ret) {
1437 dev_err(smu->adev->dev,
1438 "Attempt to get current socclk Failed!");
1439 return ret;
1440 }
1441
1442 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1443
1444 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1445 now, "socclk");
1446
1447 case SMU_FCLK:
1448 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_FCLK,
1449 &now);
1450 if (ret) {
1451 dev_err(smu->adev->dev,
1452 "Attempt to get current fclk Failed!");
1453 return ret;
1454 }
1455
1456 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1457
1458 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1459 now, "fclk");
1460
1461 case SMU_VCLK:
1462 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_VCLK,
1463 &now);
1464 if (ret) {
1465 dev_err(smu->adev->dev,
1466 "Attempt to get current vclk Failed!");
1467 return ret;
1468 }
1469
1470 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1471
1472 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1473 now, "vclk");
1474
1475 case SMU_DCLK:
1476 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_DCLK,
1477 &now);
1478 if (ret) {
1479 dev_err(smu->adev->dev,
1480 "Attempt to get current dclk Failed!");
1481 return ret;
1482 }
1483
1484 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1485
1486 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1487 now, "dclk");
1488
1489 default:
1490 break;
1491 }
1492
1493 return size;
1494 }
1495
smu_v13_0_6_upload_dpm_level(struct smu_context * smu,bool max,uint32_t feature_mask,uint32_t level)1496 static int smu_v13_0_6_upload_dpm_level(struct smu_context *smu, bool max,
1497 uint32_t feature_mask, uint32_t level)
1498 {
1499 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1500 uint32_t freq;
1501 int ret = 0;
1502
1503 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1504 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK))) {
1505 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
1506 ret = smu_cmn_send_smc_msg_with_param(
1507 smu,
1508 (max ? SMU_MSG_SetSoftMaxGfxClk :
1509 SMU_MSG_SetSoftMinGfxclk),
1510 freq & 0xffff, NULL);
1511 if (ret) {
1512 dev_err(smu->adev->dev,
1513 "Failed to set soft %s gfxclk !\n",
1514 max ? "max" : "min");
1515 return ret;
1516 }
1517 }
1518
1519 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1520 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK))) {
1521 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level]
1522 .value;
1523 ret = smu_cmn_send_smc_msg_with_param(
1524 smu,
1525 (max ? SMU_MSG_SetSoftMaxByFreq :
1526 SMU_MSG_SetSoftMinByFreq),
1527 (PPCLK_UCLK << 16) | (freq & 0xffff), NULL);
1528 if (ret) {
1529 dev_err(smu->adev->dev,
1530 "Failed to set soft %s memclk !\n",
1531 max ? "max" : "min");
1532 return ret;
1533 }
1534 }
1535
1536 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1537 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK))) {
1538 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
1539 ret = smu_cmn_send_smc_msg_with_param(
1540 smu,
1541 (max ? SMU_MSG_SetSoftMaxByFreq :
1542 SMU_MSG_SetSoftMinByFreq),
1543 (PPCLK_SOCCLK << 16) | (freq & 0xffff), NULL);
1544 if (ret) {
1545 dev_err(smu->adev->dev,
1546 "Failed to set soft %s socclk !\n",
1547 max ? "max" : "min");
1548 return ret;
1549 }
1550 }
1551
1552 return ret;
1553 }
1554
smu_v13_0_6_force_clk_levels(struct smu_context * smu,enum smu_clk_type type,uint32_t mask)1555 static int smu_v13_0_6_force_clk_levels(struct smu_context *smu,
1556 enum smu_clk_type type, uint32_t mask)
1557 {
1558 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1559 struct smu_13_0_dpm_table *single_dpm_table = NULL;
1560 uint32_t soft_min_level, soft_max_level;
1561 int ret = 0;
1562
1563 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1564 soft_max_level = mask ? (fls(mask) - 1) : 0;
1565
1566 switch (type) {
1567 case SMU_SCLK:
1568 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1569 if (soft_max_level >= single_dpm_table->count) {
1570 dev_err(smu->adev->dev,
1571 "Clock level specified %d is over max allowed %d\n",
1572 soft_max_level, single_dpm_table->count - 1);
1573 ret = -EINVAL;
1574 break;
1575 }
1576
1577 ret = smu_v13_0_6_upload_dpm_level(
1578 smu, false, FEATURE_MASK(FEATURE_DPM_GFXCLK),
1579 soft_min_level);
1580 if (ret) {
1581 dev_err(smu->adev->dev,
1582 "Failed to upload boot level to lowest!\n");
1583 break;
1584 }
1585
1586 ret = smu_v13_0_6_upload_dpm_level(
1587 smu, true, FEATURE_MASK(FEATURE_DPM_GFXCLK),
1588 soft_max_level);
1589 if (ret)
1590 dev_err(smu->adev->dev,
1591 "Failed to upload dpm max level to highest!\n");
1592
1593 break;
1594
1595 case SMU_MCLK:
1596 case SMU_SOCCLK:
1597 case SMU_FCLK:
1598 /*
1599 * Should not arrive here since smu_13_0_6 does not
1600 * support mclk/socclk/fclk softmin/softmax settings
1601 */
1602 ret = -EINVAL;
1603 break;
1604
1605 default:
1606 break;
1607 }
1608
1609 return ret;
1610 }
1611
smu_v13_0_6_get_current_activity_percent(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1612 static int smu_v13_0_6_get_current_activity_percent(struct smu_context *smu,
1613 enum amd_pp_sensors sensor,
1614 uint32_t *value)
1615 {
1616 int ret = 0;
1617
1618 if (!value)
1619 return -EINVAL;
1620
1621 switch (sensor) {
1622 case AMDGPU_PP_SENSOR_GPU_LOAD:
1623 ret = smu_v13_0_6_get_smu_metrics_data(
1624 smu, METRICS_AVERAGE_GFXACTIVITY, value);
1625 break;
1626 case AMDGPU_PP_SENSOR_MEM_LOAD:
1627 ret = smu_v13_0_6_get_smu_metrics_data(
1628 smu, METRICS_AVERAGE_MEMACTIVITY, value);
1629 break;
1630 default:
1631 dev_err(smu->adev->dev,
1632 "Invalid sensor for retrieving clock activity\n");
1633 return -EINVAL;
1634 }
1635
1636 return ret;
1637 }
1638
smu_v13_0_6_thermal_get_temperature(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1639 static int smu_v13_0_6_thermal_get_temperature(struct smu_context *smu,
1640 enum amd_pp_sensors sensor,
1641 uint32_t *value)
1642 {
1643 int ret = 0;
1644
1645 if (!value)
1646 return -EINVAL;
1647
1648 switch (sensor) {
1649 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1650 ret = smu_v13_0_6_get_smu_metrics_data(
1651 smu, METRICS_TEMPERATURE_HOTSPOT, value);
1652 break;
1653 case AMDGPU_PP_SENSOR_MEM_TEMP:
1654 ret = smu_v13_0_6_get_smu_metrics_data(
1655 smu, METRICS_TEMPERATURE_MEM, value);
1656 break;
1657 default:
1658 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1659 return -EINVAL;
1660 }
1661
1662 return ret;
1663 }
1664
smu_v13_0_6_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1665 static int smu_v13_0_6_read_sensor(struct smu_context *smu,
1666 enum amd_pp_sensors sensor, void *data,
1667 uint32_t *size)
1668 {
1669 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1670 int ret = 0;
1671
1672 if (amdgpu_ras_intr_triggered())
1673 return 0;
1674
1675 if (!data || !size)
1676 return -EINVAL;
1677
1678 switch (sensor) {
1679 case AMDGPU_PP_SENSOR_MEM_LOAD:
1680 case AMDGPU_PP_SENSOR_GPU_LOAD:
1681 ret = smu_v13_0_6_get_current_activity_percent(smu, sensor,
1682 (uint32_t *)data);
1683 *size = 4;
1684 break;
1685 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1686 ret = smu_v13_0_6_get_smu_metrics_data(smu,
1687 METRICS_CURR_SOCKETPOWER,
1688 (uint32_t *)data);
1689 *size = 4;
1690 break;
1691 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1692 case AMDGPU_PP_SENSOR_MEM_TEMP:
1693 ret = smu_v13_0_6_thermal_get_temperature(smu, sensor,
1694 (uint32_t *)data);
1695 *size = 4;
1696 break;
1697 case AMDGPU_PP_SENSOR_GFX_MCLK:
1698 ret = smu_v13_0_6_get_current_clk_freq_by_table(
1699 smu, SMU_UCLK, (uint32_t *)data);
1700 /* the output clock frequency in 10K unit */
1701 *(uint32_t *)data *= 100;
1702 *size = 4;
1703 break;
1704 case AMDGPU_PP_SENSOR_GFX_SCLK:
1705 ret = smu_v13_0_6_get_current_clk_freq_by_table(
1706 smu, SMU_GFXCLK, (uint32_t *)data);
1707 *(uint32_t *)data *= 100;
1708 *size = 4;
1709 break;
1710 case AMDGPU_PP_SENSOR_VDDGFX:
1711 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1712 *size = 4;
1713 break;
1714 case AMDGPU_PP_SENSOR_VDDBOARD:
1715 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(BOARD_VOLTAGE))) {
1716 *(uint32_t *)data = dpm_context->board_volt;
1717 *size = 4;
1718 break;
1719 } else {
1720 ret = -EOPNOTSUPP;
1721 break;
1722 }
1723 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1724 default:
1725 ret = -EOPNOTSUPP;
1726 break;
1727 }
1728
1729 return ret;
1730 }
1731
smu_v13_0_6_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)1732 static int smu_v13_0_6_get_power_limit(struct smu_context *smu,
1733 uint32_t *current_power_limit,
1734 uint32_t *default_power_limit,
1735 uint32_t *max_power_limit,
1736 uint32_t *min_power_limit)
1737 {
1738 struct smu_table_context *smu_table = &smu->smu_table;
1739 struct PPTable_t *pptable =
1740 (struct PPTable_t *)smu_table->driver_pptable;
1741 uint32_t power_limit = 0;
1742 int ret;
1743
1744 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit);
1745
1746 if (ret) {
1747 dev_err(smu->adev->dev, "Couldn't get PPT limit");
1748 return -EINVAL;
1749 }
1750
1751 if (current_power_limit)
1752 *current_power_limit = power_limit;
1753 if (default_power_limit)
1754 *default_power_limit = power_limit;
1755
1756 if (max_power_limit) {
1757 *max_power_limit = pptable->MaxSocketPowerLimit;
1758 }
1759
1760 if (min_power_limit)
1761 *min_power_limit = 0;
1762 return 0;
1763 }
1764
smu_v13_0_6_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)1765 static int smu_v13_0_6_set_power_limit(struct smu_context *smu,
1766 enum smu_ppt_limit_type limit_type,
1767 uint32_t limit)
1768 {
1769 return smu_v13_0_set_power_limit(smu, limit_type, limit);
1770 }
1771
smu_v13_0_6_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1772 static int smu_v13_0_6_irq_process(struct amdgpu_device *adev,
1773 struct amdgpu_irq_src *source,
1774 struct amdgpu_iv_entry *entry)
1775 {
1776 struct smu_context *smu = adev->powerplay.pp_handle;
1777 struct smu_power_context *smu_power = &smu->smu_power;
1778 struct smu_13_0_power_context *power_context = smu_power->power_context;
1779 uint32_t client_id = entry->client_id;
1780 uint32_t ctxid = entry->src_data[0];
1781 uint32_t src_id = entry->src_id;
1782 uint32_t data;
1783
1784 if (client_id == SOC15_IH_CLIENTID_MP1) {
1785 if (src_id == IH_INTERRUPT_ID_TO_DRIVER) {
1786 /* ACK SMUToHost interrupt */
1787 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1788 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1789 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1790 /*
1791 * ctxid is used to distinguish different events for SMCToHost
1792 * interrupt.
1793 */
1794 switch (ctxid) {
1795 case IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1796 /*
1797 * Increment the throttle interrupt counter
1798 */
1799 atomic64_inc(&smu->throttle_int_counter);
1800
1801 if (!atomic_read(&adev->throttling_logging_enabled))
1802 return 0;
1803
1804 /* This uses the new method which fixes the
1805 * incorrect throttling status reporting
1806 * through metrics table. For older FWs,
1807 * it will be ignored.
1808 */
1809 if (__ratelimit(&adev->throttling_logging_rs)) {
1810 atomic_set(
1811 &power_context->throttle_status,
1812 entry->src_data[1]);
1813 schedule_work(&smu->throttling_logging_work);
1814 }
1815 break;
1816 default:
1817 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1818 ctxid, client_id);
1819 break;
1820 }
1821 }
1822 }
1823
1824 return 0;
1825 }
1826
smu_v13_0_6_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1827 static int smu_v13_0_6_set_irq_state(struct amdgpu_device *adev,
1828 struct amdgpu_irq_src *source,
1829 unsigned tyep,
1830 enum amdgpu_interrupt_state state)
1831 {
1832 uint32_t val = 0;
1833
1834 switch (state) {
1835 case AMDGPU_IRQ_STATE_DISABLE:
1836 /* For MP1 SW irqs */
1837 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1838 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1839 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1840
1841 break;
1842 case AMDGPU_IRQ_STATE_ENABLE:
1843 /* For MP1 SW irqs */
1844 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1845 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1846 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1847 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1848
1849 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1850 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1851 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1852
1853 break;
1854 default:
1855 break;
1856 }
1857
1858 return 0;
1859 }
1860
1861 static const struct amdgpu_irq_src_funcs smu_v13_0_6_irq_funcs = {
1862 .set = smu_v13_0_6_set_irq_state,
1863 .process = smu_v13_0_6_irq_process,
1864 };
1865
smu_v13_0_6_register_irq_handler(struct smu_context * smu)1866 static int smu_v13_0_6_register_irq_handler(struct smu_context *smu)
1867 {
1868 struct amdgpu_device *adev = smu->adev;
1869 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1870 int ret = 0;
1871
1872 if (amdgpu_sriov_vf(adev))
1873 return 0;
1874
1875 irq_src->num_types = 1;
1876 irq_src->funcs = &smu_v13_0_6_irq_funcs;
1877
1878 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1879 IH_INTERRUPT_ID_TO_DRIVER,
1880 irq_src);
1881 if (ret)
1882 return ret;
1883
1884 return ret;
1885 }
1886
smu_v13_0_6_notify_unload(struct smu_context * smu)1887 static int smu_v13_0_6_notify_unload(struct smu_context *smu)
1888 {
1889 if (amdgpu_in_reset(smu->adev))
1890 return 0;
1891
1892 dev_dbg(smu->adev->dev, "Notify PMFW about driver unload");
1893 /* Ignore return, just intimate FW that driver is not going to be there */
1894 smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
1895
1896 return 0;
1897 }
1898
smu_v13_0_6_mca_set_debug_mode(struct smu_context * smu,bool enable)1899 static int smu_v13_0_6_mca_set_debug_mode(struct smu_context *smu, bool enable)
1900 {
1901 /* NOTE: this ClearMcaOnRead message is only supported for smu version 85.72.0 or higher */
1902 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(MCA_DEBUG_MODE)))
1903 return 0;
1904
1905 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ClearMcaOnRead,
1906 enable ? 0 : ClearMcaOnRead_UE_FLAG_MASK | ClearMcaOnRead_CE_POLL_MASK,
1907 NULL);
1908 }
1909
smu_v13_0_6_system_features_control(struct smu_context * smu,bool enable)1910 static int smu_v13_0_6_system_features_control(struct smu_context *smu,
1911 bool enable)
1912 {
1913 struct amdgpu_device *adev = smu->adev;
1914 int ret = 0;
1915
1916 if (amdgpu_sriov_vf(adev))
1917 return 0;
1918
1919 if (enable) {
1920 if (!(adev->flags & AMD_IS_APU))
1921 ret = smu_v13_0_system_features_control(smu, enable);
1922 } else {
1923 /* Notify FW that the device is no longer driver managed */
1924 smu_v13_0_6_notify_unload(smu);
1925 }
1926
1927 return ret;
1928 }
1929
smu_v13_0_6_set_gfx_soft_freq_limited_range(struct smu_context * smu,uint32_t min,uint32_t max)1930 static int smu_v13_0_6_set_gfx_soft_freq_limited_range(struct smu_context *smu,
1931 uint32_t min,
1932 uint32_t max)
1933 {
1934 int ret;
1935
1936 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1937 max & 0xffff, NULL);
1938 if (ret)
1939 return ret;
1940
1941 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinGfxclk,
1942 min & 0xffff, NULL);
1943
1944 return ret;
1945 }
1946
smu_v13_0_6_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1947 static int smu_v13_0_6_set_performance_level(struct smu_context *smu,
1948 enum amd_dpm_forced_level level)
1949 {
1950 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1951 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1952 struct smu_13_0_dpm_table *gfx_table =
1953 &dpm_context->dpm_tables.gfx_table;
1954 struct smu_13_0_dpm_table *uclk_table =
1955 &dpm_context->dpm_tables.uclk_table;
1956 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1957 int ret;
1958
1959 /* Disable determinism if switching to another mode */
1960 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1961 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1962 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1963 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1964 }
1965
1966 switch (level) {
1967 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1968 return 0;
1969
1970 case AMD_DPM_FORCED_LEVEL_AUTO:
1971 if ((gfx_table->min != pstate_table->gfxclk_pstate.curr.min) ||
1972 (gfx_table->max != pstate_table->gfxclk_pstate.curr.max)) {
1973 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(
1974 smu, gfx_table->min, gfx_table->max);
1975 if (ret)
1976 return ret;
1977
1978 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
1979 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1980 }
1981
1982 if (uclk_table->max != pstate_table->uclk_pstate.curr.max) {
1983 /* Min UCLK is not expected to be changed */
1984 ret = smu_v13_0_set_soft_freq_limited_range(
1985 smu, SMU_UCLK, 0, uclk_table->max, false);
1986 if (ret)
1987 return ret;
1988 pstate_table->uclk_pstate.curr.max = uclk_table->max;
1989 }
1990 smu_v13_0_reset_custom_level(smu);
1991
1992 return 0;
1993 case AMD_DPM_FORCED_LEVEL_MANUAL:
1994 return 0;
1995 default:
1996 break;
1997 }
1998
1999 return -EOPNOTSUPP;
2000 }
2001
smu_v13_0_6_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)2002 static int smu_v13_0_6_set_soft_freq_limited_range(struct smu_context *smu,
2003 enum smu_clk_type clk_type,
2004 uint32_t min, uint32_t max,
2005 bool automatic)
2006 {
2007 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2008 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
2009 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
2010 struct amdgpu_device *adev = smu->adev;
2011 uint32_t min_clk;
2012 uint32_t max_clk;
2013 int ret = 0;
2014
2015 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK &&
2016 clk_type != SMU_UCLK)
2017 return -EINVAL;
2018
2019 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
2020 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
2021 return -EINVAL;
2022
2023 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
2024 if (min >= max) {
2025 dev_err(smu->adev->dev,
2026 "Minimum clk should be less than the maximum allowed clock\n");
2027 return -EINVAL;
2028 }
2029
2030 if (clk_type == SMU_GFXCLK) {
2031 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
2032 (max == pstate_table->gfxclk_pstate.curr.max))
2033 return 0;
2034
2035 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(
2036 smu, min, max);
2037 if (!ret) {
2038 pstate_table->gfxclk_pstate.curr.min = min;
2039 pstate_table->gfxclk_pstate.curr.max = max;
2040 }
2041 }
2042
2043 if (clk_type == SMU_UCLK) {
2044 if (max == pstate_table->uclk_pstate.curr.max)
2045 return 0;
2046 /* For VF, only allowed in FW versions 85.102 or greater */
2047 if (!smu_v13_0_6_cap_supported(smu,
2048 SMU_CAP(SET_UCLK_MAX)))
2049 return -EOPNOTSUPP;
2050 /* Only max clock limiting is allowed for UCLK */
2051 ret = smu_v13_0_set_soft_freq_limited_range(
2052 smu, SMU_UCLK, 0, max, false);
2053 if (!ret)
2054 pstate_table->uclk_pstate.curr.max = max;
2055 }
2056
2057 return ret;
2058 }
2059
2060 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2061 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
2062 (max > dpm_context->dpm_tables.gfx_table.max)) {
2063 dev_warn(
2064 adev->dev,
2065 "Invalid max frequency %d MHz specified for determinism\n",
2066 max);
2067 return -EINVAL;
2068 }
2069
2070 /* Restore default min/max clocks and enable determinism */
2071 min_clk = dpm_context->dpm_tables.gfx_table.min;
2072 max_clk = dpm_context->dpm_tables.gfx_table.max;
2073 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(smu, min_clk,
2074 max_clk);
2075 if (!ret) {
2076 usleep_range(500, 1000);
2077 ret = smu_cmn_send_smc_msg_with_param(
2078 smu, SMU_MSG_EnableDeterminism, max, NULL);
2079 if (ret) {
2080 dev_err(adev->dev,
2081 "Failed to enable determinism at GFX clock %d MHz\n",
2082 max);
2083 } else {
2084 pstate_table->gfxclk_pstate.curr.min = min_clk;
2085 pstate_table->gfxclk_pstate.curr.max = max;
2086 }
2087 }
2088 }
2089
2090 return ret;
2091 }
2092
smu_v13_0_6_usr_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2093 static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu,
2094 enum PP_OD_DPM_TABLE_COMMAND type,
2095 long input[], uint32_t size)
2096 {
2097 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2098 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
2099 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
2100 uint32_t min_clk;
2101 uint32_t max_clk;
2102 int ret = 0;
2103
2104 /* Only allowed in manual or determinism mode */
2105 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
2106 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
2107 return -EINVAL;
2108
2109 switch (type) {
2110 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2111 if (size != 2) {
2112 dev_err(smu->adev->dev,
2113 "Input parameter number not correct\n");
2114 return -EINVAL;
2115 }
2116
2117 if (input[0] == 0) {
2118 if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
2119 dev_warn(
2120 smu->adev->dev,
2121 "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
2122 input[1],
2123 dpm_context->dpm_tables.gfx_table.min);
2124 pstate_table->gfxclk_pstate.custom.min =
2125 pstate_table->gfxclk_pstate.curr.min;
2126 return -EINVAL;
2127 }
2128
2129 pstate_table->gfxclk_pstate.custom.min = input[1];
2130 } else if (input[0] == 1) {
2131 if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
2132 dev_warn(
2133 smu->adev->dev,
2134 "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
2135 input[1],
2136 dpm_context->dpm_tables.gfx_table.max);
2137 pstate_table->gfxclk_pstate.custom.max =
2138 pstate_table->gfxclk_pstate.curr.max;
2139 return -EINVAL;
2140 }
2141
2142 pstate_table->gfxclk_pstate.custom.max = input[1];
2143 } else {
2144 return -EINVAL;
2145 }
2146 break;
2147 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2148 if (size != 2) {
2149 dev_err(smu->adev->dev,
2150 "Input parameter number not correct\n");
2151 return -EINVAL;
2152 }
2153
2154 if (!smu_cmn_feature_is_enabled(smu,
2155 SMU_FEATURE_DPM_UCLK_BIT)) {
2156 dev_warn(smu->adev->dev,
2157 "UCLK_LIMITS setting not supported!\n");
2158 return -EOPNOTSUPP;
2159 }
2160
2161 if (input[0] == 0) {
2162 dev_info(smu->adev->dev,
2163 "Setting min UCLK level is not supported");
2164 return -EINVAL;
2165 } else if (input[0] == 1) {
2166 if (input[1] > dpm_context->dpm_tables.uclk_table.max) {
2167 dev_warn(
2168 smu->adev->dev,
2169 "Maximum UCLK (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
2170 input[1],
2171 dpm_context->dpm_tables.uclk_table.max);
2172 pstate_table->uclk_pstate.custom.max =
2173 pstate_table->uclk_pstate.curr.max;
2174 return -EINVAL;
2175 }
2176
2177 pstate_table->uclk_pstate.custom.max = input[1];
2178 }
2179 break;
2180
2181 case PP_OD_RESTORE_DEFAULT_TABLE:
2182 if (size != 0) {
2183 dev_err(smu->adev->dev,
2184 "Input parameter number not correct\n");
2185 return -EINVAL;
2186 } else {
2187 /* Use the default frequencies for manual and determinism mode */
2188 min_clk = dpm_context->dpm_tables.gfx_table.min;
2189 max_clk = dpm_context->dpm_tables.gfx_table.max;
2190
2191 ret = smu_v13_0_6_set_soft_freq_limited_range(
2192 smu, SMU_GFXCLK, min_clk, max_clk, false);
2193
2194 if (ret)
2195 return ret;
2196
2197 min_clk = dpm_context->dpm_tables.uclk_table.min;
2198 max_clk = dpm_context->dpm_tables.uclk_table.max;
2199 ret = smu_v13_0_6_set_soft_freq_limited_range(
2200 smu, SMU_UCLK, min_clk, max_clk, false);
2201 if (ret)
2202 return ret;
2203 smu_v13_0_reset_custom_level(smu);
2204 }
2205 break;
2206 case PP_OD_COMMIT_DPM_TABLE:
2207 if (size != 0) {
2208 dev_err(smu->adev->dev,
2209 "Input parameter number not correct\n");
2210 return -EINVAL;
2211 } else {
2212 if (!pstate_table->gfxclk_pstate.custom.min)
2213 pstate_table->gfxclk_pstate.custom.min =
2214 pstate_table->gfxclk_pstate.curr.min;
2215
2216 if (!pstate_table->gfxclk_pstate.custom.max)
2217 pstate_table->gfxclk_pstate.custom.max =
2218 pstate_table->gfxclk_pstate.curr.max;
2219
2220 min_clk = pstate_table->gfxclk_pstate.custom.min;
2221 max_clk = pstate_table->gfxclk_pstate.custom.max;
2222
2223 ret = smu_v13_0_6_set_soft_freq_limited_range(
2224 smu, SMU_GFXCLK, min_clk, max_clk, false);
2225
2226 if (ret)
2227 return ret;
2228
2229 if (!pstate_table->uclk_pstate.custom.max)
2230 return 0;
2231
2232 min_clk = pstate_table->uclk_pstate.curr.min;
2233 max_clk = pstate_table->uclk_pstate.custom.max;
2234 return smu_v13_0_6_set_soft_freq_limited_range(
2235 smu, SMU_UCLK, min_clk, max_clk, false);
2236 }
2237 break;
2238 default:
2239 return -ENOSYS;
2240 }
2241
2242 return ret;
2243 }
2244
smu_v13_0_6_get_enabled_mask(struct smu_context * smu,uint64_t * feature_mask)2245 static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu,
2246 uint64_t *feature_mask)
2247 {
2248 int ret;
2249
2250 ret = smu_cmn_get_enabled_mask(smu, feature_mask);
2251
2252 if (ret == -EIO && !smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
2253 *feature_mask = 0;
2254 ret = 0;
2255 }
2256
2257 return ret;
2258 }
2259
smu_v13_0_6_is_dpm_running(struct smu_context * smu)2260 static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu)
2261 {
2262 int ret;
2263 uint64_t feature_enabled;
2264
2265 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12))
2266 return smu_v13_0_12_is_dpm_running(smu);
2267
2268 ret = smu_v13_0_6_get_enabled_mask(smu, &feature_enabled);
2269
2270 if (ret)
2271 return false;
2272
2273 return !!(feature_enabled & SMC_DPM_FEATURE);
2274 }
2275
smu_v13_0_6_request_i2c_xfer(struct smu_context * smu,void * table_data)2276 static int smu_v13_0_6_request_i2c_xfer(struct smu_context *smu,
2277 void *table_data)
2278 {
2279 struct smu_table_context *smu_table = &smu->smu_table;
2280 struct smu_table *table = &smu_table->driver_table;
2281 struct amdgpu_device *adev = smu->adev;
2282 uint32_t table_size;
2283 int ret = 0;
2284
2285 if (!table_data)
2286 return -EINVAL;
2287
2288 table_size = smu_table->tables[SMU_TABLE_I2C_COMMANDS].size;
2289
2290 memcpy(table->cpu_addr, table_data, table_size);
2291 /* Flush hdp cache */
2292 amdgpu_asic_flush_hdp(adev, NULL);
2293 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RequestI2cTransaction,
2294 NULL);
2295
2296 return ret;
2297 }
2298
smu_v13_0_6_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)2299 static int smu_v13_0_6_i2c_xfer(struct i2c_adapter *i2c_adap,
2300 struct i2c_msg *msg, int num_msgs)
2301 {
2302 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2303 struct amdgpu_device *adev = smu_i2c->adev;
2304 struct smu_context *smu = adev->powerplay.pp_handle;
2305 struct smu_table_context *smu_table = &smu->smu_table;
2306 struct smu_table *table = &smu_table->driver_table;
2307 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2308 int i, j, r, c;
2309 u16 dir;
2310
2311 if (!adev->pm.dpm_enabled)
2312 return -EBUSY;
2313
2314 req = kzalloc(sizeof(*req), GFP_KERNEL);
2315 if (!req)
2316 return -ENOMEM;
2317
2318 req->I2CcontrollerPort = smu_i2c->port;
2319 req->I2CSpeed = I2C_SPEED_FAST_400K;
2320 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2321 dir = msg[0].flags & I2C_M_RD;
2322
2323 for (c = i = 0; i < num_msgs; i++) {
2324 for (j = 0; j < msg[i].len; j++, c++) {
2325 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2326
2327 if (!(msg[i].flags & I2C_M_RD)) {
2328 /* write */
2329 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
2330 cmd->ReadWriteData = msg[i].buf[j];
2331 }
2332
2333 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2334 /* The direction changes.
2335 */
2336 dir = msg[i].flags & I2C_M_RD;
2337 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2338 }
2339
2340 req->NumCmds++;
2341
2342 /*
2343 * Insert STOP if we are at the last byte of either last
2344 * message for the transaction or the client explicitly
2345 * requires a STOP at this particular message.
2346 */
2347 if ((j == msg[i].len - 1) &&
2348 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2349 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2350 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2351 }
2352 }
2353 }
2354 mutex_lock(&adev->pm.mutex);
2355 r = smu_v13_0_6_request_i2c_xfer(smu, req);
2356 if (r) {
2357 /* Retry once, in case of an i2c collision */
2358 r = smu_v13_0_6_request_i2c_xfer(smu, req);
2359 if (r)
2360 goto fail;
2361 }
2362
2363 for (c = i = 0; i < num_msgs; i++) {
2364 if (!(msg[i].flags & I2C_M_RD)) {
2365 c += msg[i].len;
2366 continue;
2367 }
2368 for (j = 0; j < msg[i].len; j++, c++) {
2369 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2370
2371 msg[i].buf[j] = cmd->ReadWriteData;
2372 }
2373 }
2374 r = num_msgs;
2375 fail:
2376 mutex_unlock(&adev->pm.mutex);
2377 kfree(req);
2378 return r;
2379 }
2380
smu_v13_0_6_i2c_func(struct i2c_adapter * adap)2381 static u32 smu_v13_0_6_i2c_func(struct i2c_adapter *adap)
2382 {
2383 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2384 }
2385
2386 static const struct i2c_algorithm smu_v13_0_6_i2c_algo = {
2387 .master_xfer = smu_v13_0_6_i2c_xfer,
2388 .functionality = smu_v13_0_6_i2c_func,
2389 };
2390
2391 static const struct i2c_adapter_quirks smu_v13_0_6_i2c_control_quirks = {
2392 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2393 .max_read_len = MAX_SW_I2C_COMMANDS,
2394 .max_write_len = MAX_SW_I2C_COMMANDS,
2395 .max_comb_1st_msg_len = 2,
2396 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2397 };
2398
smu_v13_0_6_i2c_control_init(struct smu_context * smu)2399 static int smu_v13_0_6_i2c_control_init(struct smu_context *smu)
2400 {
2401 struct amdgpu_device *adev = smu->adev;
2402 int res, i;
2403
2404 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2405 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2406 struct i2c_adapter *control = &smu_i2c->adapter;
2407
2408 smu_i2c->adev = adev;
2409 smu_i2c->port = i;
2410 mutex_init(&smu_i2c->mutex);
2411 control->owner = THIS_MODULE;
2412 control->dev.parent = &adev->pdev->dev;
2413 control->algo = &smu_v13_0_6_i2c_algo;
2414 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2415 control->quirks = &smu_v13_0_6_i2c_control_quirks;
2416 i2c_set_adapdata(control, smu_i2c);
2417
2418 res = i2c_add_adapter(control);
2419 if (res) {
2420 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2421 goto Out_err;
2422 }
2423 }
2424
2425 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2426 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2427
2428 return 0;
2429 Out_err:
2430 for ( ; i >= 0; i--) {
2431 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2432 struct i2c_adapter *control = &smu_i2c->adapter;
2433
2434 i2c_del_adapter(control);
2435 }
2436 return res;
2437 }
2438
smu_v13_0_6_i2c_control_fini(struct smu_context * smu)2439 static void smu_v13_0_6_i2c_control_fini(struct smu_context *smu)
2440 {
2441 struct amdgpu_device *adev = smu->adev;
2442 int i;
2443
2444 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2445 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2446 struct i2c_adapter *control = &smu_i2c->adapter;
2447
2448 i2c_del_adapter(control);
2449 }
2450 adev->pm.ras_eeprom_i2c_bus = NULL;
2451 adev->pm.fru_eeprom_i2c_bus = NULL;
2452 }
2453
smu_v13_0_6_get_unique_id(struct smu_context * smu)2454 static void smu_v13_0_6_get_unique_id(struct smu_context *smu)
2455 {
2456 struct amdgpu_device *adev = smu->adev;
2457 struct smu_table_context *smu_table = &smu->smu_table;
2458 struct PPTable_t *pptable =
2459 (struct PPTable_t *)smu_table->driver_pptable;
2460
2461 adev->unique_id = pptable->PublicSerialNumber_AID;
2462 }
2463
smu_v13_0_6_get_bamaco_support(struct smu_context * smu)2464 static int smu_v13_0_6_get_bamaco_support(struct smu_context *smu)
2465 {
2466 /* smu_13_0_6 does not support baco */
2467
2468 return 0;
2469 }
2470
2471 static const char *const throttling_logging_label[] = {
2472 [THROTTLER_PROCHOT_BIT] = "Prochot",
2473 [THROTTLER_PPT_BIT] = "PPT",
2474 [THROTTLER_THERMAL_SOCKET_BIT] = "SOC",
2475 [THROTTLER_THERMAL_VR_BIT] = "VR",
2476 [THROTTLER_THERMAL_HBM_BIT] = "HBM"
2477 };
2478
smu_v13_0_6_log_thermal_throttling_event(struct smu_context * smu)2479 static void smu_v13_0_6_log_thermal_throttling_event(struct smu_context *smu)
2480 {
2481 int throttler_idx, throttling_events = 0, buf_idx = 0;
2482 struct amdgpu_device *adev = smu->adev;
2483 uint32_t throttler_status;
2484 char log_buf[256];
2485
2486 throttler_status = smu_v13_0_6_get_throttler_status(smu);
2487 if (!throttler_status)
2488 return;
2489
2490 memset(log_buf, 0, sizeof(log_buf));
2491 for (throttler_idx = 0;
2492 throttler_idx < ARRAY_SIZE(throttling_logging_label);
2493 throttler_idx++) {
2494 if (throttler_status & (1U << throttler_idx)) {
2495 throttling_events++;
2496 buf_idx += snprintf(
2497 log_buf + buf_idx, sizeof(log_buf) - buf_idx,
2498 "%s%s", throttling_events > 1 ? " and " : "",
2499 throttling_logging_label[throttler_idx]);
2500 if (buf_idx >= sizeof(log_buf)) {
2501 dev_err(adev->dev, "buffer overflow!\n");
2502 log_buf[sizeof(log_buf) - 1] = '\0';
2503 break;
2504 }
2505 }
2506 }
2507
2508 dev_warn(adev->dev,
2509 "WARN: GPU is throttled, expect performance decrease. %s.\n",
2510 log_buf);
2511 kgd2kfd_smi_event_throttle(
2512 smu->adev->kfd.dev,
2513 smu_cmn_get_indep_throttler_status(throttler_status,
2514 smu_v13_0_6_throttler_map));
2515 }
2516
2517 static int
smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context * smu)2518 smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context *smu)
2519 {
2520 struct amdgpu_device *adev = smu->adev;
2521
2522 return REG_GET_FIELD(RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL),
2523 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
2524 }
2525
smu_v13_0_6_get_current_pcie_link_speed(struct smu_context * smu)2526 static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)
2527 {
2528 struct amdgpu_device *adev = smu->adev;
2529 uint32_t speed_level;
2530 uint32_t esm_ctrl;
2531
2532 /* TODO: confirm this on real target */
2533 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2534 if ((esm_ctrl >> 15) & 0x1)
2535 return (((esm_ctrl >> 8) & 0x7F) + 128);
2536
2537 speed_level = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2538 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2539 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2540 if (speed_level > LINK_SPEED_MAX)
2541 speed_level = 0;
2542
2543 return pcie_gen_to_speed(speed_level + 1);
2544 }
2545
smu_v13_0_6_get_xcp_metrics(struct smu_context * smu,int xcp_id,void * table)2546 static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id,
2547 void *table)
2548 {
2549 const u8 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3;
2550 int version = smu_v13_0_6_get_metrics_version(smu);
2551 struct amdgpu_partition_metrics_v1_0 *xcp_metrics;
2552 struct amdgpu_device *adev = smu->adev;
2553 int ret, inst, i, j, k, idx;
2554 MetricsTableV0_t *metrics_v0;
2555 MetricsTableV1_t *metrics_v1;
2556 MetricsTableV2_t *metrics_v2;
2557 struct amdgpu_xcp *xcp;
2558 u32 inst_mask;
2559 bool per_inst;
2560
2561 if (!table)
2562 return sizeof(*xcp_metrics);
2563
2564 for_each_xcp(adev->xcp_mgr, xcp, i) {
2565 if (xcp->id == xcp_id)
2566 break;
2567 }
2568 if (i == adev->xcp_mgr->num_xcps)
2569 return -EINVAL;
2570
2571 xcp_metrics = (struct amdgpu_partition_metrics_v1_0 *)table;
2572 smu_cmn_init_partition_metrics(xcp_metrics, 1, 0);
2573
2574 metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
2575 if (!metrics_v0)
2576 return -ENOMEM;
2577
2578 ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, false);
2579 if (ret) {
2580 kfree(metrics_v0);
2581 return ret;
2582 }
2583
2584 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
2585 IP_VERSION(13, 0, 12) &&
2586 smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) {
2587 ret = smu_v13_0_12_get_xcp_metrics(smu, xcp, table, metrics_v0);
2588 goto out;
2589 }
2590
2591 metrics_v1 = (MetricsTableV1_t *)metrics_v0;
2592 metrics_v2 = (MetricsTableV2_t *)metrics_v0;
2593
2594 per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS));
2595
2596 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
2597 idx = 0;
2598 for_each_inst(k, inst_mask) {
2599 /* Both JPEG and VCN has same instances */
2600 inst = GET_INST(VCN, k);
2601
2602 for (j = 0; j < num_jpeg_rings; ++j) {
2603 xcp_metrics->jpeg_busy[(idx * num_jpeg_rings) + j] =
2604 SMUQ10_ROUND(GET_METRIC_FIELD(
2605 JpegBusy,
2606 version)[(inst * num_jpeg_rings) + j]);
2607 }
2608 xcp_metrics->vcn_busy[idx] =
2609 SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);
2610
2611 xcp_metrics->current_vclk0[idx] = SMUQ10_ROUND(
2612 GET_METRIC_FIELD(VclkFrequency, version)[inst]);
2613 xcp_metrics->current_dclk0[idx] = SMUQ10_ROUND(
2614 GET_METRIC_FIELD(DclkFrequency, version)[inst]);
2615 xcp_metrics->current_socclk[idx] = SMUQ10_ROUND(
2616 GET_METRIC_FIELD(SocclkFrequency, version)[inst]);
2617
2618 idx++;
2619 }
2620
2621 xcp_metrics->current_uclk =
2622 SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
2623
2624 if (per_inst) {
2625 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
2626 idx = 0;
2627 for_each_inst(k, inst_mask) {
2628 inst = GET_INST(GC, k);
2629 xcp_metrics->current_gfxclk[idx] =
2630 SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency,
2631 version)[inst]);
2632
2633 xcp_metrics->gfx_busy_inst[idx] = SMUQ10_ROUND(
2634 GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);
2635 xcp_metrics->gfx_busy_acc[idx] = SMUQ10_ROUND(
2636 GET_GPU_METRIC_FIELD(GfxBusyAcc,
2637 version)[inst]);
2638 if (smu_v13_0_6_cap_supported(
2639 smu, SMU_CAP(HST_LIMIT_METRICS))) {
2640 xcp_metrics->gfx_below_host_limit_ppt_acc
2641 [idx] = SMUQ10_ROUND(
2642 metrics_v0->GfxclkBelowHostLimitPptAcc
2643 [inst]);
2644 xcp_metrics->gfx_below_host_limit_thm_acc
2645 [idx] = SMUQ10_ROUND(
2646 metrics_v0->GfxclkBelowHostLimitThmAcc
2647 [inst]);
2648 xcp_metrics->gfx_low_utilization_acc
2649 [idx] = SMUQ10_ROUND(
2650 metrics_v0
2651 ->GfxclkLowUtilizationAcc[inst]);
2652 xcp_metrics->gfx_below_host_limit_total_acc
2653 [idx] = SMUQ10_ROUND(
2654 metrics_v0->GfxclkBelowHostLimitTotalAcc
2655 [inst]);
2656 }
2657 idx++;
2658 }
2659 }
2660 out:
2661 kfree(metrics_v0);
2662
2663 return sizeof(*xcp_metrics);
2664 }
2665
smu_v13_0_6_get_gpu_metrics(struct smu_context * smu,void ** table)2666 static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table)
2667 {
2668 struct smu_table_context *smu_table = &smu->smu_table;
2669 struct gpu_metrics_v1_8 *gpu_metrics =
2670 (struct gpu_metrics_v1_8 *)smu_table->gpu_metrics_table;
2671 int version = smu_v13_0_6_get_metrics_version(smu);
2672 int ret = 0, xcc_id, inst, i, j, k, idx;
2673 struct amdgpu_device *adev = smu->adev;
2674 MetricsTableV0_t *metrics_v0;
2675 MetricsTableV1_t *metrics_v1;
2676 MetricsTableV2_t *metrics_v2;
2677 struct amdgpu_xcp *xcp;
2678 u16 link_width_level;
2679 ssize_t num_bytes;
2680 u8 num_jpeg_rings;
2681 u32 inst_mask;
2682 bool per_inst;
2683
2684 metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
2685 ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, true);
2686 if (ret) {
2687 kfree(metrics_v0);
2688 return ret;
2689 }
2690
2691 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) &&
2692 smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) {
2693 num_bytes = smu_v13_0_12_get_gpu_metrics(smu, table, metrics_v0);
2694 kfree(metrics_v0);
2695 return num_bytes;
2696 }
2697
2698 metrics_v1 = (MetricsTableV1_t *)metrics_v0;
2699 metrics_v2 = (MetricsTableV2_t *)metrics_v0;
2700
2701 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 8);
2702
2703 gpu_metrics->temperature_hotspot =
2704 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version));
2705 /* Individual HBM stack temperature is not reported */
2706 gpu_metrics->temperature_mem =
2707 SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, version));
2708 /* Reports max temperature of all voltage rails */
2709 gpu_metrics->temperature_vrsoc =
2710 SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, version));
2711
2712 gpu_metrics->average_gfx_activity =
2713 SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, version));
2714 gpu_metrics->average_umc_activity =
2715 SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, version));
2716
2717 gpu_metrics->mem_max_bandwidth =
2718 SMUQ10_ROUND(GET_METRIC_FIELD(MaxDramBandwidth, version));
2719
2720 gpu_metrics->curr_socket_power =
2721 SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, version));
2722 /* Energy counter reported in 15.259uJ (2^-16) units */
2723 gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc, version);
2724
2725 for (i = 0; i < MAX_GFX_CLKS; i++) {
2726 xcc_id = GET_INST(GC, i);
2727 if (xcc_id >= 0)
2728 gpu_metrics->current_gfxclk[i] =
2729 SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]);
2730
2731 if (i < MAX_CLKS) {
2732 gpu_metrics->current_socclk[i] =
2733 SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, version)[i]);
2734 inst = GET_INST(VCN, i);
2735 if (inst >= 0) {
2736 gpu_metrics->current_vclk0[i] =
2737 SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency,
2738 version)[inst]);
2739 gpu_metrics->current_dclk0[i] =
2740 SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency,
2741 version)[inst]);
2742 }
2743 }
2744 }
2745
2746 gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
2747
2748 /* Total accumulated cycle counter */
2749 gpu_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, version);
2750
2751 /* Accumulated throttler residencies */
2752 gpu_metrics->prochot_residency_acc = GET_METRIC_FIELD(ProchotResidencyAcc, version);
2753 gpu_metrics->ppt_residency_acc = GET_METRIC_FIELD(PptResidencyAcc, version);
2754 gpu_metrics->socket_thm_residency_acc = GET_METRIC_FIELD(SocketThmResidencyAcc, version);
2755 gpu_metrics->vr_thm_residency_acc = GET_METRIC_FIELD(VrThmResidencyAcc, version);
2756 gpu_metrics->hbm_thm_residency_acc =
2757 GET_METRIC_FIELD(HbmThmResidencyAcc, version);
2758
2759 /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */
2760 gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak,
2761 version) >> GET_INST(GC, 0);
2762
2763 if (!(adev->flags & AMD_IS_APU)) {
2764 /*Check smu version, PCIE link speed and width will be reported from pmfw metric
2765 * table for both pf & one vf for smu version 85.99.0 or higher else report only
2766 * for pf from registers
2767 */
2768 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PCIE_METRICS))) {
2769 gpu_metrics->pcie_link_width = GET_GPU_METRIC_FIELD(PCIeLinkWidth, version);
2770 gpu_metrics->pcie_link_speed =
2771 pcie_gen_to_speed(GET_GPU_METRIC_FIELD(PCIeLinkSpeed, version));
2772 } else if (!amdgpu_sriov_vf(adev)) {
2773 link_width_level = smu_v13_0_6_get_current_pcie_link_width_level(smu);
2774 if (link_width_level > MAX_LINK_WIDTH)
2775 link_width_level = 0;
2776
2777 gpu_metrics->pcie_link_width =
2778 DECODE_LANE_WIDTH(link_width_level);
2779 gpu_metrics->pcie_link_speed =
2780 smu_v13_0_6_get_current_pcie_link_speed(smu);
2781 }
2782
2783 gpu_metrics->pcie_bandwidth_acc =
2784 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(PcieBandwidthAcc, version)[0]);
2785 gpu_metrics->pcie_bandwidth_inst =
2786 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(PcieBandwidth, version)[0]);
2787 gpu_metrics->pcie_l0_to_recov_count_acc =
2788 GET_GPU_METRIC_FIELD(PCIeL0ToRecoveryCountAcc, version);
2789 gpu_metrics->pcie_replay_count_acc =
2790 GET_GPU_METRIC_FIELD(PCIenReplayAAcc, version);
2791 gpu_metrics->pcie_replay_rover_count_acc =
2792 GET_GPU_METRIC_FIELD(PCIenReplayARolloverCountAcc, version);
2793 gpu_metrics->pcie_nak_sent_count_acc =
2794 GET_GPU_METRIC_FIELD(PCIeNAKSentCountAcc, version);
2795 gpu_metrics->pcie_nak_rcvd_count_acc =
2796 GET_GPU_METRIC_FIELD(PCIeNAKReceivedCountAcc, version);
2797 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(OTHER_END_METRICS)))
2798 gpu_metrics->pcie_lc_perf_other_end_recovery =
2799 GET_GPU_METRIC_FIELD(PCIeOtherEndRecoveryAcc, version);
2800
2801 }
2802
2803 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2804
2805 gpu_metrics->gfx_activity_acc =
2806 SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc, version));
2807 gpu_metrics->mem_activity_acc =
2808 SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc, version));
2809
2810 for (i = 0; i < NUM_XGMI_LINKS; i++) {
2811 j = amdgpu_xgmi_get_ext_link(adev, i);
2812 if (j < 0 || j >= NUM_XGMI_LINKS)
2813 continue;
2814 gpu_metrics->xgmi_read_data_acc[j] = SMUQ10_ROUND(
2815 GET_METRIC_FIELD(XgmiReadDataSizeAcc, version)[i]);
2816 gpu_metrics->xgmi_write_data_acc[j] = SMUQ10_ROUND(
2817 GET_METRIC_FIELD(XgmiWriteDataSizeAcc, version)[i]);
2818 ret = amdgpu_get_xgmi_link_status(adev, i);
2819 if (ret >= 0)
2820 gpu_metrics->xgmi_link_status[j] = ret;
2821 }
2822
2823 gpu_metrics->num_partition = adev->xcp_mgr->num_xcps;
2824
2825 per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS));
2826
2827 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3;
2828 for_each_xcp(adev->xcp_mgr, xcp, i) {
2829 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
2830 idx = 0;
2831 for_each_inst(k, inst_mask) {
2832 /* Both JPEG and VCN has same instances */
2833 inst = GET_INST(VCN, k);
2834
2835 for (j = 0; j < num_jpeg_rings; ++j) {
2836 gpu_metrics->xcp_stats[i].jpeg_busy
2837 [(idx * num_jpeg_rings) + j] =
2838 SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, version)
2839 [(inst * num_jpeg_rings) + j]);
2840 }
2841 gpu_metrics->xcp_stats[i].vcn_busy[idx] =
2842 SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);
2843 idx++;
2844
2845 }
2846
2847 if (per_inst) {
2848 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
2849 idx = 0;
2850 for_each_inst(k, inst_mask) {
2851 inst = GET_INST(GC, k);
2852 gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] =
2853 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);
2854 gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] =
2855 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusyAcc,
2856 version)[inst]);
2857 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(HST_LIMIT_METRICS))) {
2858 gpu_metrics->xcp_stats[i].gfx_below_host_limit_ppt_acc[idx] =
2859 SMUQ10_ROUND
2860 (metrics_v0->GfxclkBelowHostLimitPptAcc[inst]);
2861 gpu_metrics->xcp_stats[i].gfx_below_host_limit_thm_acc[idx] =
2862 SMUQ10_ROUND
2863 (metrics_v0->GfxclkBelowHostLimitThmAcc[inst]);
2864 gpu_metrics->xcp_stats[i].gfx_low_utilization_acc[idx] =
2865 SMUQ10_ROUND
2866 (metrics_v0->GfxclkLowUtilizationAcc[inst]);
2867 gpu_metrics->xcp_stats[i].gfx_below_host_limit_total_acc[idx] =
2868 SMUQ10_ROUND
2869 (metrics_v0->GfxclkBelowHostLimitTotalAcc[inst]);
2870 }
2871 idx++;
2872 }
2873 }
2874 }
2875
2876 gpu_metrics->xgmi_link_width = GET_METRIC_FIELD(XgmiWidth, version);
2877 gpu_metrics->xgmi_link_speed = GET_METRIC_FIELD(XgmiBitrate, version);
2878
2879 gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version);
2880
2881 *table = (void *)gpu_metrics;
2882 kfree(metrics_v0);
2883
2884 return sizeof(*gpu_metrics);
2885 }
2886
smu_v13_0_6_restore_pci_config(struct smu_context * smu)2887 static void smu_v13_0_6_restore_pci_config(struct smu_context *smu)
2888 {
2889 struct amdgpu_device *adev = smu->adev;
2890 int i;
2891
2892 for (i = 0; i < 16; i++)
2893 pci_write_config_dword(adev->pdev, i * 4,
2894 adev->pdev->saved_config_space[i]);
2895 pci_restore_msi_state(adev->pdev);
2896 }
2897
smu_v13_0_6_mode2_reset(struct smu_context * smu)2898 static int smu_v13_0_6_mode2_reset(struct smu_context *smu)
2899 {
2900 int ret = 0, index;
2901 struct amdgpu_device *adev = smu->adev;
2902 int timeout = 10;
2903
2904 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2905 SMU_MSG_GfxDeviceDriverReset);
2906 if (index < 0)
2907 return index;
2908
2909 mutex_lock(&smu->message_lock);
2910
2911 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
2912 SMU_RESET_MODE_2);
2913
2914 /* Reset takes a bit longer, wait for 200ms. */
2915 msleep(200);
2916
2917 dev_dbg(smu->adev->dev, "restore config space...\n");
2918 /* Restore the config space saved during init */
2919 amdgpu_device_load_pci_state(adev->pdev);
2920
2921 /* Certain platforms have switches which assign virtual BAR values to
2922 * devices. OS uses the virtual BAR values and device behind the switch
2923 * is assgined another BAR value. When device's config space registers
2924 * are queried, switch returns the virtual BAR values. When mode-2 reset
2925 * is performed, switch is unaware of it, and will continue to return
2926 * the same virtual values to the OS.This affects
2927 * pci_restore_config_space() API as it doesn't write the value saved if
2928 * the current value read from config space is the same as what is
2929 * saved. As a workaround, make sure the config space is restored
2930 * always.
2931 */
2932 if (!(adev->flags & AMD_IS_APU))
2933 smu_v13_0_6_restore_pci_config(smu);
2934
2935 dev_dbg(smu->adev->dev, "wait for reset ack\n");
2936 do {
2937 ret = smu_cmn_wait_for_response(smu);
2938 /* Wait a bit more time for getting ACK */
2939 if (ret == -ETIME) {
2940 --timeout;
2941 usleep_range(500, 1000);
2942 continue;
2943 }
2944
2945 if (ret)
2946 goto out;
2947
2948 } while (ret == -ETIME && timeout);
2949
2950 out:
2951 mutex_unlock(&smu->message_lock);
2952
2953 if (ret)
2954 dev_err(adev->dev, "failed to send mode2 reset, error code %d",
2955 ret);
2956
2957 return ret;
2958 }
2959
smu_v13_0_6_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2960 static int smu_v13_0_6_get_thermal_temperature_range(struct smu_context *smu,
2961 struct smu_temperature_range *range)
2962 {
2963 struct amdgpu_device *adev = smu->adev;
2964 u32 aid_temp, xcd_temp, max_temp;
2965 u32 ccd_temp = 0;
2966 int ret;
2967
2968 if (amdgpu_sriov_vf(smu->adev))
2969 return 0;
2970
2971 if (!range)
2972 return -EINVAL;
2973
2974 /*Check smu version, GetCtfLimit message only supported for smu version 85.69 or higher */
2975 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(CTF_LIMIT)))
2976 return 0;
2977
2978 /* Get SOC Max operating temperature */
2979 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2980 PPSMC_AID_THM_TYPE, &aid_temp);
2981 if (ret)
2982 goto failed;
2983 if (adev->flags & AMD_IS_APU) {
2984 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2985 PPSMC_CCD_THM_TYPE, &ccd_temp);
2986 if (ret)
2987 goto failed;
2988 }
2989 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2990 PPSMC_XCD_THM_TYPE, &xcd_temp);
2991 if (ret)
2992 goto failed;
2993 range->hotspot_emergency_max = max3(aid_temp, xcd_temp, ccd_temp) *
2994 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2995
2996 /* Get HBM Max operating temperature */
2997 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2998 PPSMC_HBM_THM_TYPE, &max_temp);
2999 if (ret)
3000 goto failed;
3001 range->mem_emergency_max =
3002 max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3003
3004 /* Get SOC thermal throttle limit */
3005 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetThermalLimit,
3006 PPSMC_THROTTLING_LIMIT_TYPE_SOCKET,
3007 &max_temp);
3008 if (ret)
3009 goto failed;
3010 range->hotspot_crit_max =
3011 max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3012
3013 /* Get HBM thermal throttle limit */
3014 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetThermalLimit,
3015 PPSMC_THROTTLING_LIMIT_TYPE_HBM,
3016 &max_temp);
3017 if (ret)
3018 goto failed;
3019
3020 range->mem_crit_max = max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3021
3022 failed:
3023 return ret;
3024 }
3025
smu_v13_0_6_mode1_reset(struct smu_context * smu)3026 static int smu_v13_0_6_mode1_reset(struct smu_context *smu)
3027 {
3028 struct amdgpu_device *adev = smu->adev;
3029 u32 fatal_err, param;
3030 int ret = 0;
3031
3032 fatal_err = 0;
3033 param = SMU_RESET_MODE_1;
3034
3035 /* fatal error triggered by ras, PMFW supports the flag */
3036 if (amdgpu_ras_get_fed_status(adev))
3037 fatal_err = 1;
3038
3039 param |= (fatal_err << 16);
3040 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
3041 param, NULL);
3042
3043 if (!ret)
3044 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
3045
3046 return ret;
3047 }
3048
smu_v13_0_6_link_reset(struct smu_context * smu)3049 static int smu_v13_0_6_link_reset(struct smu_context *smu)
3050 {
3051 int ret = 0;
3052
3053 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
3054 SMU_RESET_MODE_4, NULL);
3055 return ret;
3056 }
3057
smu_v13_0_6_is_mode1_reset_supported(struct smu_context * smu)3058 static bool smu_v13_0_6_is_mode1_reset_supported(struct smu_context *smu)
3059 {
3060 return true;
3061 }
3062
smu_v13_0_6_is_link_reset_supported(struct smu_context * smu)3063 static inline bool smu_v13_0_6_is_link_reset_supported(struct smu_context *smu)
3064 {
3065 struct amdgpu_device *adev = smu->adev;
3066 int var = (adev->pdev->device & 0xF);
3067
3068 if (var == 0x1)
3069 return true;
3070
3071 return false;
3072 }
3073
smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context * smu,uint32_t size)3074 static int smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context *smu,
3075 uint32_t size)
3076 {
3077 int ret = 0;
3078
3079 /* message SMU to update the bad page number on SMUBUS */
3080 ret = smu_cmn_send_smc_msg_with_param(
3081 smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
3082 if (ret)
3083 dev_err(smu->adev->dev,
3084 "[%s] failed to message SMU to update HBM bad pages number\n",
3085 __func__);
3086
3087 return ret;
3088 }
3089
smu_v13_0_6_send_rma_reason(struct smu_context * smu)3090 static int smu_v13_0_6_send_rma_reason(struct smu_context *smu)
3091 {
3092 int ret;
3093
3094 /* NOTE: the message is only valid on dGPU with pmfw 85.90.0 and above */
3095 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(RMA_MSG)))
3096 return 0;
3097
3098 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RmaDueToBadPageThreshold, NULL);
3099 if (ret)
3100 dev_err(smu->adev->dev,
3101 "[%s] failed to send BadPageThreshold event to SMU\n",
3102 __func__);
3103
3104 return ret;
3105 }
3106
3107 /**
3108 * smu_v13_0_6_reset_sdma_is_supported - Check if SDMA reset is supported
3109 * @smu: smu_context pointer
3110 *
3111 * This function checks if the SMU supports resetting the SDMA engine.
3112 * It returns false if the capability is not supported.
3113 */
smu_v13_0_6_reset_sdma_is_supported(struct smu_context * smu)3114 static bool smu_v13_0_6_reset_sdma_is_supported(struct smu_context *smu)
3115 {
3116 bool ret = true;
3117
3118 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SDMA_RESET))) {
3119 dev_info(smu->adev->dev,
3120 "SDMA reset capability is not supported\n");
3121 ret = false;
3122 }
3123
3124 return ret;
3125 }
3126
smu_v13_0_6_reset_sdma(struct smu_context * smu,uint32_t inst_mask)3127 static int smu_v13_0_6_reset_sdma(struct smu_context *smu, uint32_t inst_mask)
3128 {
3129 int ret = 0;
3130
3131 if (!smu_v13_0_6_reset_sdma_is_supported(smu))
3132 return -EOPNOTSUPP;
3133
3134 ret = smu_cmn_send_smc_msg_with_param(smu,
3135 SMU_MSG_ResetSDMA, inst_mask, NULL);
3136 if (ret)
3137 dev_err(smu->adev->dev,
3138 "failed to send ResetSDMA event with mask 0x%x\n",
3139 inst_mask);
3140
3141 return ret;
3142 }
3143
smu_v13_0_6_reset_vcn(struct smu_context * smu,uint32_t inst_mask)3144 static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask)
3145 {
3146 int ret = 0;
3147
3148 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ResetVCN, inst_mask, NULL);
3149 if (ret)
3150 dev_err(smu->adev->dev,
3151 "failed to send ResetVCN event with mask 0x%x\n",
3152 inst_mask);
3153 return ret;
3154 }
3155
3156
mca_smu_set_debug_mode(struct amdgpu_device * adev,bool enable)3157 static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
3158 {
3159 struct smu_context *smu = adev->powerplay.pp_handle;
3160
3161 return smu_v13_0_6_mca_set_debug_mode(smu, enable);
3162 }
3163
smu_v13_0_6_get_valid_mca_count(struct smu_context * smu,enum amdgpu_mca_error_type type,uint32_t * count)3164 static int smu_v13_0_6_get_valid_mca_count(struct smu_context *smu, enum amdgpu_mca_error_type type, uint32_t *count)
3165 {
3166 uint32_t msg;
3167 int ret;
3168
3169 if (!count)
3170 return -EINVAL;
3171
3172 switch (type) {
3173 case AMDGPU_MCA_ERROR_TYPE_UE:
3174 msg = SMU_MSG_QueryValidMcaCount;
3175 break;
3176 case AMDGPU_MCA_ERROR_TYPE_CE:
3177 msg = SMU_MSG_QueryValidMcaCeCount;
3178 break;
3179 default:
3180 return -EINVAL;
3181 }
3182
3183 ret = smu_cmn_send_smc_msg(smu, msg, count);
3184 if (ret) {
3185 *count = 0;
3186 return ret;
3187 }
3188
3189 return 0;
3190 }
3191
__smu_v13_0_6_mca_dump_bank(struct smu_context * smu,enum amdgpu_mca_error_type type,int idx,int offset,uint32_t * val)3192 static int __smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
3193 int idx, int offset, uint32_t *val)
3194 {
3195 uint32_t msg, param;
3196
3197 switch (type) {
3198 case AMDGPU_MCA_ERROR_TYPE_UE:
3199 msg = SMU_MSG_McaBankDumpDW;
3200 break;
3201 case AMDGPU_MCA_ERROR_TYPE_CE:
3202 msg = SMU_MSG_McaBankCeDumpDW;
3203 break;
3204 default:
3205 return -EINVAL;
3206 }
3207
3208 param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
3209
3210 return smu_cmn_send_smc_msg_with_param(smu, msg, param, val);
3211 }
3212
smu_v13_0_6_mca_dump_bank(struct smu_context * smu,enum amdgpu_mca_error_type type,int idx,int offset,uint32_t * val,int count)3213 static int smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
3214 int idx, int offset, uint32_t *val, int count)
3215 {
3216 int ret, i;
3217
3218 if (!val)
3219 return -EINVAL;
3220
3221 for (i = 0; i < count; i++) {
3222 ret = __smu_v13_0_6_mca_dump_bank(smu, type, idx, offset + (i << 2), &val[i]);
3223 if (ret)
3224 return ret;
3225 }
3226
3227 return 0;
3228 }
3229
3230 static const struct mca_bank_ipid smu_v13_0_6_mca_ipid_table[AMDGPU_MCA_IP_COUNT] = {
3231 MCA_BANK_IPID(UMC, 0x96, 0x0),
3232 MCA_BANK_IPID(SMU, 0x01, 0x1),
3233 MCA_BANK_IPID(MP5, 0x01, 0x2),
3234 MCA_BANK_IPID(PCS_XGMI, 0x50, 0x0),
3235 };
3236
mca_bank_entry_info_decode(struct mca_bank_entry * entry,struct mca_bank_info * info)3237 static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_bank_info *info)
3238 {
3239 u64 ipid = entry->regs[MCA_REG_IDX_IPID];
3240 u32 instidhi, instid;
3241
3242 /* NOTE: All MCA IPID register share the same format,
3243 * so the driver can share the MCMP1 register header file.
3244 * */
3245
3246 info->hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);
3247 info->mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType);
3248
3249 /*
3250 * Unfied DieID Format: SAASS. A:AID, S:Socket.
3251 * Unfied DieID[4] = InstanceId[0]
3252 * Unfied DieID[0:3] = InstanceIdHi[0:3]
3253 */
3254 instidhi = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi);
3255 instid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo);
3256 info->aid = ((instidhi >> 2) & 0x03);
3257 info->socket_id = ((instid & 0x1) << 2) | (instidhi & 0x03);
3258 }
3259
mca_bank_read_reg(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,int reg_idx,uint64_t * val)3260 static int mca_bank_read_reg(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
3261 int idx, int reg_idx, uint64_t *val)
3262 {
3263 struct smu_context *smu = adev->powerplay.pp_handle;
3264 uint32_t data[2] = {0, 0};
3265 int ret;
3266
3267 if (!val || reg_idx >= MCA_REG_IDX_COUNT)
3268 return -EINVAL;
3269
3270 ret = smu_v13_0_6_mca_dump_bank(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
3271 if (ret)
3272 return ret;
3273
3274 *val = (uint64_t)data[1] << 32 | data[0];
3275
3276 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3277 type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
3278
3279 return 0;
3280 }
3281
mca_get_mca_entry(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,struct mca_bank_entry * entry)3282 static int mca_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
3283 int idx, struct mca_bank_entry *entry)
3284 {
3285 int i, ret;
3286
3287 /* NOTE: populated all mca register by default */
3288 for (i = 0; i < ARRAY_SIZE(entry->regs); i++) {
3289 ret = mca_bank_read_reg(adev, type, idx, i, &entry->regs[i]);
3290 if (ret)
3291 return ret;
3292 }
3293
3294 entry->idx = idx;
3295 entry->type = type;
3296
3297 mca_bank_entry_info_decode(entry, &entry->info);
3298
3299 return 0;
3300 }
3301
mca_decode_ipid_to_hwip(uint64_t val)3302 static int mca_decode_ipid_to_hwip(uint64_t val)
3303 {
3304 const struct mca_bank_ipid *ipid;
3305 uint16_t hwid, mcatype;
3306 int i;
3307
3308 hwid = REG_GET_FIELD(val, MCMP1_IPIDT0, HardwareID);
3309 mcatype = REG_GET_FIELD(val, MCMP1_IPIDT0, McaType);
3310
3311 for (i = 0; i < ARRAY_SIZE(smu_v13_0_6_mca_ipid_table); i++) {
3312 ipid = &smu_v13_0_6_mca_ipid_table[i];
3313
3314 if (!ipid->hwid)
3315 continue;
3316
3317 if (ipid->hwid == hwid && ipid->mcatype == mcatype)
3318 return i;
3319 }
3320
3321 return AMDGPU_MCA_IP_UNKNOW;
3322 }
3323
mca_umc_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3324 static int mca_umc_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3325 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3326 {
3327 uint64_t status0;
3328 uint32_t ext_error_code;
3329 uint32_t odecc_err_cnt;
3330
3331 status0 = entry->regs[MCA_REG_IDX_STATUS];
3332 ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(status0);
3333 odecc_err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
3334
3335 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3336 *count = 0;
3337 return 0;
3338 }
3339
3340 if (umc_v12_0_is_deferred_error(adev, status0) ||
3341 umc_v12_0_is_uncorrectable_error(adev, status0) ||
3342 umc_v12_0_is_correctable_error(adev, status0))
3343 *count = (ext_error_code == 0) ? odecc_err_cnt : 1;
3344
3345 amdgpu_umc_update_ecc_status(adev,
3346 entry->regs[MCA_REG_IDX_STATUS],
3347 entry->regs[MCA_REG_IDX_IPID],
3348 entry->regs[MCA_REG_IDX_ADDR]);
3349
3350 return 0;
3351 }
3352
mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3353 static int mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3354 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry,
3355 uint32_t *count)
3356 {
3357 u32 ext_error_code;
3358 u32 err_cnt;
3359
3360 ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(entry->regs[MCA_REG_IDX_STATUS]);
3361 err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
3362
3363 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3364 (ext_error_code == 0 || ext_error_code == 9))
3365 *count = err_cnt;
3366 else if (type == AMDGPU_MCA_ERROR_TYPE_CE && ext_error_code == 6)
3367 *count = err_cnt;
3368
3369 return 0;
3370 }
3371
mca_smu_check_error_code(struct amdgpu_device * adev,const struct mca_ras_info * mca_ras,uint32_t errcode)3372 static bool mca_smu_check_error_code(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
3373 uint32_t errcode)
3374 {
3375 int i;
3376
3377 if (!mca_ras->err_code_count || !mca_ras->err_code_array)
3378 return true;
3379
3380 for (i = 0; i < mca_ras->err_code_count; i++) {
3381 if (errcode == mca_ras->err_code_array[i])
3382 return true;
3383 }
3384
3385 return false;
3386 }
3387
mca_gfx_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3388 static int mca_gfx_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3389 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3390 {
3391 uint64_t status0, misc0;
3392
3393 status0 = entry->regs[MCA_REG_IDX_STATUS];
3394 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3395 *count = 0;
3396 return 0;
3397 }
3398
3399 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3400 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
3401 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
3402 *count = 1;
3403 return 0;
3404 } else {
3405 misc0 = entry->regs[MCA_REG_IDX_MISC0];
3406 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
3407 }
3408
3409 return 0;
3410 }
3411
mca_smu_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3412 static int mca_smu_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3413 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3414 {
3415 uint64_t status0, misc0;
3416
3417 status0 = entry->regs[MCA_REG_IDX_STATUS];
3418 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3419 *count = 0;
3420 return 0;
3421 }
3422
3423 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3424 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
3425 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
3426 if (count)
3427 *count = 1;
3428 return 0;
3429 }
3430
3431 misc0 = entry->regs[MCA_REG_IDX_MISC0];
3432 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
3433
3434 return 0;
3435 }
3436
mca_gfx_smu_bank_is_valid(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3437 static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3438 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3439 {
3440 uint32_t instlo;
3441
3442 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
3443 instlo &= GENMASK(31, 1);
3444 switch (instlo) {
3445 case 0x36430400: /* SMNAID XCD 0 */
3446 case 0x38430400: /* SMNAID XCD 1 */
3447 case 0x40430400: /* SMNXCD XCD 0, NOTE: FIXME: fix this error later */
3448 return true;
3449 default:
3450 return false;
3451 }
3452
3453 return false;
3454 };
3455
mca_smu_bank_is_valid(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3456 static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3457 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3458 {
3459 struct smu_context *smu = adev->powerplay.pp_handle;
3460 uint32_t errcode, instlo;
3461
3462 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
3463 instlo &= GENMASK(31, 1);
3464 if (instlo != 0x03b30400)
3465 return false;
3466
3467 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(ACA_SYND))) {
3468 errcode = MCA_REG__SYND__ERRORINFORMATION(entry->regs[MCA_REG_IDX_SYND]);
3469 errcode &= 0xff;
3470 } else {
3471 errcode = REG_GET_FIELD(entry->regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode);
3472 }
3473
3474 return mca_smu_check_error_code(adev, mca_ras, errcode);
3475 }
3476
3477 static int sdma_err_codes[] = { CODE_SDMA0, CODE_SDMA1, CODE_SDMA2, CODE_SDMA3 };
3478 static int mmhub_err_codes[] = {
3479 CODE_DAGB0, CODE_DAGB0 + 1, CODE_DAGB0 + 2, CODE_DAGB0 + 3, CODE_DAGB0 + 4, /* DAGB0-4 */
3480 CODE_EA0, CODE_EA0 + 1, CODE_EA0 + 2, CODE_EA0 + 3, CODE_EA0 + 4, /* MMEA0-4*/
3481 CODE_VML2, CODE_VML2_WALKER, CODE_MMCANE,
3482 };
3483
3484 static int vcn_err_codes[] = {
3485 CODE_VIDD, CODE_VIDV,
3486 };
3487 static int jpeg_err_codes[] = {
3488 CODE_JPEG0S, CODE_JPEG0D, CODE_JPEG1S, CODE_JPEG1D,
3489 CODE_JPEG2S, CODE_JPEG2D, CODE_JPEG3S, CODE_JPEG3D,
3490 CODE_JPEG4S, CODE_JPEG4D, CODE_JPEG5S, CODE_JPEG5D,
3491 CODE_JPEG6S, CODE_JPEG6D, CODE_JPEG7S, CODE_JPEG7D,
3492 };
3493
3494 static const struct mca_ras_info mca_ras_table[] = {
3495 {
3496 .blkid = AMDGPU_RAS_BLOCK__UMC,
3497 .ip = AMDGPU_MCA_IP_UMC,
3498 .get_err_count = mca_umc_mca_get_err_count,
3499 }, {
3500 .blkid = AMDGPU_RAS_BLOCK__GFX,
3501 .ip = AMDGPU_MCA_IP_SMU,
3502 .get_err_count = mca_gfx_mca_get_err_count,
3503 .bank_is_valid = mca_gfx_smu_bank_is_valid,
3504 }, {
3505 .blkid = AMDGPU_RAS_BLOCK__SDMA,
3506 .ip = AMDGPU_MCA_IP_SMU,
3507 .err_code_array = sdma_err_codes,
3508 .err_code_count = ARRAY_SIZE(sdma_err_codes),
3509 .get_err_count = mca_smu_mca_get_err_count,
3510 .bank_is_valid = mca_smu_bank_is_valid,
3511 }, {
3512 .blkid = AMDGPU_RAS_BLOCK__MMHUB,
3513 .ip = AMDGPU_MCA_IP_SMU,
3514 .err_code_array = mmhub_err_codes,
3515 .err_code_count = ARRAY_SIZE(mmhub_err_codes),
3516 .get_err_count = mca_smu_mca_get_err_count,
3517 .bank_is_valid = mca_smu_bank_is_valid,
3518 }, {
3519 .blkid = AMDGPU_RAS_BLOCK__XGMI_WAFL,
3520 .ip = AMDGPU_MCA_IP_PCS_XGMI,
3521 .get_err_count = mca_pcs_xgmi_mca_get_err_count,
3522 }, {
3523 .blkid = AMDGPU_RAS_BLOCK__VCN,
3524 .ip = AMDGPU_MCA_IP_SMU,
3525 .err_code_array = vcn_err_codes,
3526 .err_code_count = ARRAY_SIZE(vcn_err_codes),
3527 .get_err_count = mca_smu_mca_get_err_count,
3528 .bank_is_valid = mca_smu_bank_is_valid,
3529 }, {
3530 .blkid = AMDGPU_RAS_BLOCK__JPEG,
3531 .ip = AMDGPU_MCA_IP_SMU,
3532 .err_code_array = jpeg_err_codes,
3533 .err_code_count = ARRAY_SIZE(jpeg_err_codes),
3534 .get_err_count = mca_smu_mca_get_err_count,
3535 .bank_is_valid = mca_smu_bank_is_valid,
3536 },
3537 };
3538
mca_get_mca_ras_info(struct amdgpu_device * adev,enum amdgpu_ras_block blkid)3539 static const struct mca_ras_info *mca_get_mca_ras_info(struct amdgpu_device *adev, enum amdgpu_ras_block blkid)
3540 {
3541 int i;
3542
3543 for (i = 0; i < ARRAY_SIZE(mca_ras_table); i++) {
3544 if (mca_ras_table[i].blkid == blkid)
3545 return &mca_ras_table[i];
3546 }
3547
3548 return NULL;
3549 }
3550
mca_get_valid_mca_count(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,uint32_t * count)3551 static int mca_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count)
3552 {
3553 struct smu_context *smu = adev->powerplay.pp_handle;
3554 int ret;
3555
3556 switch (type) {
3557 case AMDGPU_MCA_ERROR_TYPE_UE:
3558 case AMDGPU_MCA_ERROR_TYPE_CE:
3559 ret = smu_v13_0_6_get_valid_mca_count(smu, type, count);
3560 break;
3561 default:
3562 ret = -EINVAL;
3563 break;
3564 }
3565
3566 return ret;
3567 }
3568
mca_bank_is_valid(struct amdgpu_device * adev,const struct mca_ras_info * mca_ras,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3569 static bool mca_bank_is_valid(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
3570 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3571 {
3572 if (mca_decode_ipid_to_hwip(entry->regs[MCA_REG_IDX_IPID]) != mca_ras->ip)
3573 return false;
3574
3575 if (mca_ras->bank_is_valid)
3576 return mca_ras->bank_is_valid(mca_ras, adev, type, entry);
3577
3578 return true;
3579 }
3580
mca_smu_parse_mca_error_count(struct amdgpu_device * adev,enum amdgpu_ras_block blk,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3581 static int mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
3582 struct mca_bank_entry *entry, uint32_t *count)
3583 {
3584 const struct mca_ras_info *mca_ras;
3585
3586 if (!entry || !count)
3587 return -EINVAL;
3588
3589 mca_ras = mca_get_mca_ras_info(adev, blk);
3590 if (!mca_ras)
3591 return -EOPNOTSUPP;
3592
3593 if (!mca_bank_is_valid(adev, mca_ras, type, entry)) {
3594 *count = 0;
3595 return 0;
3596 }
3597
3598 return mca_ras->get_err_count(mca_ras, adev, type, entry, count);
3599 }
3600
mca_smu_get_mca_entry(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,struct mca_bank_entry * entry)3601 static int mca_smu_get_mca_entry(struct amdgpu_device *adev,
3602 enum amdgpu_mca_error_type type, int idx, struct mca_bank_entry *entry)
3603 {
3604 return mca_get_mca_entry(adev, type, idx, entry);
3605 }
3606
mca_smu_get_valid_mca_count(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,uint32_t * count)3607 static int mca_smu_get_valid_mca_count(struct amdgpu_device *adev,
3608 enum amdgpu_mca_error_type type, uint32_t *count)
3609 {
3610 return mca_get_valid_mca_count(adev, type, count);
3611 }
3612
3613 static const struct amdgpu_mca_smu_funcs smu_v13_0_6_mca_smu_funcs = {
3614 .max_ue_count = 12,
3615 .max_ce_count = 12,
3616 .mca_set_debug_mode = mca_smu_set_debug_mode,
3617 .mca_parse_mca_error_count = mca_smu_parse_mca_error_count,
3618 .mca_get_mca_entry = mca_smu_get_mca_entry,
3619 .mca_get_valid_mca_count = mca_smu_get_valid_mca_count,
3620 };
3621
aca_smu_set_debug_mode(struct amdgpu_device * adev,bool enable)3622 static int aca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
3623 {
3624 struct smu_context *smu = adev->powerplay.pp_handle;
3625
3626 return smu_v13_0_6_mca_set_debug_mode(smu, enable);
3627 }
3628
smu_v13_0_6_get_valid_aca_count(struct smu_context * smu,enum aca_smu_type type,u32 * count)3629 static int smu_v13_0_6_get_valid_aca_count(struct smu_context *smu, enum aca_smu_type type, u32 *count)
3630 {
3631 uint32_t msg;
3632 int ret;
3633
3634 if (!count)
3635 return -EINVAL;
3636
3637 switch (type) {
3638 case ACA_SMU_TYPE_UE:
3639 msg = SMU_MSG_QueryValidMcaCount;
3640 break;
3641 case ACA_SMU_TYPE_CE:
3642 msg = SMU_MSG_QueryValidMcaCeCount;
3643 break;
3644 default:
3645 return -EINVAL;
3646 }
3647
3648 ret = smu_cmn_send_smc_msg(smu, msg, count);
3649 if (ret) {
3650 *count = 0;
3651 return ret;
3652 }
3653
3654 return 0;
3655 }
3656
aca_smu_get_valid_aca_count(struct amdgpu_device * adev,enum aca_smu_type type,u32 * count)3657 static int aca_smu_get_valid_aca_count(struct amdgpu_device *adev,
3658 enum aca_smu_type type, u32 *count)
3659 {
3660 struct smu_context *smu = adev->powerplay.pp_handle;
3661 int ret;
3662
3663 switch (type) {
3664 case ACA_SMU_TYPE_UE:
3665 case ACA_SMU_TYPE_CE:
3666 ret = smu_v13_0_6_get_valid_aca_count(smu, type, count);
3667 break;
3668 default:
3669 ret = -EINVAL;
3670 break;
3671 }
3672
3673 return ret;
3674 }
3675
__smu_v13_0_6_aca_bank_dump(struct smu_context * smu,enum aca_smu_type type,int idx,int offset,u32 * val)3676 static int __smu_v13_0_6_aca_bank_dump(struct smu_context *smu, enum aca_smu_type type,
3677 int idx, int offset, u32 *val)
3678 {
3679 uint32_t msg, param;
3680
3681 switch (type) {
3682 case ACA_SMU_TYPE_UE:
3683 msg = SMU_MSG_McaBankDumpDW;
3684 break;
3685 case ACA_SMU_TYPE_CE:
3686 msg = SMU_MSG_McaBankCeDumpDW;
3687 break;
3688 default:
3689 return -EINVAL;
3690 }
3691
3692 param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
3693
3694 return smu_cmn_send_smc_msg_with_param(smu, msg, param, (uint32_t *)val);
3695 }
3696
smu_v13_0_6_aca_bank_dump(struct smu_context * smu,enum aca_smu_type type,int idx,int offset,u32 * val,int count)3697 static int smu_v13_0_6_aca_bank_dump(struct smu_context *smu, enum aca_smu_type type,
3698 int idx, int offset, u32 *val, int count)
3699 {
3700 int ret, i;
3701
3702 if (!val)
3703 return -EINVAL;
3704
3705 for (i = 0; i < count; i++) {
3706 ret = __smu_v13_0_6_aca_bank_dump(smu, type, idx, offset + (i << 2), &val[i]);
3707 if (ret)
3708 return ret;
3709 }
3710
3711 return 0;
3712 }
3713
aca_bank_read_reg(struct amdgpu_device * adev,enum aca_smu_type type,int idx,int reg_idx,u64 * val)3714 static int aca_bank_read_reg(struct amdgpu_device *adev, enum aca_smu_type type,
3715 int idx, int reg_idx, u64 *val)
3716 {
3717 struct smu_context *smu = adev->powerplay.pp_handle;
3718 u32 data[2] = {0, 0};
3719 int ret;
3720
3721 if (!val || reg_idx >= ACA_REG_IDX_COUNT)
3722 return -EINVAL;
3723
3724 ret = smu_v13_0_6_aca_bank_dump(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
3725 if (ret)
3726 return ret;
3727
3728 *val = (u64)data[1] << 32 | data[0];
3729
3730 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3731 type == ACA_SMU_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
3732
3733 return 0;
3734 }
3735
aca_smu_get_valid_aca_bank(struct amdgpu_device * adev,enum aca_smu_type type,int idx,struct aca_bank * bank)3736 static int aca_smu_get_valid_aca_bank(struct amdgpu_device *adev,
3737 enum aca_smu_type type, int idx, struct aca_bank *bank)
3738 {
3739 int i, ret, count;
3740
3741 count = min_t(int, 16, ARRAY_SIZE(bank->regs));
3742 for (i = 0; i < count; i++) {
3743 ret = aca_bank_read_reg(adev, type, idx, i, &bank->regs[i]);
3744 if (ret)
3745 return ret;
3746 }
3747
3748 return 0;
3749 }
3750
aca_smu_parse_error_code(struct amdgpu_device * adev,struct aca_bank * bank)3751 static int aca_smu_parse_error_code(struct amdgpu_device *adev, struct aca_bank *bank)
3752 {
3753 struct smu_context *smu = adev->powerplay.pp_handle;
3754 int error_code;
3755
3756 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(ACA_SYND)))
3757 error_code = ACA_REG__SYND__ERRORINFORMATION(bank->regs[ACA_REG_IDX_SYND]);
3758 else
3759 error_code = ACA_REG__STATUS__ERRORCODE(bank->regs[ACA_REG_IDX_STATUS]);
3760
3761 return error_code & 0xff;
3762 }
3763
3764 static const struct aca_smu_funcs smu_v13_0_6_aca_smu_funcs = {
3765 .max_ue_bank_count = 12,
3766 .max_ce_bank_count = 12,
3767 .set_debug_mode = aca_smu_set_debug_mode,
3768 .get_valid_aca_count = aca_smu_get_valid_aca_count,
3769 .get_valid_aca_bank = aca_smu_get_valid_aca_bank,
3770 .parse_error_code = aca_smu_parse_error_code,
3771 };
3772
3773 static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
3774 /* init dpm */
3775 .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask,
3776 /* dpm/clk tables */
3777 .set_default_dpm_table = smu_v13_0_6_set_default_dpm_table,
3778 .populate_umd_state_clk = smu_v13_0_6_populate_umd_state_clk,
3779 .print_clk_levels = smu_v13_0_6_print_clk_levels,
3780 .force_clk_levels = smu_v13_0_6_force_clk_levels,
3781 .read_sensor = smu_v13_0_6_read_sensor,
3782 .set_performance_level = smu_v13_0_6_set_performance_level,
3783 .get_power_limit = smu_v13_0_6_get_power_limit,
3784 .is_dpm_running = smu_v13_0_6_is_dpm_running,
3785 .get_unique_id = smu_v13_0_6_get_unique_id,
3786 .init_microcode = smu_v13_0_6_init_microcode,
3787 .fini_microcode = smu_v13_0_fini_microcode,
3788 .init_smc_tables = smu_v13_0_6_init_smc_tables,
3789 .fini_smc_tables = smu_v13_0_fini_smc_tables,
3790 .init_power = smu_v13_0_init_power,
3791 .fini_power = smu_v13_0_fini_power,
3792 .check_fw_status = smu_v13_0_6_check_fw_status,
3793 /* pptable related */
3794 .check_fw_version = smu_v13_0_6_check_fw_version,
3795 .set_driver_table_location = smu_v13_0_set_driver_table_location,
3796 .set_tool_table_location = smu_v13_0_set_tool_table_location,
3797 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
3798 .system_features_control = smu_v13_0_6_system_features_control,
3799 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3800 .send_smc_msg = smu_cmn_send_smc_msg,
3801 .get_enabled_mask = smu_v13_0_6_get_enabled_mask,
3802 .feature_is_enabled = smu_cmn_feature_is_enabled,
3803 .set_power_limit = smu_v13_0_6_set_power_limit,
3804 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
3805 .register_irq_handler = smu_v13_0_6_register_irq_handler,
3806 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
3807 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
3808 .setup_pptable = smu_v13_0_6_setup_pptable,
3809 .get_bamaco_support = smu_v13_0_6_get_bamaco_support,
3810 .get_dpm_ultimate_freq = smu_v13_0_6_get_dpm_ultimate_freq,
3811 .set_soft_freq_limited_range = smu_v13_0_6_set_soft_freq_limited_range,
3812 .od_edit_dpm_table = smu_v13_0_6_usr_edit_dpm_table,
3813 .log_thermal_throttling_event = smu_v13_0_6_log_thermal_throttling_event,
3814 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3815 .get_gpu_metrics = smu_v13_0_6_get_gpu_metrics,
3816 .get_pm_metrics = smu_v13_0_6_get_pm_metrics,
3817 .get_xcp_metrics = smu_v13_0_6_get_xcp_metrics,
3818 .get_thermal_temperature_range = smu_v13_0_6_get_thermal_temperature_range,
3819 .mode1_reset_is_support = smu_v13_0_6_is_mode1_reset_supported,
3820 .link_reset_is_support = smu_v13_0_6_is_link_reset_supported,
3821 .mode1_reset = smu_v13_0_6_mode1_reset,
3822 .mode2_reset = smu_v13_0_6_mode2_reset,
3823 .link_reset = smu_v13_0_6_link_reset,
3824 .wait_for_event = smu_v13_0_wait_for_event,
3825 .i2c_init = smu_v13_0_6_i2c_control_init,
3826 .i2c_fini = smu_v13_0_6_i2c_control_fini,
3827 .send_hbm_bad_pages_num = smu_v13_0_6_smu_send_hbm_bad_page_num,
3828 .send_rma_reason = smu_v13_0_6_send_rma_reason,
3829 .reset_sdma = smu_v13_0_6_reset_sdma,
3830 .reset_sdma_is_supported = smu_v13_0_6_reset_sdma_is_supported,
3831 .dpm_reset_vcn = smu_v13_0_6_reset_vcn,
3832 };
3833
smu_v13_0_6_set_ppt_funcs(struct smu_context * smu)3834 void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)
3835 {
3836 smu->ppt_funcs = &smu_v13_0_6_ppt_funcs;
3837 smu->message_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ?
3838 smu_v13_0_12_message_map : smu_v13_0_6_message_map;
3839 smu->clock_map = smu_v13_0_6_clk_map;
3840 smu->feature_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ?
3841 smu_v13_0_12_feature_mask_map : smu_v13_0_6_feature_mask_map;
3842 smu->table_map = smu_v13_0_6_table_map;
3843 smu->smc_driver_if_version = SMU13_0_6_DRIVER_IF_VERSION;
3844 smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI;
3845 smu_v13_0_set_smu_mailbox_registers(smu);
3846 amdgpu_mca_smu_init_funcs(smu->adev, &smu_v13_0_6_mca_smu_funcs);
3847 amdgpu_aca_set_smu_funcs(smu->adev, &smu_v13_0_6_aca_smu_funcs);
3848 }
3849