1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * es8328.c -- ES8328 ALSA SoC Audio driver 4 * 5 * Copyright 2014 Sutajio Ko-Usagi PTE LTD 6 * 7 * Author: Sean Cross <xobs@kosagi.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/module.h> 13 #include <linux/pm.h> 14 #include <linux/regmap.h> 15 #include <linux/slab.h> 16 #include <linux/regulator/consumer.h> 17 #include <sound/core.h> 18 #include <sound/initval.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include <sound/tlv.h> 23 #include "es8328.h" 24 25 static const unsigned int rates_12288[] = { 26 8000, 12000, 16000, 24000, 32000, 48000, 96000, 27 }; 28 29 static const int ratios_12288[] = { 30 10, 7, 6, 4, 3, 2, 0, 31 }; 32 33 static const struct snd_pcm_hw_constraint_list constraints_12288 = { 34 .count = ARRAY_SIZE(rates_12288), 35 .list = rates_12288, 36 }; 37 38 static const unsigned int rates_11289[] = { 39 8018, 11025, 22050, 44100, 88200, 40 }; 41 42 static const int ratios_11289[] = { 43 9, 7, 4, 2, 0, 44 }; 45 46 static const struct snd_pcm_hw_constraint_list constraints_11289 = { 47 .count = ARRAY_SIZE(rates_11289), 48 .list = rates_11289, 49 }; 50 51 /* regulator supplies for sgtl5000, VDDD is an optional external supply */ 52 enum sgtl5000_regulator_supplies { 53 DVDD, 54 AVDD, 55 PVDD, 56 HPVDD, 57 ES8328_SUPPLY_NUM 58 }; 59 60 /* vddd is optional supply */ 61 static const char * const supply_names[ES8328_SUPPLY_NUM] = { 62 "DVDD", 63 "AVDD", 64 "PVDD", 65 "HPVDD", 66 }; 67 68 #define ES8328_RATES (SNDRV_PCM_RATE_192000 | \ 69 SNDRV_PCM_RATE_96000 | \ 70 SNDRV_PCM_RATE_88200 | \ 71 SNDRV_PCM_RATE_8000_48000) 72 #define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 73 SNDRV_PCM_FMTBIT_S18_3LE | \ 74 SNDRV_PCM_FMTBIT_S20_3LE | \ 75 SNDRV_PCM_FMTBIT_S24_LE | \ 76 SNDRV_PCM_FMTBIT_S32_LE) 77 78 struct es8328_priv { 79 struct regmap *regmap; 80 struct clk *clk; 81 int playback_fs; 82 bool deemph; 83 int mclkdiv2; 84 const struct snd_pcm_hw_constraint_list *sysclk_constraints; 85 const int *mclk_ratios; 86 bool provider; 87 struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM]; 88 }; 89 90 /* 91 * ES8328 Controls 92 */ 93 94 static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert", 95 "L + R Invert"}; 96 static SOC_ENUM_SINGLE_DECL(adcpol, 97 ES8328_ADCCONTROL6, 6, adcpol_txt); 98 99 static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0); 100 static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0); 101 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); 102 static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0); 103 104 static const struct { 105 int rate; 106 unsigned int val; 107 } deemph_settings[] = { 108 { 0, ES8328_DACCONTROL6_DEEMPH_OFF }, 109 { 32000, ES8328_DACCONTROL6_DEEMPH_32k }, 110 { 44100, ES8328_DACCONTROL6_DEEMPH_44_1k }, 111 { 48000, ES8328_DACCONTROL6_DEEMPH_48k }, 112 }; 113 114 static int es8328_set_deemph(struct snd_soc_component *component) 115 { 116 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 117 int val, i, best; 118 119 /* 120 * If we're using deemphasis select the nearest available sample 121 * rate. 122 */ 123 if (es8328->deemph) { 124 best = 0; 125 for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) { 126 if (abs(deemph_settings[i].rate - es8328->playback_fs) < 127 abs(deemph_settings[best].rate - es8328->playback_fs)) 128 best = i; 129 } 130 131 val = deemph_settings[best].val; 132 } else { 133 val = ES8328_DACCONTROL6_DEEMPH_OFF; 134 } 135 136 dev_dbg(component->dev, "Set deemphasis %d\n", val); 137 138 return snd_soc_component_update_bits(component, ES8328_DACCONTROL6, 139 ES8328_DACCONTROL6_DEEMPH_MASK, val); 140 } 141 142 static int es8328_get_deemph(struct snd_kcontrol *kcontrol, 143 struct snd_ctl_elem_value *ucontrol) 144 { 145 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 146 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 147 148 ucontrol->value.integer.value[0] = es8328->deemph; 149 return 0; 150 } 151 152 static int es8328_put_deemph(struct snd_kcontrol *kcontrol, 153 struct snd_ctl_elem_value *ucontrol) 154 { 155 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 156 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 157 unsigned int deemph = ucontrol->value.integer.value[0]; 158 int ret; 159 160 if (deemph > 1) 161 return -EINVAL; 162 163 if (es8328->deemph == deemph) 164 return 0; 165 166 es8328->deemph = deemph; 167 ret = es8328_set_deemph(component); 168 if (ret < 0) 169 return ret; 170 171 return 1; 172 } 173 174 175 176 static const struct snd_kcontrol_new es8328_snd_controls[] = { 177 SOC_DOUBLE_R_TLV("Capture Digital Volume", 178 ES8328_ADCCONTROL8, ES8328_ADCCONTROL9, 179 0, 0xc0, 1, dac_adc_tlv), 180 SOC_SINGLE("Capture ZC Switch", ES8328_ADCCONTROL7, 6, 1, 0), 181 182 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, 183 es8328_get_deemph, es8328_put_deemph), 184 185 SOC_ENUM("Capture Polarity", adcpol), 186 187 SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", 188 ES8328_DACCONTROL17, 3, 7, 1, bypass_tlv), 189 SOC_SINGLE_TLV("Left Mixer Right Bypass Volume", 190 ES8328_DACCONTROL19, 3, 7, 1, bypass_tlv), 191 SOC_SINGLE_TLV("Right Mixer Left Bypass Volume", 192 ES8328_DACCONTROL18, 3, 7, 1, bypass_tlv), 193 SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", 194 ES8328_DACCONTROL20, 3, 7, 1, bypass_tlv), 195 196 SOC_DOUBLE_R_TLV("PCM Volume", 197 ES8328_LDACVOL, ES8328_RDACVOL, 198 0, ES8328_DACVOL_MAX, 1, dac_adc_tlv), 199 200 SOC_DOUBLE_R_TLV("Output 1 Playback Volume", 201 ES8328_LOUT1VOL, ES8328_ROUT1VOL, 202 0, ES8328_OUT1VOL_MAX, 0, play_tlv), 203 204 SOC_DOUBLE_R_TLV("Output 2 Playback Volume", 205 ES8328_LOUT2VOL, ES8328_ROUT2VOL, 206 0, ES8328_OUT2VOL_MAX, 0, play_tlv), 207 208 SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1, 209 4, 0, 8, 0, mic_tlv), 210 }; 211 212 /* 213 * DAPM Controls 214 */ 215 216 static const char * const es8328_line_texts[] = { 217 "Line 1", "Line 2", "PGA", "Differential"}; 218 219 static const struct soc_enum es8328_lline_enum = 220 SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 3, 221 ARRAY_SIZE(es8328_line_texts), 222 es8328_line_texts); 223 static const struct snd_kcontrol_new es8328_left_line_controls = 224 SOC_DAPM_ENUM("Route", es8328_lline_enum); 225 226 static const struct soc_enum es8328_rline_enum = 227 SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 0, 228 ARRAY_SIZE(es8328_line_texts), 229 es8328_line_texts); 230 static const struct snd_kcontrol_new es8328_right_line_controls = 231 SOC_DAPM_ENUM("Route", es8328_rline_enum); 232 233 /* Left Mixer */ 234 static const struct snd_kcontrol_new es8328_left_mixer_controls[] = { 235 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0), 236 SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0), 237 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0), 238 }; 239 240 /* Right Mixer */ 241 static const struct snd_kcontrol_new es8328_right_mixer_controls[] = { 242 SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0), 243 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0), 244 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0), 245 }; 246 247 static const char * const es8328_pga_sel[] = { 248 "Line 1", "Line 2", "Line 3", "Differential"}; 249 250 /* Left PGA Mux */ 251 static const struct soc_enum es8328_lpga_enum = 252 SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 6, 253 ARRAY_SIZE(es8328_pga_sel), 254 es8328_pga_sel); 255 static const struct snd_kcontrol_new es8328_left_pga_controls = 256 SOC_DAPM_ENUM("Route", es8328_lpga_enum); 257 258 /* Right PGA Mux */ 259 static const struct soc_enum es8328_rpga_enum = 260 SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 4, 261 ARRAY_SIZE(es8328_pga_sel), 262 es8328_pga_sel); 263 static const struct snd_kcontrol_new es8328_right_pga_controls = 264 SOC_DAPM_ENUM("Route", es8328_rpga_enum); 265 266 /* Differential Mux */ 267 static const char * const es8328_diff_sel[] = {"Line 1", "Line 2"}; 268 static SOC_ENUM_SINGLE_DECL(diffmux, 269 ES8328_ADCCONTROL3, 7, es8328_diff_sel); 270 static const struct snd_kcontrol_new es8328_diffmux_controls = 271 SOC_DAPM_ENUM("Route", diffmux); 272 273 /* Mono ADC Mux */ 274 static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)", 275 "Mono (Right)", "Digital Mono"}; 276 static SOC_ENUM_SINGLE_DECL(monomux, 277 ES8328_ADCCONTROL3, 3, es8328_mono_mux); 278 static const struct snd_kcontrol_new es8328_monomux_controls = 279 SOC_DAPM_ENUM("Route", monomux); 280 281 static const struct snd_soc_dapm_widget es8328_dapm_widgets[] = { 282 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0, 283 &es8328_diffmux_controls), 284 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0, 285 &es8328_monomux_controls), 286 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0, 287 &es8328_monomux_controls), 288 289 SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER, 290 ES8328_ADCPOWER_AINL_OFF, 1, 291 &es8328_left_pga_controls), 292 SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER, 293 ES8328_ADCPOWER_AINR_OFF, 1, 294 &es8328_right_pga_controls), 295 296 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0, 297 &es8328_left_line_controls), 298 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0, 299 &es8328_right_line_controls), 300 301 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER, 302 ES8328_ADCPOWER_ADCR_OFF, 1), 303 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER, 304 ES8328_ADCPOWER_ADCL_OFF, 1), 305 306 SND_SOC_DAPM_SUPPLY("Mic Bias", ES8328_ADCPOWER, 307 ES8328_ADCPOWER_MIC_BIAS_OFF, 1, NULL, 0), 308 SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8328_ADCPOWER, 309 ES8328_ADCPOWER_ADC_BIAS_GEN_OFF, 1, NULL, 0), 310 311 SND_SOC_DAPM_SUPPLY("DAC STM", ES8328_CHIPPOWER, 312 ES8328_CHIPPOWER_DACSTM_RESET, 1, NULL, 0), 313 SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER, 314 ES8328_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0), 315 316 SND_SOC_DAPM_SUPPLY("DAC DIG", ES8328_CHIPPOWER, 317 ES8328_CHIPPOWER_DACDIG_OFF, 1, NULL, 0), 318 SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER, 319 ES8328_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0), 320 321 SND_SOC_DAPM_SUPPLY("DAC DLL", ES8328_CHIPPOWER, 322 ES8328_CHIPPOWER_DACDLL_OFF, 1, NULL, 0), 323 SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER, 324 ES8328_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0), 325 326 SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER, 327 ES8328_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0), 328 SND_SOC_DAPM_SUPPLY("DAC Vref", ES8328_CHIPPOWER, 329 ES8328_CHIPPOWER_DACVREF_OFF, 1, NULL, 0), 330 331 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER, 332 ES8328_DACPOWER_RDAC_OFF, 1), 333 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER, 334 ES8328_DACPOWER_LDAC_OFF, 1), 335 336 SND_SOC_DAPM_MIXER("Left Mixer", ES8328_DACCONTROL17, 7, 0, 337 &es8328_left_mixer_controls[0], 338 ARRAY_SIZE(es8328_left_mixer_controls)), 339 SND_SOC_DAPM_MIXER("Right Mixer", ES8328_DACCONTROL20, 7, 0, 340 &es8328_right_mixer_controls[0], 341 ARRAY_SIZE(es8328_right_mixer_controls)), 342 343 SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER, 344 ES8328_DACPOWER_ROUT2_ON, 0, NULL, 0), 345 SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER, 346 ES8328_DACPOWER_LOUT2_ON, 0, NULL, 0), 347 SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER, 348 ES8328_DACPOWER_ROUT1_ON, 0, NULL, 0), 349 SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER, 350 ES8328_DACPOWER_LOUT1_ON, 0, NULL, 0), 351 352 SND_SOC_DAPM_OUTPUT("LOUT1"), 353 SND_SOC_DAPM_OUTPUT("ROUT1"), 354 SND_SOC_DAPM_OUTPUT("LOUT2"), 355 SND_SOC_DAPM_OUTPUT("ROUT2"), 356 357 SND_SOC_DAPM_INPUT("LINPUT1"), 358 SND_SOC_DAPM_INPUT("LINPUT2"), 359 SND_SOC_DAPM_INPUT("RINPUT1"), 360 SND_SOC_DAPM_INPUT("RINPUT2"), 361 }; 362 363 static const struct snd_soc_dapm_route es8328_dapm_routes[] = { 364 365 { "Left Line Mux", "Line 1", "LINPUT1" }, 366 { "Left Line Mux", "Line 2", "LINPUT2" }, 367 { "Left Line Mux", "PGA", "Left PGA Mux" }, 368 { "Left Line Mux", "Differential", "Differential Mux" }, 369 370 { "Right Line Mux", "Line 1", "RINPUT1" }, 371 { "Right Line Mux", "Line 2", "RINPUT2" }, 372 { "Right Line Mux", "PGA", "Right PGA Mux" }, 373 { "Right Line Mux", "Differential", "Differential Mux" }, 374 375 { "Left PGA Mux", "Line 1", "LINPUT1" }, 376 { "Left PGA Mux", "Line 2", "LINPUT2" }, 377 { "Left PGA Mux", "Differential", "Differential Mux" }, 378 379 { "Right PGA Mux", "Line 1", "RINPUT1" }, 380 { "Right PGA Mux", "Line 2", "RINPUT2" }, 381 { "Right PGA Mux", "Differential", "Differential Mux" }, 382 383 { "Differential Mux", "Line 1", "LINPUT1" }, 384 { "Differential Mux", "Line 1", "RINPUT1" }, 385 { "Differential Mux", "Line 2", "LINPUT2" }, 386 { "Differential Mux", "Line 2", "RINPUT2" }, 387 388 { "Left ADC Mux", "Stereo", "Left PGA Mux" }, 389 { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" }, 390 { "Left ADC Mux", "Digital Mono", "Left PGA Mux" }, 391 392 { "Right ADC Mux", "Stereo", "Right PGA Mux" }, 393 { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" }, 394 { "Right ADC Mux", "Digital Mono", "Right PGA Mux" }, 395 396 { "Left ADC", NULL, "Left ADC Mux" }, 397 { "Right ADC", NULL, "Right ADC Mux" }, 398 399 { "ADC DIG", NULL, "ADC STM" }, 400 { "ADC DIG", NULL, "ADC Vref" }, 401 { "ADC DIG", NULL, "ADC DLL" }, 402 403 { "Left ADC", NULL, "ADC DIG" }, 404 { "Right ADC", NULL, "ADC DIG" }, 405 406 { "Mic Bias", NULL, "Mic Bias Gen" }, 407 408 { "Left Mixer", NULL, "Left DAC" }, 409 { "Left Mixer", "Left Bypass Switch", "Left Line Mux" }, 410 { "Left Mixer", "Right Playback Switch", "Right DAC" }, 411 { "Left Mixer", "Right Bypass Switch", "Right Line Mux" }, 412 413 { "Right Mixer", "Left Playback Switch", "Left DAC" }, 414 { "Right Mixer", "Left Bypass Switch", "Left Line Mux" }, 415 { "Right Mixer", NULL, "Right DAC" }, 416 { "Right Mixer", "Right Bypass Switch", "Right Line Mux" }, 417 418 { "DAC DIG", NULL, "DAC STM" }, 419 { "DAC DIG", NULL, "DAC Vref" }, 420 { "DAC DIG", NULL, "DAC DLL" }, 421 422 { "Left DAC", NULL, "DAC DIG" }, 423 { "Right DAC", NULL, "DAC DIG" }, 424 425 { "Left Out 1", NULL, "Left Mixer" }, 426 { "LOUT1", NULL, "Left Out 1" }, 427 { "Right Out 1", NULL, "Right Mixer" }, 428 { "ROUT1", NULL, "Right Out 1" }, 429 430 { "Left Out 2", NULL, "Left Mixer" }, 431 { "LOUT2", NULL, "Left Out 2" }, 432 { "Right Out 2", NULL, "Right Mixer" }, 433 { "ROUT2", NULL, "Right Out 2" }, 434 }; 435 436 static int es8328_mute(struct snd_soc_dai *dai, int mute, int direction) 437 { 438 return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3, 439 ES8328_DACCONTROL3_DACMUTE, 440 mute ? ES8328_DACCONTROL3_DACMUTE : 0); 441 } 442 443 static int es8328_startup(struct snd_pcm_substream *substream, 444 struct snd_soc_dai *dai) 445 { 446 struct snd_soc_component *component = dai->component; 447 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 448 449 if (es8328->provider && es8328->sysclk_constraints) 450 snd_pcm_hw_constraint_list(substream->runtime, 0, 451 SNDRV_PCM_HW_PARAM_RATE, 452 es8328->sysclk_constraints); 453 454 return 0; 455 } 456 457 static int es8328_hw_params(struct snd_pcm_substream *substream, 458 struct snd_pcm_hw_params *params, 459 struct snd_soc_dai *dai) 460 { 461 struct snd_soc_component *component = dai->component; 462 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 463 int ret; 464 int i; 465 int reg; 466 int wl; 467 int ratio; 468 469 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 470 reg = ES8328_DACCONTROL2; 471 else 472 reg = ES8328_ADCCONTROL5; 473 474 if (es8328->provider) { 475 if (!es8328->sysclk_constraints) { 476 dev_err(component->dev, "No MCLK configured\n"); 477 return -EINVAL; 478 } 479 480 for (i = 0; i < es8328->sysclk_constraints->count; i++) 481 if (es8328->sysclk_constraints->list[i] == 482 params_rate(params)) 483 break; 484 485 if (i == es8328->sysclk_constraints->count) { 486 dev_err(component->dev, 487 "LRCLK %d unsupported with current clock\n", 488 params_rate(params)); 489 return -EINVAL; 490 } 491 ratio = es8328->mclk_ratios[i]; 492 } else { 493 ratio = 0; 494 es8328->mclkdiv2 = 0; 495 } 496 497 ret = snd_soc_component_update_bits(component, ES8328_MASTERMODE, 498 ES8328_MASTERMODE_MCLKDIV2, 499 es8328->mclkdiv2 ? 500 ES8328_MASTERMODE_MCLKDIV2 : 0); 501 if (ret < 0) 502 return ret; 503 504 switch (params_width(params)) { 505 case 16: 506 wl = 3; 507 break; 508 case 18: 509 wl = 2; 510 break; 511 case 20: 512 wl = 1; 513 break; 514 case 24: 515 wl = 0; 516 break; 517 case 32: 518 wl = 4; 519 break; 520 default: 521 return -EINVAL; 522 } 523 524 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 525 ret = snd_soc_component_update_bits(component, ES8328_DACCONTROL1, 526 ES8328_DACCONTROL1_DACWL_MASK, 527 wl << ES8328_DACCONTROL1_DACWL_SHIFT); 528 if (ret < 0) 529 return ret; 530 531 es8328->playback_fs = params_rate(params); 532 ret = es8328_set_deemph(component); 533 if (ret < 0) 534 return ret; 535 } else { 536 ret = snd_soc_component_update_bits(component, ES8328_ADCCONTROL4, 537 ES8328_ADCCONTROL4_ADCWL_MASK, 538 wl << ES8328_ADCCONTROL4_ADCWL_SHIFT); 539 if (ret < 0) 540 return ret; 541 } 542 543 ret = snd_soc_component_update_bits(component, reg, ES8328_RATEMASK, ratio); 544 if (ret < 0) 545 return ret; 546 return 0; 547 } 548 549 static int es8328_set_sysclk(struct snd_soc_dai *codec_dai, 550 int clk_id, unsigned int freq, int dir) 551 { 552 struct snd_soc_component *component = codec_dai->component; 553 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 554 int mclkdiv2 = 0; 555 unsigned int round_freq; 556 557 /* 558 * Allow a small tolerance for frequencies within 100hz. Note 559 * this value is chosen arbitrarily. 560 */ 561 round_freq = DIV_ROUND_CLOSEST(freq, 100) * 100; 562 563 switch (round_freq) { 564 case 0: 565 es8328->sysclk_constraints = NULL; 566 es8328->mclk_ratios = NULL; 567 break; 568 case 22579200: 569 mclkdiv2 = 1; 570 fallthrough; 571 case 11289600: 572 es8328->sysclk_constraints = &constraints_11289; 573 es8328->mclk_ratios = ratios_11289; 574 break; 575 case 24576000: 576 mclkdiv2 = 1; 577 fallthrough; 578 case 12288000: 579 es8328->sysclk_constraints = &constraints_12288; 580 es8328->mclk_ratios = ratios_12288; 581 break; 582 default: 583 return -EINVAL; 584 } 585 586 es8328->mclkdiv2 = mclkdiv2; 587 return 0; 588 } 589 590 static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai, 591 unsigned int fmt) 592 { 593 struct snd_soc_component *component = codec_dai->component; 594 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 595 int ret; 596 u8 dac_mode = 0; 597 u8 adc_mode = 0; 598 599 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 600 case SND_SOC_DAIFMT_CBP_CFP: 601 /* Master serial port mode, with BCLK generated automatically */ 602 ret = snd_soc_component_update_bits(component, ES8328_MASTERMODE, 603 ES8328_MASTERMODE_MSC, 604 ES8328_MASTERMODE_MSC); 605 if (ret < 0) 606 return ret; 607 es8328->provider = true; 608 break; 609 case SND_SOC_DAIFMT_CBC_CFC: 610 /* Slave serial port mode */ 611 ret = snd_soc_component_update_bits(component, ES8328_MASTERMODE, 612 ES8328_MASTERMODE_MSC, 0); 613 if (ret < 0) 614 return ret; 615 es8328->provider = false; 616 break; 617 default: 618 return -EINVAL; 619 } 620 621 /* interface format */ 622 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 623 case SND_SOC_DAIFMT_I2S: 624 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S; 625 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S; 626 break; 627 case SND_SOC_DAIFMT_RIGHT_J: 628 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST; 629 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST; 630 break; 631 case SND_SOC_DAIFMT_LEFT_J: 632 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST; 633 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST; 634 break; 635 default: 636 return -EINVAL; 637 } 638 639 /* clock inversion */ 640 if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) 641 return -EINVAL; 642 643 ret = snd_soc_component_update_bits(component, ES8328_DACCONTROL1, 644 ES8328_DACCONTROL1_DACFORMAT_MASK, 645 dac_mode); 646 if (ret < 0) 647 return ret; 648 649 ret = snd_soc_component_update_bits(component, ES8328_ADCCONTROL4, 650 ES8328_ADCCONTROL4_ADCFORMAT_MASK, 651 adc_mode); 652 if (ret < 0) 653 return ret; 654 655 return 0; 656 } 657 658 static int es8328_set_bias_level(struct snd_soc_component *component, 659 enum snd_soc_bias_level level) 660 { 661 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 662 int ret; 663 664 switch (level) { 665 case SND_SOC_BIAS_ON: 666 break; 667 668 case SND_SOC_BIAS_PREPARE: 669 /* VREF, VMID=2x50k, digital enabled */ 670 ret = snd_soc_component_write(component, ES8328_CHIPPOWER, 0); 671 if (ret < 0) 672 return ret; 673 674 ret = snd_soc_component_update_bits(component, ES8328_CONTROL1, 675 ES8328_CONTROL1_VMIDSEL_MASK | 676 ES8328_CONTROL1_ENREF, 677 ES8328_CONTROL1_VMIDSEL_50k | 678 ES8328_CONTROL1_ENREF); 679 if (ret < 0) 680 return ret; 681 break; 682 683 case SND_SOC_BIAS_STANDBY: 684 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 685 ret = snd_soc_component_update_bits(component, ES8328_CONTROL1, 686 ES8328_CONTROL1_VMIDSEL_MASK | 687 ES8328_CONTROL1_ENREF, 688 ES8328_CONTROL1_VMIDSEL_5k | 689 ES8328_CONTROL1_ENREF); 690 if (ret < 0) 691 return ret; 692 693 /* Charge caps */ 694 msleep(100); 695 } 696 697 ret = snd_soc_component_write(component, ES8328_CONTROL2, 698 ES8328_CONTROL2_OVERCURRENT_ON | 699 ES8328_CONTROL2_THERMAL_SHUTDOWN_ON); 700 if (ret < 0) 701 return ret; 702 703 /* VREF, VMID=2*500k, digital stopped */ 704 ret = snd_soc_component_update_bits(component, ES8328_CONTROL1, 705 ES8328_CONTROL1_VMIDSEL_MASK | 706 ES8328_CONTROL1_ENREF, 707 ES8328_CONTROL1_VMIDSEL_500k | 708 ES8328_CONTROL1_ENREF); 709 if (ret < 0) 710 return ret; 711 break; 712 713 case SND_SOC_BIAS_OFF: 714 ret = snd_soc_component_update_bits(component, ES8328_CONTROL1, 715 ES8328_CONTROL1_VMIDSEL_MASK | 716 ES8328_CONTROL1_ENREF, 717 0); 718 if (ret < 0) 719 return ret; 720 break; 721 } 722 return 0; 723 } 724 725 static const struct snd_soc_dai_ops es8328_dai_ops = { 726 .startup = es8328_startup, 727 .hw_params = es8328_hw_params, 728 .mute_stream = es8328_mute, 729 .set_sysclk = es8328_set_sysclk, 730 .set_fmt = es8328_set_dai_fmt, 731 .no_capture_mute = 1, 732 }; 733 734 static struct snd_soc_dai_driver es8328_dai = { 735 .name = "es8328-hifi-analog", 736 .playback = { 737 .stream_name = "Playback", 738 .channels_min = 2, 739 .channels_max = 2, 740 .rates = ES8328_RATES, 741 .formats = ES8328_FORMATS, 742 }, 743 .capture = { 744 .stream_name = "Capture", 745 .channels_min = 2, 746 .channels_max = 2, 747 .rates = ES8328_RATES, 748 .formats = ES8328_FORMATS, 749 }, 750 .ops = &es8328_dai_ops, 751 .symmetric_rate = 1, 752 }; 753 754 static int es8328_suspend(struct snd_soc_component *component) 755 { 756 struct es8328_priv *es8328; 757 int ret; 758 759 es8328 = snd_soc_component_get_drvdata(component); 760 761 clk_disable_unprepare(es8328->clk); 762 763 ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), 764 es8328->supplies); 765 if (ret) { 766 dev_err(component->dev, "unable to disable regulators\n"); 767 return ret; 768 } 769 return 0; 770 } 771 772 static int es8328_resume(struct snd_soc_component *component) 773 { 774 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component); 775 int ret; 776 777 ret = clk_prepare_enable(es8328->clk); 778 if (ret) { 779 dev_err(component->dev, "unable to enable clock\n"); 780 return ret; 781 } 782 783 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), 784 es8328->supplies); 785 if (ret) { 786 dev_err(component->dev, "unable to enable regulators\n"); 787 goto err_clk; 788 } 789 790 regcache_mark_dirty(es8328->regmap); 791 ret = regcache_sync(es8328->regmap); 792 if (ret) { 793 dev_err(component->dev, "unable to sync regcache\n"); 794 goto err_regulators; 795 } 796 797 return 0; 798 799 err_regulators: 800 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), es8328->supplies); 801 err_clk: 802 clk_disable_unprepare(es8328->clk); 803 return ret; 804 } 805 806 static int es8328_component_probe(struct snd_soc_component *component) 807 { 808 struct es8328_priv *es8328; 809 int ret; 810 811 es8328 = snd_soc_component_get_drvdata(component); 812 813 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), 814 es8328->supplies); 815 if (ret) { 816 dev_err(component->dev, "unable to enable regulators\n"); 817 return ret; 818 } 819 820 /* Setup clocks */ 821 es8328->clk = devm_clk_get(component->dev, NULL); 822 if (IS_ERR(es8328->clk)) { 823 dev_err(component->dev, "codec clock missing or invalid\n"); 824 ret = PTR_ERR(es8328->clk); 825 goto clk_fail; 826 } 827 828 ret = clk_prepare_enable(es8328->clk); 829 if (ret) { 830 dev_err(component->dev, "unable to prepare codec clk\n"); 831 goto clk_fail; 832 } 833 834 return 0; 835 836 clk_fail: 837 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), 838 es8328->supplies); 839 return ret; 840 } 841 842 static void es8328_remove(struct snd_soc_component *component) 843 { 844 struct es8328_priv *es8328; 845 846 es8328 = snd_soc_component_get_drvdata(component); 847 848 clk_disable_unprepare(es8328->clk); 849 850 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), 851 es8328->supplies); 852 } 853 854 const struct regmap_config es8328_regmap_config = { 855 .reg_bits = 8, 856 .val_bits = 8, 857 .max_register = ES8328_REG_MAX, 858 .cache_type = REGCACHE_MAPLE, 859 .use_single_read = true, 860 .use_single_write = true, 861 }; 862 EXPORT_SYMBOL_GPL(es8328_regmap_config); 863 864 static const struct snd_soc_component_driver es8328_component_driver = { 865 .probe = es8328_component_probe, 866 .remove = es8328_remove, 867 .suspend = es8328_suspend, 868 .resume = es8328_resume, 869 .set_bias_level = es8328_set_bias_level, 870 .controls = es8328_snd_controls, 871 .num_controls = ARRAY_SIZE(es8328_snd_controls), 872 .dapm_widgets = es8328_dapm_widgets, 873 .num_dapm_widgets = ARRAY_SIZE(es8328_dapm_widgets), 874 .dapm_routes = es8328_dapm_routes, 875 .num_dapm_routes = ARRAY_SIZE(es8328_dapm_routes), 876 .suspend_bias_off = 1, 877 .idle_bias_on = 1, 878 .use_pmdown_time = 1, 879 .endianness = 1, 880 }; 881 882 int es8328_probe(struct device *dev, struct regmap *regmap) 883 { 884 struct es8328_priv *es8328; 885 int ret; 886 int i; 887 888 if (IS_ERR(regmap)) 889 return PTR_ERR(regmap); 890 891 es8328 = devm_kzalloc(dev, sizeof(*es8328), GFP_KERNEL); 892 if (es8328 == NULL) 893 return -ENOMEM; 894 895 es8328->regmap = regmap; 896 897 for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++) 898 es8328->supplies[i].supply = supply_names[i]; 899 900 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies), 901 es8328->supplies); 902 if (ret) { 903 dev_err(dev, "unable to get regulators\n"); 904 return ret; 905 } 906 907 dev_set_drvdata(dev, es8328); 908 909 return devm_snd_soc_register_component(dev, 910 &es8328_component_driver, &es8328_dai, 1); 911 } 912 EXPORT_SYMBOL_GPL(es8328_probe); 913 914 MODULE_DESCRIPTION("ASoC ES8328 driver"); 915 MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>"); 916 MODULE_LICENSE("GPL"); 917