1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // es8326.c -- es8326 ALSA SoC audio driver 4 // Copyright Everest Semiconductor Co., Ltd 5 // 6 // Authors: David Yang <yangxiaohua@everest-semi.com> 7 // 8 9 #include <linux/clk.h> 10 #include <linux/i2c.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/module.h> 14 #include <sound/jack.h> 15 #include <sound/pcm_params.h> 16 #include <sound/soc.h> 17 #include <sound/soc-dapm.h> 18 #include <sound/tlv.h> 19 #include "es8326.h" 20 21 struct es8326_priv { 22 struct clk *mclk; 23 struct i2c_client *i2c; 24 struct regmap *regmap; 25 struct snd_soc_component *component; 26 struct delayed_work jack_detect_work; 27 struct delayed_work button_press_work; 28 struct snd_soc_jack *jack; 29 int irq; 30 /* The lock protects the situation that an irq is generated 31 * while enabling or disabling or during an irq. 32 */ 33 struct mutex lock; 34 u8 jack_pol; 35 u8 interrupt_src; 36 u8 interrupt_clk; 37 u8 hpl_vol; 38 u8 hpr_vol; 39 bool jd_inverted; 40 unsigned int sysclk; 41 42 bool calibrated; 43 int version; 44 int hp; 45 int jack_remove_retry; 46 }; 47 48 static int es8326_crosstalk1_get(struct snd_kcontrol *kcontrol, 49 struct snd_ctl_elem_value *ucontrol) 50 { 51 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 52 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 53 unsigned int crosstalk_h, crosstalk_l; 54 unsigned int crosstalk; 55 56 regmap_read(es8326->regmap, ES8326_DAC_RAMPRATE, &crosstalk_h); 57 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l); 58 crosstalk_h &= 0x20; 59 crosstalk_l &= 0xf0; 60 crosstalk = crosstalk_h >> 1 | crosstalk_l >> 4; 61 ucontrol->value.integer.value[0] = crosstalk; 62 63 return 0; 64 } 65 66 static int es8326_crosstalk1_set(struct snd_kcontrol *kcontrol, 67 struct snd_ctl_elem_value *ucontrol) 68 { 69 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 70 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 71 unsigned int crosstalk_h, crosstalk_l; 72 unsigned int crosstalk; 73 74 crosstalk = ucontrol->value.integer.value[0]; 75 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l); 76 crosstalk_h = (crosstalk & 0x10) << 1; 77 crosstalk_l &= 0x0f; 78 crosstalk_l |= (crosstalk & 0x0f) << 4; 79 regmap_update_bits(es8326->regmap, ES8326_DAC_RAMPRATE, 80 0x20, crosstalk_h); 81 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, crosstalk_l); 82 83 return 0; 84 } 85 86 static int es8326_crosstalk2_get(struct snd_kcontrol *kcontrol, 87 struct snd_ctl_elem_value *ucontrol) 88 { 89 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 90 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 91 unsigned int crosstalk_h, crosstalk_l; 92 unsigned int crosstalk; 93 94 regmap_read(es8326->regmap, ES8326_DAC_RAMPRATE, &crosstalk_h); 95 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l); 96 crosstalk_h &= 0x10; 97 crosstalk_l &= 0x0f; 98 crosstalk = crosstalk_h | crosstalk_l; 99 ucontrol->value.integer.value[0] = crosstalk; 100 101 return 0; 102 } 103 104 static int es8326_crosstalk2_set(struct snd_kcontrol *kcontrol, 105 struct snd_ctl_elem_value *ucontrol) 106 { 107 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 108 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 109 unsigned int crosstalk_h, crosstalk_l; 110 unsigned int crosstalk; 111 112 crosstalk = ucontrol->value.integer.value[0]; 113 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l); 114 crosstalk_h = crosstalk & 0x10; 115 crosstalk_l &= 0xf0; 116 crosstalk_l |= crosstalk & 0x0f; 117 regmap_update_bits(es8326->regmap, ES8326_DAC_RAMPRATE, 118 0x10, crosstalk_h); 119 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, crosstalk_l); 120 121 return 0; 122 } 123 124 static int es8326_hplvol_get(struct snd_kcontrol *kcontrol, 125 struct snd_ctl_elem_value *ucontrol) 126 { 127 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 128 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 129 130 ucontrol->value.integer.value[0] = es8326->hpl_vol; 131 132 return 0; 133 } 134 135 static int es8326_hplvol_set(struct snd_kcontrol *kcontrol, 136 struct snd_ctl_elem_value *ucontrol) 137 { 138 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 139 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 140 unsigned int hp_vol; 141 142 hp_vol = ucontrol->value.integer.value[0]; 143 if (hp_vol > 5) 144 return -EINVAL; 145 if (es8326->hpl_vol != hp_vol) { 146 es8326->hpl_vol = hp_vol; 147 if (hp_vol >= 3) 148 hp_vol++; 149 regmap_update_bits(es8326->regmap, ES8326_HP_VOL, 150 0x70, (hp_vol << 4)); 151 return 1; 152 } 153 154 return 0; 155 } 156 157 static int es8326_hprvol_get(struct snd_kcontrol *kcontrol, 158 struct snd_ctl_elem_value *ucontrol) 159 { 160 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 161 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 162 163 ucontrol->value.integer.value[0] = es8326->hpr_vol; 164 165 return 0; 166 } 167 168 static int es8326_hprvol_set(struct snd_kcontrol *kcontrol, 169 struct snd_ctl_elem_value *ucontrol) 170 { 171 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 172 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 173 unsigned int hp_vol; 174 175 hp_vol = ucontrol->value.integer.value[0]; 176 if (hp_vol > 5) 177 return -EINVAL; 178 if (es8326->hpr_vol != hp_vol) { 179 es8326->hpr_vol = hp_vol; 180 if (hp_vol >= 3) 181 hp_vol++; 182 regmap_update_bits(es8326->regmap, ES8326_HP_VOL, 183 0x07, hp_vol); 184 return 1; 185 } 186 187 return 0; 188 } 189 190 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dac_vol_tlv, -9550, 50, 0); 191 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_vol_tlv, -9550, 50, 0); 192 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_analog_pga_tlv, 0, 300, 0); 193 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_pga_tlv, 0, 600, 0); 194 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(softramp_rate, 0, 100, 0); 195 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_target_tlv, -3200, 200, 0); 196 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_recovery_tlv, -125, 250, 0); 197 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dre_gain_tlv, -9550, 400, 0); 198 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dre_gate_tlv, -9600, 600, 0); 199 200 static const char *const winsize[] = { 201 "0.25db/2 LRCK", 202 "0.25db/4 LRCK", 203 "0.25db/8 LRCK", 204 "0.25db/16 LRCK", 205 "0.25db/32 LRCK", 206 "0.25db/64 LRCK", 207 "0.25db/128 LRCK", 208 "0.25db/256 LRCK", 209 "0.25db/512 LRCK", 210 "0.25db/1024 LRCK", 211 "0.25db/2048 LRCK", 212 "0.25db/4096 LRCK", 213 "0.25db/8192 LRCK", 214 "0.25db/16384 LRCK", 215 "0.25db/32768 LRCK", 216 "0.25db/65536 LRCK", 217 }; 218 219 static const char *const dacpol_txt[] = { 220 "Normal", "R Invert", "L Invert", "L + R Invert" }; 221 222 static const char *const hp_spkvol_switch[] = { 223 "HPVOL: HPL+HPL, SPKVOL: HPL+HPL", 224 "HPVOL: HPL+HPR, SPKVOL: HPL+HPR", 225 "HPVOL: HPL+HPL, SPKVOL: SPKL+SPKR", 226 "HPVOL: HPL+HPR, SPKVOL: SPKL+SPKR", 227 }; 228 229 static const struct soc_enum dacpol = 230 SOC_ENUM_SINGLE(ES8326_DAC_DSM, 4, 4, dacpol_txt); 231 static const struct soc_enum dre_winsize = 232 SOC_ENUM_SINGLE(ES8326_ADC_DRE, 0, 16, winsize); 233 static const struct soc_enum alc_winsize = 234 SOC_ENUM_SINGLE(ES8326_ADC_RAMPRATE, 4, 16, winsize); 235 static const struct soc_enum drc_winsize = 236 SOC_ENUM_SINGLE(ES8326_DRC_WINSIZE, 4, 16, winsize); 237 static const struct soc_enum hpvol_spkvol_switch = 238 SOC_ENUM_SINGLE(ES8326_HP_MISC, 6, 4, hp_spkvol_switch); 239 240 static const struct snd_kcontrol_new es8326_snd_controls[] = { 241 SOC_SINGLE_TLV("DAC Playback Volume", ES8326_DACL_VOL, 0, 0xbf, 0, dac_vol_tlv), 242 SOC_ENUM("Playback Polarity", dacpol), 243 SOC_SINGLE_TLV("DAC Ramp Rate", ES8326_DAC_RAMPRATE, 0, 0x0f, 0, softramp_rate), 244 SOC_SINGLE_TLV("DRC Recovery Level", ES8326_DRC_RECOVERY, 0, 4, 0, drc_recovery_tlv), 245 SOC_ENUM("DRC Winsize", drc_winsize), 246 SOC_SINGLE_TLV("DRC Target Level", ES8326_DRC_WINSIZE, 0, 0x0f, 0, drc_target_tlv), 247 248 SOC_DOUBLE_R_TLV("ADC Capture Volume", ES8326_ADC1_VOL, ES8326_ADC2_VOL, 0, 0xff, 0, 249 adc_vol_tlv), 250 SOC_DOUBLE_TLV("ADC PGA Volume", ES8326_ADC_SCALE, 4, 0, 5, 0, adc_pga_tlv), 251 SOC_SINGLE_TLV("ADC PGA Gain Volume", ES8326_PGAGAIN, 0, 10, 0, adc_analog_pga_tlv), 252 SOC_SINGLE("ADC PGA SE Switch", ES8326_PGAGAIN, 7, 1, 0), 253 SOC_SINGLE_TLV("ADC Ramp Rate", ES8326_ADC_RAMPRATE, 0, 0x0f, 0, softramp_rate), 254 SOC_SINGLE("ADC4 DRE Switch", ES8326_ADC_DRE, 4, 1, 0), 255 SOC_SINGLE("ADC3 DRE Switch", ES8326_ADC_DRE, 5, 1, 0), 256 SOC_SINGLE("ADC2 DRE Switch", ES8326_ADC_DRE, 6, 1, 0), 257 SOC_SINGLE("ADC1 DRE Switch", ES8326_ADC_DRE, 7, 1, 0), 258 SOC_ENUM("DRE Winsize", dre_winsize), 259 SOC_SINGLE("DRE Gain Switch", ES8326_ADC_DRE_GAIN, 5, 1, 0), 260 SOC_SINGLE_TLV("DRE Gain Volume", ES8326_ADC_DRE_GAIN, 261 0, 0x1F, 0, dre_gain_tlv), 262 SOC_SINGLE_TLV("DRE Gate Volume", ES8326_ADC_DRE_GATE, 263 4, 0x07, 0, dre_gate_tlv), 264 SOC_SINGLE("ALC Capture Switch", ES8326_ALC_RECOVERY, 3, 1, 0), 265 SOC_SINGLE_TLV("ALC Capture Recovery Level", ES8326_ALC_LEVEL, 266 0, 4, 0, drc_recovery_tlv), 267 SOC_ENUM("ALC Capture Winsize", alc_winsize), 268 SOC_SINGLE_TLV("ALC Capture Target Level", ES8326_ALC_LEVEL, 269 0, 0x0f, 0, drc_target_tlv), 270 271 SOC_SINGLE_EXT("CROSSTALK1", SND_SOC_NOPM, 0, 31, 0, 272 es8326_crosstalk1_get, es8326_crosstalk1_set), 273 SOC_SINGLE_EXT("CROSSTALK2", SND_SOC_NOPM, 0, 31, 0, 274 es8326_crosstalk2_get, es8326_crosstalk2_set), 275 SOC_SINGLE_EXT("HPL Volume", SND_SOC_NOPM, 0, 5, 0, 276 es8326_hplvol_get, es8326_hplvol_set), 277 SOC_SINGLE_EXT("HPR Volume", SND_SOC_NOPM, 0, 5, 0, 278 es8326_hprvol_get, es8326_hprvol_set), 279 280 SOC_SINGLE_TLV("HPL Playback Volume", ES8326_DACL_VOL, 0, 0xbf, 0, dac_vol_tlv), 281 SOC_SINGLE_TLV("HPR Playback Volume", ES8326_DACR_VOL, 0, 0xbf, 0, dac_vol_tlv), 282 SOC_SINGLE_TLV("SPKL Playback Volume", ES8326_SPKL_VOL, 0, 0xbf, 0, dac_vol_tlv), 283 SOC_SINGLE_TLV("SPKR Playback Volume", ES8326_SPKR_VOL, 0, 0xbf, 0, dac_vol_tlv), 284 285 SOC_ENUM("HPVol SPKVol Switch", hpvol_spkvol_switch), 286 }; 287 288 static const struct snd_soc_dapm_widget es8326_dapm_widgets[] = { 289 SND_SOC_DAPM_INPUT("MIC1"), 290 SND_SOC_DAPM_INPUT("MIC2"), 291 SND_SOC_DAPM_INPUT("MIC3"), 292 SND_SOC_DAPM_INPUT("MIC4"), 293 294 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 295 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 296 297 /* Digital Interface */ 298 SND_SOC_DAPM_AIF_OUT("I2S OUT", "I2S1 Capture", 0, SND_SOC_NOPM, 0, 0), 299 SND_SOC_DAPM_AIF_IN("I2S IN", "I2S1 Playback", 0, SND_SOC_NOPM, 0, 0), 300 301 /* Analog Power Supply*/ 302 SND_SOC_DAPM_DAC("Right DAC", NULL, ES8326_ANA_PDN, 0, 1), 303 SND_SOC_DAPM_DAC("Left DAC", NULL, ES8326_ANA_PDN, 1, 1), 304 SND_SOC_DAPM_SUPPLY("MICBIAS1", ES8326_ANA_MICBIAS, 2, 0, NULL, 0), 305 SND_SOC_DAPM_SUPPLY("MICBIAS2", ES8326_ANA_MICBIAS, 3, 0, NULL, 0), 306 307 SND_SOC_DAPM_PGA("LHPMIX", ES8326_DAC2HPMIX, 7, 0, NULL, 0), 308 SND_SOC_DAPM_PGA("RHPMIX", ES8326_DAC2HPMIX, 3, 0, NULL, 0), 309 310 SND_SOC_DAPM_OUTPUT("HPOL"), 311 SND_SOC_DAPM_OUTPUT("HPOR"), 312 }; 313 314 static const struct snd_soc_dapm_route es8326_dapm_routes[] = { 315 {"ADC L", NULL, "MIC1"}, 316 {"ADC R", NULL, "MIC2"}, 317 {"ADC L", NULL, "MIC3"}, 318 {"ADC R", NULL, "MIC4"}, 319 320 {"I2S OUT", NULL, "ADC L"}, 321 {"I2S OUT", NULL, "ADC R"}, 322 323 {"Right DAC", NULL, "I2S IN"}, 324 {"Left DAC", NULL, "I2S IN"}, 325 326 {"LHPMIX", NULL, "Left DAC"}, 327 {"RHPMIX", NULL, "Right DAC"}, 328 329 {"HPOL", NULL, "LHPMIX"}, 330 {"HPOR", NULL, "RHPMIX"}, 331 }; 332 333 static bool es8326_volatile_register(struct device *dev, unsigned int reg) 334 { 335 switch (reg) { 336 case ES8326_HPL_OFFSET_INI: 337 case ES8326_HPR_OFFSET_INI: 338 case ES8326_HPDET_STA: 339 case ES8326_CTIA_OMTP_STA: 340 case ES8326_CSM_MUTE_STA: 341 return true; 342 default: 343 return false; 344 } 345 } 346 347 static bool es8326_writeable_register(struct device *dev, unsigned int reg) 348 { 349 switch (reg) { 350 case ES8326_BIAS_SW1: 351 case ES8326_BIAS_SW2: 352 case ES8326_BIAS_SW3: 353 case ES8326_BIAS_SW4: 354 case ES8326_ADC_HPFS1: 355 case ES8326_ADC_HPFS2: 356 return false; 357 default: 358 return true; 359 } 360 } 361 362 static const struct regmap_config es8326_regmap_config = { 363 .reg_bits = 8, 364 .val_bits = 8, 365 .max_register = 0xff, 366 .use_single_read = true, 367 .use_single_write = true, 368 .volatile_reg = es8326_volatile_register, 369 .writeable_reg = es8326_writeable_register, 370 .cache_type = REGCACHE_RBTREE, 371 }; 372 373 struct _coeff_div { 374 u16 fs; 375 u32 rate; 376 u32 mclk; 377 u8 reg4; 378 u8 reg5; 379 u8 reg6; 380 u8 reg7; 381 u8 reg8; 382 u8 reg9; 383 u8 rega; 384 u8 regb; 385 }; 386 387 /* codec hifi mclk clock divider coefficients */ 388 /* {ratio, LRCK, MCLK, REG04, REG05, REG06, REG07, REG08, REG09, REG10, REG11} */ 389 static const struct _coeff_div coeff_div_v0[] = { 390 {64, 8000, 512000, 0x60, 0x01, 0x0F, 0x75, 0x0A, 0x1B, 0x1F, 0x7F}, 391 {64, 16000, 1024000, 0x20, 0x00, 0x33, 0x35, 0x0A, 0x1B, 0x1F, 0x3F}, 392 {64, 44100, 2822400, 0xE0, 0x00, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 393 {64, 48000, 3072000, 0xE0, 0x00, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 394 {128, 8000, 1024000, 0x60, 0x00, 0x33, 0x35, 0x0A, 0x1B, 0x1F, 0x7F}, 395 {128, 16000, 2048000, 0x20, 0x00, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x3F}, 396 {128, 44100, 5644800, 0xE0, 0x01, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 397 {128, 48000, 6144000, 0xE0, 0x01, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 398 399 {192, 32000, 6144000, 0xE0, 0x02, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 400 {256, 8000, 2048000, 0x60, 0x00, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x7F}, 401 {256, 16000, 4096000, 0x20, 0x01, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x3F}, 402 {256, 44100, 11289600, 0xE0, 0x00, 0x30, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 403 {256, 48000, 12288000, 0xE0, 0x00, 0x30, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 404 {384, 32000, 12288000, 0xE0, 0x05, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 405 {400, 48000, 19200000, 0xE9, 0x04, 0x0F, 0x6d, 0x4A, 0x0A, 0x1F, 0x1F}, 406 407 {500, 48000, 24000000, 0xF8, 0x04, 0x3F, 0x6D, 0x4A, 0x0A, 0x1F, 0x1F}, 408 {512, 8000, 4096000, 0x60, 0x01, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x7F}, 409 {512, 16000, 8192000, 0x20, 0x00, 0x30, 0x35, 0x0A, 0x1B, 0x1F, 0x3F}, 410 {512, 44100, 22579200, 0xE0, 0x00, 0x00, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 411 {512, 48000, 24576000, 0xE0, 0x00, 0x00, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 412 {768, 32000, 24576000, 0xE0, 0x02, 0x30, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 413 {1024, 8000, 8192000, 0x60, 0x00, 0x30, 0x35, 0x0A, 0x1B, 0x1F, 0x7F}, 414 {1024, 16000, 16384000, 0x20, 0x00, 0x00, 0x35, 0x0A, 0x1B, 0x1F, 0x3F}, 415 }; 416 417 static const struct _coeff_div coeff_div_v3[] = { 418 {32, 8000, 256000, 0x60, 0x00, 0x0F, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 419 {32, 16000, 512000, 0x20, 0x00, 0x0D, 0x75, 0x8A, 0x1B, 0x1F, 0x3F}, 420 {32, 44100, 1411200, 0x00, 0x00, 0x13, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F}, 421 {32, 48000, 1536000, 0x00, 0x00, 0x13, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F}, 422 {36, 8000, 288000, 0x20, 0x00, 0x0D, 0x75, 0x8A, 0x1B, 0x23, 0x47}, 423 {36, 16000, 576000, 0x20, 0x00, 0x0D, 0x75, 0x8A, 0x1B, 0x23, 0x47}, 424 {48, 8000, 384000, 0x60, 0x02, 0x1F, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 425 {48, 16000, 768000, 0x20, 0x02, 0x0F, 0x75, 0x8A, 0x1B, 0x1F, 0x3F}, 426 {48, 48000, 2304000, 0x00, 0x02, 0x0D, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F}, 427 428 {64, 8000, 512000, 0x60, 0x00, 0x35, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 429 {64, 16000, 1024000, 0x20, 0x00, 0x05, 0x75, 0x8A, 0x1B, 0x1F, 0x3F}, 430 {64, 44100, 2822400, 0xE0, 0x00, 0x31, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 431 {64, 48000, 3072000, 0xE0, 0x00, 0x31, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 432 {72, 8000, 576000, 0x20, 0x00, 0x13, 0x35, 0x8A, 0x1B, 0x23, 0x47}, 433 {72, 16000, 1152000, 0x20, 0x00, 0x05, 0x75, 0x8A, 0x1B, 0x23, 0x47}, 434 {96, 8000, 768000, 0x60, 0x02, 0x1D, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 435 {96, 16000, 1536000, 0x20, 0x02, 0x0D, 0x75, 0x8A, 0x1B, 0x1F, 0x3F}, 436 {100, 48000, 4800000, 0x04, 0x04, 0x3F, 0x6D, 0xB8, 0x08, 0x4f, 0x1f}, 437 {125, 48000, 6000000, 0x04, 0x04, 0x1F, 0x2D, 0x8A, 0x0A, 0x27, 0x27}, 438 439 {128, 8000, 1024000, 0x60, 0x00, 0x05, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 440 {128, 16000, 2048000, 0x20, 0x00, 0x31, 0x35, 0x08, 0x19, 0x1F, 0x3F}, 441 {128, 44100, 5644800, 0xE0, 0x00, 0x01, 0x2D, 0x48, 0x08, 0x1F, 0x1F}, 442 {128, 48000, 6144000, 0xE0, 0x00, 0x01, 0x2D, 0x48, 0x08, 0x1F, 0x1F}, 443 {144, 8000, 1152000, 0x20, 0x00, 0x03, 0x35, 0x8A, 0x1B, 0x23, 0x47}, 444 {144, 16000, 2304000, 0x20, 0x00, 0x11, 0x35, 0x8A, 0x1B, 0x23, 0x47}, 445 {192, 8000, 1536000, 0x60, 0x02, 0x0D, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 446 {192, 32000, 6144000, 0xE0, 0x02, 0x31, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 447 {192, 16000, 3072000, 0x20, 0x02, 0x05, 0x75, 0xCA, 0x1B, 0x1F, 0x3F}, 448 449 {200, 48000, 9600000, 0x04, 0x04, 0x0F, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 450 {250, 48000, 12000000, 0x04, 0x04, 0x0F, 0x2D, 0xCA, 0x0A, 0x27, 0x27}, 451 {256, 8000, 2048000, 0x60, 0x00, 0x31, 0x35, 0x08, 0x19, 0x1F, 0x7F}, 452 {256, 16000, 4096000, 0x20, 0x00, 0x01, 0x35, 0x08, 0x19, 0x1F, 0x3F}, 453 {256, 44100, 11289600, 0xE0, 0x01, 0x01, 0x2D, 0x48, 0x08, 0x1F, 0x1F}, 454 {256, 48000, 12288000, 0xE0, 0x01, 0x01, 0x2D, 0x48, 0x08, 0x1F, 0x1F}, 455 {288, 8000, 2304000, 0x20, 0x00, 0x01, 0x35, 0x8A, 0x1B, 0x23, 0x47}, 456 {384, 8000, 3072000, 0x60, 0x02, 0x05, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 457 {384, 16000, 6144000, 0x20, 0x02, 0x03, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 458 {384, 32000, 12288000, 0xE0, 0x02, 0x01, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 459 {384, 48000, 18432000, 0x00, 0x02, 0x01, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F}, 460 461 {400, 48000, 19200000, 0xE4, 0x04, 0x35, 0x6d, 0xCA, 0x0A, 0x1F, 0x1F}, 462 {500, 48000, 24000000, 0xF8, 0x04, 0x3F, 0x6D, 0xCA, 0x0A, 0x1F, 0x1F}, 463 {512, 8000, 4096000, 0x60, 0x00, 0x01, 0x08, 0x19, 0x1B, 0x1F, 0x7F}, 464 {512, 16000, 8192000, 0x20, 0x00, 0x30, 0x35, 0x08, 0x19, 0x1F, 0x3F}, 465 {512, 44100, 22579200, 0xE0, 0x00, 0x00, 0x2D, 0x48, 0x08, 0x1F, 0x1F}, 466 {512, 48000, 24576000, 0xE0, 0x00, 0x00, 0x2D, 0x48, 0x08, 0x1F, 0x1F}, 467 {768, 8000, 6144000, 0x60, 0x02, 0x11, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 468 {768, 16000, 12288000, 0x20, 0x02, 0x01, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 469 {768, 32000, 24576000, 0xE0, 0x02, 0x30, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 470 {800, 48000, 38400000, 0x00, 0x18, 0x13, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F}, 471 472 {1024, 8000, 8192000, 0x60, 0x00, 0x30, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 473 {1024, 16000, 16384000, 0x20, 0x00, 0x00, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 474 {1152, 16000, 18432000, 0x20, 0x08, 0x11, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 475 {1536, 8000, 12288000, 0x60, 0x02, 0x01, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 476 {1536, 16000, 24576000, 0x20, 0x02, 0x10, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 477 {1625, 8000, 13000000, 0x0C, 0x18, 0x1F, 0x2D, 0x8A, 0x0A, 0x27, 0x27}, 478 {1625, 16000, 26000000, 0x0C, 0x18, 0x1F, 0x2D, 0x8A, 0x0A, 0x27, 0x27}, 479 {2048, 8000, 16384000, 0x60, 0x00, 0x00, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 480 {2304, 8000, 18432000, 0x40, 0x02, 0x10, 0x35, 0x8A, 0x1B, 0x1F, 0x5F}, 481 {3072, 8000, 24576000, 0x60, 0x02, 0x10, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 482 {3250, 8000, 26000000, 0x0C, 0x18, 0x0F, 0x2D, 0x8A, 0x0A, 0x27, 0x27}, 483 }; 484 485 static inline int get_coeff(int mclk, int rate, int array, 486 const struct _coeff_div *coeff_div) 487 { 488 int i; 489 490 for (i = 0; i < array; i++) { 491 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk) 492 return i; 493 } 494 495 return -EINVAL; 496 } 497 498 static int es8326_set_dai_sysclk(struct snd_soc_dai *codec_dai, 499 int clk_id, unsigned int freq, int dir) 500 { 501 struct snd_soc_component *codec = codec_dai->component; 502 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(codec); 503 504 es8326->sysclk = freq; 505 506 return 0; 507 } 508 509 static int es8326_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 510 { 511 struct snd_soc_component *component = codec_dai->component; 512 u8 iface = 0; 513 514 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 515 case SND_SOC_DAIFMT_CBC_CFP: 516 snd_soc_component_update_bits(component, ES8326_RESET, 517 ES8326_MASTER_MODE_EN, ES8326_MASTER_MODE_EN); 518 break; 519 case SND_SOC_DAIFMT_CBC_CFC: 520 break; 521 default: 522 return -EINVAL; 523 } 524 525 /* interface format */ 526 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 527 case SND_SOC_DAIFMT_I2S: 528 break; 529 case SND_SOC_DAIFMT_RIGHT_J: 530 dev_err(component->dev, "Codec driver does not support right justified\n"); 531 return -EINVAL; 532 case SND_SOC_DAIFMT_LEFT_J: 533 iface |= ES8326_DAIFMT_LEFT_J; 534 break; 535 case SND_SOC_DAIFMT_DSP_A: 536 iface |= ES8326_DAIFMT_DSP_A; 537 break; 538 case SND_SOC_DAIFMT_DSP_B: 539 iface |= ES8326_DAIFMT_DSP_B; 540 break; 541 default: 542 return -EINVAL; 543 } 544 545 snd_soc_component_update_bits(component, ES8326_FMT, ES8326_DAIFMT_MASK, iface); 546 547 return 0; 548 } 549 550 static int es8326_pcm_hw_params(struct snd_pcm_substream *substream, 551 struct snd_pcm_hw_params *params, 552 struct snd_soc_dai *dai) 553 { 554 struct snd_soc_component *component = dai->component; 555 const struct _coeff_div *coeff_div; 556 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 557 u8 srate = 0; 558 int coeff, array; 559 560 if (es8326->version == 0) { 561 coeff_div = coeff_div_v0; 562 array = ARRAY_SIZE(coeff_div_v0); 563 } else { 564 coeff_div = coeff_div_v3; 565 array = ARRAY_SIZE(coeff_div_v3); 566 } 567 coeff = get_coeff(es8326->sysclk, params_rate(params), array, coeff_div); 568 /* bit size */ 569 switch (params_format(params)) { 570 case SNDRV_PCM_FORMAT_S16_LE: 571 srate |= ES8326_S16_LE; 572 break; 573 case SNDRV_PCM_FORMAT_S20_3LE: 574 srate |= ES8326_S20_3_LE; 575 break; 576 case SNDRV_PCM_FORMAT_S18_3LE: 577 srate |= ES8326_S18_LE; 578 break; 579 case SNDRV_PCM_FORMAT_S24_LE: 580 srate |= ES8326_S24_LE; 581 break; 582 case SNDRV_PCM_FORMAT_S32_LE: 583 srate |= ES8326_S32_LE; 584 break; 585 default: 586 return -EINVAL; 587 } 588 589 /* set iface & srate */ 590 snd_soc_component_update_bits(component, ES8326_FMT, ES8326_DATA_LEN_MASK, srate); 591 592 if (coeff >= 0) { 593 regmap_write(es8326->regmap, ES8326_CLK_DIV1, 594 coeff_div[coeff].reg4); 595 regmap_write(es8326->regmap, ES8326_CLK_DIV2, 596 coeff_div[coeff].reg5); 597 regmap_write(es8326->regmap, ES8326_CLK_DLL, 598 coeff_div[coeff].reg6); 599 regmap_write(es8326->regmap, ES8326_CLK_MUX, 600 coeff_div[coeff].reg7); 601 regmap_write(es8326->regmap, ES8326_CLK_ADC_SEL, 602 coeff_div[coeff].reg8); 603 regmap_write(es8326->regmap, ES8326_CLK_DAC_SEL, 604 coeff_div[coeff].reg9); 605 regmap_write(es8326->regmap, ES8326_CLK_ADC_OSR, 606 coeff_div[coeff].rega); 607 regmap_write(es8326->regmap, ES8326_CLK_DAC_OSR, 608 coeff_div[coeff].regb); 609 } else { 610 dev_warn(component->dev, "Clock coefficients do not match"); 611 } 612 613 return 0; 614 } 615 616 static int es8326_mute(struct snd_soc_dai *dai, int mute, int direction) 617 { 618 struct snd_soc_component *component = dai->component; 619 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 620 unsigned int offset_l, offset_r; 621 622 if (mute) { 623 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 624 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF); 625 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE, 626 ES8326_MUTE_MASK, ES8326_MUTE); 627 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 628 0x30, 0x00); 629 } else { 630 regmap_update_bits(es8326->regmap, ES8326_ADC_MUTE, 631 0x0F, 0x0F); 632 if (es8326->version > ES8326_VERSION_B) { 633 regmap_update_bits(es8326->regmap, ES8326_VMIDSEL, 0x40, 0x40); 634 regmap_update_bits(es8326->regmap, ES8326_ANA_MICBIAS, 0x70, 0x30); 635 } 636 } 637 } else { 638 if (!es8326->calibrated) { 639 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_FORCE_CAL); 640 msleep(30); 641 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF); 642 regmap_read(es8326->regmap, ES8326_HPL_OFFSET_INI, &offset_l); 643 regmap_read(es8326->regmap, ES8326_HPR_OFFSET_INI, &offset_r); 644 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c); 645 regmap_write(es8326->regmap, ES8326_HPL_OFFSET_INI, offset_l); 646 regmap_write(es8326->regmap, ES8326_HPR_OFFSET_INI, offset_r); 647 es8326->calibrated = true; 648 } 649 regmap_update_bits(es8326->regmap, ES8326_CLK_INV, 0xc0, 0x00); 650 regmap_update_bits(es8326->regmap, ES8326_CLK_MUX, 0x80, 0x00); 651 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 652 regmap_update_bits(es8326->regmap, ES8326_DAC_DSM, 0x01, 0x01); 653 usleep_range(1000, 5000); 654 regmap_update_bits(es8326->regmap, ES8326_DAC_DSM, 0x01, 0x00); 655 usleep_range(1000, 5000); 656 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x30, 0x20); 657 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x30, 0x30); 658 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa1); 659 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_ON); 660 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE, 661 ES8326_MUTE_MASK, ~(ES8326_MUTE)); 662 } else { 663 msleep(300); 664 if (es8326->version > ES8326_VERSION_B) { 665 regmap_update_bits(es8326->regmap, ES8326_ANA_MICBIAS, 0x70, 0x70); 666 regmap_update_bits(es8326->regmap, ES8326_VMIDSEL, 0x40, 0x00); 667 } 668 regmap_update_bits(es8326->regmap, ES8326_ADC_MUTE, 669 0x0F, 0x00); 670 } 671 } 672 return 0; 673 } 674 675 static int es8326_set_bias_level(struct snd_soc_component *codec, 676 enum snd_soc_bias_level level) 677 { 678 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(codec); 679 int ret; 680 681 switch (level) { 682 case SND_SOC_BIAS_ON: 683 ret = clk_prepare_enable(es8326->mclk); 684 if (ret) 685 return ret; 686 687 regmap_update_bits(es8326->regmap, ES8326_RESET, 0x02, 0x02); 688 usleep_range(5000, 10000); 689 regmap_write(es8326->regmap, ES8326_INTOUT_IO, es8326->interrupt_clk); 690 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO, 691 (ES8326_IO_DMIC_CLK << ES8326_SDINOUT1_SHIFT)); 692 regmap_write(es8326->regmap, ES8326_PGA_PDN, 0x40); 693 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x00); 694 regmap_update_bits(es8326->regmap, ES8326_CLK_CTL, 0x20, 0x20); 695 regmap_update_bits(es8326->regmap, ES8326_RESET, 0x02, 0x00); 696 if (es8326->version > ES8326_VERSION_B) { 697 regmap_update_bits(es8326->regmap, ES8326_VMIDSEL, 0x40, 0x40); 698 regmap_update_bits(es8326->regmap, ES8326_ANA_MICBIAS, 0x70, 0x30); 699 } 700 break; 701 case SND_SOC_BIAS_PREPARE: 702 break; 703 case SND_SOC_BIAS_STANDBY: 704 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x3b); 705 regmap_update_bits(es8326->regmap, ES8326_CLK_CTL, 0x20, 0x00); 706 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO, ES8326_IO_INPUT); 707 if (es8326->version > ES8326_VERSION_B) { 708 regmap_update_bits(es8326->regmap, ES8326_VMIDSEL, 0x40, 0x40); 709 regmap_update_bits(es8326->regmap, ES8326_ANA_MICBIAS, 0x70, 0x10); 710 } 711 regmap_update_bits(es8326->regmap, ES8326_CLK_INV, 0xc0, 0xc0); 712 regmap_update_bits(es8326->regmap, ES8326_CLK_MUX, 0x80, 0x80); 713 break; 714 case SND_SOC_BIAS_OFF: 715 clk_disable_unprepare(es8326->mclk); 716 break; 717 } 718 719 return 0; 720 } 721 722 #define es8326_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 723 SNDRV_PCM_FMTBIT_S24_LE) 724 725 static const struct snd_soc_dai_ops es8326_ops = { 726 .hw_params = es8326_pcm_hw_params, 727 .set_fmt = es8326_set_dai_fmt, 728 .set_sysclk = es8326_set_dai_sysclk, 729 .mute_stream = es8326_mute, 730 .no_capture_mute = 0, 731 }; 732 733 static struct snd_soc_dai_driver es8326_dai = { 734 .name = "ES8326 HiFi", 735 .playback = { 736 .stream_name = "Playback", 737 .channels_min = 1, 738 .channels_max = 2, 739 .rates = SNDRV_PCM_RATE_8000_48000, 740 .formats = es8326_FORMATS, 741 }, 742 .capture = { 743 .stream_name = "Capture", 744 .channels_min = 1, 745 .channels_max = 2, 746 .rates = SNDRV_PCM_RATE_8000_48000, 747 .formats = es8326_FORMATS, 748 }, 749 .ops = &es8326_ops, 750 .symmetric_rate = 1, 751 }; 752 753 static void es8326_enable_micbias(struct snd_soc_component *component) 754 { 755 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 756 757 snd_soc_dapm_mutex_lock(dapm); 758 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS1"); 759 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS2"); 760 snd_soc_dapm_sync_unlocked(dapm); 761 snd_soc_dapm_mutex_unlock(dapm); 762 } 763 764 static void es8326_disable_micbias(struct snd_soc_component *component) 765 { 766 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 767 768 snd_soc_dapm_mutex_lock(dapm); 769 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS1"); 770 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS2"); 771 snd_soc_dapm_sync_unlocked(dapm); 772 snd_soc_dapm_mutex_unlock(dapm); 773 } 774 775 /* 776 * For button detection, set the following in soundcard 777 * snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE); 778 * snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEUP); 779 * snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN); 780 */ 781 static void es8326_jack_button_handler(struct work_struct *work) 782 { 783 struct es8326_priv *es8326 = 784 container_of(work, struct es8326_priv, button_press_work.work); 785 struct snd_soc_component *comp = es8326->component; 786 unsigned int iface; 787 static int button_to_report, press_count; 788 static int prev_button, cur_button; 789 790 if (!(es8326->jack->status & SND_JACK_HEADSET)) /* Jack unplugged */ 791 return; 792 793 mutex_lock(&es8326->lock); 794 iface = snd_soc_component_read(comp, ES8326_HPDET_STA); 795 switch (iface) { 796 case 0x93: 797 /* pause button detected */ 798 cur_button = SND_JACK_BTN_0; 799 break; 800 case 0x6f: 801 case 0x4b: 802 /* button volume up */ 803 if ((iface == 0x6f) && (es8326->version > ES8326_VERSION_B)) 804 cur_button = SND_JACK_BTN_0; 805 else 806 cur_button = SND_JACK_BTN_1; 807 break; 808 case 0x27: 809 /* button volume down */ 810 cur_button = SND_JACK_BTN_2; 811 break; 812 case 0x1e: 813 case 0xe2: 814 /* button released or not pressed */ 815 cur_button = 0; 816 break; 817 default: 818 break; 819 } 820 821 if ((prev_button == cur_button) && (cur_button != 0)) { 822 press_count++; 823 if (press_count > 3) { 824 /* report a press every 120ms */ 825 snd_soc_jack_report(es8326->jack, cur_button, 826 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2); 827 press_count = 0; 828 } 829 button_to_report = cur_button; 830 queue_delayed_work(system_dfl_wq, &es8326->button_press_work, 831 msecs_to_jiffies(35)); 832 } else if (prev_button != cur_button) { 833 /* mismatch, detect again */ 834 prev_button = cur_button; 835 queue_delayed_work(system_dfl_wq, &es8326->button_press_work, 836 msecs_to_jiffies(35)); 837 } else { 838 /* released or no pressed */ 839 if (button_to_report != 0) { 840 snd_soc_jack_report(es8326->jack, button_to_report, 841 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2); 842 snd_soc_jack_report(es8326->jack, 0, 843 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2); 844 button_to_report = 0; 845 } 846 es8326_disable_micbias(es8326->component); 847 } 848 mutex_unlock(&es8326->lock); 849 } 850 851 static void es8326_jack_detect_handler(struct work_struct *work) 852 { 853 struct es8326_priv *es8326 = 854 container_of(work, struct es8326_priv, jack_detect_work.work); 855 struct snd_soc_component *comp = es8326->component; 856 unsigned int iface; 857 858 mutex_lock(&es8326->lock); 859 iface = snd_soc_component_read(comp, ES8326_HPDET_STA); 860 dev_dbg(comp->dev, "gpio flag %#04x", iface); 861 862 if ((es8326->jack_remove_retry == 1) && (es8326->version < ES8326_VERSION_B)) { 863 if (iface & ES8326_HPINSERT_FLAG) 864 es8326->jack_remove_retry = 2; 865 else 866 es8326->jack_remove_retry = 0; 867 868 dev_dbg(comp->dev, "remove event check, set HPJACK_POL normal, cnt = %d\n", 869 es8326->jack_remove_retry); 870 /* 871 * Inverted HPJACK_POL bit to trigger one IRQ to double check HP Removal event 872 */ 873 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 874 ES8326_HP_DET_JACK_POL, (es8326->jd_inverted ? 875 ~es8326->jack_pol : es8326->jack_pol)); 876 goto exit; 877 } 878 879 if ((iface & ES8326_HPINSERT_FLAG) == 0) { 880 /* Jack unplugged or spurious IRQ */ 881 dev_dbg(comp->dev, "No headset detected\n"); 882 es8326_disable_micbias(es8326->component); 883 if (es8326->jack->status & SND_JACK_HEADPHONE) { 884 dev_dbg(comp->dev, "Report hp remove event\n"); 885 snd_soc_jack_report(es8326->jack, 0, 886 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2); 887 snd_soc_jack_report(es8326->jack, 0, SND_JACK_HEADSET); 888 /* mute adc when mic path switch */ 889 regmap_write(es8326->regmap, ES8326_ADC1_SRC, 0x44); 890 regmap_write(es8326->regmap, ES8326_ADC2_SRC, 0x66); 891 } 892 es8326->hp = 0; 893 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x01); 894 regmap_write(es8326->regmap, ES8326_SYS_BIAS, 0x0a); 895 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x0f, 0x03); 896 regmap_write(es8326->regmap, ES8326_INT_SOURCE, ES8326_INT_SRC_PIN9); 897 /* 898 * Inverted HPJACK_POL bit to trigger one IRQ to double check HP Removal event 899 */ 900 if ((es8326->jack_remove_retry == 0) && (es8326->version < ES8326_VERSION_B)) { 901 es8326->jack_remove_retry = 1; 902 dev_dbg(comp->dev, "remove event check, invert HPJACK_POL, cnt = %d\n", 903 es8326->jack_remove_retry); 904 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 905 ES8326_HP_DET_JACK_POL, (es8326->jd_inverted ? 906 es8326->jack_pol : ~es8326->jack_pol)); 907 908 } else { 909 es8326->jack_remove_retry = 0; 910 } 911 } else if ((iface & ES8326_HPINSERT_FLAG) == ES8326_HPINSERT_FLAG) { 912 es8326->jack_remove_retry = 0; 913 if (es8326->hp == 0) { 914 dev_dbg(comp->dev, "First insert, start OMTP/CTIA type check\n"); 915 /* 916 * set auto-check mode, then restart jack_detect_work after 400ms. 917 * Don't report jack status. 918 */ 919 regmap_write(es8326->regmap, ES8326_INT_SOURCE, 0x00); 920 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x01); 921 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x10, 0x00); 922 usleep_range(50000, 70000); 923 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x00); 924 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x10, 0x10); 925 usleep_range(50000, 70000); 926 regmap_write(es8326->regmap, ES8326_INT_SOURCE, 927 (ES8326_INT_SRC_PIN9 | ES8326_INT_SRC_BUTTON)); 928 regmap_write(es8326->regmap, ES8326_SYS_BIAS, 0x1f); 929 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x0f, 0x0d); 930 queue_delayed_work(system_dfl_wq, &es8326->jack_detect_work, 931 msecs_to_jiffies(400)); 932 es8326->hp = 1; 933 goto exit; 934 } 935 if (es8326->jack->status & SND_JACK_HEADSET) { 936 /* detect button */ 937 dev_dbg(comp->dev, "button pressed\n"); 938 regmap_write(es8326->regmap, ES8326_INT_SOURCE, 939 (ES8326_INT_SRC_PIN9 | ES8326_INT_SRC_BUTTON)); 940 es8326_enable_micbias(es8326->component); 941 queue_delayed_work(system_dfl_wq, &es8326->button_press_work, 10); 942 goto exit; 943 } 944 if ((iface & ES8326_HPBUTTON_FLAG) == 0x01) { 945 dev_dbg(comp->dev, "Headphone detected\n"); 946 snd_soc_jack_report(es8326->jack, 947 SND_JACK_HEADPHONE, SND_JACK_HEADSET); 948 } else { 949 dev_dbg(comp->dev, "Headset detected\n"); 950 snd_soc_jack_report(es8326->jack, 951 SND_JACK_HEADSET, SND_JACK_HEADSET); 952 regmap_update_bits(es8326->regmap, ES8326_PGA_PDN, 953 0x08, 0x08); 954 regmap_write(es8326->regmap, ES8326_ADC1_SRC, 0x00); 955 regmap_write(es8326->regmap, ES8326_ADC2_SRC, 0x00); 956 regmap_update_bits(es8326->regmap, ES8326_PGA_PDN, 957 0x08, 0x00); 958 usleep_range(10000, 15000); 959 } 960 } 961 exit: 962 mutex_unlock(&es8326->lock); 963 } 964 965 static irqreturn_t es8326_irq(int irq, void *dev_id) 966 { 967 struct es8326_priv *es8326 = dev_id; 968 969 if (!es8326->jack) 970 goto out; 971 972 if (es8326->jack->status & SND_JACK_HEADSET) 973 queue_delayed_work(system_dfl_wq, &es8326->jack_detect_work, 974 msecs_to_jiffies(10)); 975 else 976 queue_delayed_work(system_dfl_wq, &es8326->jack_detect_work, 977 msecs_to_jiffies(300)); 978 979 out: 980 return IRQ_HANDLED; 981 } 982 983 static int es8326_calibrate(struct snd_soc_component *component) 984 { 985 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 986 unsigned int reg; 987 unsigned int offset_l, offset_r; 988 989 regmap_read(es8326->regmap, ES8326_CHIP_VERSION, ®); 990 es8326->version = reg; 991 992 if ((es8326->version >= ES8326_VERSION_B) && (es8326->calibrated == false)) { 993 dev_dbg(component->dev, "ES8326_VERSION_B, calibrating\n"); 994 regmap_write(es8326->regmap, ES8326_CLK_INV, 0xc0); 995 regmap_write(es8326->regmap, ES8326_CLK_DIV1, 0x03); 996 regmap_write(es8326->regmap, ES8326_CLK_DLL, 0x30); 997 regmap_write(es8326->regmap, ES8326_CLK_MUX, 0xed); 998 regmap_write(es8326->regmap, ES8326_CLK_DAC_SEL, 0x08); 999 regmap_write(es8326->regmap, ES8326_CLK_TRI, 0xc1); 1000 regmap_write(es8326->regmap, ES8326_DAC_MUTE, 0x03); 1001 regmap_write(es8326->regmap, ES8326_ANA_VSEL, 0x7f); 1002 regmap_write(es8326->regmap, ES8326_VMIDLOW, 0x23); 1003 regmap_write(es8326->regmap, ES8326_DAC2HPMIX, 0x88); 1004 usleep_range(15000, 20000); 1005 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c); 1006 usleep_range(15000, 20000); 1007 regmap_write(es8326->regmap, ES8326_RESET, 0xc0); 1008 usleep_range(15000, 20000); 1009 1010 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, ES8326_HP_OFF); 1011 regmap_read(es8326->regmap, ES8326_CSM_MUTE_STA, ®); 1012 if ((reg & 0xf0) != 0x40) 1013 msleep(50); 1014 1015 regmap_write(es8326->regmap, ES8326_HP_CAL, 0xd4); 1016 msleep(200); 1017 regmap_write(es8326->regmap, ES8326_HP_CAL, 0x4d); 1018 msleep(200); 1019 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF); 1020 regmap_read(es8326->regmap, ES8326_HPL_OFFSET_INI, &offset_l); 1021 regmap_read(es8326->regmap, ES8326_HPR_OFFSET_INI, &offset_r); 1022 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c); 1023 regmap_write(es8326->regmap, ES8326_HPL_OFFSET_INI, offset_l); 1024 regmap_write(es8326->regmap, ES8326_HPR_OFFSET_INI, offset_r); 1025 regmap_write(es8326->regmap, ES8326_CLK_INV, 0x00); 1026 1027 es8326->calibrated = true; 1028 } 1029 1030 return 0; 1031 } 1032 1033 static void es8326_init(struct snd_soc_component *component) 1034 { 1035 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 1036 1037 regmap_write(es8326->regmap, ES8326_RESET, 0x1f); 1038 regmap_write(es8326->regmap, ES8326_VMIDSEL, 0x3E); 1039 regmap_write(es8326->regmap, ES8326_ANA_LP, 0xf0); 1040 usleep_range(10000, 15000); 1041 regmap_write(es8326->regmap, ES8326_HPJACK_TIMER, 0xd9); 1042 regmap_write(es8326->regmap, ES8326_ANA_MICBIAS, 0xd8); 1043 /* set headphone default type and detect pin */ 1044 regmap_write(es8326->regmap, ES8326_HPDET_TYPE, 0x83); 1045 regmap_write(es8326->regmap, ES8326_CLK_RESAMPLE, 0x05); 1046 1047 /* set internal oscillator as clock source of headpone cp */ 1048 regmap_write(es8326->regmap, ES8326_CLK_DIV_CPC, 0x89); 1049 regmap_write(es8326->regmap, ES8326_CLK_CTL, ES8326_CLK_ON); 1050 /* clock manager reset release */ 1051 regmap_write(es8326->regmap, ES8326_RESET, 0x17); 1052 /* set headphone detection as half scan mode */ 1053 regmap_write(es8326->regmap, ES8326_HP_MISC, 0x3d); 1054 regmap_write(es8326->regmap, ES8326_PULLUP_CTL, 0x00); 1055 1056 /* enable headphone driver */ 1057 regmap_write(es8326->regmap, ES8326_HP_VOL, 0xc4); 1058 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa7); 1059 usleep_range(2000, 5000); 1060 regmap_write(es8326->regmap, ES8326_HP_DRIVER_REF, 0x23); 1061 regmap_write(es8326->regmap, ES8326_HP_DRIVER_REF, 0x33); 1062 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa1); 1063 1064 regmap_write(es8326->regmap, ES8326_CLK_INV, 0x00); 1065 regmap_write(es8326->regmap, ES8326_CLK_VMIDS1, 0xc4); 1066 regmap_write(es8326->regmap, ES8326_CLK_VMIDS2, 0x81); 1067 regmap_write(es8326->regmap, ES8326_CLK_CAL_TIME, 0x00); 1068 /* calibrate for B version */ 1069 es8326_calibrate(component); 1070 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, 0xaa); 1071 regmap_write(es8326->regmap, ES8326_DAC_RAMPRATE, 0x00); 1072 /* turn off headphone out */ 1073 regmap_write(es8326->regmap, ES8326_HP_CAL, 0x00); 1074 /* set ADC and DAC in low power mode */ 1075 regmap_write(es8326->regmap, ES8326_ANA_LP, 0xf0); 1076 1077 regmap_write(es8326->regmap, ES8326_ANA_VSEL, 0x7F); 1078 /* select vdda as micbias source */ 1079 regmap_write(es8326->regmap, ES8326_VMIDLOW, 0x03); 1080 /* set dac dsmclip = 1 */ 1081 regmap_write(es8326->regmap, ES8326_DAC_DSM, 0x08); 1082 regmap_write(es8326->regmap, ES8326_DAC_VPPSCALE, 0x15); 1083 1084 regmap_write(es8326->regmap, ES8326_HPDET_TYPE, 0x80 | 1085 ((es8326->version >= ES8326_VERSION_B) ? 1086 (ES8326_HP_DET_SRC_PIN9 | es8326->jack_pol) : 1087 (ES8326_HP_DET_SRC_PIN9 | es8326->jack_pol | 0x04))); 1088 usleep_range(5000, 10000); 1089 es8326_enable_micbias(es8326->component); 1090 usleep_range(50000, 70000); 1091 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x00); 1092 regmap_write(es8326->regmap, ES8326_INTOUT_IO, 1093 es8326->interrupt_clk); 1094 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO, ES8326_IO_INPUT); 1095 regmap_write(es8326->regmap, ES8326_SDINOUT23_IO, ES8326_IO_INPUT); 1096 1097 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x00); 1098 regmap_write(es8326->regmap, ES8326_RESET, ES8326_CSM_ON); 1099 regmap_update_bits(es8326->regmap, ES8326_PGAGAIN, ES8326_MIC_SEL_MASK, 1100 ES8326_MIC1_SEL); 1101 1102 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE, ES8326_MUTE_MASK, 1103 ES8326_MUTE); 1104 1105 regmap_write(es8326->regmap, ES8326_ADC_MUTE, 0x0f); 1106 regmap_write(es8326->regmap, ES8326_CLK_DIV_LRCK, 0xff); 1107 regmap_write(es8326->regmap, ES8326_ADC1_SRC, 0x44); 1108 regmap_write(es8326->regmap, ES8326_ADC2_SRC, 0x66); 1109 es8326_disable_micbias(es8326->component); 1110 if (es8326->version > ES8326_VERSION_B) { 1111 regmap_update_bits(es8326->regmap, ES8326_ANA_MICBIAS, 0x73, 0x10); 1112 regmap_update_bits(es8326->regmap, ES8326_VMIDSEL, 0x40, 0x40); 1113 } 1114 1115 msleep(200); 1116 regmap_write(es8326->regmap, ES8326_INT_SOURCE, ES8326_INT_SRC_PIN9); 1117 } 1118 1119 static int es8326_resume(struct snd_soc_component *component) 1120 { 1121 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 1122 unsigned int reg; 1123 1124 regcache_cache_only(es8326->regmap, false); 1125 regcache_cache_bypass(es8326->regmap, true); 1126 regmap_read(es8326->regmap, ES8326_CLK_RESAMPLE, ®); 1127 regcache_cache_bypass(es8326->regmap, false); 1128 /* reset internal clock state */ 1129 if (reg == 0x05) 1130 regmap_write(es8326->regmap, ES8326_CLK_CTL, ES8326_CLK_ON); 1131 else 1132 es8326_init(component); 1133 1134 regcache_sync(es8326->regmap); 1135 1136 es8326_irq(es8326->irq, es8326); 1137 return 0; 1138 } 1139 1140 static int es8326_suspend(struct snd_soc_component *component) 1141 { 1142 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 1143 1144 cancel_delayed_work_sync(&es8326->jack_detect_work); 1145 es8326_disable_micbias(component); 1146 es8326->calibrated = false; 1147 regmap_write(es8326->regmap, ES8326_CLK_MUX, 0x2d); 1148 regmap_write(es8326->regmap, ES8326_DAC2HPMIX, 0x00); 1149 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x3b); 1150 regmap_write(es8326->regmap, ES8326_CLK_CTL, ES8326_CLK_OFF); 1151 regcache_cache_only(es8326->regmap, true); 1152 1153 /* reset register value to default */ 1154 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x01); 1155 usleep_range(1000, 3000); 1156 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x00); 1157 1158 regcache_mark_dirty(es8326->regmap); 1159 return 0; 1160 } 1161 1162 static int es8326_probe(struct snd_soc_component *component) 1163 { 1164 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 1165 int ret; 1166 1167 es8326->component = component; 1168 es8326->jd_inverted = device_property_read_bool(component->dev, 1169 "everest,jack-detect-inverted"); 1170 1171 ret = device_property_read_u8(component->dev, "everest,jack-pol", &es8326->jack_pol); 1172 if (ret != 0) { 1173 dev_dbg(component->dev, "jack-pol return %d", ret); 1174 es8326->jack_pol = ES8326_HP_TYPE_AUTO; 1175 } 1176 dev_dbg(component->dev, "jack-pol %x", es8326->jack_pol); 1177 1178 ret = device_property_read_u8(component->dev, "everest,interrupt-src", 1179 &es8326->interrupt_src); 1180 if (ret != 0) { 1181 dev_dbg(component->dev, "interrupt-src return %d", ret); 1182 es8326->interrupt_src = ES8326_HP_DET_SRC_PIN9; 1183 } 1184 dev_dbg(component->dev, "interrupt-src %x", es8326->interrupt_src); 1185 1186 ret = device_property_read_u8(component->dev, "everest,interrupt-clk", 1187 &es8326->interrupt_clk); 1188 if (ret != 0) { 1189 dev_dbg(component->dev, "interrupt-clk return %d", ret); 1190 es8326->interrupt_clk = 0x00; 1191 } 1192 dev_dbg(component->dev, "interrupt-clk %x", es8326->interrupt_clk); 1193 1194 es8326_init(component); 1195 return 0; 1196 } 1197 1198 static void es8326_enable_jack_detect(struct snd_soc_component *component, 1199 struct snd_soc_jack *jack) 1200 { 1201 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 1202 1203 mutex_lock(&es8326->lock); 1204 if (es8326->jd_inverted) 1205 snd_soc_component_update_bits(component, ES8326_HPDET_TYPE, 1206 ES8326_HP_DET_JACK_POL, ~es8326->jack_pol); 1207 es8326->jack = jack; 1208 1209 mutex_unlock(&es8326->lock); 1210 es8326_irq(es8326->irq, es8326); 1211 } 1212 1213 static void es8326_disable_jack_detect(struct snd_soc_component *component) 1214 { 1215 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 1216 1217 dev_dbg(component->dev, "Enter into %s\n", __func__); 1218 if (!es8326->jack) 1219 return; /* Already disabled (or never enabled) */ 1220 cancel_delayed_work_sync(&es8326->jack_detect_work); 1221 1222 mutex_lock(&es8326->lock); 1223 if (es8326->jack->status & SND_JACK_MICROPHONE) { 1224 es8326_disable_micbias(component); 1225 snd_soc_jack_report(es8326->jack, 0, SND_JACK_HEADSET); 1226 } 1227 es8326->jack = NULL; 1228 mutex_unlock(&es8326->lock); 1229 } 1230 1231 static int es8326_set_jack(struct snd_soc_component *component, 1232 struct snd_soc_jack *jack, void *data) 1233 { 1234 if (jack) 1235 es8326_enable_jack_detect(component, jack); 1236 else 1237 es8326_disable_jack_detect(component); 1238 1239 return 0; 1240 } 1241 1242 static void es8326_remove(struct snd_soc_component *component) 1243 { 1244 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 1245 1246 es8326_disable_jack_detect(component); 1247 es8326_set_bias_level(component, SND_SOC_BIAS_OFF); 1248 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x01); 1249 usleep_range(1000, 3000); 1250 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x00); 1251 } 1252 1253 static const struct snd_soc_component_driver soc_component_dev_es8326 = { 1254 .probe = es8326_probe, 1255 .remove = es8326_remove, 1256 .resume = es8326_resume, 1257 .suspend = es8326_suspend, 1258 .set_bias_level = es8326_set_bias_level, 1259 .set_jack = es8326_set_jack, 1260 .dapm_widgets = es8326_dapm_widgets, 1261 .num_dapm_widgets = ARRAY_SIZE(es8326_dapm_widgets), 1262 .dapm_routes = es8326_dapm_routes, 1263 .num_dapm_routes = ARRAY_SIZE(es8326_dapm_routes), 1264 .controls = es8326_snd_controls, 1265 .num_controls = ARRAY_SIZE(es8326_snd_controls), 1266 .use_pmdown_time = 1, 1267 .endianness = 1, 1268 }; 1269 1270 static int es8326_i2c_probe(struct i2c_client *i2c) 1271 { 1272 struct es8326_priv *es8326; 1273 int ret; 1274 1275 es8326 = devm_kzalloc(&i2c->dev, sizeof(struct es8326_priv), GFP_KERNEL); 1276 if (!es8326) 1277 return -ENOMEM; 1278 1279 i2c_set_clientdata(i2c, es8326); 1280 es8326->i2c = i2c; 1281 mutex_init(&es8326->lock); 1282 es8326->regmap = devm_regmap_init_i2c(i2c, &es8326_regmap_config); 1283 if (IS_ERR(es8326->regmap)) { 1284 ret = PTR_ERR(es8326->regmap); 1285 dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret); 1286 return ret; 1287 } 1288 1289 es8326->irq = i2c->irq; 1290 es8326->jack_remove_retry = 0; 1291 es8326->hp = 0; 1292 es8326->hpl_vol = 0x03; 1293 es8326->hpr_vol = 0x03; 1294 INIT_DELAYED_WORK(&es8326->jack_detect_work, 1295 es8326_jack_detect_handler); 1296 INIT_DELAYED_WORK(&es8326->button_press_work, 1297 es8326_jack_button_handler); 1298 /* ES8316 is level-based while ES8326 is edge-based */ 1299 ret = devm_request_threaded_irq(&i2c->dev, es8326->irq, NULL, es8326_irq, 1300 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1301 "es8326", es8326); 1302 if (ret) { 1303 dev_warn(&i2c->dev, "Failed to request IRQ: %d: %d\n", 1304 es8326->irq, ret); 1305 es8326->irq = -ENXIO; 1306 } 1307 1308 es8326->mclk = devm_clk_get_optional(&i2c->dev, "mclk"); 1309 if (IS_ERR(es8326->mclk)) { 1310 dev_err(&i2c->dev, "unable to get mclk\n"); 1311 return PTR_ERR(es8326->mclk); 1312 } 1313 if (!es8326->mclk) 1314 dev_warn(&i2c->dev, "assuming static mclk\n"); 1315 1316 ret = clk_prepare_enable(es8326->mclk); 1317 if (ret) { 1318 dev_err(&i2c->dev, "unable to enable mclk\n"); 1319 return ret; 1320 } 1321 return devm_snd_soc_register_component(&i2c->dev, 1322 &soc_component_dev_es8326, 1323 &es8326_dai, 1); 1324 } 1325 1326 1327 static void es8326_i2c_shutdown(struct i2c_client *i2c) 1328 { 1329 struct snd_soc_component *component; 1330 struct es8326_priv *es8326; 1331 1332 es8326 = i2c_get_clientdata(i2c); 1333 component = es8326->component; 1334 dev_dbg(component->dev, "Enter into %s\n", __func__); 1335 cancel_delayed_work_sync(&es8326->jack_detect_work); 1336 cancel_delayed_work_sync(&es8326->button_press_work); 1337 1338 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x01); 1339 usleep_range(1000, 3000); 1340 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x00); 1341 1342 } 1343 1344 static void es8326_i2c_remove(struct i2c_client *i2c) 1345 { 1346 es8326_i2c_shutdown(i2c); 1347 } 1348 1349 static const struct i2c_device_id es8326_i2c_id[] = { 1350 {"es8326" }, 1351 {} 1352 }; 1353 MODULE_DEVICE_TABLE(i2c, es8326_i2c_id); 1354 1355 #ifdef CONFIG_OF 1356 static const struct of_device_id es8326_of_match[] = { 1357 { .compatible = "everest,es8326", }, 1358 {} 1359 }; 1360 MODULE_DEVICE_TABLE(of, es8326_of_match); 1361 #endif 1362 1363 #ifdef CONFIG_ACPI 1364 static const struct acpi_device_id es8326_acpi_match[] = { 1365 {"ESSX8326", 0}, 1366 {}, 1367 }; 1368 MODULE_DEVICE_TABLE(acpi, es8326_acpi_match); 1369 #endif 1370 1371 static struct i2c_driver es8326_i2c_driver = { 1372 .driver = { 1373 .name = "es8326", 1374 .acpi_match_table = ACPI_PTR(es8326_acpi_match), 1375 .of_match_table = of_match_ptr(es8326_of_match), 1376 }, 1377 .probe = es8326_i2c_probe, 1378 .shutdown = es8326_i2c_shutdown, 1379 .remove = es8326_i2c_remove, 1380 .id_table = es8326_i2c_id, 1381 }; 1382 module_i2c_driver(es8326_i2c_driver); 1383 1384 MODULE_DESCRIPTION("ASoC es8326 driver"); 1385 MODULE_AUTHOR("David Yang <yangxiaohua@everest-semi.com>"); 1386 MODULE_LICENSE("GPL"); 1387