1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // es8326.c -- es8326 ALSA SoC audio driver 4 // Copyright Everest Semiconductor Co., Ltd 5 // 6 // Authors: David Yang <yangxiaohua@everest-semi.com> 7 // 8 9 #include <linux/cleanup.h> 10 #include <linux/clk.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/irq.h> 14 #include <linux/module.h> 15 #include <sound/jack.h> 16 #include <sound/pcm_params.h> 17 #include <sound/soc.h> 18 #include <sound/soc-dapm.h> 19 #include <sound/tlv.h> 20 #include "es8326.h" 21 22 struct es8326_priv { 23 struct clk *mclk; 24 struct i2c_client *i2c; 25 struct regmap *regmap; 26 struct snd_soc_component *component; 27 struct delayed_work jack_detect_work; 28 struct delayed_work button_press_work; 29 struct snd_soc_jack *jack; 30 int irq; 31 /* The lock protects the situation that an irq is generated 32 * while enabling or disabling or during an irq. 33 */ 34 struct mutex lock; 35 u8 jack_pol; 36 u8 interrupt_src; 37 u8 interrupt_clk; 38 u8 hpl_vol; 39 u8 hpr_vol; 40 bool jd_inverted; 41 unsigned int sysclk; 42 43 bool calibrated; 44 int version; 45 int hp; 46 int jack_remove_retry; 47 }; 48 49 static int es8326_crosstalk1_get(struct snd_kcontrol *kcontrol, 50 struct snd_ctl_elem_value *ucontrol) 51 { 52 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 53 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 54 unsigned int crosstalk_h, crosstalk_l; 55 unsigned int crosstalk; 56 57 regmap_read(es8326->regmap, ES8326_DAC_RAMPRATE, &crosstalk_h); 58 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l); 59 crosstalk_h &= 0x20; 60 crosstalk_l &= 0xf0; 61 crosstalk = crosstalk_h >> 1 | crosstalk_l >> 4; 62 ucontrol->value.integer.value[0] = crosstalk; 63 64 return 0; 65 } 66 67 static int es8326_crosstalk1_set(struct snd_kcontrol *kcontrol, 68 struct snd_ctl_elem_value *ucontrol) 69 { 70 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 71 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 72 unsigned int crosstalk_h, crosstalk_l; 73 unsigned int crosstalk; 74 75 crosstalk = ucontrol->value.integer.value[0]; 76 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l); 77 crosstalk_h = (crosstalk & 0x10) << 1; 78 crosstalk_l &= 0x0f; 79 crosstalk_l |= (crosstalk & 0x0f) << 4; 80 regmap_update_bits(es8326->regmap, ES8326_DAC_RAMPRATE, 81 0x20, crosstalk_h); 82 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, crosstalk_l); 83 84 return 0; 85 } 86 87 static int es8326_crosstalk2_get(struct snd_kcontrol *kcontrol, 88 struct snd_ctl_elem_value *ucontrol) 89 { 90 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 91 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 92 unsigned int crosstalk_h, crosstalk_l; 93 unsigned int crosstalk; 94 95 regmap_read(es8326->regmap, ES8326_DAC_RAMPRATE, &crosstalk_h); 96 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l); 97 crosstalk_h &= 0x10; 98 crosstalk_l &= 0x0f; 99 crosstalk = crosstalk_h | crosstalk_l; 100 ucontrol->value.integer.value[0] = crosstalk; 101 102 return 0; 103 } 104 105 static int es8326_crosstalk2_set(struct snd_kcontrol *kcontrol, 106 struct snd_ctl_elem_value *ucontrol) 107 { 108 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 109 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 110 unsigned int crosstalk_h, crosstalk_l; 111 unsigned int crosstalk; 112 113 crosstalk = ucontrol->value.integer.value[0]; 114 regmap_read(es8326->regmap, ES8326_DAC_CROSSTALK, &crosstalk_l); 115 crosstalk_h = crosstalk & 0x10; 116 crosstalk_l &= 0xf0; 117 crosstalk_l |= crosstalk & 0x0f; 118 regmap_update_bits(es8326->regmap, ES8326_DAC_RAMPRATE, 119 0x10, crosstalk_h); 120 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, crosstalk_l); 121 122 return 0; 123 } 124 125 static int es8326_hplvol_get(struct snd_kcontrol *kcontrol, 126 struct snd_ctl_elem_value *ucontrol) 127 { 128 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 129 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 130 131 ucontrol->value.integer.value[0] = es8326->hpl_vol; 132 133 return 0; 134 } 135 136 static int es8326_hplvol_set(struct snd_kcontrol *kcontrol, 137 struct snd_ctl_elem_value *ucontrol) 138 { 139 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 140 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 141 unsigned int hp_vol; 142 143 hp_vol = ucontrol->value.integer.value[0]; 144 if (hp_vol > 5) 145 return -EINVAL; 146 if (es8326->hpl_vol != hp_vol) { 147 es8326->hpl_vol = hp_vol; 148 if (hp_vol >= 3) 149 hp_vol++; 150 regmap_update_bits(es8326->regmap, ES8326_HP_VOL, 151 0x70, (hp_vol << 4)); 152 return 1; 153 } 154 155 return 0; 156 } 157 158 static int es8326_hprvol_get(struct snd_kcontrol *kcontrol, 159 struct snd_ctl_elem_value *ucontrol) 160 { 161 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 162 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 163 164 ucontrol->value.integer.value[0] = es8326->hpr_vol; 165 166 return 0; 167 } 168 169 static int es8326_hprvol_set(struct snd_kcontrol *kcontrol, 170 struct snd_ctl_elem_value *ucontrol) 171 { 172 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 173 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 174 unsigned int hp_vol; 175 176 hp_vol = ucontrol->value.integer.value[0]; 177 if (hp_vol > 5) 178 return -EINVAL; 179 if (es8326->hpr_vol != hp_vol) { 180 es8326->hpr_vol = hp_vol; 181 if (hp_vol >= 3) 182 hp_vol++; 183 regmap_update_bits(es8326->regmap, ES8326_HP_VOL, 184 0x07, hp_vol); 185 return 1; 186 } 187 188 return 0; 189 } 190 191 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dac_vol_tlv, -9550, 50, 0); 192 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_vol_tlv, -9550, 50, 0); 193 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_analog_pga_tlv, 0, 300, 0); 194 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_pga_tlv, 0, 600, 0); 195 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(softramp_rate, 0, 100, 0); 196 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_target_tlv, -3200, 200, 0); 197 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_recovery_tlv, -125, 250, 0); 198 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dre_gain_tlv, -9550, 400, 0); 199 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dre_gate_tlv, -9600, 600, 0); 200 201 static const char *const winsize[] = { 202 "0.25db/2 LRCK", 203 "0.25db/4 LRCK", 204 "0.25db/8 LRCK", 205 "0.25db/16 LRCK", 206 "0.25db/32 LRCK", 207 "0.25db/64 LRCK", 208 "0.25db/128 LRCK", 209 "0.25db/256 LRCK", 210 "0.25db/512 LRCK", 211 "0.25db/1024 LRCK", 212 "0.25db/2048 LRCK", 213 "0.25db/4096 LRCK", 214 "0.25db/8192 LRCK", 215 "0.25db/16384 LRCK", 216 "0.25db/32768 LRCK", 217 "0.25db/65536 LRCK", 218 }; 219 220 static const char *const dacpol_txt[] = { 221 "Normal", "R Invert", "L Invert", "L + R Invert" }; 222 223 static const char *const hp_spkvol_switch[] = { 224 "HPVOL: HPL+HPL, SPKVOL: HPL+HPL", 225 "HPVOL: HPL+HPR, SPKVOL: HPL+HPR", 226 "HPVOL: HPL+HPL, SPKVOL: SPKL+SPKR", 227 "HPVOL: HPL+HPR, SPKVOL: SPKL+SPKR", 228 }; 229 230 static const struct soc_enum dacpol = 231 SOC_ENUM_SINGLE(ES8326_DAC_DSM, 4, 4, dacpol_txt); 232 static const struct soc_enum dre_winsize = 233 SOC_ENUM_SINGLE(ES8326_ADC_DRE, 0, 16, winsize); 234 static const struct soc_enum alc_winsize = 235 SOC_ENUM_SINGLE(ES8326_ADC_RAMPRATE, 4, 16, winsize); 236 static const struct soc_enum drc_winsize = 237 SOC_ENUM_SINGLE(ES8326_DRC_WINSIZE, 4, 16, winsize); 238 static const struct soc_enum hpvol_spkvol_switch = 239 SOC_ENUM_SINGLE(ES8326_HP_MISC, 6, 4, hp_spkvol_switch); 240 241 static const struct snd_kcontrol_new es8326_snd_controls[] = { 242 SOC_SINGLE_TLV("DAC Playback Volume", ES8326_DACL_VOL, 0, 0xbf, 0, dac_vol_tlv), 243 SOC_ENUM("Playback Polarity", dacpol), 244 SOC_SINGLE_TLV("DAC Ramp Rate", ES8326_DAC_RAMPRATE, 0, 0x0f, 0, softramp_rate), 245 SOC_SINGLE_TLV("DRC Recovery Level", ES8326_DRC_RECOVERY, 0, 4, 0, drc_recovery_tlv), 246 SOC_ENUM("DRC Winsize", drc_winsize), 247 SOC_SINGLE_TLV("DRC Target Level", ES8326_DRC_WINSIZE, 0, 0x0f, 0, drc_target_tlv), 248 249 SOC_DOUBLE_R_TLV("ADC Capture Volume", ES8326_ADC1_VOL, ES8326_ADC2_VOL, 0, 0xff, 0, 250 adc_vol_tlv), 251 SOC_DOUBLE_TLV("ADC PGA Volume", ES8326_ADC_SCALE, 4, 0, 5, 0, adc_pga_tlv), 252 SOC_SINGLE_TLV("ADC PGA Gain Volume", ES8326_PGAGAIN, 0, 10, 0, adc_analog_pga_tlv), 253 SOC_SINGLE("ADC PGA SE Switch", ES8326_PGAGAIN, 7, 1, 0), 254 SOC_SINGLE_TLV("ADC Ramp Rate", ES8326_ADC_RAMPRATE, 0, 0x0f, 0, softramp_rate), 255 SOC_SINGLE("ADC4 DRE Switch", ES8326_ADC_DRE, 4, 1, 0), 256 SOC_SINGLE("ADC3 DRE Switch", ES8326_ADC_DRE, 5, 1, 0), 257 SOC_SINGLE("ADC2 DRE Switch", ES8326_ADC_DRE, 6, 1, 0), 258 SOC_SINGLE("ADC1 DRE Switch", ES8326_ADC_DRE, 7, 1, 0), 259 SOC_ENUM("DRE Winsize", dre_winsize), 260 SOC_SINGLE("DRE Gain Switch", ES8326_ADC_DRE_GAIN, 5, 1, 0), 261 SOC_SINGLE_TLV("DRE Gain Volume", ES8326_ADC_DRE_GAIN, 262 0, 0x1F, 0, dre_gain_tlv), 263 SOC_SINGLE_TLV("DRE Gate Volume", ES8326_ADC_DRE_GATE, 264 4, 0x07, 0, dre_gate_tlv), 265 SOC_SINGLE("ALC Capture Switch", ES8326_ALC_RECOVERY, 3, 1, 0), 266 SOC_SINGLE_TLV("ALC Capture Recovery Level", ES8326_ALC_LEVEL, 267 0, 4, 0, drc_recovery_tlv), 268 SOC_ENUM("ALC Capture Winsize", alc_winsize), 269 SOC_SINGLE_TLV("ALC Capture Target Level", ES8326_ALC_LEVEL, 270 0, 0x0f, 0, drc_target_tlv), 271 272 SOC_SINGLE_EXT("CROSSTALK1", SND_SOC_NOPM, 0, 31, 0, 273 es8326_crosstalk1_get, es8326_crosstalk1_set), 274 SOC_SINGLE_EXT("CROSSTALK2", SND_SOC_NOPM, 0, 31, 0, 275 es8326_crosstalk2_get, es8326_crosstalk2_set), 276 SOC_SINGLE_EXT("HPL Volume", SND_SOC_NOPM, 0, 5, 0, 277 es8326_hplvol_get, es8326_hplvol_set), 278 SOC_SINGLE_EXT("HPR Volume", SND_SOC_NOPM, 0, 5, 0, 279 es8326_hprvol_get, es8326_hprvol_set), 280 281 SOC_SINGLE_TLV("HPL Playback Volume", ES8326_DACL_VOL, 0, 0xbf, 0, dac_vol_tlv), 282 SOC_SINGLE_TLV("HPR Playback Volume", ES8326_DACR_VOL, 0, 0xbf, 0, dac_vol_tlv), 283 SOC_SINGLE_TLV("SPKL Playback Volume", ES8326_SPKL_VOL, 0, 0xbf, 0, dac_vol_tlv), 284 SOC_SINGLE_TLV("SPKR Playback Volume", ES8326_SPKR_VOL, 0, 0xbf, 0, dac_vol_tlv), 285 286 SOC_ENUM("HPVol SPKVol Switch", hpvol_spkvol_switch), 287 }; 288 289 static const struct snd_soc_dapm_widget es8326_dapm_widgets[] = { 290 SND_SOC_DAPM_INPUT("MIC1"), 291 SND_SOC_DAPM_INPUT("MIC2"), 292 SND_SOC_DAPM_INPUT("MIC3"), 293 SND_SOC_DAPM_INPUT("MIC4"), 294 295 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 296 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 297 298 /* Digital Interface */ 299 SND_SOC_DAPM_AIF_OUT("I2S OUT", "I2S1 Capture", 0, SND_SOC_NOPM, 0, 0), 300 SND_SOC_DAPM_AIF_IN("I2S IN", "I2S1 Playback", 0, SND_SOC_NOPM, 0, 0), 301 302 /* Analog Power Supply*/ 303 SND_SOC_DAPM_DAC("Right DAC", NULL, ES8326_ANA_PDN, 0, 1), 304 SND_SOC_DAPM_DAC("Left DAC", NULL, ES8326_ANA_PDN, 1, 1), 305 SND_SOC_DAPM_SUPPLY("MICBIAS1", ES8326_ANA_MICBIAS, 2, 0, NULL, 0), 306 SND_SOC_DAPM_SUPPLY("MICBIAS2", ES8326_ANA_MICBIAS, 3, 0, NULL, 0), 307 308 SND_SOC_DAPM_PGA("LHPMIX", ES8326_DAC2HPMIX, 7, 0, NULL, 0), 309 SND_SOC_DAPM_PGA("RHPMIX", ES8326_DAC2HPMIX, 3, 0, NULL, 0), 310 311 SND_SOC_DAPM_OUTPUT("HPOL"), 312 SND_SOC_DAPM_OUTPUT("HPOR"), 313 }; 314 315 static const struct snd_soc_dapm_route es8326_dapm_routes[] = { 316 {"ADC L", NULL, "MIC1"}, 317 {"ADC R", NULL, "MIC2"}, 318 {"ADC L", NULL, "MIC3"}, 319 {"ADC R", NULL, "MIC4"}, 320 321 {"I2S OUT", NULL, "ADC L"}, 322 {"I2S OUT", NULL, "ADC R"}, 323 324 {"Right DAC", NULL, "I2S IN"}, 325 {"Left DAC", NULL, "I2S IN"}, 326 327 {"LHPMIX", NULL, "Left DAC"}, 328 {"RHPMIX", NULL, "Right DAC"}, 329 330 {"HPOL", NULL, "LHPMIX"}, 331 {"HPOR", NULL, "RHPMIX"}, 332 }; 333 334 static bool es8326_volatile_register(struct device *dev, unsigned int reg) 335 { 336 switch (reg) { 337 case ES8326_HPL_OFFSET_INI: 338 case ES8326_HPR_OFFSET_INI: 339 case ES8326_HPDET_STA: 340 case ES8326_CTIA_OMTP_STA: 341 case ES8326_CSM_MUTE_STA: 342 return true; 343 default: 344 return false; 345 } 346 } 347 348 static bool es8326_writeable_register(struct device *dev, unsigned int reg) 349 { 350 switch (reg) { 351 case ES8326_BIAS_SW1: 352 case ES8326_BIAS_SW2: 353 case ES8326_BIAS_SW3: 354 case ES8326_BIAS_SW4: 355 case ES8326_ADC_HPFS1: 356 case ES8326_ADC_HPFS2: 357 return false; 358 default: 359 return true; 360 } 361 } 362 363 static const struct regmap_config es8326_regmap_config = { 364 .reg_bits = 8, 365 .val_bits = 8, 366 .max_register = 0xff, 367 .use_single_read = true, 368 .use_single_write = true, 369 .volatile_reg = es8326_volatile_register, 370 .writeable_reg = es8326_writeable_register, 371 .cache_type = REGCACHE_RBTREE, 372 }; 373 374 struct _coeff_div { 375 u16 fs; 376 u32 rate; 377 u32 mclk; 378 u8 reg4; 379 u8 reg5; 380 u8 reg6; 381 u8 reg7; 382 u8 reg8; 383 u8 reg9; 384 u8 rega; 385 u8 regb; 386 }; 387 388 /* codec hifi mclk clock divider coefficients */ 389 /* {ratio, LRCK, MCLK, REG04, REG05, REG06, REG07, REG08, REG09, REG10, REG11} */ 390 static const struct _coeff_div coeff_div_v0[] = { 391 {64, 8000, 512000, 0x60, 0x01, 0x0F, 0x75, 0x0A, 0x1B, 0x1F, 0x7F}, 392 {64, 16000, 1024000, 0x20, 0x00, 0x33, 0x35, 0x0A, 0x1B, 0x1F, 0x3F}, 393 {64, 44100, 2822400, 0xE0, 0x00, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 394 {64, 48000, 3072000, 0xE0, 0x00, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 395 {128, 8000, 1024000, 0x60, 0x00, 0x33, 0x35, 0x0A, 0x1B, 0x1F, 0x7F}, 396 {128, 16000, 2048000, 0x20, 0x00, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x3F}, 397 {128, 44100, 5644800, 0xE0, 0x01, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 398 {128, 48000, 6144000, 0xE0, 0x01, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 399 400 {192, 32000, 6144000, 0xE0, 0x02, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 401 {256, 8000, 2048000, 0x60, 0x00, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x7F}, 402 {256, 16000, 4096000, 0x20, 0x01, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x3F}, 403 {256, 44100, 11289600, 0xE0, 0x00, 0x30, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 404 {256, 48000, 12288000, 0xE0, 0x00, 0x30, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 405 {384, 32000, 12288000, 0xE0, 0x05, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 406 {400, 48000, 19200000, 0xE9, 0x04, 0x0F, 0x6d, 0x4A, 0x0A, 0x1F, 0x1F}, 407 408 {500, 48000, 24000000, 0xF8, 0x04, 0x3F, 0x6D, 0x4A, 0x0A, 0x1F, 0x1F}, 409 {512, 8000, 4096000, 0x60, 0x01, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x7F}, 410 {512, 16000, 8192000, 0x20, 0x00, 0x30, 0x35, 0x0A, 0x1B, 0x1F, 0x3F}, 411 {512, 44100, 22579200, 0xE0, 0x00, 0x00, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 412 {512, 48000, 24576000, 0xE0, 0x00, 0x00, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 413 {768, 32000, 24576000, 0xE0, 0x02, 0x30, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 414 {1024, 8000, 8192000, 0x60, 0x00, 0x30, 0x35, 0x0A, 0x1B, 0x1F, 0x7F}, 415 {1024, 16000, 16384000, 0x20, 0x00, 0x00, 0x35, 0x0A, 0x1B, 0x1F, 0x3F}, 416 }; 417 418 static const struct _coeff_div coeff_div_v3[] = { 419 {32, 8000, 256000, 0x60, 0x00, 0x0F, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 420 {32, 16000, 512000, 0x20, 0x00, 0x0D, 0x75, 0x8A, 0x1B, 0x1F, 0x3F}, 421 {32, 44100, 1411200, 0x00, 0x00, 0x13, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F}, 422 {32, 48000, 1536000, 0x00, 0x00, 0x13, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F}, 423 {36, 8000, 288000, 0x20, 0x00, 0x0D, 0x75, 0x8A, 0x1B, 0x23, 0x47}, 424 {36, 16000, 576000, 0x20, 0x00, 0x0D, 0x75, 0x8A, 0x1B, 0x23, 0x47}, 425 {48, 8000, 384000, 0x60, 0x02, 0x1F, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 426 {48, 16000, 768000, 0x20, 0x02, 0x0F, 0x75, 0x8A, 0x1B, 0x1F, 0x3F}, 427 {48, 48000, 2304000, 0x00, 0x02, 0x0D, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F}, 428 429 {64, 8000, 512000, 0x60, 0x00, 0x35, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 430 {64, 16000, 1024000, 0x20, 0x00, 0x05, 0x75, 0x8A, 0x1B, 0x1F, 0x3F}, 431 {64, 44100, 2822400, 0xE0, 0x00, 0x31, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 432 {64, 48000, 3072000, 0xE0, 0x00, 0x31, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 433 {72, 8000, 576000, 0x20, 0x00, 0x13, 0x35, 0x8A, 0x1B, 0x23, 0x47}, 434 {72, 16000, 1152000, 0x20, 0x00, 0x05, 0x75, 0x8A, 0x1B, 0x23, 0x47}, 435 {96, 8000, 768000, 0x60, 0x02, 0x1D, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 436 {96, 16000, 1536000, 0x20, 0x02, 0x0D, 0x75, 0x8A, 0x1B, 0x1F, 0x3F}, 437 {100, 48000, 4800000, 0x04, 0x04, 0x3F, 0x6D, 0xB8, 0x08, 0x4f, 0x1f}, 438 {125, 48000, 6000000, 0x04, 0x04, 0x1F, 0x2D, 0x8A, 0x0A, 0x27, 0x27}, 439 440 {128, 8000, 1024000, 0x60, 0x00, 0x05, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 441 {128, 16000, 2048000, 0x20, 0x00, 0x31, 0x35, 0x08, 0x19, 0x1F, 0x3F}, 442 {128, 44100, 5644800, 0xE0, 0x00, 0x01, 0x2D, 0x48, 0x08, 0x1F, 0x1F}, 443 {128, 48000, 6144000, 0xE0, 0x00, 0x01, 0x2D, 0x48, 0x08, 0x1F, 0x1F}, 444 {144, 8000, 1152000, 0x20, 0x00, 0x03, 0x35, 0x8A, 0x1B, 0x23, 0x47}, 445 {144, 16000, 2304000, 0x20, 0x00, 0x11, 0x35, 0x8A, 0x1B, 0x23, 0x47}, 446 {192, 8000, 1536000, 0x60, 0x02, 0x0D, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 447 {192, 32000, 6144000, 0xE0, 0x02, 0x31, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 448 {192, 16000, 3072000, 0x20, 0x02, 0x05, 0x75, 0xCA, 0x1B, 0x1F, 0x3F}, 449 450 {200, 48000, 9600000, 0x04, 0x04, 0x0F, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 451 {250, 48000, 12000000, 0x04, 0x04, 0x0F, 0x2D, 0xCA, 0x0A, 0x27, 0x27}, 452 {256, 8000, 2048000, 0x60, 0x00, 0x31, 0x35, 0x08, 0x19, 0x1F, 0x7F}, 453 {256, 16000, 4096000, 0x20, 0x00, 0x01, 0x35, 0x08, 0x19, 0x1F, 0x3F}, 454 {256, 44100, 11289600, 0xE0, 0x01, 0x01, 0x2D, 0x48, 0x08, 0x1F, 0x1F}, 455 {256, 48000, 12288000, 0xE0, 0x01, 0x01, 0x2D, 0x48, 0x08, 0x1F, 0x1F}, 456 {288, 8000, 2304000, 0x20, 0x00, 0x01, 0x35, 0x8A, 0x1B, 0x23, 0x47}, 457 {384, 8000, 3072000, 0x60, 0x02, 0x05, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 458 {384, 16000, 6144000, 0x20, 0x02, 0x03, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 459 {384, 32000, 12288000, 0xE0, 0x02, 0x01, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 460 {384, 48000, 18432000, 0x00, 0x02, 0x01, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F}, 461 462 {400, 48000, 19200000, 0xE4, 0x04, 0x35, 0x6d, 0xCA, 0x0A, 0x1F, 0x1F}, 463 {500, 48000, 24000000, 0xF8, 0x04, 0x3F, 0x6D, 0xCA, 0x0A, 0x1F, 0x1F}, 464 {512, 8000, 4096000, 0x60, 0x00, 0x01, 0x08, 0x19, 0x1B, 0x1F, 0x7F}, 465 {512, 16000, 8192000, 0x20, 0x00, 0x30, 0x35, 0x08, 0x19, 0x1F, 0x3F}, 466 {512, 44100, 22579200, 0xE0, 0x00, 0x00, 0x2D, 0x48, 0x08, 0x1F, 0x1F}, 467 {512, 48000, 24576000, 0xE0, 0x00, 0x00, 0x2D, 0x48, 0x08, 0x1F, 0x1F}, 468 {768, 8000, 6144000, 0x60, 0x02, 0x11, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 469 {768, 16000, 12288000, 0x20, 0x02, 0x01, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 470 {768, 32000, 24576000, 0xE0, 0x02, 0x30, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 471 {800, 48000, 38400000, 0x00, 0x18, 0x13, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F}, 472 473 {1024, 8000, 8192000, 0x60, 0x00, 0x30, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 474 {1024, 16000, 16384000, 0x20, 0x00, 0x00, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 475 {1152, 16000, 18432000, 0x20, 0x08, 0x11, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 476 {1536, 8000, 12288000, 0x60, 0x02, 0x01, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 477 {1536, 16000, 24576000, 0x20, 0x02, 0x10, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 478 {1625, 8000, 13000000, 0x0C, 0x18, 0x1F, 0x2D, 0x8A, 0x0A, 0x27, 0x27}, 479 {1625, 16000, 26000000, 0x0C, 0x18, 0x1F, 0x2D, 0x8A, 0x0A, 0x27, 0x27}, 480 {2048, 8000, 16384000, 0x60, 0x00, 0x00, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 481 {2304, 8000, 18432000, 0x40, 0x02, 0x10, 0x35, 0x8A, 0x1B, 0x1F, 0x5F}, 482 {3072, 8000, 24576000, 0x60, 0x02, 0x10, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 483 {3250, 8000, 26000000, 0x0C, 0x18, 0x0F, 0x2D, 0x8A, 0x0A, 0x27, 0x27}, 484 }; 485 486 static inline int get_coeff(int mclk, int rate, int array, 487 const struct _coeff_div *coeff_div) 488 { 489 int i; 490 491 for (i = 0; i < array; i++) { 492 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk) 493 return i; 494 } 495 496 return -EINVAL; 497 } 498 499 static int es8326_set_dai_sysclk(struct snd_soc_dai *codec_dai, 500 int clk_id, unsigned int freq, int dir) 501 { 502 struct snd_soc_component *codec = codec_dai->component; 503 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(codec); 504 505 es8326->sysclk = freq; 506 507 return 0; 508 } 509 510 static int es8326_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 511 { 512 struct snd_soc_component *component = codec_dai->component; 513 u8 iface = 0; 514 515 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 516 case SND_SOC_DAIFMT_CBC_CFP: 517 snd_soc_component_update_bits(component, ES8326_RESET, 518 ES8326_MASTER_MODE_EN, ES8326_MASTER_MODE_EN); 519 break; 520 case SND_SOC_DAIFMT_CBC_CFC: 521 break; 522 default: 523 return -EINVAL; 524 } 525 526 /* interface format */ 527 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 528 case SND_SOC_DAIFMT_I2S: 529 break; 530 case SND_SOC_DAIFMT_RIGHT_J: 531 dev_err(component->dev, "Codec driver does not support right justified\n"); 532 return -EINVAL; 533 case SND_SOC_DAIFMT_LEFT_J: 534 iface |= ES8326_DAIFMT_LEFT_J; 535 break; 536 case SND_SOC_DAIFMT_DSP_A: 537 iface |= ES8326_DAIFMT_DSP_A; 538 break; 539 case SND_SOC_DAIFMT_DSP_B: 540 iface |= ES8326_DAIFMT_DSP_B; 541 break; 542 default: 543 return -EINVAL; 544 } 545 546 snd_soc_component_update_bits(component, ES8326_FMT, ES8326_DAIFMT_MASK, iface); 547 548 return 0; 549 } 550 551 static int es8326_pcm_hw_params(struct snd_pcm_substream *substream, 552 struct snd_pcm_hw_params *params, 553 struct snd_soc_dai *dai) 554 { 555 struct snd_soc_component *component = dai->component; 556 const struct _coeff_div *coeff_div; 557 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 558 u8 srate = 0; 559 int coeff, array; 560 561 if (es8326->version == 0) { 562 coeff_div = coeff_div_v0; 563 array = ARRAY_SIZE(coeff_div_v0); 564 } else { 565 coeff_div = coeff_div_v3; 566 array = ARRAY_SIZE(coeff_div_v3); 567 } 568 coeff = get_coeff(es8326->sysclk, params_rate(params), array, coeff_div); 569 /* bit size */ 570 switch (params_format(params)) { 571 case SNDRV_PCM_FORMAT_S16_LE: 572 srate |= ES8326_S16_LE; 573 break; 574 case SNDRV_PCM_FORMAT_S20_3LE: 575 srate |= ES8326_S20_3_LE; 576 break; 577 case SNDRV_PCM_FORMAT_S18_3LE: 578 srate |= ES8326_S18_LE; 579 break; 580 case SNDRV_PCM_FORMAT_S24_LE: 581 srate |= ES8326_S24_LE; 582 break; 583 case SNDRV_PCM_FORMAT_S32_LE: 584 srate |= ES8326_S32_LE; 585 break; 586 default: 587 return -EINVAL; 588 } 589 590 /* set iface & srate */ 591 snd_soc_component_update_bits(component, ES8326_FMT, ES8326_DATA_LEN_MASK, srate); 592 593 if (coeff >= 0) { 594 regmap_write(es8326->regmap, ES8326_CLK_DIV1, 595 coeff_div[coeff].reg4); 596 regmap_write(es8326->regmap, ES8326_CLK_DIV2, 597 coeff_div[coeff].reg5); 598 regmap_write(es8326->regmap, ES8326_CLK_DLL, 599 coeff_div[coeff].reg6); 600 regmap_write(es8326->regmap, ES8326_CLK_MUX, 601 coeff_div[coeff].reg7); 602 regmap_write(es8326->regmap, ES8326_CLK_ADC_SEL, 603 coeff_div[coeff].reg8); 604 regmap_write(es8326->regmap, ES8326_CLK_DAC_SEL, 605 coeff_div[coeff].reg9); 606 regmap_write(es8326->regmap, ES8326_CLK_ADC_OSR, 607 coeff_div[coeff].rega); 608 regmap_write(es8326->regmap, ES8326_CLK_DAC_OSR, 609 coeff_div[coeff].regb); 610 } else { 611 dev_warn(component->dev, "Clock coefficients do not match"); 612 } 613 614 return 0; 615 } 616 617 static int es8326_mute(struct snd_soc_dai *dai, int mute, int direction) 618 { 619 struct snd_soc_component *component = dai->component; 620 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 621 unsigned int offset_l, offset_r; 622 623 if (mute) { 624 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 625 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF); 626 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE, 627 ES8326_MUTE_MASK, ES8326_MUTE); 628 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 629 0x30, 0x00); 630 } else { 631 regmap_update_bits(es8326->regmap, ES8326_ADC_MUTE, 632 0x0F, 0x0F); 633 if (es8326->version > ES8326_VERSION_B) { 634 regmap_update_bits(es8326->regmap, ES8326_VMIDSEL, 0x40, 0x40); 635 regmap_update_bits(es8326->regmap, ES8326_ANA_MICBIAS, 0x70, 0x30); 636 } 637 } 638 } else { 639 if (!es8326->calibrated) { 640 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_FORCE_CAL); 641 msleep(30); 642 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF); 643 regmap_read(es8326->regmap, ES8326_HPL_OFFSET_INI, &offset_l); 644 regmap_read(es8326->regmap, ES8326_HPR_OFFSET_INI, &offset_r); 645 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c); 646 regmap_write(es8326->regmap, ES8326_HPL_OFFSET_INI, offset_l); 647 regmap_write(es8326->regmap, ES8326_HPR_OFFSET_INI, offset_r); 648 es8326->calibrated = true; 649 } 650 regmap_update_bits(es8326->regmap, ES8326_CLK_INV, 0xc0, 0x00); 651 regmap_update_bits(es8326->regmap, ES8326_CLK_MUX, 0x80, 0x00); 652 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 653 regmap_update_bits(es8326->regmap, ES8326_DAC_DSM, 0x01, 0x01); 654 usleep_range(1000, 5000); 655 regmap_update_bits(es8326->regmap, ES8326_DAC_DSM, 0x01, 0x00); 656 usleep_range(1000, 5000); 657 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x30, 0x20); 658 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x30, 0x30); 659 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa1); 660 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_ON); 661 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE, 662 ES8326_MUTE_MASK, ~(ES8326_MUTE)); 663 } else { 664 msleep(300); 665 if (es8326->version > ES8326_VERSION_B) { 666 regmap_update_bits(es8326->regmap, ES8326_ANA_MICBIAS, 0x70, 0x70); 667 regmap_update_bits(es8326->regmap, ES8326_VMIDSEL, 0x40, 0x00); 668 } 669 regmap_update_bits(es8326->regmap, ES8326_ADC_MUTE, 670 0x0F, 0x00); 671 } 672 } 673 return 0; 674 } 675 676 static int es8326_set_bias_level(struct snd_soc_component *codec, 677 enum snd_soc_bias_level level) 678 { 679 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(codec); 680 int ret; 681 682 switch (level) { 683 case SND_SOC_BIAS_ON: 684 ret = clk_prepare_enable(es8326->mclk); 685 if (ret) 686 return ret; 687 688 regmap_update_bits(es8326->regmap, ES8326_RESET, 0x02, 0x02); 689 usleep_range(5000, 10000); 690 regmap_write(es8326->regmap, ES8326_INTOUT_IO, es8326->interrupt_clk); 691 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO, 692 (ES8326_IO_DMIC_CLK << ES8326_SDINOUT1_SHIFT)); 693 regmap_write(es8326->regmap, ES8326_PGA_PDN, 0x40); 694 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x00); 695 regmap_update_bits(es8326->regmap, ES8326_CLK_CTL, 0x20, 0x20); 696 regmap_update_bits(es8326->regmap, ES8326_RESET, 0x02, 0x00); 697 if (es8326->version > ES8326_VERSION_B) { 698 regmap_update_bits(es8326->regmap, ES8326_VMIDSEL, 0x40, 0x40); 699 regmap_update_bits(es8326->regmap, ES8326_ANA_MICBIAS, 0x70, 0x30); 700 } 701 break; 702 case SND_SOC_BIAS_PREPARE: 703 break; 704 case SND_SOC_BIAS_STANDBY: 705 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x3b); 706 regmap_update_bits(es8326->regmap, ES8326_CLK_CTL, 0x20, 0x00); 707 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO, ES8326_IO_INPUT); 708 if (es8326->version > ES8326_VERSION_B) { 709 regmap_update_bits(es8326->regmap, ES8326_VMIDSEL, 0x40, 0x40); 710 regmap_update_bits(es8326->regmap, ES8326_ANA_MICBIAS, 0x70, 0x10); 711 } 712 regmap_update_bits(es8326->regmap, ES8326_CLK_INV, 0xc0, 0xc0); 713 regmap_update_bits(es8326->regmap, ES8326_CLK_MUX, 0x80, 0x80); 714 break; 715 case SND_SOC_BIAS_OFF: 716 clk_disable_unprepare(es8326->mclk); 717 break; 718 } 719 720 return 0; 721 } 722 723 #define es8326_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 724 SNDRV_PCM_FMTBIT_S24_LE) 725 726 static const struct snd_soc_dai_ops es8326_ops = { 727 .hw_params = es8326_pcm_hw_params, 728 .set_fmt = es8326_set_dai_fmt, 729 .set_sysclk = es8326_set_dai_sysclk, 730 .mute_stream = es8326_mute, 731 .no_capture_mute = 0, 732 }; 733 734 static struct snd_soc_dai_driver es8326_dai = { 735 .name = "ES8326 HiFi", 736 .playback = { 737 .stream_name = "Playback", 738 .channels_min = 1, 739 .channels_max = 2, 740 .rates = SNDRV_PCM_RATE_8000_48000, 741 .formats = es8326_FORMATS, 742 }, 743 .capture = { 744 .stream_name = "Capture", 745 .channels_min = 1, 746 .channels_max = 2, 747 .rates = SNDRV_PCM_RATE_8000_48000, 748 .formats = es8326_FORMATS, 749 }, 750 .ops = &es8326_ops, 751 .symmetric_rate = 1, 752 }; 753 754 static void es8326_enable_micbias(struct snd_soc_component *component) 755 { 756 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 757 758 snd_soc_dapm_mutex_lock(dapm); 759 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS1"); 760 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS2"); 761 snd_soc_dapm_sync_unlocked(dapm); 762 snd_soc_dapm_mutex_unlock(dapm); 763 } 764 765 static void es8326_disable_micbias(struct snd_soc_component *component) 766 { 767 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 768 769 snd_soc_dapm_mutex_lock(dapm); 770 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS1"); 771 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS2"); 772 snd_soc_dapm_sync_unlocked(dapm); 773 snd_soc_dapm_mutex_unlock(dapm); 774 } 775 776 /* 777 * For button detection, set the following in soundcard 778 * snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE); 779 * snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEUP); 780 * snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN); 781 */ 782 static void es8326_jack_button_handler(struct work_struct *work) 783 { 784 struct es8326_priv *es8326 = 785 container_of(work, struct es8326_priv, button_press_work.work); 786 struct snd_soc_component *comp = es8326->component; 787 unsigned int iface; 788 static int button_to_report, press_count; 789 static int prev_button, cur_button; 790 791 if (!(es8326->jack->status & SND_JACK_HEADSET)) /* Jack unplugged */ 792 return; 793 794 guard(mutex)(&es8326->lock); 795 iface = snd_soc_component_read(comp, ES8326_HPDET_STA); 796 switch (iface) { 797 case 0x93: 798 /* pause button detected */ 799 cur_button = SND_JACK_BTN_0; 800 break; 801 case 0x6f: 802 case 0x4b: 803 /* button volume up */ 804 if ((iface == 0x6f) && (es8326->version > ES8326_VERSION_B)) 805 cur_button = SND_JACK_BTN_0; 806 else 807 cur_button = SND_JACK_BTN_1; 808 break; 809 case 0x27: 810 /* button volume down */ 811 cur_button = SND_JACK_BTN_2; 812 break; 813 case 0x1e: 814 case 0xe2: 815 /* button released or not pressed */ 816 cur_button = 0; 817 break; 818 default: 819 break; 820 } 821 822 if ((prev_button == cur_button) && (cur_button != 0)) { 823 press_count++; 824 if (press_count > 3) { 825 /* report a press every 120ms */ 826 snd_soc_jack_report(es8326->jack, cur_button, 827 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2); 828 press_count = 0; 829 } 830 button_to_report = cur_button; 831 queue_delayed_work(system_dfl_wq, &es8326->button_press_work, 832 msecs_to_jiffies(35)); 833 } else if (prev_button != cur_button) { 834 /* mismatch, detect again */ 835 prev_button = cur_button; 836 queue_delayed_work(system_dfl_wq, &es8326->button_press_work, 837 msecs_to_jiffies(35)); 838 } else { 839 /* released or no pressed */ 840 if (button_to_report != 0) { 841 snd_soc_jack_report(es8326->jack, button_to_report, 842 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2); 843 snd_soc_jack_report(es8326->jack, 0, 844 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2); 845 button_to_report = 0; 846 } 847 es8326_disable_micbias(es8326->component); 848 } 849 } 850 851 static void es8326_jack_detect_handler(struct work_struct *work) 852 { 853 struct es8326_priv *es8326 = 854 container_of(work, struct es8326_priv, jack_detect_work.work); 855 struct snd_soc_component *comp = es8326->component; 856 unsigned int iface; 857 858 guard(mutex)(&es8326->lock); 859 iface = snd_soc_component_read(comp, ES8326_HPDET_STA); 860 dev_dbg(comp->dev, "gpio flag %#04x", iface); 861 862 if ((es8326->jack_remove_retry == 1) && (es8326->version < ES8326_VERSION_B)) { 863 if (iface & ES8326_HPINSERT_FLAG) 864 es8326->jack_remove_retry = 2; 865 else 866 es8326->jack_remove_retry = 0; 867 868 dev_dbg(comp->dev, "remove event check, set HPJACK_POL normal, cnt = %d\n", 869 es8326->jack_remove_retry); 870 /* 871 * Inverted HPJACK_POL bit to trigger one IRQ to double check HP Removal event 872 */ 873 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 874 ES8326_HP_DET_JACK_POL, (es8326->jd_inverted ? 875 ~es8326->jack_pol : es8326->jack_pol)); 876 return; 877 } 878 879 if ((iface & ES8326_HPINSERT_FLAG) == 0) { 880 /* Jack unplugged or spurious IRQ */ 881 dev_dbg(comp->dev, "No headset detected\n"); 882 es8326_disable_micbias(es8326->component); 883 if (es8326->jack->status & SND_JACK_HEADPHONE) { 884 dev_dbg(comp->dev, "Report hp remove event\n"); 885 snd_soc_jack_report(es8326->jack, 0, 886 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2); 887 snd_soc_jack_report(es8326->jack, 0, SND_JACK_HEADSET); 888 /* mute adc when mic path switch */ 889 regmap_write(es8326->regmap, ES8326_ADC1_SRC, 0x44); 890 regmap_write(es8326->regmap, ES8326_ADC2_SRC, 0x66); 891 } 892 es8326->hp = 0; 893 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x01); 894 regmap_write(es8326->regmap, ES8326_SYS_BIAS, 0x0a); 895 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x0f, 0x03); 896 regmap_write(es8326->regmap, ES8326_INT_SOURCE, ES8326_INT_SRC_PIN9); 897 /* 898 * Inverted HPJACK_POL bit to trigger one IRQ to double check HP Removal event 899 */ 900 if ((es8326->jack_remove_retry == 0) && (es8326->version < ES8326_VERSION_B)) { 901 es8326->jack_remove_retry = 1; 902 dev_dbg(comp->dev, "remove event check, invert HPJACK_POL, cnt = %d\n", 903 es8326->jack_remove_retry); 904 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 905 ES8326_HP_DET_JACK_POL, (es8326->jd_inverted ? 906 es8326->jack_pol : ~es8326->jack_pol)); 907 908 } else { 909 es8326->jack_remove_retry = 0; 910 } 911 } else if ((iface & ES8326_HPINSERT_FLAG) == ES8326_HPINSERT_FLAG) { 912 es8326->jack_remove_retry = 0; 913 if (es8326->hp == 0) { 914 dev_dbg(comp->dev, "First insert, start OMTP/CTIA type check\n"); 915 /* 916 * set auto-check mode, then restart jack_detect_work after 400ms. 917 * Don't report jack status. 918 */ 919 regmap_write(es8326->regmap, ES8326_INT_SOURCE, 0x00); 920 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x01); 921 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x10, 0x00); 922 usleep_range(50000, 70000); 923 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x00); 924 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x10, 0x10); 925 usleep_range(50000, 70000); 926 regmap_write(es8326->regmap, ES8326_INT_SOURCE, 927 (ES8326_INT_SRC_PIN9 | ES8326_INT_SRC_BUTTON)); 928 regmap_write(es8326->regmap, ES8326_SYS_BIAS, 0x1f); 929 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x0f, 0x0d); 930 queue_delayed_work(system_dfl_wq, &es8326->jack_detect_work, 931 msecs_to_jiffies(400)); 932 es8326->hp = 1; 933 return; 934 } 935 if (es8326->jack->status & SND_JACK_HEADSET) { 936 /* detect button */ 937 dev_dbg(comp->dev, "button pressed\n"); 938 regmap_write(es8326->regmap, ES8326_INT_SOURCE, 939 (ES8326_INT_SRC_PIN9 | ES8326_INT_SRC_BUTTON)); 940 es8326_enable_micbias(es8326->component); 941 queue_delayed_work(system_dfl_wq, &es8326->button_press_work, 10); 942 return; 943 } 944 if ((iface & ES8326_HPBUTTON_FLAG) == 0x01) { 945 dev_dbg(comp->dev, "Headphone detected\n"); 946 snd_soc_jack_report(es8326->jack, 947 SND_JACK_HEADPHONE, SND_JACK_HEADSET); 948 } else { 949 dev_dbg(comp->dev, "Headset detected\n"); 950 snd_soc_jack_report(es8326->jack, 951 SND_JACK_HEADSET, SND_JACK_HEADSET); 952 regmap_update_bits(es8326->regmap, ES8326_PGA_PDN, 953 0x08, 0x08); 954 regmap_write(es8326->regmap, ES8326_ADC1_SRC, 0x00); 955 regmap_write(es8326->regmap, ES8326_ADC2_SRC, 0x00); 956 regmap_update_bits(es8326->regmap, ES8326_PGA_PDN, 957 0x08, 0x00); 958 usleep_range(10000, 15000); 959 } 960 } 961 } 962 963 static irqreturn_t es8326_irq(int irq, void *dev_id) 964 { 965 struct es8326_priv *es8326 = dev_id; 966 967 if (!es8326->jack) 968 goto out; 969 970 if (es8326->jack->status & SND_JACK_HEADSET) 971 queue_delayed_work(system_dfl_wq, &es8326->jack_detect_work, 972 msecs_to_jiffies(10)); 973 else 974 queue_delayed_work(system_dfl_wq, &es8326->jack_detect_work, 975 msecs_to_jiffies(300)); 976 977 out: 978 return IRQ_HANDLED; 979 } 980 981 static int es8326_calibrate(struct snd_soc_component *component) 982 { 983 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 984 unsigned int reg; 985 unsigned int offset_l, offset_r; 986 987 regmap_read(es8326->regmap, ES8326_CHIP_VERSION, ®); 988 es8326->version = reg; 989 990 if ((es8326->version >= ES8326_VERSION_B) && (es8326->calibrated == false)) { 991 dev_dbg(component->dev, "ES8326_VERSION_B, calibrating\n"); 992 regmap_write(es8326->regmap, ES8326_CLK_INV, 0xc0); 993 regmap_write(es8326->regmap, ES8326_CLK_DIV1, 0x03); 994 regmap_write(es8326->regmap, ES8326_CLK_DLL, 0x30); 995 regmap_write(es8326->regmap, ES8326_CLK_MUX, 0xed); 996 regmap_write(es8326->regmap, ES8326_CLK_DAC_SEL, 0x08); 997 regmap_write(es8326->regmap, ES8326_CLK_TRI, 0xc1); 998 regmap_write(es8326->regmap, ES8326_DAC_MUTE, 0x03); 999 regmap_write(es8326->regmap, ES8326_ANA_VSEL, 0x7f); 1000 regmap_write(es8326->regmap, ES8326_VMIDLOW, 0x23); 1001 regmap_write(es8326->regmap, ES8326_DAC2HPMIX, 0x88); 1002 usleep_range(15000, 20000); 1003 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c); 1004 usleep_range(15000, 20000); 1005 regmap_write(es8326->regmap, ES8326_RESET, 0xc0); 1006 usleep_range(15000, 20000); 1007 1008 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, ES8326_HP_OFF); 1009 regmap_read(es8326->regmap, ES8326_CSM_MUTE_STA, ®); 1010 if ((reg & 0xf0) != 0x40) 1011 msleep(50); 1012 1013 regmap_write(es8326->regmap, ES8326_HP_CAL, 0xd4); 1014 msleep(200); 1015 regmap_write(es8326->regmap, ES8326_HP_CAL, 0x4d); 1016 msleep(200); 1017 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF); 1018 regmap_read(es8326->regmap, ES8326_HPL_OFFSET_INI, &offset_l); 1019 regmap_read(es8326->regmap, ES8326_HPR_OFFSET_INI, &offset_r); 1020 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c); 1021 regmap_write(es8326->regmap, ES8326_HPL_OFFSET_INI, offset_l); 1022 regmap_write(es8326->regmap, ES8326_HPR_OFFSET_INI, offset_r); 1023 regmap_write(es8326->regmap, ES8326_CLK_INV, 0x00); 1024 1025 es8326->calibrated = true; 1026 } 1027 1028 return 0; 1029 } 1030 1031 static void es8326_init(struct snd_soc_component *component) 1032 { 1033 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 1034 1035 regmap_write(es8326->regmap, ES8326_RESET, 0x1f); 1036 regmap_write(es8326->regmap, ES8326_VMIDSEL, 0x3E); 1037 regmap_write(es8326->regmap, ES8326_ANA_LP, 0xf0); 1038 usleep_range(10000, 15000); 1039 regmap_write(es8326->regmap, ES8326_HPJACK_TIMER, 0xd9); 1040 regmap_write(es8326->regmap, ES8326_ANA_MICBIAS, 0xd8); 1041 /* set headphone default type and detect pin */ 1042 regmap_write(es8326->regmap, ES8326_HPDET_TYPE, 0x83); 1043 regmap_write(es8326->regmap, ES8326_CLK_RESAMPLE, 0x05); 1044 1045 /* set internal oscillator as clock source of headpone cp */ 1046 regmap_write(es8326->regmap, ES8326_CLK_DIV_CPC, 0x89); 1047 regmap_write(es8326->regmap, ES8326_CLK_CTL, ES8326_CLK_ON); 1048 /* clock manager reset release */ 1049 regmap_write(es8326->regmap, ES8326_RESET, 0x17); 1050 /* set headphone detection as half scan mode */ 1051 regmap_write(es8326->regmap, ES8326_HP_MISC, 0x3d); 1052 regmap_write(es8326->regmap, ES8326_PULLUP_CTL, 0x00); 1053 1054 /* enable headphone driver */ 1055 regmap_write(es8326->regmap, ES8326_HP_VOL, 0xc4); 1056 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa7); 1057 usleep_range(2000, 5000); 1058 regmap_write(es8326->regmap, ES8326_HP_DRIVER_REF, 0x23); 1059 regmap_write(es8326->regmap, ES8326_HP_DRIVER_REF, 0x33); 1060 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa1); 1061 1062 regmap_write(es8326->regmap, ES8326_CLK_INV, 0x00); 1063 regmap_write(es8326->regmap, ES8326_CLK_VMIDS1, 0xc4); 1064 regmap_write(es8326->regmap, ES8326_CLK_VMIDS2, 0x81); 1065 regmap_write(es8326->regmap, ES8326_CLK_CAL_TIME, 0x00); 1066 /* calibrate for B version */ 1067 es8326_calibrate(component); 1068 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, 0xaa); 1069 regmap_write(es8326->regmap, ES8326_DAC_RAMPRATE, 0x00); 1070 /* turn off headphone out */ 1071 regmap_write(es8326->regmap, ES8326_HP_CAL, 0x00); 1072 /* set ADC and DAC in low power mode */ 1073 regmap_write(es8326->regmap, ES8326_ANA_LP, 0xf0); 1074 1075 regmap_write(es8326->regmap, ES8326_ANA_VSEL, 0x7F); 1076 /* select vdda as micbias source */ 1077 regmap_write(es8326->regmap, ES8326_VMIDLOW, 0x03); 1078 /* set dac dsmclip = 1 */ 1079 regmap_write(es8326->regmap, ES8326_DAC_DSM, 0x08); 1080 regmap_write(es8326->regmap, ES8326_DAC_VPPSCALE, 0x15); 1081 1082 regmap_write(es8326->regmap, ES8326_HPDET_TYPE, 0x80 | 1083 ((es8326->version >= ES8326_VERSION_B) ? 1084 (ES8326_HP_DET_SRC_PIN9 | es8326->jack_pol) : 1085 (ES8326_HP_DET_SRC_PIN9 | es8326->jack_pol | 0x04))); 1086 usleep_range(5000, 10000); 1087 es8326_enable_micbias(es8326->component); 1088 usleep_range(50000, 70000); 1089 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x00); 1090 regmap_write(es8326->regmap, ES8326_INTOUT_IO, 1091 es8326->interrupt_clk); 1092 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO, ES8326_IO_INPUT); 1093 regmap_write(es8326->regmap, ES8326_SDINOUT23_IO, ES8326_IO_INPUT); 1094 1095 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x00); 1096 regmap_write(es8326->regmap, ES8326_RESET, ES8326_CSM_ON); 1097 regmap_update_bits(es8326->regmap, ES8326_PGAGAIN, ES8326_MIC_SEL_MASK, 1098 ES8326_MIC1_SEL); 1099 1100 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE, ES8326_MUTE_MASK, 1101 ES8326_MUTE); 1102 1103 regmap_write(es8326->regmap, ES8326_ADC_MUTE, 0x0f); 1104 regmap_write(es8326->regmap, ES8326_CLK_DIV_LRCK, 0xff); 1105 regmap_write(es8326->regmap, ES8326_ADC1_SRC, 0x44); 1106 regmap_write(es8326->regmap, ES8326_ADC2_SRC, 0x66); 1107 es8326_disable_micbias(es8326->component); 1108 if (es8326->version > ES8326_VERSION_B) { 1109 regmap_update_bits(es8326->regmap, ES8326_ANA_MICBIAS, 0x73, 0x10); 1110 regmap_update_bits(es8326->regmap, ES8326_VMIDSEL, 0x40, 0x40); 1111 } 1112 1113 msleep(200); 1114 regmap_write(es8326->regmap, ES8326_INT_SOURCE, ES8326_INT_SRC_PIN9); 1115 } 1116 1117 static int es8326_resume(struct snd_soc_component *component) 1118 { 1119 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 1120 unsigned int reg; 1121 1122 regcache_cache_only(es8326->regmap, false); 1123 regcache_cache_bypass(es8326->regmap, true); 1124 regmap_read(es8326->regmap, ES8326_CLK_RESAMPLE, ®); 1125 regcache_cache_bypass(es8326->regmap, false); 1126 /* reset internal clock state */ 1127 if (reg == 0x05) 1128 regmap_write(es8326->regmap, ES8326_CLK_CTL, ES8326_CLK_ON); 1129 else 1130 es8326_init(component); 1131 1132 regcache_sync(es8326->regmap); 1133 1134 es8326_irq(es8326->irq, es8326); 1135 return 0; 1136 } 1137 1138 static int es8326_suspend(struct snd_soc_component *component) 1139 { 1140 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 1141 1142 cancel_delayed_work_sync(&es8326->jack_detect_work); 1143 es8326_disable_micbias(component); 1144 es8326->calibrated = false; 1145 regmap_write(es8326->regmap, ES8326_CLK_MUX, 0x2d); 1146 regmap_write(es8326->regmap, ES8326_DAC2HPMIX, 0x00); 1147 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x3b); 1148 regmap_write(es8326->regmap, ES8326_CLK_CTL, ES8326_CLK_OFF); 1149 regcache_cache_only(es8326->regmap, true); 1150 1151 /* reset register value to default */ 1152 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x01); 1153 usleep_range(1000, 3000); 1154 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x00); 1155 1156 regcache_mark_dirty(es8326->regmap); 1157 return 0; 1158 } 1159 1160 static int es8326_probe(struct snd_soc_component *component) 1161 { 1162 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 1163 int ret; 1164 1165 es8326->component = component; 1166 es8326->jd_inverted = device_property_read_bool(component->dev, 1167 "everest,jack-detect-inverted"); 1168 1169 ret = device_property_read_u8(component->dev, "everest,jack-pol", &es8326->jack_pol); 1170 if (ret != 0) { 1171 dev_dbg(component->dev, "jack-pol return %d", ret); 1172 es8326->jack_pol = ES8326_HP_TYPE_AUTO; 1173 } 1174 dev_dbg(component->dev, "jack-pol %x", es8326->jack_pol); 1175 1176 ret = device_property_read_u8(component->dev, "everest,interrupt-src", 1177 &es8326->interrupt_src); 1178 if (ret != 0) { 1179 dev_dbg(component->dev, "interrupt-src return %d", ret); 1180 es8326->interrupt_src = ES8326_HP_DET_SRC_PIN9; 1181 } 1182 dev_dbg(component->dev, "interrupt-src %x", es8326->interrupt_src); 1183 1184 ret = device_property_read_u8(component->dev, "everest,interrupt-clk", 1185 &es8326->interrupt_clk); 1186 if (ret != 0) { 1187 dev_dbg(component->dev, "interrupt-clk return %d", ret); 1188 es8326->interrupt_clk = 0x00; 1189 } 1190 dev_dbg(component->dev, "interrupt-clk %x", es8326->interrupt_clk); 1191 1192 es8326_init(component); 1193 return 0; 1194 } 1195 1196 static void es8326_enable_jack_detect(struct snd_soc_component *component, 1197 struct snd_soc_jack *jack) 1198 { 1199 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 1200 1201 scoped_guard(mutex, &es8326->lock) { 1202 if (es8326->jd_inverted) 1203 snd_soc_component_update_bits(component, ES8326_HPDET_TYPE, 1204 ES8326_HP_DET_JACK_POL, ~es8326->jack_pol); 1205 es8326->jack = jack; 1206 } 1207 es8326_irq(es8326->irq, es8326); 1208 } 1209 1210 static void es8326_disable_jack_detect(struct snd_soc_component *component) 1211 { 1212 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 1213 1214 dev_dbg(component->dev, "Enter into %s\n", __func__); 1215 if (!es8326->jack) 1216 return; /* Already disabled (or never enabled) */ 1217 cancel_delayed_work_sync(&es8326->jack_detect_work); 1218 1219 guard(mutex)(&es8326->lock); 1220 if (es8326->jack->status & SND_JACK_MICROPHONE) { 1221 es8326_disable_micbias(component); 1222 snd_soc_jack_report(es8326->jack, 0, SND_JACK_HEADSET); 1223 } 1224 es8326->jack = NULL; 1225 } 1226 1227 static int es8326_set_jack(struct snd_soc_component *component, 1228 struct snd_soc_jack *jack, void *data) 1229 { 1230 if (jack) 1231 es8326_enable_jack_detect(component, jack); 1232 else 1233 es8326_disable_jack_detect(component); 1234 1235 return 0; 1236 } 1237 1238 static void es8326_remove(struct snd_soc_component *component) 1239 { 1240 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 1241 1242 es8326_disable_jack_detect(component); 1243 es8326_set_bias_level(component, SND_SOC_BIAS_OFF); 1244 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x01); 1245 usleep_range(1000, 3000); 1246 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x00); 1247 } 1248 1249 static const struct snd_soc_component_driver soc_component_dev_es8326 = { 1250 .probe = es8326_probe, 1251 .remove = es8326_remove, 1252 .resume = es8326_resume, 1253 .suspend = es8326_suspend, 1254 .set_bias_level = es8326_set_bias_level, 1255 .set_jack = es8326_set_jack, 1256 .dapm_widgets = es8326_dapm_widgets, 1257 .num_dapm_widgets = ARRAY_SIZE(es8326_dapm_widgets), 1258 .dapm_routes = es8326_dapm_routes, 1259 .num_dapm_routes = ARRAY_SIZE(es8326_dapm_routes), 1260 .controls = es8326_snd_controls, 1261 .num_controls = ARRAY_SIZE(es8326_snd_controls), 1262 .use_pmdown_time = 1, 1263 .endianness = 1, 1264 }; 1265 1266 static int es8326_i2c_probe(struct i2c_client *i2c) 1267 { 1268 struct es8326_priv *es8326; 1269 int ret; 1270 1271 es8326 = devm_kzalloc(&i2c->dev, sizeof(struct es8326_priv), GFP_KERNEL); 1272 if (!es8326) 1273 return -ENOMEM; 1274 1275 i2c_set_clientdata(i2c, es8326); 1276 es8326->i2c = i2c; 1277 mutex_init(&es8326->lock); 1278 es8326->regmap = devm_regmap_init_i2c(i2c, &es8326_regmap_config); 1279 if (IS_ERR(es8326->regmap)) { 1280 ret = PTR_ERR(es8326->regmap); 1281 dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret); 1282 return ret; 1283 } 1284 1285 es8326->irq = i2c->irq; 1286 es8326->jack_remove_retry = 0; 1287 es8326->hp = 0; 1288 es8326->hpl_vol = 0x03; 1289 es8326->hpr_vol = 0x03; 1290 INIT_DELAYED_WORK(&es8326->jack_detect_work, 1291 es8326_jack_detect_handler); 1292 INIT_DELAYED_WORK(&es8326->button_press_work, 1293 es8326_jack_button_handler); 1294 /* ES8316 is level-based while ES8326 is edge-based */ 1295 ret = devm_request_threaded_irq(&i2c->dev, es8326->irq, NULL, es8326_irq, 1296 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1297 "es8326", es8326); 1298 if (ret) { 1299 dev_warn(&i2c->dev, "Failed to request IRQ: %d: %d\n", 1300 es8326->irq, ret); 1301 es8326->irq = -ENXIO; 1302 } 1303 1304 es8326->mclk = devm_clk_get_optional(&i2c->dev, "mclk"); 1305 if (IS_ERR(es8326->mclk)) { 1306 dev_err(&i2c->dev, "unable to get mclk\n"); 1307 return PTR_ERR(es8326->mclk); 1308 } 1309 if (!es8326->mclk) 1310 dev_warn(&i2c->dev, "assuming static mclk\n"); 1311 1312 ret = clk_prepare_enable(es8326->mclk); 1313 if (ret) { 1314 dev_err(&i2c->dev, "unable to enable mclk\n"); 1315 return ret; 1316 } 1317 return devm_snd_soc_register_component(&i2c->dev, 1318 &soc_component_dev_es8326, 1319 &es8326_dai, 1); 1320 } 1321 1322 1323 static void es8326_i2c_shutdown(struct i2c_client *i2c) 1324 { 1325 struct snd_soc_component *component; 1326 struct es8326_priv *es8326; 1327 1328 es8326 = i2c_get_clientdata(i2c); 1329 component = es8326->component; 1330 dev_dbg(component->dev, "Enter into %s\n", __func__); 1331 cancel_delayed_work_sync(&es8326->jack_detect_work); 1332 cancel_delayed_work_sync(&es8326->button_press_work); 1333 1334 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x01); 1335 usleep_range(1000, 3000); 1336 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x00); 1337 1338 } 1339 1340 static void es8326_i2c_remove(struct i2c_client *i2c) 1341 { 1342 es8326_i2c_shutdown(i2c); 1343 } 1344 1345 static const struct i2c_device_id es8326_i2c_id[] = { 1346 { .name = "es8326" }, 1347 { } 1348 }; 1349 MODULE_DEVICE_TABLE(i2c, es8326_i2c_id); 1350 1351 #ifdef CONFIG_OF 1352 static const struct of_device_id es8326_of_match[] = { 1353 { .compatible = "everest,es8326", }, 1354 {} 1355 }; 1356 MODULE_DEVICE_TABLE(of, es8326_of_match); 1357 #endif 1358 1359 #ifdef CONFIG_ACPI 1360 static const struct acpi_device_id es8326_acpi_match[] = { 1361 {"ESSX8326", 0}, 1362 {}, 1363 }; 1364 MODULE_DEVICE_TABLE(acpi, es8326_acpi_match); 1365 #endif 1366 1367 static struct i2c_driver es8326_i2c_driver = { 1368 .driver = { 1369 .name = "es8326", 1370 .acpi_match_table = ACPI_PTR(es8326_acpi_match), 1371 .of_match_table = of_match_ptr(es8326_of_match), 1372 }, 1373 .probe = es8326_i2c_probe, 1374 .shutdown = es8326_i2c_shutdown, 1375 .remove = es8326_i2c_remove, 1376 .id_table = es8326_i2c_id, 1377 }; 1378 module_i2c_driver(es8326_i2c_driver); 1379 1380 MODULE_DESCRIPTION("ASoC es8326 driver"); 1381 MODULE_AUTHOR("David Yang <yangxiaohua@everest-semi.com>"); 1382 MODULE_LICENSE("GPL"); 1383