1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor 4 * 5 * Multi-channel Audio Serial Port Driver 6 * 7 * Author: Nirmal Pandey <n-pandey@ti.com>, 8 * Suresh Rajashekara <suresh.r@ti.com> 9 * Steve Chen <schen@.mvista.com> 10 * 11 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> 12 * Copyright: (C) 2009 Texas Instruments, India 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/device.h> 18 #include <linux/slab.h> 19 #include <linux/delay.h> 20 #include <linux/io.h> 21 #include <linux/clk.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/of.h> 24 #include <linux/platform_data/davinci_asp.h> 25 #include <linux/math64.h> 26 #include <linux/bitmap.h> 27 #include <linux/gpio/driver.h> 28 #include <linux/property.h> 29 30 #include <sound/asoundef.h> 31 #include <sound/core.h> 32 #include <sound/pcm.h> 33 #include <sound/pcm_params.h> 34 #include <sound/initval.h> 35 #include <sound/soc.h> 36 #include <sound/dmaengine_pcm.h> 37 38 #include "edma-pcm.h" 39 #include "sdma-pcm.h" 40 #include "udma-pcm.h" 41 #include "davinci-mcasp.h" 42 43 #define MCASP_MAX_AFIFO_DEPTH 64 44 45 #ifdef CONFIG_PM 46 static u32 context_regs[] = { 47 DAVINCI_MCASP_TXFMCTL_REG, 48 DAVINCI_MCASP_RXFMCTL_REG, 49 DAVINCI_MCASP_TXFMT_REG, 50 DAVINCI_MCASP_RXFMT_REG, 51 DAVINCI_MCASP_ACLKXCTL_REG, 52 DAVINCI_MCASP_ACLKRCTL_REG, 53 DAVINCI_MCASP_AHCLKXCTL_REG, 54 DAVINCI_MCASP_AHCLKRCTL_REG, 55 DAVINCI_MCASP_PDIR_REG, 56 DAVINCI_MCASP_PFUNC_REG, 57 DAVINCI_MCASP_RXMASK_REG, 58 DAVINCI_MCASP_TXMASK_REG, 59 DAVINCI_MCASP_RXTDM_REG, 60 DAVINCI_MCASP_TXTDM_REG, 61 }; 62 63 struct davinci_mcasp_context { 64 u32 config_regs[ARRAY_SIZE(context_regs)]; 65 u32 afifo_regs[2]; /* for read/write fifo control registers */ 66 u32 *xrsr_regs; /* for serializer configuration */ 67 bool pm_state; 68 }; 69 #endif 70 71 struct davinci_mcasp_ruledata { 72 struct davinci_mcasp *mcasp; 73 int serializers; 74 int stream; 75 }; 76 77 struct davinci_mcasp { 78 struct snd_dmaengine_dai_dma_data dma_data[2]; 79 struct davinci_mcasp_pdata *pdata; 80 void __iomem *base; 81 u32 fifo_base; 82 struct device *dev; 83 struct snd_pcm_substream *substreams[2]; 84 unsigned int dai_fmt; 85 86 u32 iec958_status; 87 88 /* Audio can not be enabled due to missing parameter(s) */ 89 bool missing_audio_param; 90 91 /* McASP specific data */ 92 int tdm_slots_tx; 93 int tdm_slots_rx; 94 u32 tdm_mask[2]; 95 int slot_width_tx; 96 int slot_width_rx; 97 u8 op_mode; 98 u8 dismod; 99 u8 num_serializer; 100 u8 *serial_dir; 101 u8 version; 102 u8 bclk_div_tx; 103 u8 bclk_div_rx; 104 int streams; 105 u32 irq_request[2]; 106 107 unsigned int sysclk_freq_tx; 108 unsigned int sysclk_freq_rx; 109 bool bclk_master; 110 bool async_mode; 111 u32 auxclk_fs_ratio_tx; 112 u32 auxclk_fs_ratio_rx; 113 114 unsigned long pdir; /* Pin direction bitfield */ 115 116 /* McASP FIFO related */ 117 u8 txnumevt; 118 u8 rxnumevt; 119 120 bool dat_port; 121 122 /* Used for comstraint setting on the second stream */ 123 u32 channels; 124 int max_format_width; 125 u8 active_serializers[2]; 126 127 #ifdef CONFIG_GPIOLIB 128 struct gpio_chip gpio_chip; 129 #endif 130 131 #ifdef CONFIG_PM 132 struct davinci_mcasp_context context; 133 #endif 134 135 struct davinci_mcasp_ruledata ruledata[2]; 136 struct snd_pcm_hw_constraint_list chconstr[2]; 137 }; 138 139 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, 140 u32 val) 141 { 142 void __iomem *reg = mcasp->base + offset; 143 __raw_writel(__raw_readl(reg) | val, reg); 144 } 145 146 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, 147 u32 val) 148 { 149 void __iomem *reg = mcasp->base + offset; 150 __raw_writel((__raw_readl(reg) & ~(val)), reg); 151 } 152 153 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, 154 u32 val, u32 mask) 155 { 156 void __iomem *reg = mcasp->base + offset; 157 __raw_writel((__raw_readl(reg) & ~mask) | val, reg); 158 } 159 160 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, 161 u32 val) 162 { 163 __raw_writel(val, mcasp->base + offset); 164 } 165 166 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) 167 { 168 return (u32)__raw_readl(mcasp->base + offset); 169 } 170 171 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) 172 { 173 int i = 0; 174 175 mcasp_set_bits(mcasp, ctl_reg, val); 176 177 /* programming GBLCTL needs to read back from GBLCTL and verfiy */ 178 /* loop count is to avoid the lock-up */ 179 for (i = 0; i < 1000; i++) { 180 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) 181 break; 182 } 183 184 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) 185 printk(KERN_ERR "GBLCTL write error\n"); 186 } 187 188 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) 189 { 190 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); 191 192 return !(aclkxctl & TX_ASYNC); 193 } 194 195 static bool mcasp_is_frame_producer(struct davinci_mcasp *mcasp) 196 { 197 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); 198 199 return rxfmctl & AFSRE; 200 } 201 202 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable) 203 { 204 u32 bit = PIN_BIT_AMUTE; 205 206 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) { 207 if (enable) 208 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 209 else 210 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 211 } 212 } 213 214 static inline void mcasp_set_clk_pdir_stream(struct davinci_mcasp *mcasp, 215 int stream, bool enable) 216 { 217 u32 bit, bit_end; 218 219 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 220 bit = PIN_BIT_ACLKX; 221 bit_end = PIN_BIT_AFSX + 1; 222 } else { 223 bit = PIN_BIT_ACLKR; 224 bit_end = PIN_BIT_AFSR + 1; 225 } 226 227 for_each_set_bit_from(bit, &mcasp->pdir, bit_end) { 228 if (enable) 229 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 230 else 231 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 232 } 233 } 234 235 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable) 236 { 237 u32 bit; 238 239 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) { 240 if (enable) 241 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 242 else 243 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 244 } 245 } 246 247 static inline int mcasp_get_tdm_slots(struct davinci_mcasp *mcasp, int stream) 248 { 249 return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? 250 mcasp->tdm_slots_tx : mcasp->tdm_slots_rx; 251 } 252 253 static inline int mcasp_get_slot_width(struct davinci_mcasp *mcasp, int stream) 254 { 255 return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? 256 mcasp->slot_width_tx : mcasp->slot_width_rx; 257 } 258 259 static inline unsigned int mcasp_get_sysclk_freq(struct davinci_mcasp *mcasp, int stream) 260 { 261 return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? 262 mcasp->sysclk_freq_tx : mcasp->sysclk_freq_rx; 263 } 264 265 static inline unsigned int mcasp_get_bclk_div(struct davinci_mcasp *mcasp, int stream) 266 { 267 return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? 268 mcasp->bclk_div_tx : mcasp->bclk_div_rx; 269 } 270 271 static inline unsigned int mcasp_get_auxclk_fs_ratio(struct davinci_mcasp *mcasp, int stream) 272 { 273 return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? 274 mcasp->auxclk_fs_ratio_tx : mcasp->auxclk_fs_ratio_rx; 275 } 276 277 static void mcasp_start_rx(struct davinci_mcasp *mcasp) 278 { 279 if (mcasp->rxnumevt) { /* enable FIFO */ 280 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 281 282 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 283 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 284 } 285 286 /* Start clocks */ 287 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); 288 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); 289 /* 290 * When ASYNC == 0 the transmit and receive sections operate 291 * synchronously from the transmit clock and frame sync. We need to make 292 * sure that the TX signals are enabled when starting reception, 293 * when the McASP is the producer. 294 */ 295 if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp)) { 296 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 297 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 298 } 299 if (mcasp_is_synchronous(mcasp)) 300 mcasp_set_clk_pdir(mcasp, true); 301 else 302 mcasp_set_clk_pdir_stream(mcasp, SNDRV_PCM_STREAM_CAPTURE, true); 303 304 /* Activate serializer(s) */ 305 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 306 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); 307 /* Release RX state machine */ 308 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); 309 /* Release Frame Sync generator */ 310 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); 311 if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp)) 312 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 313 314 /* enable receive IRQs */ 315 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 316 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 317 } 318 319 static void mcasp_start_tx(struct davinci_mcasp *mcasp) 320 { 321 u32 cnt; 322 323 if (mcasp->txnumevt) { /* enable FIFO */ 324 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 325 326 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 327 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 328 } 329 330 /* Start clocks */ 331 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 332 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 333 if (mcasp_is_synchronous(mcasp)) 334 mcasp_set_clk_pdir(mcasp, true); 335 else 336 mcasp_set_clk_pdir_stream(mcasp, SNDRV_PCM_STREAM_PLAYBACK, true); 337 338 /* Activate serializer(s) */ 339 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 340 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); 341 342 /* wait for XDATA to be cleared */ 343 cnt = 0; 344 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) && 345 (cnt < 100000)) 346 cnt++; 347 348 mcasp_set_axr_pdir(mcasp, true); 349 350 /* Release TX state machine */ 351 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); 352 /* Release Frame Sync generator */ 353 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 354 355 /* enable transmit IRQs */ 356 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 357 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 358 } 359 360 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) 361 { 362 mcasp->streams++; 363 364 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 365 mcasp_start_tx(mcasp); 366 else 367 mcasp_start_rx(mcasp); 368 } 369 370 static void mcasp_stop_rx(struct davinci_mcasp *mcasp) 371 { 372 /* disable IRQ sources */ 373 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 374 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 375 376 /* 377 * In synchronous mode stop the TX clocks if no other stream is 378 * running 379 * Otherwise in async mode only stop RX clocks 380 */ 381 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) 382 mcasp_set_clk_pdir(mcasp, false); 383 else if (!mcasp_is_synchronous(mcasp)) 384 mcasp_set_clk_pdir_stream(mcasp, SNDRV_PCM_STREAM_CAPTURE, false); 385 /* 386 * When McASP is the producer and operating in synchronous mode, 387 * stop the transmit clocks if no other stream is running. As 388 * tx & rx operate synchronously from the transmit clock. 389 */ 390 if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) && !mcasp->streams) 391 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); 392 393 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); 394 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 395 396 if (mcasp->rxnumevt) { /* disable FIFO */ 397 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 398 399 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 400 } 401 } 402 403 static void mcasp_stop_tx(struct davinci_mcasp *mcasp) 404 { 405 u32 val = 0; 406 407 /* disable IRQ sources */ 408 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 409 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 410 411 /* 412 * In synchronous mode keep TX clocks running if the capture stream is 413 * still running. 414 * Otherwise in async mode only stop TX clocks 415 */ 416 if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) && mcasp->streams) 417 val = TXHCLKRST | TXCLKRST | TXFSRST; 418 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) 419 mcasp_set_clk_pdir(mcasp, false); 420 else if (!mcasp_is_synchronous(mcasp)) 421 mcasp_set_clk_pdir_stream(mcasp, SNDRV_PCM_STREAM_PLAYBACK, false); 422 423 424 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); 425 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 426 427 if (mcasp->txnumevt) { /* disable FIFO */ 428 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 429 430 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 431 } 432 433 mcasp_set_axr_pdir(mcasp, false); 434 } 435 436 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) 437 { 438 mcasp->streams--; 439 440 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 441 mcasp_stop_tx(mcasp); 442 else 443 mcasp_stop_rx(mcasp); 444 } 445 446 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data) 447 { 448 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 449 struct snd_pcm_substream *substream; 450 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; 451 u32 handled_mask = 0; 452 u32 stat; 453 454 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); 455 if (stat & XUNDRN & irq_mask) { 456 dev_warn(mcasp->dev, "Transmit buffer underflow\n"); 457 handled_mask |= XUNDRN; 458 459 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; 460 if (substream) 461 snd_pcm_stop_xrun(substream); 462 } 463 464 if (!handled_mask) 465 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", 466 stat); 467 468 if (stat & XRERR) 469 handled_mask |= XRERR; 470 471 /* Ack the handled event only */ 472 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); 473 474 return IRQ_RETVAL(handled_mask); 475 } 476 477 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data) 478 { 479 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 480 struct snd_pcm_substream *substream; 481 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; 482 u32 handled_mask = 0; 483 u32 stat; 484 485 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); 486 if (stat & ROVRN & irq_mask) { 487 dev_warn(mcasp->dev, "Receive buffer overflow\n"); 488 handled_mask |= ROVRN; 489 490 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; 491 if (substream) 492 snd_pcm_stop_xrun(substream); 493 } 494 495 if (!handled_mask) 496 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", 497 stat); 498 499 if (stat & XRERR) 500 handled_mask |= XRERR; 501 502 /* Ack the handled event only */ 503 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); 504 505 return IRQ_RETVAL(handled_mask); 506 } 507 508 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data) 509 { 510 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 511 irqreturn_t ret = IRQ_NONE; 512 513 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) 514 ret = davinci_mcasp_tx_irq_handler(irq, data); 515 516 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) 517 ret |= davinci_mcasp_rx_irq_handler(irq, data); 518 519 return ret; 520 } 521 522 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 523 unsigned int fmt) 524 { 525 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 526 int ret = 0; 527 u32 data_delay; 528 bool fs_pol_rising; 529 bool inv_fs = false; 530 531 if (!fmt) 532 return 0; 533 534 pm_runtime_get_sync(mcasp->dev); 535 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 536 case SND_SOC_DAIFMT_DSP_A: 537 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 538 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 539 /* 1st data bit occur one ACLK cycle after the frame sync */ 540 data_delay = 1; 541 break; 542 case SND_SOC_DAIFMT_DSP_B: 543 case SND_SOC_DAIFMT_AC97: 544 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 545 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 546 /* No delay after FS */ 547 data_delay = 0; 548 break; 549 case SND_SOC_DAIFMT_I2S: 550 /* configure a full-word SYNC pulse (LRCLK) */ 551 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 552 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 553 /* 1st data bit occur one ACLK cycle after the frame sync */ 554 data_delay = 1; 555 /* FS need to be inverted */ 556 inv_fs = true; 557 break; 558 case SND_SOC_DAIFMT_RIGHT_J: 559 case SND_SOC_DAIFMT_LEFT_J: 560 /* configure a full-word SYNC pulse (LRCLK) */ 561 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 562 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 563 /* No delay after FS */ 564 data_delay = 0; 565 break; 566 default: 567 ret = -EINVAL; 568 goto out; 569 } 570 571 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), 572 FSXDLY(3)); 573 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), 574 FSRDLY(3)); 575 576 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 577 case SND_SOC_DAIFMT_BP_FP: 578 /* codec is clock and frame slave */ 579 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 580 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 581 582 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 583 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 584 585 /* BCLK */ 586 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 587 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 588 /* Frame Sync */ 589 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 590 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 591 592 mcasp->bclk_master = 1; 593 break; 594 case SND_SOC_DAIFMT_BP_FC: 595 /* codec is clock slave and frame master */ 596 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 597 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 598 599 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 600 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 601 602 /* BCLK */ 603 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 604 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 605 /* Frame Sync */ 606 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 607 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 608 609 mcasp->bclk_master = 1; 610 break; 611 case SND_SOC_DAIFMT_BC_FP: 612 /* codec is clock master and frame slave */ 613 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 614 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 615 616 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 617 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 618 619 /* BCLK */ 620 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 621 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 622 /* Frame Sync */ 623 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 624 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 625 626 mcasp->bclk_master = 0; 627 break; 628 case SND_SOC_DAIFMT_BC_FC: 629 /* codec is clock and frame master */ 630 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 631 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 632 633 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 634 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 635 636 /* BCLK */ 637 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 638 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 639 /* Frame Sync */ 640 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 641 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 642 643 mcasp->bclk_master = 0; 644 break; 645 default: 646 ret = -EINVAL; 647 goto out; 648 } 649 650 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 651 case SND_SOC_DAIFMT_IB_NF: 652 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 653 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 654 fs_pol_rising = true; 655 break; 656 case SND_SOC_DAIFMT_NB_IF: 657 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 658 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 659 fs_pol_rising = false; 660 break; 661 case SND_SOC_DAIFMT_IB_IF: 662 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 663 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 664 fs_pol_rising = false; 665 break; 666 case SND_SOC_DAIFMT_NB_NF: 667 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 668 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 669 fs_pol_rising = true; 670 break; 671 default: 672 ret = -EINVAL; 673 goto out; 674 } 675 676 if (inv_fs) 677 fs_pol_rising = !fs_pol_rising; 678 679 if (fs_pol_rising) { 680 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 681 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 682 } else { 683 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 684 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 685 } 686 687 mcasp->dai_fmt = fmt; 688 out: 689 pm_runtime_put(mcasp->dev); 690 return ret; 691 } 692 693 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id, 694 int div, bool explicit) 695 { 696 pm_runtime_get_sync(mcasp->dev); 697 switch (div_id) { 698 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */ 699 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 700 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); 701 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 702 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); 703 break; 704 705 case MCASP_CLKDIV_AUXCLK_TXONLY: /* MCLK divider for TX only */ 706 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 707 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); 708 break; 709 710 case MCASP_CLKDIV_AUXCLK_RXONLY: /* MCLK divider for RX only */ 711 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 712 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); 713 break; 714 715 case MCASP_CLKDIV_BCLK: /* BCLK divider */ 716 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, 717 ACLKXDIV(div - 1), ACLKXDIV_MASK); 718 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, 719 ACLKRDIV(div - 1), ACLKRDIV_MASK); 720 if (explicit) { 721 mcasp->bclk_div_tx = div; 722 mcasp->bclk_div_rx = div; 723 } 724 break; 725 726 case MCASP_CLKDIV_BCLK_TXONLY: /* BCLK divider for TX only */ 727 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, 728 ACLKXDIV(div - 1), ACLKXDIV_MASK); 729 if (explicit) 730 mcasp->bclk_div_tx = div; 731 break; 732 733 case MCASP_CLKDIV_BCLK_RXONLY: /* BCLK divider for RX only */ 734 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, 735 ACLKRDIV(div - 1), ACLKRDIV_MASK); 736 if (explicit) 737 mcasp->bclk_div_rx = div; 738 break; 739 740 case MCASP_CLKDIV_BCLK_FS_RATIO: 741 /* 742 * BCLK/LRCLK ratio descries how many bit-clock cycles 743 * fit into one frame. The clock ratio is given for a 744 * full period of data (for I2S format both left and 745 * right channels), so it has to be divided by number 746 * of tdm-slots (for I2S - divided by 2). 747 * Instead of storing this ratio, we calculate a new 748 * tdm_slot width by dividing the ratio by the 749 * number of configured tdm slots. 750 */ 751 mcasp->slot_width_tx = div / mcasp->tdm_slots_tx; 752 if (div % mcasp->tdm_slots_tx) 753 dev_warn(mcasp->dev, 754 "%s(): BCLK/LRCLK %d is not divisible by %d tx tdm slots", 755 __func__, div, mcasp->tdm_slots_tx); 756 757 mcasp->slot_width_rx = div / mcasp->tdm_slots_rx; 758 if (div % mcasp->tdm_slots_rx) 759 dev_warn(mcasp->dev, 760 "%s(): BCLK/LRCLK %d is not divisible by %d rx tdm slots", 761 __func__, div, mcasp->tdm_slots_rx); 762 break; 763 764 case MCASP_CLKDIV_BCLK_FS_RATIO_TXONLY: 765 mcasp->slot_width_tx = div / mcasp->tdm_slots_tx; 766 if (div % mcasp->tdm_slots_tx) 767 dev_warn(mcasp->dev, 768 "%s(): BCLK/LRCLK %d is not divisible by %d tx tdm slots", 769 __func__, div, mcasp->tdm_slots_tx); 770 break; 771 772 case MCASP_CLKDIV_BCLK_FS_RATIO_RXONLY: 773 mcasp->slot_width_rx = div / mcasp->tdm_slots_rx; 774 if (div % mcasp->tdm_slots_rx) 775 dev_warn(mcasp->dev, 776 "%s(): BCLK/LRCLK %d is not divisible by %d rx tdm slots", 777 __func__, div, mcasp->tdm_slots_rx); 778 break; 779 780 default: 781 return -EINVAL; 782 } 783 784 pm_runtime_put(mcasp->dev); 785 return 0; 786 } 787 788 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, 789 int div) 790 { 791 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 792 793 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1); 794 } 795 796 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, 797 unsigned int freq, int dir) 798 { 799 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 800 801 pm_runtime_get_sync(mcasp->dev); 802 803 if (dir == SND_SOC_CLOCK_IN) { 804 switch (clk_id) { 805 case MCASP_CLK_HCLK_AHCLK: 806 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 807 AHCLKXE); 808 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 809 AHCLKRE); 810 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 811 mcasp->sysclk_freq_tx = freq; 812 mcasp->sysclk_freq_rx = freq; 813 break; 814 case MCASP_CLK_HCLK_AHCLK_TXONLY: 815 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 816 AHCLKXE); 817 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 818 mcasp->sysclk_freq_tx = freq; 819 break; 820 case MCASP_CLK_HCLK_AHCLK_RXONLY: 821 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 822 AHCLKRE); 823 clear_bit(PIN_BIT_AHCLKR, &mcasp->pdir); 824 mcasp->sysclk_freq_rx = freq; 825 break; 826 case MCASP_CLK_HCLK_AUXCLK: 827 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 828 AHCLKXE); 829 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 830 AHCLKRE); 831 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 832 mcasp->sysclk_freq_tx = freq; 833 mcasp->sysclk_freq_rx = freq; 834 break; 835 case MCASP_CLK_HCLK_AUXCLK_TXONLY: 836 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 837 AHCLKXE); 838 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 839 mcasp->sysclk_freq_tx = freq; 840 break; 841 case MCASP_CLK_HCLK_AUXCLK_RXONLY: 842 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 843 AHCLKRE); 844 set_bit(PIN_BIT_AHCLKR, &mcasp->pdir); 845 mcasp->sysclk_freq_rx = freq; 846 break; 847 default: 848 dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id); 849 goto out; 850 } 851 } else { 852 /* McASP is clock master, select AUXCLK as HCLK */ 853 switch (clk_id) { 854 case MCASP_CLK_HCLK_AUXCLK_TXONLY: 855 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 856 AHCLKXE); 857 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 858 mcasp->sysclk_freq_tx = freq; 859 break; 860 case MCASP_CLK_HCLK_AUXCLK_RXONLY: 861 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 862 AHCLKRE); 863 set_bit(PIN_BIT_AHCLKR, &mcasp->pdir); 864 mcasp->sysclk_freq_rx = freq; 865 break; 866 default: 867 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 868 AHCLKXE); 869 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 870 AHCLKRE); 871 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 872 set_bit(PIN_BIT_AHCLKR, &mcasp->pdir); 873 mcasp->sysclk_freq_tx = freq; 874 mcasp->sysclk_freq_rx = freq; 875 break; 876 } 877 } 878 /* 879 * When AHCLK X/R is selected to be output it means that the HCLK is 880 * the same clock - coming via AUXCLK. 881 */ 882 out: 883 pm_runtime_put(mcasp->dev); 884 return 0; 885 } 886 887 /* All serializers must have equal number of channels */ 888 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream, 889 int serializers) 890 { 891 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream]; 892 unsigned int *list = (unsigned int *) cl->list; 893 int slots; 894 int i, count = 0; 895 896 slots = mcasp_get_tdm_slots(mcasp, stream); 897 898 if (mcasp->tdm_mask[stream]) 899 slots = hweight32(mcasp->tdm_mask[stream]); 900 901 for (i = 1; i <= slots; i++) 902 list[count++] = i; 903 904 for (i = 2; i <= serializers; i++) 905 list[count++] = i*slots; 906 907 cl->count = count; 908 909 return 0; 910 } 911 912 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp) 913 { 914 int rx_serializers = 0, tx_serializers = 0, ret, i; 915 916 for (i = 0; i < mcasp->num_serializer; i++) 917 if (mcasp->serial_dir[i] == TX_MODE) 918 tx_serializers++; 919 else if (mcasp->serial_dir[i] == RX_MODE) 920 rx_serializers++; 921 922 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK, 923 tx_serializers); 924 if (ret) 925 return ret; 926 927 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE, 928 rx_serializers); 929 930 return ret; 931 } 932 933 934 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai, 935 unsigned int tx_mask, 936 unsigned int rx_mask, 937 int slots, int slot_width) 938 { 939 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 940 941 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 942 return 0; 943 944 dev_dbg(mcasp->dev, 945 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n", 946 __func__, tx_mask, rx_mask, slots, slot_width); 947 948 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { 949 dev_err(mcasp->dev, 950 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", 951 tx_mask, rx_mask, slots); 952 return -EINVAL; 953 } 954 955 if (slot_width && 956 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) { 957 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n", 958 __func__, slot_width); 959 return -EINVAL; 960 } 961 962 if (mcasp->async_mode) { 963 if (tx_mask) { 964 mcasp->tdm_slots_tx = slots; 965 mcasp->slot_width_tx = slot_width; 966 } 967 if (rx_mask) { 968 mcasp->tdm_slots_rx = slots; 969 mcasp->slot_width_rx = slot_width; 970 } 971 } else { 972 mcasp->tdm_slots_tx = slots; 973 mcasp->tdm_slots_rx = slots; 974 mcasp->slot_width_tx = slot_width; 975 mcasp->slot_width_rx = slot_width; 976 } 977 978 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; 979 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; 980 981 return davinci_mcasp_set_ch_constraints(mcasp); 982 } 983 984 static int davinci_config_channel_size(struct davinci_mcasp *mcasp, 985 int sample_width, int stream) 986 { 987 u32 fmt; 988 u32 tx_rotate, rx_rotate, slot_width; 989 u32 mask = (1ULL << sample_width) - 1; 990 991 slot_width = mcasp_get_slot_width(mcasp, stream); 992 if (!slot_width) { 993 if (mcasp->max_format_width) 994 slot_width = mcasp->max_format_width; 995 else 996 slot_width = sample_width; 997 } 998 /* 999 * TX rotation: 1000 * right aligned formats: rotate w/ slot_width 1001 * left aligned formats: rotate w/ sample_width 1002 * 1003 * RX rotation: 1004 * right aligned formats: no rotation needed 1005 * left aligned formats: rotate w/ (slot_width - sample_width) 1006 */ 1007 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == 1008 SND_SOC_DAIFMT_RIGHT_J) { 1009 tx_rotate = (slot_width / 4) & 0x7; 1010 rx_rotate = 0; 1011 } else { 1012 tx_rotate = (sample_width / 4) & 0x7; 1013 rx_rotate = (slot_width - sample_width) / 4; 1014 } 1015 1016 /* mapping of the XSSZ bit-field as described in the datasheet */ 1017 fmt = (slot_width >> 1) - 1; 1018 1019 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 1020 if (!mcasp->async_mode || stream == SNDRV_PCM_STREAM_PLAYBACK) { 1021 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), 1022 TXSSZ(0x0F)); 1023 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), 1024 TXROT(7)); 1025 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); 1026 } 1027 if (!mcasp->async_mode || stream == SNDRV_PCM_STREAM_CAPTURE) { 1028 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), 1029 RXSSZ(0x0F)); 1030 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), 1031 RXROT(7)); 1032 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); 1033 } 1034 } else { 1035 /* 1036 * DIT mode only use TX serializers 1037 * according to the TRM it should be TXROT=0, this one works: 1038 * 16 bit to 23-8 (TXROT=6, rotate 24 bits) 1039 * 24 bit to 23-0 (TXROT=0, rotate 0 bits) 1040 * 1041 * TXROT = 0 only works with 24bit samples 1042 */ 1043 tx_rotate = (sample_width / 4 + 2) & 0x7; 1044 1045 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), 1046 TXROT(7)); 1047 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(15), 1048 TXSSZ(0x0F)); 1049 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); 1050 } 1051 1052 return 0; 1053 } 1054 1055 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, 1056 int period_words, int channels) 1057 { 1058 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; 1059 int i; 1060 u8 tx_ser = 0; 1061 u8 rx_ser = 0; 1062 int slots; 1063 u8 max_active_serializers, max_rx_serializers, max_tx_serializers; 1064 int active_serializers, numevt; 1065 u32 reg; 1066 1067 slots = mcasp_get_tdm_slots(mcasp, stream); 1068 1069 /* In DIT mode we only allow maximum of one serializers for now */ 1070 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1071 max_active_serializers = 1; 1072 else 1073 max_active_serializers = DIV_ROUND_UP(channels, slots); 1074 1075 /* Default configuration */ 1076 if (mcasp->version < MCASP_VERSION_3) 1077 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); 1078 1079 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1080 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 1081 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 1082 max_tx_serializers = max_active_serializers; 1083 max_rx_serializers = 1084 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE]; 1085 } else { 1086 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 1087 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); 1088 max_tx_serializers = 1089 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK]; 1090 max_rx_serializers = max_active_serializers; 1091 } 1092 1093 for (i = 0; i < mcasp->num_serializer; i++) { 1094 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 1095 mcasp->serial_dir[i]); 1096 if (mcasp->serial_dir[i] == TX_MODE && 1097 tx_ser < max_tx_serializers) { 1098 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 1099 mcasp->dismod, DISMOD_MASK); 1100 set_bit(PIN_BIT_AXR(i), &mcasp->pdir); 1101 tx_ser++; 1102 } else if (mcasp->serial_dir[i] == RX_MODE && 1103 rx_ser < max_rx_serializers) { 1104 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 1105 rx_ser++; 1106 } else { 1107 /* Inactive or unused pin, set it to inactive */ 1108 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 1109 SRMOD_INACTIVE, SRMOD_MASK); 1110 /* If unused, set DISMOD for the pin */ 1111 if (mcasp->serial_dir[i] != INACTIVE_MODE) 1112 mcasp_mod_bits(mcasp, 1113 DAVINCI_MCASP_XRSRCTL_REG(i), 1114 mcasp->dismod, DISMOD_MASK); 1115 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 1116 } 1117 } 1118 1119 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1120 active_serializers = tx_ser; 1121 numevt = mcasp->txnumevt; 1122 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 1123 } else { 1124 active_serializers = rx_ser; 1125 numevt = mcasp->rxnumevt; 1126 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 1127 } 1128 1129 if (active_serializers < max_active_serializers) { 1130 dev_warn(mcasp->dev, "stream has more channels (%d) than are " 1131 "enabled in mcasp (%d)\n", channels, 1132 active_serializers * slots); 1133 return -EINVAL; 1134 } 1135 1136 /* AFIFO is not in use */ 1137 if (!numevt) { 1138 /* Configure the burst size for platform drivers */ 1139 if (active_serializers > 1) { 1140 /* 1141 * If more than one serializers are in use we have one 1142 * DMA request to provide data for all serializers. 1143 * For example if three serializers are enabled the DMA 1144 * need to transfer three words per DMA request. 1145 */ 1146 dma_data->maxburst = active_serializers; 1147 } else { 1148 dma_data->maxburst = 0; 1149 } 1150 1151 goto out; 1152 } 1153 1154 if (period_words % active_serializers) { 1155 dev_err(mcasp->dev, "Invalid combination of period words and " 1156 "active serializers: %d, %d\n", period_words, 1157 active_serializers); 1158 return -EINVAL; 1159 } 1160 1161 /* 1162 * Calculate the optimal AFIFO depth for platform side: 1163 * The number of words for numevt need to be in steps of active 1164 * serializers. 1165 */ 1166 numevt = (numevt / active_serializers) * active_serializers; 1167 1168 while (period_words % numevt && numevt > 0) 1169 numevt -= active_serializers; 1170 if (numevt <= 0) 1171 numevt = active_serializers; 1172 1173 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); 1174 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); 1175 1176 /* Configure the burst size for platform drivers */ 1177 if (numevt == 1) 1178 numevt = 0; 1179 dma_data->maxburst = numevt; 1180 1181 out: 1182 mcasp->active_serializers[stream] = active_serializers; 1183 1184 return 0; 1185 } 1186 1187 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, 1188 int channels) 1189 { 1190 int i, active_slots; 1191 int total_slots; 1192 int active_serializers; 1193 u32 mask = 0; 1194 u32 busel = 0; 1195 1196 total_slots = mcasp_get_tdm_slots(mcasp, stream); 1197 1198 /* 1199 * If more than one serializer is needed, then use them with 1200 * all the specified tdm_slots. Otherwise, one serializer can 1201 * cope with the transaction using just as many slots as there 1202 * are channels in the stream. 1203 */ 1204 if (mcasp->tdm_mask[stream]) { 1205 active_slots = hweight32(mcasp->tdm_mask[stream]); 1206 active_serializers = DIV_ROUND_UP(channels, active_slots); 1207 if (active_serializers == 1) 1208 active_slots = channels; 1209 for (i = 0; i < total_slots; i++) { 1210 if ((1 << i) & mcasp->tdm_mask[stream]) { 1211 mask |= (1 << i); 1212 if (--active_slots <= 0) 1213 break; 1214 } 1215 } 1216 } else { 1217 active_serializers = DIV_ROUND_UP(channels, total_slots); 1218 if (active_serializers == 1) 1219 active_slots = channels; 1220 else 1221 active_slots = total_slots; 1222 1223 for (i = 0; i < active_slots; i++) 1224 mask |= (1 << i); 1225 } 1226 1227 if (mcasp->async_mode) 1228 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); 1229 else 1230 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); 1231 1232 if (!mcasp->dat_port) 1233 busel = TXSEL; 1234 1235 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1236 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); 1237 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); 1238 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 1239 FSXMOD(total_slots), FSXMOD(0x1FF)); 1240 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) { 1241 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); 1242 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); 1243 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, 1244 FSRMOD(total_slots), FSRMOD(0x1FF)); 1245 /* 1246 * If McASP is set to be TX/RX synchronous and the playback is 1247 * not running already we need to configure the TX slots in 1248 * order to have correct FSX on the bus 1249 */ 1250 if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) && 1251 !mcasp->channels) 1252 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 1253 FSXMOD(total_slots), FSXMOD(0x1FF)); 1254 } 1255 1256 return 0; 1257 } 1258 1259 /* S/PDIF */ 1260 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, 1261 unsigned int rate) 1262 { 1263 u8 *cs_bytes = (u8 *)&mcasp->iec958_status; 1264 1265 if (!mcasp->dat_port) 1266 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL); 1267 else 1268 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL); 1269 1270 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ 1271 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); 1272 1273 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, 0xFFFF); 1274 1275 /* Set the TX tdm : for all the slots */ 1276 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); 1277 1278 /* Set the TX clock controls : div = 1 and internal */ 1279 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); 1280 1281 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 1282 1283 /* Set S/PDIF channel status bits */ 1284 cs_bytes[3] &= ~IEC958_AES3_CON_FS; 1285 switch (rate) { 1286 case 22050: 1287 cs_bytes[3] |= IEC958_AES3_CON_FS_22050; 1288 break; 1289 case 24000: 1290 cs_bytes[3] |= IEC958_AES3_CON_FS_24000; 1291 break; 1292 case 32000: 1293 cs_bytes[3] |= IEC958_AES3_CON_FS_32000; 1294 break; 1295 case 44100: 1296 cs_bytes[3] |= IEC958_AES3_CON_FS_44100; 1297 break; 1298 case 48000: 1299 cs_bytes[3] |= IEC958_AES3_CON_FS_48000; 1300 break; 1301 case 88200: 1302 cs_bytes[3] |= IEC958_AES3_CON_FS_88200; 1303 break; 1304 case 96000: 1305 cs_bytes[3] |= IEC958_AES3_CON_FS_96000; 1306 break; 1307 case 176400: 1308 cs_bytes[3] |= IEC958_AES3_CON_FS_176400; 1309 break; 1310 case 192000: 1311 cs_bytes[3] |= IEC958_AES3_CON_FS_192000; 1312 break; 1313 default: 1314 dev_err(mcasp->dev, "unsupported sampling rate: %d\n", rate); 1315 return -EINVAL; 1316 } 1317 1318 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, mcasp->iec958_status); 1319 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, mcasp->iec958_status); 1320 1321 /* Enable the DIT */ 1322 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); 1323 1324 return 0; 1325 } 1326 1327 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, 1328 unsigned int sysclk_freq, 1329 unsigned int bclk_freq, 1330 int stream, 1331 bool set) 1332 { 1333 int div = sysclk_freq / bclk_freq; 1334 int rem = sysclk_freq % bclk_freq; 1335 int error_ppm; 1336 int aux_div = 1; 1337 int bclk_div_id, auxclk_div_id; 1338 bool auxclk_enabled; 1339 1340 if (mcasp->async_mode && stream == SNDRV_PCM_STREAM_CAPTURE) { 1341 auxclk_enabled = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG) & AHCLKRE; 1342 bclk_div_id = MCASP_CLKDIV_BCLK_RXONLY; 1343 auxclk_div_id = MCASP_CLKDIV_AUXCLK_RXONLY; 1344 } else if (mcasp->async_mode && stream == SNDRV_PCM_STREAM_PLAYBACK) { 1345 auxclk_enabled = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG) & AHCLKXE; 1346 bclk_div_id = MCASP_CLKDIV_BCLK_TXONLY; 1347 auxclk_div_id = MCASP_CLKDIV_AUXCLK_TXONLY; 1348 } else { 1349 auxclk_enabled = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG) & AHCLKXE; 1350 bclk_div_id = MCASP_CLKDIV_BCLK; 1351 auxclk_div_id = MCASP_CLKDIV_AUXCLK; 1352 } 1353 1354 if (div > (ACLKXDIV_MASK + 1)) { 1355 if (auxclk_enabled) { 1356 aux_div = div / (ACLKXDIV_MASK + 1); 1357 if (div % (ACLKXDIV_MASK + 1)) 1358 aux_div++; 1359 1360 sysclk_freq /= aux_div; 1361 div = sysclk_freq / bclk_freq; 1362 rem = sysclk_freq % bclk_freq; 1363 } else if (set) { 1364 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n", 1365 sysclk_freq); 1366 } 1367 } 1368 1369 if (rem != 0) { 1370 if (div == 0 || 1371 ((sysclk_freq / div) - bclk_freq) > 1372 (bclk_freq - (sysclk_freq / (div+1)))) { 1373 div++; 1374 rem = rem - bclk_freq; 1375 } 1376 } 1377 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem, 1378 (int)bclk_freq)) / div - 1000000; 1379 1380 if (set) { 1381 if (error_ppm) 1382 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", 1383 error_ppm); 1384 1385 __davinci_mcasp_set_clkdiv(mcasp, bclk_div_id, div, false); 1386 if (auxclk_enabled) 1387 __davinci_mcasp_set_clkdiv(mcasp, auxclk_div_id, 1388 aux_div, false); 1389 } 1390 1391 return error_ppm; 1392 } 1393 1394 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp) 1395 { 1396 if (!mcasp->txnumevt) 1397 return 0; 1398 1399 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET); 1400 } 1401 1402 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp) 1403 { 1404 if (!mcasp->rxnumevt) 1405 return 0; 1406 1407 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET); 1408 } 1409 1410 static snd_pcm_sframes_t davinci_mcasp_delay( 1411 struct snd_pcm_substream *substream, 1412 struct snd_soc_dai *cpu_dai) 1413 { 1414 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1415 u32 fifo_use; 1416 1417 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1418 fifo_use = davinci_mcasp_tx_delay(mcasp); 1419 else 1420 fifo_use = davinci_mcasp_rx_delay(mcasp); 1421 1422 /* 1423 * Divide the used locations with the channel count to get the 1424 * FIFO usage in samples (don't care about partial samples in the 1425 * buffer). 1426 */ 1427 return fifo_use / substream->runtime->channels; 1428 } 1429 1430 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, 1431 struct snd_pcm_hw_params *params, 1432 struct snd_soc_dai *cpu_dai) 1433 { 1434 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1435 int word_length; 1436 int channels = params_channels(params); 1437 int period_size = params_period_size(params); 1438 int ret; 1439 unsigned int sysclk_freq = mcasp_get_sysclk_freq(mcasp, substream->stream); 1440 1441 switch (params_format(params)) { 1442 case SNDRV_PCM_FORMAT_U8: 1443 case SNDRV_PCM_FORMAT_S8: 1444 word_length = 8; 1445 break; 1446 1447 case SNDRV_PCM_FORMAT_U16_LE: 1448 case SNDRV_PCM_FORMAT_S16_LE: 1449 word_length = 16; 1450 break; 1451 1452 case SNDRV_PCM_FORMAT_U24_3LE: 1453 case SNDRV_PCM_FORMAT_S24_3LE: 1454 word_length = 24; 1455 break; 1456 1457 case SNDRV_PCM_FORMAT_U24_LE: 1458 case SNDRV_PCM_FORMAT_S24_LE: 1459 word_length = 24; 1460 break; 1461 1462 case SNDRV_PCM_FORMAT_U32_LE: 1463 case SNDRV_PCM_FORMAT_S32_LE: 1464 word_length = 32; 1465 break; 1466 1467 default: 1468 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); 1469 return -EINVAL; 1470 } 1471 1472 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt); 1473 if (ret) 1474 return ret; 1475 1476 /* 1477 * If mcasp is BCLK master, and a BCLK divider was not provided by 1478 * the machine driver, we need to calculate the ratio. 1479 */ 1480 if (mcasp->bclk_master && mcasp_get_bclk_div(mcasp, substream->stream) == 0 && 1481 sysclk_freq) { 1482 int slots, slot_width; 1483 int rate = params_rate(params); 1484 int sbits = params_width(params); 1485 unsigned int bclk_target; 1486 1487 slots = mcasp_get_tdm_slots(mcasp, substream->stream); 1488 1489 slot_width = mcasp_get_slot_width(mcasp, substream->stream); 1490 if (slot_width) 1491 sbits = slot_width; 1492 1493 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) 1494 bclk_target = rate * sbits * slots; 1495 else 1496 bclk_target = rate * 128; 1497 1498 davinci_mcasp_calc_clk_div(mcasp, sysclk_freq, 1499 bclk_target, substream->stream, true); 1500 } 1501 1502 ret = mcasp_common_hw_param(mcasp, substream->stream, 1503 period_size * channels, channels); 1504 if (ret) 1505 return ret; 1506 1507 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1508 ret = mcasp_dit_hw_param(mcasp, params_rate(params)); 1509 else 1510 ret = mcasp_i2s_hw_param(mcasp, substream->stream, 1511 channels); 1512 1513 if (ret) 1514 return ret; 1515 1516 davinci_config_channel_size(mcasp, word_length, substream->stream); 1517 1518 /* Channel constraints are disabled for async mode */ 1519 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE && !mcasp->async_mode) { 1520 mcasp->channels = channels; 1521 if (!mcasp->max_format_width) 1522 mcasp->max_format_width = word_length; 1523 } 1524 1525 return 0; 1526 } 1527 1528 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, 1529 int cmd, struct snd_soc_dai *cpu_dai) 1530 { 1531 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1532 int ret = 0; 1533 1534 switch (cmd) { 1535 case SNDRV_PCM_TRIGGER_RESUME: 1536 case SNDRV_PCM_TRIGGER_START: 1537 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1538 davinci_mcasp_start(mcasp, substream->stream); 1539 break; 1540 case SNDRV_PCM_TRIGGER_SUSPEND: 1541 case SNDRV_PCM_TRIGGER_STOP: 1542 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1543 davinci_mcasp_stop(mcasp, substream->stream); 1544 break; 1545 1546 default: 1547 ret = -EINVAL; 1548 } 1549 1550 return ret; 1551 } 1552 1553 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params, 1554 struct snd_pcm_hw_rule *rule) 1555 { 1556 struct davinci_mcasp_ruledata *rd = rule->private; 1557 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1558 struct snd_mask nfmt; 1559 int slot_width; 1560 snd_pcm_format_t i; 1561 1562 snd_mask_none(&nfmt); 1563 slot_width = mcasp_get_slot_width(rd->mcasp, rd->stream); 1564 1565 pcm_for_each_format(i) { 1566 if (snd_mask_test_format(fmt, i)) { 1567 if (snd_pcm_format_width(i) <= slot_width) { 1568 snd_mask_set_format(&nfmt, i); 1569 } 1570 } 1571 } 1572 1573 return snd_mask_refine(fmt, &nfmt); 1574 } 1575 1576 static int davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params *params, 1577 struct snd_pcm_hw_rule *rule) 1578 { 1579 struct davinci_mcasp_ruledata *rd = rule->private; 1580 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1581 struct snd_mask nfmt; 1582 int format_width; 1583 snd_pcm_format_t i; 1584 1585 snd_mask_none(&nfmt); 1586 format_width = rd->mcasp->max_format_width; 1587 1588 pcm_for_each_format(i) { 1589 if (snd_mask_test_format(fmt, i)) { 1590 if (snd_pcm_format_width(i) == format_width) { 1591 snd_mask_set_format(&nfmt, i); 1592 } 1593 } 1594 } 1595 1596 return snd_mask_refine(fmt, &nfmt); 1597 } 1598 1599 static const unsigned int davinci_mcasp_dai_rates[] = { 1600 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 1601 88200, 96000, 176400, 192000, 1602 }; 1603 1604 #define DAVINCI_MAX_RATE_ERROR_PPM 1000 1605 1606 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params, 1607 struct snd_pcm_hw_rule *rule) 1608 { 1609 struct davinci_mcasp_ruledata *rd = rule->private; 1610 struct snd_interval *ri = 1611 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 1612 int sbits = params_width(params); 1613 int slots, slot_width; 1614 struct snd_interval range; 1615 int i; 1616 1617 slots = mcasp_get_tdm_slots(rd->mcasp, rd->stream); 1618 1619 slot_width = mcasp_get_slot_width(rd->mcasp, rd->stream); 1620 if (slot_width) 1621 sbits = slot_width; 1622 1623 snd_interval_any(&range); 1624 range.empty = 1; 1625 1626 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) { 1627 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) { 1628 uint bclk_freq = sbits * slots * 1629 davinci_mcasp_dai_rates[i]; 1630 unsigned int sysclk_freq; 1631 unsigned int ratio; 1632 int ppm; 1633 1634 ratio = mcasp_get_auxclk_fs_ratio(rd->mcasp, rd->stream); 1635 if (ratio) 1636 sysclk_freq = davinci_mcasp_dai_rates[i] * ratio; 1637 else 1638 sysclk_freq = mcasp_get_sysclk_freq(rd->mcasp, rd->stream); 1639 1640 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, 1641 bclk_freq, rd->stream, false); 1642 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1643 if (range.empty) { 1644 range.min = davinci_mcasp_dai_rates[i]; 1645 range.empty = 0; 1646 } 1647 range.max = davinci_mcasp_dai_rates[i]; 1648 } 1649 } 1650 } 1651 1652 dev_dbg(rd->mcasp->dev, 1653 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n", 1654 ri->min, ri->max, range.min, range.max, sbits, slots); 1655 1656 return snd_interval_refine(hw_param_interval(params, rule->var), 1657 &range); 1658 } 1659 1660 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params, 1661 struct snd_pcm_hw_rule *rule) 1662 { 1663 struct davinci_mcasp_ruledata *rd = rule->private; 1664 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1665 struct snd_mask nfmt; 1666 int rate = params_rate(params); 1667 int slots; 1668 int count = 0; 1669 snd_pcm_format_t i; 1670 1671 slots = mcasp_get_tdm_slots(rd->mcasp, rd->stream); 1672 1673 snd_mask_none(&nfmt); 1674 1675 pcm_for_each_format(i) { 1676 if (snd_mask_test_format(fmt, i)) { 1677 uint sbits = snd_pcm_format_width(i); 1678 unsigned int sysclk_freq; 1679 unsigned int ratio; 1680 int ppm, slot_width; 1681 1682 ratio = mcasp_get_auxclk_fs_ratio(rd->mcasp, rd->stream); 1683 if (ratio) 1684 sysclk_freq = rate * ratio; 1685 else 1686 sysclk_freq = mcasp_get_sysclk_freq(rd->mcasp, rd->stream); 1687 1688 slot_width = mcasp_get_slot_width(rd->mcasp, rd->stream); 1689 if (slot_width) 1690 sbits = slot_width; 1691 1692 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, 1693 sbits * slots * rate, 1694 rd->stream, false); 1695 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1696 snd_mask_set_format(&nfmt, i); 1697 count++; 1698 } 1699 } 1700 } 1701 dev_dbg(rd->mcasp->dev, 1702 "%d possible sample format for %d Hz and %d tdm slots\n", 1703 count, rate, slots); 1704 1705 return snd_mask_refine(fmt, &nfmt); 1706 } 1707 1708 static int davinci_mcasp_hw_rule_min_periodsize( 1709 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) 1710 { 1711 struct snd_interval *period_size = hw_param_interval(params, 1712 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 1713 u8 numevt = *((u8 *)rule->private); 1714 struct snd_interval frames; 1715 1716 snd_interval_any(&frames); 1717 frames.min = numevt; 1718 frames.integer = 1; 1719 1720 return snd_interval_refine(period_size, &frames); 1721 } 1722 1723 static int davinci_mcasp_startup(struct snd_pcm_substream *substream, 1724 struct snd_soc_dai *cpu_dai) 1725 { 1726 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1727 struct davinci_mcasp_ruledata *ruledata = 1728 &mcasp->ruledata[substream->stream]; 1729 u32 max_channels = 0; 1730 int i, dir, ret; 1731 int tdm_slots; 1732 u8 *numevt; 1733 1734 /* Do not allow more then one stream per direction */ 1735 if (mcasp->substreams[substream->stream]) 1736 return -EBUSY; 1737 1738 mcasp->substreams[substream->stream] = substream; 1739 1740 tdm_slots = mcasp_get_tdm_slots(mcasp, substream->stream); 1741 1742 if (mcasp->tdm_mask[substream->stream]) 1743 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]); 1744 1745 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1746 return 0; 1747 1748 /* 1749 * Limit the maximum allowed channels for the first stream: 1750 * number of serializers for the direction * tdm slots per serializer 1751 */ 1752 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1753 dir = TX_MODE; 1754 else 1755 dir = RX_MODE; 1756 1757 for (i = 0; i < mcasp->num_serializer; i++) { 1758 if (mcasp->serial_dir[i] == dir) 1759 max_channels++; 1760 } 1761 ruledata->serializers = max_channels; 1762 ruledata->mcasp = mcasp; 1763 ruledata->stream = substream->stream; 1764 max_channels *= tdm_slots; 1765 /* 1766 * If the already active stream has less channels than the calculated 1767 * limit based on the seirializers * tdm_slots, and only one serializer 1768 * is in use we need to use that as a constraint for the second stream. 1769 * Otherwise (first stream or less allowed channels or more than one 1770 * serializer in use) we use the calculated constraint. 1771 * 1772 * However, in async mode, TX and RX have independent clocks and can 1773 * use different configurations, so don't apply the constraint. 1774 */ 1775 if (mcasp->channels && mcasp->channels < max_channels && 1776 ruledata->serializers == 1 && 1777 !mcasp->async_mode) 1778 max_channels = mcasp->channels; 1779 /* 1780 * But we can always allow channels upto the amount of 1781 * the available tdm_slots. 1782 */ 1783 if (max_channels < tdm_slots) 1784 max_channels = tdm_slots; 1785 1786 snd_pcm_hw_constraint_minmax(substream->runtime, 1787 SNDRV_PCM_HW_PARAM_CHANNELS, 1788 0, max_channels); 1789 1790 snd_pcm_hw_constraint_list(substream->runtime, 1791 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1792 &mcasp->chconstr[substream->stream]); 1793 1794 if (mcasp->max_format_width && !mcasp->async_mode) { 1795 /* 1796 * Only allow formats which require same amount of bits on the 1797 * bus as the currently running stream to ensure sync mode 1798 */ 1799 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1800 SNDRV_PCM_HW_PARAM_FORMAT, 1801 davinci_mcasp_hw_rule_format_width, 1802 ruledata, 1803 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1804 if (ret) 1805 return ret; 1806 } else if (mcasp_get_slot_width(mcasp, substream->stream)) { 1807 /* Only allow formats require <= slot_width bits on the bus */ 1808 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1809 SNDRV_PCM_HW_PARAM_FORMAT, 1810 davinci_mcasp_hw_rule_slot_width, 1811 ruledata, 1812 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1813 if (ret) 1814 return ret; 1815 } 1816 1817 /* 1818 * If we rely on implicit BCLK divider setting we should 1819 * set constraints based on what we can provide. 1820 */ 1821 if (mcasp->bclk_master && mcasp_get_bclk_div(mcasp, substream->stream) == 0 && 1822 mcasp_get_sysclk_freq(mcasp, substream->stream)) { 1823 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1824 SNDRV_PCM_HW_PARAM_RATE, 1825 davinci_mcasp_hw_rule_rate, 1826 ruledata, 1827 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1828 if (ret) 1829 return ret; 1830 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1831 SNDRV_PCM_HW_PARAM_FORMAT, 1832 davinci_mcasp_hw_rule_format, 1833 ruledata, 1834 SNDRV_PCM_HW_PARAM_RATE, -1); 1835 if (ret) 1836 return ret; 1837 } 1838 1839 numevt = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 1840 &mcasp->txnumevt : 1841 &mcasp->rxnumevt; 1842 snd_pcm_hw_rule_add(substream->runtime, 0, 1843 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1844 davinci_mcasp_hw_rule_min_periodsize, numevt, 1845 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1); 1846 1847 return 0; 1848 } 1849 1850 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream, 1851 struct snd_soc_dai *cpu_dai) 1852 { 1853 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1854 1855 mcasp->substreams[substream->stream] = NULL; 1856 mcasp->active_serializers[substream->stream] = 0; 1857 1858 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1859 return; 1860 1861 if (!snd_soc_dai_active(cpu_dai)) { 1862 mcasp->channels = 0; 1863 mcasp->max_format_width = 0; 1864 } 1865 } 1866 1867 static int davinci_mcasp_iec958_info(struct snd_kcontrol *kcontrol, 1868 struct snd_ctl_elem_info *uinfo) 1869 { 1870 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1871 uinfo->count = 1; 1872 1873 return 0; 1874 } 1875 1876 static int davinci_mcasp_iec958_get(struct snd_kcontrol *kcontrol, 1877 struct snd_ctl_elem_value *uctl) 1878 { 1879 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1880 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1881 1882 memcpy(uctl->value.iec958.status, &mcasp->iec958_status, 1883 sizeof(mcasp->iec958_status)); 1884 1885 return 0; 1886 } 1887 1888 static int davinci_mcasp_iec958_put(struct snd_kcontrol *kcontrol, 1889 struct snd_ctl_elem_value *uctl) 1890 { 1891 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1892 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1893 1894 memcpy(&mcasp->iec958_status, uctl->value.iec958.status, 1895 sizeof(mcasp->iec958_status)); 1896 1897 return 0; 1898 } 1899 1900 static int davinci_mcasp_iec958_con_mask_get(struct snd_kcontrol *kcontrol, 1901 struct snd_ctl_elem_value *ucontrol) 1902 { 1903 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1904 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1905 1906 memset(ucontrol->value.iec958.status, 0xff, sizeof(mcasp->iec958_status)); 1907 return 0; 1908 } 1909 1910 static const struct snd_kcontrol_new davinci_mcasp_iec958_ctls[] = { 1911 { 1912 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 1913 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 1914 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1915 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1916 .info = davinci_mcasp_iec958_info, 1917 .get = davinci_mcasp_iec958_get, 1918 .put = davinci_mcasp_iec958_put, 1919 }, { 1920 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1921 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1922 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK), 1923 .info = davinci_mcasp_iec958_info, 1924 .get = davinci_mcasp_iec958_con_mask_get, 1925 }, 1926 }; 1927 1928 static void davinci_mcasp_init_iec958_status(struct davinci_mcasp *mcasp) 1929 { 1930 unsigned char *cs = (u8 *)&mcasp->iec958_status; 1931 1932 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; 1933 cs[1] = IEC958_AES1_CON_PCM_CODER; 1934 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; 1935 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM; 1936 } 1937 1938 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) 1939 { 1940 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 1941 int stream; 1942 1943 for_each_pcm_streams(stream) 1944 snd_soc_dai_dma_data_set(dai, stream, &mcasp->dma_data[stream]); 1945 1946 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) { 1947 davinci_mcasp_init_iec958_status(mcasp); 1948 snd_soc_add_dai_controls(dai, davinci_mcasp_iec958_ctls, 1949 ARRAY_SIZE(davinci_mcasp_iec958_ctls)); 1950 } 1951 1952 return 0; 1953 } 1954 1955 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { 1956 .probe = davinci_mcasp_dai_probe, 1957 .startup = davinci_mcasp_startup, 1958 .shutdown = davinci_mcasp_shutdown, 1959 .trigger = davinci_mcasp_trigger, 1960 .delay = davinci_mcasp_delay, 1961 .hw_params = davinci_mcasp_hw_params, 1962 .set_fmt = davinci_mcasp_set_dai_fmt, 1963 .set_clkdiv = davinci_mcasp_set_clkdiv, 1964 .set_sysclk = davinci_mcasp_set_sysclk, 1965 .set_tdm_slot = davinci_mcasp_set_tdm_slot, 1966 }; 1967 1968 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 1969 1970 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 1971 SNDRV_PCM_FMTBIT_U8 | \ 1972 SNDRV_PCM_FMTBIT_S16_LE | \ 1973 SNDRV_PCM_FMTBIT_U16_LE | \ 1974 SNDRV_PCM_FMTBIT_S24_LE | \ 1975 SNDRV_PCM_FMTBIT_U24_LE | \ 1976 SNDRV_PCM_FMTBIT_S24_3LE | \ 1977 SNDRV_PCM_FMTBIT_U24_3LE | \ 1978 SNDRV_PCM_FMTBIT_S32_LE | \ 1979 SNDRV_PCM_FMTBIT_U32_LE) 1980 1981 static struct snd_soc_dai_driver davinci_mcasp_dai[] = { 1982 { 1983 .name = "davinci-mcasp.0", 1984 .playback = { 1985 .stream_name = "IIS Playback", 1986 .channels_min = 1, 1987 .channels_max = 32 * 16, 1988 .rates = DAVINCI_MCASP_RATES, 1989 .formats = DAVINCI_MCASP_PCM_FMTS, 1990 }, 1991 .capture = { 1992 .stream_name = "IIS Capture", 1993 .channels_min = 1, 1994 .channels_max = 32 * 16, 1995 .rates = DAVINCI_MCASP_RATES, 1996 .formats = DAVINCI_MCASP_PCM_FMTS, 1997 }, 1998 .ops = &davinci_mcasp_dai_ops, 1999 }, 2000 { 2001 .name = "davinci-mcasp.1", 2002 .playback = { 2003 .stream_name = "DIT Playback", 2004 .channels_min = 1, 2005 .channels_max = 384, 2006 .rates = DAVINCI_MCASP_RATES, 2007 .formats = SNDRV_PCM_FMTBIT_S16_LE | 2008 SNDRV_PCM_FMTBIT_S24_LE, 2009 }, 2010 .ops = &davinci_mcasp_dai_ops, 2011 }, 2012 2013 }; 2014 2015 static const struct snd_soc_component_driver davinci_mcasp_component = { 2016 .name = "davinci-mcasp", 2017 .legacy_dai_naming = 1, 2018 }; 2019 2020 /* Some HW specific values and defaults. The rest is filled in from DT. */ 2021 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { 2022 .tx_dma_offset = 0x400, 2023 .rx_dma_offset = 0x400, 2024 .version = MCASP_VERSION_1, 2025 }; 2026 2027 static struct davinci_mcasp_pdata da830_mcasp_pdata = { 2028 .tx_dma_offset = 0x2000, 2029 .rx_dma_offset = 0x2000, 2030 .version = MCASP_VERSION_2, 2031 }; 2032 2033 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { 2034 .tx_dma_offset = 0, 2035 .rx_dma_offset = 0, 2036 .version = MCASP_VERSION_3, 2037 }; 2038 2039 static struct davinci_mcasp_pdata dra7_mcasp_pdata = { 2040 /* The CFG port offset will be calculated if it is needed */ 2041 .tx_dma_offset = 0, 2042 .rx_dma_offset = 0, 2043 .version = MCASP_VERSION_4, 2044 }; 2045 2046 static struct davinci_mcasp_pdata omap_mcasp_pdata = { 2047 .tx_dma_offset = 0x200, 2048 .rx_dma_offset = 0, 2049 .version = MCASP_VERSION_OMAP, 2050 }; 2051 2052 static const struct of_device_id mcasp_dt_ids[] = { 2053 { 2054 .compatible = "ti,dm646x-mcasp-audio", 2055 .data = &dm646x_mcasp_pdata, 2056 }, 2057 { 2058 .compatible = "ti,da830-mcasp-audio", 2059 .data = &da830_mcasp_pdata, 2060 }, 2061 { 2062 .compatible = "ti,am33xx-mcasp-audio", 2063 .data = &am33xx_mcasp_pdata, 2064 }, 2065 { 2066 .compatible = "ti,dra7-mcasp-audio", 2067 .data = &dra7_mcasp_pdata, 2068 }, 2069 { 2070 .compatible = "ti,omap4-mcasp-audio", 2071 .data = &omap_mcasp_pdata, 2072 }, 2073 { /* sentinel */ } 2074 }; 2075 MODULE_DEVICE_TABLE(of, mcasp_dt_ids); 2076 2077 static int mcasp_reparent_fck(struct platform_device *pdev) 2078 { 2079 struct device_node *node = pdev->dev.of_node; 2080 struct clk *gfclk, *parent_clk; 2081 const char *parent_name; 2082 int ret; 2083 2084 if (!node) 2085 return 0; 2086 2087 parent_name = of_get_property(node, "fck_parent", NULL); 2088 if (!parent_name) 2089 return 0; 2090 2091 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n"); 2092 2093 gfclk = clk_get(&pdev->dev, "fck"); 2094 if (IS_ERR(gfclk)) { 2095 dev_err(&pdev->dev, "failed to get fck\n"); 2096 return PTR_ERR(gfclk); 2097 } 2098 2099 parent_clk = clk_get(NULL, parent_name); 2100 if (IS_ERR(parent_clk)) { 2101 dev_err(&pdev->dev, "failed to get parent clock\n"); 2102 ret = PTR_ERR(parent_clk); 2103 goto err1; 2104 } 2105 2106 ret = clk_set_parent(gfclk, parent_clk); 2107 if (ret) { 2108 dev_err(&pdev->dev, "failed to reparent fck\n"); 2109 goto err2; 2110 } 2111 2112 err2: 2113 clk_put(parent_clk); 2114 err1: 2115 clk_put(gfclk); 2116 return ret; 2117 } 2118 2119 static bool davinci_mcasp_have_gpiochip(struct davinci_mcasp *mcasp) 2120 { 2121 return device_property_present(mcasp->dev, "gpio-controller"); 2122 } 2123 2124 static int davinci_mcasp_get_config(struct davinci_mcasp *mcasp, 2125 struct platform_device *pdev) 2126 { 2127 struct device_node *np = pdev->dev.of_node; 2128 struct davinci_mcasp_pdata *pdata = NULL; 2129 const struct davinci_mcasp_pdata *match_pdata = 2130 device_get_match_data(&pdev->dev); 2131 const u32 *of_serial_dir32; 2132 u32 val; 2133 int i; 2134 2135 if (pdev->dev.platform_data) { 2136 pdata = pdev->dev.platform_data; 2137 pdata->dismod = DISMOD_LOW; 2138 goto out; 2139 } else if (match_pdata) { 2140 pdata = devm_kmemdup(&pdev->dev, match_pdata, sizeof(*pdata), 2141 GFP_KERNEL); 2142 if (!pdata) 2143 return -ENOMEM; 2144 } else { 2145 dev_err(&pdev->dev, "No compatible match found\n"); 2146 return -EINVAL; 2147 } 2148 2149 if (of_property_read_u32(np, "op-mode", &val) == 0) { 2150 pdata->op_mode = val; 2151 } else { 2152 mcasp->missing_audio_param = true; 2153 goto out; 2154 } 2155 2156 /* Parse TX-specific TDM slot and use it as default for RX */ 2157 if (of_property_read_u32(np, "tdm-slots", &val) == 0) { 2158 if (val < 2 || val > 32) { 2159 dev_err(&pdev->dev, "tdm-slots must be in range [2-32]\n"); 2160 return -EINVAL; 2161 } 2162 2163 pdata->tdm_slots_tx = val; 2164 pdata->tdm_slots_rx = val; 2165 } else if (pdata->op_mode == DAVINCI_MCASP_IIS_MODE) { 2166 mcasp->missing_audio_param = true; 2167 goto out; 2168 } 2169 2170 /* Parse RX-specific TDM slot count if provided */ 2171 if (of_property_read_u32(np, "tdm-slots-rx", &val) == 0) { 2172 if (val < 2 || val > 32) { 2173 dev_err(&pdev->dev, "tdm-slots-rx must be in range [2-32]\n"); 2174 return -EINVAL; 2175 } 2176 2177 pdata->tdm_slots_rx = val; 2178 } 2179 2180 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) 2181 mcasp->async_mode = of_property_read_bool(np, "ti,async-mode"); 2182 2183 of_serial_dir32 = of_get_property(np, "serial-dir", &val); 2184 val /= sizeof(u32); 2185 if (of_serial_dir32) { 2186 u8 *of_serial_dir = devm_kzalloc(&pdev->dev, 2187 (sizeof(*of_serial_dir) * val), 2188 GFP_KERNEL); 2189 if (!of_serial_dir) 2190 return -ENOMEM; 2191 2192 for (i = 0; i < val; i++) 2193 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); 2194 2195 pdata->num_serializer = val; 2196 pdata->serial_dir = of_serial_dir; 2197 } else { 2198 mcasp->missing_audio_param = true; 2199 goto out; 2200 } 2201 2202 if (of_property_read_u32(np, "tx-num-evt", &val) == 0) 2203 pdata->txnumevt = val; 2204 2205 if (of_property_read_u32(np, "rx-num-evt", &val) == 0) 2206 pdata->rxnumevt = val; 2207 2208 /* Parse TX-specific auxclk/fs ratio and use it as default for RX */ 2209 if (of_property_read_u32(np, "auxclk-fs-ratio", &val) == 0) { 2210 mcasp->auxclk_fs_ratio_tx = val; 2211 mcasp->auxclk_fs_ratio_rx = val; 2212 } 2213 2214 /* Parse RX-specific auxclk/fs ratio if provided */ 2215 if (of_property_read_u32(np, "auxclk-fs-ratio-rx", &val) == 0) 2216 mcasp->auxclk_fs_ratio_rx = val; 2217 2218 if (of_property_read_u32(np, "dismod", &val) == 0) { 2219 if (val == 0 || val == 2 || val == 3) { 2220 pdata->dismod = DISMOD_VAL(val); 2221 } else { 2222 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val); 2223 pdata->dismod = DISMOD_LOW; 2224 } 2225 } else { 2226 pdata->dismod = DISMOD_LOW; 2227 } 2228 2229 out: 2230 mcasp->pdata = pdata; 2231 2232 if (mcasp->missing_audio_param) { 2233 if (davinci_mcasp_have_gpiochip(mcasp)) { 2234 dev_dbg(&pdev->dev, "Missing DT parameter(s) for audio\n"); 2235 return 0; 2236 } 2237 2238 dev_err(&pdev->dev, "Insufficient DT parameter(s)\n"); 2239 return -ENODEV; 2240 } 2241 2242 mcasp->op_mode = pdata->op_mode; 2243 /* sanity check for tdm slots parameter */ 2244 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { 2245 if (pdata->tdm_slots_tx < 2) { 2246 dev_warn(&pdev->dev, "invalid tdm tx slots: %d\n", 2247 pdata->tdm_slots_tx); 2248 mcasp->tdm_slots_tx = 2; 2249 } else if (pdata->tdm_slots_tx > 32) { 2250 dev_warn(&pdev->dev, "invalid tdm tx slots: %d\n", 2251 pdata->tdm_slots_tx); 2252 mcasp->tdm_slots_tx = 32; 2253 } else { 2254 mcasp->tdm_slots_tx = pdata->tdm_slots_tx; 2255 } 2256 2257 if (pdata->tdm_slots_rx < 2) { 2258 dev_warn(&pdev->dev, "invalid tdm rx slots: %d\n", 2259 pdata->tdm_slots_rx); 2260 mcasp->tdm_slots_rx = 2; 2261 } else if (pdata->tdm_slots_rx > 32) { 2262 dev_warn(&pdev->dev, "invalid tdm rx slots: %d\n", 2263 pdata->tdm_slots_rx); 2264 mcasp->tdm_slots_rx = 32; 2265 } else { 2266 mcasp->tdm_slots_rx = pdata->tdm_slots_rx; 2267 } 2268 } else { 2269 mcasp->tdm_slots_tx = 32; 2270 mcasp->tdm_slots_rx = 32; 2271 } 2272 2273 /* Different TX/RX slot counts require async mode */ 2274 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE && 2275 mcasp->tdm_slots_tx != mcasp->tdm_slots_rx && !mcasp->async_mode) { 2276 dev_err(&pdev->dev, 2277 "Different TX (%d) and RX (%d) TDM slots require ti,async-mode\n", 2278 mcasp->tdm_slots_tx, mcasp->tdm_slots_rx); 2279 return -EINVAL; 2280 } 2281 2282 /* Different TX/RX auxclk-fs-ratio require async mode */ 2283 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE && 2284 mcasp->auxclk_fs_ratio_tx && mcasp->auxclk_fs_ratio_rx && 2285 mcasp->auxclk_fs_ratio_tx != mcasp->auxclk_fs_ratio_rx && !mcasp->async_mode) { 2286 dev_err(&pdev->dev, 2287 "Different TX (%d) and RX (%d) auxclk-fs-ratio require ti,async-mode\n", 2288 mcasp->auxclk_fs_ratio_tx, mcasp->auxclk_fs_ratio_rx); 2289 return -EINVAL; 2290 } 2291 2292 mcasp->num_serializer = pdata->num_serializer; 2293 #ifdef CONFIG_PM 2294 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev, 2295 mcasp->num_serializer, sizeof(u32), 2296 GFP_KERNEL); 2297 if (!mcasp->context.xrsr_regs) 2298 return -ENOMEM; 2299 #endif 2300 mcasp->serial_dir = pdata->serial_dir; 2301 mcasp->version = pdata->version; 2302 mcasp->txnumevt = pdata->txnumevt; 2303 mcasp->rxnumevt = pdata->rxnumevt; 2304 mcasp->dismod = pdata->dismod; 2305 2306 return 0; 2307 } 2308 2309 enum { 2310 PCM_EDMA, 2311 PCM_SDMA, 2312 PCM_UDMA, 2313 }; 2314 static const char *sdma_prefix = "ti,omap"; 2315 2316 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) 2317 { 2318 struct dma_chan *chan; 2319 const char *tmp; 2320 int ret = PCM_EDMA; 2321 2322 if (!mcasp->dev->of_node) 2323 return PCM_EDMA; 2324 2325 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data; 2326 chan = dma_request_chan(mcasp->dev, tmp); 2327 if (IS_ERR(chan)) 2328 return dev_err_probe(mcasp->dev, PTR_ERR(chan), 2329 "Can't verify DMA configuration\n"); 2330 if (WARN_ON(!chan->device || !chan->device->dev)) { 2331 dma_release_channel(chan); 2332 return -EINVAL; 2333 } 2334 2335 if (chan->device->dev->of_node) 2336 ret = of_property_read_string(chan->device->dev->of_node, 2337 "compatible", &tmp); 2338 else 2339 dev_dbg(mcasp->dev, "DMA controller has no of-node\n"); 2340 2341 dma_release_channel(chan); 2342 if (ret) 2343 return ret; 2344 2345 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp); 2346 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix))) 2347 return PCM_SDMA; 2348 else if (strstr(tmp, "udmap")) 2349 return PCM_UDMA; 2350 else if (strstr(tmp, "bcdma")) 2351 return PCM_UDMA; 2352 2353 return PCM_EDMA; 2354 } 2355 2356 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata) 2357 { 2358 int i; 2359 u32 offset = 0; 2360 2361 if (pdata->version != MCASP_VERSION_4) 2362 return pdata->tx_dma_offset; 2363 2364 for (i = 0; i < pdata->num_serializer; i++) { 2365 if (pdata->serial_dir[i] == TX_MODE) { 2366 if (!offset) { 2367 offset = DAVINCI_MCASP_TXBUF_REG(i); 2368 } else { 2369 pr_err("%s: Only one serializer allowed!\n", 2370 __func__); 2371 break; 2372 } 2373 } 2374 } 2375 2376 return offset; 2377 } 2378 2379 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata) 2380 { 2381 int i; 2382 u32 offset = 0; 2383 2384 if (pdata->version != MCASP_VERSION_4) 2385 return pdata->rx_dma_offset; 2386 2387 for (i = 0; i < pdata->num_serializer; i++) { 2388 if (pdata->serial_dir[i] == RX_MODE) { 2389 if (!offset) { 2390 offset = DAVINCI_MCASP_RXBUF_REG(i); 2391 } else { 2392 pr_err("%s: Only one serializer allowed!\n", 2393 __func__); 2394 break; 2395 } 2396 } 2397 } 2398 2399 return offset; 2400 } 2401 2402 #ifdef CONFIG_GPIOLIB 2403 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset) 2404 { 2405 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2406 2407 if (mcasp->num_serializer && offset < mcasp->num_serializer && 2408 mcasp->serial_dir[offset] != INACTIVE_MODE) { 2409 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset); 2410 return -EBUSY; 2411 } 2412 2413 /* Do not change the PIN yet */ 2414 return pm_runtime_resume_and_get(mcasp->dev); 2415 } 2416 2417 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset) 2418 { 2419 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2420 2421 /* Set the direction to input */ 2422 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2423 2424 /* Set the pin as McASP pin */ 2425 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2426 2427 pm_runtime_put_sync(mcasp->dev); 2428 } 2429 2430 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip, 2431 unsigned offset, int value) 2432 { 2433 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2434 u32 val; 2435 2436 if (value) 2437 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2438 else 2439 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2440 2441 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 2442 if (!(val & BIT(offset))) { 2443 /* Set the pin as GPIO pin */ 2444 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2445 2446 /* Set the direction to output */ 2447 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2448 } 2449 2450 return 0; 2451 } 2452 2453 static int davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned int offset, 2454 int value) 2455 { 2456 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2457 2458 if (value) 2459 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2460 else 2461 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2462 2463 return 0; 2464 } 2465 2466 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip, 2467 unsigned offset) 2468 { 2469 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2470 u32 val; 2471 2472 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 2473 if (!(val & BIT(offset))) { 2474 /* Set the direction to input */ 2475 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2476 2477 /* Set the pin as GPIO pin */ 2478 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2479 } 2480 2481 return 0; 2482 } 2483 2484 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset) 2485 { 2486 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2487 u32 val; 2488 2489 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG); 2490 if (val & BIT(offset)) 2491 return 1; 2492 2493 return 0; 2494 } 2495 2496 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip, 2497 unsigned offset) 2498 { 2499 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2500 u32 val; 2501 2502 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); 2503 if (val & BIT(offset)) 2504 return 0; 2505 2506 return 1; 2507 } 2508 2509 static const struct gpio_chip davinci_mcasp_template_chip = { 2510 .owner = THIS_MODULE, 2511 .request = davinci_mcasp_gpio_request, 2512 .free = davinci_mcasp_gpio_free, 2513 .direction_output = davinci_mcasp_gpio_direction_out, 2514 .set = davinci_mcasp_gpio_set, 2515 .direction_input = davinci_mcasp_gpio_direction_in, 2516 .get = davinci_mcasp_gpio_get, 2517 .get_direction = davinci_mcasp_gpio_get_direction, 2518 .base = -1, 2519 .ngpio = 32, 2520 }; 2521 2522 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 2523 { 2524 if (!davinci_mcasp_have_gpiochip(mcasp)) 2525 return 0; 2526 2527 mcasp->gpio_chip = davinci_mcasp_template_chip; 2528 mcasp->gpio_chip.label = dev_name(mcasp->dev); 2529 mcasp->gpio_chip.parent = mcasp->dev; 2530 2531 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp); 2532 } 2533 2534 #else /* CONFIG_GPIOLIB */ 2535 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 2536 { 2537 return 0; 2538 } 2539 #endif /* CONFIG_GPIOLIB */ 2540 2541 static int davinci_mcasp_probe(struct platform_device *pdev) 2542 { 2543 struct snd_dmaengine_dai_dma_data *dma_data; 2544 struct resource *mem, *dat; 2545 struct davinci_mcasp *mcasp; 2546 char *irq_name; 2547 int irq; 2548 int ret; 2549 2550 if (!pdev->dev.platform_data && !pdev->dev.of_node) { 2551 dev_err(&pdev->dev, "No platform data supplied\n"); 2552 return -EINVAL; 2553 } 2554 2555 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), 2556 GFP_KERNEL); 2557 if (!mcasp) 2558 return -ENOMEM; 2559 2560 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 2561 if (!mem) { 2562 dev_warn(&pdev->dev, 2563 "\"mpu\" mem resource not found, using index 0\n"); 2564 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2565 if (!mem) { 2566 dev_err(&pdev->dev, "no mem resource?\n"); 2567 return -ENODEV; 2568 } 2569 } 2570 2571 mcasp->base = devm_ioremap_resource(&pdev->dev, mem); 2572 if (IS_ERR(mcasp->base)) 2573 return PTR_ERR(mcasp->base); 2574 2575 dev_set_drvdata(&pdev->dev, mcasp); 2576 pm_runtime_enable(&pdev->dev); 2577 2578 mcasp->dev = &pdev->dev; 2579 ret = davinci_mcasp_get_config(mcasp, pdev); 2580 if (ret) 2581 goto err; 2582 2583 /* All PINS as McASP */ 2584 pm_runtime_get_sync(mcasp->dev); 2585 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); 2586 pm_runtime_put(mcasp->dev); 2587 2588 /* Skip audio related setup code if the configuration is not adequat */ 2589 if (mcasp->missing_audio_param) 2590 goto no_audio; 2591 2592 irq = platform_get_irq_byname_optional(pdev, "common"); 2593 if (irq > 0) { 2594 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common", 2595 dev_name(&pdev->dev)); 2596 if (!irq_name) { 2597 ret = -ENOMEM; 2598 goto err; 2599 } 2600 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2601 davinci_mcasp_common_irq_handler, 2602 IRQF_ONESHOT | IRQF_SHARED, 2603 irq_name, mcasp); 2604 if (ret) { 2605 dev_err(&pdev->dev, "common IRQ request failed\n"); 2606 goto err; 2607 } 2608 2609 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2610 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2611 } 2612 2613 irq = platform_get_irq_byname_optional(pdev, "rx"); 2614 if (irq > 0) { 2615 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx", 2616 dev_name(&pdev->dev)); 2617 if (!irq_name) { 2618 ret = -ENOMEM; 2619 goto err; 2620 } 2621 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2622 davinci_mcasp_rx_irq_handler, 2623 IRQF_ONESHOT, irq_name, mcasp); 2624 if (ret) { 2625 dev_err(&pdev->dev, "RX IRQ request failed\n"); 2626 goto err; 2627 } 2628 2629 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2630 } 2631 2632 irq = platform_get_irq_byname_optional(pdev, "tx"); 2633 if (irq > 0) { 2634 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx", 2635 dev_name(&pdev->dev)); 2636 if (!irq_name) { 2637 ret = -ENOMEM; 2638 goto err; 2639 } 2640 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2641 davinci_mcasp_tx_irq_handler, 2642 IRQF_ONESHOT, irq_name, mcasp); 2643 if (ret) { 2644 dev_err(&pdev->dev, "TX IRQ request failed\n"); 2645 goto err; 2646 } 2647 2648 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2649 } 2650 2651 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 2652 if (dat) 2653 mcasp->dat_port = true; 2654 2655 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 2656 dma_data->filter_data = "tx"; 2657 if (dat) { 2658 dma_data->addr = dat->start; 2659 /* 2660 * According to the TRM there should be 0x200 offset added to 2661 * the DAT port address 2662 */ 2663 if (mcasp->version == MCASP_VERSION_OMAP) 2664 dma_data->addr += davinci_mcasp_txdma_offset(mcasp->pdata); 2665 } else { 2666 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(mcasp->pdata); 2667 } 2668 2669 2670 /* RX is not valid in DIT mode */ 2671 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 2672 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; 2673 dma_data->filter_data = "rx"; 2674 if (dat) 2675 dma_data->addr = dat->start; 2676 else 2677 dma_data->addr = 2678 mem->start + davinci_mcasp_rxdma_offset(mcasp->pdata); 2679 } 2680 2681 if (mcasp->version < MCASP_VERSION_3) { 2682 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; 2683 /* dma_params->dma_addr is pointing to the data port address */ 2684 mcasp->dat_port = true; 2685 } else { 2686 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; 2687 } 2688 2689 /* Allocate memory for long enough list for all possible 2690 * scenarios. Maximum number tdm slots is 32 and there cannot 2691 * be more serializers than given in the configuration. The 2692 * serializer directions could be taken into account, but it 2693 * would make code much more complex and save only couple of 2694 * bytes. 2695 */ 2696 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list = 2697 devm_kcalloc(mcasp->dev, 2698 32 + mcasp->num_serializer - 1, 2699 sizeof(unsigned int), 2700 GFP_KERNEL); 2701 2702 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list = 2703 devm_kcalloc(mcasp->dev, 2704 32 + mcasp->num_serializer - 1, 2705 sizeof(unsigned int), 2706 GFP_KERNEL); 2707 2708 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list || 2709 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) { 2710 ret = -ENOMEM; 2711 goto err; 2712 } 2713 2714 ret = davinci_mcasp_set_ch_constraints(mcasp); 2715 if (ret) 2716 goto err; 2717 2718 mcasp_reparent_fck(pdev); 2719 2720 ret = davinci_mcasp_get_dma_type(mcasp); 2721 switch (ret) { 2722 case PCM_EDMA: 2723 ret = edma_pcm_platform_register(&pdev->dev); 2724 break; 2725 case PCM_SDMA: 2726 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) 2727 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx"); 2728 else 2729 ret = sdma_pcm_platform_register(&pdev->dev, "tx", NULL); 2730 break; 2731 case PCM_UDMA: 2732 ret = udma_pcm_platform_register(&pdev->dev); 2733 break; 2734 default: 2735 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret); 2736 fallthrough; 2737 case -EPROBE_DEFER: 2738 goto err; 2739 } 2740 2741 if (ret) { 2742 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 2743 goto err; 2744 } 2745 2746 ret = devm_snd_soc_register_component(&pdev->dev, &davinci_mcasp_component, 2747 &davinci_mcasp_dai[mcasp->op_mode], 1); 2748 2749 if (ret != 0) 2750 goto err; 2751 2752 no_audio: 2753 ret = davinci_mcasp_init_gpiochip(mcasp); 2754 if (ret) { 2755 dev_err(&pdev->dev, "gpiochip registration failed: %d\n", ret); 2756 goto err; 2757 } 2758 2759 return 0; 2760 err: 2761 pm_runtime_disable(&pdev->dev); 2762 return ret; 2763 } 2764 2765 static void davinci_mcasp_remove(struct platform_device *pdev) 2766 { 2767 pm_runtime_disable(&pdev->dev); 2768 } 2769 2770 #ifdef CONFIG_PM 2771 static int davinci_mcasp_runtime_suspend(struct device *dev) 2772 { 2773 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2774 struct davinci_mcasp_context *context = &mcasp->context; 2775 u32 reg; 2776 int i; 2777 2778 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2779 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); 2780 2781 if (mcasp->txnumevt) { 2782 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2783 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); 2784 } 2785 if (mcasp->rxnumevt) { 2786 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2787 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); 2788 } 2789 2790 for (i = 0; i < mcasp->num_serializer; i++) 2791 context->xrsr_regs[i] = mcasp_get_reg(mcasp, 2792 DAVINCI_MCASP_XRSRCTL_REG(i)); 2793 2794 return 0; 2795 } 2796 2797 static int davinci_mcasp_runtime_resume(struct device *dev) 2798 { 2799 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2800 struct davinci_mcasp_context *context = &mcasp->context; 2801 u32 reg; 2802 int i; 2803 2804 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2805 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); 2806 2807 if (mcasp->txnumevt) { 2808 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2809 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); 2810 } 2811 if (mcasp->rxnumevt) { 2812 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2813 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); 2814 } 2815 2816 for (i = 0; i < mcasp->num_serializer; i++) 2817 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 2818 context->xrsr_regs[i]); 2819 2820 return 0; 2821 } 2822 2823 #endif 2824 2825 static const struct dev_pm_ops davinci_mcasp_pm_ops = { 2826 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend, 2827 davinci_mcasp_runtime_resume, 2828 NULL) 2829 }; 2830 2831 static struct platform_driver davinci_mcasp_driver = { 2832 .probe = davinci_mcasp_probe, 2833 .remove = davinci_mcasp_remove, 2834 .driver = { 2835 .name = "davinci-mcasp", 2836 .pm = &davinci_mcasp_pm_ops, 2837 .of_match_table = mcasp_dt_ids, 2838 }, 2839 }; 2840 2841 module_platform_driver(davinci_mcasp_driver); 2842 2843 MODULE_AUTHOR("Steve Chen"); 2844 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); 2845 MODULE_LICENSE("GPL"); 2846