1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/etherdevice.h> 34 #include <rdma/ib_umem.h> 35 #include <rdma/ib_cache.h> 36 #include <rdma/ib_user_verbs.h> 37 #include <rdma/rdma_counter.h> 38 #include <linux/mlx5/fs.h> 39 #include "mlx5_ib.h" 40 #include "ib_rep.h" 41 #include "counters.h" 42 #include "cmd.h" 43 #include "umr.h" 44 #include "qp.h" 45 #include "wr.h" 46 47 enum { 48 MLX5_IB_ACK_REQ_FREQ = 8, 49 }; 50 51 enum { 52 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 53 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 54 MLX5_IB_LINK_TYPE_IB = 0, 55 MLX5_IB_LINK_TYPE_ETH = 1 56 }; 57 58 enum raw_qp_set_mask_map { 59 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 60 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, 61 }; 62 63 enum { 64 MLX5_QP_RM_GO_BACK_N = 0x1, 65 }; 66 67 struct mlx5_modify_raw_qp_param { 68 u16 operation; 69 70 u32 set_mask; /* raw_qp_set_mask_map */ 71 72 struct mlx5_rate_limit rl; 73 74 u8 rq_q_ctr_id; 75 u32 port; 76 }; 77 78 struct mlx5_ib_qp_event_work { 79 struct work_struct work; 80 struct mlx5_core_qp *qp; 81 int type; 82 }; 83 84 static struct workqueue_struct *mlx5_ib_qp_event_wq; 85 86 static void get_cqs(enum ib_qp_type qp_type, 87 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 88 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 89 90 static int is_qp0(enum ib_qp_type qp_type) 91 { 92 return qp_type == IB_QPT_SMI; 93 } 94 95 static int is_sqp(enum ib_qp_type qp_type) 96 { 97 return is_qp0(qp_type) || is_qp1(qp_type); 98 } 99 100 /** 101 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ 102 * to kernel buffer 103 * 104 * @umem: User space memory where the WQ is 105 * @buffer: buffer to copy to 106 * @buflen: buffer length 107 * @wqe_index: index of WQE to copy from 108 * @wq_offset: offset to start of WQ 109 * @wq_wqe_cnt: number of WQEs in WQ 110 * @wq_wqe_shift: log2 of WQE size 111 * @bcnt: number of bytes to copy 112 * @bytes_copied: number of bytes to copy (return value) 113 * 114 * Copies from start of WQE bcnt or less bytes. 115 * Does not gurantee to copy the entire WQE. 116 * 117 * Return: zero on success, or an error code. 118 */ 119 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer, 120 size_t buflen, int wqe_index, 121 int wq_offset, int wq_wqe_cnt, 122 int wq_wqe_shift, int bcnt, 123 size_t *bytes_copied) 124 { 125 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); 126 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); 127 size_t copy_length; 128 int ret; 129 130 /* don't copy more than requested, more than buffer length or 131 * beyond WQ end 132 */ 133 copy_length = min_t(u32, buflen, wq_end - offset); 134 copy_length = min_t(u32, copy_length, bcnt); 135 136 ret = ib_umem_copy_from(buffer, umem, offset, copy_length); 137 if (ret) 138 return ret; 139 140 if (!ret && bytes_copied) 141 *bytes_copied = copy_length; 142 143 return 0; 144 } 145 146 static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 147 void *buffer, size_t buflen, size_t *bc) 148 { 149 struct mlx5_wqe_ctrl_seg *ctrl; 150 size_t bytes_copied = 0; 151 size_t wqe_length; 152 void *p; 153 int ds; 154 155 wqe_index = wqe_index & qp->sq.fbc.sz_m1; 156 157 /* read the control segment first */ 158 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 159 ctrl = p; 160 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 161 wqe_length = ds * MLX5_WQE_DS_UNITS; 162 163 /* read rest of WQE if it spreads over more than one stride */ 164 while (bytes_copied < wqe_length) { 165 size_t copy_length = 166 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB); 167 168 if (!copy_length) 169 break; 170 171 memcpy(buffer + bytes_copied, p, copy_length); 172 bytes_copied += copy_length; 173 174 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1; 175 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); 176 } 177 *bc = bytes_copied; 178 return 0; 179 } 180 181 static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, 182 void *buffer, size_t buflen, size_t *bc) 183 { 184 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 185 struct ib_umem *umem = base->ubuffer.umem; 186 struct mlx5_ib_wq *wq = &qp->sq; 187 struct mlx5_wqe_ctrl_seg *ctrl; 188 size_t bytes_copied; 189 size_t bytes_copied2; 190 size_t wqe_length; 191 int ret; 192 int ds; 193 194 /* at first read as much as possible */ 195 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 196 wq->offset, wq->wqe_cnt, 197 wq->wqe_shift, buflen, 198 &bytes_copied); 199 if (ret) 200 return ret; 201 202 /* we need at least control segment size to proceed */ 203 if (bytes_copied < sizeof(*ctrl)) 204 return -EINVAL; 205 206 ctrl = buffer; 207 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 208 wqe_length = ds * MLX5_WQE_DS_UNITS; 209 210 /* if we copied enough then we are done */ 211 if (bytes_copied >= wqe_length) { 212 *bc = bytes_copied; 213 return 0; 214 } 215 216 /* otherwise this a wrapped around wqe 217 * so read the remaining bytes starting 218 * from wqe_index 0 219 */ 220 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied, 221 buflen - bytes_copied, 0, wq->offset, 222 wq->wqe_cnt, wq->wqe_shift, 223 wqe_length - bytes_copied, 224 &bytes_copied2); 225 226 if (ret) 227 return ret; 228 *bc = bytes_copied + bytes_copied2; 229 return 0; 230 } 231 232 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 233 size_t buflen, size_t *bc) 234 { 235 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 236 struct ib_umem *umem = base->ubuffer.umem; 237 238 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg)) 239 return -EINVAL; 240 241 if (!umem) 242 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer, 243 buflen, bc); 244 245 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc); 246 } 247 248 static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, 249 void *buffer, size_t buflen, size_t *bc) 250 { 251 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 252 struct ib_umem *umem = base->ubuffer.umem; 253 struct mlx5_ib_wq *wq = &qp->rq; 254 size_t bytes_copied; 255 int ret; 256 257 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 258 wq->offset, wq->wqe_cnt, 259 wq->wqe_shift, buflen, 260 &bytes_copied); 261 262 if (ret) 263 return ret; 264 *bc = bytes_copied; 265 return 0; 266 } 267 268 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 269 size_t buflen, size_t *bc) 270 { 271 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 272 struct ib_umem *umem = base->ubuffer.umem; 273 struct mlx5_ib_wq *wq = &qp->rq; 274 size_t wqe_size = 1 << wq->wqe_shift; 275 276 if (buflen < wqe_size) 277 return -EINVAL; 278 279 if (!umem) 280 return -EOPNOTSUPP; 281 282 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc); 283 } 284 285 static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, 286 void *buffer, size_t buflen, size_t *bc) 287 { 288 struct ib_umem *umem = srq->umem; 289 size_t bytes_copied; 290 int ret; 291 292 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0, 293 srq->msrq.max, srq->msrq.wqe_shift, 294 buflen, &bytes_copied); 295 296 if (ret) 297 return ret; 298 *bc = bytes_copied; 299 return 0; 300 } 301 302 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 303 size_t buflen, size_t *bc) 304 { 305 struct ib_umem *umem = srq->umem; 306 size_t wqe_size = 1 << srq->msrq.wqe_shift; 307 308 if (buflen < wqe_size) 309 return -EINVAL; 310 311 if (!umem) 312 return -EOPNOTSUPP; 313 314 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc); 315 } 316 317 static void mlx5_ib_qp_err_syndrome(struct ib_qp *ibqp) 318 { 319 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 320 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 321 struct mlx5_ib_qp *qp = to_mqp(ibqp); 322 void *pas_ext_union, *err_syn; 323 u32 *outb; 324 int err; 325 326 if (!MLX5_CAP_GEN(dev->mdev, qpc_extension) || 327 !MLX5_CAP_GEN(dev->mdev, qp_error_syndrome)) 328 return; 329 330 outb = kzalloc(outlen, GFP_KERNEL); 331 if (!outb) 332 return; 333 334 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen, 335 true); 336 if (err) 337 goto out; 338 339 pas_ext_union = 340 MLX5_ADDR_OF(query_qp_out, outb, qp_pas_or_qpc_ext_and_pas); 341 err_syn = MLX5_ADDR_OF(qpc_extension_and_pas_list_in, pas_ext_union, 342 qpc_data_extension.error_syndrome); 343 344 pr_err("%s/%d: QP %d error: %s (0x%x 0x%x 0x%x)\n", 345 ibqp->device->name, ibqp->port, ibqp->qp_num, 346 ib_wc_status_msg( 347 MLX5_GET(cqe_error_syndrome, err_syn, syndrome)), 348 MLX5_GET(cqe_error_syndrome, err_syn, vendor_error_syndrome), 349 MLX5_GET(cqe_error_syndrome, err_syn, hw_syndrome_type), 350 MLX5_GET(cqe_error_syndrome, err_syn, hw_error_syndrome)); 351 out: 352 kfree(outb); 353 } 354 355 static void mlx5_ib_handle_qp_event(struct work_struct *_work) 356 { 357 struct mlx5_ib_qp_event_work *qpe_work = 358 container_of(_work, struct mlx5_ib_qp_event_work, work); 359 struct ib_qp *ibqp = &to_mibqp(qpe_work->qp)->ibqp; 360 struct ib_event event = {}; 361 362 event.device = ibqp->device; 363 event.element.qp = ibqp; 364 switch (qpe_work->type) { 365 case MLX5_EVENT_TYPE_PATH_MIG: 366 event.event = IB_EVENT_PATH_MIG; 367 break; 368 case MLX5_EVENT_TYPE_COMM_EST: 369 event.event = IB_EVENT_COMM_EST; 370 break; 371 case MLX5_EVENT_TYPE_SQ_DRAINED: 372 event.event = IB_EVENT_SQ_DRAINED; 373 break; 374 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 375 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 376 break; 377 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 378 event.event = IB_EVENT_QP_FATAL; 379 break; 380 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 381 event.event = IB_EVENT_PATH_MIG_ERR; 382 break; 383 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 384 event.event = IB_EVENT_QP_REQ_ERR; 385 break; 386 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 387 event.event = IB_EVENT_QP_ACCESS_ERR; 388 break; 389 default: 390 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", 391 qpe_work->type, qpe_work->qp->qpn); 392 goto out; 393 } 394 395 if ((event.event == IB_EVENT_QP_FATAL) || 396 (event.event == IB_EVENT_QP_ACCESS_ERR)) 397 mlx5_ib_qp_err_syndrome(ibqp); 398 399 ibqp->event_handler(&event, ibqp->qp_context); 400 401 out: 402 mlx5_core_res_put(&qpe_work->qp->common); 403 kfree(qpe_work); 404 } 405 406 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 407 { 408 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 409 struct mlx5_ib_qp_event_work *qpe_work; 410 411 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 412 /* This event is only valid for trans_qps */ 413 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 414 } 415 416 if (!ibqp->event_handler) 417 goto out_no_handler; 418 419 qpe_work = kzalloc_obj(*qpe_work, GFP_ATOMIC); 420 if (!qpe_work) 421 goto out_no_handler; 422 423 qpe_work->qp = qp; 424 qpe_work->type = type; 425 INIT_WORK(&qpe_work->work, mlx5_ib_handle_qp_event); 426 queue_work(mlx5_ib_qp_event_wq, &qpe_work->work); 427 return; 428 429 out_no_handler: 430 mlx5_core_res_put(&qp->common); 431 } 432 433 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 434 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 435 { 436 int wqe_size; 437 int wq_size; 438 439 /* Sanity check RQ size before proceeding */ 440 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 441 return -EINVAL; 442 443 if (!has_rq) { 444 qp->rq.max_gs = 0; 445 qp->rq.wqe_cnt = 0; 446 qp->rq.wqe_shift = 0; 447 cap->max_recv_wr = 0; 448 cap->max_recv_sge = 0; 449 } else { 450 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE); 451 452 if (ucmd) { 453 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 454 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) 455 return -EINVAL; 456 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 457 if ((1 << qp->rq.wqe_shift) / 458 sizeof(struct mlx5_wqe_data_seg) < 459 wq_sig) 460 return -EINVAL; 461 qp->rq.max_gs = 462 (1 << qp->rq.wqe_shift) / 463 sizeof(struct mlx5_wqe_data_seg) - 464 wq_sig; 465 qp->rq.max_post = qp->rq.wqe_cnt; 466 } else { 467 wqe_size = 468 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 469 0; 470 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 471 wqe_size = roundup_pow_of_two(wqe_size); 472 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 473 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 474 qp->rq.wqe_cnt = wq_size / wqe_size; 475 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 476 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 477 wqe_size, 478 MLX5_CAP_GEN(dev->mdev, 479 max_wqe_sz_rq)); 480 return -EINVAL; 481 } 482 qp->rq.wqe_shift = ilog2(wqe_size); 483 qp->rq.max_gs = 484 (1 << qp->rq.wqe_shift) / 485 sizeof(struct mlx5_wqe_data_seg) - 486 wq_sig; 487 qp->rq.max_post = qp->rq.wqe_cnt; 488 } 489 } 490 491 return 0; 492 } 493 494 static int sq_overhead(struct ib_qp_init_attr *attr) 495 { 496 int size = 0; 497 498 switch (attr->qp_type) { 499 case IB_QPT_XRC_INI: 500 size += sizeof(struct mlx5_wqe_xrc_seg); 501 fallthrough; 502 case IB_QPT_RC: 503 size += sizeof(struct mlx5_wqe_ctrl_seg) + 504 max(sizeof(struct mlx5_wqe_atomic_seg) + 505 sizeof(struct mlx5_wqe_raddr_seg), 506 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 507 sizeof(struct mlx5_mkey_seg) + 508 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / 509 MLX5_IB_UMR_OCTOWORD); 510 break; 511 512 case IB_QPT_XRC_TGT: 513 return 0; 514 515 case IB_QPT_UC: 516 size += sizeof(struct mlx5_wqe_ctrl_seg) + 517 max(sizeof(struct mlx5_wqe_raddr_seg), 518 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 519 sizeof(struct mlx5_mkey_seg)); 520 break; 521 522 case IB_QPT_UD: 523 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 524 size += sizeof(struct mlx5_wqe_eth_pad) + 525 sizeof(struct mlx5_wqe_eth_seg); 526 fallthrough; 527 case IB_QPT_SMI: 528 case MLX5_IB_QPT_HW_GSI: 529 size += sizeof(struct mlx5_wqe_ctrl_seg) + 530 sizeof(struct mlx5_wqe_datagram_seg); 531 break; 532 533 case MLX5_IB_QPT_REG_UMR: 534 size += sizeof(struct mlx5_wqe_ctrl_seg) + 535 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 536 sizeof(struct mlx5_mkey_seg); 537 break; 538 539 default: 540 return -EINVAL; 541 } 542 543 return size; 544 } 545 546 static int calc_send_wqe(struct ib_qp_init_attr *attr) 547 { 548 int inl_size = 0; 549 int size; 550 551 size = sq_overhead(attr); 552 if (size < 0) 553 return size; 554 555 if (attr->cap.max_inline_data) { 556 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 557 attr->cap.max_inline_data; 558 } 559 560 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 561 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN && 562 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 563 return MLX5_SIG_WQE_SIZE; 564 else 565 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 566 } 567 568 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 569 { 570 int max_sge; 571 572 if (attr->qp_type == IB_QPT_RC) 573 max_sge = (min_t(int, wqe_size, 512) - 574 sizeof(struct mlx5_wqe_ctrl_seg) - 575 sizeof(struct mlx5_wqe_raddr_seg)) / 576 sizeof(struct mlx5_wqe_data_seg); 577 else if (attr->qp_type == IB_QPT_XRC_INI) 578 max_sge = (min_t(int, wqe_size, 512) - 579 sizeof(struct mlx5_wqe_ctrl_seg) - 580 sizeof(struct mlx5_wqe_xrc_seg) - 581 sizeof(struct mlx5_wqe_raddr_seg)) / 582 sizeof(struct mlx5_wqe_data_seg); 583 else 584 max_sge = (wqe_size - sq_overhead(attr)) / 585 sizeof(struct mlx5_wqe_data_seg); 586 587 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 588 sizeof(struct mlx5_wqe_data_seg)); 589 } 590 591 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 592 struct mlx5_ib_qp *qp) 593 { 594 int wqe_size; 595 int wq_size; 596 597 if (!attr->cap.max_send_wr) 598 return 0; 599 600 wqe_size = calc_send_wqe(attr); 601 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 602 if (wqe_size < 0) 603 return wqe_size; 604 605 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 606 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 607 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 608 return -EINVAL; 609 } 610 611 qp->max_inline_data = wqe_size - sq_overhead(attr) - 612 sizeof(struct mlx5_wqe_inline_seg); 613 attr->cap.max_inline_data = qp->max_inline_data; 614 615 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 616 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 617 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 618 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", 619 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, 620 qp->sq.wqe_cnt, 621 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 622 return -ENOMEM; 623 } 624 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 625 qp->sq.max_gs = get_send_sge(attr, wqe_size); 626 if (qp->sq.max_gs < attr->cap.max_send_sge) 627 return -ENOMEM; 628 629 attr->cap.max_send_sge = qp->sq.max_gs; 630 qp->sq.max_post = wq_size / wqe_size; 631 attr->cap.max_send_wr = qp->sq.max_post; 632 633 return wq_size; 634 } 635 636 static int set_user_buf_size(struct mlx5_ib_dev *dev, 637 struct mlx5_ib_qp *qp, 638 struct mlx5_ib_create_qp *ucmd, 639 struct mlx5_ib_qp_base *base, 640 struct ib_qp_init_attr *attr) 641 { 642 int desc_sz = 1 << qp->sq.wqe_shift; 643 644 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 645 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 646 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 647 return -EINVAL; 648 } 649 650 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { 651 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", 652 ucmd->sq_wqe_count); 653 return -EINVAL; 654 } 655 656 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 657 658 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 659 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 660 qp->sq.wqe_cnt, 661 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 662 return -EINVAL; 663 } 664 665 if (attr->qp_type == IB_QPT_RAW_PACKET || 666 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 667 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 668 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 669 } else { 670 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 671 (qp->sq.wqe_cnt << 6); 672 } 673 674 return 0; 675 } 676 677 static int qp_has_rq(struct ib_qp_init_attr *attr) 678 { 679 if (attr->qp_type == IB_QPT_XRC_INI || 680 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 681 attr->qp_type == MLX5_IB_QPT_REG_UMR || 682 !attr->cap.max_recv_wr) 683 return 0; 684 685 return 1; 686 } 687 688 enum { 689 /* this is the first blue flame register in the array of bfregs assigned 690 * to a processes. Since we do not use it for blue flame but rather 691 * regular 64 bit doorbells, we do not need a lock for maintaiing 692 * "odd/even" order 693 */ 694 NUM_NON_BLUE_FLAME_BFREGS = 1, 695 }; 696 697 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 698 { 699 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 700 bfregi->num_static_sys_pages * MLX5_NON_FP_BFREGS_PER_UAR; 701 } 702 703 static int num_med_bfreg(struct mlx5_ib_dev *dev, 704 struct mlx5_bfreg_info *bfregi) 705 { 706 int n; 707 708 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 709 NUM_NON_BLUE_FLAME_BFREGS; 710 711 return n >= 0 ? n : 0; 712 } 713 714 static int first_med_bfreg(struct mlx5_ib_dev *dev, 715 struct mlx5_bfreg_info *bfregi) 716 { 717 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 718 } 719 720 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 721 struct mlx5_bfreg_info *bfregi) 722 { 723 int med; 724 725 med = num_med_bfreg(dev, bfregi); 726 return ++med; 727 } 728 729 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 730 struct mlx5_bfreg_info *bfregi) 731 { 732 int i; 733 734 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 735 if (!bfregi->count[i]) { 736 bfregi->count[i]++; 737 return i; 738 } 739 } 740 741 return -ENOMEM; 742 } 743 744 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 745 struct mlx5_bfreg_info *bfregi) 746 { 747 int minidx = first_med_bfreg(dev, bfregi); 748 int i; 749 750 if (minidx < 0) 751 return minidx; 752 753 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 754 if (bfregi->count[i] < bfregi->count[minidx]) 755 minidx = i; 756 if (!bfregi->count[minidx]) 757 break; 758 } 759 760 bfregi->count[minidx]++; 761 return minidx; 762 } 763 764 static int alloc_bfreg(struct mlx5_ib_dev *dev, 765 struct mlx5_bfreg_info *bfregi) 766 { 767 int bfregn = -ENOMEM; 768 769 if (bfregi->lib_uar_dyn) 770 return -EINVAL; 771 772 mutex_lock(&bfregi->lock); 773 if (bfregi->ver >= 2) { 774 bfregn = alloc_high_class_bfreg(dev, bfregi); 775 if (bfregn < 0) 776 bfregn = alloc_med_class_bfreg(dev, bfregi); 777 } 778 779 if (bfregn < 0) { 780 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 781 bfregn = 0; 782 bfregi->count[bfregn]++; 783 } 784 mutex_unlock(&bfregi->lock); 785 786 return bfregn; 787 } 788 789 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 790 { 791 mutex_lock(&bfregi->lock); 792 bfregi->count[bfregn]--; 793 mutex_unlock(&bfregi->lock); 794 } 795 796 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 797 { 798 switch (state) { 799 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 800 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 801 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 802 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 803 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 804 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 805 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 806 default: return -1; 807 } 808 } 809 810 static int to_mlx5_st(enum ib_qp_type type) 811 { 812 switch (type) { 813 case IB_QPT_RC: return MLX5_QP_ST_RC; 814 case IB_QPT_UC: return MLX5_QP_ST_UC; 815 case IB_QPT_UD: return MLX5_QP_ST_UD; 816 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 817 case IB_QPT_XRC_INI: 818 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 819 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 820 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 821 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; 822 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE; 823 default: return -EINVAL; 824 } 825 } 826 827 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 828 struct mlx5_ib_cq *recv_cq); 829 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 830 struct mlx5_ib_cq *recv_cq); 831 832 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 833 struct mlx5_bfreg_info *bfregi, u32 bfregn, 834 bool dyn_bfreg) 835 { 836 unsigned int bfregs_per_sys_page; 837 u32 index_of_sys_page; 838 u32 offset; 839 840 if (bfregi->lib_uar_dyn) 841 return -EINVAL; 842 843 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 844 MLX5_NON_FP_BFREGS_PER_UAR; 845 index_of_sys_page = bfregn / bfregs_per_sys_page; 846 847 if (dyn_bfreg) { 848 index_of_sys_page += bfregi->num_static_sys_pages; 849 850 if (index_of_sys_page >= bfregi->num_sys_pages) 851 return -EINVAL; 852 853 if (bfregn > bfregi->num_dyn_bfregs || 854 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 855 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 856 return -EINVAL; 857 } 858 } 859 860 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 861 return bfregi->sys_pages[index_of_sys_page] + offset; 862 } 863 864 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 865 struct mlx5_ib_rwq *rwq, struct ib_udata *udata) 866 { 867 struct mlx5_ib_ucontext *context = 868 rdma_udata_to_drv_context( 869 udata, 870 struct mlx5_ib_ucontext, 871 ibucontext); 872 873 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) 874 atomic_dec(&dev->delay_drop.rqs_cnt); 875 876 mlx5_ib_db_unmap_user(context, &rwq->db); 877 ib_umem_release(rwq->umem); 878 } 879 880 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 881 struct ib_udata *udata, struct mlx5_ib_rwq *rwq, 882 struct mlx5_ib_create_wq *ucmd) 883 { 884 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 885 udata, struct mlx5_ib_ucontext, ibucontext); 886 unsigned long page_size = 0; 887 u32 offset = 0; 888 int err; 889 890 if (!ucmd->buf_addr) 891 return -EINVAL; 892 893 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0); 894 if (IS_ERR(rwq->umem)) { 895 mlx5_ib_dbg(dev, "umem_get failed\n"); 896 err = PTR_ERR(rwq->umem); 897 return err; 898 } 899 900 page_size = mlx5_umem_find_best_quantized_pgoff( 901 rwq->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 902 page_offset, 64, &rwq->rq_page_offset); 903 if (!page_size) { 904 mlx5_ib_warn(dev, "bad offset\n"); 905 err = -EINVAL; 906 goto err_umem; 907 } 908 909 rwq->rq_num_pas = ib_umem_num_dma_blocks(rwq->umem, page_size); 910 rwq->page_shift = order_base_2(page_size); 911 rwq->log_page_size = rwq->page_shift - MLX5_ADAPTER_PAGE_SHIFT; 912 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 913 914 mlx5_ib_dbg( 915 dev, 916 "addr 0x%llx, size %zd, npages %zu, page_size %ld, ncont %d, offset %d\n", 917 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 918 ib_umem_num_pages(rwq->umem), page_size, rwq->rq_num_pas, 919 offset); 920 921 err = mlx5_ib_db_map_user(ucontext, ucmd->db_addr, &rwq->db); 922 if (err) { 923 mlx5_ib_dbg(dev, "map failed\n"); 924 goto err_umem; 925 } 926 927 return 0; 928 929 err_umem: 930 ib_umem_release(rwq->umem); 931 return err; 932 } 933 934 static int adjust_bfregn(struct mlx5_ib_dev *dev, 935 struct mlx5_bfreg_info *bfregi, int bfregn) 936 { 937 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 938 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 939 } 940 941 static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 942 struct mlx5_ib_qp *qp, struct ib_udata *udata, 943 struct ib_qp_init_attr *attr, u32 **in, 944 struct mlx5_ib_create_qp_resp *resp, int *inlen, 945 struct mlx5_ib_qp_base *base, 946 struct mlx5_ib_create_qp *ucmd) 947 { 948 struct mlx5_ib_ucontext *context; 949 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 950 unsigned int page_offset_quantized = 0; 951 unsigned long page_size = 0; 952 int uar_index = 0; 953 int bfregn; 954 int ncont = 0; 955 __be64 *pas; 956 void *qpc; 957 int err; 958 u16 uid; 959 u32 uar_flags; 960 961 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, 962 ibucontext); 963 uar_flags = qp->flags_en & 964 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX); 965 switch (uar_flags) { 966 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 967 uar_index = ucmd->bfreg_index; 968 bfregn = MLX5_IB_INVALID_BFREG; 969 break; 970 case MLX5_QP_FLAG_BFREG_INDEX: 971 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 972 ucmd->bfreg_index, true); 973 if (uar_index < 0) 974 return uar_index; 975 bfregn = MLX5_IB_INVALID_BFREG; 976 break; 977 case 0: 978 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 979 return -EINVAL; 980 bfregn = alloc_bfreg(dev, &context->bfregi); 981 if (bfregn < 0) 982 return bfregn; 983 break; 984 default: 985 return -EINVAL; 986 } 987 988 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 989 if (bfregn != MLX5_IB_INVALID_BFREG) 990 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 991 false); 992 993 qp->rq.offset = 0; 994 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 995 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 996 997 err = set_user_buf_size(dev, qp, ucmd, base, attr); 998 if (err) 999 goto err_bfreg; 1000 1001 if (ucmd->buf_addr && ubuffer->buf_size) { 1002 ubuffer->buf_addr = ucmd->buf_addr; 1003 ubuffer->umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 1004 ubuffer->buf_size, 0); 1005 if (IS_ERR(ubuffer->umem)) { 1006 err = PTR_ERR(ubuffer->umem); 1007 goto err_bfreg; 1008 } 1009 page_size = mlx5_umem_find_best_quantized_pgoff( 1010 ubuffer->umem, qpc, log_page_size, 1011 MLX5_ADAPTER_PAGE_SHIFT, page_offset, 64, 1012 &page_offset_quantized); 1013 if (!page_size) { 1014 err = -EINVAL; 1015 goto err_umem; 1016 } 1017 ncont = ib_umem_num_dma_blocks(ubuffer->umem, page_size); 1018 } else { 1019 ubuffer->umem = NULL; 1020 } 1021 1022 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1023 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 1024 *in = kvzalloc(*inlen, GFP_KERNEL); 1025 if (!*in) { 1026 err = -ENOMEM; 1027 goto err_umem; 1028 } 1029 1030 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 1031 MLX5_SET(create_qp_in, *in, uid, uid); 1032 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1033 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 1034 if (ubuffer->umem) { 1035 mlx5_ib_populate_pas(ubuffer->umem, page_size, pas, 0); 1036 MLX5_SET(qpc, qpc, log_page_size, 1037 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1038 MLX5_SET(qpc, qpc, page_offset, page_offset_quantized); 1039 } 1040 MLX5_SET(qpc, qpc, uar_page, uar_index); 1041 if (bfregn != MLX5_IB_INVALID_BFREG) 1042 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 1043 else 1044 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 1045 qp->bfregn = bfregn; 1046 1047 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &qp->db); 1048 if (err) { 1049 mlx5_ib_dbg(dev, "map failed\n"); 1050 goto err_free; 1051 } 1052 1053 return 0; 1054 1055 err_free: 1056 kvfree(*in); 1057 1058 err_umem: 1059 ib_umem_release(ubuffer->umem); 1060 1061 err_bfreg: 1062 if (bfregn != MLX5_IB_INVALID_BFREG) 1063 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 1064 return err; 1065 } 1066 1067 static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1068 struct mlx5_ib_qp_base *base, struct ib_udata *udata) 1069 { 1070 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1071 udata, struct mlx5_ib_ucontext, ibucontext); 1072 1073 if (udata) { 1074 /* User QP */ 1075 mlx5_ib_db_unmap_user(context, &qp->db); 1076 ib_umem_release(base->ubuffer.umem); 1077 1078 /* 1079 * Free only the BFREGs which are handled by the kernel. 1080 * BFREGs of UARs allocated dynamically are handled by user. 1081 */ 1082 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 1083 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 1084 return; 1085 } 1086 1087 /* Kernel QP */ 1088 kvfree(qp->sq.wqe_head); 1089 kvfree(qp->sq.w_list); 1090 kvfree(qp->sq.wrid); 1091 kvfree(qp->sq.wr_data); 1092 kvfree(qp->rq.wrid); 1093 if (qp->db.db) 1094 mlx5_db_free(dev->mdev, &qp->db); 1095 if (qp->buf.frags) 1096 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1097 } 1098 1099 static int _create_kernel_qp(struct mlx5_ib_dev *dev, 1100 struct ib_qp_init_attr *init_attr, 1101 struct mlx5_ib_qp *qp, u32 **in, int *inlen, 1102 struct mlx5_ib_qp_base *base) 1103 { 1104 int uar_index; 1105 void *qpc; 1106 int err; 1107 1108 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 1109 qp->bf.bfreg = &dev->fp_bfreg; 1110 else 1111 qp->bf.bfreg = &dev->bfreg; 1112 1113 /* We need to divide by two since each register is comprised of 1114 * two buffers of identical size, namely odd and even 1115 */ 1116 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 1117 uar_index = qp->bf.bfreg->index; 1118 1119 err = calc_sq_size(dev, init_attr, qp); 1120 if (err < 0) { 1121 mlx5_ib_dbg(dev, "err %d\n", err); 1122 return err; 1123 } 1124 1125 qp->rq.offset = 0; 1126 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 1127 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 1128 1129 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, 1130 &qp->buf, dev->mdev->priv.numa_node); 1131 if (err) { 1132 mlx5_ib_dbg(dev, "err %d\n", err); 1133 return err; 1134 } 1135 1136 if (qp->rq.wqe_cnt) 1137 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, 1138 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); 1139 1140 if (qp->sq.wqe_cnt) { 1141 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / 1142 MLX5_SEND_WQE_BB; 1143 mlx5_init_fbc_offset(qp->buf.frags + 1144 (qp->sq.offset / PAGE_SIZE), 1145 ilog2(MLX5_SEND_WQE_BB), 1146 ilog2(qp->sq.wqe_cnt), 1147 sq_strides_offset, &qp->sq.fbc); 1148 1149 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 1150 } 1151 1152 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 1153 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 1154 *in = kvzalloc(*inlen, GFP_KERNEL); 1155 if (!*in) { 1156 err = -ENOMEM; 1157 goto err_buf; 1158 } 1159 1160 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 1161 MLX5_SET(qpc, qpc, uar_page, uar_index); 1162 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 1163 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1164 1165 /* Set "fast registration enabled" for all kernel QPs */ 1166 MLX5_SET(qpc, qpc, fre, 1); 1167 MLX5_SET(qpc, qpc, rlky, 1); 1168 1169 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 1170 MLX5_SET(qpc, qpc, deth_sqpn, 1); 1171 1172 mlx5_fill_page_frag_array(&qp->buf, 1173 (__be64 *)MLX5_ADDR_OF(create_qp_in, 1174 *in, pas)); 1175 1176 err = mlx5_db_alloc(dev->mdev, &qp->db); 1177 if (err) { 1178 mlx5_ib_dbg(dev, "err %d\n", err); 1179 goto err_free; 1180 } 1181 1182 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1183 sizeof(*qp->sq.wrid), GFP_KERNEL); 1184 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, 1185 sizeof(*qp->sq.wr_data), GFP_KERNEL); 1186 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1187 sizeof(*qp->rq.wrid), GFP_KERNEL); 1188 qp->sq.w_list = kvmalloc_objs(*qp->sq.w_list, qp->sq.wqe_cnt); 1189 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, 1190 sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1191 1192 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1193 !qp->sq.w_list || !qp->sq.wqe_head) { 1194 err = -ENOMEM; 1195 goto err_wrid; 1196 } 1197 1198 return 0; 1199 1200 err_wrid: 1201 kvfree(qp->sq.wqe_head); 1202 kvfree(qp->sq.w_list); 1203 kvfree(qp->sq.wrid); 1204 kvfree(qp->sq.wr_data); 1205 kvfree(qp->rq.wrid); 1206 mlx5_db_free(dev->mdev, &qp->db); 1207 1208 err_free: 1209 kvfree(*in); 1210 1211 err_buf: 1212 mlx5_frag_buf_free(dev->mdev, &qp->buf); 1213 return err; 1214 } 1215 1216 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1217 { 1218 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) || 1219 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI)) 1220 return MLX5_SRQ_RQ; 1221 else if (!qp->has_rq) 1222 return MLX5_ZERO_LEN_RQ; 1223 1224 return MLX5_NON_ZERO_RQ; 1225 } 1226 1227 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1228 struct mlx5_ib_qp *qp, 1229 struct mlx5_ib_sq *sq, u32 tdn, 1230 struct ib_pd *pd) 1231 { 1232 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 1233 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1234 1235 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1236 MLX5_SET(tisc, tisc, transport_domain, tdn); 1237 if (!mlx5_ib_lag_should_assign_affinity(dev) && 1238 mlx5_lag_is_lacp_owner(dev->mdev)) 1239 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1); 1240 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 1241 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); 1242 1243 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn); 1244 } 1245 1246 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1247 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1248 { 1249 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1250 } 1251 1252 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq) 1253 { 1254 if (sq->flow_rule) 1255 mlx5_del_flow_rules(sq->flow_rule); 1256 sq->flow_rule = NULL; 1257 } 1258 1259 static bool fr_supported(int ts_cap) 1260 { 1261 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING || 1262 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1263 } 1264 1265 static int get_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1266 bool fr_sup, bool rt_sup) 1267 { 1268 if (cq->private_flags & MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS) { 1269 if (!rt_sup) { 1270 mlx5_ib_dbg(dev, 1271 "Real time TS format is not supported\n"); 1272 return -EOPNOTSUPP; 1273 } 1274 return MLX5_TIMESTAMP_FORMAT_REAL_TIME; 1275 } 1276 if (cq->private_flags & MLX5_IB_CQ_PR_TIMESTAMP_COMPLETION) { 1277 if (!fr_sup) { 1278 mlx5_ib_dbg(dev, 1279 "Free running TS format is not supported\n"); 1280 return -EOPNOTSUPP; 1281 } 1282 return MLX5_TIMESTAMP_FORMAT_FREE_RUNNING; 1283 } 1284 return fr_sup ? MLX5_TIMESTAMP_FORMAT_FREE_RUNNING : 1285 MLX5_TIMESTAMP_FORMAT_DEFAULT; 1286 } 1287 1288 static int get_rq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *recv_cq) 1289 { 1290 u8 ts_cap = MLX5_CAP_GEN(dev->mdev, rq_ts_format); 1291 1292 return get_ts_format(dev, recv_cq, fr_supported(ts_cap), 1293 rt_supported(ts_cap)); 1294 } 1295 1296 static int get_sq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq) 1297 { 1298 u8 ts_cap = MLX5_CAP_GEN(dev->mdev, sq_ts_format); 1299 1300 return get_ts_format(dev, send_cq, fr_supported(ts_cap), 1301 rt_supported(ts_cap)); 1302 } 1303 1304 static int get_qp_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq, 1305 struct mlx5_ib_cq *recv_cq) 1306 { 1307 u8 ts_cap = MLX5_CAP_ROCE(dev->mdev, qp_ts_format); 1308 bool fr_sup = fr_supported(ts_cap); 1309 bool rt_sup = rt_supported(ts_cap); 1310 u8 default_ts = fr_sup ? MLX5_TIMESTAMP_FORMAT_FREE_RUNNING : 1311 MLX5_TIMESTAMP_FORMAT_DEFAULT; 1312 int send_ts_format = 1313 send_cq ? get_ts_format(dev, send_cq, fr_sup, rt_sup) : 1314 default_ts; 1315 int recv_ts_format = 1316 recv_cq ? get_ts_format(dev, recv_cq, fr_sup, rt_sup) : 1317 default_ts; 1318 1319 if (send_ts_format < 0 || recv_ts_format < 0) 1320 return -EOPNOTSUPP; 1321 1322 if (send_ts_format != MLX5_TIMESTAMP_FORMAT_DEFAULT && 1323 recv_ts_format != MLX5_TIMESTAMP_FORMAT_DEFAULT && 1324 send_ts_format != recv_ts_format) { 1325 mlx5_ib_dbg( 1326 dev, 1327 "The send ts_format does not match the receive ts_format\n"); 1328 return -EOPNOTSUPP; 1329 } 1330 1331 return send_ts_format == default_ts ? recv_ts_format : send_ts_format; 1332 } 1333 1334 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1335 struct ib_udata *udata, 1336 struct mlx5_ib_sq *sq, void *qpin, 1337 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1338 { 1339 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1340 __be64 *pas; 1341 void *in; 1342 void *sqc; 1343 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1344 void *wq; 1345 int inlen; 1346 int err; 1347 unsigned int page_offset_quantized; 1348 unsigned long page_size; 1349 int ts_format; 1350 1351 ts_format = get_sq_ts_format(dev, cq); 1352 if (ts_format < 0) 1353 return ts_format; 1354 1355 sq->ubuffer.umem = ib_umem_get(&dev->ib_dev, ubuffer->buf_addr, 1356 ubuffer->buf_size, 0); 1357 if (IS_ERR(sq->ubuffer.umem)) 1358 return PTR_ERR(sq->ubuffer.umem); 1359 page_size = mlx5_umem_find_best_quantized_pgoff( 1360 ubuffer->umem, wq, log_wq_pg_sz, MLX5_ADAPTER_PAGE_SHIFT, 1361 page_offset, 64, &page_offset_quantized); 1362 if (!page_size) { 1363 err = -EINVAL; 1364 goto err_umem; 1365 } 1366 1367 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1368 sizeof(u64) * 1369 ib_umem_num_dma_blocks(sq->ubuffer.umem, page_size); 1370 in = kvzalloc(inlen, GFP_KERNEL); 1371 if (!in) { 1372 err = -ENOMEM; 1373 goto err_umem; 1374 } 1375 1376 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1377 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1378 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1379 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1380 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1381 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1382 MLX5_SET(sqc, sqc, ts_format, ts_format); 1383 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1384 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1385 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1386 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1387 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1388 MLX5_CAP_ETH(dev->mdev, swp)) 1389 MLX5_SET(sqc, sqc, allow_swp, 1); 1390 1391 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1392 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1393 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1394 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1395 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1396 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1397 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1398 MLX5_SET(wq, wq, log_wq_pg_sz, 1399 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1400 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1401 1402 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1403 mlx5_ib_populate_pas(sq->ubuffer.umem, page_size, pas, 0); 1404 1405 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp); 1406 1407 kvfree(in); 1408 1409 if (err) 1410 goto err_umem; 1411 1412 return 0; 1413 1414 err_umem: 1415 ib_umem_release(sq->ubuffer.umem); 1416 sq->ubuffer.umem = NULL; 1417 1418 return err; 1419 } 1420 1421 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1422 struct mlx5_ib_sq *sq) 1423 { 1424 destroy_flow_rule_vport_sq(sq); 1425 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp); 1426 ib_umem_release(sq->ubuffer.umem); 1427 } 1428 1429 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1430 struct mlx5_ib_rq *rq, void *qpin, 1431 struct ib_pd *pd, struct mlx5_ib_cq *cq) 1432 { 1433 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1434 __be64 *pas; 1435 void *in; 1436 void *rqc; 1437 void *wq; 1438 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1439 struct ib_umem *umem = rq->base.ubuffer.umem; 1440 unsigned int page_offset_quantized; 1441 unsigned long page_size = 0; 1442 int ts_format; 1443 size_t inlen; 1444 int err; 1445 1446 ts_format = get_rq_ts_format(dev, cq); 1447 if (ts_format < 0) 1448 return ts_format; 1449 1450 page_size = mlx5_umem_find_best_quantized_pgoff(umem, wq, log_wq_pg_sz, 1451 MLX5_ADAPTER_PAGE_SHIFT, 1452 page_offset, 64, 1453 &page_offset_quantized); 1454 if (!page_size) 1455 return -EINVAL; 1456 1457 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1458 sizeof(u64) * ib_umem_num_dma_blocks(umem, page_size); 1459 in = kvzalloc(inlen, GFP_KERNEL); 1460 if (!in) 1461 return -ENOMEM; 1462 1463 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1464 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1465 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) 1466 MLX5_SET(rqc, rqc, vsd, 1); 1467 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 1468 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1469 MLX5_SET(rqc, rqc, ts_format, ts_format); 1470 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1471 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1472 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1473 1474 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS) 1475 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1476 1477 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1478 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1479 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) 1480 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1481 MLX5_SET(wq, wq, page_offset, page_offset_quantized); 1482 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1483 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1484 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1485 MLX5_SET(wq, wq, log_wq_pg_sz, 1486 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT); 1487 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1488 1489 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1490 mlx5_ib_populate_pas(umem, page_size, pas, 0); 1491 1492 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp); 1493 1494 kvfree(in); 1495 1496 return err; 1497 } 1498 1499 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1500 struct mlx5_ib_rq *rq) 1501 { 1502 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp); 1503 } 1504 1505 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1506 struct mlx5_ib_rq *rq, 1507 u32 qp_flags_en, 1508 struct ib_pd *pd) 1509 { 1510 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1511 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1512 mlx5_ib_disable_lb(dev, false, true); 1513 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1514 } 1515 1516 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1517 struct mlx5_ib_rq *rq, u32 tdn, 1518 u32 *qp_flags_en, struct ib_pd *pd, 1519 u32 *out) 1520 { 1521 u8 lb_flag = 0; 1522 u32 *in; 1523 void *tirc; 1524 int inlen; 1525 int err; 1526 1527 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1528 in = kvzalloc(inlen, GFP_KERNEL); 1529 if (!in) 1530 return -ENOMEM; 1531 1532 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1533 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1534 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1535 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1536 MLX5_SET(tirc, tirc, transport_domain, tdn); 1537 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1538 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1539 1540 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1541 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1542 1543 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1544 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1545 1546 if (dev->is_rep) { 1547 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1548 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1549 } 1550 1551 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1552 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1553 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1554 rq->tirn = MLX5_GET(create_tir_out, out, tirn); 1555 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1556 err = mlx5_ib_enable_lb(dev, false, true); 1557 1558 if (err) 1559 destroy_raw_packet_qp_tir(dev, rq, 0, pd); 1560 } 1561 kvfree(in); 1562 1563 return err; 1564 } 1565 1566 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1567 u32 *in, size_t inlen, struct ib_pd *pd, 1568 struct ib_udata *udata, 1569 struct mlx5_ib_create_qp_resp *resp, 1570 struct ib_qp_init_attr *init_attr) 1571 { 1572 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1573 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1574 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1575 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1576 udata, struct mlx5_ib_ucontext, ibucontext); 1577 int err; 1578 u32 tdn = mucontext->tdn; 1579 u16 uid = to_mpd(pd)->uid; 1580 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; 1581 1582 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt) 1583 return -EINVAL; 1584 if (qp->sq.wqe_cnt) { 1585 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); 1586 if (err) 1587 return err; 1588 1589 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd, 1590 to_mcq(init_attr->send_cq)); 1591 if (err) 1592 goto err_destroy_tis; 1593 1594 if (uid) { 1595 resp->tisn = sq->tisn; 1596 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; 1597 resp->sqn = sq->base.mqp.qpn; 1598 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; 1599 } 1600 1601 sq->base.container_mibqp = qp; 1602 sq->base.mqp.event = mlx5_ib_qp_event; 1603 } 1604 1605 if (qp->rq.wqe_cnt) { 1606 rq->base.container_mibqp = qp; 1607 1608 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING) 1609 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; 1610 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) 1611 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; 1612 err = create_raw_packet_qp_rq(dev, rq, in, pd, 1613 to_mcq(init_attr->recv_cq)); 1614 if (err) 1615 goto err_destroy_sq; 1616 1617 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd, 1618 out); 1619 if (err) 1620 goto err_destroy_rq; 1621 1622 if (uid) { 1623 resp->rqn = rq->base.mqp.qpn; 1624 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; 1625 resp->tirn = rq->tirn; 1626 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1627 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1628 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1629 resp->tir_icm_addr = MLX5_GET( 1630 create_tir_out, out, icm_address_31_0); 1631 resp->tir_icm_addr |= 1632 (u64)MLX5_GET(create_tir_out, out, 1633 icm_address_39_32) 1634 << 32; 1635 resp->tir_icm_addr |= 1636 (u64)MLX5_GET(create_tir_out, out, 1637 icm_address_63_40) 1638 << 40; 1639 resp->comp_mask |= 1640 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1641 } 1642 } 1643 } 1644 1645 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1646 rq->base.mqp.qpn; 1647 return 0; 1648 1649 err_destroy_rq: 1650 destroy_raw_packet_qp_rq(dev, rq); 1651 err_destroy_sq: 1652 if (!qp->sq.wqe_cnt) 1653 return err; 1654 destroy_raw_packet_qp_sq(dev, sq); 1655 err_destroy_tis: 1656 destroy_raw_packet_qp_tis(dev, sq, pd); 1657 1658 return err; 1659 } 1660 1661 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1662 struct mlx5_ib_qp *qp) 1663 { 1664 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1665 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1666 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1667 1668 if (qp->rq.wqe_cnt) { 1669 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); 1670 destroy_raw_packet_qp_rq(dev, rq); 1671 } 1672 1673 if (qp->sq.wqe_cnt) { 1674 destroy_raw_packet_qp_sq(dev, sq); 1675 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1676 } 1677 } 1678 1679 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1680 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1681 { 1682 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1683 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1684 1685 sq->sq = &qp->sq; 1686 rq->rq = &qp->rq; 1687 sq->doorbell = &qp->db; 1688 rq->doorbell = &qp->db; 1689 } 1690 1691 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1692 { 1693 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 1694 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) 1695 mlx5_ib_disable_lb(dev, false, true); 1696 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1697 to_mpd(qp->ibqp.pd)->uid); 1698 } 1699 1700 struct mlx5_create_qp_params { 1701 struct ib_udata *udata; 1702 size_t inlen; 1703 size_t outlen; 1704 size_t ucmd_size; 1705 void *ucmd; 1706 u8 is_rss_raw : 1; 1707 struct ib_qp_init_attr *attr; 1708 u32 uidx; 1709 struct mlx5_ib_create_qp_resp resp; 1710 }; 1711 1712 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1713 struct mlx5_ib_qp *qp, 1714 struct mlx5_create_qp_params *params) 1715 { 1716 struct ib_qp_init_attr *init_attr = params->attr; 1717 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd; 1718 struct ib_udata *udata = params->udata; 1719 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( 1720 udata, struct mlx5_ib_ucontext, ibucontext); 1721 int inlen; 1722 int outlen; 1723 int err; 1724 u32 *in; 1725 u32 *out; 1726 void *tirc; 1727 void *hfso; 1728 u32 selected_fields = 0; 1729 u32 outer_l4; 1730 u32 tdn = mucontext->tdn; 1731 u8 lb_flag = 0; 1732 1733 if (ucmd->comp_mask) { 1734 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1735 return -EOPNOTSUPP; 1736 } 1737 1738 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER && 1739 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { 1740 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); 1741 return -EOPNOTSUPP; 1742 } 1743 1744 if (dev->is_rep) 1745 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; 1746 1747 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) 1748 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 1749 1750 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) 1751 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 1752 1753 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1754 outlen = MLX5_ST_SZ_BYTES(create_tir_out); 1755 in = kvzalloc(inlen + outlen, GFP_KERNEL); 1756 if (!in) 1757 return -ENOMEM; 1758 1759 out = in + MLX5_ST_SZ_DW(create_tir_in); 1760 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1761 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 1762 MLX5_SET(tirc, tirc, disp_type, 1763 MLX5_TIRC_DISP_TYPE_INDIRECT); 1764 MLX5_SET(tirc, tirc, indirect_table, 1765 init_attr->rwq_ind_tbl->ind_tbl_num); 1766 MLX5_SET(tirc, tirc, transport_domain, tdn); 1767 1768 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1769 1770 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) 1771 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 1772 1773 MLX5_SET(tirc, tirc, self_lb_block, lb_flag); 1774 1775 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER) 1776 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 1777 else 1778 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1779 1780 switch (ucmd->rx_hash_function) { 1781 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1782 { 1783 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1784 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1785 1786 if (len != ucmd->rx_key_len) { 1787 err = -EINVAL; 1788 goto err; 1789 } 1790 1791 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); 1792 memcpy(rss_key, ucmd->rx_hash_key, len); 1793 break; 1794 } 1795 default: 1796 err = -EOPNOTSUPP; 1797 goto err; 1798 } 1799 1800 if (!ucmd->rx_hash_fields_mask) { 1801 /* special case when this TIR serves as steering entry without hashing */ 1802 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1803 goto create_tir; 1804 err = -EINVAL; 1805 goto err; 1806 } 1807 1808 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1809 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1810 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1811 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1812 err = -EINVAL; 1813 goto err; 1814 } 1815 1816 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1817 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1818 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1819 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1820 MLX5_L3_PROT_TYPE_IPV4); 1821 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1822 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1823 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1824 MLX5_L3_PROT_TYPE_IPV6); 1825 1826 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1827 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1828 << 0 | 1829 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1830 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1831 << 1 | 1832 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; 1833 1834 /* Check that only one l4 protocol is set */ 1835 if (outer_l4 & (outer_l4 - 1)) { 1836 err = -EINVAL; 1837 goto err; 1838 } 1839 1840 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1841 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1842 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1843 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1844 MLX5_L4_PROT_TYPE_TCP); 1845 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1846 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1847 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1848 MLX5_L4_PROT_TYPE_UDP); 1849 1850 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1851 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1852 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1853 1854 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1855 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1856 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1857 1858 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1859 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1860 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1861 1862 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1863 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1864 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1865 1866 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) 1867 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; 1868 1869 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1870 1871 create_tir: 1872 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1873 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out); 1874 1875 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn); 1876 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { 1877 err = mlx5_ib_enable_lb(dev, false, true); 1878 1879 if (err) 1880 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1881 to_mpd(pd)->uid); 1882 } 1883 1884 if (err) 1885 goto err; 1886 1887 if (mucontext->devx_uid) { 1888 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; 1889 params->resp.tirn = qp->rss_qp.tirn; 1890 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) || 1891 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) { 1892 params->resp.tir_icm_addr = 1893 MLX5_GET(create_tir_out, out, icm_address_31_0); 1894 params->resp.tir_icm_addr |= 1895 (u64)MLX5_GET(create_tir_out, out, 1896 icm_address_39_32) 1897 << 32; 1898 params->resp.tir_icm_addr |= 1899 (u64)MLX5_GET(create_tir_out, out, 1900 icm_address_63_40) 1901 << 40; 1902 params->resp.comp_mask |= 1903 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; 1904 } 1905 } 1906 1907 kvfree(in); 1908 /* qpn is reserved for that QP */ 1909 qp->trans_qp.base.mqp.qpn = 0; 1910 qp->is_rss = true; 1911 return 0; 1912 1913 err: 1914 kvfree(in); 1915 return err; 1916 } 1917 1918 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, 1919 struct mlx5_ib_qp *qp, 1920 struct ib_qp_init_attr *init_attr, 1921 void *qpc) 1922 { 1923 int scqe_sz; 1924 bool allow_scat_cqe = false; 1925 1926 allow_scat_cqe = qp->flags_en & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; 1927 1928 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) 1929 return; 1930 1931 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); 1932 if (scqe_sz == 128) { 1933 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1934 return; 1935 } 1936 1937 if (init_attr->qp_type != MLX5_IB_QPT_DCI || 1938 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) 1939 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1940 } 1941 1942 static int atomic_size_to_mode(int size_mask) 1943 { 1944 /* driver does not support atomic_size > 256B 1945 * and does not know how to translate bigger sizes 1946 */ 1947 int supported_size_mask = size_mask & 0x1ff; 1948 int log_max_size; 1949 1950 if (!supported_size_mask) 1951 return -EOPNOTSUPP; 1952 1953 log_max_size = __fls(supported_size_mask); 1954 1955 if (log_max_size > 3) 1956 return log_max_size; 1957 1958 return MLX5_ATOMIC_MODE_8B; 1959 } 1960 1961 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1962 struct mlx5_ib_qp *qp) 1963 { 1964 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1965 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1966 int atomic_mode = -EOPNOTSUPP; 1967 int atomic_size_mask; 1968 1969 if (!atomic) 1970 return -EOPNOTSUPP; 1971 1972 if (qp->type == MLX5_IB_QPT_DCT) 1973 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1974 else 1975 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1976 1977 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || 1978 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) 1979 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1980 1981 if (atomic_mode <= 0 && 1982 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1983 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1984 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1985 1986 /* OOO DP QPs do not support larger than 8-Bytes atomic operations */ 1987 if (atomic_mode > MLX5_ATOMIC_MODE_8B && qp->is_ooo_rq) 1988 atomic_mode = MLX5_ATOMIC_MODE_8B; 1989 1990 return atomic_mode; 1991 } 1992 1993 static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1994 struct mlx5_create_qp_params *params) 1995 { 1996 struct ib_qp_init_attr *attr = params->attr; 1997 u32 uidx = params->uidx; 1998 struct mlx5_ib_resources *devr = &dev->devr; 1999 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2000 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2001 struct mlx5_core_dev *mdev = dev->mdev; 2002 struct mlx5_ib_qp_base *base; 2003 unsigned long flags; 2004 void *qpc; 2005 u32 *in; 2006 int err; 2007 2008 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2009 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2010 2011 in = kvzalloc(inlen, GFP_KERNEL); 2012 if (!in) 2013 return -ENOMEM; 2014 2015 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2016 2017 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC); 2018 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2019 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn); 2020 2021 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2022 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2023 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2024 MLX5_SET(qpc, qpc, cd_master, 1); 2025 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2026 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2027 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 2028 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2029 2030 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 2031 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ); 2032 MLX5_SET(qpc, qpc, no_sq, 1); 2033 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2034 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 2035 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2036 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn); 2037 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2038 2039 /* 0xffffff means we ask to work with cqe version 0 */ 2040 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2041 MLX5_SET(qpc, qpc, user_index, uidx); 2042 2043 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2044 MLX5_SET(qpc, qpc, end_padding_mode, 2045 MLX5_WQ_END_PAD_MODE_ALIGN); 2046 /* Special case to clean flag */ 2047 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2048 } 2049 2050 base = &qp->trans_qp.base; 2051 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2052 kvfree(in); 2053 if (err) 2054 return err; 2055 2056 base->container_mibqp = qp; 2057 base->mqp.event = mlx5_ib_qp_event; 2058 if (MLX5_CAP_GEN(mdev, ece_support)) 2059 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2060 2061 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2062 list_add_tail(&qp->qps_list, &dev->qp_list); 2063 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2064 2065 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn; 2066 return 0; 2067 } 2068 2069 static int create_dci(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2070 struct mlx5_ib_qp *qp, 2071 struct mlx5_create_qp_params *params) 2072 { 2073 struct ib_qp_init_attr *init_attr = params->attr; 2074 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2075 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2076 struct ib_udata *udata = params->udata; 2077 u32 uidx = params->uidx; 2078 struct mlx5_ib_resources *devr = &dev->devr; 2079 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2080 struct mlx5_core_dev *mdev = dev->mdev; 2081 struct mlx5_ib_cq *send_cq; 2082 struct mlx5_ib_cq *recv_cq; 2083 unsigned long flags; 2084 struct mlx5_ib_qp_base *base; 2085 int ts_format; 2086 int mlx5_st; 2087 void *qpc; 2088 u32 *in; 2089 int err; 2090 2091 spin_lock_init(&qp->sq.lock); 2092 spin_lock_init(&qp->rq.lock); 2093 2094 mlx5_st = to_mlx5_st(qp->type); 2095 if (mlx5_st < 0) 2096 return -EINVAL; 2097 2098 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2099 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2100 2101 base = &qp->trans_qp.base; 2102 2103 qp->has_rq = qp_has_rq(init_attr); 2104 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 2105 if (err) { 2106 mlx5_ib_dbg(dev, "err %d\n", err); 2107 return err; 2108 } 2109 2110 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 2111 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 2112 return -EINVAL; 2113 2114 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 2115 return -EINVAL; 2116 2117 ts_format = get_qp_ts_format(dev, to_mcq(init_attr->send_cq), 2118 to_mcq(init_attr->recv_cq)); 2119 2120 if (ts_format < 0) 2121 return ts_format; 2122 2123 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 2124 &inlen, base, ucmd); 2125 if (err) 2126 return err; 2127 2128 if (MLX5_CAP_GEN(mdev, ece_support)) 2129 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 2130 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2131 2132 MLX5_SET(qpc, qpc, st, mlx5_st); 2133 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2134 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 2135 2136 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 2137 MLX5_SET(qpc, qpc, wq_signature, 1); 2138 2139 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2140 MLX5_SET(qpc, qpc, cd_master, 1); 2141 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2142 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2143 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) 2144 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2145 2146 if (qp->rq.wqe_cnt) { 2147 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2148 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2149 } 2150 2151 if (qp->flags_en & MLX5_QP_FLAG_DCI_STREAM) { 2152 MLX5_SET(qpc, qpc, log_num_dci_stream_channels, 2153 ucmd->dci_streams.log_num_concurent); 2154 MLX5_SET(qpc, qpc, log_num_dci_errored_streams, 2155 ucmd->dci_streams.log_num_errored); 2156 } 2157 2158 MLX5_SET(qpc, qpc, ts_format, ts_format); 2159 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2160 2161 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2162 2163 /* Set default resources */ 2164 if (init_attr->srq) { 2165 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2166 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2167 to_msrq(init_attr->srq)->msrq.srqn); 2168 } else { 2169 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2170 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2171 to_msrq(devr->s1)->msrq.srqn); 2172 } 2173 2174 if (init_attr->send_cq) 2175 MLX5_SET(qpc, qpc, cqn_snd, 2176 to_mcq(init_attr->send_cq)->mcq.cqn); 2177 2178 if (init_attr->recv_cq) 2179 MLX5_SET(qpc, qpc, cqn_rcv, 2180 to_mcq(init_attr->recv_cq)->mcq.cqn); 2181 2182 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2183 2184 /* 0xffffff means we ask to work with cqe version 0 */ 2185 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2186 MLX5_SET(qpc, qpc, user_index, uidx); 2187 2188 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { 2189 MLX5_SET(qpc, qpc, end_padding_mode, 2190 MLX5_WQ_END_PAD_MODE_ALIGN); 2191 /* Special case to clean flag */ 2192 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2193 } 2194 2195 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2196 2197 kvfree(in); 2198 if (err) 2199 goto err_create; 2200 2201 base->container_mibqp = qp; 2202 base->mqp.event = mlx5_ib_qp_event; 2203 if (MLX5_CAP_GEN(mdev, ece_support)) 2204 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2205 2206 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2207 &send_cq, &recv_cq); 2208 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2209 mlx5_ib_lock_cqs(send_cq, recv_cq); 2210 /* Maintain device to QPs access, needed for further handling via reset 2211 * flow 2212 */ 2213 list_add_tail(&qp->qps_list, &dev->qp_list); 2214 /* Maintain CQ to QPs access, needed for further handling via reset flow 2215 */ 2216 if (send_cq) 2217 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2218 if (recv_cq) 2219 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2220 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2221 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2222 2223 return 0; 2224 2225 err_create: 2226 destroy_qp(dev, qp, base, udata); 2227 return err; 2228 } 2229 2230 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2231 struct mlx5_ib_qp *qp, 2232 struct mlx5_create_qp_params *params) 2233 { 2234 struct ib_qp_init_attr *init_attr = params->attr; 2235 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2236 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2237 struct ib_udata *udata = params->udata; 2238 u32 uidx = params->uidx; 2239 struct mlx5_ib_resources *devr = &dev->devr; 2240 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2241 struct mlx5_core_dev *mdev = dev->mdev; 2242 struct mlx5_ib_cq *send_cq; 2243 struct mlx5_ib_cq *recv_cq; 2244 unsigned long flags; 2245 struct mlx5_ib_qp_base *base; 2246 int ts_format; 2247 int mlx5_st; 2248 void *qpc; 2249 u32 *in; 2250 int err; 2251 2252 spin_lock_init(&qp->sq.lock); 2253 spin_lock_init(&qp->rq.lock); 2254 2255 mlx5_st = to_mlx5_st(qp->type); 2256 if (mlx5_st < 0) 2257 return -EINVAL; 2258 2259 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2260 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2261 2262 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 2263 qp->underlay_qpn = init_attr->source_qpn; 2264 2265 base = (init_attr->qp_type == IB_QPT_RAW_PACKET || 2266 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2267 &qp->raw_packet_qp.rq.base : 2268 &qp->trans_qp.base; 2269 2270 qp->has_rq = qp_has_rq(init_attr); 2271 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd); 2272 if (err) { 2273 mlx5_ib_dbg(dev, "err %d\n", err); 2274 return err; 2275 } 2276 2277 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift || 2278 ucmd->rq_wqe_count != qp->rq.wqe_cnt) 2279 return -EINVAL; 2280 2281 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz))) 2282 return -EINVAL; 2283 2284 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 2285 ts_format = get_qp_ts_format(dev, to_mcq(init_attr->send_cq), 2286 to_mcq(init_attr->recv_cq)); 2287 if (ts_format < 0) 2288 return ts_format; 2289 } 2290 2291 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp, 2292 &inlen, base, ucmd); 2293 if (err) 2294 return err; 2295 2296 if (is_sqp(init_attr->qp_type)) 2297 qp->port = init_attr->port_num; 2298 2299 if (MLX5_CAP_GEN(mdev, ece_support)) 2300 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options); 2301 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2302 2303 MLX5_SET(qpc, qpc, st, mlx5_st); 2304 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2305 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn); 2306 2307 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE) 2308 MLX5_SET(qpc, qpc, wq_signature, 1); 2309 2310 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2311 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2312 2313 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL) 2314 MLX5_SET(qpc, qpc, cd_master, 1); 2315 if (qp->flags & IB_QP_CREATE_MANAGED_SEND) 2316 MLX5_SET(qpc, qpc, cd_slave_send, 1); 2317 if (qp->flags & IB_QP_CREATE_MANAGED_RECV) 2318 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 2319 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) 2320 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); 2321 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2322 (init_attr->qp_type == IB_QPT_RC || 2323 init_attr->qp_type == IB_QPT_UC)) { 2324 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); 2325 2326 MLX5_SET(qpc, qpc, cs_res, 2327 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : 2328 MLX5_RES_SCAT_DATA32_CQE); 2329 } 2330 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) && 2331 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC)) 2332 configure_requester_scat_cqe(dev, qp, init_attr, qpc); 2333 2334 if (qp->rq.wqe_cnt) { 2335 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2336 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2337 } 2338 2339 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 2340 MLX5_SET(qpc, qpc, ts_format, ts_format); 2341 2342 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 2343 2344 if (qp->sq.wqe_cnt) { 2345 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2346 } else { 2347 MLX5_SET(qpc, qpc, no_sq, 1); 2348 if (init_attr->srq && 2349 init_attr->srq->srq_type == IB_SRQT_TM) 2350 MLX5_SET(qpc, qpc, offload_type, 2351 MLX5_QPC_OFFLOAD_TYPE_RNDV); 2352 } 2353 2354 /* Set default resources */ 2355 switch (init_attr->qp_type) { 2356 case IB_QPT_XRC_INI: 2357 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 2358 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2359 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); 2360 break; 2361 default: 2362 if (init_attr->srq) { 2363 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2364 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); 2365 } else { 2366 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2367 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); 2368 } 2369 } 2370 2371 if (init_attr->send_cq) 2372 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 2373 2374 if (init_attr->recv_cq) 2375 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 2376 2377 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2378 2379 /* 0xffffff means we ask to work with cqe version 0 */ 2380 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2381 MLX5_SET(qpc, qpc, user_index, uidx); 2382 2383 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING && 2384 init_attr->qp_type != IB_QPT_RAW_PACKET) { 2385 MLX5_SET(qpc, qpc, end_padding_mode, 2386 MLX5_WQ_END_PAD_MODE_ALIGN); 2387 /* Special case to clean flag */ 2388 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING; 2389 } 2390 2391 if (init_attr->qp_type == IB_QPT_RAW_PACKET || 2392 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2393 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr; 2394 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 2395 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, 2396 ¶ms->resp, init_attr); 2397 } else 2398 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2399 2400 kvfree(in); 2401 if (err) 2402 goto err_create; 2403 2404 base->container_mibqp = qp; 2405 base->mqp.event = mlx5_ib_qp_event; 2406 if (MLX5_CAP_GEN(mdev, ece_support)) 2407 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece); 2408 2409 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq, 2410 &send_cq, &recv_cq); 2411 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2412 mlx5_ib_lock_cqs(send_cq, recv_cq); 2413 /* Maintain device to QPs access, needed for further handling via reset 2414 * flow 2415 */ 2416 list_add_tail(&qp->qps_list, &dev->qp_list); 2417 /* Maintain CQ to QPs access, needed for further handling via reset flow 2418 */ 2419 if (send_cq) 2420 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2421 if (recv_cq) 2422 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2423 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2424 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2425 2426 return 0; 2427 2428 err_create: 2429 destroy_qp(dev, qp, base, udata); 2430 return err; 2431 } 2432 2433 static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2434 struct mlx5_ib_qp *qp, 2435 struct mlx5_create_qp_params *params) 2436 { 2437 struct ib_qp_init_attr *attr = params->attr; 2438 u32 uidx = params->uidx; 2439 struct mlx5_ib_resources *devr = &dev->devr; 2440 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; 2441 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 2442 struct mlx5_core_dev *mdev = dev->mdev; 2443 struct mlx5_ib_cq *send_cq; 2444 struct mlx5_ib_cq *recv_cq; 2445 unsigned long flags; 2446 struct mlx5_ib_qp_base *base; 2447 int mlx5_st; 2448 void *qpc; 2449 u32 *in; 2450 int err; 2451 2452 spin_lock_init(&qp->sq.lock); 2453 spin_lock_init(&qp->rq.lock); 2454 2455 mlx5_st = to_mlx5_st(qp->type); 2456 if (mlx5_st < 0) 2457 return -EINVAL; 2458 2459 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR) 2460 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 2461 2462 base = &qp->trans_qp.base; 2463 2464 qp->has_rq = qp_has_rq(attr); 2465 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL); 2466 if (err) { 2467 mlx5_ib_dbg(dev, "err %d\n", err); 2468 return err; 2469 } 2470 2471 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base); 2472 if (err) 2473 return err; 2474 2475 if (is_sqp(attr->qp_type)) 2476 qp->port = attr->port_num; 2477 2478 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2479 2480 MLX5_SET(qpc, qpc, st, mlx5_st); 2481 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2482 2483 if (attr->qp_type != MLX5_IB_QPT_REG_UMR) 2484 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 2485 else 2486 MLX5_SET(qpc, qpc, latency_sensitive, 1); 2487 2488 2489 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 2490 MLX5_SET(qpc, qpc, block_lb_mc, 1); 2491 2492 if (qp->rq.wqe_cnt) { 2493 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 2494 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 2495 } 2496 2497 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr)); 2498 2499 if (qp->sq.wqe_cnt) 2500 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 2501 else 2502 MLX5_SET(qpc, qpc, no_sq, 1); 2503 2504 if (attr->srq) { 2505 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0); 2506 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2507 to_msrq(attr->srq)->msrq.srqn); 2508 } else { 2509 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1); 2510 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, 2511 to_msrq(devr->s1)->msrq.srqn); 2512 } 2513 2514 if (attr->send_cq) 2515 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn); 2516 2517 if (attr->recv_cq) 2518 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn); 2519 2520 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 2521 2522 /* 0xffffff means we ask to work with cqe version 0 */ 2523 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 2524 MLX5_SET(qpc, qpc, user_index, uidx); 2525 2526 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 2527 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) 2528 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 2529 2530 if (qp->flags & IB_QP_CREATE_INTEGRITY_EN && 2531 MLX5_CAP_GEN(mdev, go_back_n)) 2532 MLX5_SET(qpc, qpc, retry_mode, MLX5_QP_RM_GO_BACK_N); 2533 2534 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out); 2535 kvfree(in); 2536 if (err) 2537 goto err_create; 2538 2539 base->container_mibqp = qp; 2540 base->mqp.event = mlx5_ib_qp_event; 2541 2542 get_cqs(qp->type, attr->send_cq, attr->recv_cq, 2543 &send_cq, &recv_cq); 2544 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2545 mlx5_ib_lock_cqs(send_cq, recv_cq); 2546 /* Maintain device to QPs access, needed for further handling via reset 2547 * flow 2548 */ 2549 list_add_tail(&qp->qps_list, &dev->qp_list); 2550 /* Maintain CQ to QPs access, needed for further handling via reset flow 2551 */ 2552 if (send_cq) 2553 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 2554 if (recv_cq) 2555 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 2556 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2557 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2558 2559 return 0; 2560 2561 err_create: 2562 destroy_qp(dev, qp, base, NULL); 2563 return err; 2564 } 2565 2566 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2567 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 2568 { 2569 if (send_cq) { 2570 if (recv_cq) { 2571 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2572 spin_lock(&send_cq->lock); 2573 spin_lock_nested(&recv_cq->lock, 2574 SINGLE_DEPTH_NESTING); 2575 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2576 spin_lock(&send_cq->lock); 2577 __acquire(&recv_cq->lock); 2578 } else { 2579 spin_lock(&recv_cq->lock); 2580 spin_lock_nested(&send_cq->lock, 2581 SINGLE_DEPTH_NESTING); 2582 } 2583 } else { 2584 spin_lock(&send_cq->lock); 2585 __acquire(&recv_cq->lock); 2586 } 2587 } else if (recv_cq) { 2588 spin_lock(&recv_cq->lock); 2589 __acquire(&send_cq->lock); 2590 } else { 2591 __acquire(&send_cq->lock); 2592 __acquire(&recv_cq->lock); 2593 } 2594 } 2595 2596 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 2597 __releases(&send_cq->lock) __releases(&recv_cq->lock) 2598 { 2599 if (send_cq) { 2600 if (recv_cq) { 2601 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 2602 spin_unlock(&recv_cq->lock); 2603 spin_unlock(&send_cq->lock); 2604 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 2605 __release(&recv_cq->lock); 2606 spin_unlock(&send_cq->lock); 2607 } else { 2608 spin_unlock(&send_cq->lock); 2609 spin_unlock(&recv_cq->lock); 2610 } 2611 } else { 2612 __release(&recv_cq->lock); 2613 spin_unlock(&send_cq->lock); 2614 } 2615 } else if (recv_cq) { 2616 __release(&send_cq->lock); 2617 spin_unlock(&recv_cq->lock); 2618 } else { 2619 __release(&recv_cq->lock); 2620 __release(&send_cq->lock); 2621 } 2622 } 2623 2624 static void get_cqs(enum ib_qp_type qp_type, 2625 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 2626 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 2627 { 2628 switch (qp_type) { 2629 case IB_QPT_XRC_TGT: 2630 *send_cq = NULL; 2631 *recv_cq = NULL; 2632 break; 2633 case MLX5_IB_QPT_REG_UMR: 2634 case IB_QPT_XRC_INI: 2635 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2636 *recv_cq = NULL; 2637 break; 2638 2639 case IB_QPT_SMI: 2640 case MLX5_IB_QPT_HW_GSI: 2641 case IB_QPT_RC: 2642 case IB_QPT_UC: 2643 case IB_QPT_UD: 2644 case IB_QPT_RAW_PACKET: 2645 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 2646 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 2647 break; 2648 default: 2649 *send_cq = NULL; 2650 *recv_cq = NULL; 2651 break; 2652 } 2653 } 2654 2655 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2656 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2657 u8 lag_tx_affinity); 2658 2659 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2660 struct ib_udata *udata) 2661 { 2662 struct mlx5_ib_cq *send_cq, *recv_cq; 2663 struct mlx5_ib_qp_base *base; 2664 unsigned long flags; 2665 int err; 2666 2667 if (qp->is_rss) { 2668 destroy_rss_raw_qp_tir(dev, qp); 2669 return; 2670 } 2671 2672 base = (qp->type == IB_QPT_RAW_PACKET || 2673 qp->flags & IB_QP_CREATE_SOURCE_QPN) ? 2674 &qp->raw_packet_qp.rq.base : 2675 &qp->trans_qp.base; 2676 2677 if (qp->state != IB_QPS_RESET) { 2678 if (qp->type != IB_QPT_RAW_PACKET && 2679 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) { 2680 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0, 2681 NULL, &base->mqp, NULL); 2682 } else { 2683 struct mlx5_modify_raw_qp_param raw_qp_param = { 2684 .operation = MLX5_CMD_OP_2RST_QP 2685 }; 2686 2687 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2688 } 2689 if (err) 2690 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2691 base->mqp.qpn); 2692 } 2693 2694 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq, 2695 &recv_cq); 2696 2697 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2698 mlx5_ib_lock_cqs(send_cq, recv_cq); 2699 /* del from lists under both locks above to protect reset flow paths */ 2700 list_del(&qp->qps_list); 2701 if (send_cq) 2702 list_del(&qp->cq_send_list); 2703 2704 if (recv_cq) 2705 list_del(&qp->cq_recv_list); 2706 2707 if (!udata) { 2708 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2709 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2710 if (send_cq != recv_cq) 2711 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2712 NULL); 2713 } 2714 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2715 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2716 2717 if (qp->type == IB_QPT_RAW_PACKET || 2718 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 2719 destroy_raw_packet_qp(dev, qp); 2720 } else { 2721 err = mlx5_core_destroy_qp(dev, &base->mqp); 2722 if (err) 2723 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2724 base->mqp.qpn); 2725 } 2726 2727 destroy_qp(dev, qp, base, udata); 2728 } 2729 2730 static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2731 struct mlx5_ib_qp *qp, 2732 struct mlx5_create_qp_params *params) 2733 { 2734 struct ib_qp_init_attr *attr = params->attr; 2735 struct mlx5_ib_create_qp *ucmd = params->ucmd; 2736 u32 uidx = params->uidx; 2737 void *dctc; 2738 2739 if (mlx5_lag_is_active(dev->mdev) && !MLX5_CAP_GEN(dev->mdev, lag_dct)) 2740 return -EOPNOTSUPP; 2741 2742 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); 2743 if (!qp->dct.in) 2744 return -ENOMEM; 2745 2746 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); 2747 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 2748 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); 2749 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); 2750 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); 2751 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); 2752 MLX5_SET(dctc, dctc, user_index, uidx); 2753 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2754 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 2755 2756 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) { 2757 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq); 2758 2759 if (rcqe_sz == 128) 2760 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 2761 } 2762 2763 qp->state = IB_QPS_RESET; 2764 return 0; 2765 } 2766 2767 static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 2768 enum ib_qp_type *type) 2769 { 2770 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct)) 2771 goto out; 2772 2773 switch (attr->qp_type) { 2774 case IB_QPT_XRC_TGT: 2775 case IB_QPT_XRC_INI: 2776 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2777 goto out; 2778 fallthrough; 2779 case IB_QPT_RC: 2780 case IB_QPT_UC: 2781 case IB_QPT_SMI: 2782 case MLX5_IB_QPT_HW_GSI: 2783 case IB_QPT_DRIVER: 2784 case IB_QPT_GSI: 2785 case IB_QPT_RAW_PACKET: 2786 case IB_QPT_UD: 2787 case MLX5_IB_QPT_REG_UMR: 2788 break; 2789 default: 2790 goto out; 2791 } 2792 2793 *type = attr->qp_type; 2794 return 0; 2795 2796 out: 2797 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type); 2798 return -EOPNOTSUPP; 2799 } 2800 2801 static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd, 2802 struct ib_qp_init_attr *attr, 2803 struct ib_udata *udata) 2804 { 2805 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2806 udata, struct mlx5_ib_ucontext, ibucontext); 2807 2808 if (!udata) { 2809 /* Kernel create_qp callers */ 2810 if (attr->rwq_ind_tbl) 2811 return -EOPNOTSUPP; 2812 2813 switch (attr->qp_type) { 2814 case IB_QPT_RAW_PACKET: 2815 case IB_QPT_DRIVER: 2816 return -EOPNOTSUPP; 2817 default: 2818 return 0; 2819 } 2820 } 2821 2822 /* Userspace create_qp callers */ 2823 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) { 2824 mlx5_ib_dbg(dev, 2825 "Raw Packet QP is only supported for CQE version > 0\n"); 2826 return -EINVAL; 2827 } 2828 2829 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) { 2830 mlx5_ib_dbg(dev, 2831 "Wrong QP type %d for the RWQ indirect table\n", 2832 attr->qp_type); 2833 return -EINVAL; 2834 } 2835 2836 /* 2837 * We don't need to see this warning, it means that kernel code 2838 * missing ib_pd. Placed here to catch developer's mistakes. 2839 */ 2840 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT, 2841 "There is a missing PD pointer assignment\n"); 2842 return 0; 2843 } 2844 2845 static bool get_dp_ooo_cap(struct mlx5_core_dev *mdev, enum ib_qp_type qp_type) 2846 { 2847 if (!MLX5_CAP_GEN_2(mdev, dp_ordering_force)) 2848 return false; 2849 2850 switch (qp_type) { 2851 case IB_QPT_RC: 2852 return MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_rc); 2853 case IB_QPT_XRC_INI: 2854 case IB_QPT_XRC_TGT: 2855 return MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_xrc); 2856 case IB_QPT_UC: 2857 return MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_uc); 2858 case IB_QPT_UD: 2859 return MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_ud); 2860 case MLX5_IB_QPT_DCI: 2861 case MLX5_IB_QPT_DCT: 2862 return MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_dc); 2863 default: 2864 return false; 2865 } 2866 } 2867 2868 static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2869 bool cond, struct mlx5_ib_qp *qp) 2870 { 2871 if (!(*flags & flag)) 2872 return; 2873 2874 if (cond) { 2875 qp->flags_en |= flag; 2876 *flags &= ~flag; 2877 return; 2878 } 2879 2880 switch (flag) { 2881 case MLX5_QP_FLAG_SCATTER_CQE: 2882 case MLX5_QP_FLAG_ALLOW_SCATTER_CQE: 2883 /* 2884 * We don't return error if these flags were provided, 2885 * and mlx5 doesn't have right capability. 2886 */ 2887 *flags &= ~(MLX5_QP_FLAG_SCATTER_CQE | 2888 MLX5_QP_FLAG_ALLOW_SCATTER_CQE); 2889 return; 2890 default: 2891 break; 2892 } 2893 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag); 2894 } 2895 2896 static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2897 void *ucmd, struct ib_qp_init_attr *attr) 2898 { 2899 struct mlx5_core_dev *mdev = dev->mdev; 2900 bool cond; 2901 int flags; 2902 2903 if (attr->rwq_ind_tbl) 2904 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags; 2905 else 2906 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags; 2907 2908 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) { 2909 case MLX5_QP_FLAG_TYPE_DCI: 2910 qp->type = MLX5_IB_QPT_DCI; 2911 break; 2912 case MLX5_QP_FLAG_TYPE_DCT: 2913 qp->type = MLX5_IB_QPT_DCT; 2914 break; 2915 default: 2916 if (qp->type != IB_QPT_DRIVER) 2917 break; 2918 /* 2919 * It is IB_QPT_DRIVER and or no subtype or 2920 * wrong subtype were provided. 2921 */ 2922 return -EINVAL; 2923 } 2924 2925 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp); 2926 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp); 2927 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_DCI_STREAM, 2928 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels), 2929 qp); 2930 2931 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp); 2932 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE, 2933 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2934 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_ALLOW_SCATTER_CQE, 2935 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp); 2936 2937 if (qp->type == IB_QPT_RAW_PACKET) { 2938 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || 2939 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) || 2940 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx); 2941 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS, 2942 cond, qp); 2943 process_vendor_flag(dev, &flags, 2944 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true, 2945 qp); 2946 process_vendor_flag(dev, &flags, 2947 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true, 2948 qp); 2949 } 2950 2951 if (qp->type == IB_QPT_RC) 2952 process_vendor_flag(dev, &flags, 2953 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE, 2954 MLX5_CAP_GEN(mdev, qp_packet_based), qp); 2955 2956 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp); 2957 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp); 2958 2959 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | 2960 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | 2961 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC); 2962 if (attr->rwq_ind_tbl && cond) { 2963 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n", 2964 cond); 2965 return -EINVAL; 2966 } 2967 2968 if (flags) 2969 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags); 2970 2971 return (flags) ? -EINVAL : 0; 2972 } 2973 2974 static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag, 2975 bool cond, struct mlx5_ib_qp *qp) 2976 { 2977 if (!(*flags & flag)) 2978 return; 2979 2980 if (cond) { 2981 qp->flags |= flag; 2982 *flags &= ~flag; 2983 return; 2984 } 2985 2986 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag); 2987 } 2988 2989 static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2990 struct ib_qp_init_attr *attr) 2991 { 2992 enum ib_qp_type qp_type = qp->type; 2993 struct mlx5_core_dev *mdev = dev->mdev; 2994 int create_flags = attr->create_flags; 2995 bool cond; 2996 2997 if (qp_type == MLX5_IB_QPT_DCT) 2998 return (create_flags) ? -EINVAL : 0; 2999 3000 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) 3001 return (create_flags) ? -EINVAL : 0; 3002 3003 process_create_flag(dev, &create_flags, IB_QP_CREATE_NETIF_QP, 3004 mlx5_get_flow_namespace(dev->mdev, 3005 MLX5_FLOW_NAMESPACE_BYPASS), 3006 qp); 3007 process_create_flag(dev, &create_flags, 3008 IB_QP_CREATE_INTEGRITY_EN, 3009 MLX5_CAP_GEN(mdev, sho), qp); 3010 process_create_flag(dev, &create_flags, 3011 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 3012 MLX5_CAP_GEN(mdev, block_lb_mc), qp); 3013 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL, 3014 MLX5_CAP_GEN(mdev, cd), qp); 3015 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND, 3016 MLX5_CAP_GEN(mdev, cd), qp); 3017 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV, 3018 MLX5_CAP_GEN(mdev, cd), qp); 3019 3020 if (qp_type == IB_QPT_UD) { 3021 process_create_flag(dev, &create_flags, 3022 IB_QP_CREATE_IPOIB_UD_LSO, 3023 MLX5_CAP_GEN(mdev, ipoib_basic_offloads), 3024 qp); 3025 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB; 3026 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN, 3027 cond, qp); 3028 } 3029 3030 if (qp_type == IB_QPT_RAW_PACKET) { 3031 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 3032 MLX5_CAP_ETH(mdev, scatter_fcs); 3033 process_create_flag(dev, &create_flags, 3034 IB_QP_CREATE_SCATTER_FCS, cond, qp); 3035 3036 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) && 3037 MLX5_CAP_ETH(mdev, vlan_cap); 3038 process_create_flag(dev, &create_flags, 3039 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp); 3040 } 3041 3042 process_create_flag(dev, &create_flags, 3043 IB_QP_CREATE_PCI_WRITE_END_PADDING, 3044 MLX5_CAP_GEN(mdev, end_pad), qp); 3045 3046 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1, 3047 true, qp); 3048 3049 if (create_flags) { 3050 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n", 3051 create_flags); 3052 return -EOPNOTSUPP; 3053 } 3054 return 0; 3055 } 3056 3057 static int process_udata_size(struct mlx5_ib_dev *dev, 3058 struct mlx5_create_qp_params *params) 3059 { 3060 size_t ucmd = sizeof(struct mlx5_ib_create_qp); 3061 struct ib_udata *udata = params->udata; 3062 size_t outlen = udata->outlen; 3063 size_t inlen = udata->inlen; 3064 3065 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp)); 3066 params->ucmd_size = ucmd; 3067 if (!params->is_rss_raw) { 3068 /* User has old rdma-core, which doesn't support ECE */ 3069 size_t min_inlen = 3070 offsetof(struct mlx5_ib_create_qp, ece_options); 3071 3072 /* 3073 * We will check in check_ucmd_data() that user 3074 * cleared everything after inlen. 3075 */ 3076 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd); 3077 goto out; 3078 } 3079 3080 /* RSS RAW QP */ 3081 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags)) 3082 return -EINVAL; 3083 3084 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index)) 3085 return -EINVAL; 3086 3087 ucmd = sizeof(struct mlx5_ib_create_qp_rss); 3088 params->ucmd_size = ucmd; 3089 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd)) 3090 return -EINVAL; 3091 3092 params->inlen = min(ucmd, inlen); 3093 out: 3094 if (!params->inlen) 3095 mlx5_ib_dbg(dev, "udata is too small\n"); 3096 3097 return (params->inlen) ? 0 : -EINVAL; 3098 } 3099 3100 static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 3101 struct mlx5_ib_qp *qp, 3102 struct mlx5_create_qp_params *params) 3103 { 3104 int err; 3105 3106 if (params->is_rss_raw) { 3107 err = create_rss_raw_qp_tir(dev, pd, qp, params); 3108 goto out; 3109 } 3110 3111 switch (qp->type) { 3112 case MLX5_IB_QPT_DCT: 3113 err = create_dct(dev, pd, qp, params); 3114 break; 3115 case MLX5_IB_QPT_DCI: 3116 err = create_dci(dev, pd, qp, params); 3117 break; 3118 case IB_QPT_XRC_TGT: 3119 err = create_xrc_tgt_qp(dev, qp, params); 3120 break; 3121 case IB_QPT_GSI: 3122 err = mlx5_ib_create_gsi(pd, qp, params->attr); 3123 break; 3124 case MLX5_IB_QPT_HW_GSI: 3125 rdma_restrack_no_track(&qp->ibqp.res); 3126 fallthrough; 3127 case MLX5_IB_QPT_REG_UMR: 3128 default: 3129 if (params->udata) 3130 err = create_user_qp(dev, pd, qp, params); 3131 else 3132 err = create_kernel_qp(dev, pd, qp, params); 3133 } 3134 3135 out: 3136 if (err) { 3137 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type); 3138 return err; 3139 } 3140 3141 if (is_qp0(qp->type)) 3142 qp->ibqp.qp_num = 0; 3143 else if (is_qp1(qp->type)) 3144 qp->ibqp.qp_num = 1; 3145 else 3146 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 3147 3148 mlx5_ib_dbg(dev, 3149 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n", 3150 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 3151 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn : 3152 -1, 3153 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn : 3154 -1, 3155 params->resp.ece_options); 3156 3157 return 0; 3158 } 3159 3160 static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3161 struct ib_qp_init_attr *attr) 3162 { 3163 int ret = 0; 3164 3165 switch (qp->type) { 3166 case MLX5_IB_QPT_DCT: 3167 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0; 3168 break; 3169 case MLX5_IB_QPT_DCI: 3170 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ? 3171 -EINVAL : 3172 0; 3173 break; 3174 case IB_QPT_RAW_PACKET: 3175 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0; 3176 break; 3177 default: 3178 break; 3179 } 3180 3181 if (ret) 3182 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type); 3183 3184 return ret; 3185 } 3186 3187 static int get_qp_uidx(struct mlx5_ib_qp *qp, 3188 struct mlx5_create_qp_params *params) 3189 { 3190 struct mlx5_ib_create_qp *ucmd = params->ucmd; 3191 struct ib_udata *udata = params->udata; 3192 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 3193 udata, struct mlx5_ib_ucontext, ibucontext); 3194 3195 if (params->is_rss_raw) 3196 return 0; 3197 3198 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), ¶ms->uidx); 3199 } 3200 3201 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) 3202 { 3203 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); 3204 3205 if (mqp->state == IB_QPS_RTR) { 3206 int err; 3207 3208 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); 3209 if (err) { 3210 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); 3211 return err; 3212 } 3213 } 3214 3215 kfree(mqp->dct.in); 3216 return 0; 3217 } 3218 3219 static int check_ucmd_data(struct mlx5_ib_dev *dev, 3220 struct mlx5_create_qp_params *params) 3221 { 3222 struct ib_udata *udata = params->udata; 3223 size_t size, last; 3224 int ret; 3225 3226 if (params->is_rss_raw) 3227 /* 3228 * These QPs don't have "reserved" field in their 3229 * create_qp input struct, so their data is always valid. 3230 */ 3231 last = sizeof(struct mlx5_ib_create_qp_rss); 3232 else 3233 last = offsetof(struct mlx5_ib_create_qp, reserved); 3234 3235 if (udata->inlen <= last) 3236 return 0; 3237 3238 /* 3239 * User provides different create_qp structures based on the 3240 * flow and we need to know if he cleared memory after our 3241 * struct create_qp ends. 3242 */ 3243 size = udata->inlen - last; 3244 ret = ib_is_udata_cleared(params->udata, last, size); 3245 if (!ret) 3246 mlx5_ib_dbg( 3247 dev, 3248 "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n", 3249 udata->inlen, params->ucmd_size, last, size); 3250 return ret ? 0 : -EINVAL; 3251 } 3252 3253 int mlx5_ib_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attr, 3254 struct ib_udata *udata) 3255 { 3256 struct mlx5_create_qp_params params = {}; 3257 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3258 struct mlx5_ib_qp *qp = to_mqp(ibqp); 3259 struct ib_pd *pd = ibqp->pd; 3260 enum ib_qp_type type; 3261 int err; 3262 3263 err = mlx5_ib_dev_res_srq_init(dev); 3264 if (err) 3265 return err; 3266 3267 err = check_qp_type(dev, attr, &type); 3268 if (err) 3269 return err; 3270 3271 err = check_valid_flow(dev, pd, attr, udata); 3272 if (err) 3273 return err; 3274 3275 params.udata = udata; 3276 params.uidx = MLX5_IB_DEFAULT_UIDX; 3277 params.attr = attr; 3278 params.is_rss_raw = !!attr->rwq_ind_tbl; 3279 3280 if (udata) { 3281 err = process_udata_size(dev, ¶ms); 3282 if (err) 3283 return err; 3284 3285 err = check_ucmd_data(dev, ¶ms); 3286 if (err) 3287 return err; 3288 3289 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL); 3290 if (!params.ucmd) 3291 return -ENOMEM; 3292 3293 err = ib_copy_from_udata(params.ucmd, udata, params.inlen); 3294 if (err) 3295 goto free_ucmd; 3296 } 3297 3298 mutex_init(&qp->mutex); 3299 qp->type = type; 3300 if (udata) { 3301 err = process_vendor_flags(dev, qp, params.ucmd, attr); 3302 if (err) 3303 goto free_ucmd; 3304 3305 err = get_qp_uidx(qp, ¶ms); 3306 if (err) 3307 goto free_ucmd; 3308 } 3309 err = process_create_flags(dev, qp, attr); 3310 if (err) 3311 goto free_ucmd; 3312 3313 err = check_qp_attr(dev, qp, attr); 3314 if (err) 3315 goto free_ucmd; 3316 3317 err = create_qp(dev, pd, qp, ¶ms); 3318 if (err) 3319 goto free_ucmd; 3320 3321 kfree(params.ucmd); 3322 params.ucmd = NULL; 3323 3324 if (udata) 3325 /* 3326 * It is safe to copy response for all user create QP flows, 3327 * including MLX5_IB_QPT_DCT, which doesn't need it. 3328 * In that case, resp will be filled with zeros. 3329 */ 3330 err = ib_copy_to_udata(udata, ¶ms.resp, params.outlen); 3331 if (err) 3332 goto destroy_qp; 3333 3334 return 0; 3335 3336 destroy_qp: 3337 switch (qp->type) { 3338 case MLX5_IB_QPT_DCT: 3339 mlx5_ib_destroy_dct(qp); 3340 break; 3341 case IB_QPT_GSI: 3342 mlx5_ib_destroy_gsi(qp); 3343 break; 3344 default: 3345 destroy_qp_common(dev, qp, udata); 3346 } 3347 3348 free_ucmd: 3349 kfree(params.ucmd); 3350 return err; 3351 } 3352 3353 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 3354 { 3355 struct mlx5_ib_dev *dev = to_mdev(qp->device); 3356 struct mlx5_ib_qp *mqp = to_mqp(qp); 3357 3358 if (mqp->type == IB_QPT_GSI) 3359 return mlx5_ib_destroy_gsi(mqp); 3360 3361 if (mqp->type == MLX5_IB_QPT_DCT) 3362 return mlx5_ib_destroy_dct(mqp); 3363 3364 destroy_qp_common(dev, mqp, udata); 3365 return 0; 3366 } 3367 3368 static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp, 3369 const struct ib_qp_attr *attr, int attr_mask, 3370 void *qpc) 3371 { 3372 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 3373 u8 dest_rd_atomic; 3374 u32 access_flags; 3375 3376 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3377 dest_rd_atomic = attr->max_dest_rd_atomic; 3378 else 3379 dest_rd_atomic = qp->trans_qp.resp_depth; 3380 3381 if (attr_mask & IB_QP_ACCESS_FLAGS) 3382 access_flags = attr->qp_access_flags; 3383 else 3384 access_flags = qp->trans_qp.atomic_rd_en; 3385 3386 if (!dest_rd_atomic) 3387 access_flags &= IB_ACCESS_REMOTE_WRITE; 3388 3389 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ)); 3390 3391 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 3392 int atomic_mode; 3393 3394 atomic_mode = get_atomic_mode(dev, qp); 3395 if (atomic_mode < 0) 3396 return -EOPNOTSUPP; 3397 3398 MLX5_SET(qpc, qpc, rae, 1); 3399 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode); 3400 } 3401 3402 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 3403 return 0; 3404 } 3405 3406 enum { 3407 MLX5_PATH_FLAG_FL = 1 << 0, 3408 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 3409 MLX5_PATH_FLAG_COUNTER = 1 << 2, 3410 }; 3411 3412 static int mlx5_to_ib_rate_map(u8 rate) 3413 { 3414 static const int rates[] = { IB_RATE_PORT_CURRENT, IB_RATE_56_GBPS, 3415 IB_RATE_25_GBPS, IB_RATE_100_GBPS, 3416 IB_RATE_200_GBPS, IB_RATE_50_GBPS, 3417 IB_RATE_400_GBPS }; 3418 3419 if (rate < ARRAY_SIZE(rates)) 3420 return rates[rate]; 3421 3422 return rate - MLX5_STAT_RATE_OFFSET; 3423 } 3424 3425 static int ib_to_mlx5_rate_map(u8 rate) 3426 { 3427 switch (rate) { 3428 case IB_RATE_PORT_CURRENT: 3429 return 0; 3430 case IB_RATE_56_GBPS: 3431 return 1; 3432 case IB_RATE_25_GBPS: 3433 return 2; 3434 case IB_RATE_100_GBPS: 3435 return 3; 3436 case IB_RATE_200_GBPS: 3437 return 4; 3438 case IB_RATE_50_GBPS: 3439 return 5; 3440 case IB_RATE_400_GBPS: 3441 return 6; 3442 default: 3443 return rate + MLX5_STAT_RATE_OFFSET; 3444 } 3445 3446 return 0; 3447 } 3448 3449 int mlx5r_ib_rate(struct mlx5_ib_dev *dev, u8 rate) 3450 { 3451 u32 stat_rate_support; 3452 3453 if (rate == IB_RATE_PORT_CURRENT || rate == IB_RATE_800_GBPS || 3454 rate == IB_RATE_1600_GBPS) 3455 return 0; 3456 3457 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_1600_GBPS) 3458 return -EINVAL; 3459 3460 stat_rate_support = MLX5_CAP_GEN(dev->mdev, stat_rate_support); 3461 while (rate != IB_RATE_PORT_CURRENT && 3462 !(1 << ib_to_mlx5_rate_map(rate) & stat_rate_support)) 3463 --rate; 3464 3465 return ib_to_mlx5_rate_map(rate); 3466 } 3467 3468 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 3469 struct mlx5_ib_sq *sq, u8 sl, 3470 struct ib_pd *pd) 3471 { 3472 void *in; 3473 void *tisc; 3474 int inlen; 3475 int err; 3476 3477 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3478 in = kvzalloc(inlen, GFP_KERNEL); 3479 if (!in) 3480 return -ENOMEM; 3481 3482 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 3483 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3484 3485 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3486 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 3487 3488 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3489 3490 kvfree(in); 3491 3492 return err; 3493 } 3494 3495 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 3496 struct mlx5_ib_sq *sq, u8 tx_affinity, 3497 struct ib_pd *pd) 3498 { 3499 void *in; 3500 void *tisc; 3501 int inlen; 3502 int err; 3503 3504 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 3505 in = kvzalloc(inlen, GFP_KERNEL); 3506 if (!in) 3507 return -ENOMEM; 3508 3509 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 3510 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 3511 3512 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 3513 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 3514 3515 err = mlx5_core_modify_tis(dev, sq->tisn, in); 3516 3517 kvfree(in); 3518 3519 return err; 3520 } 3521 3522 static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah, 3523 u32 lqpn, u32 rqpn) 3524 3525 { 3526 u32 fl = ah->grh.flow_label; 3527 3528 if (!fl) 3529 fl = rdma_calc_flow_label(lqpn, rqpn); 3530 3531 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl)); 3532 } 3533 3534 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3535 const struct rdma_ah_attr *ah, void *path, u8 port, 3536 int attr_mask, u32 path_flags, 3537 const struct ib_qp_attr *attr, bool alt) 3538 { 3539 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 3540 int err; 3541 enum ib_gid_type gid_type; 3542 u8 ah_flags = rdma_ah_get_ah_flags(ah); 3543 u8 sl = rdma_ah_get_sl(ah); 3544 3545 if (attr_mask & IB_QP_PKEY_INDEX) 3546 MLX5_SET(ads, path, pkey_index, 3547 alt ? attr->alt_pkey_index : attr->pkey_index); 3548 3549 if (ah_flags & IB_AH_GRH) { 3550 const struct ib_port_immutable *immutable; 3551 3552 immutable = ib_port_immutable_read(&dev->ib_dev, port); 3553 if (grh->sgid_index >= immutable->gid_tbl_len) { 3554 pr_err("sgid_index (%u) too large. max is %d\n", 3555 grh->sgid_index, 3556 immutable->gid_tbl_len); 3557 return -EINVAL; 3558 } 3559 } 3560 3561 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 3562 if (!(ah_flags & IB_AH_GRH)) 3563 return -EINVAL; 3564 3565 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32), 3566 ah->roce.dmac); 3567 if ((qp->type == IB_QPT_RC || 3568 qp->type == IB_QPT_UC || 3569 qp->type == IB_QPT_XRC_INI || 3570 qp->type == IB_QPT_XRC_TGT) && 3571 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) && 3572 (attr_mask & IB_QP_DEST_QPN)) 3573 mlx5_set_path_udp_sport(path, ah, 3574 qp->ibqp.qp_num, 3575 attr->dest_qp_num); 3576 MLX5_SET(ads, path, eth_prio, sl & 0x7); 3577 gid_type = ah->grh.sgid_attr->gid_type; 3578 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 3579 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2); 3580 } else { 3581 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL)); 3582 MLX5_SET(ads, path, free_ar, 3583 !!(path_flags & MLX5_PATH_FLAG_FREE_AR)); 3584 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah)); 3585 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah)); 3586 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH)); 3587 MLX5_SET(ads, path, sl, sl); 3588 } 3589 3590 if (ah_flags & IB_AH_GRH) { 3591 MLX5_SET(ads, path, src_addr_index, grh->sgid_index); 3592 MLX5_SET(ads, path, hop_limit, grh->hop_limit); 3593 MLX5_SET(ads, path, tclass, grh->traffic_class); 3594 MLX5_SET(ads, path, flow_label, grh->flow_label); 3595 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw, 3596 sizeof(grh->dgid.raw)); 3597 } 3598 3599 err = mlx5r_ib_rate(dev, rdma_ah_get_static_rate(ah)); 3600 if (err < 0) 3601 return err; 3602 MLX5_SET(ads, path, stat_rate, err); 3603 MLX5_SET(ads, path, vhca_port_num, port); 3604 3605 if (attr_mask & IB_QP_TIMEOUT) 3606 MLX5_SET(ads, path, ack_timeout, 3607 alt ? attr->alt_timeout : attr->timeout); 3608 3609 if ((qp->type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 3610 return modify_raw_packet_eth_prio(dev->mdev, 3611 &qp->raw_packet_qp.sq, 3612 sl & 0xf, qp->ibqp.pd); 3613 3614 return 0; 3615 } 3616 3617 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 3618 [MLX5_QP_STATE_INIT] = { 3619 [MLX5_QP_STATE_INIT] = { 3620 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3621 MLX5_QP_OPTPAR_RAE | 3622 MLX5_QP_OPTPAR_RWE | 3623 MLX5_QP_OPTPAR_PKEY_INDEX | 3624 MLX5_QP_OPTPAR_PRI_PORT | 3625 MLX5_QP_OPTPAR_LAG_TX_AFF, 3626 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3627 MLX5_QP_OPTPAR_PKEY_INDEX | 3628 MLX5_QP_OPTPAR_PRI_PORT | 3629 MLX5_QP_OPTPAR_LAG_TX_AFF, 3630 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3631 MLX5_QP_OPTPAR_Q_KEY | 3632 MLX5_QP_OPTPAR_PRI_PORT, 3633 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3634 MLX5_QP_OPTPAR_RAE | 3635 MLX5_QP_OPTPAR_RWE | 3636 MLX5_QP_OPTPAR_PKEY_INDEX | 3637 MLX5_QP_OPTPAR_PRI_PORT | 3638 MLX5_QP_OPTPAR_LAG_TX_AFF, 3639 }, 3640 [MLX5_QP_STATE_RTR] = { 3641 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3642 MLX5_QP_OPTPAR_RRE | 3643 MLX5_QP_OPTPAR_RAE | 3644 MLX5_QP_OPTPAR_RWE | 3645 MLX5_QP_OPTPAR_PKEY_INDEX | 3646 MLX5_QP_OPTPAR_LAG_TX_AFF, 3647 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3648 MLX5_QP_OPTPAR_RWE | 3649 MLX5_QP_OPTPAR_PKEY_INDEX | 3650 MLX5_QP_OPTPAR_LAG_TX_AFF, 3651 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 3652 MLX5_QP_OPTPAR_Q_KEY, 3653 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 3654 MLX5_QP_OPTPAR_Q_KEY, 3655 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3656 MLX5_QP_OPTPAR_RRE | 3657 MLX5_QP_OPTPAR_RAE | 3658 MLX5_QP_OPTPAR_RWE | 3659 MLX5_QP_OPTPAR_PKEY_INDEX | 3660 MLX5_QP_OPTPAR_LAG_TX_AFF, 3661 }, 3662 }, 3663 [MLX5_QP_STATE_RTR] = { 3664 [MLX5_QP_STATE_RTS] = { 3665 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3666 MLX5_QP_OPTPAR_RRE | 3667 MLX5_QP_OPTPAR_RAE | 3668 MLX5_QP_OPTPAR_RWE | 3669 MLX5_QP_OPTPAR_PM_STATE | 3670 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3671 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3672 MLX5_QP_OPTPAR_RWE | 3673 MLX5_QP_OPTPAR_PM_STATE, 3674 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3675 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 3676 MLX5_QP_OPTPAR_RRE | 3677 MLX5_QP_OPTPAR_RAE | 3678 MLX5_QP_OPTPAR_RWE | 3679 MLX5_QP_OPTPAR_PM_STATE | 3680 MLX5_QP_OPTPAR_RNR_TIMEOUT, 3681 }, 3682 }, 3683 [MLX5_QP_STATE_RTS] = { 3684 [MLX5_QP_STATE_RTS] = { 3685 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 3686 MLX5_QP_OPTPAR_RAE | 3687 MLX5_QP_OPTPAR_RWE | 3688 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3689 MLX5_QP_OPTPAR_PM_STATE | 3690 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3691 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 3692 MLX5_QP_OPTPAR_PM_STATE | 3693 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3694 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 3695 MLX5_QP_OPTPAR_SRQN | 3696 MLX5_QP_OPTPAR_CQN_RCV, 3697 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | 3698 MLX5_QP_OPTPAR_RAE | 3699 MLX5_QP_OPTPAR_RWE | 3700 MLX5_QP_OPTPAR_RNR_TIMEOUT | 3701 MLX5_QP_OPTPAR_PM_STATE | 3702 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 3703 }, 3704 }, 3705 [MLX5_QP_STATE_SQER] = { 3706 [MLX5_QP_STATE_RTS] = { 3707 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3708 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3709 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3710 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3711 MLX5_QP_OPTPAR_RWE | 3712 MLX5_QP_OPTPAR_RAE | 3713 MLX5_QP_OPTPAR_RRE, 3714 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3715 MLX5_QP_OPTPAR_RWE | 3716 MLX5_QP_OPTPAR_RAE | 3717 MLX5_QP_OPTPAR_RRE, 3718 }, 3719 }, 3720 [MLX5_QP_STATE_SQD] = { 3721 [MLX5_QP_STATE_RTS] = { 3722 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 3723 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 3724 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 3725 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 3726 MLX5_QP_OPTPAR_RWE | 3727 MLX5_QP_OPTPAR_RAE | 3728 MLX5_QP_OPTPAR_RRE, 3729 }, 3730 }, 3731 }; 3732 3733 static int ib_nr_to_mlx5_nr(int ib_mask) 3734 { 3735 switch (ib_mask) { 3736 case IB_QP_STATE: 3737 return 0; 3738 case IB_QP_CUR_STATE: 3739 return 0; 3740 case IB_QP_EN_SQD_ASYNC_NOTIFY: 3741 return 0; 3742 case IB_QP_ACCESS_FLAGS: 3743 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 3744 MLX5_QP_OPTPAR_RAE; 3745 case IB_QP_PKEY_INDEX: 3746 return MLX5_QP_OPTPAR_PKEY_INDEX; 3747 case IB_QP_PORT: 3748 return MLX5_QP_OPTPAR_PRI_PORT; 3749 case IB_QP_QKEY: 3750 return MLX5_QP_OPTPAR_Q_KEY; 3751 case IB_QP_AV: 3752 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 3753 MLX5_QP_OPTPAR_PRI_PORT; 3754 case IB_QP_PATH_MTU: 3755 return 0; 3756 case IB_QP_TIMEOUT: 3757 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 3758 case IB_QP_RETRY_CNT: 3759 return MLX5_QP_OPTPAR_RETRY_COUNT; 3760 case IB_QP_RNR_RETRY: 3761 return MLX5_QP_OPTPAR_RNR_RETRY; 3762 case IB_QP_RQ_PSN: 3763 return 0; 3764 case IB_QP_MAX_QP_RD_ATOMIC: 3765 return MLX5_QP_OPTPAR_SRA_MAX; 3766 case IB_QP_ALT_PATH: 3767 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 3768 case IB_QP_MIN_RNR_TIMER: 3769 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 3770 case IB_QP_SQ_PSN: 3771 return 0; 3772 case IB_QP_MAX_DEST_RD_ATOMIC: 3773 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 3774 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 3775 case IB_QP_PATH_MIG_STATE: 3776 return MLX5_QP_OPTPAR_PM_STATE; 3777 case IB_QP_CAP: 3778 return 0; 3779 case IB_QP_DEST_QPN: 3780 return 0; 3781 } 3782 return 0; 3783 } 3784 3785 static int ib_mask_to_mlx5_opt(int ib_mask) 3786 { 3787 int result = 0; 3788 int i; 3789 3790 for (i = 0; i < 8 * sizeof(int); i++) { 3791 if ((1 << i) & ib_mask) 3792 result |= ib_nr_to_mlx5_nr(1 << i); 3793 } 3794 3795 return result; 3796 } 3797 3798 static int modify_raw_packet_qp_rq( 3799 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 3800 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3801 { 3802 void *in; 3803 void *rqc; 3804 int inlen; 3805 int err; 3806 3807 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 3808 in = kvzalloc(inlen, GFP_KERNEL); 3809 if (!in) 3810 return -ENOMEM; 3811 3812 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 3813 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 3814 3815 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 3816 MLX5_SET(rqc, rqc, state, new_state); 3817 3818 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 3819 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 3820 MLX5_SET64(modify_rq_in, in, modify_bitmask, 3821 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 3822 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 3823 } else 3824 dev_info_once( 3825 &dev->ib_dev.dev, 3826 "RAW PACKET QP counters are not supported on current FW\n"); 3827 } 3828 3829 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in); 3830 if (err) 3831 goto out; 3832 3833 rq->state = new_state; 3834 3835 out: 3836 kvfree(in); 3837 return err; 3838 } 3839 3840 static int modify_raw_packet_qp_sq( 3841 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, 3842 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 3843 { 3844 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; 3845 struct mlx5_rate_limit old_rl = ibqp->rl; 3846 struct mlx5_rate_limit new_rl = old_rl; 3847 bool new_rate_added = false; 3848 u16 rl_index = 0; 3849 void *in; 3850 void *sqc; 3851 int inlen; 3852 int err; 3853 3854 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 3855 in = kvzalloc(inlen, GFP_KERNEL); 3856 if (!in) 3857 return -ENOMEM; 3858 3859 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 3860 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 3861 3862 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 3863 MLX5_SET(sqc, sqc, state, new_state); 3864 3865 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { 3866 if (new_state != MLX5_SQC_STATE_RDY) 3867 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", 3868 __func__); 3869 else 3870 new_rl = raw_qp_param->rl; 3871 } 3872 3873 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { 3874 if (new_rl.rate) { 3875 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); 3876 if (err) { 3877 pr_err("Failed configuring rate limit(err %d): \ 3878 rate %u, max_burst_sz %u, typical_pkt_sz %u\n", 3879 err, new_rl.rate, new_rl.max_burst_sz, 3880 new_rl.typical_pkt_sz); 3881 3882 goto out; 3883 } 3884 new_rate_added = true; 3885 } 3886 3887 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); 3888 /* index 0 means no limit */ 3889 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); 3890 } 3891 3892 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in); 3893 if (err) { 3894 /* Remove new rate from table if failed */ 3895 if (new_rate_added) 3896 mlx5_rl_remove_rate(dev, &new_rl); 3897 goto out; 3898 } 3899 3900 /* Only remove the old rate after new rate was set */ 3901 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) || 3902 (new_state != MLX5_SQC_STATE_RDY)) { 3903 mlx5_rl_remove_rate(dev, &old_rl); 3904 if (new_state != MLX5_SQC_STATE_RDY) 3905 memset(&new_rl, 0, sizeof(new_rl)); 3906 } 3907 3908 ibqp->rl = new_rl; 3909 sq->state = new_state; 3910 3911 out: 3912 kvfree(in); 3913 return err; 3914 } 3915 3916 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 3917 const struct mlx5_modify_raw_qp_param *raw_qp_param, 3918 u8 tx_affinity) 3919 { 3920 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 3921 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 3922 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 3923 int modify_rq = !!qp->rq.wqe_cnt; 3924 int modify_sq = !!qp->sq.wqe_cnt; 3925 int rq_state; 3926 int sq_state; 3927 int err; 3928 3929 switch (raw_qp_param->operation) { 3930 case MLX5_CMD_OP_RST2INIT_QP: 3931 rq_state = MLX5_RQC_STATE_RDY; 3932 sq_state = MLX5_SQC_STATE_RST; 3933 break; 3934 case MLX5_CMD_OP_2ERR_QP: 3935 rq_state = MLX5_RQC_STATE_ERR; 3936 sq_state = MLX5_SQC_STATE_ERR; 3937 break; 3938 case MLX5_CMD_OP_2RST_QP: 3939 rq_state = MLX5_RQC_STATE_RST; 3940 sq_state = MLX5_SQC_STATE_RST; 3941 break; 3942 case MLX5_CMD_OP_RTR2RTS_QP: 3943 case MLX5_CMD_OP_RTS2RTS_QP: 3944 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT) 3945 return -EINVAL; 3946 3947 modify_rq = 0; 3948 sq_state = MLX5_SQC_STATE_RDY; 3949 break; 3950 case MLX5_CMD_OP_INIT2INIT_QP: 3951 case MLX5_CMD_OP_INIT2RTR_QP: 3952 if (raw_qp_param->set_mask) 3953 return -EINVAL; 3954 else 3955 return 0; 3956 default: 3957 WARN_ON(1); 3958 return -EINVAL; 3959 } 3960 3961 if (modify_rq) { 3962 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 3963 qp->ibqp.pd); 3964 if (err) 3965 return err; 3966 } 3967 3968 if (modify_sq) { 3969 struct mlx5_flow_handle *flow_rule; 3970 3971 if (tx_affinity) { 3972 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 3973 tx_affinity, 3974 qp->ibqp.pd); 3975 if (err) 3976 return err; 3977 } 3978 3979 flow_rule = create_flow_rule_vport_sq(dev, sq, 3980 raw_qp_param->port); 3981 if (IS_ERR(flow_rule)) 3982 return PTR_ERR(flow_rule); 3983 3984 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, 3985 raw_qp_param, qp->ibqp.pd); 3986 if (err) { 3987 if (flow_rule) 3988 mlx5_del_flow_rules(flow_rule); 3989 return err; 3990 } 3991 3992 if (flow_rule) { 3993 destroy_flow_rule_vport_sq(sq); 3994 sq->flow_rule = flow_rule; 3995 } 3996 3997 return err; 3998 } 3999 4000 return 0; 4001 } 4002 4003 static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev, 4004 struct ib_udata *udata) 4005 { 4006 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 4007 udata, struct mlx5_ib_ucontext, ibucontext); 4008 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4009 atomic_t *tx_port_affinity; 4010 4011 if (ucontext) 4012 tx_port_affinity = &ucontext->tx_port_affinity; 4013 else 4014 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity; 4015 4016 return (unsigned int)atomic_add_return(1, tx_port_affinity) % 4017 (dev->lag_active ? dev->lag_ports : MLX5_CAP_GEN(dev->mdev, num_lag_ports)) + 1; 4018 } 4019 4020 static bool qp_supports_affinity(struct mlx5_ib_qp *qp) 4021 { 4022 if ((qp->type == IB_QPT_RC) || (qp->type == IB_QPT_UD) || 4023 (qp->type == IB_QPT_UC) || (qp->type == IB_QPT_RAW_PACKET) || 4024 (qp->type == IB_QPT_XRC_INI) || (qp->type == IB_QPT_XRC_TGT) || 4025 (qp->type == MLX5_IB_QPT_DCI)) 4026 return true; 4027 return false; 4028 } 4029 4030 static unsigned int get_tx_affinity(struct ib_qp *qp, 4031 const struct ib_qp_attr *attr, 4032 int attr_mask, u8 init, 4033 struct ib_udata *udata) 4034 { 4035 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( 4036 udata, struct mlx5_ib_ucontext, ibucontext); 4037 struct mlx5_ib_dev *dev = to_mdev(qp->device); 4038 struct mlx5_ib_qp *mqp = to_mqp(qp); 4039 struct mlx5_ib_qp_base *qp_base; 4040 unsigned int tx_affinity; 4041 4042 if (!(mlx5_ib_lag_should_assign_affinity(dev) && 4043 qp_supports_affinity(mqp))) 4044 return 0; 4045 4046 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 4047 tx_affinity = mqp->gsi_lag_port; 4048 else if (init) 4049 tx_affinity = get_tx_affinity_rr(dev, udata); 4050 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave) 4051 tx_affinity = 4052 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave); 4053 else 4054 return 0; 4055 4056 qp_base = &mqp->trans_qp.base; 4057 if (ucontext) 4058 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", 4059 tx_affinity, qp_base->mqp.qpn, ucontext); 4060 else 4061 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", 4062 tx_affinity, qp_base->mqp.qpn); 4063 return tx_affinity; 4064 } 4065 4066 static int __mlx5_ib_qp_set_raw_qp_counter(struct mlx5_ib_qp *qp, u32 set_id, 4067 struct mlx5_core_dev *mdev) 4068 { 4069 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4070 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4071 u32 in[MLX5_ST_SZ_DW(modify_rq_in)] = {}; 4072 void *rqc; 4073 4074 if (!qp->rq.wqe_cnt) 4075 return 0; 4076 4077 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 4078 MLX5_SET(modify_rq_in, in, uid, to_mpd(qp->ibqp.pd)->uid); 4079 4080 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 4081 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); 4082 4083 MLX5_SET64(modify_rq_in, in, modify_bitmask, 4084 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 4085 MLX5_SET(rqc, rqc, counter_set_id, set_id); 4086 4087 return mlx5_core_modify_rq(mdev, rq->base.mqp.qpn, in); 4088 } 4089 4090 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, 4091 struct rdma_counter *counter) 4092 { 4093 struct mlx5_ib_dev *dev = to_mdev(qp->device); 4094 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {}; 4095 struct mlx5_ib_qp *mqp = to_mqp(qp); 4096 struct mlx5_ib_qp_base *base; 4097 u32 set_id; 4098 u32 *qpc; 4099 4100 if (counter) 4101 set_id = counter->id; 4102 else 4103 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); 4104 4105 if (mqp->type == IB_QPT_RAW_PACKET) 4106 return __mlx5_ib_qp_set_raw_qp_counter(mqp, set_id, dev->mdev); 4107 4108 base = &mqp->trans_qp.base; 4109 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP); 4110 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn); 4111 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid); 4112 MLX5_SET(rts2rts_qp_in, in, opt_param_mask, 4113 MLX5_QP_OPTPAR_COUNTER_SET_ID); 4114 4115 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc); 4116 MLX5_SET(qpc, qpc, counter_set_id, set_id); 4117 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in); 4118 } 4119 4120 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 4121 const struct ib_qp_attr *attr, int attr_mask, 4122 enum ib_qp_state cur_state, 4123 enum ib_qp_state new_state, 4124 const struct mlx5_ib_modify_qp *ucmd, 4125 struct mlx5_ib_modify_qp_resp *resp, 4126 struct ib_udata *udata) 4127 { 4128 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 4129 [MLX5_QP_STATE_RST] = { 4130 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4131 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4132 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 4133 }, 4134 [MLX5_QP_STATE_INIT] = { 4135 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4136 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4137 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 4138 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 4139 }, 4140 [MLX5_QP_STATE_RTR] = { 4141 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4142 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4143 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 4144 }, 4145 [MLX5_QP_STATE_RTS] = { 4146 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4147 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4148 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 4149 }, 4150 [MLX5_QP_STATE_SQD] = { 4151 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4152 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4153 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQD_RTS_QP, 4154 }, 4155 [MLX5_QP_STATE_SQER] = { 4156 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4157 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4158 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 4159 }, 4160 [MLX5_QP_STATE_ERR] = { 4161 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 4162 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 4163 } 4164 }; 4165 4166 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4167 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4168 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 4169 struct mlx5_ib_cq *send_cq, *recv_cq; 4170 struct mlx5_ib_pd *pd; 4171 enum mlx5_qp_state mlx5_cur, mlx5_new; 4172 void *qpc, *pri_path, *alt_path; 4173 enum mlx5_qp_optpar optpar = 0; 4174 u32 set_id = 0; 4175 int mlx5_st; 4176 int err; 4177 u16 op; 4178 u8 tx_affinity = 0; 4179 4180 mlx5_st = to_mlx5_st(qp->type); 4181 if (mlx5_st < 0) 4182 return -EINVAL; 4183 4184 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL); 4185 if (!qpc) 4186 return -ENOMEM; 4187 4188 pd = to_mpd(qp->ibqp.pd); 4189 MLX5_SET(qpc, qpc, st, mlx5_st); 4190 4191 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 4192 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 4193 } else { 4194 switch (attr->path_mig_state) { 4195 case IB_MIG_MIGRATED: 4196 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 4197 break; 4198 case IB_MIG_REARM: 4199 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM); 4200 break; 4201 case IB_MIG_ARMED: 4202 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED); 4203 break; 4204 } 4205 } 4206 4207 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask, 4208 cur_state == IB_QPS_RESET && 4209 new_state == IB_QPS_INIT, udata); 4210 4211 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity); 4212 if (tx_affinity && new_state == IB_QPS_RTR && 4213 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity)) 4214 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF; 4215 4216 if (is_sqp(qp->type)) { 4217 MLX5_SET(qpc, qpc, mtu, IB_MTU_256); 4218 MLX5_SET(qpc, qpc, log_msg_max, 8); 4219 } else if ((qp->type == IB_QPT_UD && 4220 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) || 4221 qp->type == MLX5_IB_QPT_REG_UMR) { 4222 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096); 4223 MLX5_SET(qpc, qpc, log_msg_max, 12); 4224 } else if (attr_mask & IB_QP_PATH_MTU) { 4225 if (attr->path_mtu < IB_MTU_256 || 4226 attr->path_mtu > IB_MTU_4096) { 4227 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 4228 err = -EINVAL; 4229 goto out; 4230 } 4231 MLX5_SET(qpc, qpc, mtu, attr->path_mtu); 4232 MLX5_SET(qpc, qpc, log_msg_max, 4233 MLX5_CAP_GEN(dev->mdev, log_max_msg)); 4234 } 4235 4236 if (attr_mask & IB_QP_DEST_QPN) 4237 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num); 4238 4239 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 4240 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 4241 4242 if (attr_mask & IB_QP_PKEY_INDEX) 4243 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index); 4244 4245 /* todo implement counter_index functionality */ 4246 4247 if (dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI && is_qp0(qp->type)) { 4248 MLX5_SET(ads, pri_path, vhca_port_num, 4249 smi_to_native_portnum(dev, qp->port)); 4250 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) 4251 MLX5_SET(ads, pri_path, plane_index, qp->port); 4252 } else if (is_sqp(qp->type)) 4253 MLX5_SET(ads, pri_path, vhca_port_num, qp->port); 4254 4255 if (attr_mask & IB_QP_PORT) 4256 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num); 4257 4258 if (attr_mask & IB_QP_AV) { 4259 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path, 4260 attr_mask & IB_QP_PORT ? attr->port_num : 4261 qp->port, 4262 attr_mask, 0, attr, false); 4263 if (err) 4264 goto out; 4265 } 4266 4267 if (attr_mask & IB_QP_TIMEOUT) 4268 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout); 4269 4270 if (attr_mask & IB_QP_ALT_PATH) { 4271 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path, 4272 attr->alt_port_num, 4273 attr_mask | IB_QP_PKEY_INDEX | 4274 IB_QP_TIMEOUT, 4275 0, attr, true); 4276 if (err) 4277 goto out; 4278 } 4279 4280 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 4281 &send_cq, &recv_cq); 4282 4283 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 4284 if (send_cq) 4285 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn); 4286 if (recv_cq) 4287 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn); 4288 4289 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ); 4290 4291 if (attr_mask & IB_QP_RNR_RETRY) 4292 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry); 4293 4294 if (attr_mask & IB_QP_RETRY_CNT) 4295 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt); 4296 4297 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic) 4298 MLX5_SET(qpc, qpc, log_sra_max, fls(attr->max_rd_atomic - 1)); 4299 4300 if (attr_mask & IB_QP_SQ_PSN) 4301 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn); 4302 4303 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic) 4304 MLX5_SET(qpc, qpc, log_rra_max, 4305 fls(attr->max_dest_rd_atomic - 1)); 4306 4307 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 4308 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc); 4309 if (err) 4310 goto out; 4311 } 4312 4313 if (attr_mask & IB_QP_MIN_RNR_TIMER) 4314 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer); 4315 4316 if (attr_mask & IB_QP_RQ_PSN) 4317 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn); 4318 4319 if (attr_mask & IB_QP_QKEY) 4320 MLX5_SET(qpc, qpc, q_key, attr->qkey); 4321 4322 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4323 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 4324 4325 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4326 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 4327 qp->port) - 1; 4328 4329 /* Underlay port should be used - index 0 function per port */ 4330 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) 4331 port_num = 0; 4332 4333 if (ibqp->counter) 4334 set_id = ibqp->counter->id; 4335 else 4336 set_id = mlx5_ib_get_counters_id(dev, port_num); 4337 MLX5_SET(qpc, qpc, counter_set_id, set_id); 4338 } 4339 4340 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 4341 MLX5_SET(qpc, qpc, rlky, 1); 4342 4343 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1) 4344 MLX5_SET(qpc, qpc, deth_sqpn, 1); 4345 4346 if (qp->is_ooo_rq && cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4347 MLX5_SET(qpc, qpc, dp_ordering_1, 1); 4348 MLX5_SET(qpc, qpc, dp_ordering_force, 1); 4349 } 4350 4351 mlx5_cur = to_mlx5_state(cur_state); 4352 mlx5_new = to_mlx5_state(new_state); 4353 4354 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 4355 !optab[mlx5_cur][mlx5_new]) { 4356 err = -EINVAL; 4357 goto out; 4358 } 4359 4360 op = optab[mlx5_cur][mlx5_new]; 4361 optpar |= ib_mask_to_mlx5_opt(attr_mask); 4362 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 4363 4364 if (attr_mask & IB_QP_RATE_LIMIT && qp->type != IB_QPT_RAW_PACKET) { 4365 err = -EOPNOTSUPP; 4366 goto out; 4367 } 4368 4369 if (qp->type == IB_QPT_RAW_PACKET || 4370 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4371 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 4372 4373 raw_qp_param.operation = op; 4374 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4375 raw_qp_param.rq_q_ctr_id = set_id; 4376 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 4377 } 4378 4379 if (attr_mask & IB_QP_PORT) 4380 raw_qp_param.port = attr->port_num; 4381 4382 if (attr_mask & IB_QP_RATE_LIMIT) { 4383 raw_qp_param.rl.rate = attr->rate_limit; 4384 4385 if (ucmd->burst_info.max_burst_sz) { 4386 if (attr->rate_limit && 4387 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { 4388 raw_qp_param.rl.max_burst_sz = 4389 ucmd->burst_info.max_burst_sz; 4390 } else { 4391 err = -EINVAL; 4392 goto out; 4393 } 4394 } 4395 4396 if (ucmd->burst_info.typical_pkt_sz) { 4397 if (attr->rate_limit && 4398 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { 4399 raw_qp_param.rl.typical_pkt_sz = 4400 ucmd->burst_info.typical_pkt_sz; 4401 } else { 4402 err = -EINVAL; 4403 goto out; 4404 } 4405 } 4406 4407 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; 4408 } 4409 4410 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 4411 } else { 4412 if (udata) { 4413 /* For the kernel flows, the resp will stay zero */ 4414 resp->ece_options = 4415 MLX5_CAP_GEN(dev->mdev, ece_support) ? 4416 ucmd->ece_options : 0; 4417 resp->response_length = sizeof(*resp); 4418 } 4419 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp, 4420 &resp->ece_options); 4421 } 4422 4423 if (err) 4424 goto out; 4425 4426 qp->state = new_state; 4427 4428 if (attr_mask & IB_QP_ACCESS_FLAGS) 4429 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 4430 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4431 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 4432 if (attr_mask & IB_QP_PORT) 4433 qp->port = attr->port_num; 4434 if (attr_mask & IB_QP_ALT_PATH) 4435 qp->trans_qp.alt_port = attr->alt_port_num; 4436 4437 /* 4438 * If we moved a kernel QP to RESET, clean up all old CQ 4439 * entries and reinitialize the QP. 4440 */ 4441 if (new_state == IB_QPS_RESET && 4442 !ibqp->uobject && qp->type != IB_QPT_XRC_TGT) { 4443 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 4444 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 4445 if (send_cq != recv_cq) 4446 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 4447 4448 qp->rq.head = 0; 4449 qp->rq.tail = 0; 4450 qp->sq.head = 0; 4451 qp->sq.tail = 0; 4452 qp->sq.cur_post = 0; 4453 if (qp->sq.wqe_cnt) 4454 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); 4455 qp->sq.last_poll = 0; 4456 qp->db.db[MLX5_RCV_DBR] = 0; 4457 qp->db.db[MLX5_SND_DBR] = 0; 4458 } 4459 4460 if ((new_state == IB_QPS_RTS) && qp->counter_pending) { 4461 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter); 4462 if (!err) 4463 qp->counter_pending = 0; 4464 } 4465 4466 out: 4467 kfree(qpc); 4468 return err; 4469 } 4470 4471 static inline bool is_valid_mask(int mask, int req, int opt) 4472 { 4473 if ((mask & req) != req) 4474 return false; 4475 4476 if (mask & ~(req | opt)) 4477 return false; 4478 4479 return true; 4480 } 4481 4482 /* check valid transition for driver QP types 4483 * for now the only QP type that this function supports is DCI 4484 */ 4485 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, 4486 enum ib_qp_attr_mask attr_mask) 4487 { 4488 int req = IB_QP_STATE; 4489 int opt = 0; 4490 4491 if (new_state == IB_QPS_RESET) { 4492 return is_valid_mask(attr_mask, req, opt); 4493 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4494 req |= IB_QP_PKEY_INDEX | IB_QP_PORT; 4495 return is_valid_mask(attr_mask, req, opt); 4496 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4497 opt = IB_QP_PKEY_INDEX | IB_QP_PORT; 4498 return is_valid_mask(attr_mask, req, opt); 4499 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4500 req |= IB_QP_PATH_MTU; 4501 opt = IB_QP_PKEY_INDEX | IB_QP_AV; 4502 return is_valid_mask(attr_mask, req, opt); 4503 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4504 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | 4505 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; 4506 opt = IB_QP_MIN_RNR_TIMER; 4507 return is_valid_mask(attr_mask, req, opt); 4508 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { 4509 opt = IB_QP_MIN_RNR_TIMER; 4510 return is_valid_mask(attr_mask, req, opt); 4511 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { 4512 return is_valid_mask(attr_mask, req, opt); 4513 } 4514 return false; 4515 } 4516 4517 /* mlx5_ib_modify_dct: modify a DCT QP 4518 * valid transitions are: 4519 * RESET to INIT: must set access_flags, pkey_index and port 4520 * INIT to RTR : must set min_rnr_timer, tclass, flow_label, 4521 * mtu, gid_index and hop_limit 4522 * Other transitions and attributes are illegal 4523 */ 4524 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4525 int attr_mask, struct mlx5_ib_modify_qp *ucmd, 4526 struct ib_udata *udata) 4527 { 4528 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4529 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4530 enum ib_qp_state cur_state, new_state; 4531 int required = IB_QP_STATE; 4532 void *dctc; 4533 int err; 4534 4535 if (!(attr_mask & IB_QP_STATE)) 4536 return -EINVAL; 4537 4538 cur_state = qp->state; 4539 new_state = attr->qp_state; 4540 4541 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); 4542 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options) 4543 /* 4544 * DCT doesn't initialize QP till modify command is executed, 4545 * so we need to overwrite previously set ECE field if user 4546 * provided any value except zero, which means not set/not 4547 * valid. 4548 */ 4549 MLX5_SET(dctc, dctc, ece, ucmd->ece_options); 4550 4551 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4552 u16 set_id; 4553 4554 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; 4555 if (!is_valid_mask(attr_mask, required, 0)) 4556 return -EINVAL; 4557 4558 if (attr->port_num == 0 || 4559 attr->port_num > dev->num_ports) { 4560 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4561 attr->port_num, dev->num_ports); 4562 return -EINVAL; 4563 } 4564 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) 4565 MLX5_SET(dctc, dctc, rre, 1); 4566 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) 4567 MLX5_SET(dctc, dctc, rwe, 1); 4568 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { 4569 int atomic_mode; 4570 4571 atomic_mode = get_atomic_mode(dev, qp); 4572 if (atomic_mode < 0) 4573 return -EOPNOTSUPP; 4574 4575 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); 4576 MLX5_SET(dctc, dctc, rae, 1); 4577 } 4578 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); 4579 if (mlx5_lag_is_active(dev->mdev)) 4580 MLX5_SET(dctc, dctc, port, 4581 get_tx_affinity_rr(dev, udata)); 4582 else 4583 MLX5_SET(dctc, dctc, port, attr->port_num); 4584 4585 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1); 4586 MLX5_SET(dctc, dctc, counter_set_id, set_id); 4587 4588 qp->port = attr->port_num; 4589 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4590 struct mlx5_ib_modify_qp_resp resp = {}; 4591 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {}; 4592 u32 min_resp_len = offsetofend(typeof(resp), dctn); 4593 4594 if (udata->outlen < min_resp_len) 4595 return -EINVAL; 4596 /* 4597 * If we don't have enough space for the ECE options, 4598 * simply indicate it with resp.response_length. 4599 */ 4600 resp.response_length = (udata->outlen < sizeof(resp)) ? 4601 min_resp_len : 4602 sizeof(resp); 4603 4604 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; 4605 if (!is_valid_mask(attr_mask, required, 0)) 4606 return -EINVAL; 4607 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); 4608 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); 4609 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); 4610 MLX5_SET(dctc, dctc, mtu, attr->path_mtu); 4611 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); 4612 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); 4613 if (attr->ah_attr.type == RDMA_AH_ATTR_TYPE_ROCE) 4614 MLX5_SET(dctc, dctc, eth_prio, attr->ah_attr.sl & 0x7); 4615 if (qp->is_ooo_rq) { 4616 MLX5_SET(dctc, dctc, dp_ordering_1, 1); 4617 MLX5_SET(dctc, dctc, dp_ordering_force, 1); 4618 } 4619 4620 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in, 4621 MLX5_ST_SZ_BYTES(create_dct_in), out, 4622 sizeof(out)); 4623 err = mlx5_cmd_check(dev->mdev, err, qp->dct.in, out); 4624 if (err) 4625 return err; 4626 resp.dctn = qp->dct.mdct.mqp.qpn; 4627 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 4628 resp.ece_options = MLX5_GET(create_dct_out, out, ece); 4629 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4630 if (err) { 4631 mlx5_core_destroy_dct(dev, &qp->dct.mdct); 4632 return err; 4633 } 4634 } else { 4635 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); 4636 return -EINVAL; 4637 } 4638 4639 qp->state = new_state; 4640 return 0; 4641 } 4642 4643 static bool mlx5_ib_modify_qp_allowed(struct mlx5_ib_dev *dev, 4644 struct mlx5_ib_qp *qp) 4645 { 4646 if (dev->profile != &raw_eth_profile) 4647 return true; 4648 4649 if (qp->type == IB_QPT_RAW_PACKET || qp->type == MLX5_IB_QPT_REG_UMR) 4650 return true; 4651 4652 return false; 4653 } 4654 4655 static int validate_rd_atomic(struct mlx5_ib_dev *dev, struct ib_qp_attr *attr, 4656 int attr_mask, enum ib_qp_type qp_type) 4657 { 4658 int log_max_ra_res; 4659 int log_max_ra_req; 4660 4661 if (qp_type == MLX5_IB_QPT_DCI) { 4662 log_max_ra_res = 1 << MLX5_CAP_GEN(dev->mdev, 4663 log_max_ra_res_dc); 4664 log_max_ra_req = 1 << MLX5_CAP_GEN(dev->mdev, 4665 log_max_ra_req_dc); 4666 } else { 4667 log_max_ra_res = 1 << MLX5_CAP_GEN(dev->mdev, 4668 log_max_ra_res_qp); 4669 log_max_ra_req = 1 << MLX5_CAP_GEN(dev->mdev, 4670 log_max_ra_req_qp); 4671 } 4672 4673 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 4674 attr->max_rd_atomic > log_max_ra_res) { 4675 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 4676 attr->max_rd_atomic); 4677 return false; 4678 } 4679 4680 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 4681 attr->max_dest_rd_atomic > log_max_ra_req) { 4682 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 4683 attr->max_dest_rd_atomic); 4684 return false; 4685 } 4686 return true; 4687 } 4688 4689 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 4690 int attr_mask, struct ib_udata *udata) 4691 { 4692 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4693 struct mlx5_ib_modify_qp_resp resp = {}; 4694 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4695 struct mlx5_ib_modify_qp ucmd; 4696 enum ib_qp_type qp_type; 4697 enum ib_qp_state cur_state, new_state; 4698 int err = -EINVAL; 4699 4700 if (!mlx5_ib_modify_qp_allowed(dev, qp)) 4701 return -EOPNOTSUPP; 4702 4703 if (attr_mask & ~(IB_QP_ATTR_STANDARD_BITS | IB_QP_RATE_LIMIT)) 4704 return -EOPNOTSUPP; 4705 4706 if (ibqp->rwq_ind_tbl) 4707 return -ENOSYS; 4708 4709 if (udata && udata->inlen) { 4710 err = ib_copy_validate_udata_in_cm(udata, ucmd, ece_options, 4711 MLX5_IB_MODIFY_QP_OOO_DP); 4712 if (err) 4713 return err; 4714 4715 if (memchr_inv(&ucmd.burst_info.reserved, 0, 4716 sizeof(ucmd.burst_info.reserved))) 4717 return -EOPNOTSUPP; 4718 4719 if (ucmd.comp_mask & MLX5_IB_MODIFY_QP_OOO_DP) { 4720 if (!get_dp_ooo_cap(dev->mdev, qp->type)) 4721 return -EOPNOTSUPP; 4722 qp->is_ooo_rq = 1; 4723 } 4724 } 4725 4726 if (qp->type == IB_QPT_GSI) 4727 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 4728 4729 qp_type = (qp->type == MLX5_IB_QPT_HW_GSI) ? IB_QPT_GSI : qp->type; 4730 4731 if (qp_type == MLX5_IB_QPT_DCT) 4732 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata); 4733 4734 mutex_lock(&qp->mutex); 4735 4736 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 4737 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 4738 4739 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) { 4740 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { 4741 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", 4742 attr_mask); 4743 goto out; 4744 } 4745 } else if (qp_type != MLX5_IB_QPT_REG_UMR && 4746 qp_type != MLX5_IB_QPT_DCI && 4747 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, 4748 attr_mask)) { 4749 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4750 cur_state, new_state, qp->type, attr_mask); 4751 goto out; 4752 } else if (qp_type == MLX5_IB_QPT_DCI && 4753 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { 4754 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 4755 cur_state, new_state, qp_type, attr_mask); 4756 goto out; 4757 } 4758 4759 if ((attr_mask & IB_QP_PORT) && 4760 (attr->port_num == 0 || 4761 attr->port_num > dev->num_ports)) { 4762 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 4763 attr->port_num, dev->num_ports); 4764 goto out; 4765 } 4766 4767 if ((attr_mask & IB_QP_PKEY_INDEX) && 4768 attr->pkey_index >= dev->pkey_table_len) { 4769 mlx5_ib_dbg(dev, "invalid pkey index %d\n", attr->pkey_index); 4770 goto out; 4771 } 4772 4773 if (!validate_rd_atomic(dev, attr, attr_mask, qp_type)) 4774 goto out; 4775 4776 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 4777 err = 0; 4778 goto out; 4779 } 4780 4781 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, 4782 new_state, &ucmd, &resp, udata); 4783 4784 /* resp.response_length is set in ECE supported flows only */ 4785 if (!err && resp.response_length && 4786 udata->outlen >= resp.response_length) 4787 /* Return -EFAULT to the user and expect him to destroy QP. */ 4788 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4789 4790 out: 4791 mutex_unlock(&qp->mutex); 4792 return err; 4793 } 4794 4795 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4796 { 4797 switch (mlx5_state) { 4798 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4799 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4800 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4801 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4802 case MLX5_QP_STATE_SQ_DRAINING: 4803 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4804 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4805 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4806 default: return -1; 4807 } 4808 } 4809 4810 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4811 { 4812 switch (mlx5_mig_state) { 4813 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4814 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4815 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4816 default: return -1; 4817 } 4818 } 4819 4820 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, 4821 struct rdma_ah_attr *ah_attr, void *path) 4822 { 4823 int port = MLX5_GET(ads, path, vhca_port_num); 4824 int static_rate; 4825 4826 memset(ah_attr, 0, sizeof(*ah_attr)); 4827 4828 if (!port || port > ibdev->num_ports) 4829 return; 4830 4831 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port); 4832 4833 rdma_ah_set_port_num(ah_attr, port); 4834 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl)); 4835 4836 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid)); 4837 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid)); 4838 4839 static_rate = MLX5_GET(ads, path, stat_rate); 4840 rdma_ah_set_static_rate(ah_attr, mlx5_to_ib_rate_map(static_rate)); 4841 if (MLX5_GET(ads, path, grh) || 4842 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) { 4843 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label), 4844 MLX5_GET(ads, path, src_addr_index), 4845 MLX5_GET(ads, path, hop_limit), 4846 MLX5_GET(ads, path, tclass)); 4847 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip)); 4848 } 4849 } 4850 4851 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4852 struct mlx5_ib_sq *sq, 4853 u8 *sq_state) 4854 { 4855 int err; 4856 4857 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); 4858 if (err) 4859 goto out; 4860 sq->state = *sq_state; 4861 4862 out: 4863 return err; 4864 } 4865 4866 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4867 struct mlx5_ib_rq *rq, 4868 u8 *rq_state) 4869 { 4870 void *out; 4871 void *rqc; 4872 int inlen; 4873 int err; 4874 4875 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4876 out = kvzalloc(inlen, GFP_KERNEL); 4877 if (!out) 4878 return -ENOMEM; 4879 4880 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4881 if (err) 4882 goto out; 4883 4884 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4885 *rq_state = MLX5_GET(rqc, rqc, state); 4886 rq->state = *rq_state; 4887 4888 out: 4889 kvfree(out); 4890 return err; 4891 } 4892 4893 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4894 struct mlx5_ib_qp *qp, u8 *qp_state) 4895 { 4896 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4897 [MLX5_RQC_STATE_RST] = { 4898 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4899 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4900 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4901 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4902 }, 4903 [MLX5_RQC_STATE_RDY] = { 4904 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4905 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4906 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4907 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4908 }, 4909 [MLX5_RQC_STATE_ERR] = { 4910 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4911 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4912 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4913 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4914 }, 4915 [MLX5_RQ_STATE_NA] = { 4916 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE, 4917 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4918 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4919 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4920 }, 4921 }; 4922 4923 *qp_state = sqrq_trans[rq_state][sq_state]; 4924 4925 if (*qp_state == MLX5_QP_STATE_BAD) { 4926 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4927 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4928 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4929 return -EINVAL; 4930 } 4931 4932 if (*qp_state == MLX5_QP_STATE) 4933 *qp_state = qp->state; 4934 4935 return 0; 4936 } 4937 4938 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4939 struct mlx5_ib_qp *qp, 4940 u8 *raw_packet_qp_state) 4941 { 4942 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4943 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4944 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4945 int err; 4946 u8 sq_state = MLX5_SQ_STATE_NA; 4947 u8 rq_state = MLX5_RQ_STATE_NA; 4948 4949 if (qp->sq.wqe_cnt) { 4950 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4951 if (err) 4952 return err; 4953 } 4954 4955 if (qp->rq.wqe_cnt) { 4956 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4957 if (err) 4958 return err; 4959 } 4960 4961 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4962 raw_packet_qp_state); 4963 } 4964 4965 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4966 struct ib_qp_attr *qp_attr) 4967 { 4968 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4969 void *qpc, *pri_path, *alt_path; 4970 u32 *outb; 4971 int err; 4972 4973 outb = kzalloc(outlen, GFP_KERNEL); 4974 if (!outb) 4975 return -ENOMEM; 4976 4977 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen, 4978 false); 4979 if (err) 4980 goto out; 4981 4982 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc); 4983 4984 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state)); 4985 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING) 4986 qp_attr->sq_draining = 1; 4987 4988 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu); 4989 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state)); 4990 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key); 4991 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn); 4992 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn); 4993 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn); 4994 4995 if (MLX5_GET(qpc, qpc, rre)) 4996 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ; 4997 if (MLX5_GET(qpc, qpc, rwe)) 4998 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE; 4999 if (MLX5_GET(qpc, qpc, rae)) 5000 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5001 5002 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max); 5003 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max); 5004 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak); 5005 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count); 5006 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry); 5007 5008 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path); 5009 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path); 5010 5011 if (qp->type == IB_QPT_RC || qp->type == IB_QPT_UC || 5012 qp->type == IB_QPT_XRC_INI || qp->type == IB_QPT_XRC_TGT) { 5013 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path); 5014 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path); 5015 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index); 5016 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num); 5017 } 5018 5019 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index); 5020 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num); 5021 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout); 5022 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout); 5023 5024 out: 5025 kfree(outb); 5026 return err; 5027 } 5028 5029 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, 5030 struct ib_qp_attr *qp_attr, int qp_attr_mask, 5031 struct ib_qp_init_attr *qp_init_attr) 5032 { 5033 struct mlx5_core_dct *dct = &mqp->dct.mdct; 5034 u32 *out; 5035 u32 access_flags = 0; 5036 int outlen = MLX5_ST_SZ_BYTES(query_dct_out); 5037 void *dctc; 5038 int err; 5039 int supported_mask = IB_QP_STATE | 5040 IB_QP_ACCESS_FLAGS | 5041 IB_QP_PORT | 5042 IB_QP_MIN_RNR_TIMER | 5043 IB_QP_AV | 5044 IB_QP_PATH_MTU | 5045 IB_QP_PKEY_INDEX; 5046 5047 if (qp_attr_mask & ~supported_mask) 5048 return -EINVAL; 5049 if (mqp->state != IB_QPS_RTR) 5050 return -EINVAL; 5051 5052 out = kzalloc(outlen, GFP_KERNEL); 5053 if (!out) 5054 return -ENOMEM; 5055 5056 err = mlx5_core_dct_query(dev, dct, out, outlen); 5057 if (err) 5058 goto out; 5059 5060 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); 5061 5062 if (qp_attr_mask & IB_QP_STATE) 5063 qp_attr->qp_state = IB_QPS_RTR; 5064 5065 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 5066 if (MLX5_GET(dctc, dctc, rre)) 5067 access_flags |= IB_ACCESS_REMOTE_READ; 5068 if (MLX5_GET(dctc, dctc, rwe)) 5069 access_flags |= IB_ACCESS_REMOTE_WRITE; 5070 if (MLX5_GET(dctc, dctc, rae)) 5071 access_flags |= IB_ACCESS_REMOTE_ATOMIC; 5072 qp_attr->qp_access_flags = access_flags; 5073 } 5074 5075 if (qp_attr_mask & IB_QP_PORT) 5076 qp_attr->port_num = mqp->port; 5077 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) 5078 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); 5079 if (qp_attr_mask & IB_QP_AV) { 5080 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); 5081 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); 5082 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); 5083 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); 5084 } 5085 if (qp_attr_mask & IB_QP_PATH_MTU) 5086 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); 5087 if (qp_attr_mask & IB_QP_PKEY_INDEX) 5088 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); 5089 out: 5090 kfree(out); 5091 return err; 5092 } 5093 5094 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5095 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 5096 { 5097 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 5098 struct mlx5_ib_qp *qp = to_mqp(ibqp); 5099 int err = 0; 5100 u8 raw_packet_qp_state; 5101 5102 if (ibqp->rwq_ind_tbl) 5103 return -ENOSYS; 5104 5105 if (qp->type == IB_QPT_GSI) 5106 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 5107 qp_init_attr); 5108 5109 /* Not all of output fields are applicable, make sure to zero them */ 5110 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5111 memset(qp_attr, 0, sizeof(*qp_attr)); 5112 5113 if (unlikely(qp->type == MLX5_IB_QPT_DCT)) 5114 return mlx5_ib_dct_query_qp(dev, qp, qp_attr, 5115 qp_attr_mask, qp_init_attr); 5116 5117 mutex_lock(&qp->mutex); 5118 5119 if (qp->type == IB_QPT_RAW_PACKET || 5120 qp->flags & IB_QP_CREATE_SOURCE_QPN) { 5121 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 5122 if (err) 5123 goto out; 5124 qp->state = raw_packet_qp_state; 5125 qp_attr->port_num = 1; 5126 } else { 5127 err = query_qp_attr(dev, qp, qp_attr); 5128 if (err) 5129 goto out; 5130 } 5131 5132 qp_attr->qp_state = qp->state; 5133 qp_attr->cur_qp_state = qp_attr->qp_state; 5134 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 5135 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 5136 5137 if (!ibqp->uobject) { 5138 qp_attr->cap.max_send_wr = qp->sq.max_post; 5139 qp_attr->cap.max_send_sge = qp->sq.max_gs; 5140 qp_init_attr->qp_context = ibqp->qp_context; 5141 } else { 5142 qp_attr->cap.max_send_wr = 0; 5143 qp_attr->cap.max_send_sge = 0; 5144 } 5145 5146 qp_init_attr->qp_type = qp->type; 5147 qp_init_attr->recv_cq = ibqp->recv_cq; 5148 qp_init_attr->send_cq = ibqp->send_cq; 5149 qp_init_attr->srq = ibqp->srq; 5150 qp_attr->cap.max_inline_data = qp->max_inline_data; 5151 5152 qp_init_attr->cap = qp_attr->cap; 5153 5154 qp_init_attr->create_flags = qp->flags; 5155 5156 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 5157 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 5158 5159 out: 5160 mutex_unlock(&qp->mutex); 5161 return err; 5162 } 5163 5164 int mlx5_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata) 5165 { 5166 struct mlx5_ib_dev *dev = to_mdev(ibxrcd->device); 5167 struct mlx5_ib_xrcd *xrcd = to_mxrcd(ibxrcd); 5168 5169 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 5170 return -EOPNOTSUPP; 5171 5172 return mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); 5173 } 5174 5175 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 5176 { 5177 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 5178 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 5179 5180 return mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); 5181 } 5182 5183 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 5184 { 5185 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 5186 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 5187 struct ib_event event; 5188 5189 if (rwq->ibwq.event_handler) { 5190 event.device = rwq->ibwq.device; 5191 event.element.wq = &rwq->ibwq; 5192 switch (type) { 5193 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 5194 event.event = IB_EVENT_WQ_FATAL; 5195 break; 5196 default: 5197 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 5198 return; 5199 } 5200 5201 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 5202 } 5203 } 5204 5205 static int set_delay_drop(struct mlx5_ib_dev *dev) 5206 { 5207 int err = 0; 5208 5209 mutex_lock(&dev->delay_drop.lock); 5210 if (dev->delay_drop.activate) 5211 goto out; 5212 5213 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout); 5214 if (err) 5215 goto out; 5216 5217 dev->delay_drop.activate = true; 5218 out: 5219 mutex_unlock(&dev->delay_drop.lock); 5220 5221 if (!err) 5222 atomic_inc(&dev->delay_drop.rqs_cnt); 5223 return err; 5224 } 5225 5226 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 5227 struct ib_wq_init_attr *init_attr) 5228 { 5229 struct mlx5_ib_dev *dev; 5230 int has_net_offloads; 5231 __be64 *rq_pas0; 5232 int ts_format; 5233 void *in; 5234 void *rqc; 5235 void *wq; 5236 int inlen; 5237 int err; 5238 5239 dev = to_mdev(pd->device); 5240 5241 ts_format = get_rq_ts_format(dev, to_mcq(init_attr->cq)); 5242 if (ts_format < 0) 5243 return ts_format; 5244 5245 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 5246 in = kvzalloc(inlen, GFP_KERNEL); 5247 if (!in) 5248 return -ENOMEM; 5249 5250 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 5251 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 5252 MLX5_SET(rqc, rqc, mem_rq_type, 5253 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); 5254 MLX5_SET(rqc, rqc, ts_format, ts_format); 5255 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 5256 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 5257 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 5258 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 5259 wq = MLX5_ADDR_OF(rqc, rqc, wq); 5260 MLX5_SET(wq, wq, wq_type, 5261 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? 5262 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); 5263 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5264 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { 5265 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); 5266 err = -EOPNOTSUPP; 5267 goto out; 5268 } else { 5269 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 5270 } 5271 } 5272 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 5273 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { 5274 /* 5275 * In Firmware number of strides in each WQE is: 5276 * "512 * 2^single_wqe_log_num_of_strides" 5277 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are 5278 * accepted as 0 to 9 5279 */ 5280 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1, 5281 2, 3, 4, 5, 6, 7, 8, 9 }; 5282 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); 5283 MLX5_SET(wq, wq, log_wqe_stride_size, 5284 rwq->single_stride_log_num_of_bytes - 5285 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); 5286 MLX5_SET(wq, wq, log_wqe_num_of_strides, 5287 fw_map[rwq->log_num_strides - 5288 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]); 5289 } 5290 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 5291 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 5292 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 5293 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 5294 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 5295 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 5296 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); 5297 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5298 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5299 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5300 err = -EOPNOTSUPP; 5301 goto out; 5302 } 5303 } else { 5304 MLX5_SET(rqc, rqc, vsd, 1); 5305 } 5306 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { 5307 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { 5308 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); 5309 err = -EOPNOTSUPP; 5310 goto out; 5311 } 5312 MLX5_SET(rqc, rqc, scatter_fcs, 1); 5313 } 5314 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5315 if (!(dev->ib_dev.attrs.raw_packet_caps & 5316 IB_RAW_PACKET_CAP_DELAY_DROP)) { 5317 mlx5_ib_dbg(dev, "Delay drop is not supported\n"); 5318 err = -EOPNOTSUPP; 5319 goto out; 5320 } 5321 MLX5_SET(rqc, rqc, delay_drop_en, 1); 5322 } 5323 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 5324 mlx5_ib_populate_pas(rwq->umem, 1UL << rwq->page_shift, rq_pas0, 0); 5325 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp); 5326 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { 5327 err = set_delay_drop(dev); 5328 if (err) { 5329 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", 5330 err); 5331 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5332 } else { 5333 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; 5334 } 5335 } 5336 out: 5337 kvfree(in); 5338 return err; 5339 } 5340 5341 static int set_user_rq_size(struct mlx5_ib_dev *dev, 5342 struct ib_wq_init_attr *wq_init_attr, 5343 struct mlx5_ib_create_wq *ucmd, 5344 struct mlx5_ib_rwq *rwq) 5345 { 5346 /* Sanity check RQ size before proceeding */ 5347 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 5348 return -EINVAL; 5349 5350 if (!ucmd->rq_wqe_count) 5351 return -EINVAL; 5352 5353 rwq->wqe_count = ucmd->rq_wqe_count; 5354 rwq->wqe_shift = ucmd->rq_wqe_shift; 5355 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) 5356 return -EINVAL; 5357 5358 rwq->log_rq_stride = rwq->wqe_shift; 5359 rwq->log_rq_size = ilog2(rwq->wqe_count); 5360 return 0; 5361 } 5362 5363 static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides) 5364 { 5365 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || 5366 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5367 return false; 5368 5369 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) && 5370 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) 5371 return false; 5372 5373 return true; 5374 } 5375 5376 static int prepare_user_rq(struct ib_pd *pd, 5377 struct ib_wq_init_attr *init_attr, 5378 struct ib_udata *udata, 5379 struct mlx5_ib_rwq *rwq) 5380 { 5381 struct mlx5_ib_dev *dev = to_mdev(pd->device); 5382 struct mlx5_ib_create_wq ucmd; 5383 int err; 5384 5385 err = ib_copy_validate_udata_in_cm(udata, ucmd, 5386 single_stride_log_num_of_bytes, 5387 MLX5_IB_CREATE_WQ_STRIDING_RQ); 5388 if (err) { 5389 mlx5_ib_dbg(dev, "copy failed\n"); 5390 return err; 5391 } 5392 5393 if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { 5394 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { 5395 mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); 5396 return -EOPNOTSUPP; 5397 } 5398 if ((ucmd.single_stride_log_num_of_bytes < 5399 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || 5400 (ucmd.single_stride_log_num_of_bytes > 5401 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { 5402 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", 5403 ucmd.single_stride_log_num_of_bytes, 5404 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, 5405 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); 5406 return -EINVAL; 5407 } 5408 if (!log_of_strides_valid(dev, 5409 ucmd.single_wqe_log_num_of_strides)) { 5410 mlx5_ib_dbg( 5411 dev, 5412 "Invalid log num strides (%u. Range is %u - %u)\n", 5413 ucmd.single_wqe_log_num_of_strides, 5414 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ? 5415 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES : 5416 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, 5417 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); 5418 return -EINVAL; 5419 } 5420 rwq->single_stride_log_num_of_bytes = 5421 ucmd.single_stride_log_num_of_bytes; 5422 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; 5423 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; 5424 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; 5425 } 5426 5427 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 5428 if (err) { 5429 mlx5_ib_dbg(dev, "err %d\n", err); 5430 return err; 5431 } 5432 5433 err = create_user_rq(dev, pd, udata, rwq, &ucmd); 5434 if (err) { 5435 mlx5_ib_dbg(dev, "err %d\n", err); 5436 return err; 5437 } 5438 5439 rwq->user_index = ucmd.user_index; 5440 return 0; 5441 } 5442 5443 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 5444 struct ib_wq_init_attr *init_attr, 5445 struct ib_udata *udata) 5446 { 5447 struct mlx5_ib_dev *dev; 5448 struct mlx5_ib_rwq *rwq; 5449 struct mlx5_ib_create_wq_resp resp = {}; 5450 size_t min_resp_len; 5451 int err; 5452 5453 if (!udata) 5454 return ERR_PTR(-ENOSYS); 5455 5456 min_resp_len = offsetofend(struct mlx5_ib_create_wq_resp, reserved); 5457 if (udata->outlen && udata->outlen < min_resp_len) 5458 return ERR_PTR(-EINVAL); 5459 5460 if (!capable(CAP_SYS_RAWIO) && 5461 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) 5462 return ERR_PTR(-EPERM); 5463 5464 dev = to_mdev(pd->device); 5465 switch (init_attr->wq_type) { 5466 case IB_WQT_RQ: 5467 rwq = kzalloc_obj(*rwq); 5468 if (!rwq) 5469 return ERR_PTR(-ENOMEM); 5470 err = prepare_user_rq(pd, init_attr, udata, rwq); 5471 if (err) 5472 goto err; 5473 err = create_rq(rwq, pd, init_attr); 5474 if (err) 5475 goto err_user_rq; 5476 break; 5477 default: 5478 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 5479 init_attr->wq_type); 5480 return ERR_PTR(-EINVAL); 5481 } 5482 5483 rwq->ibwq.wq_num = rwq->core_qp.qpn; 5484 rwq->ibwq.state = IB_WQS_RESET; 5485 if (udata->outlen) { 5486 resp.response_length = offsetofend( 5487 struct mlx5_ib_create_wq_resp, response_length); 5488 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5489 if (err) 5490 goto err_copy; 5491 } 5492 5493 rwq->core_qp.event = mlx5_ib_wq_event; 5494 rwq->ibwq.event_handler = init_attr->event_handler; 5495 return &rwq->ibwq; 5496 5497 err_copy: 5498 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5499 err_user_rq: 5500 destroy_user_rq(dev, pd, rwq, udata); 5501 err: 5502 kfree(rwq); 5503 return ERR_PTR(err); 5504 } 5505 5506 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 5507 { 5508 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5509 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5510 int ret; 5511 5512 ret = mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp); 5513 if (ret) 5514 return ret; 5515 destroy_user_rq(dev, wq->pd, rwq, udata); 5516 kfree(rwq); 5517 return 0; 5518 } 5519 5520 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 5521 struct ib_rwq_ind_table_init_attr *init_attr, 5522 struct ib_udata *udata) 5523 { 5524 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = 5525 to_mrwq_ind_table(ib_rwq_ind_table); 5526 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_table->device); 5527 int sz = 1 << init_attr->log_ind_tbl_size; 5528 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 5529 size_t min_resp_len; 5530 int inlen; 5531 int err; 5532 int i; 5533 u32 *in; 5534 void *rqtc; 5535 5536 if (udata->inlen > 0 && 5537 !ib_is_udata_cleared(udata, 0, 5538 udata->inlen)) 5539 return -EOPNOTSUPP; 5540 5541 if (init_attr->log_ind_tbl_size > 5542 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 5543 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 5544 init_attr->log_ind_tbl_size, 5545 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 5546 return -EINVAL; 5547 } 5548 5549 min_resp_len = 5550 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, reserved); 5551 if (udata->outlen && udata->outlen < min_resp_len) 5552 return -EINVAL; 5553 5554 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 5555 in = kvzalloc(inlen, GFP_KERNEL); 5556 if (!in) 5557 return -ENOMEM; 5558 5559 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 5560 5561 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 5562 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 5563 5564 for (i = 0; i < sz; i++) 5565 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 5566 5567 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 5568 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 5569 5570 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 5571 kvfree(in); 5572 if (err) 5573 return err; 5574 5575 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 5576 if (udata->outlen) { 5577 resp.response_length = 5578 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, 5579 response_length); 5580 err = ib_copy_to_udata(udata, &resp, resp.response_length); 5581 if (err) 5582 goto err_copy; 5583 } 5584 5585 return 0; 5586 5587 err_copy: 5588 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5589 return err; 5590 } 5591 5592 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 5593 { 5594 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 5595 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 5596 5597 return mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 5598 } 5599 5600 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 5601 u32 wq_attr_mask, struct ib_udata *udata) 5602 { 5603 struct mlx5_ib_dev *dev = to_mdev(wq->device); 5604 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 5605 struct mlx5_ib_modify_wq ucmd = {}; 5606 int curr_wq_state; 5607 int wq_state; 5608 int inlen; 5609 int err; 5610 void *rqc; 5611 void *in; 5612 5613 err = ib_copy_validate_udata_in_cm(udata, ucmd, reserved, 0); 5614 if (err) 5615 return err; 5616 5617 if (ucmd.reserved) 5618 return -EOPNOTSUPP; 5619 5620 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5621 in = kvzalloc(inlen, GFP_KERNEL); 5622 if (!in) 5623 return -ENOMEM; 5624 5625 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5626 5627 curr_wq_state = wq_attr->curr_wq_state; 5628 wq_state = wq_attr->wq_state; 5629 if (curr_wq_state == IB_WQS_ERR) 5630 curr_wq_state = MLX5_RQC_STATE_ERR; 5631 if (wq_state == IB_WQS_ERR) 5632 wq_state = MLX5_RQC_STATE_ERR; 5633 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5634 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 5635 MLX5_SET(rqc, rqc, state, wq_state); 5636 5637 if (wq_attr_mask & IB_WQ_FLAGS) { 5638 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { 5639 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 5640 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { 5641 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); 5642 err = -EOPNOTSUPP; 5643 goto out; 5644 } 5645 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5646 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 5647 MLX5_SET(rqc, rqc, vsd, 5648 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); 5649 } 5650 5651 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { 5652 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); 5653 err = -EOPNOTSUPP; 5654 goto out; 5655 } 5656 } 5657 5658 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { 5659 u16 set_id; 5660 5661 set_id = mlx5_ib_get_counters_id(dev, 0); 5662 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { 5663 MLX5_SET64(modify_rq_in, in, modify_bitmask, 5664 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); 5665 MLX5_SET(rqc, rqc, counter_set_id, set_id); 5666 } else 5667 dev_info_once( 5668 &dev->ib_dev.dev, 5669 "Receive WQ counters are not supported on current FW\n"); 5670 } 5671 5672 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in); 5673 if (!err) 5674 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5675 5676 out: 5677 kvfree(in); 5678 return err; 5679 } 5680 5681 struct mlx5_ib_drain_cqe { 5682 struct ib_cqe cqe; 5683 struct completion done; 5684 }; 5685 5686 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 5687 { 5688 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 5689 struct mlx5_ib_drain_cqe, 5690 cqe); 5691 5692 complete(&cqe->done); 5693 } 5694 5695 /* This function returns only once the drained WR was completed */ 5696 static void handle_drain_completion(struct ib_cq *cq, 5697 struct mlx5_ib_drain_cqe *sdrain, 5698 struct mlx5_ib_dev *dev) 5699 { 5700 struct mlx5_core_dev *mdev = dev->mdev; 5701 5702 if (cq->poll_ctx == IB_POLL_DIRECT) { 5703 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 5704 ib_process_cq_direct(cq, -1); 5705 return; 5706 } 5707 5708 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5709 struct mlx5_ib_cq *mcq = to_mcq(cq); 5710 bool triggered = false; 5711 unsigned long flags; 5712 5713 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 5714 /* Make sure that the CQ handler won't run if wasn't run yet */ 5715 if (!mcq->mcq.reset_notify_added) 5716 mcq->mcq.reset_notify_added = 1; 5717 else 5718 triggered = true; 5719 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 5720 5721 if (triggered) { 5722 /* Wait for any scheduled/running task to be ended */ 5723 switch (cq->poll_ctx) { 5724 case IB_POLL_SOFTIRQ: 5725 irq_poll_disable(&cq->iop); 5726 irq_poll_enable(&cq->iop); 5727 break; 5728 case IB_POLL_WORKQUEUE: 5729 cancel_work_sync(&cq->work); 5730 break; 5731 default: 5732 WARN_ON_ONCE(1); 5733 } 5734 } 5735 5736 /* Run the CQ handler - this makes sure that the drain WR will 5737 * be processed if wasn't processed yet. 5738 */ 5739 mcq->mcq.comp(&mcq->mcq, NULL); 5740 } 5741 5742 wait_for_completion(&sdrain->done); 5743 } 5744 5745 void mlx5_ib_drain_sq(struct ib_qp *qp) 5746 { 5747 struct ib_cq *cq = qp->send_cq; 5748 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5749 struct mlx5_ib_drain_cqe sdrain; 5750 const struct ib_send_wr *bad_swr; 5751 struct ib_rdma_wr swr = { 5752 .wr = { 5753 .next = NULL, 5754 { .wr_cqe = &sdrain.cqe, }, 5755 .opcode = IB_WR_RDMA_WRITE, 5756 }, 5757 }; 5758 int ret; 5759 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5760 struct mlx5_core_dev *mdev = dev->mdev; 5761 5762 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5763 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5764 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5765 return; 5766 } 5767 5768 sdrain.cqe.done = mlx5_ib_drain_qp_done; 5769 init_completion(&sdrain.done); 5770 5771 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr); 5772 if (ret) { 5773 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 5774 return; 5775 } 5776 5777 handle_drain_completion(cq, &sdrain, dev); 5778 } 5779 5780 void mlx5_ib_drain_rq(struct ib_qp *qp) 5781 { 5782 struct ib_cq *cq = qp->recv_cq; 5783 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 5784 struct mlx5_ib_drain_cqe rdrain; 5785 struct ib_recv_wr rwr = {}; 5786 const struct ib_recv_wr *bad_rwr; 5787 int ret; 5788 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5789 struct mlx5_core_dev *mdev = dev->mdev; 5790 5791 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 5792 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 5793 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5794 return; 5795 } 5796 5797 rwr.wr_cqe = &rdrain.cqe; 5798 rdrain.cqe.done = mlx5_ib_drain_qp_done; 5799 init_completion(&rdrain.done); 5800 5801 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr); 5802 if (ret) { 5803 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 5804 return; 5805 } 5806 5807 handle_drain_completion(cq, &rdrain, dev); 5808 } 5809 5810 /* 5811 * Bind a qp to a counter. If @counter is NULL then bind the qp to 5812 * the default counter 5813 */ 5814 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter) 5815 { 5816 struct mlx5_ib_dev *dev = to_mdev(qp->device); 5817 struct mlx5_ib_qp *mqp = to_mqp(qp); 5818 int err = 0; 5819 5820 mutex_lock(&mqp->mutex); 5821 if (mqp->state == IB_QPS_RESET) { 5822 qp->counter = counter; 5823 goto out; 5824 } 5825 5826 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) { 5827 err = -EOPNOTSUPP; 5828 goto out; 5829 } 5830 5831 if (mqp->state == IB_QPS_RTS) { 5832 err = __mlx5_ib_qp_set_counter(qp, counter); 5833 if (!err) 5834 qp->counter = counter; 5835 5836 goto out; 5837 } 5838 5839 mqp->counter_pending = 1; 5840 qp->counter = counter; 5841 5842 out: 5843 mutex_unlock(&mqp->mutex); 5844 return err; 5845 } 5846 5847 int mlx5_ib_qp_event_init(void) 5848 { 5849 mlx5_ib_qp_event_wq = alloc_ordered_workqueue("mlx5_ib_qp_event_wq", 0); 5850 if (!mlx5_ib_qp_event_wq) 5851 return -ENOMEM; 5852 5853 return 0; 5854 } 5855 5856 void mlx5_ib_qp_event_cleanup(void) 5857 { 5858 destroy_workqueue(mlx5_ib_qp_event_wq); 5859 } 5860