1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5 */
6
7 #include <linux/fips.h>
8 #include <linux/ieee80211.h>
9 #include <linux/kernel.h>
10 #include <linux/skbuff.h>
11 #include "core.h"
12 #include "debug.h"
13 #include "debugfs_htt_stats.h"
14 #include "debugfs_sta.h"
15 #include "hal_desc.h"
16 #include "hw.h"
17 #include "dp_rx.h"
18 #include "hal_rx.h"
19 #include "dp_tx.h"
20 #include "peer.h"
21
22 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
23
24 static inline
ath11k_dp_rx_h_80211_hdr(struct ath11k_base * ab,struct hal_rx_desc * desc)25 u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc)
26 {
27 return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc);
28 }
29
30 static inline
ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base * ab,struct hal_rx_desc * desc)31 enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab,
32 struct hal_rx_desc *desc)
33 {
34 if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc))
35 return HAL_ENCRYPT_TYPE_OPEN;
36
37 return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc);
38 }
39
ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base * ab,struct hal_rx_desc * desc)40 static inline u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab,
41 struct hal_rx_desc *desc)
42 {
43 return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc);
44 }
45
46 static inline
ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base * ab,struct hal_rx_desc * desc)47 bool ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base *ab,
48 struct hal_rx_desc *desc)
49 {
50 return ab->hw_params.hw_ops->rx_desc_get_ldpc_support(desc);
51 }
52
53 static inline
ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base * ab,struct hal_rx_desc * desc)54 u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab,
55 struct hal_rx_desc *desc)
56 {
57 return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc);
58 }
59
60 static inline
ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)61 bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab,
62 struct hal_rx_desc *desc)
63 {
64 return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
65 }
66
ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)67 static inline bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab,
68 struct hal_rx_desc *desc)
69 {
70 return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc);
71 }
72
ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base * ab,struct sk_buff * skb)73 static inline bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab,
74 struct sk_buff *skb)
75 {
76 struct ieee80211_hdr *hdr;
77
78 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
79 return ieee80211_has_morefrags(hdr->frame_control);
80 }
81
ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base * ab,struct sk_buff * skb)82 static inline u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab,
83 struct sk_buff *skb)
84 {
85 struct ieee80211_hdr *hdr;
86
87 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
88 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
89 }
90
ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base * ab,struct hal_rx_desc * desc)91 static inline u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab,
92 struct hal_rx_desc *desc)
93 {
94 return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc);
95 }
96
ath11k_dp_rx_get_attention(struct ath11k_base * ab,struct hal_rx_desc * desc)97 static inline void *ath11k_dp_rx_get_attention(struct ath11k_base *ab,
98 struct hal_rx_desc *desc)
99 {
100 return ab->hw_params.hw_ops->rx_desc_get_attention(desc);
101 }
102
ath11k_dp_rx_h_attn_msdu_done(struct rx_attention * attn)103 static inline bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn)
104 {
105 return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
106 __le32_to_cpu(attn->info2));
107 }
108
ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention * attn)109 static inline bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn)
110 {
111 return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
112 __le32_to_cpu(attn->info1));
113 }
114
ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention * attn)115 static inline bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn)
116 {
117 return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
118 __le32_to_cpu(attn->info1));
119 }
120
ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention * attn)121 static inline bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn)
122 {
123 return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
124 __le32_to_cpu(attn->info2)) ==
125 RX_DESC_DECRYPT_STATUS_CODE_OK);
126 }
127
ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention * attn)128 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn)
129 {
130 u32 info = __le32_to_cpu(attn->info1);
131 u32 errmap = 0;
132
133 if (info & RX_ATTENTION_INFO1_FCS_ERR)
134 errmap |= DP_RX_MPDU_ERR_FCS;
135
136 if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
137 errmap |= DP_RX_MPDU_ERR_DECRYPT;
138
139 if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
140 errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
141
142 if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
143 errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
144
145 if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
146 errmap |= DP_RX_MPDU_ERR_OVERFLOW;
147
148 if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
149 errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
150
151 if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
152 errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
153
154 return errmap;
155 }
156
ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base * ab,struct hal_rx_desc * desc)157 static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab,
158 struct hal_rx_desc *desc)
159 {
160 struct rx_attention *rx_attention;
161 u32 errmap;
162
163 rx_attention = ath11k_dp_rx_get_attention(ab, desc);
164 errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
165
166 return errmap & DP_RX_MPDU_ERR_MSDU_LEN;
167 }
168
ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc)169 static inline u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab,
170 struct hal_rx_desc *desc)
171 {
172 return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc);
173 }
174
ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base * ab,struct hal_rx_desc * desc)175 static inline u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab,
176 struct hal_rx_desc *desc)
177 {
178 return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc);
179 }
180
ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base * ab,struct hal_rx_desc * desc)181 static inline u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab,
182 struct hal_rx_desc *desc)
183 {
184 return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc);
185 }
186
ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base * ab,struct hal_rx_desc * desc)187 static inline u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab,
188 struct hal_rx_desc *desc)
189 {
190 return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc);
191 }
192
ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base * ab,struct hal_rx_desc * desc)193 static inline u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab,
194 struct hal_rx_desc *desc)
195 {
196 return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc);
197 }
198
ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base * ab,struct hal_rx_desc * desc)199 static inline u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab,
200 struct hal_rx_desc *desc)
201 {
202 return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc);
203 }
204
ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base * ab,struct hal_rx_desc * desc)205 static inline u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab,
206 struct hal_rx_desc *desc)
207 {
208 return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc));
209 }
210
ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base * ab,struct hal_rx_desc * desc)211 static inline u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab,
212 struct hal_rx_desc *desc)
213 {
214 return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc);
215 }
216
ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base * ab,struct hal_rx_desc * desc)217 static inline u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab,
218 struct hal_rx_desc *desc)
219 {
220 return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc);
221 }
222
ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base * ab,struct hal_rx_desc * desc)223 static inline u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab,
224 struct hal_rx_desc *desc)
225 {
226 return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc);
227 }
228
ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)229 static inline bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab,
230 struct hal_rx_desc *desc)
231 {
232 return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc);
233 }
234
ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)235 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab,
236 struct hal_rx_desc *desc)
237 {
238 return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc);
239 }
240
ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base * ab,struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)241 static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab,
242 struct hal_rx_desc *fdesc,
243 struct hal_rx_desc *ldesc)
244 {
245 ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc);
246 }
247
ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention * attn)248 static inline u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn)
249 {
250 return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
251 __le32_to_cpu(attn->info1));
252 }
253
ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)254 static inline u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab,
255 struct hal_rx_desc *rx_desc)
256 {
257 u8 *rx_pkt_hdr;
258
259 rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc);
260
261 return rx_pkt_hdr;
262 }
263
ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)264 static inline bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab,
265 struct hal_rx_desc *rx_desc)
266 {
267 u32 tlv_tag;
268
269 tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc);
270
271 return tlv_tag == HAL_RX_MPDU_START;
272 }
273
ath11k_dp_rxdesc_get_ppduid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)274 static inline u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab,
275 struct hal_rx_desc *rx_desc)
276 {
277 return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc);
278 }
279
ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc,u16 len)280 static inline void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab,
281 struct hal_rx_desc *desc,
282 u16 len)
283 {
284 ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len);
285 }
286
ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base * ab,struct hal_rx_desc * desc)287 static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab,
288 struct hal_rx_desc *desc)
289 {
290 struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc);
291
292 return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) &&
293 (!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST,
294 __le32_to_cpu(attn->info1)));
295 }
296
ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)297 static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab,
298 struct hal_rx_desc *desc)
299 {
300 return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc);
301 }
302
ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base * ab,struct hal_rx_desc * desc)303 static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab,
304 struct hal_rx_desc *desc)
305 {
306 return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc);
307 }
308
ath11k_dp_service_mon_ring(struct timer_list * t)309 static void ath11k_dp_service_mon_ring(struct timer_list *t)
310 {
311 struct ath11k_base *ab = timer_container_of(ab, t, mon_reap_timer);
312 int i;
313
314 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++)
315 ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
316
317 mod_timer(&ab->mon_reap_timer, jiffies +
318 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
319 }
320
ath11k_dp_purge_mon_ring(struct ath11k_base * ab)321 static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab)
322 {
323 int i, reaped = 0;
324 unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS);
325
326 do {
327 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++)
328 reaped += ath11k_dp_rx_process_mon_rings(ab, i,
329 NULL,
330 DP_MON_SERVICE_BUDGET);
331
332 /* nothing more to reap */
333 if (reaped < DP_MON_SERVICE_BUDGET)
334 return 0;
335
336 } while (time_before(jiffies, timeout));
337
338 ath11k_warn(ab, "dp mon ring purge timeout");
339
340 return -ETIMEDOUT;
341 }
342
343 /* Returns number of Rx buffers replenished */
ath11k_dp_rxbufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)344 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
345 struct dp_rxdma_ring *rx_ring,
346 int req_entries,
347 enum hal_rx_buf_return_buf_manager mgr)
348 {
349 struct hal_srng *srng;
350 u32 *desc;
351 struct sk_buff *skb;
352 int num_free;
353 int num_remain;
354 int buf_id;
355 u32 cookie;
356 dma_addr_t paddr;
357
358 req_entries = min(req_entries, rx_ring->bufs_max);
359
360 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
361
362 spin_lock_bh(&srng->lock);
363
364 ath11k_hal_srng_access_begin(ab, srng);
365
366 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
367 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
368 req_entries = num_free;
369
370 req_entries = min(num_free, req_entries);
371 num_remain = req_entries;
372
373 while (num_remain > 0) {
374 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
375 DP_RX_BUFFER_ALIGN_SIZE);
376 if (!skb)
377 break;
378
379 if (!IS_ALIGNED((unsigned long)skb->data,
380 DP_RX_BUFFER_ALIGN_SIZE)) {
381 skb_pull(skb,
382 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
383 skb->data);
384 }
385
386 paddr = dma_map_single(ab->dev, skb->data,
387 skb->len + skb_tailroom(skb),
388 DMA_FROM_DEVICE);
389 if (dma_mapping_error(ab->dev, paddr))
390 goto fail_free_skb;
391
392 spin_lock_bh(&rx_ring->idr_lock);
393 buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 1,
394 (rx_ring->bufs_max * 3) + 1, GFP_ATOMIC);
395 spin_unlock_bh(&rx_ring->idr_lock);
396 if (buf_id <= 0)
397 goto fail_dma_unmap;
398
399 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
400 if (!desc)
401 goto fail_idr_remove;
402
403 ATH11K_SKB_RXCB(skb)->paddr = paddr;
404
405 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
406 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
407
408 num_remain--;
409
410 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
411 }
412
413 ath11k_hal_srng_access_end(ab, srng);
414
415 spin_unlock_bh(&srng->lock);
416
417 return req_entries - num_remain;
418
419 fail_idr_remove:
420 spin_lock_bh(&rx_ring->idr_lock);
421 idr_remove(&rx_ring->bufs_idr, buf_id);
422 spin_unlock_bh(&rx_ring->idr_lock);
423 fail_dma_unmap:
424 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
425 DMA_FROM_DEVICE);
426 fail_free_skb:
427 dev_kfree_skb_any(skb);
428
429 ath11k_hal_srng_access_end(ab, srng);
430
431 spin_unlock_bh(&srng->lock);
432
433 return req_entries - num_remain;
434 }
435
ath11k_dp_rxdma_buf_ring_free(struct ath11k * ar,struct dp_rxdma_ring * rx_ring)436 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
437 struct dp_rxdma_ring *rx_ring)
438 {
439 struct sk_buff *skb;
440 int buf_id;
441
442 spin_lock_bh(&rx_ring->idr_lock);
443 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
444 idr_remove(&rx_ring->bufs_idr, buf_id);
445 /* TODO: Understand where internal driver does this dma_unmap
446 * of rxdma_buffer.
447 */
448 dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
449 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
450 dev_kfree_skb_any(skb);
451 }
452
453 idr_destroy(&rx_ring->bufs_idr);
454 spin_unlock_bh(&rx_ring->idr_lock);
455
456 return 0;
457 }
458
ath11k_dp_rxdma_pdev_buf_free(struct ath11k * ar)459 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
460 {
461 struct ath11k_pdev_dp *dp = &ar->dp;
462 struct ath11k_base *ab = ar->ab;
463 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
464 int i;
465
466 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
467
468 rx_ring = &dp->rxdma_mon_buf_ring;
469 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
470
471 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
472 rx_ring = &dp->rx_mon_status_refill_ring[i];
473 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
474 }
475
476 return 0;
477 }
478
ath11k_dp_rxdma_ring_buf_setup(struct ath11k * ar,struct dp_rxdma_ring * rx_ring,u32 ringtype)479 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
480 struct dp_rxdma_ring *rx_ring,
481 u32 ringtype)
482 {
483 struct ath11k_pdev_dp *dp = &ar->dp;
484 int num_entries;
485
486 num_entries = rx_ring->refill_buf_ring.size /
487 ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
488
489 rx_ring->bufs_max = num_entries;
490 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
491 ar->ab->hw_params.hal_params->rx_buf_rbm);
492 return 0;
493 }
494
ath11k_dp_rxdma_pdev_buf_setup(struct ath11k * ar)495 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
496 {
497 struct ath11k_pdev_dp *dp = &ar->dp;
498 struct ath11k_base *ab = ar->ab;
499 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
500 int i;
501
502 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
503
504 if (ar->ab->hw_params.rxdma1_enable) {
505 rx_ring = &dp->rxdma_mon_buf_ring;
506 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
507 }
508
509 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
510 rx_ring = &dp->rx_mon_status_refill_ring[i];
511 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
512 }
513
514 return 0;
515 }
516
ath11k_dp_rx_pdev_srng_free(struct ath11k * ar)517 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
518 {
519 struct ath11k_pdev_dp *dp = &ar->dp;
520 struct ath11k_base *ab = ar->ab;
521 int i;
522
523 ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
524
525 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
526 if (ab->hw_params.rx_mac_buf_ring)
527 ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
528
529 ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
530 ath11k_dp_srng_cleanup(ab,
531 &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
532 }
533
534 ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
535 }
536
ath11k_dp_pdev_reo_cleanup(struct ath11k_base * ab)537 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
538 {
539 struct ath11k_dp *dp = &ab->dp;
540 int i;
541
542 for (i = 0; i < DP_REO_DST_RING_MAX; i++)
543 ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
544 }
545
ath11k_dp_pdev_reo_setup(struct ath11k_base * ab)546 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
547 {
548 struct ath11k_dp *dp = &ab->dp;
549 int ret;
550 int i;
551
552 for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
553 ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
554 HAL_REO_DST, i, 0,
555 DP_REO_DST_RING_SIZE);
556 if (ret) {
557 ath11k_warn(ab, "failed to setup reo_dst_ring\n");
558 goto err_reo_cleanup;
559 }
560 }
561
562 return 0;
563
564 err_reo_cleanup:
565 ath11k_dp_pdev_reo_cleanup(ab);
566
567 return ret;
568 }
569
ath11k_dp_rx_pdev_srng_alloc(struct ath11k * ar)570 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
571 {
572 struct ath11k_pdev_dp *dp = &ar->dp;
573 struct ath11k_base *ab = ar->ab;
574 struct dp_srng *srng = NULL;
575 int i;
576 int ret;
577
578 ret = ath11k_dp_srng_setup(ar->ab,
579 &dp->rx_refill_buf_ring.refill_buf_ring,
580 HAL_RXDMA_BUF, 0,
581 dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
582 if (ret) {
583 ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
584 return ret;
585 }
586
587 if (ar->ab->hw_params.rx_mac_buf_ring) {
588 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
589 ret = ath11k_dp_srng_setup(ar->ab,
590 &dp->rx_mac_buf_ring[i],
591 HAL_RXDMA_BUF, 1,
592 dp->mac_id + i, 1024);
593 if (ret) {
594 ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
595 i);
596 return ret;
597 }
598 }
599 }
600
601 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
602 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
603 HAL_RXDMA_DST, 0, dp->mac_id + i,
604 DP_RXDMA_ERR_DST_RING_SIZE);
605 if (ret) {
606 ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
607 return ret;
608 }
609 }
610
611 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
612 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
613 ret = ath11k_dp_srng_setup(ar->ab,
614 srng,
615 HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
616 DP_RXDMA_MON_STATUS_RING_SIZE);
617 if (ret) {
618 ath11k_warn(ar->ab,
619 "failed to setup rx_mon_status_refill_ring %d\n", i);
620 return ret;
621 }
622 }
623
624 /* if rxdma1_enable is false, then it doesn't need
625 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
626 * and rxdma_mon_desc_ring.
627 * init reap timer for QCA6390.
628 */
629 if (!ar->ab->hw_params.rxdma1_enable) {
630 //init mon status buffer reap timer
631 timer_setup(&ar->ab->mon_reap_timer,
632 ath11k_dp_service_mon_ring, 0);
633 return 0;
634 }
635
636 ret = ath11k_dp_srng_setup(ar->ab,
637 &dp->rxdma_mon_buf_ring.refill_buf_ring,
638 HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
639 DP_RXDMA_MONITOR_BUF_RING_SIZE);
640 if (ret) {
641 ath11k_warn(ar->ab,
642 "failed to setup HAL_RXDMA_MONITOR_BUF\n");
643 return ret;
644 }
645
646 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
647 HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
648 DP_RXDMA_MONITOR_DST_RING_SIZE);
649 if (ret) {
650 ath11k_warn(ar->ab,
651 "failed to setup HAL_RXDMA_MONITOR_DST\n");
652 return ret;
653 }
654
655 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
656 HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
657 DP_RXDMA_MONITOR_DESC_RING_SIZE);
658 if (ret) {
659 ath11k_warn(ar->ab,
660 "failed to setup HAL_RXDMA_MONITOR_DESC\n");
661 return ret;
662 }
663
664 return 0;
665 }
666
ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base * ab)667 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
668 {
669 struct ath11k_dp *dp = &ab->dp;
670 struct dp_reo_cmd *cmd, *tmp;
671 struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
672 struct dp_rx_tid *rx_tid;
673
674 spin_lock_bh(&dp->reo_cmd_lock);
675 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
676 list_del(&cmd->list);
677 rx_tid = &cmd->data;
678 if (rx_tid->vaddr_unaligned) {
679 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
680 rx_tid->vaddr_unaligned,
681 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
682 rx_tid->vaddr_unaligned = NULL;
683 }
684 kfree(cmd);
685 }
686
687 list_for_each_entry_safe(cmd_cache, tmp_cache,
688 &dp->reo_cmd_cache_flush_list, list) {
689 list_del(&cmd_cache->list);
690 dp->reo_cmd_cache_flush_count--;
691 rx_tid = &cmd_cache->data;
692 if (rx_tid->vaddr_unaligned) {
693 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
694 rx_tid->vaddr_unaligned,
695 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
696 rx_tid->vaddr_unaligned = NULL;
697 }
698 kfree(cmd_cache);
699 }
700 spin_unlock_bh(&dp->reo_cmd_lock);
701 }
702
ath11k_dp_reo_cmd_free(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)703 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
704 enum hal_reo_cmd_status status)
705 {
706 struct dp_rx_tid *rx_tid = ctx;
707
708 if (status != HAL_REO_CMD_SUCCESS)
709 ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
710 rx_tid->tid, status);
711 if (rx_tid->vaddr_unaligned) {
712 dma_free_noncoherent(dp->ab->dev, rx_tid->unaligned_size,
713 rx_tid->vaddr_unaligned,
714 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
715 rx_tid->vaddr_unaligned = NULL;
716 }
717 }
718
ath11k_dp_reo_cache_flush(struct ath11k_base * ab,struct dp_rx_tid * rx_tid)719 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
720 struct dp_rx_tid *rx_tid)
721 {
722 struct ath11k_hal_reo_cmd cmd = {};
723 unsigned long tot_desc_sz, desc_sz;
724 int ret;
725
726 tot_desc_sz = rx_tid->size;
727 desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
728
729 while (tot_desc_sz > desc_sz) {
730 tot_desc_sz -= desc_sz;
731 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
732 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
733 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
734 HAL_REO_CMD_FLUSH_CACHE, &cmd,
735 NULL);
736 if (ret)
737 ath11k_warn(ab,
738 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
739 rx_tid->tid, ret);
740 }
741
742 memset(&cmd, 0, sizeof(cmd));
743 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
744 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
745 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
746 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
747 HAL_REO_CMD_FLUSH_CACHE,
748 &cmd, ath11k_dp_reo_cmd_free);
749 if (ret) {
750 ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
751 rx_tid->tid, ret);
752 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
753 rx_tid->vaddr_unaligned,
754 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
755 rx_tid->vaddr_unaligned = NULL;
756 }
757 }
758
ath11k_dp_rx_tid_del_func(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)759 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
760 enum hal_reo_cmd_status status)
761 {
762 struct ath11k_base *ab = dp->ab;
763 struct dp_rx_tid *rx_tid = ctx;
764 struct dp_reo_cache_flush_elem *elem, *tmp;
765
766 if (status == HAL_REO_CMD_DRAIN) {
767 goto free_desc;
768 } else if (status != HAL_REO_CMD_SUCCESS) {
769 /* Shouldn't happen! Cleanup in case of other failure? */
770 ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
771 rx_tid->tid, status);
772 return;
773 }
774
775 elem = kzalloc_obj(*elem, GFP_ATOMIC);
776 if (!elem)
777 goto free_desc;
778
779 elem->ts = jiffies;
780 memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
781
782 spin_lock_bh(&dp->reo_cmd_lock);
783 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
784 dp->reo_cmd_cache_flush_count++;
785
786 /* Flush and invalidate aged REO desc from HW cache */
787 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
788 list) {
789 if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
790 time_after(jiffies, elem->ts +
791 msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
792 list_del(&elem->list);
793 dp->reo_cmd_cache_flush_count--;
794 spin_unlock_bh(&dp->reo_cmd_lock);
795
796 ath11k_dp_reo_cache_flush(ab, &elem->data);
797 kfree(elem);
798 spin_lock_bh(&dp->reo_cmd_lock);
799 }
800 }
801 spin_unlock_bh(&dp->reo_cmd_lock);
802
803 return;
804 free_desc:
805 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
806 rx_tid->vaddr_unaligned,
807 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
808 rx_tid->vaddr_unaligned = NULL;
809 }
810
ath11k_peer_rx_tid_delete(struct ath11k * ar,struct ath11k_peer * peer,u8 tid)811 void ath11k_peer_rx_tid_delete(struct ath11k *ar,
812 struct ath11k_peer *peer, u8 tid)
813 {
814 struct ath11k_hal_reo_cmd cmd = {};
815 struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
816 int ret;
817
818 if (!rx_tid->active)
819 return;
820
821 rx_tid->active = false;
822
823 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
824 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
825 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
826 cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
827 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
828 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
829 ath11k_dp_rx_tid_del_func);
830 if (ret) {
831 if (ret != -ESHUTDOWN)
832 ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
833 tid, ret);
834 dma_free_noncoherent(ar->ab->dev, rx_tid->unaligned_size,
835 rx_tid->vaddr_unaligned,
836 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
837 rx_tid->vaddr_unaligned = NULL;
838 }
839
840 rx_tid->paddr = 0;
841 rx_tid->paddr_unaligned = 0;
842 rx_tid->size = 0;
843 rx_tid->unaligned_size = 0;
844 }
845
ath11k_dp_rx_link_desc_return(struct ath11k_base * ab,u32 * link_desc,enum hal_wbm_rel_bm_act action)846 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
847 u32 *link_desc,
848 enum hal_wbm_rel_bm_act action)
849 {
850 struct ath11k_dp *dp = &ab->dp;
851 struct hal_srng *srng;
852 u32 *desc;
853 int ret = 0;
854
855 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
856
857 spin_lock_bh(&srng->lock);
858
859 ath11k_hal_srng_access_begin(ab, srng);
860
861 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
862 if (!desc) {
863 ret = -ENOBUFS;
864 goto exit;
865 }
866
867 ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
868 action);
869
870 exit:
871 ath11k_hal_srng_access_end(ab, srng);
872
873 spin_unlock_bh(&srng->lock);
874
875 return ret;
876 }
877
ath11k_dp_rx_frags_cleanup(struct dp_rx_tid * rx_tid,bool rel_link_desc)878 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
879 {
880 struct ath11k_base *ab = rx_tid->ab;
881
882 lockdep_assert_held(&ab->base_lock);
883
884 if (rx_tid->dst_ring_desc) {
885 if (rel_link_desc)
886 ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
887 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
888 kfree(rx_tid->dst_ring_desc);
889 rx_tid->dst_ring_desc = NULL;
890 }
891
892 rx_tid->cur_sn = 0;
893 rx_tid->last_frag_no = 0;
894 rx_tid->rx_frag_bitmap = 0;
895 __skb_queue_purge(&rx_tid->rx_frags);
896 }
897
ath11k_peer_frags_flush(struct ath11k * ar,struct ath11k_peer * peer)898 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
899 {
900 struct dp_rx_tid *rx_tid;
901 int i;
902
903 lockdep_assert_held(&ar->ab->base_lock);
904
905 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
906 rx_tid = &peer->rx_tid[i];
907
908 spin_unlock_bh(&ar->ab->base_lock);
909 timer_delete_sync(&rx_tid->frag_timer);
910 spin_lock_bh(&ar->ab->base_lock);
911
912 ath11k_dp_rx_frags_cleanup(rx_tid, true);
913 }
914 }
915
ath11k_peer_rx_tid_cleanup(struct ath11k * ar,struct ath11k_peer * peer)916 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
917 {
918 struct dp_rx_tid *rx_tid;
919 int i;
920
921 lockdep_assert_held(&ar->ab->base_lock);
922
923 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
924 rx_tid = &peer->rx_tid[i];
925
926 ath11k_peer_rx_tid_delete(ar, peer, i);
927 ath11k_dp_rx_frags_cleanup(rx_tid, true);
928
929 spin_unlock_bh(&ar->ab->base_lock);
930 timer_delete_sync(&rx_tid->frag_timer);
931 spin_lock_bh(&ar->ab->base_lock);
932 }
933 }
934
ath11k_peer_rx_tid_reo_update(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)935 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
936 struct ath11k_peer *peer,
937 struct dp_rx_tid *rx_tid,
938 u32 ba_win_sz, u16 ssn,
939 bool update_ssn)
940 {
941 struct ath11k_hal_reo_cmd cmd = {};
942 int ret;
943
944 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
945 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
946 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
947 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
948 cmd.ba_window_size = ba_win_sz;
949
950 if (update_ssn) {
951 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
952 cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
953 }
954
955 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
956 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
957 NULL);
958 if (ret) {
959 ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
960 rx_tid->tid, ret);
961 return ret;
962 }
963
964 rx_tid->ba_win_sz = ba_win_sz;
965
966 return 0;
967 }
968
ath11k_dp_rx_tid_mem_free(struct ath11k_base * ab,const u8 * peer_mac,int vdev_id,u8 tid)969 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
970 const u8 *peer_mac, int vdev_id, u8 tid)
971 {
972 struct ath11k_peer *peer;
973 struct dp_rx_tid *rx_tid;
974
975 spin_lock_bh(&ab->base_lock);
976
977 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
978 if (!peer) {
979 ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
980 goto unlock_exit;
981 }
982
983 rx_tid = &peer->rx_tid[tid];
984 if (!rx_tid->active)
985 goto unlock_exit;
986
987 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size, rx_tid->vaddr_unaligned,
988 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
989 rx_tid->vaddr_unaligned = NULL;
990
991 rx_tid->active = false;
992
993 unlock_exit:
994 spin_unlock_bh(&ab->base_lock);
995 }
996
ath11k_peer_rx_tid_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)997 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
998 u8 tid, u32 ba_win_sz, u16 ssn,
999 enum hal_pn_type pn_type)
1000 {
1001 struct ath11k_base *ab = ar->ab;
1002 struct ath11k_peer *peer;
1003 struct dp_rx_tid *rx_tid;
1004 u32 hw_desc_sz, *vaddr;
1005 void *vaddr_unaligned;
1006 dma_addr_t paddr;
1007 int ret;
1008
1009 spin_lock_bh(&ab->base_lock);
1010
1011 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
1012 if (!peer) {
1013 ath11k_warn(ab, "failed to find the peer %pM to set up rx tid\n",
1014 peer_mac);
1015 spin_unlock_bh(&ab->base_lock);
1016 return -ENOENT;
1017 }
1018
1019 rx_tid = &peer->rx_tid[tid];
1020 /* Update the tid queue if it is already setup */
1021 if (rx_tid->active) {
1022 paddr = rx_tid->paddr;
1023 ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
1024 ba_win_sz, ssn, true);
1025 spin_unlock_bh(&ab->base_lock);
1026 if (ret) {
1027 ath11k_warn(ab, "failed to update reo for peer %pM rx tid %d\n: %d",
1028 peer_mac, tid, ret);
1029 return ret;
1030 }
1031
1032 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1033 peer_mac, paddr,
1034 tid, 1, ba_win_sz);
1035 if (ret)
1036 ath11k_warn(ab, "failed to send wmi rx reorder queue for peer %pM tid %d: %d\n",
1037 peer_mac, tid, ret);
1038 return ret;
1039 }
1040
1041 rx_tid->tid = tid;
1042
1043 rx_tid->ba_win_sz = ba_win_sz;
1044
1045 /* TODO: Optimize the memory allocation for qos tid based on
1046 * the actual BA window size in REO tid update path.
1047 */
1048 if (tid == HAL_DESC_REO_NON_QOS_TID)
1049 hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
1050 else
1051 hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
1052
1053 rx_tid->unaligned_size = hw_desc_sz + HAL_LINK_DESC_ALIGN - 1;
1054 vaddr_unaligned = dma_alloc_noncoherent(ab->dev, rx_tid->unaligned_size, &paddr,
1055 DMA_BIDIRECTIONAL, GFP_ATOMIC);
1056 if (!vaddr_unaligned) {
1057 spin_unlock_bh(&ab->base_lock);
1058 return -ENOMEM;
1059 }
1060
1061 rx_tid->vaddr_unaligned = vaddr_unaligned;
1062 vaddr = PTR_ALIGN(vaddr_unaligned, HAL_LINK_DESC_ALIGN);
1063 rx_tid->paddr_unaligned = paddr;
1064 rx_tid->paddr = rx_tid->paddr_unaligned + ((unsigned long)vaddr -
1065 (unsigned long)rx_tid->vaddr_unaligned);
1066 ath11k_hal_reo_qdesc_setup(vaddr, tid, ba_win_sz, ssn, pn_type);
1067 rx_tid->size = hw_desc_sz;
1068 rx_tid->active = true;
1069
1070 /* After dma_alloc_noncoherent, vaddr is being modified for reo qdesc setup.
1071 * Since these changes are not reflected in the device, driver now needs to
1072 * explicitly call dma_sync_single_for_device.
1073 */
1074 dma_sync_single_for_device(ab->dev, rx_tid->paddr,
1075 rx_tid->size,
1076 DMA_TO_DEVICE);
1077 spin_unlock_bh(&ab->base_lock);
1078
1079 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, rx_tid->paddr,
1080 tid, 1, ba_win_sz);
1081 if (ret) {
1082 ath11k_warn(ar->ab, "failed to setup rx reorder queue for peer %pM tid %d: %d\n",
1083 peer_mac, tid, ret);
1084 ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
1085 }
1086
1087 return ret;
1088 }
1089
ath11k_dp_rx_ampdu_start(struct ath11k * ar,struct ieee80211_ampdu_params * params)1090 int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
1091 struct ieee80211_ampdu_params *params)
1092 {
1093 struct ath11k_base *ab = ar->ab;
1094 struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta);
1095 int vdev_id = arsta->arvif->vdev_id;
1096 int ret;
1097
1098 ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
1099 params->tid, params->buf_size,
1100 params->ssn, arsta->pn_type);
1101 if (ret)
1102 ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
1103
1104 return ret;
1105 }
1106
ath11k_dp_rx_ampdu_stop(struct ath11k * ar,struct ieee80211_ampdu_params * params)1107 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
1108 struct ieee80211_ampdu_params *params)
1109 {
1110 struct ath11k_base *ab = ar->ab;
1111 struct ath11k_peer *peer;
1112 struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta);
1113 struct dp_rx_tid *rx_tid;
1114 int vdev_id = arsta->arvif->vdev_id;
1115 int ret;
1116
1117 spin_lock_bh(&ab->base_lock);
1118
1119 peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
1120 if (!peer) {
1121 ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1122 spin_unlock_bh(&ab->base_lock);
1123 return -ENOENT;
1124 }
1125
1126 rx_tid = &peer->rx_tid[params->tid];
1127
1128 if (!rx_tid->active) {
1129 spin_unlock_bh(&ab->base_lock);
1130 return 0;
1131 }
1132
1133 ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid, 1, 0, false);
1134 spin_unlock_bh(&ab->base_lock);
1135 if (ret) {
1136 ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1137 params->tid, ret);
1138 return ret;
1139 }
1140
1141 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1142 params->sta->addr,
1143 rx_tid->paddr,
1144 params->tid, 1, 1);
1145 if (ret)
1146 ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
1147 ret);
1148
1149 return ret;
1150 }
1151
ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1152 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
1153 const u8 *peer_addr,
1154 enum set_key_cmd key_cmd,
1155 struct ieee80211_key_conf *key)
1156 {
1157 struct ath11k *ar = arvif->ar;
1158 struct ath11k_base *ab = ar->ab;
1159 struct ath11k_hal_reo_cmd cmd = {};
1160 struct ath11k_peer *peer;
1161 struct dp_rx_tid *rx_tid;
1162 u8 tid;
1163 int ret = 0;
1164
1165 /* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1166 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1167 * for now.
1168 */
1169 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1170 return 0;
1171
1172 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
1173 cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
1174 HAL_REO_CMD_UPD0_PN_SIZE |
1175 HAL_REO_CMD_UPD0_PN_VALID |
1176 HAL_REO_CMD_UPD0_PN_CHECK |
1177 HAL_REO_CMD_UPD0_SVLD;
1178
1179 switch (key->cipher) {
1180 case WLAN_CIPHER_SUITE_TKIP:
1181 case WLAN_CIPHER_SUITE_CCMP:
1182 case WLAN_CIPHER_SUITE_CCMP_256:
1183 case WLAN_CIPHER_SUITE_GCMP:
1184 case WLAN_CIPHER_SUITE_GCMP_256:
1185 if (key_cmd == SET_KEY) {
1186 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1187 cmd.pn_size = 48;
1188 }
1189 break;
1190 default:
1191 break;
1192 }
1193
1194 spin_lock_bh(&ab->base_lock);
1195
1196 peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
1197 if (!peer) {
1198 ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
1199 spin_unlock_bh(&ab->base_lock);
1200 return -ENOENT;
1201 }
1202
1203 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1204 rx_tid = &peer->rx_tid[tid];
1205 if (!rx_tid->active)
1206 continue;
1207 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1208 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1209 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
1210 HAL_REO_CMD_UPDATE_RX_QUEUE,
1211 &cmd, NULL);
1212 if (ret) {
1213 ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
1214 tid, ret);
1215 break;
1216 }
1217 }
1218
1219 spin_unlock_bh(&ab->base_lock);
1220
1221 return ret;
1222 }
1223
ath11k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1224 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1225 u16 peer_id)
1226 {
1227 int i;
1228
1229 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1230 if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1231 if (peer_id == ppdu_stats->user_stats[i].peer_id)
1232 return i;
1233 } else {
1234 return i;
1235 }
1236 }
1237
1238 return -EINVAL;
1239 }
1240
ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1241 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
1242 u16 tag, u16 len, const void *ptr,
1243 void *data)
1244 {
1245 struct htt_ppdu_stats_info *ppdu_info;
1246 struct htt_ppdu_user_stats *user_stats;
1247 int cur_user;
1248 u16 peer_id;
1249
1250 ppdu_info = data;
1251
1252 switch (tag) {
1253 case HTT_PPDU_STATS_TAG_COMMON:
1254 if (len < sizeof(struct htt_ppdu_stats_common)) {
1255 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1256 len, tag);
1257 return -EINVAL;
1258 }
1259 memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
1260 sizeof(struct htt_ppdu_stats_common));
1261 break;
1262 case HTT_PPDU_STATS_TAG_USR_RATE:
1263 if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1264 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1265 len, tag);
1266 return -EINVAL;
1267 }
1268
1269 peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1270 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1271 peer_id);
1272 if (cur_user < 0)
1273 return -EINVAL;
1274 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1275 user_stats->peer_id = peer_id;
1276 user_stats->is_valid_peer_id = true;
1277 memcpy((void *)&user_stats->rate, ptr,
1278 sizeof(struct htt_ppdu_stats_user_rate));
1279 user_stats->tlv_flags |= BIT(tag);
1280 break;
1281 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1282 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1283 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1284 len, tag);
1285 return -EINVAL;
1286 }
1287
1288 peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1289 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1290 peer_id);
1291 if (cur_user < 0)
1292 return -EINVAL;
1293 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1294 user_stats->peer_id = peer_id;
1295 user_stats->is_valid_peer_id = true;
1296 memcpy((void *)&user_stats->cmpltn_cmn, ptr,
1297 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1298 user_stats->tlv_flags |= BIT(tag);
1299 break;
1300 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1301 if (len <
1302 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1303 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1304 len, tag);
1305 return -EINVAL;
1306 }
1307
1308 peer_id =
1309 ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1310 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1311 peer_id);
1312 if (cur_user < 0)
1313 return -EINVAL;
1314 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1315 user_stats->peer_id = peer_id;
1316 user_stats->is_valid_peer_id = true;
1317 memcpy((void *)&user_stats->ack_ba, ptr,
1318 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1319 user_stats->tlv_flags |= BIT(tag);
1320 break;
1321 }
1322 return 0;
1323 }
1324
ath11k_dp_htt_tlv_iter(struct ath11k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath11k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1325 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
1326 int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
1327 const void *ptr, void *data),
1328 void *data)
1329 {
1330 const struct htt_tlv *tlv;
1331 const void *begin = ptr;
1332 u16 tlv_tag, tlv_len;
1333 int ret = -EINVAL;
1334
1335 while (len > 0) {
1336 if (len < sizeof(*tlv)) {
1337 ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1338 ptr - begin, len, sizeof(*tlv));
1339 return -EINVAL;
1340 }
1341 tlv = (struct htt_tlv *)ptr;
1342 tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
1343 tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
1344 ptr += sizeof(*tlv);
1345 len -= sizeof(*tlv);
1346
1347 if (tlv_len > len) {
1348 ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1349 tlv_tag, ptr - begin, len, tlv_len);
1350 return -EINVAL;
1351 }
1352 ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1353 if (ret == -ENOMEM)
1354 return ret;
1355
1356 ptr += tlv_len;
1357 len -= tlv_len;
1358 }
1359 return 0;
1360 }
1361
1362 static void
ath11k_update_per_peer_tx_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1363 ath11k_update_per_peer_tx_stats(struct ath11k *ar,
1364 struct htt_ppdu_stats *ppdu_stats, u8 user)
1365 {
1366 struct ath11k_base *ab = ar->ab;
1367 struct ath11k_peer *peer;
1368 struct ieee80211_sta *sta;
1369 struct ath11k_sta *arsta;
1370 struct htt_ppdu_stats_user_rate *user_rate;
1371 struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1372 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1373 struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1374 int ret;
1375 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1376 u32 succ_bytes = 0;
1377 u16 rate = 0, succ_pkts = 0;
1378 u32 tx_duration = 0;
1379 u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1380 bool is_ampdu = false;
1381
1382 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1383 return;
1384
1385 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1386 is_ampdu =
1387 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1388
1389 if (usr_stats->tlv_flags &
1390 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1391 succ_bytes = usr_stats->ack_ba.success_bytes;
1392 succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
1393 usr_stats->ack_ba.info);
1394 tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
1395 usr_stats->ack_ba.info);
1396 }
1397
1398 if (common->fes_duration_us)
1399 tx_duration = common->fes_duration_us;
1400
1401 user_rate = &usr_stats->rate;
1402 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1403 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1404 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1405 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1406 sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1407 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1408
1409 /* Note: If host configured fixed rates and in some other special
1410 * cases, the broadcast/management frames are sent in different rates.
1411 * Firmware rate's control to be skipped for this?
1412 */
1413
1414 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
1415 ath11k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
1416 return;
1417 }
1418
1419 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
1420 ath11k_warn(ab, "Invalid VHT mcs %d peer stats", mcs);
1421 return;
1422 }
1423
1424 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
1425 ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1426 mcs, nss);
1427 return;
1428 }
1429
1430 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1431 ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
1432 flags,
1433 &rate_idx,
1434 &rate);
1435 if (ret < 0)
1436 return;
1437 }
1438
1439 rcu_read_lock();
1440 spin_lock_bh(&ab->base_lock);
1441 peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
1442
1443 if (!peer || !peer->sta) {
1444 spin_unlock_bh(&ab->base_lock);
1445 rcu_read_unlock();
1446 return;
1447 }
1448
1449 sta = peer->sta;
1450 arsta = ath11k_sta_to_arsta(sta);
1451
1452 memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1453
1454 switch (flags) {
1455 case WMI_RATE_PREAMBLE_OFDM:
1456 arsta->txrate.legacy = rate;
1457 break;
1458 case WMI_RATE_PREAMBLE_CCK:
1459 arsta->txrate.legacy = rate;
1460 break;
1461 case WMI_RATE_PREAMBLE_HT:
1462 arsta->txrate.mcs = mcs + 8 * (nss - 1);
1463 arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1464 if (sgi)
1465 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1466 break;
1467 case WMI_RATE_PREAMBLE_VHT:
1468 arsta->txrate.mcs = mcs;
1469 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1470 if (sgi)
1471 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1472 break;
1473 case WMI_RATE_PREAMBLE_HE:
1474 arsta->txrate.mcs = mcs;
1475 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1476 arsta->txrate.he_dcm = dcm;
1477 arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
1478 arsta->txrate.he_ru_alloc = ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc
1479 ((user_rate->ru_end -
1480 user_rate->ru_start) + 1);
1481 break;
1482 }
1483
1484 arsta->txrate.nss = nss;
1485
1486 arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
1487 arsta->tx_duration += tx_duration;
1488 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1489
1490 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1491 * So skip peer stats update for mgmt packets.
1492 */
1493 if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1494 memset(peer_stats, 0, sizeof(*peer_stats));
1495 peer_stats->succ_pkts = succ_pkts;
1496 peer_stats->succ_bytes = succ_bytes;
1497 peer_stats->is_ampdu = is_ampdu;
1498 peer_stats->duration = tx_duration;
1499 peer_stats->ba_fails =
1500 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1501 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1502
1503 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
1504 ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
1505 }
1506
1507 spin_unlock_bh(&ab->base_lock);
1508 rcu_read_unlock();
1509 }
1510
ath11k_htt_update_ppdu_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats)1511 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
1512 struct htt_ppdu_stats *ppdu_stats)
1513 {
1514 u8 user;
1515
1516 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1517 ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1518 }
1519
1520 static
ath11k_dp_htt_get_ppdu_desc(struct ath11k * ar,u32 ppdu_id)1521 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
1522 u32 ppdu_id)
1523 {
1524 struct htt_ppdu_stats_info *ppdu_info;
1525
1526 lockdep_assert_held(&ar->data_lock);
1527
1528 if (!list_empty(&ar->ppdu_stats_info)) {
1529 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1530 if (ppdu_info->ppdu_id == ppdu_id)
1531 return ppdu_info;
1532 }
1533
1534 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1535 ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1536 typeof(*ppdu_info), list);
1537 list_del(&ppdu_info->list);
1538 ar->ppdu_stat_list_depth--;
1539 ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1540 kfree(ppdu_info);
1541 }
1542 }
1543
1544 ppdu_info = kzalloc_obj(*ppdu_info, GFP_ATOMIC);
1545 if (!ppdu_info)
1546 return NULL;
1547
1548 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1549 ar->ppdu_stat_list_depth++;
1550
1551 return ppdu_info;
1552 }
1553
ath11k_htt_pull_ppdu_stats(struct ath11k_base * ab,struct sk_buff * skb)1554 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
1555 struct sk_buff *skb)
1556 {
1557 struct ath11k_htt_ppdu_stats_msg *msg;
1558 struct htt_ppdu_stats_info *ppdu_info;
1559 struct ath11k *ar;
1560 int ret;
1561 u8 pdev_id;
1562 u32 ppdu_id, len;
1563
1564 msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
1565 len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
1566 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
1567 ppdu_id = msg->ppdu_id;
1568
1569 rcu_read_lock();
1570 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1571 if (!ar) {
1572 ret = -EINVAL;
1573 goto out;
1574 }
1575
1576 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
1577 trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
1578
1579 spin_lock_bh(&ar->data_lock);
1580 ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1581 if (!ppdu_info) {
1582 ret = -EINVAL;
1583 goto out_unlock_data;
1584 }
1585
1586 ppdu_info->ppdu_id = ppdu_id;
1587 ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
1588 ath11k_htt_tlv_ppdu_stats_parse,
1589 (void *)ppdu_info);
1590 if (ret) {
1591 ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
1592 goto out_unlock_data;
1593 }
1594
1595 out_unlock_data:
1596 spin_unlock_bh(&ar->data_lock);
1597
1598 out:
1599 rcu_read_unlock();
1600
1601 return ret;
1602 }
1603
ath11k_htt_pktlog(struct ath11k_base * ab,struct sk_buff * skb)1604 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
1605 {
1606 struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
1607 struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
1608 struct ath11k *ar;
1609 u8 pdev_id;
1610
1611 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
1612
1613 rcu_read_lock();
1614
1615 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1616 if (!ar) {
1617 ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
1618 goto out;
1619 }
1620
1621 trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
1622 ar->ab->pktlog_defs_checksum);
1623
1624 out:
1625 rcu_read_unlock();
1626 }
1627
ath11k_htt_backpressure_event_handler(struct ath11k_base * ab,struct sk_buff * skb)1628 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
1629 struct sk_buff *skb)
1630 {
1631 u32 *data = (u32 *)skb->data;
1632 u8 pdev_id, ring_type, ring_id, pdev_idx;
1633 u16 hp, tp;
1634 u32 backpressure_time;
1635 struct ath11k_bp_stats *bp_stats;
1636
1637 pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
1638 ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
1639 ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
1640 ++data;
1641
1642 hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
1643 tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
1644 ++data;
1645
1646 backpressure_time = *data;
1647
1648 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
1649 pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
1650
1651 if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
1652 if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
1653 return;
1654
1655 bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
1656 } else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
1657 pdev_idx = DP_HW2SW_MACID(pdev_id);
1658
1659 if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
1660 return;
1661
1662 bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
1663 } else {
1664 ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
1665 ring_type);
1666 return;
1667 }
1668
1669 spin_lock_bh(&ab->base_lock);
1670 bp_stats->hp = hp;
1671 bp_stats->tp = tp;
1672 bp_stats->count++;
1673 bp_stats->jiffies = jiffies;
1674 spin_unlock_bh(&ab->base_lock);
1675 }
1676
ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base * ab,struct sk_buff * skb)1677 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
1678 struct sk_buff *skb)
1679 {
1680 struct ath11k_dp *dp = &ab->dp;
1681 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1682 enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
1683 u16 peer_id;
1684 u8 vdev_id;
1685 u8 mac_addr[ETH_ALEN];
1686 u16 peer_mac_h16;
1687 u16 ast_hash;
1688 u16 hw_peer_id;
1689
1690 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1691
1692 switch (type) {
1693 case HTT_T2H_MSG_TYPE_VERSION_CONF:
1694 dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
1695 resp->version_msg.version);
1696 dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
1697 resp->version_msg.version);
1698 complete(&dp->htt_tgt_version_received);
1699 break;
1700 case HTT_T2H_MSG_TYPE_PEER_MAP:
1701 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1702 resp->peer_map_ev.info);
1703 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1704 resp->peer_map_ev.info);
1705 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1706 resp->peer_map_ev.info1);
1707 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1708 peer_mac_h16, mac_addr);
1709 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1710 break;
1711 case HTT_T2H_MSG_TYPE_PEER_MAP2:
1712 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1713 resp->peer_map_ev.info);
1714 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1715 resp->peer_map_ev.info);
1716 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1717 resp->peer_map_ev.info1);
1718 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1719 peer_mac_h16, mac_addr);
1720 ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
1721 resp->peer_map_ev.info2);
1722 hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID,
1723 resp->peer_map_ev.info1);
1724 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1725 hw_peer_id);
1726 break;
1727 case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1728 case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1729 peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
1730 resp->peer_unmap_ev.info);
1731 ath11k_peer_unmap_event(ab, peer_id);
1732 break;
1733 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1734 ath11k_htt_pull_ppdu_stats(ab, skb);
1735 break;
1736 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1737 ath11k_debugfs_htt_ext_stats_handler(ab, skb);
1738 break;
1739 case HTT_T2H_MSG_TYPE_PKTLOG:
1740 ath11k_htt_pktlog(ab, skb);
1741 break;
1742 case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
1743 ath11k_htt_backpressure_event_handler(ab, skb);
1744 break;
1745 default:
1746 ath11k_warn(ab, "htt event %d not handled\n", type);
1747 break;
1748 }
1749
1750 dev_kfree_skb_any(skb);
1751 }
1752
ath11k_dp_rx_msdu_coalesce(struct ath11k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1753 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
1754 struct sk_buff_head *msdu_list,
1755 struct sk_buff *first, struct sk_buff *last,
1756 u8 l3pad_bytes, int msdu_len)
1757 {
1758 struct ath11k_base *ab = ar->ab;
1759 struct sk_buff *skb;
1760 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1761 int buf_first_hdr_len, buf_first_len;
1762 struct hal_rx_desc *ldesc;
1763 int space_extra, rem_len, buf_len;
1764 bool is_continuation;
1765 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
1766
1767 /* As the msdu is spread across multiple rx buffers,
1768 * find the offset to the start of msdu for computing
1769 * the length of the msdu in the first buffer.
1770 */
1771 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1772 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1773
1774 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1775 skb_put(first, buf_first_hdr_len + msdu_len);
1776 skb_pull(first, buf_first_hdr_len);
1777 return 0;
1778 }
1779
1780 ldesc = (struct hal_rx_desc *)last->data;
1781 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc);
1782 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc);
1783
1784 /* MSDU spans over multiple buffers because the length of the MSDU
1785 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1786 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1787 */
1788 skb_put(first, DP_RX_BUFFER_SIZE);
1789 skb_pull(first, buf_first_hdr_len);
1790
1791 /* When an MSDU spread over multiple buffers attention, MSDU_END and
1792 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
1793 */
1794 ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1795
1796 space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1797 if (space_extra > 0 &&
1798 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1799 /* Free up all buffers of the MSDU */
1800 while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1801 rxcb = ATH11K_SKB_RXCB(skb);
1802 if (!rxcb->is_continuation) {
1803 dev_kfree_skb_any(skb);
1804 break;
1805 }
1806 dev_kfree_skb_any(skb);
1807 }
1808 return -ENOMEM;
1809 }
1810
1811 rem_len = msdu_len - buf_first_len;
1812 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1813 rxcb = ATH11K_SKB_RXCB(skb);
1814 is_continuation = rxcb->is_continuation;
1815 if (is_continuation)
1816 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1817 else
1818 buf_len = rem_len;
1819
1820 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1821 WARN_ON_ONCE(1);
1822 dev_kfree_skb_any(skb);
1823 return -EINVAL;
1824 }
1825
1826 skb_put(skb, buf_len + hal_rx_desc_sz);
1827 skb_pull(skb, hal_rx_desc_sz);
1828 skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1829 buf_len);
1830 dev_kfree_skb_any(skb);
1831
1832 rem_len -= buf_len;
1833 if (!is_continuation)
1834 break;
1835 }
1836
1837 return 0;
1838 }
1839
ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1840 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1841 struct sk_buff *first)
1842 {
1843 struct sk_buff *skb;
1844 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1845
1846 if (!rxcb->is_continuation)
1847 return first;
1848
1849 skb_queue_walk(msdu_list, skb) {
1850 rxcb = ATH11K_SKB_RXCB(skb);
1851 if (!rxcb->is_continuation)
1852 return skb;
1853 }
1854
1855 return NULL;
1856 }
1857
ath11k_dp_rx_h_csum_offload(struct ath11k * ar,struct sk_buff * msdu)1858 static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu)
1859 {
1860 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1861 struct rx_attention *rx_attention;
1862 bool ip_csum_fail, l4_csum_fail;
1863
1864 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc);
1865 ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention);
1866 l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention);
1867
1868 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1869 CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1870 }
1871
ath11k_dp_rx_crypto_mic_len(struct ath11k * ar,enum hal_encrypt_type enctype)1872 int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar, enum hal_encrypt_type enctype)
1873 {
1874 switch (enctype) {
1875 case HAL_ENCRYPT_TYPE_OPEN:
1876 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1877 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1878 return 0;
1879 case HAL_ENCRYPT_TYPE_CCMP_128:
1880 return IEEE80211_CCMP_MIC_LEN;
1881 case HAL_ENCRYPT_TYPE_CCMP_256:
1882 return IEEE80211_CCMP_256_MIC_LEN;
1883 case HAL_ENCRYPT_TYPE_GCMP_128:
1884 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1885 return IEEE80211_GCMP_MIC_LEN;
1886 case HAL_ENCRYPT_TYPE_WEP_40:
1887 case HAL_ENCRYPT_TYPE_WEP_104:
1888 case HAL_ENCRYPT_TYPE_WEP_128:
1889 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1890 case HAL_ENCRYPT_TYPE_WAPI:
1891 break;
1892 }
1893
1894 ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1895 return 0;
1896 }
1897
ath11k_dp_rx_crypto_param_len(struct ath11k * ar,enum hal_encrypt_type enctype)1898 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
1899 enum hal_encrypt_type enctype)
1900 {
1901 switch (enctype) {
1902 case HAL_ENCRYPT_TYPE_OPEN:
1903 return 0;
1904 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1905 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1906 return IEEE80211_TKIP_IV_LEN;
1907 case HAL_ENCRYPT_TYPE_CCMP_128:
1908 return IEEE80211_CCMP_HDR_LEN;
1909 case HAL_ENCRYPT_TYPE_CCMP_256:
1910 return IEEE80211_CCMP_256_HDR_LEN;
1911 case HAL_ENCRYPT_TYPE_GCMP_128:
1912 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1913 return IEEE80211_GCMP_HDR_LEN;
1914 case HAL_ENCRYPT_TYPE_WEP_40:
1915 case HAL_ENCRYPT_TYPE_WEP_104:
1916 case HAL_ENCRYPT_TYPE_WEP_128:
1917 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1918 case HAL_ENCRYPT_TYPE_WAPI:
1919 break;
1920 }
1921
1922 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1923 return 0;
1924 }
1925
ath11k_dp_rx_crypto_icv_len(struct ath11k * ar,enum hal_encrypt_type enctype)1926 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
1927 enum hal_encrypt_type enctype)
1928 {
1929 switch (enctype) {
1930 case HAL_ENCRYPT_TYPE_OPEN:
1931 case HAL_ENCRYPT_TYPE_CCMP_128:
1932 case HAL_ENCRYPT_TYPE_CCMP_256:
1933 case HAL_ENCRYPT_TYPE_GCMP_128:
1934 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1935 return 0;
1936 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1937 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1938 return IEEE80211_TKIP_ICV_LEN;
1939 case HAL_ENCRYPT_TYPE_WEP_40:
1940 case HAL_ENCRYPT_TYPE_WEP_104:
1941 case HAL_ENCRYPT_TYPE_WEP_128:
1942 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1943 case HAL_ENCRYPT_TYPE_WAPI:
1944 break;
1945 }
1946
1947 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1948 return 0;
1949 }
1950
ath11k_dp_rx_h_undecap_nwifi(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)1951 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
1952 struct sk_buff *msdu,
1953 u8 *first_hdr,
1954 enum hal_encrypt_type enctype,
1955 struct ieee80211_rx_status *status)
1956 {
1957 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1958 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1959 struct ieee80211_hdr *hdr;
1960 size_t hdr_len;
1961 u8 da[ETH_ALEN];
1962 u8 sa[ETH_ALEN];
1963 u16 qos_ctl = 0;
1964 u8 *qos;
1965
1966 /* copy SA & DA and pull decapped header */
1967 hdr = (struct ieee80211_hdr *)msdu->data;
1968 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1969 ether_addr_copy(da, ieee80211_get_DA(hdr));
1970 ether_addr_copy(sa, ieee80211_get_SA(hdr));
1971 skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
1972
1973 if (rxcb->is_first_msdu) {
1974 /* original 802.11 header is valid for the first msdu
1975 * hence we can reuse the same header
1976 */
1977 hdr = (struct ieee80211_hdr *)first_hdr;
1978 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1979
1980 /* Each A-MSDU subframe will be reported as a separate MSDU,
1981 * so strip the A-MSDU bit from QoS Ctl.
1982 */
1983 if (ieee80211_is_data_qos(hdr->frame_control)) {
1984 qos = ieee80211_get_qos_ctl(hdr);
1985 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
1986 }
1987 } else {
1988 /* Rebuild qos header if this is a middle/last msdu */
1989 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
1990
1991 /* Reset the order bit as the HT_Control header is stripped */
1992 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
1993
1994 qos_ctl = rxcb->tid;
1995
1996 if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc))
1997 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
1998
1999 /* TODO Add other QoS ctl fields when required */
2000
2001 /* copy decap header before overwriting for reuse below */
2002 memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
2003 }
2004
2005 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2006 memcpy(skb_push(msdu,
2007 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2008 (void *)hdr + hdr_len,
2009 ath11k_dp_rx_crypto_param_len(ar, enctype));
2010 }
2011
2012 if (!rxcb->is_first_msdu) {
2013 memcpy(skb_push(msdu,
2014 IEEE80211_QOS_CTL_LEN), &qos_ctl,
2015 IEEE80211_QOS_CTL_LEN);
2016 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
2017 return;
2018 }
2019
2020 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2021
2022 /* original 802.11 header has a different DA and in
2023 * case of 4addr it may also have different SA
2024 */
2025 hdr = (struct ieee80211_hdr *)msdu->data;
2026 ether_addr_copy(ieee80211_get_DA(hdr), da);
2027 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2028 }
2029
ath11k_dp_rx_h_undecap_raw(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2030 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
2031 enum hal_encrypt_type enctype,
2032 struct ieee80211_rx_status *status,
2033 bool decrypted)
2034 {
2035 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2036 struct ieee80211_hdr *hdr;
2037 size_t hdr_len;
2038 size_t crypto_len;
2039
2040 if (!rxcb->is_first_msdu ||
2041 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2042 WARN_ON_ONCE(1);
2043 return;
2044 }
2045
2046 skb_trim(msdu, msdu->len - FCS_LEN);
2047
2048 if (!decrypted)
2049 return;
2050
2051 hdr = (void *)msdu->data;
2052
2053 /* Tail */
2054 if (status->flag & RX_FLAG_IV_STRIPPED) {
2055 skb_trim(msdu, msdu->len -
2056 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2057
2058 skb_trim(msdu, msdu->len -
2059 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2060 } else {
2061 /* MIC */
2062 if (status->flag & RX_FLAG_MIC_STRIPPED)
2063 skb_trim(msdu, msdu->len -
2064 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2065
2066 /* ICV */
2067 if (status->flag & RX_FLAG_ICV_STRIPPED)
2068 skb_trim(msdu, msdu->len -
2069 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2070 }
2071
2072 /* MMIC */
2073 if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2074 !ieee80211_has_morefrags(hdr->frame_control) &&
2075 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2076 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2077
2078 /* Head */
2079 if (status->flag & RX_FLAG_IV_STRIPPED) {
2080 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2081 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2082
2083 memmove((void *)msdu->data + crypto_len,
2084 (void *)msdu->data, hdr_len);
2085 skb_pull(msdu, crypto_len);
2086 }
2087 }
2088
ath11k_dp_rx_h_find_rfc1042(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype)2089 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
2090 struct sk_buff *msdu,
2091 enum hal_encrypt_type enctype)
2092 {
2093 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2094 struct ieee80211_hdr *hdr;
2095 size_t hdr_len, crypto_len;
2096 void *rfc1042;
2097 bool is_amsdu;
2098
2099 is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
2100 hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc);
2101 rfc1042 = hdr;
2102
2103 if (rxcb->is_first_msdu) {
2104 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2105 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2106
2107 rfc1042 += hdr_len + crypto_len;
2108 }
2109
2110 if (is_amsdu)
2111 rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
2112
2113 return rfc1042;
2114 }
2115
ath11k_dp_rx_h_undecap_eth(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2116 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
2117 struct sk_buff *msdu,
2118 u8 *first_hdr,
2119 enum hal_encrypt_type enctype,
2120 struct ieee80211_rx_status *status)
2121 {
2122 struct ieee80211_hdr *hdr;
2123 struct ethhdr *eth;
2124 size_t hdr_len;
2125 u8 da[ETH_ALEN];
2126 u8 sa[ETH_ALEN];
2127 void *rfc1042;
2128
2129 rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
2130 if (WARN_ON_ONCE(!rfc1042))
2131 return;
2132
2133 /* pull decapped header and copy SA & DA */
2134 eth = (struct ethhdr *)msdu->data;
2135 ether_addr_copy(da, eth->h_dest);
2136 ether_addr_copy(sa, eth->h_source);
2137 skb_pull(msdu, sizeof(struct ethhdr));
2138
2139 /* push rfc1042/llc/snap */
2140 memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
2141 sizeof(struct ath11k_dp_rfc1042_hdr));
2142
2143 /* push original 802.11 header */
2144 hdr = (struct ieee80211_hdr *)first_hdr;
2145 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2146
2147 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2148 memcpy(skb_push(msdu,
2149 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2150 (void *)hdr + hdr_len,
2151 ath11k_dp_rx_crypto_param_len(ar, enctype));
2152 }
2153
2154 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2155
2156 /* original 802.11 header has a different DA and in
2157 * case of 4addr it may also have different SA
2158 */
2159 hdr = (struct ieee80211_hdr *)msdu->data;
2160 ether_addr_copy(ieee80211_get_DA(hdr), da);
2161 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2162 }
2163
ath11k_dp_rx_h_undecap(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2164 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
2165 struct hal_rx_desc *rx_desc,
2166 enum hal_encrypt_type enctype,
2167 struct ieee80211_rx_status *status,
2168 bool decrypted)
2169 {
2170 u8 *first_hdr;
2171 u8 decap;
2172 struct ethhdr *ehdr;
2173
2174 first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
2175 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc);
2176
2177 switch (decap) {
2178 case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2179 ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
2180 enctype, status);
2181 break;
2182 case DP_RX_DECAP_TYPE_RAW:
2183 ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2184 decrypted);
2185 break;
2186 case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2187 ehdr = (struct ethhdr *)msdu->data;
2188
2189 /* mac80211 allows fast path only for authorized STA */
2190 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
2191 ATH11K_SKB_RXCB(msdu)->is_eapol = true;
2192 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2193 enctype, status);
2194 break;
2195 }
2196
2197 /* PN for mcast packets will be validated in mac80211;
2198 * remove eth header and add 802.11 header.
2199 */
2200 if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted)
2201 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2202 enctype, status);
2203 break;
2204 case DP_RX_DECAP_TYPE_8023:
2205 /* TODO: Handle undecap for these formats */
2206 break;
2207 }
2208 }
2209
2210 static struct ath11k_peer *
ath11k_dp_rx_h_find_peer(struct ath11k_base * ab,struct sk_buff * msdu)2211 ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu)
2212 {
2213 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2214 struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2215 struct ath11k_peer *peer = NULL;
2216
2217 lockdep_assert_held(&ab->base_lock);
2218
2219 peer = ath11k_peer_find_by_id(ab, rxcb->peer_id);
2220
2221 if (peer)
2222 return peer;
2223
2224 if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
2225 return NULL;
2226
2227 peer = ath11k_peer_find_by_addr(ab,
2228 ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc));
2229 return peer;
2230 }
2231
ath11k_dp_rx_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2232 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
2233 struct sk_buff *msdu,
2234 struct hal_rx_desc *rx_desc,
2235 struct ieee80211_rx_status *rx_status)
2236 {
2237 bool fill_crypto_hdr;
2238 enum hal_encrypt_type enctype;
2239 bool is_decrypted = false;
2240 struct ath11k_skb_rxcb *rxcb;
2241 struct ieee80211_hdr *hdr;
2242 struct ath11k_peer *peer;
2243 struct rx_attention *rx_attention;
2244 u32 err_bitmap;
2245
2246 /* PN for multicast packets will be checked in mac80211 */
2247 rxcb = ATH11K_SKB_RXCB(msdu);
2248 fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
2249 rxcb->is_mcbc = fill_crypto_hdr;
2250
2251 if (rxcb->is_mcbc) {
2252 rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
2253 rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
2254 }
2255
2256 spin_lock_bh(&ar->ab->base_lock);
2257 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2258 if (peer) {
2259 if (rxcb->is_mcbc)
2260 enctype = peer->sec_type_grp;
2261 else
2262 enctype = peer->sec_type;
2263 } else {
2264 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
2265 }
2266 spin_unlock_bh(&ar->ab->base_lock);
2267
2268 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
2269 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
2270 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2271 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
2272
2273 /* Clear per-MPDU flags while leaving per-PPDU flags intact */
2274 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2275 RX_FLAG_MMIC_ERROR |
2276 RX_FLAG_DECRYPTED |
2277 RX_FLAG_IV_STRIPPED |
2278 RX_FLAG_MMIC_STRIPPED);
2279
2280 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
2281 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2282 if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
2283 rx_status->flag |= RX_FLAG_MMIC_ERROR;
2284
2285 if (is_decrypted) {
2286 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2287
2288 if (fill_crypto_hdr)
2289 rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2290 RX_FLAG_ICV_STRIPPED;
2291 else
2292 rx_status->flag |= RX_FLAG_IV_STRIPPED |
2293 RX_FLAG_PN_VALIDATED;
2294 }
2295
2296 ath11k_dp_rx_h_csum_offload(ar, msdu);
2297 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
2298 enctype, rx_status, is_decrypted);
2299
2300 if (!is_decrypted || fill_crypto_hdr)
2301 return;
2302
2303 if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) !=
2304 DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
2305 hdr = (void *)msdu->data;
2306 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2307 }
2308 }
2309
ath11k_dp_rx_h_rate(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2310 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2311 struct ieee80211_rx_status *rx_status)
2312 {
2313 struct ieee80211_supported_band *sband;
2314 enum rx_msdu_start_pkt_type pkt_type;
2315 u8 bw;
2316 u8 rate_mcs, nss;
2317 u8 sgi;
2318 bool is_cck, is_ldpc;
2319
2320 pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc);
2321 bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc);
2322 rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc);
2323 nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc);
2324 sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc);
2325
2326 switch (pkt_type) {
2327 case RX_MSDU_START_PKT_TYPE_11A:
2328 case RX_MSDU_START_PKT_TYPE_11B:
2329 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2330 sband = &ar->mac.sbands[rx_status->band];
2331 rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
2332 is_cck);
2333 break;
2334 case RX_MSDU_START_PKT_TYPE_11N:
2335 rx_status->encoding = RX_ENC_HT;
2336 if (rate_mcs > ATH11K_HT_MCS_MAX) {
2337 ath11k_dbg(ar->ab, ATH11K_DBG_DP_RX,
2338 "Received HT frame with out-of-range mcs %d, capping to %d\n",
2339 rate_mcs, ATH11K_HT_MCS_MAX);
2340 rate_mcs = ATH11K_HT_MCS_MAX;
2341 }
2342 rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2343 if (sgi)
2344 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2345 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2346 break;
2347 case RX_MSDU_START_PKT_TYPE_11AC:
2348 rx_status->encoding = RX_ENC_VHT;
2349 if (rate_mcs > ATH11K_VHT_MCS_MAX) {
2350 ath11k_dbg(ar->ab, ATH11K_DBG_DP_RX,
2351 "Received VHT frame with out-of-range mcs %d, capping to %d\n",
2352 rate_mcs, ATH11K_VHT_MCS_MAX);
2353 rate_mcs = ATH11K_VHT_MCS_MAX;
2354 }
2355 rx_status->rate_idx = rate_mcs;
2356 rx_status->nss = nss;
2357 if (sgi)
2358 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2359 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2360 is_ldpc = ath11k_dp_rx_h_msdu_start_ldpc_support(ar->ab, rx_desc);
2361 if (is_ldpc)
2362 rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
2363 break;
2364 case RX_MSDU_START_PKT_TYPE_11AX:
2365 rx_status->encoding = RX_ENC_HE;
2366 if (rate_mcs > ATH11K_HE_MCS_MAX) {
2367 ath11k_dbg(ar->ab, ATH11K_DBG_DP_RX,
2368 "Received HE frame with out-of-range mcs %d, capping to %d\n",
2369 rate_mcs, ATH11K_HE_MCS_MAX);
2370 rate_mcs = ATH11K_HE_MCS_MAX;
2371 }
2372 rx_status->rate_idx = rate_mcs;
2373 rx_status->nss = nss;
2374 rx_status->he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
2375 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2376 break;
2377 }
2378 }
2379
ath11k_dp_rx_h_ppdu(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2380 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2381 struct ieee80211_rx_status *rx_status)
2382 {
2383 u8 channel_num;
2384 u32 center_freq, meta_data;
2385 struct ieee80211_channel *channel;
2386
2387 rx_status->freq = 0;
2388 rx_status->rate_idx = 0;
2389 rx_status->nss = 0;
2390 rx_status->encoding = RX_ENC_LEGACY;
2391 rx_status->bw = RATE_INFO_BW_20;
2392
2393 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2394
2395 meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc);
2396 channel_num = meta_data;
2397 center_freq = meta_data >> 16;
2398
2399 if (center_freq >= ATH11K_MIN_6G_FREQ &&
2400 center_freq <= ATH11K_MAX_6G_FREQ) {
2401 rx_status->band = NL80211_BAND_6GHZ;
2402 rx_status->freq = center_freq;
2403 } else if (channel_num >= 1 && channel_num <= 14) {
2404 rx_status->band = NL80211_BAND_2GHZ;
2405 } else if (channel_num >= 36 && channel_num <= 177) {
2406 rx_status->band = NL80211_BAND_5GHZ;
2407 } else {
2408 spin_lock_bh(&ar->data_lock);
2409 channel = ar->rx_channel;
2410 if (channel) {
2411 rx_status->band = channel->band;
2412 channel_num =
2413 ieee80211_frequency_to_channel(channel->center_freq);
2414 }
2415 spin_unlock_bh(&ar->data_lock);
2416 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
2417 rx_desc, sizeof(struct hal_rx_desc));
2418 }
2419
2420 if (rx_status->band != NL80211_BAND_6GHZ)
2421 rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2422 rx_status->band);
2423
2424 ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
2425 }
2426
ath11k_dp_rx_deliver_msdu(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)2427 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
2428 struct sk_buff *msdu,
2429 struct ieee80211_rx_status *status)
2430 {
2431 static const struct ieee80211_radiotap_he known = {
2432 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2433 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2434 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2435 };
2436 struct ieee80211_rx_status *rx_status;
2437 struct ieee80211_radiotap_he *he = NULL;
2438 struct ieee80211_sta *pubsta = NULL;
2439 struct ath11k_peer *peer;
2440 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2441 u8 decap = DP_RX_DECAP_TYPE_RAW;
2442 bool is_mcbc = rxcb->is_mcbc;
2443 bool is_eapol = rxcb->is_eapol;
2444
2445 if (status->encoding == RX_ENC_HE &&
2446 !(status->flag & RX_FLAG_RADIOTAP_HE) &&
2447 !(status->flag & RX_FLAG_SKIP_MONITOR)) {
2448 he = skb_push(msdu, sizeof(known));
2449 memcpy(he, &known, sizeof(known));
2450 status->flag |= RX_FLAG_RADIOTAP_HE;
2451 }
2452
2453 if (!(status->flag & RX_FLAG_ONLY_MONITOR))
2454 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc);
2455
2456 spin_lock_bh(&ar->ab->base_lock);
2457 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2458 if (peer && peer->sta)
2459 pubsta = peer->sta;
2460 spin_unlock_bh(&ar->ab->base_lock);
2461
2462 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
2463 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2464 msdu,
2465 msdu->len,
2466 peer ? peer->addr : NULL,
2467 rxcb->tid,
2468 is_mcbc ? "mcast" : "ucast",
2469 rxcb->seq_no,
2470 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2471 (status->encoding == RX_ENC_HT) ? "ht" : "",
2472 (status->encoding == RX_ENC_VHT) ? "vht" : "",
2473 (status->encoding == RX_ENC_HE) ? "he" : "",
2474 (status->bw == RATE_INFO_BW_40) ? "40" : "",
2475 (status->bw == RATE_INFO_BW_80) ? "80" : "",
2476 (status->bw == RATE_INFO_BW_160) ? "160" : "",
2477 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2478 status->rate_idx,
2479 status->nss,
2480 status->freq,
2481 status->band, status->flag,
2482 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2483 !!(status->flag & RX_FLAG_MMIC_ERROR),
2484 !!(status->flag & RX_FLAG_AMSDU_MORE));
2485
2486 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
2487 msdu->data, msdu->len);
2488
2489 rx_status = IEEE80211_SKB_RXCB(msdu);
2490 *rx_status = *status;
2491
2492 /* TODO: trace rx packet */
2493
2494 /* PN for multicast packets are not validate in HW,
2495 * so skip 802.3 rx path
2496 * Also, fast_rx expects the STA to be authorized, hence
2497 * eapol packets are sent in slow path.
2498 */
2499 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
2500 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2501 rx_status->flag |= RX_FLAG_8023;
2502
2503 ieee80211_rx_napi(ar->hw, pubsta, msdu, napi);
2504 }
2505
ath11k_dp_rx_check_nwifi_hdr_len_valid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc,struct sk_buff * msdu)2506 static bool ath11k_dp_rx_check_nwifi_hdr_len_valid(struct ath11k_base *ab,
2507 struct hal_rx_desc *rx_desc,
2508 struct sk_buff *msdu)
2509 {
2510 struct ieee80211_hdr *hdr;
2511 u8 decap_type;
2512 u32 hdr_len;
2513
2514 decap_type = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc);
2515 if (decap_type != DP_RX_DECAP_TYPE_NATIVE_WIFI)
2516 return true;
2517
2518 hdr = (struct ieee80211_hdr *)msdu->data;
2519 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2520
2521 if (likely(hdr_len <= DP_MAX_NWIFI_HDR_LEN))
2522 return true;
2523
2524 ab->soc_stats.invalid_rbm++;
2525 WARN_ON_ONCE(1);
2526 return false;
2527 }
2528
ath11k_dp_rx_process_msdu(struct ath11k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list,struct ieee80211_rx_status * rx_status)2529 static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
2530 struct sk_buff *msdu,
2531 struct sk_buff_head *msdu_list,
2532 struct ieee80211_rx_status *rx_status)
2533 {
2534 struct ath11k_base *ab = ar->ab;
2535 struct hal_rx_desc *rx_desc, *lrx_desc;
2536 struct rx_attention *rx_attention;
2537 struct ath11k_skb_rxcb *rxcb;
2538 struct sk_buff *last_buf;
2539 u8 l3_pad_bytes;
2540 u8 *hdr_status;
2541 u16 msdu_len;
2542 int ret;
2543 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
2544
2545 last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2546 if (!last_buf) {
2547 ath11k_warn(ab,
2548 "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
2549 ret = -EIO;
2550 goto free_out;
2551 }
2552
2553 rx_desc = (struct hal_rx_desc *)msdu->data;
2554 if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) {
2555 ath11k_warn(ar->ab, "msdu len not valid\n");
2556 ret = -EIO;
2557 goto free_out;
2558 }
2559
2560 lrx_desc = (struct hal_rx_desc *)last_buf->data;
2561 rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc);
2562 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
2563 ath11k_warn(ab, "msdu_done bit in attention is not set\n");
2564 ret = -EIO;
2565 goto free_out;
2566 }
2567
2568 rxcb = ATH11K_SKB_RXCB(msdu);
2569 rxcb->rx_desc = rx_desc;
2570 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc);
2571 l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc);
2572
2573 if (rxcb->is_frag) {
2574 skb_pull(msdu, hal_rx_desc_sz);
2575 } else if (!rxcb->is_continuation) {
2576 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2577 hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc);
2578 ret = -EINVAL;
2579 ath11k_warn(ab, "invalid msdu len %u\n", msdu_len);
2580 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
2581 sizeof(struct ieee80211_hdr));
2582 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
2583 sizeof(struct hal_rx_desc));
2584 goto free_out;
2585 }
2586 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2587 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2588 } else {
2589 ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
2590 msdu, last_buf,
2591 l3_pad_bytes, msdu_len);
2592 if (ret) {
2593 ath11k_warn(ab,
2594 "failed to coalesce msdu rx buffer%d\n", ret);
2595 goto free_out;
2596 }
2597 }
2598
2599 if (unlikely(!ath11k_dp_rx_check_nwifi_hdr_len_valid(ab, rx_desc, msdu))) {
2600 ret = -EINVAL;
2601 goto free_out;
2602 }
2603
2604 ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
2605 ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
2606
2607 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2608
2609 return 0;
2610
2611 free_out:
2612 return ret;
2613 }
2614
ath11k_dp_rx_process_received_packets(struct ath11k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int mac_id)2615 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
2616 struct napi_struct *napi,
2617 struct sk_buff_head *msdu_list,
2618 int mac_id)
2619 {
2620 struct sk_buff *msdu;
2621 struct ath11k *ar;
2622 struct ieee80211_rx_status rx_status = {};
2623 int ret;
2624
2625 if (skb_queue_empty(msdu_list))
2626 return;
2627
2628 if (unlikely(!rcu_access_pointer(ab->pdevs_active[mac_id]))) {
2629 __skb_queue_purge(msdu_list);
2630 return;
2631 }
2632
2633 ar = ab->pdevs[mac_id].ar;
2634 if (unlikely(test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags))) {
2635 __skb_queue_purge(msdu_list);
2636 return;
2637 }
2638
2639 while ((msdu = __skb_dequeue(msdu_list))) {
2640 ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
2641 if (unlikely(ret)) {
2642 ath11k_dbg(ab, ATH11K_DBG_DATA,
2643 "Unable to process msdu %d", ret);
2644 dev_kfree_skb_any(msdu);
2645 continue;
2646 }
2647
2648 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
2649 }
2650 }
2651
ath11k_dp_process_rx(struct ath11k_base * ab,int ring_id,struct napi_struct * napi,int budget)2652 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
2653 struct napi_struct *napi, int budget)
2654 {
2655 struct ath11k_dp *dp = &ab->dp;
2656 struct dp_rxdma_ring *rx_ring;
2657 int num_buffs_reaped[MAX_RADIOS] = {};
2658 struct sk_buff_head msdu_list[MAX_RADIOS];
2659 struct ath11k_skb_rxcb *rxcb;
2660 int total_msdu_reaped = 0;
2661 struct hal_srng *srng;
2662 struct sk_buff *msdu;
2663 bool done = false;
2664 int buf_id, mac_id;
2665 struct ath11k *ar;
2666 struct hal_reo_dest_ring *desc;
2667 enum hal_reo_dest_ring_push_reason push_reason;
2668 u32 cookie;
2669 int i;
2670
2671 for (i = 0; i < MAX_RADIOS; i++)
2672 __skb_queue_head_init(&msdu_list[i]);
2673
2674 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2675
2676 spin_lock_bh(&srng->lock);
2677
2678 try_again:
2679 ath11k_hal_srng_access_begin(ab, srng);
2680
2681 while (likely(desc =
2682 (struct hal_reo_dest_ring *)ath11k_hal_srng_dst_get_next_entry(ab,
2683 srng))) {
2684 cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
2685 desc->buf_addr_info.info1);
2686 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
2687 cookie);
2688 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
2689
2690 if (unlikely(buf_id == 0))
2691 continue;
2692
2693 ar = ab->pdevs[mac_id].ar;
2694 rx_ring = &ar->dp.rx_refill_buf_ring;
2695 spin_lock_bh(&rx_ring->idr_lock);
2696 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
2697 if (unlikely(!msdu)) {
2698 ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
2699 buf_id);
2700 spin_unlock_bh(&rx_ring->idr_lock);
2701 continue;
2702 }
2703
2704 idr_remove(&rx_ring->bufs_idr, buf_id);
2705 spin_unlock_bh(&rx_ring->idr_lock);
2706
2707 rxcb = ATH11K_SKB_RXCB(msdu);
2708 dma_unmap_single(ab->dev, rxcb->paddr,
2709 msdu->len + skb_tailroom(msdu),
2710 DMA_FROM_DEVICE);
2711
2712 num_buffs_reaped[mac_id]++;
2713
2714 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
2715 desc->info0);
2716 if (unlikely(push_reason !=
2717 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) {
2718 dev_kfree_skb_any(msdu);
2719 ab->soc_stats.hal_reo_error[ring_id]++;
2720 continue;
2721 }
2722
2723 rxcb->is_first_msdu = !!(desc->rx_msdu_info.info0 &
2724 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2725 rxcb->is_last_msdu = !!(desc->rx_msdu_info.info0 &
2726 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2727 rxcb->is_continuation = !!(desc->rx_msdu_info.info0 &
2728 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2729 rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID,
2730 desc->rx_mpdu_info.meta_data);
2731 rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM,
2732 desc->rx_mpdu_info.info0);
2733 rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
2734 desc->info0);
2735
2736 rxcb->mac_id = mac_id;
2737 __skb_queue_tail(&msdu_list[mac_id], msdu);
2738
2739 if (rxcb->is_continuation) {
2740 done = false;
2741 } else {
2742 total_msdu_reaped++;
2743 done = true;
2744 }
2745
2746 if (total_msdu_reaped >= budget)
2747 break;
2748 }
2749
2750 /* Hw might have updated the head pointer after we cached it.
2751 * In this case, even though there are entries in the ring we'll
2752 * get rx_desc NULL. Give the read another try with updated cached
2753 * head pointer so that we can reap complete MPDU in the current
2754 * rx processing.
2755 */
2756 if (unlikely(!done && ath11k_hal_srng_dst_num_free(ab, srng, true))) {
2757 ath11k_hal_srng_access_end(ab, srng);
2758 goto try_again;
2759 }
2760
2761 ath11k_hal_srng_access_end(ab, srng);
2762
2763 spin_unlock_bh(&srng->lock);
2764
2765 if (unlikely(!total_msdu_reaped))
2766 goto exit;
2767
2768 for (i = 0; i < ab->num_radios; i++) {
2769 if (!num_buffs_reaped[i])
2770 continue;
2771
2772 ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list[i], i);
2773
2774 ar = ab->pdevs[i].ar;
2775 rx_ring = &ar->dp.rx_refill_buf_ring;
2776
2777 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
2778 ab->hw_params.hal_params->rx_buf_rbm);
2779 }
2780 exit:
2781 return total_msdu_reaped;
2782 }
2783
ath11k_dp_rx_update_peer_stats(struct ath11k_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2784 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
2785 struct hal_rx_mon_ppdu_info *ppdu_info)
2786 {
2787 struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
2788 u32 num_msdu;
2789 int i;
2790
2791 if (!rx_stats)
2792 return;
2793
2794 arsta->rssi_comb = ppdu_info->rssi_comb;
2795 ewma_avg_rssi_add(&arsta->avg_rssi, ppdu_info->rssi_comb);
2796
2797 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2798 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2799
2800 rx_stats->num_msdu += num_msdu;
2801 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2802 ppdu_info->tcp_ack_msdu_count;
2803 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2804 rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2805
2806 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2807 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2808 ppdu_info->nss = 1;
2809 ppdu_info->mcs = HAL_RX_MAX_MCS;
2810 ppdu_info->tid = IEEE80211_NUM_TIDS;
2811 }
2812
2813 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
2814 rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
2815
2816 if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
2817 rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
2818
2819 if (ppdu_info->gi < HAL_RX_GI_MAX)
2820 rx_stats->gi_count[ppdu_info->gi] += num_msdu;
2821
2822 if (ppdu_info->bw < HAL_RX_BW_MAX)
2823 rx_stats->bw_count[ppdu_info->bw] += num_msdu;
2824
2825 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2826 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2827
2828 if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2829 rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2830
2831 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2832 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2833
2834 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2835 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2836
2837 if (ppdu_info->is_stbc)
2838 rx_stats->stbc_count += num_msdu;
2839
2840 if (ppdu_info->beamformed)
2841 rx_stats->beamformed_count += num_msdu;
2842
2843 if (ppdu_info->num_mpdu_fcs_ok > 1)
2844 rx_stats->ampdu_msdu_count += num_msdu;
2845 else
2846 rx_stats->non_ampdu_msdu_count += num_msdu;
2847
2848 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2849 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2850 rx_stats->dcm_count += ppdu_info->dcm;
2851 rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
2852
2853 BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) >
2854 ARRAY_SIZE(ppdu_info->rssi_chain_pri20));
2855
2856 for (i = 0; i < ARRAY_SIZE(arsta->chain_signal); i++)
2857 arsta->chain_signal[i] = ppdu_info->rssi_chain_pri20[i];
2858
2859 rx_stats->rx_duration += ppdu_info->rx_duration;
2860 arsta->rx_duration = rx_stats->rx_duration;
2861 }
2862
ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base * ab,struct dp_rxdma_ring * rx_ring,int * buf_id)2863 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
2864 struct dp_rxdma_ring *rx_ring,
2865 int *buf_id)
2866 {
2867 struct sk_buff *skb;
2868 dma_addr_t paddr;
2869
2870 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
2871 DP_RX_BUFFER_ALIGN_SIZE);
2872
2873 if (!skb)
2874 goto fail_alloc_skb;
2875
2876 if (!IS_ALIGNED((unsigned long)skb->data,
2877 DP_RX_BUFFER_ALIGN_SIZE)) {
2878 skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2879 skb->data);
2880 }
2881
2882 paddr = dma_map_single(ab->dev, skb->data,
2883 skb->len + skb_tailroom(skb),
2884 DMA_FROM_DEVICE);
2885 if (unlikely(dma_mapping_error(ab->dev, paddr)))
2886 goto fail_free_skb;
2887
2888 spin_lock_bh(&rx_ring->idr_lock);
2889 *buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
2890 rx_ring->bufs_max, GFP_ATOMIC);
2891 spin_unlock_bh(&rx_ring->idr_lock);
2892 if (*buf_id < 0)
2893 goto fail_dma_unmap;
2894
2895 ATH11K_SKB_RXCB(skb)->paddr = paddr;
2896 return skb;
2897
2898 fail_dma_unmap:
2899 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2900 DMA_FROM_DEVICE);
2901 fail_free_skb:
2902 dev_kfree_skb_any(skb);
2903 fail_alloc_skb:
2904 return NULL;
2905 }
2906
ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)2907 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
2908 struct dp_rxdma_ring *rx_ring,
2909 int req_entries,
2910 enum hal_rx_buf_return_buf_manager mgr)
2911 {
2912 struct hal_srng *srng;
2913 u32 *desc;
2914 struct sk_buff *skb;
2915 int num_free;
2916 int num_remain;
2917 int buf_id;
2918 u32 cookie;
2919 dma_addr_t paddr;
2920
2921 req_entries = min(req_entries, rx_ring->bufs_max);
2922
2923 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2924
2925 spin_lock_bh(&srng->lock);
2926
2927 ath11k_hal_srng_access_begin(ab, srng);
2928
2929 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
2930
2931 req_entries = min(num_free, req_entries);
2932 num_remain = req_entries;
2933
2934 while (num_remain > 0) {
2935 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2936 &buf_id);
2937 if (!skb)
2938 break;
2939 paddr = ATH11K_SKB_RXCB(skb)->paddr;
2940
2941 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
2942 if (!desc)
2943 goto fail_desc_get;
2944
2945 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2946 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2947
2948 num_remain--;
2949
2950 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
2951 }
2952
2953 ath11k_hal_srng_access_end(ab, srng);
2954
2955 spin_unlock_bh(&srng->lock);
2956
2957 return req_entries - num_remain;
2958
2959 fail_desc_get:
2960 spin_lock_bh(&rx_ring->idr_lock);
2961 idr_remove(&rx_ring->bufs_idr, buf_id);
2962 spin_unlock_bh(&rx_ring->idr_lock);
2963 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2964 DMA_FROM_DEVICE);
2965 dev_kfree_skb_any(skb);
2966 ath11k_hal_srng_access_end(ab, srng);
2967 spin_unlock_bh(&srng->lock);
2968
2969 return req_entries - num_remain;
2970 }
2971
2972 #define ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP 32535
2973
2974 static void
ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data * pmon,struct hal_tlv_hdr * tlv)2975 ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data *pmon,
2976 struct hal_tlv_hdr *tlv)
2977 {
2978 struct hal_rx_ppdu_start *ppdu_start;
2979 u16 ppdu_id_diff, ppdu_id, tlv_len;
2980 u8 *ptr;
2981
2982 /* PPDU id is part of second tlv, move ptr to second tlv */
2983 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl);
2984 ptr = (u8 *)tlv;
2985 ptr += sizeof(*tlv) + tlv_len;
2986 tlv = (struct hal_tlv_hdr *)ptr;
2987
2988 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_PPDU_START)
2989 return;
2990
2991 ptr += sizeof(*tlv);
2992 ppdu_start = (struct hal_rx_ppdu_start *)ptr;
2993 ppdu_id = FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID,
2994 __le32_to_cpu(ppdu_start->info0));
2995
2996 if (pmon->sw_mon_entries.ppdu_id < ppdu_id) {
2997 pmon->buf_state = DP_MON_STATUS_LEAD;
2998 ppdu_id_diff = ppdu_id - pmon->sw_mon_entries.ppdu_id;
2999 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
3000 pmon->buf_state = DP_MON_STATUS_LAG;
3001 } else if (pmon->sw_mon_entries.ppdu_id > ppdu_id) {
3002 pmon->buf_state = DP_MON_STATUS_LAG;
3003 ppdu_id_diff = pmon->sw_mon_entries.ppdu_id - ppdu_id;
3004 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
3005 pmon->buf_state = DP_MON_STATUS_LEAD;
3006 }
3007 }
3008
3009 static enum dp_mon_status_buf_state
ath11k_dp_rx_mon_buf_done(struct ath11k_base * ab,struct hal_srng * srng,struct dp_rxdma_ring * rx_ring)3010 ath11k_dp_rx_mon_buf_done(struct ath11k_base *ab, struct hal_srng *srng,
3011 struct dp_rxdma_ring *rx_ring)
3012 {
3013 struct ath11k_skb_rxcb *rxcb;
3014 struct hal_tlv_hdr *tlv;
3015 struct sk_buff *skb;
3016 void *status_desc;
3017 dma_addr_t paddr;
3018 u32 cookie;
3019 int buf_id;
3020 u8 rbm;
3021
3022 status_desc = ath11k_hal_srng_src_next_peek(ab, srng);
3023 if (!status_desc)
3024 return DP_MON_STATUS_NO_DMA;
3025
3026 ath11k_hal_rx_buf_addr_info_get(status_desc, &paddr, &cookie, &rbm);
3027
3028 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3029
3030 spin_lock_bh(&rx_ring->idr_lock);
3031 skb = idr_find(&rx_ring->bufs_idr, buf_id);
3032 spin_unlock_bh(&rx_ring->idr_lock);
3033
3034 if (!skb)
3035 return DP_MON_STATUS_NO_DMA;
3036
3037 rxcb = ATH11K_SKB_RXCB(skb);
3038 dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3039 skb->len + skb_tailroom(skb),
3040 DMA_FROM_DEVICE);
3041
3042 tlv = (struct hal_tlv_hdr *)skb->data;
3043 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_STATUS_BUFFER_DONE)
3044 return DP_MON_STATUS_NO_DMA;
3045
3046 return DP_MON_STATUS_REPLINISH;
3047 }
3048
ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base * ab,int mac_id,int * budget,struct sk_buff_head * skb_list)3049 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
3050 int *budget, struct sk_buff_head *skb_list)
3051 {
3052 struct ath11k *ar;
3053 const struct ath11k_hw_hal_params *hal_params;
3054 enum dp_mon_status_buf_state reap_status;
3055 struct ath11k_pdev_dp *dp;
3056 struct dp_rxdma_ring *rx_ring;
3057 struct ath11k_mon_data *pmon;
3058 struct hal_srng *srng;
3059 void *rx_mon_status_desc;
3060 struct sk_buff *skb;
3061 struct ath11k_skb_rxcb *rxcb;
3062 struct hal_tlv_hdr *tlv;
3063 u32 cookie;
3064 int buf_id, srng_id;
3065 dma_addr_t paddr;
3066 u8 rbm;
3067 int num_buffs_reaped = 0;
3068
3069 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
3070 dp = &ar->dp;
3071 pmon = &dp->mon_data;
3072 srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
3073 rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
3074
3075 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
3076
3077 spin_lock_bh(&srng->lock);
3078
3079 ath11k_hal_srng_access_begin(ab, srng);
3080 while (*budget) {
3081 *budget -= 1;
3082 rx_mon_status_desc =
3083 ath11k_hal_srng_src_peek(ab, srng);
3084 if (!rx_mon_status_desc) {
3085 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3086 break;
3087 }
3088
3089 ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
3090 &cookie, &rbm);
3091 if (paddr) {
3092 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3093
3094 spin_lock_bh(&rx_ring->idr_lock);
3095 skb = idr_find(&rx_ring->bufs_idr, buf_id);
3096 spin_unlock_bh(&rx_ring->idr_lock);
3097
3098 if (!skb) {
3099 ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
3100 buf_id);
3101 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3102 goto move_next;
3103 }
3104
3105 rxcb = ATH11K_SKB_RXCB(skb);
3106
3107 dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3108 skb->len + skb_tailroom(skb),
3109 DMA_FROM_DEVICE);
3110
3111 tlv = (struct hal_tlv_hdr *)skb->data;
3112 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
3113 HAL_RX_STATUS_BUFFER_DONE) {
3114 ath11k_warn(ab, "mon status DONE not set %lx, buf_id %d\n",
3115 FIELD_GET(HAL_TLV_HDR_TAG,
3116 tlv->tl), buf_id);
3117 /* RxDMA status done bit might not be set even
3118 * though tp is moved by HW.
3119 */
3120
3121 /* If done status is missing:
3122 * 1. As per MAC team's suggestion,
3123 * when HP + 1 entry is peeked and if DMA
3124 * is not done and if HP + 2 entry's DMA done
3125 * is set. skip HP + 1 entry and
3126 * start processing in next interrupt.
3127 * 2. If HP + 2 entry's DMA done is not set,
3128 * poll onto HP + 1 entry DMA done to be set.
3129 * Check status for same buffer for next time
3130 * dp_rx_mon_status_srng_process
3131 */
3132
3133 reap_status = ath11k_dp_rx_mon_buf_done(ab, srng,
3134 rx_ring);
3135 if (reap_status == DP_MON_STATUS_NO_DMA)
3136 continue;
3137
3138 spin_lock_bh(&rx_ring->idr_lock);
3139 idr_remove(&rx_ring->bufs_idr, buf_id);
3140 spin_unlock_bh(&rx_ring->idr_lock);
3141
3142 dma_unmap_single(ab->dev, rxcb->paddr,
3143 skb->len + skb_tailroom(skb),
3144 DMA_FROM_DEVICE);
3145
3146 dev_kfree_skb_any(skb);
3147 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3148 goto move_next;
3149 }
3150
3151 spin_lock_bh(&rx_ring->idr_lock);
3152 idr_remove(&rx_ring->bufs_idr, buf_id);
3153 spin_unlock_bh(&rx_ring->idr_lock);
3154 if (ab->hw_params.full_monitor_mode) {
3155 ath11k_dp_rx_mon_update_status_buf_state(pmon, tlv);
3156 if (paddr == pmon->mon_status_paddr)
3157 pmon->buf_state = DP_MON_STATUS_MATCH;
3158 }
3159
3160 dma_unmap_single(ab->dev, rxcb->paddr,
3161 skb->len + skb_tailroom(skb),
3162 DMA_FROM_DEVICE);
3163
3164 __skb_queue_tail(skb_list, skb);
3165 } else {
3166 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3167 }
3168 move_next:
3169 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
3170 &buf_id);
3171
3172 if (!skb) {
3173 hal_params = ab->hw_params.hal_params;
3174 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
3175 hal_params->rx_buf_rbm);
3176 num_buffs_reaped++;
3177 break;
3178 }
3179 rxcb = ATH11K_SKB_RXCB(skb);
3180
3181 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
3182 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3183
3184 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
3185 cookie,
3186 ab->hw_params.hal_params->rx_buf_rbm);
3187 ath11k_hal_srng_src_get_next_entry(ab, srng);
3188 num_buffs_reaped++;
3189 }
3190 ath11k_hal_srng_access_end(ab, srng);
3191 spin_unlock_bh(&srng->lock);
3192
3193 return num_buffs_reaped;
3194 }
3195
ath11k_dp_rx_frag_timer(struct timer_list * timer)3196 static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
3197 {
3198 struct dp_rx_tid *rx_tid = timer_container_of(rx_tid, timer,
3199 frag_timer);
3200
3201 spin_lock_bh(&rx_tid->ab->base_lock);
3202 if (rx_tid->last_frag_no &&
3203 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
3204 spin_unlock_bh(&rx_tid->ab->base_lock);
3205 return;
3206 }
3207 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3208 spin_unlock_bh(&rx_tid->ab->base_lock);
3209 }
3210
ath11k_peer_rx_frag_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id)3211 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
3212 {
3213 struct ath11k_base *ab = ar->ab;
3214 struct ath11k_peer *peer;
3215 struct dp_rx_tid *rx_tid;
3216 int i;
3217
3218 if (fips_enabled) {
3219 ath11k_warn(ab, "This driver is disabled due to FIPS\n");
3220 return -ENOENT;
3221 }
3222
3223 spin_lock_bh(&ab->base_lock);
3224
3225 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
3226 if (!peer) {
3227 ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
3228 spin_unlock_bh(&ab->base_lock);
3229 return -ENOENT;
3230 }
3231
3232 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
3233 rx_tid = &peer->rx_tid[i];
3234 rx_tid->ab = ab;
3235 timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
3236 skb_queue_head_init(&rx_tid->rx_frags);
3237 }
3238
3239 peer->dp_setup_done = true;
3240 spin_unlock_bh(&ab->base_lock);
3241
3242 return 0;
3243 }
3244
ath11k_dp_rx_h_verify_tkip_mic(struct ath11k * ar,struct ath11k_peer * peer,struct sk_buff * msdu)3245 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
3246 struct sk_buff *msdu)
3247 {
3248 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3249 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
3250 struct ieee80211_key_conf *key_conf;
3251 struct ieee80211_hdr *hdr;
3252 u8 mic[IEEE80211_CCMP_MIC_LEN];
3253 int head_len, tail_len;
3254 size_t data_len;
3255 u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3256 u8 *key, *data;
3257 u8 key_idx;
3258
3259 if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) !=
3260 HAL_ENCRYPT_TYPE_TKIP_MIC)
3261 return 0;
3262
3263 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3264 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3265 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
3266 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3267
3268 if (!is_multicast_ether_addr(hdr->addr1))
3269 key_idx = peer->ucast_keyidx;
3270 else
3271 key_idx = peer->mcast_keyidx;
3272
3273 key_conf = peer->keys[key_idx];
3274
3275 data = msdu->data + head_len;
3276 data_len = msdu->len - head_len - tail_len;
3277 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3278
3279 michael_mic(key, hdr, data, data_len, mic);
3280 if (memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3281 goto mic_fail;
3282
3283 return 0;
3284
3285 mic_fail:
3286 (ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
3287 (ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
3288
3289 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3290 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3291 skb_pull(msdu, hal_rx_desc_sz);
3292
3293 if (unlikely(!ath11k_dp_rx_check_nwifi_hdr_len_valid(ar->ab, rx_desc,
3294 msdu))) {
3295 dev_kfree_skb_any(msdu);
3296 return -EINVAL;
3297 }
3298
3299 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3300 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
3301 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3302 ieee80211_rx(ar->hw, msdu);
3303 return -EINVAL;
3304 }
3305
ath11k_dp_rx_h_undecap_frag(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)3306 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
3307 enum hal_encrypt_type enctype, u32 flags)
3308 {
3309 struct ieee80211_hdr *hdr;
3310 size_t hdr_len;
3311 size_t crypto_len;
3312 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3313
3314 if (!flags)
3315 return;
3316
3317 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3318
3319 if (flags & RX_FLAG_MIC_STRIPPED)
3320 skb_trim(msdu, msdu->len -
3321 ath11k_dp_rx_crypto_mic_len(ar, enctype));
3322
3323 if (flags & RX_FLAG_ICV_STRIPPED)
3324 skb_trim(msdu, msdu->len -
3325 ath11k_dp_rx_crypto_icv_len(ar, enctype));
3326
3327 if (flags & RX_FLAG_IV_STRIPPED) {
3328 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3329 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
3330
3331 memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len,
3332 (void *)msdu->data + hal_rx_desc_sz, hdr_len);
3333 skb_pull(msdu, crypto_len);
3334 }
3335 }
3336
ath11k_dp_rx_h_defrag(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)3337 static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
3338 struct ath11k_peer *peer,
3339 struct dp_rx_tid *rx_tid,
3340 struct sk_buff **defrag_skb)
3341 {
3342 struct hal_rx_desc *rx_desc;
3343 struct sk_buff *skb, *first_frag, *last_frag;
3344 struct ieee80211_hdr *hdr;
3345 struct rx_attention *rx_attention;
3346 enum hal_encrypt_type enctype;
3347 bool is_decrypted = false;
3348 int msdu_len = 0;
3349 int extra_space;
3350 u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3351
3352 first_frag = skb_peek(&rx_tid->rx_frags);
3353 last_frag = skb_peek_tail(&rx_tid->rx_frags);
3354
3355 skb_queue_walk(&rx_tid->rx_frags, skb) {
3356 flags = 0;
3357 rx_desc = (struct hal_rx_desc *)skb->data;
3358 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3359
3360 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
3361 if (enctype != HAL_ENCRYPT_TYPE_OPEN) {
3362 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
3363 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
3364 }
3365
3366 if (is_decrypted) {
3367 if (skb != first_frag)
3368 flags |= RX_FLAG_IV_STRIPPED;
3369 if (skb != last_frag)
3370 flags |= RX_FLAG_ICV_STRIPPED |
3371 RX_FLAG_MIC_STRIPPED;
3372 }
3373
3374 /* RX fragments are always raw packets */
3375 if (skb != last_frag)
3376 skb_trim(skb, skb->len - FCS_LEN);
3377 ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3378
3379 if (skb != first_frag)
3380 skb_pull(skb, hal_rx_desc_sz +
3381 ieee80211_hdrlen(hdr->frame_control));
3382 msdu_len += skb->len;
3383 }
3384
3385 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3386 if (extra_space > 0 &&
3387 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3388 return -ENOMEM;
3389
3390 __skb_unlink(first_frag, &rx_tid->rx_frags);
3391 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3392 skb_put_data(first_frag, skb->data, skb->len);
3393 dev_kfree_skb_any(skb);
3394 }
3395
3396 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
3397 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3398 ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
3399
3400 if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3401 first_frag = NULL;
3402
3403 *defrag_skb = first_frag;
3404 return 0;
3405 }
3406
ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k * ar,struct dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3407 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
3408 struct sk_buff *defrag_skb)
3409 {
3410 struct ath11k_base *ab = ar->ab;
3411 struct ath11k_pdev_dp *dp = &ar->dp;
3412 struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
3413 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3414 struct hal_reo_entrance_ring *reo_ent_ring;
3415 struct hal_reo_dest_ring *reo_dest_ring;
3416 struct dp_link_desc_bank *link_desc_banks;
3417 struct hal_rx_msdu_link *msdu_link;
3418 struct hal_rx_msdu_details *msdu0;
3419 struct hal_srng *srng;
3420 dma_addr_t paddr;
3421 u32 desc_bank, msdu_info, mpdu_info;
3422 u32 dst_idx, cookie, hal_rx_desc_sz;
3423 int ret, buf_id;
3424
3425 hal_rx_desc_sz = ab->hw_params.hal_desc_sz;
3426 link_desc_banks = ab->dp.link_desc_banks;
3427 reo_dest_ring = rx_tid->dst_ring_desc;
3428
3429 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3430 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3431 (paddr - link_desc_banks[desc_bank].paddr));
3432 msdu0 = &msdu_link->msdu_link[0];
3433 dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
3434 memset(msdu0, 0, sizeof(*msdu0));
3435
3436 msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
3437 FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
3438 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
3439 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
3440 defrag_skb->len - hal_rx_desc_sz) |
3441 FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
3442 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
3443 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
3444 msdu0->rx_msdu_info.info0 = msdu_info;
3445
3446 /* change msdu len in hal rx desc */
3447 ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3448
3449 paddr = dma_map_single(ab->dev, defrag_skb->data,
3450 defrag_skb->len + skb_tailroom(defrag_skb),
3451 DMA_TO_DEVICE);
3452 if (dma_mapping_error(ab->dev, paddr))
3453 return -ENOMEM;
3454
3455 spin_lock_bh(&rx_refill_ring->idr_lock);
3456 buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
3457 rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
3458 spin_unlock_bh(&rx_refill_ring->idr_lock);
3459 if (buf_id < 0) {
3460 ret = -ENOMEM;
3461 goto err_unmap_dma;
3462 }
3463
3464 ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
3465 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
3466 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3467
3468 ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie,
3469 ab->hw_params.hal_params->rx_buf_rbm);
3470
3471 /* Fill mpdu details into reo entrance ring */
3472 srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
3473
3474 spin_lock_bh(&srng->lock);
3475 ath11k_hal_srng_access_begin(ab, srng);
3476
3477 reo_ent_ring = (struct hal_reo_entrance_ring *)
3478 ath11k_hal_srng_src_get_next_entry(ab, srng);
3479 if (!reo_ent_ring) {
3480 ath11k_hal_srng_access_end(ab, srng);
3481 spin_unlock_bh(&srng->lock);
3482 ret = -ENOSPC;
3483 goto err_free_idr;
3484 }
3485 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3486
3487 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3488 ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
3489 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
3490
3491 mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
3492 FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
3493 FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
3494 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
3495 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
3496 FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
3497 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
3498
3499 reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
3500 reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
3501 reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
3502 reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
3503 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
3504 reo_dest_ring->info0)) |
3505 FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
3506 ath11k_hal_srng_access_end(ab, srng);
3507 spin_unlock_bh(&srng->lock);
3508
3509 return 0;
3510
3511 err_free_idr:
3512 spin_lock_bh(&rx_refill_ring->idr_lock);
3513 idr_remove(&rx_refill_ring->bufs_idr, buf_id);
3514 spin_unlock_bh(&rx_refill_ring->idr_lock);
3515 err_unmap_dma:
3516 dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3517 DMA_TO_DEVICE);
3518 return ret;
3519 }
3520
ath11k_dp_rx_h_cmp_frags(struct ath11k * ar,struct sk_buff * a,struct sk_buff * b)3521 static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar,
3522 struct sk_buff *a, struct sk_buff *b)
3523 {
3524 int frag1, frag2;
3525
3526 frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a);
3527 frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b);
3528
3529 return frag1 - frag2;
3530 }
3531
ath11k_dp_rx_h_sort_frags(struct ath11k * ar,struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3532 static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar,
3533 struct sk_buff_head *frag_list,
3534 struct sk_buff *cur_frag)
3535 {
3536 struct sk_buff *skb;
3537 int cmp;
3538
3539 skb_queue_walk(frag_list, skb) {
3540 cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag);
3541 if (cmp < 0)
3542 continue;
3543 __skb_queue_before(frag_list, skb, cur_frag);
3544 return;
3545 }
3546 __skb_queue_tail(frag_list, cur_frag);
3547 }
3548
ath11k_dp_rx_h_get_pn(struct ath11k * ar,struct sk_buff * skb)3549 static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb)
3550 {
3551 struct ieee80211_hdr *hdr;
3552 u64 pn = 0;
3553 u8 *ehdr;
3554 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3555
3556 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3557 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3558
3559 pn = ehdr[0];
3560 pn |= (u64)ehdr[1] << 8;
3561 pn |= (u64)ehdr[4] << 16;
3562 pn |= (u64)ehdr[5] << 24;
3563 pn |= (u64)ehdr[6] << 32;
3564 pn |= (u64)ehdr[7] << 40;
3565
3566 return pn;
3567 }
3568
3569 static bool
ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k * ar,struct dp_rx_tid * rx_tid)3570 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
3571 {
3572 enum hal_encrypt_type encrypt_type;
3573 struct sk_buff *first_frag, *skb;
3574 struct hal_rx_desc *desc;
3575 u64 last_pn;
3576 u64 cur_pn;
3577
3578 first_frag = skb_peek(&rx_tid->rx_frags);
3579 desc = (struct hal_rx_desc *)first_frag->data;
3580
3581 encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc);
3582 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3583 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3584 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3585 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3586 return true;
3587
3588 last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag);
3589 skb_queue_walk(&rx_tid->rx_frags, skb) {
3590 if (skb == first_frag)
3591 continue;
3592
3593 cur_pn = ath11k_dp_rx_h_get_pn(ar, skb);
3594 if (cur_pn != last_pn + 1)
3595 return false;
3596 last_pn = cur_pn;
3597 }
3598 return true;
3599 }
3600
ath11k_dp_rx_frag_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,u32 * ring_desc)3601 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
3602 struct sk_buff *msdu,
3603 u32 *ring_desc)
3604 {
3605 struct ath11k_base *ab = ar->ab;
3606 struct hal_rx_desc *rx_desc;
3607 struct ath11k_peer *peer;
3608 struct dp_rx_tid *rx_tid;
3609 struct sk_buff *defrag_skb = NULL;
3610 u32 peer_id;
3611 u16 seqno, frag_no;
3612 u8 tid;
3613 int ret = 0;
3614 bool more_frags;
3615 bool is_mcbc;
3616
3617 rx_desc = (struct hal_rx_desc *)msdu->data;
3618 peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
3619 tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc);
3620 seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
3621 frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu);
3622 more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu);
3623 is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
3624
3625 /* Multicast/Broadcast fragments are not expected */
3626 if (is_mcbc)
3627 return -EINVAL;
3628
3629 if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) ||
3630 !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) ||
3631 tid > IEEE80211_NUM_TIDS)
3632 return -EINVAL;
3633
3634 /* received unfragmented packet in reo
3635 * exception ring, this shouldn't happen
3636 * as these packets typically come from
3637 * reo2sw srngs.
3638 */
3639 if (WARN_ON_ONCE(!frag_no && !more_frags))
3640 return -EINVAL;
3641
3642 spin_lock_bh(&ab->base_lock);
3643 peer = ath11k_peer_find_by_id(ab, peer_id);
3644 if (!peer) {
3645 ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3646 peer_id);
3647 ret = -ENOENT;
3648 goto out_unlock;
3649 }
3650 if (!peer->dp_setup_done) {
3651 ath11k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n",
3652 peer->addr, peer_id);
3653 ret = -ENOENT;
3654 goto out_unlock;
3655 }
3656
3657 rx_tid = &peer->rx_tid[tid];
3658
3659 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3660 skb_queue_empty(&rx_tid->rx_frags)) {
3661 /* Flush stored fragments and start a new sequence */
3662 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3663 rx_tid->cur_sn = seqno;
3664 }
3665
3666 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3667 /* Fragment already present */
3668 ret = -EINVAL;
3669 goto out_unlock;
3670 }
3671
3672 if (!rx_tid->rx_frag_bitmap || (frag_no > __fls(rx_tid->rx_frag_bitmap)))
3673 __skb_queue_tail(&rx_tid->rx_frags, msdu);
3674 else
3675 ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu);
3676
3677 rx_tid->rx_frag_bitmap |= BIT(frag_no);
3678 if (!more_frags)
3679 rx_tid->last_frag_no = frag_no;
3680
3681 if (frag_no == 0) {
3682 rx_tid->dst_ring_desc = kmemdup(ring_desc,
3683 sizeof(*rx_tid->dst_ring_desc),
3684 GFP_ATOMIC);
3685 if (!rx_tid->dst_ring_desc) {
3686 ret = -ENOMEM;
3687 goto out_unlock;
3688 }
3689 } else {
3690 ath11k_dp_rx_link_desc_return(ab, ring_desc,
3691 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3692 }
3693
3694 if (!rx_tid->last_frag_no ||
3695 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3696 mod_timer(&rx_tid->frag_timer, jiffies +
3697 ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
3698 goto out_unlock;
3699 }
3700
3701 spin_unlock_bh(&ab->base_lock);
3702 timer_delete_sync(&rx_tid->frag_timer);
3703 spin_lock_bh(&ab->base_lock);
3704
3705 peer = ath11k_peer_find_by_id(ab, peer_id);
3706 if (!peer)
3707 goto err_frags_cleanup;
3708
3709 if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3710 goto err_frags_cleanup;
3711
3712 if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3713 goto err_frags_cleanup;
3714
3715 if (!defrag_skb)
3716 goto err_frags_cleanup;
3717
3718 if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3719 goto err_frags_cleanup;
3720
3721 ath11k_dp_rx_frags_cleanup(rx_tid, false);
3722 goto out_unlock;
3723
3724 err_frags_cleanup:
3725 dev_kfree_skb_any(defrag_skb);
3726 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3727 out_unlock:
3728 spin_unlock_bh(&ab->base_lock);
3729 return ret;
3730 }
3731
3732 static int
ath11k_dp_process_rx_err_buf(struct ath11k * ar,u32 * ring_desc,int buf_id,bool drop)3733 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
3734 {
3735 struct ath11k_pdev_dp *dp = &ar->dp;
3736 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
3737 struct sk_buff *msdu;
3738 struct ath11k_skb_rxcb *rxcb;
3739 struct hal_rx_desc *rx_desc;
3740 u8 *hdr_status;
3741 u16 msdu_len;
3742 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3743
3744 spin_lock_bh(&rx_ring->idr_lock);
3745 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3746 if (!msdu) {
3747 ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
3748 buf_id);
3749 spin_unlock_bh(&rx_ring->idr_lock);
3750 return -EINVAL;
3751 }
3752
3753 idr_remove(&rx_ring->bufs_idr, buf_id);
3754 spin_unlock_bh(&rx_ring->idr_lock);
3755
3756 rxcb = ATH11K_SKB_RXCB(msdu);
3757 dma_unmap_single(ar->ab->dev, rxcb->paddr,
3758 msdu->len + skb_tailroom(msdu),
3759 DMA_FROM_DEVICE);
3760
3761 if (drop) {
3762 dev_kfree_skb_any(msdu);
3763 return 0;
3764 }
3765
3766 rcu_read_lock();
3767 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3768 dev_kfree_skb_any(msdu);
3769 goto exit;
3770 }
3771
3772 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
3773 dev_kfree_skb_any(msdu);
3774 goto exit;
3775 }
3776
3777 rx_desc = (struct hal_rx_desc *)msdu->data;
3778 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc);
3779 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3780 hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
3781 ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3782 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
3783 sizeof(struct ieee80211_hdr));
3784 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
3785 sizeof(struct hal_rx_desc));
3786 dev_kfree_skb_any(msdu);
3787 goto exit;
3788 }
3789
3790 skb_put(msdu, hal_rx_desc_sz + msdu_len);
3791
3792 if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
3793 dev_kfree_skb_any(msdu);
3794 ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
3795 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3796 }
3797 exit:
3798 rcu_read_unlock();
3799 return 0;
3800 }
3801
ath11k_dp_process_rx_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3802 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
3803 int budget)
3804 {
3805 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3806 struct dp_link_desc_bank *link_desc_banks;
3807 enum hal_rx_buf_return_buf_manager rbm;
3808 int tot_n_bufs_reaped, quota, ret, i;
3809 int n_bufs_reaped[MAX_RADIOS] = {};
3810 struct dp_rxdma_ring *rx_ring;
3811 struct dp_srng *reo_except;
3812 u32 desc_bank, num_msdus;
3813 struct hal_srng *srng;
3814 struct ath11k_dp *dp;
3815 void *link_desc_va;
3816 int buf_id, mac_id;
3817 struct ath11k *ar;
3818 dma_addr_t paddr;
3819 u32 *desc;
3820 bool is_frag;
3821 u8 drop = 0;
3822
3823 tot_n_bufs_reaped = 0;
3824 quota = budget;
3825
3826 dp = &ab->dp;
3827 reo_except = &dp->reo_except_ring;
3828 link_desc_banks = dp->link_desc_banks;
3829
3830 srng = &ab->hal.srng_list[reo_except->ring_id];
3831
3832 spin_lock_bh(&srng->lock);
3833
3834 ath11k_hal_srng_access_begin(ab, srng);
3835
3836 while (budget &&
3837 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
3838 struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
3839
3840 ab->soc_stats.err_ring_pkts++;
3841 ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
3842 &desc_bank);
3843 if (ret) {
3844 ath11k_warn(ab, "failed to parse error reo desc %d\n",
3845 ret);
3846 continue;
3847 }
3848 link_desc_va = link_desc_banks[desc_bank].vaddr +
3849 (paddr - link_desc_banks[desc_bank].paddr);
3850 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3851 &rbm);
3852 if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
3853 rbm != HAL_RX_BUF_RBM_SW1_BM &&
3854 rbm != HAL_RX_BUF_RBM_SW3_BM) {
3855 ab->soc_stats.invalid_rbm++;
3856 ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
3857 ath11k_dp_rx_link_desc_return(ab, desc,
3858 HAL_WBM_REL_BM_ACT_REL_MSDU);
3859 continue;
3860 }
3861
3862 is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
3863
3864 /* Process only rx fragments with one msdu per link desc below, and drop
3865 * msdu's indicated due to error reasons.
3866 */
3867 if (!is_frag || num_msdus > 1) {
3868 drop = 1;
3869 /* Return the link desc back to wbm idle list */
3870 ath11k_dp_rx_link_desc_return(ab, desc,
3871 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3872 }
3873
3874 for (i = 0; i < num_msdus; i++) {
3875 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
3876 msdu_cookies[i]);
3877
3878 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
3879 msdu_cookies[i]);
3880
3881 ar = ab->pdevs[mac_id].ar;
3882
3883 if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
3884 n_bufs_reaped[mac_id]++;
3885 tot_n_bufs_reaped++;
3886 }
3887 }
3888
3889 if (tot_n_bufs_reaped >= quota) {
3890 tot_n_bufs_reaped = quota;
3891 goto exit;
3892 }
3893
3894 budget = quota - tot_n_bufs_reaped;
3895 }
3896
3897 exit:
3898 ath11k_hal_srng_access_end(ab, srng);
3899
3900 spin_unlock_bh(&srng->lock);
3901
3902 for (i = 0; i < ab->num_radios; i++) {
3903 if (!n_bufs_reaped[i])
3904 continue;
3905
3906 ar = ab->pdevs[i].ar;
3907 rx_ring = &ar->dp.rx_refill_buf_ring;
3908
3909 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
3910 ab->hw_params.hal_params->rx_buf_rbm);
3911 }
3912
3913 return tot_n_bufs_reaped;
3914 }
3915
ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k * ar,int msdu_len,struct sk_buff_head * msdu_list)3916 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
3917 int msdu_len,
3918 struct sk_buff_head *msdu_list)
3919 {
3920 struct sk_buff *skb, *tmp;
3921 struct ath11k_skb_rxcb *rxcb;
3922 int n_buffs;
3923
3924 n_buffs = DIV_ROUND_UP(msdu_len,
3925 (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz));
3926
3927 skb_queue_walk_safe(msdu_list, skb, tmp) {
3928 rxcb = ATH11K_SKB_RXCB(skb);
3929 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3930 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3931 if (!n_buffs)
3932 break;
3933 __skb_unlink(skb, msdu_list);
3934 dev_kfree_skb_any(skb);
3935 n_buffs--;
3936 }
3937 }
3938 }
3939
ath11k_dp_rx_h_null_q_desc(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3940 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
3941 struct ieee80211_rx_status *status,
3942 struct sk_buff_head *msdu_list)
3943 {
3944 u16 msdu_len;
3945 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3946 struct rx_attention *rx_attention;
3947 u8 l3pad_bytes;
3948 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3949 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3950
3951 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
3952
3953 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
3954 /* First buffer will be freed by the caller, so deduct it's length */
3955 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
3956 ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3957 return -EINVAL;
3958 }
3959
3960 rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc);
3961 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
3962 ath11k_warn(ar->ab,
3963 "msdu_done bit not set in null_q_des processing\n");
3964 __skb_queue_purge(msdu_list);
3965 return -EIO;
3966 }
3967
3968 /* Handle NULL queue descriptor violations arising out a missing
3969 * REO queue for a given peer or a given TID. This typically
3970 * may happen if a packet is received on a QOS enabled TID before the
3971 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3972 * it may also happen for MC/BC frames if they are not routed to the
3973 * non-QOS TID queue, in the absence of any other default TID queue.
3974 * This error can show up both in a REO destination or WBM release ring.
3975 */
3976
3977 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
3978 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
3979
3980 if (rxcb->is_frag) {
3981 skb_pull(msdu, hal_rx_desc_sz);
3982 } else {
3983 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
3984
3985 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
3986 return -EINVAL;
3987
3988 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3989 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3990 }
3991
3992 if (unlikely(!ath11k_dp_rx_check_nwifi_hdr_len_valid(ar->ab, desc, msdu)))
3993 return -EINVAL;
3994
3995 ath11k_dp_rx_h_ppdu(ar, desc, status);
3996
3997 ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
3998
3999 rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc);
4000
4001 /* Please note that caller will having the access to msdu and completing
4002 * rx with mac80211. Need not worry about cleaning up amsdu_list.
4003 */
4004
4005 return 0;
4006 }
4007
ath11k_dp_rx_h_reo_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)4008 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
4009 struct ieee80211_rx_status *status,
4010 struct sk_buff_head *msdu_list)
4011 {
4012 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4013 bool drop = false;
4014
4015 ar->ab->soc_stats.reo_error[rxcb->err_code]++;
4016
4017 switch (rxcb->err_code) {
4018 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
4019 if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
4020 drop = true;
4021 break;
4022 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
4023 /* TODO: Do not drop PN failed packets in the driver;
4024 * instead, it is good to drop such packets in mac80211
4025 * after incrementing the replay counters.
4026 */
4027 fallthrough;
4028 default:
4029 /* TODO: Review other errors and process them to mac80211
4030 * as appropriate.
4031 */
4032 drop = true;
4033 break;
4034 }
4035
4036 return drop;
4037 }
4038
ath11k_dp_rx_h_tkip_mic_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4039 static bool ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
4040 struct ieee80211_rx_status *status)
4041 {
4042 u16 msdu_len;
4043 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
4044 u8 l3pad_bytes;
4045 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4046 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
4047 struct ath11k_base *ab = ar->ab;
4048
4049 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
4050 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
4051
4052 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
4053 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
4054
4055 if (unlikely(hal_rx_desc_sz + l3pad_bytes + msdu_len > DP_RX_BUFFER_SIZE)) {
4056 ath11k_dbg(ab, ATH11K_DBG_DATA,
4057 "invalid msdu len in tkip mic err %u\n", msdu_len);
4058 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", desc,
4059 sizeof(*desc));
4060 return true;
4061 }
4062
4063 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
4064 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
4065
4066 if (unlikely(!ath11k_dp_rx_check_nwifi_hdr_len_valid(ab, desc, msdu)))
4067 return true;
4068
4069 ath11k_dp_rx_h_ppdu(ar, desc, status);
4070
4071 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
4072 RX_FLAG_DECRYPTED);
4073
4074 ath11k_dp_rx_h_undecap(ar, msdu, desc,
4075 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
4076
4077 return false;
4078 }
4079
ath11k_dp_rx_h_rxdma_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4080 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu,
4081 struct ieee80211_rx_status *status)
4082 {
4083 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4084 bool drop;
4085
4086 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
4087
4088 switch (rxcb->err_code) {
4089 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
4090 drop = ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
4091 break;
4092 default:
4093 /* TODO: Review other rxdma error code to check if anything is
4094 * worth reporting to mac80211
4095 */
4096 drop = true;
4097 break;
4098 }
4099
4100 return drop;
4101 }
4102
ath11k_dp_rx_wbm_err(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)4103 static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
4104 struct napi_struct *napi,
4105 struct sk_buff *msdu,
4106 struct sk_buff_head *msdu_list)
4107 {
4108 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4109 struct ieee80211_rx_status rxs = {};
4110 bool drop = true;
4111
4112 switch (rxcb->err_rel_src) {
4113 case HAL_WBM_REL_SRC_MODULE_REO:
4114 drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
4115 break;
4116 case HAL_WBM_REL_SRC_MODULE_RXDMA:
4117 drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
4118 break;
4119 default:
4120 /* msdu will get freed */
4121 break;
4122 }
4123
4124 if (drop) {
4125 dev_kfree_skb_any(msdu);
4126 return;
4127 }
4128
4129 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
4130 }
4131
ath11k_dp_rx_process_wbm_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)4132 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
4133 struct napi_struct *napi, int budget)
4134 {
4135 struct ath11k *ar;
4136 struct ath11k_dp *dp = &ab->dp;
4137 struct dp_rxdma_ring *rx_ring;
4138 struct hal_rx_wbm_rel_info err_info;
4139 struct hal_srng *srng;
4140 struct sk_buff *msdu;
4141 struct sk_buff_head msdu_list[MAX_RADIOS];
4142 struct ath11k_skb_rxcb *rxcb;
4143 u32 *rx_desc;
4144 int buf_id, mac_id;
4145 int num_buffs_reaped[MAX_RADIOS] = {};
4146 int total_num_buffs_reaped = 0;
4147 int ret, i;
4148
4149 for (i = 0; i < ab->num_radios; i++)
4150 __skb_queue_head_init(&msdu_list[i]);
4151
4152 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
4153
4154 spin_lock_bh(&srng->lock);
4155
4156 ath11k_hal_srng_access_begin(ab, srng);
4157
4158 while (budget) {
4159 rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
4160 if (!rx_desc)
4161 break;
4162
4163 ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
4164 if (ret) {
4165 ath11k_warn(ab,
4166 "failed to parse rx error in wbm_rel ring desc %d\n",
4167 ret);
4168 continue;
4169 }
4170
4171 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
4172 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
4173
4174 ar = ab->pdevs[mac_id].ar;
4175 rx_ring = &ar->dp.rx_refill_buf_ring;
4176
4177 spin_lock_bh(&rx_ring->idr_lock);
4178 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4179 if (!msdu) {
4180 ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
4181 buf_id, mac_id);
4182 spin_unlock_bh(&rx_ring->idr_lock);
4183 continue;
4184 }
4185
4186 idr_remove(&rx_ring->bufs_idr, buf_id);
4187 spin_unlock_bh(&rx_ring->idr_lock);
4188
4189 rxcb = ATH11K_SKB_RXCB(msdu);
4190 dma_unmap_single(ab->dev, rxcb->paddr,
4191 msdu->len + skb_tailroom(msdu),
4192 DMA_FROM_DEVICE);
4193
4194 num_buffs_reaped[mac_id]++;
4195 total_num_buffs_reaped++;
4196 budget--;
4197
4198 if (err_info.push_reason !=
4199 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4200 dev_kfree_skb_any(msdu);
4201 continue;
4202 }
4203
4204 rxcb->err_rel_src = err_info.err_rel_src;
4205 rxcb->err_code = err_info.err_code;
4206 rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
4207 __skb_queue_tail(&msdu_list[mac_id], msdu);
4208 }
4209
4210 ath11k_hal_srng_access_end(ab, srng);
4211
4212 spin_unlock_bh(&srng->lock);
4213
4214 if (!total_num_buffs_reaped)
4215 goto done;
4216
4217 for (i = 0; i < ab->num_radios; i++) {
4218 if (!num_buffs_reaped[i])
4219 continue;
4220
4221 ar = ab->pdevs[i].ar;
4222 rx_ring = &ar->dp.rx_refill_buf_ring;
4223
4224 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
4225 ab->hw_params.hal_params->rx_buf_rbm);
4226 }
4227
4228 rcu_read_lock();
4229 for (i = 0; i < ab->num_radios; i++) {
4230 if (!rcu_dereference(ab->pdevs_active[i])) {
4231 __skb_queue_purge(&msdu_list[i]);
4232 continue;
4233 }
4234
4235 ar = ab->pdevs[i].ar;
4236
4237 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
4238 __skb_queue_purge(&msdu_list[i]);
4239 continue;
4240 }
4241
4242 while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
4243 ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
4244 }
4245 rcu_read_unlock();
4246 done:
4247 return total_num_buffs_reaped;
4248 }
4249
ath11k_dp_process_rxdma_err(struct ath11k_base * ab,int mac_id,int budget)4250 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
4251 {
4252 struct ath11k *ar;
4253 struct dp_srng *err_ring;
4254 struct dp_rxdma_ring *rx_ring;
4255 struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
4256 struct hal_srng *srng;
4257 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
4258 enum hal_rx_buf_return_buf_manager rbm;
4259 enum hal_reo_entr_rxdma_ecode rxdma_err_code;
4260 struct ath11k_skb_rxcb *rxcb;
4261 struct sk_buff *skb;
4262 struct hal_reo_entrance_ring *entr_ring;
4263 void *desc;
4264 int num_buf_freed = 0;
4265 int quota = budget;
4266 dma_addr_t paddr;
4267 u32 desc_bank;
4268 void *link_desc_va;
4269 int num_msdus;
4270 int i;
4271 int buf_id;
4272
4273 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
4274 err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
4275 mac_id)];
4276 rx_ring = &ar->dp.rx_refill_buf_ring;
4277
4278 srng = &ab->hal.srng_list[err_ring->ring_id];
4279
4280 spin_lock_bh(&srng->lock);
4281
4282 ath11k_hal_srng_access_begin(ab, srng);
4283
4284 while (quota-- &&
4285 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4286 ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
4287
4288 entr_ring = (struct hal_reo_entrance_ring *)desc;
4289 rxdma_err_code =
4290 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4291 entr_ring->info1);
4292 ab->soc_stats.rxdma_error[rxdma_err_code]++;
4293
4294 link_desc_va = link_desc_banks[desc_bank].vaddr +
4295 (paddr - link_desc_banks[desc_bank].paddr);
4296 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
4297 msdu_cookies, &rbm);
4298
4299 for (i = 0; i < num_msdus; i++) {
4300 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4301 msdu_cookies[i]);
4302
4303 spin_lock_bh(&rx_ring->idr_lock);
4304 skb = idr_find(&rx_ring->bufs_idr, buf_id);
4305 if (!skb) {
4306 ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
4307 buf_id);
4308 spin_unlock_bh(&rx_ring->idr_lock);
4309 continue;
4310 }
4311
4312 idr_remove(&rx_ring->bufs_idr, buf_id);
4313 spin_unlock_bh(&rx_ring->idr_lock);
4314
4315 rxcb = ATH11K_SKB_RXCB(skb);
4316 dma_unmap_single(ab->dev, rxcb->paddr,
4317 skb->len + skb_tailroom(skb),
4318 DMA_FROM_DEVICE);
4319 dev_kfree_skb_any(skb);
4320
4321 num_buf_freed++;
4322 }
4323
4324 ath11k_dp_rx_link_desc_return(ab, desc,
4325 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4326 }
4327
4328 ath11k_hal_srng_access_end(ab, srng);
4329
4330 spin_unlock_bh(&srng->lock);
4331
4332 if (num_buf_freed)
4333 ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
4334 ab->hw_params.hal_params->rx_buf_rbm);
4335
4336 return budget - quota;
4337 }
4338
ath11k_dp_process_reo_status(struct ath11k_base * ab)4339 void ath11k_dp_process_reo_status(struct ath11k_base *ab)
4340 {
4341 struct ath11k_dp *dp = &ab->dp;
4342 struct hal_srng *srng;
4343 struct dp_reo_cmd *cmd, *tmp;
4344 bool found = false;
4345 u32 *reo_desc;
4346 u16 tag;
4347 struct hal_reo_status reo_status;
4348
4349 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4350
4351 memset(&reo_status, 0, sizeof(reo_status));
4352
4353 spin_lock_bh(&srng->lock);
4354
4355 ath11k_hal_srng_access_begin(ab, srng);
4356
4357 while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4358 tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
4359
4360 switch (tag) {
4361 case HAL_REO_GET_QUEUE_STATS_STATUS:
4362 ath11k_hal_reo_status_queue_stats(ab, reo_desc,
4363 &reo_status);
4364 break;
4365 case HAL_REO_FLUSH_QUEUE_STATUS:
4366 ath11k_hal_reo_flush_queue_status(ab, reo_desc,
4367 &reo_status);
4368 break;
4369 case HAL_REO_FLUSH_CACHE_STATUS:
4370 ath11k_hal_reo_flush_cache_status(ab, reo_desc,
4371 &reo_status);
4372 break;
4373 case HAL_REO_UNBLOCK_CACHE_STATUS:
4374 ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
4375 &reo_status);
4376 break;
4377 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4378 ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
4379 &reo_status);
4380 break;
4381 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4382 ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
4383 &reo_status);
4384 break;
4385 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4386 ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
4387 &reo_status);
4388 break;
4389 default:
4390 ath11k_warn(ab, "Unknown reo status type %d\n", tag);
4391 continue;
4392 }
4393
4394 spin_lock_bh(&dp->reo_cmd_lock);
4395 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4396 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4397 found = true;
4398 list_del(&cmd->list);
4399 break;
4400 }
4401 }
4402 spin_unlock_bh(&dp->reo_cmd_lock);
4403
4404 if (found) {
4405 cmd->handler(dp, (void *)&cmd->data,
4406 reo_status.uniform_hdr.cmd_status);
4407 kfree(cmd);
4408 }
4409
4410 found = false;
4411 }
4412
4413 ath11k_hal_srng_access_end(ab, srng);
4414
4415 spin_unlock_bh(&srng->lock);
4416 }
4417
ath11k_dp_rx_pdev_free(struct ath11k_base * ab,int mac_id)4418 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
4419 {
4420 struct ath11k *ar = ab->pdevs[mac_id].ar;
4421
4422 ath11k_dp_rx_pdev_srng_free(ar);
4423 ath11k_dp_rxdma_pdev_buf_free(ar);
4424 }
4425
ath11k_dp_rx_pdev_alloc(struct ath11k_base * ab,int mac_id)4426 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
4427 {
4428 struct ath11k *ar = ab->pdevs[mac_id].ar;
4429 struct ath11k_pdev_dp *dp = &ar->dp;
4430 u32 ring_id;
4431 int i;
4432 int ret;
4433
4434 ret = ath11k_dp_rx_pdev_srng_alloc(ar);
4435 if (ret) {
4436 ath11k_warn(ab, "failed to setup rx srngs\n");
4437 return ret;
4438 }
4439
4440 ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
4441 if (ret) {
4442 ath11k_warn(ab, "failed to setup rxdma ring\n");
4443 return ret;
4444 }
4445
4446 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4447 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
4448 if (ret) {
4449 ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4450 ret);
4451 return ret;
4452 }
4453
4454 if (ab->hw_params.rx_mac_buf_ring) {
4455 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4456 ring_id = dp->rx_mac_buf_ring[i].ring_id;
4457 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4458 mac_id + i, HAL_RXDMA_BUF);
4459 if (ret) {
4460 ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4461 i, ret);
4462 return ret;
4463 }
4464 }
4465 }
4466
4467 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4468 ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4469 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4470 mac_id + i, HAL_RXDMA_DST);
4471 if (ret) {
4472 ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4473 i, ret);
4474 return ret;
4475 }
4476 }
4477
4478 if (!ab->hw_params.rxdma1_enable)
4479 goto config_refill_ring;
4480
4481 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4482 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4483 mac_id, HAL_RXDMA_MONITOR_BUF);
4484 if (ret) {
4485 ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4486 ret);
4487 return ret;
4488 }
4489 ret = ath11k_dp_tx_htt_srng_setup(ab,
4490 dp->rxdma_mon_dst_ring.ring_id,
4491 mac_id, HAL_RXDMA_MONITOR_DST);
4492 if (ret) {
4493 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4494 ret);
4495 return ret;
4496 }
4497 ret = ath11k_dp_tx_htt_srng_setup(ab,
4498 dp->rxdma_mon_desc_ring.ring_id,
4499 mac_id, HAL_RXDMA_MONITOR_DESC);
4500 if (ret) {
4501 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4502 ret);
4503 return ret;
4504 }
4505
4506 config_refill_ring:
4507 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4508 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
4509 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
4510 HAL_RXDMA_MONITOR_STATUS);
4511 if (ret) {
4512 ath11k_warn(ab,
4513 "failed to configure mon_status_refill_ring%d %d\n",
4514 i, ret);
4515 return ret;
4516 }
4517 }
4518
4519 return 0;
4520 }
4521
ath11k_dp_mon_set_frag_len(u32 * total_len,u32 * frag_len)4522 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
4523 {
4524 if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
4525 *frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
4526 *total_len -= *frag_len;
4527 } else {
4528 *frag_len = *total_len;
4529 *total_len = 0;
4530 }
4531 }
4532
4533 static
ath11k_dp_rx_monitor_link_desc_return(struct ath11k * ar,void * p_last_buf_addr_info,u8 mac_id)4534 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
4535 void *p_last_buf_addr_info,
4536 u8 mac_id)
4537 {
4538 struct ath11k_pdev_dp *dp = &ar->dp;
4539 struct dp_srng *dp_srng;
4540 void *hal_srng;
4541 void *src_srng_desc;
4542 int ret = 0;
4543
4544 if (ar->ab->hw_params.rxdma1_enable) {
4545 dp_srng = &dp->rxdma_mon_desc_ring;
4546 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4547 } else {
4548 dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
4549 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4550 }
4551
4552 ath11k_hal_srng_access_begin(ar->ab, hal_srng);
4553
4554 src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
4555
4556 if (src_srng_desc) {
4557 struct ath11k_buffer_addr *src_desc = src_srng_desc;
4558
4559 *src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
4560 } else {
4561 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4562 "Monitor Link Desc Ring %d Full", mac_id);
4563 ret = -ENOMEM;
4564 }
4565
4566 ath11k_hal_srng_access_end(ar->ab, hal_srng);
4567 return ret;
4568 }
4569
4570 static
ath11k_dp_rx_mon_next_link_desc_get(void * rx_msdu_link_desc,dma_addr_t * paddr,u32 * sw_cookie,u8 * rbm,void ** pp_buf_addr_info)4571 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
4572 dma_addr_t *paddr, u32 *sw_cookie,
4573 u8 *rbm,
4574 void **pp_buf_addr_info)
4575 {
4576 struct hal_rx_msdu_link *msdu_link = rx_msdu_link_desc;
4577 struct ath11k_buffer_addr *buf_addr_info;
4578
4579 buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
4580
4581 ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
4582
4583 *pp_buf_addr_info = (void *)buf_addr_info;
4584 }
4585
ath11k_dp_pkt_set_pktlen(struct sk_buff * skb,u32 len)4586 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
4587 {
4588 if (skb->len > len) {
4589 skb_trim(skb, len);
4590 } else {
4591 if (skb_tailroom(skb) < len - skb->len) {
4592 if ((pskb_expand_head(skb, 0,
4593 len - skb->len - skb_tailroom(skb),
4594 GFP_ATOMIC))) {
4595 dev_kfree_skb_any(skb);
4596 return -ENOMEM;
4597 }
4598 }
4599 skb_put(skb, (len - skb->len));
4600 }
4601 return 0;
4602 }
4603
ath11k_hal_rx_msdu_list_get(struct ath11k * ar,void * msdu_link_desc,struct hal_rx_msdu_list * msdu_list,u16 * num_msdus)4604 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
4605 void *msdu_link_desc,
4606 struct hal_rx_msdu_list *msdu_list,
4607 u16 *num_msdus)
4608 {
4609 struct hal_rx_msdu_details *msdu_details = NULL;
4610 struct rx_msdu_desc *msdu_desc_info = NULL;
4611 struct hal_rx_msdu_link *msdu_link = NULL;
4612 int i;
4613 u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
4614 u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
4615 u8 tmp = 0;
4616
4617 msdu_link = msdu_link_desc;
4618 msdu_details = &msdu_link->msdu_link[0];
4619
4620 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
4621 if (!i && FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4622 msdu_details[i].buf_addr_info.info0) == 0)
4623 break;
4624 if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4625 msdu_details[i].buf_addr_info.info0) == 0) {
4626 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
4627 msdu_desc_info->info0 |= last;
4628 break;
4629 }
4630 msdu_desc_info = &msdu_details[i].rx_msdu_info;
4631
4632 if (!i)
4633 msdu_desc_info->info0 |= first;
4634 else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
4635 msdu_desc_info->info0 |= last;
4636 msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
4637 msdu_list->msdu_info[i].msdu_len =
4638 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
4639 msdu_list->sw_cookie[i] =
4640 FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
4641 msdu_details[i].buf_addr_info.info1);
4642 tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
4643 msdu_details[i].buf_addr_info.info1);
4644 msdu_list->rbm[i] = tmp;
4645 }
4646 *num_msdus = i;
4647 }
4648
ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id,u32 * ppdu_id,u32 * rx_bufs_used)4649 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
4650 u32 *rx_bufs_used)
4651 {
4652 u32 ret = 0;
4653
4654 if ((*ppdu_id < msdu_ppdu_id) &&
4655 ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
4656 *ppdu_id = msdu_ppdu_id;
4657 ret = msdu_ppdu_id;
4658 } else if ((*ppdu_id > msdu_ppdu_id) &&
4659 ((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
4660 /* mon_dst is behind than mon_status
4661 * skip dst_ring and free it
4662 */
4663 *rx_bufs_used += 1;
4664 *ppdu_id = msdu_ppdu_id;
4665 ret = msdu_ppdu_id;
4666 }
4667 return ret;
4668 }
4669
ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info * info,bool * is_frag,u32 * total_len,u32 * frag_len,u32 * msdu_cnt)4670 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
4671 bool *is_frag, u32 *total_len,
4672 u32 *frag_len, u32 *msdu_cnt)
4673 {
4674 if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
4675 if (!*is_frag) {
4676 *total_len = info->msdu_len;
4677 *is_frag = true;
4678 }
4679 ath11k_dp_mon_set_frag_len(total_len,
4680 frag_len);
4681 } else {
4682 if (*is_frag) {
4683 ath11k_dp_mon_set_frag_len(total_len,
4684 frag_len);
4685 } else {
4686 *frag_len = info->msdu_len;
4687 }
4688 *is_frag = false;
4689 *msdu_cnt -= 1;
4690 }
4691 }
4692
4693 /* clang stack usage explodes if this is inlined */
4694 static noinline_for_stack
ath11k_dp_rx_mon_mpdu_pop(struct ath11k * ar,int mac_id,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,u32 * npackets,u32 * ppdu_id)4695 u32 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
4696 void *ring_entry, struct sk_buff **head_msdu,
4697 struct sk_buff **tail_msdu, u32 *npackets,
4698 u32 *ppdu_id)
4699 {
4700 struct ath11k_pdev_dp *dp = &ar->dp;
4701 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4702 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
4703 struct sk_buff *msdu = NULL, *last = NULL;
4704 struct hal_rx_msdu_list msdu_list;
4705 void *p_buf_addr_info, *p_last_buf_addr_info;
4706 struct hal_rx_desc *rx_desc;
4707 void *rx_msdu_link_desc;
4708 dma_addr_t paddr;
4709 u16 num_msdus = 0;
4710 u32 rx_buf_size, rx_pkt_offset, sw_cookie;
4711 u32 rx_bufs_used = 0, i = 0;
4712 u32 msdu_ppdu_id = 0, msdu_cnt = 0;
4713 u32 total_len = 0, frag_len = 0;
4714 bool is_frag, is_first_msdu;
4715 bool drop_mpdu = false;
4716 struct ath11k_skb_rxcb *rxcb;
4717 struct hal_reo_entrance_ring *ent_desc = ring_entry;
4718 int buf_id;
4719 u32 rx_link_buf_info[2];
4720 u8 rbm;
4721
4722 if (!ar->ab->hw_params.rxdma1_enable)
4723 rx_ring = &dp->rx_refill_buf_ring;
4724
4725 ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
4726 &sw_cookie,
4727 &p_last_buf_addr_info, &rbm,
4728 &msdu_cnt);
4729
4730 if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
4731 ent_desc->info1) ==
4732 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4733 u8 rxdma_err =
4734 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4735 ent_desc->info1);
4736 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
4737 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
4738 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
4739 drop_mpdu = true;
4740 pmon->rx_mon_stats.dest_mpdu_drop++;
4741 }
4742 }
4743
4744 is_frag = false;
4745 is_first_msdu = true;
4746
4747 do {
4748 if (pmon->mon_last_linkdesc_paddr == paddr) {
4749 pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
4750 return rx_bufs_used;
4751 }
4752
4753 if (ar->ab->hw_params.rxdma1_enable)
4754 rx_msdu_link_desc =
4755 (void *)pmon->link_desc_banks[sw_cookie].vaddr +
4756 (paddr - pmon->link_desc_banks[sw_cookie].paddr);
4757 else
4758 rx_msdu_link_desc =
4759 (void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4760 (paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
4761
4762 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
4763 &num_msdus);
4764
4765 for (i = 0; i < num_msdus; i++) {
4766 u32 l2_hdr_offset;
4767
4768 if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
4769 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4770 "i %d last_cookie %d is same\n",
4771 i, pmon->mon_last_buf_cookie);
4772 drop_mpdu = true;
4773 pmon->rx_mon_stats.dup_mon_buf_cnt++;
4774 continue;
4775 }
4776 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4777 msdu_list.sw_cookie[i]);
4778
4779 spin_lock_bh(&rx_ring->idr_lock);
4780 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4781 spin_unlock_bh(&rx_ring->idr_lock);
4782 if (!msdu) {
4783 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4784 "msdu_pop: invalid buf_id %d\n", buf_id);
4785 goto next_msdu;
4786 }
4787 rxcb = ATH11K_SKB_RXCB(msdu);
4788 if (!rxcb->unmapped) {
4789 dma_unmap_single(ar->ab->dev, rxcb->paddr,
4790 msdu->len +
4791 skb_tailroom(msdu),
4792 DMA_FROM_DEVICE);
4793 rxcb->unmapped = 1;
4794 }
4795 if (drop_mpdu) {
4796 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4797 "i %d drop msdu %p *ppdu_id %x\n",
4798 i, msdu, *ppdu_id);
4799 dev_kfree_skb_any(msdu);
4800 msdu = NULL;
4801 goto next_msdu;
4802 }
4803
4804 rx_desc = (struct hal_rx_desc *)msdu->data;
4805
4806 rx_pkt_offset = sizeof(struct hal_rx_desc);
4807 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
4808
4809 if (is_first_msdu) {
4810 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
4811 drop_mpdu = true;
4812 dev_kfree_skb_any(msdu);
4813 msdu = NULL;
4814 pmon->mon_last_linkdesc_paddr = paddr;
4815 goto next_msdu;
4816 }
4817
4818 msdu_ppdu_id =
4819 ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc);
4820
4821 if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
4822 ppdu_id,
4823 &rx_bufs_used)) {
4824 if (rx_bufs_used) {
4825 drop_mpdu = true;
4826 dev_kfree_skb_any(msdu);
4827 msdu = NULL;
4828 goto next_msdu;
4829 }
4830 return rx_bufs_used;
4831 }
4832 pmon->mon_last_linkdesc_paddr = paddr;
4833 is_first_msdu = false;
4834 }
4835 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
4836 &is_frag, &total_len,
4837 &frag_len, &msdu_cnt);
4838 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
4839
4840 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
4841
4842 if (!(*head_msdu))
4843 *head_msdu = msdu;
4844 else if (last)
4845 last->next = msdu;
4846
4847 last = msdu;
4848 next_msdu:
4849 pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
4850 rx_bufs_used++;
4851 spin_lock_bh(&rx_ring->idr_lock);
4852 idr_remove(&rx_ring->bufs_idr, buf_id);
4853 spin_unlock_bh(&rx_ring->idr_lock);
4854 }
4855
4856 ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
4857
4858 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
4859 &sw_cookie, &rbm,
4860 &p_buf_addr_info);
4861
4862 if (ar->ab->hw_params.rxdma1_enable) {
4863 if (ath11k_dp_rx_monitor_link_desc_return(ar,
4864 p_last_buf_addr_info,
4865 dp->mac_id))
4866 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4867 "dp_rx_monitor_link_desc_return failed");
4868 } else {
4869 ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
4870 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4871 }
4872
4873 p_last_buf_addr_info = p_buf_addr_info;
4874
4875 } while (paddr && msdu_cnt);
4876
4877 if (last)
4878 last->next = NULL;
4879
4880 *tail_msdu = msdu;
4881
4882 if (msdu_cnt == 0)
4883 *npackets = 1;
4884
4885 return rx_bufs_used;
4886 }
4887
ath11k_dp_rx_msdus_set_payload(struct ath11k * ar,struct sk_buff * msdu)4888 static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu)
4889 {
4890 u32 rx_pkt_offset, l2_hdr_offset;
4891
4892 rx_pkt_offset = ar->ab->hw_params.hal_desc_sz;
4893 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab,
4894 (struct hal_rx_desc *)msdu->data);
4895 skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
4896 }
4897
4898 static struct sk_buff *
ath11k_dp_rx_mon_merg_msdus(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * last_msdu,struct ieee80211_rx_status * rxs,bool * fcs_err)4899 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
4900 u32 mac_id, struct sk_buff *head_msdu,
4901 struct sk_buff *last_msdu,
4902 struct ieee80211_rx_status *rxs, bool *fcs_err)
4903 {
4904 struct ath11k_base *ab = ar->ab;
4905 struct sk_buff *msdu, *prev_buf;
4906 struct hal_rx_desc *rx_desc;
4907 char *hdr_desc;
4908 u8 *dest, decap_format;
4909 struct ieee80211_hdr_3addr *wh;
4910 struct rx_attention *rx_attention;
4911 u32 err_bitmap;
4912
4913 if (!head_msdu)
4914 goto err_merge_fail;
4915
4916 rx_desc = (struct hal_rx_desc *)head_msdu->data;
4917 rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc);
4918 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
4919
4920 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
4921 *fcs_err = true;
4922
4923 if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention))
4924 return NULL;
4925
4926 decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc);
4927
4928 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
4929
4930 if (decap_format == DP_RX_DECAP_TYPE_RAW) {
4931 ath11k_dp_rx_msdus_set_payload(ar, head_msdu);
4932
4933 prev_buf = head_msdu;
4934 msdu = head_msdu->next;
4935
4936 while (msdu) {
4937 ath11k_dp_rx_msdus_set_payload(ar, msdu);
4938
4939 prev_buf = msdu;
4940 msdu = msdu->next;
4941 }
4942
4943 prev_buf->next = NULL;
4944
4945 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
4946 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
4947 u8 qos_pkt = 0;
4948
4949 rx_desc = (struct hal_rx_desc *)head_msdu->data;
4950 hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
4951
4952 /* Base size */
4953 wh = (struct ieee80211_hdr_3addr *)hdr_desc;
4954
4955 if (ieee80211_is_data_qos(wh->frame_control))
4956 qos_pkt = 1;
4957
4958 msdu = head_msdu;
4959
4960 while (msdu) {
4961 ath11k_dp_rx_msdus_set_payload(ar, msdu);
4962 if (qos_pkt) {
4963 dest = skb_push(msdu, sizeof(__le16));
4964 if (!dest)
4965 goto err_merge_fail;
4966 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr));
4967 }
4968 prev_buf = msdu;
4969 msdu = msdu->next;
4970 }
4971 dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
4972 if (!dest)
4973 goto err_merge_fail;
4974
4975 ath11k_dbg(ab, ATH11K_DBG_DATA,
4976 "mpdu_buf %p mpdu_buf->len %u",
4977 prev_buf, prev_buf->len);
4978 } else {
4979 ath11k_dbg(ab, ATH11K_DBG_DATA,
4980 "decap format %d is not supported!\n",
4981 decap_format);
4982 goto err_merge_fail;
4983 }
4984
4985 return head_msdu;
4986
4987 err_merge_fail:
4988 return NULL;
4989 }
4990
4991 static void
ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)4992 ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status,
4993 u8 *rtap_buf)
4994 {
4995 u32 rtap_len = 0;
4996
4997 put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]);
4998 rtap_len += 2;
4999
5000 put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]);
5001 rtap_len += 2;
5002
5003 put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]);
5004 rtap_len += 2;
5005
5006 put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]);
5007 rtap_len += 2;
5008
5009 put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]);
5010 rtap_len += 2;
5011
5012 put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]);
5013 }
5014
5015 static void
ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)5016 ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status,
5017 u8 *rtap_buf)
5018 {
5019 u32 rtap_len = 0;
5020
5021 put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]);
5022 rtap_len += 2;
5023
5024 put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]);
5025 rtap_len += 2;
5026
5027 rtap_buf[rtap_len] = rx_status->he_RU[0];
5028 rtap_len += 1;
5029
5030 rtap_buf[rtap_len] = rx_status->he_RU[1];
5031 rtap_len += 1;
5032
5033 rtap_buf[rtap_len] = rx_status->he_RU[2];
5034 rtap_len += 1;
5035
5036 rtap_buf[rtap_len] = rx_status->he_RU[3];
5037 }
5038
ath11k_update_radiotap(struct ath11k * ar,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * mon_skb,struct ieee80211_rx_status * rxs)5039 static void ath11k_update_radiotap(struct ath11k *ar,
5040 struct hal_rx_mon_ppdu_info *ppduinfo,
5041 struct sk_buff *mon_skb,
5042 struct ieee80211_rx_status *rxs)
5043 {
5044 struct ieee80211_supported_band *sband;
5045 u8 *ptr = NULL;
5046
5047 rxs->flag |= RX_FLAG_MACTIME_START;
5048 rxs->signal = ppduinfo->rssi_comb + ATH11K_DEFAULT_NOISE_FLOOR;
5049
5050 if (ppduinfo->nss)
5051 rxs->nss = ppduinfo->nss;
5052
5053 if (ppduinfo->he_mu_flags) {
5054 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU;
5055 rxs->encoding = RX_ENC_HE;
5056 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu));
5057 ath11k_dp_rx_update_radiotap_he_mu(ppduinfo, ptr);
5058 } else if (ppduinfo->he_flags) {
5059 rxs->flag |= RX_FLAG_RADIOTAP_HE;
5060 rxs->encoding = RX_ENC_HE;
5061 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he));
5062 ath11k_dp_rx_update_radiotap_he(ppduinfo, ptr);
5063 rxs->rate_idx = ppduinfo->rate;
5064 } else if (ppduinfo->vht_flags) {
5065 rxs->encoding = RX_ENC_VHT;
5066 rxs->rate_idx = ppduinfo->rate;
5067 } else if (ppduinfo->ht_flags) {
5068 rxs->encoding = RX_ENC_HT;
5069 rxs->rate_idx = ppduinfo->rate;
5070 } else {
5071 rxs->encoding = RX_ENC_LEGACY;
5072 sband = &ar->mac.sbands[rxs->band];
5073 rxs->rate_idx = ath11k_mac_hw_rate_to_idx(sband, ppduinfo->rate,
5074 ppduinfo->cck_flag);
5075 }
5076
5077 rxs->mactime = ppduinfo->tsft;
5078 }
5079
ath11k_dp_rx_mon_deliver(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * tail_msdu,struct napi_struct * napi)5080 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
5081 struct sk_buff *head_msdu,
5082 struct hal_rx_mon_ppdu_info *ppduinfo,
5083 struct sk_buff *tail_msdu,
5084 struct napi_struct *napi)
5085 {
5086 struct ath11k_pdev_dp *dp = &ar->dp;
5087 struct sk_buff *mon_skb, *skb_next, *header;
5088 struct ieee80211_rx_status *rxs = &dp->rx_status;
5089 bool fcs_err = false;
5090
5091 mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
5092 tail_msdu, rxs, &fcs_err);
5093
5094 if (!mon_skb)
5095 goto mon_deliver_fail;
5096
5097 header = mon_skb;
5098
5099 rxs->flag = 0;
5100
5101 if (fcs_err)
5102 rxs->flag = RX_FLAG_FAILED_FCS_CRC;
5103
5104 do {
5105 skb_next = mon_skb->next;
5106 if (!skb_next)
5107 rxs->flag &= ~RX_FLAG_AMSDU_MORE;
5108 else
5109 rxs->flag |= RX_FLAG_AMSDU_MORE;
5110
5111 if (mon_skb == header) {
5112 header = NULL;
5113 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
5114 } else {
5115 rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
5116 }
5117 rxs->flag |= RX_FLAG_ONLY_MONITOR;
5118 ath11k_update_radiotap(ar, ppduinfo, mon_skb, rxs);
5119
5120 ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs);
5121 mon_skb = skb_next;
5122 } while (mon_skb);
5123 rxs->flag = 0;
5124
5125 return 0;
5126
5127 mon_deliver_fail:
5128 mon_skb = head_msdu;
5129 while (mon_skb) {
5130 skb_next = mon_skb->next;
5131 dev_kfree_skb_any(mon_skb);
5132 mon_skb = skb_next;
5133 }
5134 return -EINVAL;
5135 }
5136
5137 /* The destination ring processing is stuck if the destination is not
5138 * moving while status ring moves 16 PPDU. The destination ring processing
5139 * skips this destination ring PPDU as a workaround.
5140 */
5141 #define MON_DEST_RING_STUCK_MAX_CNT 16
5142
ath11k_dp_rx_mon_dest_process(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)5143 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
5144 u32 quota, struct napi_struct *napi)
5145 {
5146 struct ath11k_pdev_dp *dp = &ar->dp;
5147 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5148 const struct ath11k_hw_hal_params *hal_params;
5149 void *ring_entry;
5150 struct hal_srng *mon_dst_srng;
5151 u32 ppdu_id;
5152 u32 rx_bufs_used;
5153 u32 ring_id;
5154 struct ath11k_pdev_mon_stats *rx_mon_stats;
5155 u32 npackets = 0;
5156 u32 mpdu_rx_bufs_used;
5157
5158 if (ar->ab->hw_params.rxdma1_enable)
5159 ring_id = dp->rxdma_mon_dst_ring.ring_id;
5160 else
5161 ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
5162
5163 mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
5164
5165 spin_lock_bh(&pmon->mon_lock);
5166
5167 spin_lock_bh(&mon_dst_srng->lock);
5168 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5169
5170 ppdu_id = pmon->mon_ppdu_info.ppdu_id;
5171 rx_bufs_used = 0;
5172 rx_mon_stats = &pmon->rx_mon_stats;
5173
5174 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5175 struct sk_buff *head_msdu, *tail_msdu;
5176
5177 head_msdu = NULL;
5178 tail_msdu = NULL;
5179
5180 mpdu_rx_bufs_used = ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
5181 &head_msdu,
5182 &tail_msdu,
5183 &npackets, &ppdu_id);
5184
5185 rx_bufs_used += mpdu_rx_bufs_used;
5186
5187 if (mpdu_rx_bufs_used) {
5188 dp->mon_dest_ring_stuck_cnt = 0;
5189 } else {
5190 dp->mon_dest_ring_stuck_cnt++;
5191 rx_mon_stats->dest_mon_not_reaped++;
5192 }
5193
5194 if (dp->mon_dest_ring_stuck_cnt > MON_DEST_RING_STUCK_MAX_CNT) {
5195 rx_mon_stats->dest_mon_stuck++;
5196 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5197 "status ring ppdu_id=%d dest ring ppdu_id=%d mon_dest_ring_stuck_cnt=%d dest_mon_not_reaped=%u dest_mon_stuck=%u\n",
5198 pmon->mon_ppdu_info.ppdu_id, ppdu_id,
5199 dp->mon_dest_ring_stuck_cnt,
5200 rx_mon_stats->dest_mon_not_reaped,
5201 rx_mon_stats->dest_mon_stuck);
5202 pmon->mon_ppdu_info.ppdu_id = ppdu_id;
5203 continue;
5204 }
5205
5206 if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
5207 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5208 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5209 "dest_rx: new ppdu_id %x != status ppdu_id %x dest_mon_not_reaped = %u dest_mon_stuck = %u\n",
5210 ppdu_id, pmon->mon_ppdu_info.ppdu_id,
5211 rx_mon_stats->dest_mon_not_reaped,
5212 rx_mon_stats->dest_mon_stuck);
5213 break;
5214 }
5215 if (head_msdu && tail_msdu) {
5216 ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
5217 &pmon->mon_ppdu_info,
5218 tail_msdu, napi);
5219 rx_mon_stats->dest_mpdu_done++;
5220 }
5221
5222 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5223 mon_dst_srng);
5224 }
5225 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5226 spin_unlock_bh(&mon_dst_srng->lock);
5227
5228 spin_unlock_bh(&pmon->mon_lock);
5229
5230 if (rx_bufs_used) {
5231 rx_mon_stats->dest_ppdu_done++;
5232 hal_params = ar->ab->hw_params.hal_params;
5233
5234 if (ar->ab->hw_params.rxdma1_enable)
5235 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5236 &dp->rxdma_mon_buf_ring,
5237 rx_bufs_used,
5238 hal_params->rx_buf_rbm);
5239 else
5240 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5241 &dp->rx_refill_buf_ring,
5242 rx_bufs_used,
5243 hal_params->rx_buf_rbm);
5244 }
5245 }
5246
ath11k_dp_rx_process_mon_status(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5247 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
5248 struct napi_struct *napi, int budget)
5249 {
5250 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5251 enum hal_rx_mon_status hal_status;
5252 struct sk_buff *skb;
5253 struct sk_buff_head skb_list;
5254 struct ath11k_peer *peer;
5255 struct ath11k_sta *arsta;
5256 int num_buffs_reaped = 0;
5257 u32 rx_buf_sz;
5258 u16 log_type;
5259 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&ar->dp.mon_data;
5260 struct ath11k_pdev_mon_stats *rx_mon_stats = &pmon->rx_mon_stats;
5261 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
5262
5263 __skb_queue_head_init(&skb_list);
5264
5265 num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
5266 &skb_list);
5267 if (!num_buffs_reaped)
5268 goto exit;
5269
5270 memset(ppdu_info, 0, sizeof(*ppdu_info));
5271 ppdu_info->peer_id = HAL_INVALID_PEERID;
5272
5273 while ((skb = __skb_dequeue(&skb_list))) {
5274 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) {
5275 log_type = ATH11K_PKTLOG_TYPE_LITE_RX;
5276 rx_buf_sz = DP_RX_BUFFER_SIZE_LITE;
5277 } else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) {
5278 log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF;
5279 rx_buf_sz = DP_RX_BUFFER_SIZE;
5280 } else {
5281 log_type = ATH11K_PKTLOG_TYPE_INVALID;
5282 rx_buf_sz = 0;
5283 }
5284
5285 if (log_type != ATH11K_PKTLOG_TYPE_INVALID)
5286 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5287
5288 memset(ppdu_info, 0, sizeof(*ppdu_info));
5289 ppdu_info->peer_id = HAL_INVALID_PEERID;
5290 hal_status = ath11k_hal_rx_parse_mon_status(ab, ppdu_info, skb);
5291
5292 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5293 pmon->mon_ppdu_status == DP_PPDU_STATUS_START &&
5294 hal_status == HAL_TLV_STATUS_PPDU_DONE) {
5295 rx_mon_stats->status_ppdu_done++;
5296 pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
5297 if (!ab->hw_params.full_monitor_mode) {
5298 ath11k_dp_rx_mon_dest_process(ar, mac_id,
5299 budget, napi);
5300 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5301 }
5302 }
5303
5304 if (ppdu_info->peer_id == HAL_INVALID_PEERID ||
5305 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
5306 dev_kfree_skb_any(skb);
5307 continue;
5308 }
5309
5310 rcu_read_lock();
5311 spin_lock_bh(&ab->base_lock);
5312 peer = ath11k_peer_find_by_id(ab, ppdu_info->peer_id);
5313
5314 if (!peer || !peer->sta) {
5315 ath11k_dbg(ab, ATH11K_DBG_DATA,
5316 "failed to find the peer with peer_id %d\n",
5317 ppdu_info->peer_id);
5318 goto next_skb;
5319 }
5320
5321 arsta = ath11k_sta_to_arsta(peer->sta);
5322 ath11k_dp_rx_update_peer_stats(arsta, ppdu_info);
5323
5324 if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
5325 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5326
5327 next_skb:
5328 spin_unlock_bh(&ab->base_lock);
5329 rcu_read_unlock();
5330
5331 dev_kfree_skb_any(skb);
5332 memset(ppdu_info, 0, sizeof(*ppdu_info));
5333 ppdu_info->peer_id = HAL_INVALID_PEERID;
5334 }
5335 exit:
5336 return num_buffs_reaped;
5337 }
5338
5339 static u32
ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k * ar,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,struct hal_sw_mon_ring_entries * sw_mon_entries)5340 ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k *ar,
5341 void *ring_entry, struct sk_buff **head_msdu,
5342 struct sk_buff **tail_msdu,
5343 struct hal_sw_mon_ring_entries *sw_mon_entries)
5344 {
5345 struct ath11k_pdev_dp *dp = &ar->dp;
5346 struct ath11k_mon_data *pmon = &dp->mon_data;
5347 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
5348 struct sk_buff *msdu = NULL, *last = NULL;
5349 struct hal_sw_monitor_ring *sw_desc = ring_entry;
5350 struct hal_rx_msdu_list msdu_list;
5351 struct hal_rx_desc *rx_desc;
5352 struct ath11k_skb_rxcb *rxcb;
5353 void *rx_msdu_link_desc;
5354 void *p_buf_addr_info, *p_last_buf_addr_info;
5355 int buf_id, i = 0;
5356 u32 rx_buf_size, rx_pkt_offset, l2_hdr_offset;
5357 u32 rx_bufs_used = 0, msdu_cnt = 0;
5358 u32 total_len = 0, frag_len = 0, sw_cookie;
5359 u16 num_msdus = 0;
5360 u8 rxdma_err, rbm;
5361 bool is_frag, is_first_msdu;
5362 bool drop_mpdu = false;
5363
5364 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(ring_entry, sw_mon_entries);
5365
5366 sw_cookie = sw_mon_entries->mon_dst_sw_cookie;
5367 sw_mon_entries->end_of_ppdu = false;
5368 sw_mon_entries->drop_ppdu = false;
5369 p_last_buf_addr_info = sw_mon_entries->dst_buf_addr_info;
5370 msdu_cnt = sw_mon_entries->msdu_cnt;
5371
5372 sw_mon_entries->end_of_ppdu =
5373 FIELD_GET(HAL_SW_MON_RING_INFO0_END_OF_PPDU, sw_desc->info0);
5374 if (sw_mon_entries->end_of_ppdu)
5375 return rx_bufs_used;
5376
5377 if (FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON,
5378 sw_desc->info0) ==
5379 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
5380 rxdma_err =
5381 FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE,
5382 sw_desc->info0);
5383 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
5384 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
5385 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
5386 pmon->rx_mon_stats.dest_mpdu_drop++;
5387 drop_mpdu = true;
5388 }
5389 }
5390
5391 is_frag = false;
5392 is_first_msdu = true;
5393
5394 do {
5395 rx_msdu_link_desc =
5396 (u8 *)pmon->link_desc_banks[sw_cookie].vaddr +
5397 (sw_mon_entries->mon_dst_paddr -
5398 pmon->link_desc_banks[sw_cookie].paddr);
5399
5400 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
5401 &num_msdus);
5402
5403 for (i = 0; i < num_msdus; i++) {
5404 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
5405 msdu_list.sw_cookie[i]);
5406
5407 spin_lock_bh(&rx_ring->idr_lock);
5408 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
5409 if (!msdu) {
5410 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5411 "full mon msdu_pop: invalid buf_id %d\n",
5412 buf_id);
5413 spin_unlock_bh(&rx_ring->idr_lock);
5414 goto next_msdu;
5415 }
5416 idr_remove(&rx_ring->bufs_idr, buf_id);
5417 spin_unlock_bh(&rx_ring->idr_lock);
5418
5419 rxcb = ATH11K_SKB_RXCB(msdu);
5420 if (!rxcb->unmapped) {
5421 dma_unmap_single(ar->ab->dev, rxcb->paddr,
5422 msdu->len +
5423 skb_tailroom(msdu),
5424 DMA_FROM_DEVICE);
5425 rxcb->unmapped = 1;
5426 }
5427 if (drop_mpdu) {
5428 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5429 "full mon: i %d drop msdu %p *ppdu_id %x\n",
5430 i, msdu, sw_mon_entries->ppdu_id);
5431 dev_kfree_skb_any(msdu);
5432 msdu_cnt--;
5433 goto next_msdu;
5434 }
5435
5436 rx_desc = (struct hal_rx_desc *)msdu->data;
5437
5438 rx_pkt_offset = sizeof(struct hal_rx_desc);
5439 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
5440
5441 if (is_first_msdu) {
5442 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
5443 drop_mpdu = true;
5444 dev_kfree_skb_any(msdu);
5445 msdu = NULL;
5446 goto next_msdu;
5447 }
5448 is_first_msdu = false;
5449 }
5450
5451 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
5452 &is_frag, &total_len,
5453 &frag_len, &msdu_cnt);
5454
5455 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
5456
5457 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
5458
5459 if (!(*head_msdu))
5460 *head_msdu = msdu;
5461 else if (last)
5462 last->next = msdu;
5463
5464 last = msdu;
5465 next_msdu:
5466 rx_bufs_used++;
5467 }
5468
5469 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc,
5470 &sw_mon_entries->mon_dst_paddr,
5471 &sw_mon_entries->mon_dst_sw_cookie,
5472 &rbm,
5473 &p_buf_addr_info);
5474
5475 if (ath11k_dp_rx_monitor_link_desc_return(ar,
5476 p_last_buf_addr_info,
5477 dp->mac_id))
5478 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5479 "full mon: dp_rx_monitor_link_desc_return failed\n");
5480
5481 p_last_buf_addr_info = p_buf_addr_info;
5482
5483 } while (sw_mon_entries->mon_dst_paddr && msdu_cnt);
5484
5485 if (last)
5486 last->next = NULL;
5487
5488 *tail_msdu = msdu;
5489
5490 return rx_bufs_used;
5491 }
5492
ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu,struct sk_buff * head,struct sk_buff * tail)5493 static int ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp *dp,
5494 struct dp_full_mon_mpdu *mon_mpdu,
5495 struct sk_buff *head,
5496 struct sk_buff *tail)
5497 {
5498 mon_mpdu = kzalloc_obj(*mon_mpdu, GFP_ATOMIC);
5499 if (!mon_mpdu)
5500 return -ENOMEM;
5501
5502 list_add_tail(&mon_mpdu->list, &dp->dp_full_mon_mpdu_list);
5503 mon_mpdu->head = head;
5504 mon_mpdu->tail = tail;
5505
5506 return 0;
5507 }
5508
ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu)5509 static void ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp *dp,
5510 struct dp_full_mon_mpdu *mon_mpdu)
5511 {
5512 struct dp_full_mon_mpdu *tmp;
5513 struct sk_buff *tmp_msdu, *skb_next;
5514
5515 if (list_empty(&dp->dp_full_mon_mpdu_list))
5516 return;
5517
5518 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5519 list_del(&mon_mpdu->list);
5520
5521 tmp_msdu = mon_mpdu->head;
5522 while (tmp_msdu) {
5523 skb_next = tmp_msdu->next;
5524 dev_kfree_skb_any(tmp_msdu);
5525 tmp_msdu = skb_next;
5526 }
5527
5528 kfree(mon_mpdu);
5529 }
5530 }
5531
ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k * ar,int mac_id,struct ath11k_mon_data * pmon,struct napi_struct * napi)5532 static int ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k *ar,
5533 int mac_id,
5534 struct ath11k_mon_data *pmon,
5535 struct napi_struct *napi)
5536 {
5537 struct ath11k_pdev_mon_stats *rx_mon_stats;
5538 struct dp_full_mon_mpdu *tmp;
5539 struct dp_full_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
5540 struct sk_buff *head_msdu, *tail_msdu;
5541 struct ath11k_base *ab = ar->ab;
5542 struct ath11k_dp *dp = &ab->dp;
5543 int ret;
5544
5545 rx_mon_stats = &pmon->rx_mon_stats;
5546
5547 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5548 list_del(&mon_mpdu->list);
5549 head_msdu = mon_mpdu->head;
5550 tail_msdu = mon_mpdu->tail;
5551 if (head_msdu && tail_msdu) {
5552 ret = ath11k_dp_rx_mon_deliver(ar, mac_id, head_msdu,
5553 &pmon->mon_ppdu_info,
5554 tail_msdu, napi);
5555 rx_mon_stats->dest_mpdu_done++;
5556 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, "full mon: deliver ppdu\n");
5557 }
5558 kfree(mon_mpdu);
5559 }
5560
5561 return ret;
5562 }
5563
5564 static int
ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5565 ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base *ab, int mac_id,
5566 struct napi_struct *napi, int budget)
5567 {
5568 struct ath11k *ar = ab->pdevs[mac_id].ar;
5569 struct ath11k_pdev_dp *dp = &ar->dp;
5570 struct ath11k_mon_data *pmon = &dp->mon_data;
5571 struct hal_sw_mon_ring_entries *sw_mon_entries;
5572 int quota = 0, work = 0, count;
5573
5574 sw_mon_entries = &pmon->sw_mon_entries;
5575
5576 while (pmon->hold_mon_dst_ring) {
5577 quota = ath11k_dp_rx_process_mon_status(ab, mac_id,
5578 napi, 1);
5579 if (pmon->buf_state == DP_MON_STATUS_MATCH) {
5580 count = sw_mon_entries->status_buf_count;
5581 if (count > 1) {
5582 quota += ath11k_dp_rx_process_mon_status(ab, mac_id,
5583 napi, count);
5584 }
5585
5586 ath11k_dp_rx_full_mon_deliver_ppdu(ar, dp->mac_id,
5587 pmon, napi);
5588 pmon->hold_mon_dst_ring = false;
5589 } else if (!pmon->mon_status_paddr ||
5590 pmon->buf_state == DP_MON_STATUS_LEAD) {
5591 sw_mon_entries->drop_ppdu = true;
5592 pmon->hold_mon_dst_ring = false;
5593 }
5594
5595 if (!quota)
5596 break;
5597
5598 work += quota;
5599 }
5600
5601 if (sw_mon_entries->drop_ppdu)
5602 ath11k_dp_rx_full_mon_drop_ppdu(&ab->dp, pmon->mon_mpdu);
5603
5604 return work;
5605 }
5606
ath11k_dp_full_mon_process_rx(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5607 static int ath11k_dp_full_mon_process_rx(struct ath11k_base *ab, int mac_id,
5608 struct napi_struct *napi, int budget)
5609 {
5610 struct ath11k *ar = ab->pdevs[mac_id].ar;
5611 struct ath11k_pdev_dp *dp = &ar->dp;
5612 struct ath11k_mon_data *pmon = &dp->mon_data;
5613 struct hal_sw_mon_ring_entries *sw_mon_entries;
5614 struct ath11k_pdev_mon_stats *rx_mon_stats;
5615 struct sk_buff *head_msdu, *tail_msdu;
5616 struct hal_srng *mon_dst_srng;
5617 void *ring_entry;
5618 u32 rx_bufs_used = 0, mpdu_rx_bufs_used;
5619 int quota = 0, ret;
5620 bool break_dst_ring = false;
5621
5622 spin_lock_bh(&pmon->mon_lock);
5623
5624 sw_mon_entries = &pmon->sw_mon_entries;
5625 rx_mon_stats = &pmon->rx_mon_stats;
5626
5627 if (pmon->hold_mon_dst_ring) {
5628 spin_unlock_bh(&pmon->mon_lock);
5629 goto reap_status_ring;
5630 }
5631
5632 mon_dst_srng = &ar->ab->hal.srng_list[dp->rxdma_mon_dst_ring.ring_id];
5633 spin_lock_bh(&mon_dst_srng->lock);
5634
5635 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5636 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5637 head_msdu = NULL;
5638 tail_msdu = NULL;
5639
5640 mpdu_rx_bufs_used = ath11k_dp_rx_full_mon_mpdu_pop(ar, ring_entry,
5641 &head_msdu,
5642 &tail_msdu,
5643 sw_mon_entries);
5644 rx_bufs_used += mpdu_rx_bufs_used;
5645
5646 if (!sw_mon_entries->end_of_ppdu) {
5647 if (head_msdu) {
5648 ret = ath11k_dp_rx_full_mon_prepare_mpdu(&ab->dp,
5649 pmon->mon_mpdu,
5650 head_msdu,
5651 tail_msdu);
5652 if (ret)
5653 break_dst_ring = true;
5654 }
5655
5656 goto next_entry;
5657 } else {
5658 if (!sw_mon_entries->ppdu_id &&
5659 !sw_mon_entries->mon_status_paddr) {
5660 break_dst_ring = true;
5661 goto next_entry;
5662 }
5663 }
5664
5665 rx_mon_stats->dest_ppdu_done++;
5666 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5667 pmon->buf_state = DP_MON_STATUS_LAG;
5668 pmon->mon_status_paddr = sw_mon_entries->mon_status_paddr;
5669 pmon->hold_mon_dst_ring = true;
5670 next_entry:
5671 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5672 mon_dst_srng);
5673 if (break_dst_ring)
5674 break;
5675 }
5676
5677 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5678 spin_unlock_bh(&mon_dst_srng->lock);
5679 spin_unlock_bh(&pmon->mon_lock);
5680
5681 if (rx_bufs_used) {
5682 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5683 &dp->rxdma_mon_buf_ring,
5684 rx_bufs_used,
5685 HAL_RX_BUF_RBM_SW3_BM);
5686 }
5687
5688 reap_status_ring:
5689 quota = ath11k_dp_rx_process_full_mon_status_ring(ab, mac_id,
5690 napi, budget);
5691
5692 return quota;
5693 }
5694
ath11k_dp_rx_process_mon_rings(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5695 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
5696 struct napi_struct *napi, int budget)
5697 {
5698 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5699 int ret = 0;
5700
5701 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5702 ab->hw_params.full_monitor_mode)
5703 ret = ath11k_dp_full_mon_process_rx(ab, mac_id, napi, budget);
5704 else
5705 ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
5706
5707 return ret;
5708 }
5709
ath11k_dp_rx_pdev_mon_status_attach(struct ath11k * ar)5710 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
5711 {
5712 struct ath11k_pdev_dp *dp = &ar->dp;
5713 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5714
5715 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5716
5717 memset(&pmon->rx_mon_stats, 0,
5718 sizeof(pmon->rx_mon_stats));
5719 return 0;
5720 }
5721
ath11k_dp_rx_pdev_mon_attach(struct ath11k * ar)5722 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
5723 {
5724 struct ath11k_pdev_dp *dp = &ar->dp;
5725 struct ath11k_mon_data *pmon = &dp->mon_data;
5726 struct hal_srng *mon_desc_srng = NULL;
5727 struct dp_srng *dp_srng;
5728 int ret = 0;
5729 u32 n_link_desc = 0;
5730
5731 ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
5732 if (ret) {
5733 ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
5734 return ret;
5735 }
5736
5737 /* if rxdma1_enable is false, no need to setup
5738 * rxdma_mon_desc_ring.
5739 */
5740 if (!ar->ab->hw_params.rxdma1_enable)
5741 return 0;
5742
5743 dp_srng = &dp->rxdma_mon_desc_ring;
5744 n_link_desc = dp_srng->size /
5745 ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
5746 mon_desc_srng =
5747 &ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
5748
5749 ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
5750 HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
5751 n_link_desc);
5752 if (ret) {
5753 ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
5754 return ret;
5755 }
5756 pmon->mon_last_linkdesc_paddr = 0;
5757 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
5758 spin_lock_init(&pmon->mon_lock);
5759
5760 return 0;
5761 }
5762
ath11k_dp_mon_link_free(struct ath11k * ar)5763 static int ath11k_dp_mon_link_free(struct ath11k *ar)
5764 {
5765 struct ath11k_pdev_dp *dp = &ar->dp;
5766 struct ath11k_mon_data *pmon = &dp->mon_data;
5767
5768 ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
5769 HAL_RXDMA_MONITOR_DESC,
5770 &dp->rxdma_mon_desc_ring);
5771 return 0;
5772 }
5773
ath11k_dp_rx_pdev_mon_detach(struct ath11k * ar)5774 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
5775 {
5776 ath11k_dp_mon_link_free(ar);
5777 return 0;
5778 }
5779
ath11k_dp_rx_pktlog_start(struct ath11k_base * ab)5780 int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab)
5781 {
5782 /* start reap timer */
5783 mod_timer(&ab->mon_reap_timer,
5784 jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
5785
5786 return 0;
5787 }
5788
ath11k_dp_rx_pktlog_stop(struct ath11k_base * ab,bool stop_timer)5789 int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer)
5790 {
5791 int ret;
5792
5793 if (stop_timer)
5794 timer_delete_sync(&ab->mon_reap_timer);
5795
5796 /* reap all the monitor related rings */
5797 ret = ath11k_dp_purge_mon_ring(ab);
5798 if (ret) {
5799 ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret);
5800 return ret;
5801 }
5802
5803 return 0;
5804 }
5805