xref: /linux/drivers/net/wireless/ath/ath11k/dp_rx.c (revision be54f8c558027a218423134dd9b8c7c46d92204a)
1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 #include <linux/ieee80211.h>
8 #include <linux/kernel.h>
9 #include <linux/skbuff.h>
10 #include <crypto/hash.h>
11 #include "core.h"
12 #include "debug.h"
13 #include "debugfs_htt_stats.h"
14 #include "debugfs_sta.h"
15 #include "hal_desc.h"
16 #include "hw.h"
17 #include "dp_rx.h"
18 #include "hal_rx.h"
19 #include "dp_tx.h"
20 #include "peer.h"
21 
22 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
23 
24 static inline
ath11k_dp_rx_h_80211_hdr(struct ath11k_base * ab,struct hal_rx_desc * desc)25 u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc)
26 {
27 	return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc);
28 }
29 
30 static inline
ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base * ab,struct hal_rx_desc * desc)31 enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab,
32 							struct hal_rx_desc *desc)
33 {
34 	if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc))
35 		return HAL_ENCRYPT_TYPE_OPEN;
36 
37 	return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc);
38 }
39 
ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base * ab,struct hal_rx_desc * desc)40 static inline u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab,
41 						      struct hal_rx_desc *desc)
42 {
43 	return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc);
44 }
45 
46 static inline
ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base * ab,struct hal_rx_desc * desc)47 bool ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base *ab,
48 					    struct hal_rx_desc *desc)
49 {
50 	return ab->hw_params.hw_ops->rx_desc_get_ldpc_support(desc);
51 }
52 
53 static inline
ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base * ab,struct hal_rx_desc * desc)54 u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab,
55 					      struct hal_rx_desc *desc)
56 {
57 	return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc);
58 }
59 
60 static inline
ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)61 bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab,
62 					      struct hal_rx_desc *desc)
63 {
64 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
65 }
66 
ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)67 static inline bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab,
68 						      struct hal_rx_desc *desc)
69 {
70 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc);
71 }
72 
ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base * ab,struct sk_buff * skb)73 static inline bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab,
74 							struct sk_buff *skb)
75 {
76 	struct ieee80211_hdr *hdr;
77 
78 	hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
79 	return ieee80211_has_morefrags(hdr->frame_control);
80 }
81 
ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base * ab,struct sk_buff * skb)82 static inline u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab,
83 						    struct sk_buff *skb)
84 {
85 	struct ieee80211_hdr *hdr;
86 
87 	hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
88 	return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
89 }
90 
ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base * ab,struct hal_rx_desc * desc)91 static inline u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab,
92 						   struct hal_rx_desc *desc)
93 {
94 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc);
95 }
96 
ath11k_dp_rx_get_attention(struct ath11k_base * ab,struct hal_rx_desc * desc)97 static inline void *ath11k_dp_rx_get_attention(struct ath11k_base *ab,
98 					       struct hal_rx_desc *desc)
99 {
100 	return ab->hw_params.hw_ops->rx_desc_get_attention(desc);
101 }
102 
ath11k_dp_rx_h_attn_msdu_done(struct rx_attention * attn)103 static inline bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn)
104 {
105 	return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
106 			   __le32_to_cpu(attn->info2));
107 }
108 
ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention * attn)109 static inline bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn)
110 {
111 	return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
112 			   __le32_to_cpu(attn->info1));
113 }
114 
ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention * attn)115 static inline bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn)
116 {
117 	return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
118 			   __le32_to_cpu(attn->info1));
119 }
120 
ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention * attn)121 static inline bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn)
122 {
123 	return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
124 			  __le32_to_cpu(attn->info2)) ==
125 		RX_DESC_DECRYPT_STATUS_CODE_OK);
126 }
127 
ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention * attn)128 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn)
129 {
130 	u32 info = __le32_to_cpu(attn->info1);
131 	u32 errmap = 0;
132 
133 	if (info & RX_ATTENTION_INFO1_FCS_ERR)
134 		errmap |= DP_RX_MPDU_ERR_FCS;
135 
136 	if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
137 		errmap |= DP_RX_MPDU_ERR_DECRYPT;
138 
139 	if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
140 		errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
141 
142 	if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
143 		errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
144 
145 	if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
146 		errmap |= DP_RX_MPDU_ERR_OVERFLOW;
147 
148 	if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
149 		errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
150 
151 	if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
152 		errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
153 
154 	return errmap;
155 }
156 
ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base * ab,struct hal_rx_desc * desc)157 static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab,
158 					     struct hal_rx_desc *desc)
159 {
160 	struct rx_attention *rx_attention;
161 	u32 errmap;
162 
163 	rx_attention = ath11k_dp_rx_get_attention(ab, desc);
164 	errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
165 
166 	return errmap & DP_RX_MPDU_ERR_MSDU_LEN;
167 }
168 
ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc)169 static inline u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab,
170 						     struct hal_rx_desc *desc)
171 {
172 	return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc);
173 }
174 
ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base * ab,struct hal_rx_desc * desc)175 static inline u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab,
176 					       struct hal_rx_desc *desc)
177 {
178 	return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc);
179 }
180 
ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base * ab,struct hal_rx_desc * desc)181 static inline u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab,
182 						    struct hal_rx_desc *desc)
183 {
184 	return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc);
185 }
186 
ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base * ab,struct hal_rx_desc * desc)187 static inline u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab,
188 						 struct hal_rx_desc *desc)
189 {
190 	return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc);
191 }
192 
ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base * ab,struct hal_rx_desc * desc)193 static inline u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab,
194 						 struct hal_rx_desc *desc)
195 {
196 	return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc);
197 }
198 
ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base * ab,struct hal_rx_desc * desc)199 static inline u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab,
200 						    struct hal_rx_desc *desc)
201 {
202 	return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc);
203 }
204 
ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base * ab,struct hal_rx_desc * desc)205 static inline u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab,
206 					       struct hal_rx_desc *desc)
207 {
208 	return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc));
209 }
210 
ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base * ab,struct hal_rx_desc * desc)211 static inline u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab,
212 					       struct hal_rx_desc *desc)
213 {
214 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc);
215 }
216 
ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base * ab,struct hal_rx_desc * desc)217 static inline u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab,
218 						    struct hal_rx_desc *desc)
219 {
220 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc);
221 }
222 
ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base * ab,struct hal_rx_desc * desc)223 static inline u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab,
224 					       struct hal_rx_desc *desc)
225 {
226 	return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc);
227 }
228 
ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)229 static inline bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab,
230 						      struct hal_rx_desc *desc)
231 {
232 	return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc);
233 }
234 
ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)235 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab,
236 					      struct hal_rx_desc *desc)
237 {
238 	return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc);
239 }
240 
ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base * ab,struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)241 static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab,
242 					   struct hal_rx_desc *fdesc,
243 					   struct hal_rx_desc *ldesc)
244 {
245 	ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc);
246 }
247 
ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention * attn)248 static inline u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn)
249 {
250 	return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
251 			 __le32_to_cpu(attn->info1));
252 }
253 
ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)254 static inline u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab,
255 						struct hal_rx_desc *rx_desc)
256 {
257 	u8 *rx_pkt_hdr;
258 
259 	rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc);
260 
261 	return rx_pkt_hdr;
262 }
263 
ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)264 static inline bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab,
265 					       struct hal_rx_desc *rx_desc)
266 {
267 	u32 tlv_tag;
268 
269 	tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc);
270 
271 	return tlv_tag == HAL_RX_MPDU_START;
272 }
273 
ath11k_dp_rxdesc_get_ppduid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)274 static inline u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab,
275 					      struct hal_rx_desc *rx_desc)
276 {
277 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc);
278 }
279 
ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc,u16 len)280 static inline void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab,
281 						 struct hal_rx_desc *desc,
282 						 u16 len)
283 {
284 	ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len);
285 }
286 
ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base * ab,struct hal_rx_desc * desc)287 static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab,
288 					struct hal_rx_desc *desc)
289 {
290 	struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc);
291 
292 	return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) &&
293 		(!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST,
294 		 __le32_to_cpu(attn->info1)));
295 }
296 
ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)297 static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab,
298 					     struct hal_rx_desc *desc)
299 {
300 	return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc);
301 }
302 
ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base * ab,struct hal_rx_desc * desc)303 static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab,
304 					     struct hal_rx_desc *desc)
305 {
306 	return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc);
307 }
308 
ath11k_dp_service_mon_ring(struct timer_list * t)309 static void ath11k_dp_service_mon_ring(struct timer_list *t)
310 {
311 	struct ath11k_base *ab = timer_container_of(ab, t, mon_reap_timer);
312 	int i;
313 
314 	for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++)
315 		ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
316 
317 	mod_timer(&ab->mon_reap_timer, jiffies +
318 		  msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
319 }
320 
ath11k_dp_purge_mon_ring(struct ath11k_base * ab)321 static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab)
322 {
323 	int i, reaped = 0;
324 	unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS);
325 
326 	do {
327 		for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++)
328 			reaped += ath11k_dp_rx_process_mon_rings(ab, i,
329 								 NULL,
330 								 DP_MON_SERVICE_BUDGET);
331 
332 		/* nothing more to reap */
333 		if (reaped < DP_MON_SERVICE_BUDGET)
334 			return 0;
335 
336 	} while (time_before(jiffies, timeout));
337 
338 	ath11k_warn(ab, "dp mon ring purge timeout");
339 
340 	return -ETIMEDOUT;
341 }
342 
343 /* Returns number of Rx buffers replenished */
ath11k_dp_rxbufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)344 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
345 			       struct dp_rxdma_ring *rx_ring,
346 			       int req_entries,
347 			       enum hal_rx_buf_return_buf_manager mgr)
348 {
349 	struct hal_srng *srng;
350 	u32 *desc;
351 	struct sk_buff *skb;
352 	int num_free;
353 	int num_remain;
354 	int buf_id;
355 	u32 cookie;
356 	dma_addr_t paddr;
357 
358 	req_entries = min(req_entries, rx_ring->bufs_max);
359 
360 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
361 
362 	spin_lock_bh(&srng->lock);
363 
364 	ath11k_hal_srng_access_begin(ab, srng);
365 
366 	num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
367 	if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
368 		req_entries = num_free;
369 
370 	req_entries = min(num_free, req_entries);
371 	num_remain = req_entries;
372 
373 	while (num_remain > 0) {
374 		skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
375 				    DP_RX_BUFFER_ALIGN_SIZE);
376 		if (!skb)
377 			break;
378 
379 		if (!IS_ALIGNED((unsigned long)skb->data,
380 				DP_RX_BUFFER_ALIGN_SIZE)) {
381 			skb_pull(skb,
382 				 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
383 				 skb->data);
384 		}
385 
386 		paddr = dma_map_single(ab->dev, skb->data,
387 				       skb->len + skb_tailroom(skb),
388 				       DMA_FROM_DEVICE);
389 		if (dma_mapping_error(ab->dev, paddr))
390 			goto fail_free_skb;
391 
392 		spin_lock_bh(&rx_ring->idr_lock);
393 		buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 1,
394 				   (rx_ring->bufs_max * 3) + 1, GFP_ATOMIC);
395 		spin_unlock_bh(&rx_ring->idr_lock);
396 		if (buf_id <= 0)
397 			goto fail_dma_unmap;
398 
399 		desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
400 		if (!desc)
401 			goto fail_idr_remove;
402 
403 		ATH11K_SKB_RXCB(skb)->paddr = paddr;
404 
405 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
406 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
407 
408 		num_remain--;
409 
410 		ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
411 	}
412 
413 	ath11k_hal_srng_access_end(ab, srng);
414 
415 	spin_unlock_bh(&srng->lock);
416 
417 	return req_entries - num_remain;
418 
419 fail_idr_remove:
420 	spin_lock_bh(&rx_ring->idr_lock);
421 	idr_remove(&rx_ring->bufs_idr, buf_id);
422 	spin_unlock_bh(&rx_ring->idr_lock);
423 fail_dma_unmap:
424 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
425 			 DMA_FROM_DEVICE);
426 fail_free_skb:
427 	dev_kfree_skb_any(skb);
428 
429 	ath11k_hal_srng_access_end(ab, srng);
430 
431 	spin_unlock_bh(&srng->lock);
432 
433 	return req_entries - num_remain;
434 }
435 
ath11k_dp_rxdma_buf_ring_free(struct ath11k * ar,struct dp_rxdma_ring * rx_ring)436 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
437 					 struct dp_rxdma_ring *rx_ring)
438 {
439 	struct sk_buff *skb;
440 	int buf_id;
441 
442 	spin_lock_bh(&rx_ring->idr_lock);
443 	idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
444 		idr_remove(&rx_ring->bufs_idr, buf_id);
445 		/* TODO: Understand where internal driver does this dma_unmap
446 		 * of rxdma_buffer.
447 		 */
448 		dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
449 				 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
450 		dev_kfree_skb_any(skb);
451 	}
452 
453 	idr_destroy(&rx_ring->bufs_idr);
454 	spin_unlock_bh(&rx_ring->idr_lock);
455 
456 	return 0;
457 }
458 
ath11k_dp_rxdma_pdev_buf_free(struct ath11k * ar)459 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
460 {
461 	struct ath11k_pdev_dp *dp = &ar->dp;
462 	struct ath11k_base *ab = ar->ab;
463 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
464 	int i;
465 
466 	ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
467 
468 	rx_ring = &dp->rxdma_mon_buf_ring;
469 	ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
470 
471 	for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
472 		rx_ring = &dp->rx_mon_status_refill_ring[i];
473 		ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
474 	}
475 
476 	return 0;
477 }
478 
ath11k_dp_rxdma_ring_buf_setup(struct ath11k * ar,struct dp_rxdma_ring * rx_ring,u32 ringtype)479 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
480 					  struct dp_rxdma_ring *rx_ring,
481 					  u32 ringtype)
482 {
483 	struct ath11k_pdev_dp *dp = &ar->dp;
484 	int num_entries;
485 
486 	num_entries = rx_ring->refill_buf_ring.size /
487 		ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
488 
489 	rx_ring->bufs_max = num_entries;
490 	ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
491 				   ar->ab->hw_params.hal_params->rx_buf_rbm);
492 	return 0;
493 }
494 
ath11k_dp_rxdma_pdev_buf_setup(struct ath11k * ar)495 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
496 {
497 	struct ath11k_pdev_dp *dp = &ar->dp;
498 	struct ath11k_base *ab = ar->ab;
499 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
500 	int i;
501 
502 	ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
503 
504 	if (ar->ab->hw_params.rxdma1_enable) {
505 		rx_ring = &dp->rxdma_mon_buf_ring;
506 		ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
507 	}
508 
509 	for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
510 		rx_ring = &dp->rx_mon_status_refill_ring[i];
511 		ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
512 	}
513 
514 	return 0;
515 }
516 
ath11k_dp_rx_pdev_srng_free(struct ath11k * ar)517 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
518 {
519 	struct ath11k_pdev_dp *dp = &ar->dp;
520 	struct ath11k_base *ab = ar->ab;
521 	int i;
522 
523 	ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
524 
525 	for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
526 		if (ab->hw_params.rx_mac_buf_ring)
527 			ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
528 
529 		ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
530 		ath11k_dp_srng_cleanup(ab,
531 				       &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
532 	}
533 
534 	ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
535 }
536 
ath11k_dp_pdev_reo_cleanup(struct ath11k_base * ab)537 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
538 {
539 	struct ath11k_dp *dp = &ab->dp;
540 	int i;
541 
542 	for (i = 0; i < DP_REO_DST_RING_MAX; i++)
543 		ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
544 }
545 
ath11k_dp_pdev_reo_setup(struct ath11k_base * ab)546 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
547 {
548 	struct ath11k_dp *dp = &ab->dp;
549 	int ret;
550 	int i;
551 
552 	for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
553 		ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
554 					   HAL_REO_DST, i, 0,
555 					   DP_REO_DST_RING_SIZE);
556 		if (ret) {
557 			ath11k_warn(ab, "failed to setup reo_dst_ring\n");
558 			goto err_reo_cleanup;
559 		}
560 	}
561 
562 	return 0;
563 
564 err_reo_cleanup:
565 	ath11k_dp_pdev_reo_cleanup(ab);
566 
567 	return ret;
568 }
569 
ath11k_dp_rx_pdev_srng_alloc(struct ath11k * ar)570 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
571 {
572 	struct ath11k_pdev_dp *dp = &ar->dp;
573 	struct ath11k_base *ab = ar->ab;
574 	struct dp_srng *srng = NULL;
575 	int i;
576 	int ret;
577 
578 	ret = ath11k_dp_srng_setup(ar->ab,
579 				   &dp->rx_refill_buf_ring.refill_buf_ring,
580 				   HAL_RXDMA_BUF, 0,
581 				   dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
582 	if (ret) {
583 		ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
584 		return ret;
585 	}
586 
587 	if (ar->ab->hw_params.rx_mac_buf_ring) {
588 		for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
589 			ret = ath11k_dp_srng_setup(ar->ab,
590 						   &dp->rx_mac_buf_ring[i],
591 						   HAL_RXDMA_BUF, 1,
592 						   dp->mac_id + i, 1024);
593 			if (ret) {
594 				ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
595 					    i);
596 				return ret;
597 			}
598 		}
599 	}
600 
601 	for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
602 		ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
603 					   HAL_RXDMA_DST, 0, dp->mac_id + i,
604 					   DP_RXDMA_ERR_DST_RING_SIZE);
605 		if (ret) {
606 			ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
607 			return ret;
608 		}
609 	}
610 
611 	for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
612 		srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
613 		ret = ath11k_dp_srng_setup(ar->ab,
614 					   srng,
615 					   HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
616 					   DP_RXDMA_MON_STATUS_RING_SIZE);
617 		if (ret) {
618 			ath11k_warn(ar->ab,
619 				    "failed to setup rx_mon_status_refill_ring %d\n", i);
620 			return ret;
621 		}
622 	}
623 
624 	/* if rxdma1_enable is false, then it doesn't need
625 	 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
626 	 * and rxdma_mon_desc_ring.
627 	 * init reap timer for QCA6390.
628 	 */
629 	if (!ar->ab->hw_params.rxdma1_enable) {
630 		//init mon status buffer reap timer
631 		timer_setup(&ar->ab->mon_reap_timer,
632 			    ath11k_dp_service_mon_ring, 0);
633 		return 0;
634 	}
635 
636 	ret = ath11k_dp_srng_setup(ar->ab,
637 				   &dp->rxdma_mon_buf_ring.refill_buf_ring,
638 				   HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
639 				   DP_RXDMA_MONITOR_BUF_RING_SIZE);
640 	if (ret) {
641 		ath11k_warn(ar->ab,
642 			    "failed to setup HAL_RXDMA_MONITOR_BUF\n");
643 		return ret;
644 	}
645 
646 	ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
647 				   HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
648 				   DP_RXDMA_MONITOR_DST_RING_SIZE);
649 	if (ret) {
650 		ath11k_warn(ar->ab,
651 			    "failed to setup HAL_RXDMA_MONITOR_DST\n");
652 		return ret;
653 	}
654 
655 	ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
656 				   HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
657 				   DP_RXDMA_MONITOR_DESC_RING_SIZE);
658 	if (ret) {
659 		ath11k_warn(ar->ab,
660 			    "failed to setup HAL_RXDMA_MONITOR_DESC\n");
661 		return ret;
662 	}
663 
664 	return 0;
665 }
666 
ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base * ab)667 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
668 {
669 	struct ath11k_dp *dp = &ab->dp;
670 	struct dp_reo_cmd *cmd, *tmp;
671 	struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
672 	struct dp_rx_tid *rx_tid;
673 
674 	spin_lock_bh(&dp->reo_cmd_lock);
675 	list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
676 		list_del(&cmd->list);
677 		rx_tid = &cmd->data;
678 		if (rx_tid->vaddr_unaligned) {
679 			dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
680 					     rx_tid->vaddr_unaligned,
681 					     rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
682 			rx_tid->vaddr_unaligned = NULL;
683 		}
684 		kfree(cmd);
685 	}
686 
687 	list_for_each_entry_safe(cmd_cache, tmp_cache,
688 				 &dp->reo_cmd_cache_flush_list, list) {
689 		list_del(&cmd_cache->list);
690 		dp->reo_cmd_cache_flush_count--;
691 		rx_tid = &cmd_cache->data;
692 		if (rx_tid->vaddr_unaligned) {
693 			dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
694 					     rx_tid->vaddr_unaligned,
695 					     rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
696 			rx_tid->vaddr_unaligned = NULL;
697 		}
698 		kfree(cmd_cache);
699 	}
700 	spin_unlock_bh(&dp->reo_cmd_lock);
701 }
702 
ath11k_dp_reo_cmd_free(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)703 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
704 				   enum hal_reo_cmd_status status)
705 {
706 	struct dp_rx_tid *rx_tid = ctx;
707 
708 	if (status != HAL_REO_CMD_SUCCESS)
709 		ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
710 			    rx_tid->tid, status);
711 	if (rx_tid->vaddr_unaligned) {
712 		dma_free_noncoherent(dp->ab->dev, rx_tid->unaligned_size,
713 				     rx_tid->vaddr_unaligned,
714 				     rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
715 		rx_tid->vaddr_unaligned = NULL;
716 	}
717 }
718 
ath11k_dp_reo_cache_flush(struct ath11k_base * ab,struct dp_rx_tid * rx_tid)719 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
720 				      struct dp_rx_tid *rx_tid)
721 {
722 	struct ath11k_hal_reo_cmd cmd = {0};
723 	unsigned long tot_desc_sz, desc_sz;
724 	int ret;
725 
726 	tot_desc_sz = rx_tid->size;
727 	desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
728 
729 	while (tot_desc_sz > desc_sz) {
730 		tot_desc_sz -= desc_sz;
731 		cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
732 		cmd.addr_hi = upper_32_bits(rx_tid->paddr);
733 		ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
734 						HAL_REO_CMD_FLUSH_CACHE, &cmd,
735 						NULL);
736 		if (ret)
737 			ath11k_warn(ab,
738 				    "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
739 				    rx_tid->tid, ret);
740 	}
741 
742 	memset(&cmd, 0, sizeof(cmd));
743 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
744 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
745 	cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
746 	ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
747 					HAL_REO_CMD_FLUSH_CACHE,
748 					&cmd, ath11k_dp_reo_cmd_free);
749 	if (ret) {
750 		ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
751 			   rx_tid->tid, ret);
752 		dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
753 				     rx_tid->vaddr_unaligned,
754 				     rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
755 		rx_tid->vaddr_unaligned = NULL;
756 	}
757 }
758 
ath11k_dp_rx_tid_del_func(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)759 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
760 				      enum hal_reo_cmd_status status)
761 {
762 	struct ath11k_base *ab = dp->ab;
763 	struct dp_rx_tid *rx_tid = ctx;
764 	struct dp_reo_cache_flush_elem *elem, *tmp;
765 
766 	if (status == HAL_REO_CMD_DRAIN) {
767 		goto free_desc;
768 	} else if (status != HAL_REO_CMD_SUCCESS) {
769 		/* Shouldn't happen! Cleanup in case of other failure? */
770 		ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
771 			    rx_tid->tid, status);
772 		return;
773 	}
774 
775 	elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
776 	if (!elem)
777 		goto free_desc;
778 
779 	elem->ts = jiffies;
780 	memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
781 
782 	spin_lock_bh(&dp->reo_cmd_lock);
783 	list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
784 	dp->reo_cmd_cache_flush_count++;
785 
786 	/* Flush and invalidate aged REO desc from HW cache */
787 	list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
788 				 list) {
789 		if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
790 		    time_after(jiffies, elem->ts +
791 			       msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
792 			list_del(&elem->list);
793 			dp->reo_cmd_cache_flush_count--;
794 			spin_unlock_bh(&dp->reo_cmd_lock);
795 
796 			ath11k_dp_reo_cache_flush(ab, &elem->data);
797 			kfree(elem);
798 			spin_lock_bh(&dp->reo_cmd_lock);
799 		}
800 	}
801 	spin_unlock_bh(&dp->reo_cmd_lock);
802 
803 	return;
804 free_desc:
805 	dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
806 			     rx_tid->vaddr_unaligned,
807 			     rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
808 	rx_tid->vaddr_unaligned = NULL;
809 }
810 
ath11k_peer_rx_tid_delete(struct ath11k * ar,struct ath11k_peer * peer,u8 tid)811 void ath11k_peer_rx_tid_delete(struct ath11k *ar,
812 			       struct ath11k_peer *peer, u8 tid)
813 {
814 	struct ath11k_hal_reo_cmd cmd = {0};
815 	struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
816 	int ret;
817 
818 	if (!rx_tid->active)
819 		return;
820 
821 	rx_tid->active = false;
822 
823 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
824 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
825 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
826 	cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
827 	ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
828 					HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
829 					ath11k_dp_rx_tid_del_func);
830 	if (ret) {
831 		if (ret != -ESHUTDOWN)
832 			ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
833 				   tid, ret);
834 		dma_free_noncoherent(ar->ab->dev, rx_tid->unaligned_size,
835 				     rx_tid->vaddr_unaligned,
836 				     rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
837 		rx_tid->vaddr_unaligned = NULL;
838 	}
839 
840 	rx_tid->paddr = 0;
841 	rx_tid->paddr_unaligned = 0;
842 	rx_tid->size = 0;
843 	rx_tid->unaligned_size = 0;
844 }
845 
ath11k_dp_rx_link_desc_return(struct ath11k_base * ab,u32 * link_desc,enum hal_wbm_rel_bm_act action)846 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
847 					 u32 *link_desc,
848 					 enum hal_wbm_rel_bm_act action)
849 {
850 	struct ath11k_dp *dp = &ab->dp;
851 	struct hal_srng *srng;
852 	u32 *desc;
853 	int ret = 0;
854 
855 	srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
856 
857 	spin_lock_bh(&srng->lock);
858 
859 	ath11k_hal_srng_access_begin(ab, srng);
860 
861 	desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
862 	if (!desc) {
863 		ret = -ENOBUFS;
864 		goto exit;
865 	}
866 
867 	ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
868 					 action);
869 
870 exit:
871 	ath11k_hal_srng_access_end(ab, srng);
872 
873 	spin_unlock_bh(&srng->lock);
874 
875 	return ret;
876 }
877 
ath11k_dp_rx_frags_cleanup(struct dp_rx_tid * rx_tid,bool rel_link_desc)878 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
879 {
880 	struct ath11k_base *ab = rx_tid->ab;
881 
882 	lockdep_assert_held(&ab->base_lock);
883 
884 	if (rx_tid->dst_ring_desc) {
885 		if (rel_link_desc)
886 			ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
887 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
888 		kfree(rx_tid->dst_ring_desc);
889 		rx_tid->dst_ring_desc = NULL;
890 	}
891 
892 	rx_tid->cur_sn = 0;
893 	rx_tid->last_frag_no = 0;
894 	rx_tid->rx_frag_bitmap = 0;
895 	__skb_queue_purge(&rx_tid->rx_frags);
896 }
897 
ath11k_peer_frags_flush(struct ath11k * ar,struct ath11k_peer * peer)898 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
899 {
900 	struct dp_rx_tid *rx_tid;
901 	int i;
902 
903 	lockdep_assert_held(&ar->ab->base_lock);
904 
905 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
906 		rx_tid = &peer->rx_tid[i];
907 
908 		spin_unlock_bh(&ar->ab->base_lock);
909 		timer_delete_sync(&rx_tid->frag_timer);
910 		spin_lock_bh(&ar->ab->base_lock);
911 
912 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
913 	}
914 }
915 
ath11k_peer_rx_tid_cleanup(struct ath11k * ar,struct ath11k_peer * peer)916 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
917 {
918 	struct dp_rx_tid *rx_tid;
919 	int i;
920 
921 	lockdep_assert_held(&ar->ab->base_lock);
922 
923 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
924 		rx_tid = &peer->rx_tid[i];
925 
926 		ath11k_peer_rx_tid_delete(ar, peer, i);
927 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
928 
929 		spin_unlock_bh(&ar->ab->base_lock);
930 		timer_delete_sync(&rx_tid->frag_timer);
931 		spin_lock_bh(&ar->ab->base_lock);
932 	}
933 }
934 
ath11k_peer_rx_tid_reo_update(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)935 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
936 					 struct ath11k_peer *peer,
937 					 struct dp_rx_tid *rx_tid,
938 					 u32 ba_win_sz, u16 ssn,
939 					 bool update_ssn)
940 {
941 	struct ath11k_hal_reo_cmd cmd = {0};
942 	int ret;
943 
944 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
945 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
946 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
947 	cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
948 	cmd.ba_window_size = ba_win_sz;
949 
950 	if (update_ssn) {
951 		cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
952 		cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
953 	}
954 
955 	ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
956 					HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
957 					NULL);
958 	if (ret) {
959 		ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
960 			    rx_tid->tid, ret);
961 		return ret;
962 	}
963 
964 	rx_tid->ba_win_sz = ba_win_sz;
965 
966 	return 0;
967 }
968 
ath11k_dp_rx_tid_mem_free(struct ath11k_base * ab,const u8 * peer_mac,int vdev_id,u8 tid)969 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
970 				      const u8 *peer_mac, int vdev_id, u8 tid)
971 {
972 	struct ath11k_peer *peer;
973 	struct dp_rx_tid *rx_tid;
974 
975 	spin_lock_bh(&ab->base_lock);
976 
977 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
978 	if (!peer) {
979 		ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
980 		goto unlock_exit;
981 	}
982 
983 	rx_tid = &peer->rx_tid[tid];
984 	if (!rx_tid->active)
985 		goto unlock_exit;
986 
987 	dma_free_noncoherent(ab->dev, rx_tid->unaligned_size, rx_tid->vaddr_unaligned,
988 			     rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
989 	rx_tid->vaddr_unaligned = NULL;
990 
991 	rx_tid->active = false;
992 
993 unlock_exit:
994 	spin_unlock_bh(&ab->base_lock);
995 }
996 
ath11k_peer_rx_tid_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)997 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
998 			     u8 tid, u32 ba_win_sz, u16 ssn,
999 			     enum hal_pn_type pn_type)
1000 {
1001 	struct ath11k_base *ab = ar->ab;
1002 	struct ath11k_peer *peer;
1003 	struct dp_rx_tid *rx_tid;
1004 	u32 hw_desc_sz, *vaddr;
1005 	void *vaddr_unaligned;
1006 	dma_addr_t paddr;
1007 	int ret;
1008 
1009 	spin_lock_bh(&ab->base_lock);
1010 
1011 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
1012 	if (!peer) {
1013 		ath11k_warn(ab, "failed to find the peer %pM to set up rx tid\n",
1014 			    peer_mac);
1015 		spin_unlock_bh(&ab->base_lock);
1016 		return -ENOENT;
1017 	}
1018 
1019 	rx_tid = &peer->rx_tid[tid];
1020 	/* Update the tid queue if it is already setup */
1021 	if (rx_tid->active) {
1022 		paddr = rx_tid->paddr;
1023 		ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
1024 						    ba_win_sz, ssn, true);
1025 		spin_unlock_bh(&ab->base_lock);
1026 		if (ret) {
1027 			ath11k_warn(ab, "failed to update reo for peer %pM rx tid %d\n: %d",
1028 				    peer_mac, tid, ret);
1029 			return ret;
1030 		}
1031 
1032 		ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1033 							     peer_mac, paddr,
1034 							     tid, 1, ba_win_sz);
1035 		if (ret)
1036 			ath11k_warn(ab, "failed to send wmi rx reorder queue for peer %pM tid %d: %d\n",
1037 				    peer_mac, tid, ret);
1038 		return ret;
1039 	}
1040 
1041 	rx_tid->tid = tid;
1042 
1043 	rx_tid->ba_win_sz = ba_win_sz;
1044 
1045 	/* TODO: Optimize the memory allocation for qos tid based on
1046 	 * the actual BA window size in REO tid update path.
1047 	 */
1048 	if (tid == HAL_DESC_REO_NON_QOS_TID)
1049 		hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
1050 	else
1051 		hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
1052 
1053 	rx_tid->unaligned_size = hw_desc_sz + HAL_LINK_DESC_ALIGN - 1;
1054 	vaddr_unaligned = dma_alloc_noncoherent(ab->dev, rx_tid->unaligned_size, &paddr,
1055 						DMA_BIDIRECTIONAL, GFP_ATOMIC);
1056 	if (!vaddr_unaligned) {
1057 		spin_unlock_bh(&ab->base_lock);
1058 		return -ENOMEM;
1059 	}
1060 
1061 	rx_tid->vaddr_unaligned = vaddr_unaligned;
1062 	vaddr = PTR_ALIGN(vaddr_unaligned, HAL_LINK_DESC_ALIGN);
1063 	rx_tid->paddr_unaligned = paddr;
1064 	rx_tid->paddr = rx_tid->paddr_unaligned + ((unsigned long)vaddr -
1065 			(unsigned long)rx_tid->vaddr_unaligned);
1066 	ath11k_hal_reo_qdesc_setup(vaddr, tid, ba_win_sz, ssn, pn_type);
1067 	rx_tid->size = hw_desc_sz;
1068 	rx_tid->active = true;
1069 
1070 	/* After dma_alloc_noncoherent, vaddr is being modified for reo qdesc setup.
1071 	 * Since these changes are not reflected in the device, driver now needs to
1072 	 * explicitly call dma_sync_single_for_device.
1073 	 */
1074 	dma_sync_single_for_device(ab->dev, rx_tid->paddr,
1075 				   rx_tid->size,
1076 				   DMA_TO_DEVICE);
1077 	spin_unlock_bh(&ab->base_lock);
1078 
1079 	ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, rx_tid->paddr,
1080 						     tid, 1, ba_win_sz);
1081 	if (ret) {
1082 		ath11k_warn(ar->ab, "failed to setup rx reorder queue for peer %pM tid %d: %d\n",
1083 			    peer_mac, tid, ret);
1084 		ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
1085 	}
1086 
1087 	return ret;
1088 }
1089 
ath11k_dp_rx_ampdu_start(struct ath11k * ar,struct ieee80211_ampdu_params * params)1090 int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
1091 			     struct ieee80211_ampdu_params *params)
1092 {
1093 	struct ath11k_base *ab = ar->ab;
1094 	struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta);
1095 	int vdev_id = arsta->arvif->vdev_id;
1096 	int ret;
1097 
1098 	ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
1099 				       params->tid, params->buf_size,
1100 				       params->ssn, arsta->pn_type);
1101 	if (ret)
1102 		ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
1103 
1104 	return ret;
1105 }
1106 
ath11k_dp_rx_ampdu_stop(struct ath11k * ar,struct ieee80211_ampdu_params * params)1107 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
1108 			    struct ieee80211_ampdu_params *params)
1109 {
1110 	struct ath11k_base *ab = ar->ab;
1111 	struct ath11k_peer *peer;
1112 	struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta);
1113 	int vdev_id = arsta->arvif->vdev_id;
1114 	dma_addr_t paddr;
1115 	bool active;
1116 	int ret;
1117 
1118 	spin_lock_bh(&ab->base_lock);
1119 
1120 	peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
1121 	if (!peer) {
1122 		ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1123 		spin_unlock_bh(&ab->base_lock);
1124 		return -ENOENT;
1125 	}
1126 
1127 	paddr = peer->rx_tid[params->tid].paddr;
1128 	active = peer->rx_tid[params->tid].active;
1129 
1130 	if (!active) {
1131 		spin_unlock_bh(&ab->base_lock);
1132 		return 0;
1133 	}
1134 
1135 	ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1136 	spin_unlock_bh(&ab->base_lock);
1137 	if (ret) {
1138 		ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1139 			    params->tid, ret);
1140 		return ret;
1141 	}
1142 
1143 	ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1144 						     params->sta->addr, paddr,
1145 						     params->tid, 1, 1);
1146 	if (ret)
1147 		ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
1148 			    ret);
1149 
1150 	return ret;
1151 }
1152 
ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1153 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
1154 				       const u8 *peer_addr,
1155 				       enum set_key_cmd key_cmd,
1156 				       struct ieee80211_key_conf *key)
1157 {
1158 	struct ath11k *ar = arvif->ar;
1159 	struct ath11k_base *ab = ar->ab;
1160 	struct ath11k_hal_reo_cmd cmd = {0};
1161 	struct ath11k_peer *peer;
1162 	struct dp_rx_tid *rx_tid;
1163 	u8 tid;
1164 	int ret = 0;
1165 
1166 	/* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1167 	 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1168 	 * for now.
1169 	 */
1170 	if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1171 		return 0;
1172 
1173 	cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
1174 	cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
1175 		    HAL_REO_CMD_UPD0_PN_SIZE |
1176 		    HAL_REO_CMD_UPD0_PN_VALID |
1177 		    HAL_REO_CMD_UPD0_PN_CHECK |
1178 		    HAL_REO_CMD_UPD0_SVLD;
1179 
1180 	switch (key->cipher) {
1181 	case WLAN_CIPHER_SUITE_TKIP:
1182 	case WLAN_CIPHER_SUITE_CCMP:
1183 	case WLAN_CIPHER_SUITE_CCMP_256:
1184 	case WLAN_CIPHER_SUITE_GCMP:
1185 	case WLAN_CIPHER_SUITE_GCMP_256:
1186 		if (key_cmd == SET_KEY) {
1187 			cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1188 			cmd.pn_size = 48;
1189 		}
1190 		break;
1191 	default:
1192 		break;
1193 	}
1194 
1195 	spin_lock_bh(&ab->base_lock);
1196 
1197 	peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
1198 	if (!peer) {
1199 		ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
1200 		spin_unlock_bh(&ab->base_lock);
1201 		return -ENOENT;
1202 	}
1203 
1204 	for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1205 		rx_tid = &peer->rx_tid[tid];
1206 		if (!rx_tid->active)
1207 			continue;
1208 		cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1209 		cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1210 		ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
1211 						HAL_REO_CMD_UPDATE_RX_QUEUE,
1212 						&cmd, NULL);
1213 		if (ret) {
1214 			ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
1215 				    tid, ret);
1216 			break;
1217 		}
1218 	}
1219 
1220 	spin_unlock_bh(&ab->base_lock);
1221 
1222 	return ret;
1223 }
1224 
ath11k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1225 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1226 					     u16 peer_id)
1227 {
1228 	int i;
1229 
1230 	for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1231 		if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1232 			if (peer_id == ppdu_stats->user_stats[i].peer_id)
1233 				return i;
1234 		} else {
1235 			return i;
1236 		}
1237 	}
1238 
1239 	return -EINVAL;
1240 }
1241 
ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1242 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
1243 					   u16 tag, u16 len, const void *ptr,
1244 					   void *data)
1245 {
1246 	struct htt_ppdu_stats_info *ppdu_info;
1247 	struct htt_ppdu_user_stats *user_stats;
1248 	int cur_user;
1249 	u16 peer_id;
1250 
1251 	ppdu_info = data;
1252 
1253 	switch (tag) {
1254 	case HTT_PPDU_STATS_TAG_COMMON:
1255 		if (len < sizeof(struct htt_ppdu_stats_common)) {
1256 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1257 				    len, tag);
1258 			return -EINVAL;
1259 		}
1260 		memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
1261 		       sizeof(struct htt_ppdu_stats_common));
1262 		break;
1263 	case HTT_PPDU_STATS_TAG_USR_RATE:
1264 		if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1265 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1266 				    len, tag);
1267 			return -EINVAL;
1268 		}
1269 
1270 		peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1271 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1272 						      peer_id);
1273 		if (cur_user < 0)
1274 			return -EINVAL;
1275 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1276 		user_stats->peer_id = peer_id;
1277 		user_stats->is_valid_peer_id = true;
1278 		memcpy((void *)&user_stats->rate, ptr,
1279 		       sizeof(struct htt_ppdu_stats_user_rate));
1280 		user_stats->tlv_flags |= BIT(tag);
1281 		break;
1282 	case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1283 		if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1284 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1285 				    len, tag);
1286 			return -EINVAL;
1287 		}
1288 
1289 		peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1290 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1291 						      peer_id);
1292 		if (cur_user < 0)
1293 			return -EINVAL;
1294 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1295 		user_stats->peer_id = peer_id;
1296 		user_stats->is_valid_peer_id = true;
1297 		memcpy((void *)&user_stats->cmpltn_cmn, ptr,
1298 		       sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1299 		user_stats->tlv_flags |= BIT(tag);
1300 		break;
1301 	case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1302 		if (len <
1303 		    sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1304 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1305 				    len, tag);
1306 			return -EINVAL;
1307 		}
1308 
1309 		peer_id =
1310 		((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1311 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1312 						      peer_id);
1313 		if (cur_user < 0)
1314 			return -EINVAL;
1315 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1316 		user_stats->peer_id = peer_id;
1317 		user_stats->is_valid_peer_id = true;
1318 		memcpy((void *)&user_stats->ack_ba, ptr,
1319 		       sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1320 		user_stats->tlv_flags |= BIT(tag);
1321 		break;
1322 	}
1323 	return 0;
1324 }
1325 
ath11k_dp_htt_tlv_iter(struct ath11k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath11k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1326 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
1327 			   int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
1328 				       const void *ptr, void *data),
1329 			   void *data)
1330 {
1331 	const struct htt_tlv *tlv;
1332 	const void *begin = ptr;
1333 	u16 tlv_tag, tlv_len;
1334 	int ret = -EINVAL;
1335 
1336 	while (len > 0) {
1337 		if (len < sizeof(*tlv)) {
1338 			ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1339 				   ptr - begin, len, sizeof(*tlv));
1340 			return -EINVAL;
1341 		}
1342 		tlv = (struct htt_tlv *)ptr;
1343 		tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
1344 		tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
1345 		ptr += sizeof(*tlv);
1346 		len -= sizeof(*tlv);
1347 
1348 		if (tlv_len > len) {
1349 			ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1350 				   tlv_tag, ptr - begin, len, tlv_len);
1351 			return -EINVAL;
1352 		}
1353 		ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1354 		if (ret == -ENOMEM)
1355 			return ret;
1356 
1357 		ptr += tlv_len;
1358 		len -= tlv_len;
1359 	}
1360 	return 0;
1361 }
1362 
1363 static void
ath11k_update_per_peer_tx_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1364 ath11k_update_per_peer_tx_stats(struct ath11k *ar,
1365 				struct htt_ppdu_stats *ppdu_stats, u8 user)
1366 {
1367 	struct ath11k_base *ab = ar->ab;
1368 	struct ath11k_peer *peer;
1369 	struct ieee80211_sta *sta;
1370 	struct ath11k_sta *arsta;
1371 	struct htt_ppdu_stats_user_rate *user_rate;
1372 	struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1373 	struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1374 	struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1375 	int ret;
1376 	u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1377 	u32 succ_bytes = 0;
1378 	u16 rate = 0, succ_pkts = 0;
1379 	u32 tx_duration = 0;
1380 	u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1381 	bool is_ampdu = false;
1382 
1383 	if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1384 		return;
1385 
1386 	if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1387 		is_ampdu =
1388 			HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1389 
1390 	if (usr_stats->tlv_flags &
1391 	    BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1392 		succ_bytes = usr_stats->ack_ba.success_bytes;
1393 		succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
1394 				      usr_stats->ack_ba.info);
1395 		tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
1396 				usr_stats->ack_ba.info);
1397 	}
1398 
1399 	if (common->fes_duration_us)
1400 		tx_duration = common->fes_duration_us;
1401 
1402 	user_rate = &usr_stats->rate;
1403 	flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1404 	bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1405 	nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1406 	mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1407 	sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1408 	dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1409 
1410 	/* Note: If host configured fixed rates and in some other special
1411 	 * cases, the broadcast/management frames are sent in different rates.
1412 	 * Firmware rate's control to be skipped for this?
1413 	 */
1414 
1415 	if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
1416 		ath11k_warn(ab, "Invalid HE mcs %d peer stats",  mcs);
1417 		return;
1418 	}
1419 
1420 	if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
1421 		ath11k_warn(ab, "Invalid VHT mcs %d peer stats",  mcs);
1422 		return;
1423 	}
1424 
1425 	if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
1426 		ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1427 			    mcs, nss);
1428 		return;
1429 	}
1430 
1431 	if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1432 		ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
1433 							    flags,
1434 							    &rate_idx,
1435 							    &rate);
1436 		if (ret < 0)
1437 			return;
1438 	}
1439 
1440 	rcu_read_lock();
1441 	spin_lock_bh(&ab->base_lock);
1442 	peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
1443 
1444 	if (!peer || !peer->sta) {
1445 		spin_unlock_bh(&ab->base_lock);
1446 		rcu_read_unlock();
1447 		return;
1448 	}
1449 
1450 	sta = peer->sta;
1451 	arsta = ath11k_sta_to_arsta(sta);
1452 
1453 	memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1454 
1455 	switch (flags) {
1456 	case WMI_RATE_PREAMBLE_OFDM:
1457 		arsta->txrate.legacy = rate;
1458 		break;
1459 	case WMI_RATE_PREAMBLE_CCK:
1460 		arsta->txrate.legacy = rate;
1461 		break;
1462 	case WMI_RATE_PREAMBLE_HT:
1463 		arsta->txrate.mcs = mcs + 8 * (nss - 1);
1464 		arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1465 		if (sgi)
1466 			arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1467 		break;
1468 	case WMI_RATE_PREAMBLE_VHT:
1469 		arsta->txrate.mcs = mcs;
1470 		arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1471 		if (sgi)
1472 			arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1473 		break;
1474 	case WMI_RATE_PREAMBLE_HE:
1475 		arsta->txrate.mcs = mcs;
1476 		arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1477 		arsta->txrate.he_dcm = dcm;
1478 		arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
1479 		arsta->txrate.he_ru_alloc = ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc
1480 						((user_rate->ru_end -
1481 						 user_rate->ru_start) + 1);
1482 		break;
1483 	}
1484 
1485 	arsta->txrate.nss = nss;
1486 
1487 	arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
1488 	arsta->tx_duration += tx_duration;
1489 	memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1490 
1491 	/* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1492 	 * So skip peer stats update for mgmt packets.
1493 	 */
1494 	if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1495 		memset(peer_stats, 0, sizeof(*peer_stats));
1496 		peer_stats->succ_pkts = succ_pkts;
1497 		peer_stats->succ_bytes = succ_bytes;
1498 		peer_stats->is_ampdu = is_ampdu;
1499 		peer_stats->duration = tx_duration;
1500 		peer_stats->ba_fails =
1501 			HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1502 			HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1503 
1504 		if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
1505 			ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
1506 	}
1507 
1508 	spin_unlock_bh(&ab->base_lock);
1509 	rcu_read_unlock();
1510 }
1511 
ath11k_htt_update_ppdu_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats)1512 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
1513 					 struct htt_ppdu_stats *ppdu_stats)
1514 {
1515 	u8 user;
1516 
1517 	for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1518 		ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1519 }
1520 
1521 static
ath11k_dp_htt_get_ppdu_desc(struct ath11k * ar,u32 ppdu_id)1522 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
1523 							u32 ppdu_id)
1524 {
1525 	struct htt_ppdu_stats_info *ppdu_info;
1526 
1527 	lockdep_assert_held(&ar->data_lock);
1528 
1529 	if (!list_empty(&ar->ppdu_stats_info)) {
1530 		list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1531 			if (ppdu_info->ppdu_id == ppdu_id)
1532 				return ppdu_info;
1533 		}
1534 
1535 		if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1536 			ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1537 						     typeof(*ppdu_info), list);
1538 			list_del(&ppdu_info->list);
1539 			ar->ppdu_stat_list_depth--;
1540 			ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1541 			kfree(ppdu_info);
1542 		}
1543 	}
1544 
1545 	ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1546 	if (!ppdu_info)
1547 		return NULL;
1548 
1549 	list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1550 	ar->ppdu_stat_list_depth++;
1551 
1552 	return ppdu_info;
1553 }
1554 
ath11k_htt_pull_ppdu_stats(struct ath11k_base * ab,struct sk_buff * skb)1555 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
1556 				      struct sk_buff *skb)
1557 {
1558 	struct ath11k_htt_ppdu_stats_msg *msg;
1559 	struct htt_ppdu_stats_info *ppdu_info;
1560 	struct ath11k *ar;
1561 	int ret;
1562 	u8 pdev_id;
1563 	u32 ppdu_id, len;
1564 
1565 	msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
1566 	len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
1567 	pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
1568 	ppdu_id = msg->ppdu_id;
1569 
1570 	rcu_read_lock();
1571 	ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1572 	if (!ar) {
1573 		ret = -EINVAL;
1574 		goto out;
1575 	}
1576 
1577 	if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
1578 		trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
1579 
1580 	spin_lock_bh(&ar->data_lock);
1581 	ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1582 	if (!ppdu_info) {
1583 		ret = -EINVAL;
1584 		goto out_unlock_data;
1585 	}
1586 
1587 	ppdu_info->ppdu_id = ppdu_id;
1588 	ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
1589 				     ath11k_htt_tlv_ppdu_stats_parse,
1590 				     (void *)ppdu_info);
1591 	if (ret) {
1592 		ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
1593 		goto out_unlock_data;
1594 	}
1595 
1596 out_unlock_data:
1597 	spin_unlock_bh(&ar->data_lock);
1598 
1599 out:
1600 	rcu_read_unlock();
1601 
1602 	return ret;
1603 }
1604 
ath11k_htt_pktlog(struct ath11k_base * ab,struct sk_buff * skb)1605 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
1606 {
1607 	struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
1608 	struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
1609 	struct ath11k *ar;
1610 	u8 pdev_id;
1611 
1612 	pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
1613 
1614 	rcu_read_lock();
1615 
1616 	ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1617 	if (!ar) {
1618 		ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
1619 		goto out;
1620 	}
1621 
1622 	trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
1623 				ar->ab->pktlog_defs_checksum);
1624 
1625 out:
1626 	rcu_read_unlock();
1627 }
1628 
ath11k_htt_backpressure_event_handler(struct ath11k_base * ab,struct sk_buff * skb)1629 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
1630 						  struct sk_buff *skb)
1631 {
1632 	u32 *data = (u32 *)skb->data;
1633 	u8 pdev_id, ring_type, ring_id, pdev_idx;
1634 	u16 hp, tp;
1635 	u32 backpressure_time;
1636 	struct ath11k_bp_stats *bp_stats;
1637 
1638 	pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
1639 	ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
1640 	ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
1641 	++data;
1642 
1643 	hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
1644 	tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
1645 	++data;
1646 
1647 	backpressure_time = *data;
1648 
1649 	ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
1650 		   pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
1651 
1652 	if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
1653 		if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
1654 			return;
1655 
1656 		bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
1657 	} else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
1658 		pdev_idx = DP_HW2SW_MACID(pdev_id);
1659 
1660 		if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
1661 			return;
1662 
1663 		bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
1664 	} else {
1665 		ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
1666 			    ring_type);
1667 		return;
1668 	}
1669 
1670 	spin_lock_bh(&ab->base_lock);
1671 	bp_stats->hp = hp;
1672 	bp_stats->tp = tp;
1673 	bp_stats->count++;
1674 	bp_stats->jiffies = jiffies;
1675 	spin_unlock_bh(&ab->base_lock);
1676 }
1677 
ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base * ab,struct sk_buff * skb)1678 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
1679 				       struct sk_buff *skb)
1680 {
1681 	struct ath11k_dp *dp = &ab->dp;
1682 	struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1683 	enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
1684 	u16 peer_id;
1685 	u8 vdev_id;
1686 	u8 mac_addr[ETH_ALEN];
1687 	u16 peer_mac_h16;
1688 	u16 ast_hash;
1689 	u16 hw_peer_id;
1690 
1691 	ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1692 
1693 	switch (type) {
1694 	case HTT_T2H_MSG_TYPE_VERSION_CONF:
1695 		dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
1696 						  resp->version_msg.version);
1697 		dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
1698 						  resp->version_msg.version);
1699 		complete(&dp->htt_tgt_version_received);
1700 		break;
1701 	case HTT_T2H_MSG_TYPE_PEER_MAP:
1702 		vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1703 				    resp->peer_map_ev.info);
1704 		peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1705 				    resp->peer_map_ev.info);
1706 		peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1707 					 resp->peer_map_ev.info1);
1708 		ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1709 				       peer_mac_h16, mac_addr);
1710 		ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1711 		break;
1712 	case HTT_T2H_MSG_TYPE_PEER_MAP2:
1713 		vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1714 				    resp->peer_map_ev.info);
1715 		peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1716 				    resp->peer_map_ev.info);
1717 		peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1718 					 resp->peer_map_ev.info1);
1719 		ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1720 				       peer_mac_h16, mac_addr);
1721 		ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
1722 				     resp->peer_map_ev.info2);
1723 		hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID,
1724 				       resp->peer_map_ev.info1);
1725 		ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1726 				      hw_peer_id);
1727 		break;
1728 	case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1729 	case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1730 		peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
1731 				    resp->peer_unmap_ev.info);
1732 		ath11k_peer_unmap_event(ab, peer_id);
1733 		break;
1734 	case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1735 		ath11k_htt_pull_ppdu_stats(ab, skb);
1736 		break;
1737 	case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1738 		ath11k_debugfs_htt_ext_stats_handler(ab, skb);
1739 		break;
1740 	case HTT_T2H_MSG_TYPE_PKTLOG:
1741 		ath11k_htt_pktlog(ab, skb);
1742 		break;
1743 	case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
1744 		ath11k_htt_backpressure_event_handler(ab, skb);
1745 		break;
1746 	default:
1747 		ath11k_warn(ab, "htt event %d not handled\n", type);
1748 		break;
1749 	}
1750 
1751 	dev_kfree_skb_any(skb);
1752 }
1753 
ath11k_dp_rx_msdu_coalesce(struct ath11k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1754 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
1755 				      struct sk_buff_head *msdu_list,
1756 				      struct sk_buff *first, struct sk_buff *last,
1757 				      u8 l3pad_bytes, int msdu_len)
1758 {
1759 	struct ath11k_base *ab = ar->ab;
1760 	struct sk_buff *skb;
1761 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1762 	int buf_first_hdr_len, buf_first_len;
1763 	struct hal_rx_desc *ldesc;
1764 	int space_extra, rem_len, buf_len;
1765 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
1766 
1767 	/* As the msdu is spread across multiple rx buffers,
1768 	 * find the offset to the start of msdu for computing
1769 	 * the length of the msdu in the first buffer.
1770 	 */
1771 	buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1772 	buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1773 
1774 	if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1775 		skb_put(first, buf_first_hdr_len + msdu_len);
1776 		skb_pull(first, buf_first_hdr_len);
1777 		return 0;
1778 	}
1779 
1780 	ldesc = (struct hal_rx_desc *)last->data;
1781 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc);
1782 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc);
1783 
1784 	/* MSDU spans over multiple buffers because the length of the MSDU
1785 	 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1786 	 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1787 	 */
1788 	skb_put(first, DP_RX_BUFFER_SIZE);
1789 	skb_pull(first, buf_first_hdr_len);
1790 
1791 	/* When an MSDU spread over multiple buffers attention, MSDU_END and
1792 	 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
1793 	 */
1794 	ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1795 
1796 	space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1797 	if (space_extra > 0 &&
1798 	    (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1799 		/* Free up all buffers of the MSDU */
1800 		while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1801 			rxcb = ATH11K_SKB_RXCB(skb);
1802 			if (!rxcb->is_continuation) {
1803 				dev_kfree_skb_any(skb);
1804 				break;
1805 			}
1806 			dev_kfree_skb_any(skb);
1807 		}
1808 		return -ENOMEM;
1809 	}
1810 
1811 	rem_len = msdu_len - buf_first_len;
1812 	while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1813 		rxcb = ATH11K_SKB_RXCB(skb);
1814 		if (rxcb->is_continuation)
1815 			buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1816 		else
1817 			buf_len = rem_len;
1818 
1819 		if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1820 			WARN_ON_ONCE(1);
1821 			dev_kfree_skb_any(skb);
1822 			return -EINVAL;
1823 		}
1824 
1825 		skb_put(skb, buf_len + hal_rx_desc_sz);
1826 		skb_pull(skb, hal_rx_desc_sz);
1827 		skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1828 					  buf_len);
1829 		dev_kfree_skb_any(skb);
1830 
1831 		rem_len -= buf_len;
1832 		if (!rxcb->is_continuation)
1833 			break;
1834 	}
1835 
1836 	return 0;
1837 }
1838 
ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1839 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1840 						      struct sk_buff *first)
1841 {
1842 	struct sk_buff *skb;
1843 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1844 
1845 	if (!rxcb->is_continuation)
1846 		return first;
1847 
1848 	skb_queue_walk(msdu_list, skb) {
1849 		rxcb = ATH11K_SKB_RXCB(skb);
1850 		if (!rxcb->is_continuation)
1851 			return skb;
1852 	}
1853 
1854 	return NULL;
1855 }
1856 
ath11k_dp_rx_h_csum_offload(struct ath11k * ar,struct sk_buff * msdu)1857 static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu)
1858 {
1859 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1860 	struct rx_attention *rx_attention;
1861 	bool ip_csum_fail, l4_csum_fail;
1862 
1863 	rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc);
1864 	ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention);
1865 	l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention);
1866 
1867 	msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1868 			  CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1869 }
1870 
ath11k_dp_rx_crypto_mic_len(struct ath11k * ar,enum hal_encrypt_type enctype)1871 int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar, enum hal_encrypt_type enctype)
1872 {
1873 	switch (enctype) {
1874 	case HAL_ENCRYPT_TYPE_OPEN:
1875 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1876 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1877 		return 0;
1878 	case HAL_ENCRYPT_TYPE_CCMP_128:
1879 		return IEEE80211_CCMP_MIC_LEN;
1880 	case HAL_ENCRYPT_TYPE_CCMP_256:
1881 		return IEEE80211_CCMP_256_MIC_LEN;
1882 	case HAL_ENCRYPT_TYPE_GCMP_128:
1883 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1884 		return IEEE80211_GCMP_MIC_LEN;
1885 	case HAL_ENCRYPT_TYPE_WEP_40:
1886 	case HAL_ENCRYPT_TYPE_WEP_104:
1887 	case HAL_ENCRYPT_TYPE_WEP_128:
1888 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1889 	case HAL_ENCRYPT_TYPE_WAPI:
1890 		break;
1891 	}
1892 
1893 	ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1894 	return 0;
1895 }
1896 
ath11k_dp_rx_crypto_param_len(struct ath11k * ar,enum hal_encrypt_type enctype)1897 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
1898 					 enum hal_encrypt_type enctype)
1899 {
1900 	switch (enctype) {
1901 	case HAL_ENCRYPT_TYPE_OPEN:
1902 		return 0;
1903 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1904 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1905 		return IEEE80211_TKIP_IV_LEN;
1906 	case HAL_ENCRYPT_TYPE_CCMP_128:
1907 		return IEEE80211_CCMP_HDR_LEN;
1908 	case HAL_ENCRYPT_TYPE_CCMP_256:
1909 		return IEEE80211_CCMP_256_HDR_LEN;
1910 	case HAL_ENCRYPT_TYPE_GCMP_128:
1911 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1912 		return IEEE80211_GCMP_HDR_LEN;
1913 	case HAL_ENCRYPT_TYPE_WEP_40:
1914 	case HAL_ENCRYPT_TYPE_WEP_104:
1915 	case HAL_ENCRYPT_TYPE_WEP_128:
1916 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1917 	case HAL_ENCRYPT_TYPE_WAPI:
1918 		break;
1919 	}
1920 
1921 	ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1922 	return 0;
1923 }
1924 
ath11k_dp_rx_crypto_icv_len(struct ath11k * ar,enum hal_encrypt_type enctype)1925 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
1926 				       enum hal_encrypt_type enctype)
1927 {
1928 	switch (enctype) {
1929 	case HAL_ENCRYPT_TYPE_OPEN:
1930 	case HAL_ENCRYPT_TYPE_CCMP_128:
1931 	case HAL_ENCRYPT_TYPE_CCMP_256:
1932 	case HAL_ENCRYPT_TYPE_GCMP_128:
1933 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1934 		return 0;
1935 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1936 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1937 		return IEEE80211_TKIP_ICV_LEN;
1938 	case HAL_ENCRYPT_TYPE_WEP_40:
1939 	case HAL_ENCRYPT_TYPE_WEP_104:
1940 	case HAL_ENCRYPT_TYPE_WEP_128:
1941 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1942 	case HAL_ENCRYPT_TYPE_WAPI:
1943 		break;
1944 	}
1945 
1946 	ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1947 	return 0;
1948 }
1949 
ath11k_dp_rx_h_undecap_nwifi(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)1950 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
1951 					 struct sk_buff *msdu,
1952 					 u8 *first_hdr,
1953 					 enum hal_encrypt_type enctype,
1954 					 struct ieee80211_rx_status *status)
1955 {
1956 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1957 	u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1958 	struct ieee80211_hdr *hdr;
1959 	size_t hdr_len;
1960 	u8 da[ETH_ALEN];
1961 	u8 sa[ETH_ALEN];
1962 	u16 qos_ctl = 0;
1963 	u8 *qos;
1964 
1965 	/* copy SA & DA and pull decapped header */
1966 	hdr = (struct ieee80211_hdr *)msdu->data;
1967 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
1968 	ether_addr_copy(da, ieee80211_get_DA(hdr));
1969 	ether_addr_copy(sa, ieee80211_get_SA(hdr));
1970 	skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
1971 
1972 	if (rxcb->is_first_msdu) {
1973 		/* original 802.11 header is valid for the first msdu
1974 		 * hence we can reuse the same header
1975 		 */
1976 		hdr = (struct ieee80211_hdr *)first_hdr;
1977 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
1978 
1979 		/* Each A-MSDU subframe will be reported as a separate MSDU,
1980 		 * so strip the A-MSDU bit from QoS Ctl.
1981 		 */
1982 		if (ieee80211_is_data_qos(hdr->frame_control)) {
1983 			qos = ieee80211_get_qos_ctl(hdr);
1984 			qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
1985 		}
1986 	} else {
1987 		/*  Rebuild qos header if this is a middle/last msdu */
1988 		hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
1989 
1990 		/* Reset the order bit as the HT_Control header is stripped */
1991 		hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
1992 
1993 		qos_ctl = rxcb->tid;
1994 
1995 		if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc))
1996 			qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
1997 
1998 		/* TODO Add other QoS ctl fields when required */
1999 
2000 		/* copy decap header before overwriting for reuse below */
2001 		memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
2002 	}
2003 
2004 	if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2005 		memcpy(skb_push(msdu,
2006 				ath11k_dp_rx_crypto_param_len(ar, enctype)),
2007 		       (void *)hdr + hdr_len,
2008 		       ath11k_dp_rx_crypto_param_len(ar, enctype));
2009 	}
2010 
2011 	if (!rxcb->is_first_msdu) {
2012 		memcpy(skb_push(msdu,
2013 				IEEE80211_QOS_CTL_LEN), &qos_ctl,
2014 				IEEE80211_QOS_CTL_LEN);
2015 		memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
2016 		return;
2017 	}
2018 
2019 	memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2020 
2021 	/* original 802.11 header has a different DA and in
2022 	 * case of 4addr it may also have different SA
2023 	 */
2024 	hdr = (struct ieee80211_hdr *)msdu->data;
2025 	ether_addr_copy(ieee80211_get_DA(hdr), da);
2026 	ether_addr_copy(ieee80211_get_SA(hdr), sa);
2027 }
2028 
ath11k_dp_rx_h_undecap_raw(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2029 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
2030 				       enum hal_encrypt_type enctype,
2031 				       struct ieee80211_rx_status *status,
2032 				       bool decrypted)
2033 {
2034 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2035 	struct ieee80211_hdr *hdr;
2036 	size_t hdr_len;
2037 	size_t crypto_len;
2038 
2039 	if (!rxcb->is_first_msdu ||
2040 	    !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2041 		WARN_ON_ONCE(1);
2042 		return;
2043 	}
2044 
2045 	skb_trim(msdu, msdu->len - FCS_LEN);
2046 
2047 	if (!decrypted)
2048 		return;
2049 
2050 	hdr = (void *)msdu->data;
2051 
2052 	/* Tail */
2053 	if (status->flag & RX_FLAG_IV_STRIPPED) {
2054 		skb_trim(msdu, msdu->len -
2055 			 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2056 
2057 		skb_trim(msdu, msdu->len -
2058 			 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2059 	} else {
2060 		/* MIC */
2061 		if (status->flag & RX_FLAG_MIC_STRIPPED)
2062 			skb_trim(msdu, msdu->len -
2063 				 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2064 
2065 		/* ICV */
2066 		if (status->flag & RX_FLAG_ICV_STRIPPED)
2067 			skb_trim(msdu, msdu->len -
2068 				 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2069 	}
2070 
2071 	/* MMIC */
2072 	if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2073 	    !ieee80211_has_morefrags(hdr->frame_control) &&
2074 	    enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2075 		skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2076 
2077 	/* Head */
2078 	if (status->flag & RX_FLAG_IV_STRIPPED) {
2079 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
2080 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2081 
2082 		memmove((void *)msdu->data + crypto_len,
2083 			(void *)msdu->data, hdr_len);
2084 		skb_pull(msdu, crypto_len);
2085 	}
2086 }
2087 
ath11k_dp_rx_h_find_rfc1042(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype)2088 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
2089 					 struct sk_buff *msdu,
2090 					 enum hal_encrypt_type enctype)
2091 {
2092 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2093 	struct ieee80211_hdr *hdr;
2094 	size_t hdr_len, crypto_len;
2095 	void *rfc1042;
2096 	bool is_amsdu;
2097 
2098 	is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
2099 	hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc);
2100 	rfc1042 = hdr;
2101 
2102 	if (rxcb->is_first_msdu) {
2103 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
2104 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2105 
2106 		rfc1042 += hdr_len + crypto_len;
2107 	}
2108 
2109 	if (is_amsdu)
2110 		rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
2111 
2112 	return rfc1042;
2113 }
2114 
ath11k_dp_rx_h_undecap_eth(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2115 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
2116 				       struct sk_buff *msdu,
2117 				       u8 *first_hdr,
2118 				       enum hal_encrypt_type enctype,
2119 				       struct ieee80211_rx_status *status)
2120 {
2121 	struct ieee80211_hdr *hdr;
2122 	struct ethhdr *eth;
2123 	size_t hdr_len;
2124 	u8 da[ETH_ALEN];
2125 	u8 sa[ETH_ALEN];
2126 	void *rfc1042;
2127 
2128 	rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
2129 	if (WARN_ON_ONCE(!rfc1042))
2130 		return;
2131 
2132 	/* pull decapped header and copy SA & DA */
2133 	eth = (struct ethhdr *)msdu->data;
2134 	ether_addr_copy(da, eth->h_dest);
2135 	ether_addr_copy(sa, eth->h_source);
2136 	skb_pull(msdu, sizeof(struct ethhdr));
2137 
2138 	/* push rfc1042/llc/snap */
2139 	memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
2140 	       sizeof(struct ath11k_dp_rfc1042_hdr));
2141 
2142 	/* push original 802.11 header */
2143 	hdr = (struct ieee80211_hdr *)first_hdr;
2144 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
2145 
2146 	if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2147 		memcpy(skb_push(msdu,
2148 				ath11k_dp_rx_crypto_param_len(ar, enctype)),
2149 		       (void *)hdr + hdr_len,
2150 		       ath11k_dp_rx_crypto_param_len(ar, enctype));
2151 	}
2152 
2153 	memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2154 
2155 	/* original 802.11 header has a different DA and in
2156 	 * case of 4addr it may also have different SA
2157 	 */
2158 	hdr = (struct ieee80211_hdr *)msdu->data;
2159 	ether_addr_copy(ieee80211_get_DA(hdr), da);
2160 	ether_addr_copy(ieee80211_get_SA(hdr), sa);
2161 }
2162 
ath11k_dp_rx_h_undecap(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2163 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
2164 				   struct hal_rx_desc *rx_desc,
2165 				   enum hal_encrypt_type enctype,
2166 				   struct ieee80211_rx_status *status,
2167 				   bool decrypted)
2168 {
2169 	u8 *first_hdr;
2170 	u8 decap;
2171 	struct ethhdr *ehdr;
2172 
2173 	first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
2174 	decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc);
2175 
2176 	switch (decap) {
2177 	case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2178 		ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
2179 					     enctype, status);
2180 		break;
2181 	case DP_RX_DECAP_TYPE_RAW:
2182 		ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2183 					   decrypted);
2184 		break;
2185 	case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2186 		ehdr = (struct ethhdr *)msdu->data;
2187 
2188 		/* mac80211 allows fast path only for authorized STA */
2189 		if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
2190 			ATH11K_SKB_RXCB(msdu)->is_eapol = true;
2191 			ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2192 						   enctype, status);
2193 			break;
2194 		}
2195 
2196 		/* PN for mcast packets will be validated in mac80211;
2197 		 * remove eth header and add 802.11 header.
2198 		 */
2199 		if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted)
2200 			ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2201 						   enctype, status);
2202 		break;
2203 	case DP_RX_DECAP_TYPE_8023:
2204 		/* TODO: Handle undecap for these formats */
2205 		break;
2206 	}
2207 }
2208 
2209 static struct ath11k_peer *
ath11k_dp_rx_h_find_peer(struct ath11k_base * ab,struct sk_buff * msdu)2210 ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu)
2211 {
2212 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2213 	struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2214 	struct ath11k_peer *peer = NULL;
2215 
2216 	lockdep_assert_held(&ab->base_lock);
2217 
2218 	if (rxcb->peer_id)
2219 		peer = ath11k_peer_find_by_id(ab, rxcb->peer_id);
2220 
2221 	if (peer)
2222 		return peer;
2223 
2224 	if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
2225 		return NULL;
2226 
2227 	peer = ath11k_peer_find_by_addr(ab,
2228 					ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc));
2229 	return peer;
2230 }
2231 
ath11k_dp_rx_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2232 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
2233 				struct sk_buff *msdu,
2234 				struct hal_rx_desc *rx_desc,
2235 				struct ieee80211_rx_status *rx_status)
2236 {
2237 	bool  fill_crypto_hdr;
2238 	enum hal_encrypt_type enctype;
2239 	bool is_decrypted = false;
2240 	struct ath11k_skb_rxcb *rxcb;
2241 	struct ieee80211_hdr *hdr;
2242 	struct ath11k_peer *peer;
2243 	struct rx_attention *rx_attention;
2244 	u32 err_bitmap;
2245 
2246 	/* PN for multicast packets will be checked in mac80211 */
2247 	rxcb = ATH11K_SKB_RXCB(msdu);
2248 	fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
2249 	rxcb->is_mcbc = fill_crypto_hdr;
2250 
2251 	if (rxcb->is_mcbc) {
2252 		rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
2253 		rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
2254 	}
2255 
2256 	spin_lock_bh(&ar->ab->base_lock);
2257 	peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2258 	if (peer) {
2259 		if (rxcb->is_mcbc)
2260 			enctype = peer->sec_type_grp;
2261 		else
2262 			enctype = peer->sec_type;
2263 	} else {
2264 		enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
2265 	}
2266 	spin_unlock_bh(&ar->ab->base_lock);
2267 
2268 	rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
2269 	err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
2270 	if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2271 		is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
2272 
2273 	/* Clear per-MPDU flags while leaving per-PPDU flags intact */
2274 	rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2275 			     RX_FLAG_MMIC_ERROR |
2276 			     RX_FLAG_DECRYPTED |
2277 			     RX_FLAG_IV_STRIPPED |
2278 			     RX_FLAG_MMIC_STRIPPED);
2279 
2280 	if (err_bitmap & DP_RX_MPDU_ERR_FCS)
2281 		rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2282 	if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
2283 		rx_status->flag |= RX_FLAG_MMIC_ERROR;
2284 
2285 	if (is_decrypted) {
2286 		rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2287 
2288 		if (fill_crypto_hdr)
2289 			rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2290 					RX_FLAG_ICV_STRIPPED;
2291 		else
2292 			rx_status->flag |= RX_FLAG_IV_STRIPPED |
2293 					   RX_FLAG_PN_VALIDATED;
2294 	}
2295 
2296 	ath11k_dp_rx_h_csum_offload(ar, msdu);
2297 	ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
2298 			       enctype, rx_status, is_decrypted);
2299 
2300 	if (!is_decrypted || fill_crypto_hdr)
2301 		return;
2302 
2303 	if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) !=
2304 	    DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
2305 		hdr = (void *)msdu->data;
2306 		hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2307 	}
2308 }
2309 
ath11k_dp_rx_h_rate(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2310 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2311 				struct ieee80211_rx_status *rx_status)
2312 {
2313 	struct ieee80211_supported_band *sband;
2314 	enum rx_msdu_start_pkt_type pkt_type;
2315 	u8 bw;
2316 	u8 rate_mcs, nss;
2317 	u8 sgi;
2318 	bool is_cck, is_ldpc;
2319 
2320 	pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc);
2321 	bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc);
2322 	rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc);
2323 	nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc);
2324 	sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc);
2325 
2326 	switch (pkt_type) {
2327 	case RX_MSDU_START_PKT_TYPE_11A:
2328 	case RX_MSDU_START_PKT_TYPE_11B:
2329 		is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2330 		sband = &ar->mac.sbands[rx_status->band];
2331 		rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
2332 								is_cck);
2333 		break;
2334 	case RX_MSDU_START_PKT_TYPE_11N:
2335 		rx_status->encoding = RX_ENC_HT;
2336 		if (rate_mcs > ATH11K_HT_MCS_MAX) {
2337 			ath11k_warn(ar->ab,
2338 				    "Received with invalid mcs in HT mode %d\n",
2339 				     rate_mcs);
2340 			break;
2341 		}
2342 		rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2343 		if (sgi)
2344 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2345 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2346 		break;
2347 	case RX_MSDU_START_PKT_TYPE_11AC:
2348 		rx_status->encoding = RX_ENC_VHT;
2349 		rx_status->rate_idx = rate_mcs;
2350 		if (rate_mcs > ATH11K_VHT_MCS_MAX) {
2351 			ath11k_warn(ar->ab,
2352 				    "Received with invalid mcs in VHT mode %d\n",
2353 				     rate_mcs);
2354 			break;
2355 		}
2356 		rx_status->nss = nss;
2357 		if (sgi)
2358 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2359 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2360 		is_ldpc = ath11k_dp_rx_h_msdu_start_ldpc_support(ar->ab, rx_desc);
2361 		if (is_ldpc)
2362 			rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
2363 		break;
2364 	case RX_MSDU_START_PKT_TYPE_11AX:
2365 		rx_status->rate_idx = rate_mcs;
2366 		if (rate_mcs > ATH11K_HE_MCS_MAX) {
2367 			ath11k_warn(ar->ab,
2368 				    "Received with invalid mcs in HE mode %d\n",
2369 				    rate_mcs);
2370 			break;
2371 		}
2372 		rx_status->encoding = RX_ENC_HE;
2373 		rx_status->nss = nss;
2374 		rx_status->he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
2375 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2376 		break;
2377 	}
2378 }
2379 
ath11k_dp_rx_h_ppdu(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2380 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2381 				struct ieee80211_rx_status *rx_status)
2382 {
2383 	u8 channel_num;
2384 	u32 center_freq, meta_data;
2385 	struct ieee80211_channel *channel;
2386 
2387 	rx_status->freq = 0;
2388 	rx_status->rate_idx = 0;
2389 	rx_status->nss = 0;
2390 	rx_status->encoding = RX_ENC_LEGACY;
2391 	rx_status->bw = RATE_INFO_BW_20;
2392 
2393 	rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2394 
2395 	meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc);
2396 	channel_num = meta_data;
2397 	center_freq = meta_data >> 16;
2398 
2399 	if (center_freq >= ATH11K_MIN_6G_FREQ &&
2400 	    center_freq <= ATH11K_MAX_6G_FREQ) {
2401 		rx_status->band = NL80211_BAND_6GHZ;
2402 		rx_status->freq = center_freq;
2403 	} else if (channel_num >= 1 && channel_num <= 14) {
2404 		rx_status->band = NL80211_BAND_2GHZ;
2405 	} else if (channel_num >= 36 && channel_num <= 177) {
2406 		rx_status->band = NL80211_BAND_5GHZ;
2407 	} else {
2408 		spin_lock_bh(&ar->data_lock);
2409 		channel = ar->rx_channel;
2410 		if (channel) {
2411 			rx_status->band = channel->band;
2412 			channel_num =
2413 				ieee80211_frequency_to_channel(channel->center_freq);
2414 		}
2415 		spin_unlock_bh(&ar->data_lock);
2416 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
2417 				rx_desc, sizeof(struct hal_rx_desc));
2418 	}
2419 
2420 	if (rx_status->band != NL80211_BAND_6GHZ)
2421 		rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2422 								 rx_status->band);
2423 
2424 	ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
2425 }
2426 
ath11k_dp_rx_deliver_msdu(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)2427 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
2428 				      struct sk_buff *msdu,
2429 				      struct ieee80211_rx_status *status)
2430 {
2431 	static const struct ieee80211_radiotap_he known = {
2432 		.data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2433 				     IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2434 		.data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2435 	};
2436 	struct ieee80211_rx_status *rx_status;
2437 	struct ieee80211_radiotap_he *he = NULL;
2438 	struct ieee80211_sta *pubsta = NULL;
2439 	struct ath11k_peer *peer;
2440 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2441 	u8 decap = DP_RX_DECAP_TYPE_RAW;
2442 	bool is_mcbc = rxcb->is_mcbc;
2443 	bool is_eapol = rxcb->is_eapol;
2444 
2445 	if (status->encoding == RX_ENC_HE &&
2446 	    !(status->flag & RX_FLAG_RADIOTAP_HE) &&
2447 	    !(status->flag & RX_FLAG_SKIP_MONITOR)) {
2448 		he = skb_push(msdu, sizeof(known));
2449 		memcpy(he, &known, sizeof(known));
2450 		status->flag |= RX_FLAG_RADIOTAP_HE;
2451 	}
2452 
2453 	if (!(status->flag & RX_FLAG_ONLY_MONITOR))
2454 		decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc);
2455 
2456 	spin_lock_bh(&ar->ab->base_lock);
2457 	peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2458 	if (peer && peer->sta)
2459 		pubsta = peer->sta;
2460 	spin_unlock_bh(&ar->ab->base_lock);
2461 
2462 	ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
2463 		   "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2464 		   msdu,
2465 		   msdu->len,
2466 		   peer ? peer->addr : NULL,
2467 		   rxcb->tid,
2468 		   is_mcbc ? "mcast" : "ucast",
2469 		   rxcb->seq_no,
2470 		   (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2471 		   (status->encoding == RX_ENC_HT) ? "ht" : "",
2472 		   (status->encoding == RX_ENC_VHT) ? "vht" : "",
2473 		   (status->encoding == RX_ENC_HE) ? "he" : "",
2474 		   (status->bw == RATE_INFO_BW_40) ? "40" : "",
2475 		   (status->bw == RATE_INFO_BW_80) ? "80" : "",
2476 		   (status->bw == RATE_INFO_BW_160) ? "160" : "",
2477 		   status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2478 		   status->rate_idx,
2479 		   status->nss,
2480 		   status->freq,
2481 		   status->band, status->flag,
2482 		   !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2483 		   !!(status->flag & RX_FLAG_MMIC_ERROR),
2484 		   !!(status->flag & RX_FLAG_AMSDU_MORE));
2485 
2486 	ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
2487 			msdu->data, msdu->len);
2488 
2489 	rx_status = IEEE80211_SKB_RXCB(msdu);
2490 	*rx_status = *status;
2491 
2492 	/* TODO: trace rx packet */
2493 
2494 	/* PN for multicast packets are not validate in HW,
2495 	 * so skip 802.3 rx path
2496 	 * Also, fast_rx expects the STA to be authorized, hence
2497 	 * eapol packets are sent in slow path.
2498 	 */
2499 	if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
2500 	    !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2501 		rx_status->flag |= RX_FLAG_8023;
2502 
2503 	ieee80211_rx_napi(ar->hw, pubsta, msdu, napi);
2504 }
2505 
ath11k_dp_rx_process_msdu(struct ath11k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list,struct ieee80211_rx_status * rx_status)2506 static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
2507 				     struct sk_buff *msdu,
2508 				     struct sk_buff_head *msdu_list,
2509 				     struct ieee80211_rx_status *rx_status)
2510 {
2511 	struct ath11k_base *ab = ar->ab;
2512 	struct hal_rx_desc *rx_desc, *lrx_desc;
2513 	struct rx_attention *rx_attention;
2514 	struct ath11k_skb_rxcb *rxcb;
2515 	struct sk_buff *last_buf;
2516 	u8 l3_pad_bytes;
2517 	u8 *hdr_status;
2518 	u16 msdu_len;
2519 	int ret;
2520 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
2521 
2522 	last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2523 	if (!last_buf) {
2524 		ath11k_warn(ab,
2525 			    "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
2526 		ret = -EIO;
2527 		goto free_out;
2528 	}
2529 
2530 	rx_desc = (struct hal_rx_desc *)msdu->data;
2531 	if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) {
2532 		ath11k_warn(ar->ab, "msdu len not valid\n");
2533 		ret = -EIO;
2534 		goto free_out;
2535 	}
2536 
2537 	lrx_desc = (struct hal_rx_desc *)last_buf->data;
2538 	rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc);
2539 	if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
2540 		ath11k_warn(ab, "msdu_done bit in attention is not set\n");
2541 		ret = -EIO;
2542 		goto free_out;
2543 	}
2544 
2545 	rxcb = ATH11K_SKB_RXCB(msdu);
2546 	rxcb->rx_desc = rx_desc;
2547 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc);
2548 	l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc);
2549 
2550 	if (rxcb->is_frag) {
2551 		skb_pull(msdu, hal_rx_desc_sz);
2552 	} else if (!rxcb->is_continuation) {
2553 		if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2554 			hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc);
2555 			ret = -EINVAL;
2556 			ath11k_warn(ab, "invalid msdu len %u\n", msdu_len);
2557 			ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
2558 					sizeof(struct ieee80211_hdr));
2559 			ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
2560 					sizeof(struct hal_rx_desc));
2561 			goto free_out;
2562 		}
2563 		skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2564 		skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2565 	} else {
2566 		ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
2567 						 msdu, last_buf,
2568 						 l3_pad_bytes, msdu_len);
2569 		if (ret) {
2570 			ath11k_warn(ab,
2571 				    "failed to coalesce msdu rx buffer%d\n", ret);
2572 			goto free_out;
2573 		}
2574 	}
2575 
2576 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
2577 	ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
2578 
2579 	rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2580 
2581 	return 0;
2582 
2583 free_out:
2584 	return ret;
2585 }
2586 
ath11k_dp_rx_process_received_packets(struct ath11k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int mac_id)2587 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
2588 						  struct napi_struct *napi,
2589 						  struct sk_buff_head *msdu_list,
2590 						  int mac_id)
2591 {
2592 	struct sk_buff *msdu;
2593 	struct ath11k *ar;
2594 	struct ieee80211_rx_status rx_status = {0};
2595 	int ret;
2596 
2597 	if (skb_queue_empty(msdu_list))
2598 		return;
2599 
2600 	if (unlikely(!rcu_access_pointer(ab->pdevs_active[mac_id]))) {
2601 		__skb_queue_purge(msdu_list);
2602 		return;
2603 	}
2604 
2605 	ar = ab->pdevs[mac_id].ar;
2606 	if (unlikely(test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags))) {
2607 		__skb_queue_purge(msdu_list);
2608 		return;
2609 	}
2610 
2611 	while ((msdu = __skb_dequeue(msdu_list))) {
2612 		ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
2613 		if (unlikely(ret)) {
2614 			ath11k_dbg(ab, ATH11K_DBG_DATA,
2615 				   "Unable to process msdu %d", ret);
2616 			dev_kfree_skb_any(msdu);
2617 			continue;
2618 		}
2619 
2620 		ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
2621 	}
2622 }
2623 
ath11k_dp_process_rx(struct ath11k_base * ab,int ring_id,struct napi_struct * napi,int budget)2624 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
2625 			 struct napi_struct *napi, int budget)
2626 {
2627 	struct ath11k_dp *dp = &ab->dp;
2628 	struct dp_rxdma_ring *rx_ring;
2629 	int num_buffs_reaped[MAX_RADIOS] = {0};
2630 	struct sk_buff_head msdu_list[MAX_RADIOS];
2631 	struct ath11k_skb_rxcb *rxcb;
2632 	int total_msdu_reaped = 0;
2633 	struct hal_srng *srng;
2634 	struct sk_buff *msdu;
2635 	bool done = false;
2636 	int buf_id, mac_id;
2637 	struct ath11k *ar;
2638 	struct hal_reo_dest_ring *desc;
2639 	enum hal_reo_dest_ring_push_reason push_reason;
2640 	u32 cookie, info0, rx_msdu_info0, rx_mpdu_info0;
2641 	int i;
2642 
2643 	for (i = 0; i < MAX_RADIOS; i++)
2644 		__skb_queue_head_init(&msdu_list[i]);
2645 
2646 	srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2647 
2648 	spin_lock_bh(&srng->lock);
2649 
2650 try_again:
2651 	ath11k_hal_srng_access_begin(ab, srng);
2652 
2653 	/* Make sure descriptor is read after the head pointer. */
2654 	dma_rmb();
2655 
2656 	while (likely(desc =
2657 	      (struct hal_reo_dest_ring *)ath11k_hal_srng_dst_get_next_entry(ab,
2658 									     srng))) {
2659 		cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
2660 				   READ_ONCE(desc->buf_addr_info.info1));
2661 		buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
2662 				   cookie);
2663 		mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
2664 
2665 		if (unlikely(buf_id == 0))
2666 			continue;
2667 
2668 		ar = ab->pdevs[mac_id].ar;
2669 		rx_ring = &ar->dp.rx_refill_buf_ring;
2670 		spin_lock_bh(&rx_ring->idr_lock);
2671 		msdu = idr_find(&rx_ring->bufs_idr, buf_id);
2672 		if (unlikely(!msdu)) {
2673 			ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
2674 				    buf_id);
2675 			spin_unlock_bh(&rx_ring->idr_lock);
2676 			continue;
2677 		}
2678 
2679 		idr_remove(&rx_ring->bufs_idr, buf_id);
2680 		spin_unlock_bh(&rx_ring->idr_lock);
2681 
2682 		rxcb = ATH11K_SKB_RXCB(msdu);
2683 		dma_unmap_single(ab->dev, rxcb->paddr,
2684 				 msdu->len + skb_tailroom(msdu),
2685 				 DMA_FROM_DEVICE);
2686 
2687 		num_buffs_reaped[mac_id]++;
2688 
2689 		info0 = READ_ONCE(desc->info0);
2690 		push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
2691 					info0);
2692 		if (unlikely(push_reason !=
2693 			     HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) {
2694 			dev_kfree_skb_any(msdu);
2695 			ab->soc_stats.hal_reo_error[ring_id]++;
2696 			continue;
2697 		}
2698 
2699 		rx_msdu_info0 = READ_ONCE(desc->rx_msdu_info.info0);
2700 		rx_mpdu_info0 = READ_ONCE(desc->rx_mpdu_info.info0);
2701 
2702 		rxcb->is_first_msdu = !!(rx_msdu_info0 &
2703 					 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2704 		rxcb->is_last_msdu = !!(rx_msdu_info0 &
2705 					RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2706 		rxcb->is_continuation = !!(rx_msdu_info0 &
2707 					   RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2708 		rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID,
2709 					  READ_ONCE(desc->rx_mpdu_info.meta_data));
2710 		rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM,
2711 					 rx_mpdu_info0);
2712 		rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
2713 				      info0);
2714 
2715 		rxcb->mac_id = mac_id;
2716 		__skb_queue_tail(&msdu_list[mac_id], msdu);
2717 
2718 		if (rxcb->is_continuation) {
2719 			done = false;
2720 		} else {
2721 			total_msdu_reaped++;
2722 			done = true;
2723 		}
2724 
2725 		if (total_msdu_reaped >= budget)
2726 			break;
2727 	}
2728 
2729 	/* Hw might have updated the head pointer after we cached it.
2730 	 * In this case, even though there are entries in the ring we'll
2731 	 * get rx_desc NULL. Give the read another try with updated cached
2732 	 * head pointer so that we can reap complete MPDU in the current
2733 	 * rx processing.
2734 	 */
2735 	if (unlikely(!done && ath11k_hal_srng_dst_num_free(ab, srng, true))) {
2736 		ath11k_hal_srng_access_end(ab, srng);
2737 		goto try_again;
2738 	}
2739 
2740 	ath11k_hal_srng_access_end(ab, srng);
2741 
2742 	spin_unlock_bh(&srng->lock);
2743 
2744 	if (unlikely(!total_msdu_reaped))
2745 		goto exit;
2746 
2747 	for (i = 0; i < ab->num_radios; i++) {
2748 		if (!num_buffs_reaped[i])
2749 			continue;
2750 
2751 		ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list[i], i);
2752 
2753 		ar = ab->pdevs[i].ar;
2754 		rx_ring = &ar->dp.rx_refill_buf_ring;
2755 
2756 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
2757 					   ab->hw_params.hal_params->rx_buf_rbm);
2758 	}
2759 exit:
2760 	return total_msdu_reaped;
2761 }
2762 
ath11k_dp_rx_update_peer_stats(struct ath11k_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2763 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
2764 					   struct hal_rx_mon_ppdu_info *ppdu_info)
2765 {
2766 	struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
2767 	u32 num_msdu;
2768 	int i;
2769 
2770 	if (!rx_stats)
2771 		return;
2772 
2773 	arsta->rssi_comb = ppdu_info->rssi_comb;
2774 	ewma_avg_rssi_add(&arsta->avg_rssi, ppdu_info->rssi_comb);
2775 
2776 	num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2777 		   ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2778 
2779 	rx_stats->num_msdu += num_msdu;
2780 	rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2781 				    ppdu_info->tcp_ack_msdu_count;
2782 	rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2783 	rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2784 
2785 	if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2786 	    ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2787 		ppdu_info->nss = 1;
2788 		ppdu_info->mcs = HAL_RX_MAX_MCS;
2789 		ppdu_info->tid = IEEE80211_NUM_TIDS;
2790 	}
2791 
2792 	if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
2793 		rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
2794 
2795 	if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
2796 		rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
2797 
2798 	if (ppdu_info->gi < HAL_RX_GI_MAX)
2799 		rx_stats->gi_count[ppdu_info->gi] += num_msdu;
2800 
2801 	if (ppdu_info->bw < HAL_RX_BW_MAX)
2802 		rx_stats->bw_count[ppdu_info->bw] += num_msdu;
2803 
2804 	if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2805 		rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2806 
2807 	if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2808 		rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2809 
2810 	if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2811 		rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2812 
2813 	if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2814 		rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2815 
2816 	if (ppdu_info->is_stbc)
2817 		rx_stats->stbc_count += num_msdu;
2818 
2819 	if (ppdu_info->beamformed)
2820 		rx_stats->beamformed_count += num_msdu;
2821 
2822 	if (ppdu_info->num_mpdu_fcs_ok > 1)
2823 		rx_stats->ampdu_msdu_count += num_msdu;
2824 	else
2825 		rx_stats->non_ampdu_msdu_count += num_msdu;
2826 
2827 	rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2828 	rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2829 	rx_stats->dcm_count += ppdu_info->dcm;
2830 	rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
2831 
2832 	BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) >
2833 			     ARRAY_SIZE(ppdu_info->rssi_chain_pri20));
2834 
2835 	for (i = 0; i < ARRAY_SIZE(arsta->chain_signal); i++)
2836 		arsta->chain_signal[i] = ppdu_info->rssi_chain_pri20[i];
2837 
2838 	rx_stats->rx_duration += ppdu_info->rx_duration;
2839 	arsta->rx_duration = rx_stats->rx_duration;
2840 }
2841 
ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base * ab,struct dp_rxdma_ring * rx_ring,int * buf_id)2842 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
2843 							 struct dp_rxdma_ring *rx_ring,
2844 							 int *buf_id)
2845 {
2846 	struct sk_buff *skb;
2847 	dma_addr_t paddr;
2848 
2849 	skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
2850 			    DP_RX_BUFFER_ALIGN_SIZE);
2851 
2852 	if (!skb)
2853 		goto fail_alloc_skb;
2854 
2855 	if (!IS_ALIGNED((unsigned long)skb->data,
2856 			DP_RX_BUFFER_ALIGN_SIZE)) {
2857 		skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2858 			 skb->data);
2859 	}
2860 
2861 	paddr = dma_map_single(ab->dev, skb->data,
2862 			       skb->len + skb_tailroom(skb),
2863 			       DMA_FROM_DEVICE);
2864 	if (unlikely(dma_mapping_error(ab->dev, paddr)))
2865 		goto fail_free_skb;
2866 
2867 	spin_lock_bh(&rx_ring->idr_lock);
2868 	*buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
2869 			    rx_ring->bufs_max, GFP_ATOMIC);
2870 	spin_unlock_bh(&rx_ring->idr_lock);
2871 	if (*buf_id < 0)
2872 		goto fail_dma_unmap;
2873 
2874 	ATH11K_SKB_RXCB(skb)->paddr = paddr;
2875 	return skb;
2876 
2877 fail_dma_unmap:
2878 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2879 			 DMA_FROM_DEVICE);
2880 fail_free_skb:
2881 	dev_kfree_skb_any(skb);
2882 fail_alloc_skb:
2883 	return NULL;
2884 }
2885 
ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)2886 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
2887 					   struct dp_rxdma_ring *rx_ring,
2888 					   int req_entries,
2889 					   enum hal_rx_buf_return_buf_manager mgr)
2890 {
2891 	struct hal_srng *srng;
2892 	u32 *desc;
2893 	struct sk_buff *skb;
2894 	int num_free;
2895 	int num_remain;
2896 	int buf_id;
2897 	u32 cookie;
2898 	dma_addr_t paddr;
2899 
2900 	req_entries = min(req_entries, rx_ring->bufs_max);
2901 
2902 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2903 
2904 	spin_lock_bh(&srng->lock);
2905 
2906 	ath11k_hal_srng_access_begin(ab, srng);
2907 
2908 	num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
2909 
2910 	req_entries = min(num_free, req_entries);
2911 	num_remain = req_entries;
2912 
2913 	while (num_remain > 0) {
2914 		skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2915 							&buf_id);
2916 		if (!skb)
2917 			break;
2918 		paddr = ATH11K_SKB_RXCB(skb)->paddr;
2919 
2920 		desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
2921 		if (!desc)
2922 			goto fail_desc_get;
2923 
2924 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2925 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2926 
2927 		num_remain--;
2928 
2929 		ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
2930 	}
2931 
2932 	ath11k_hal_srng_access_end(ab, srng);
2933 
2934 	spin_unlock_bh(&srng->lock);
2935 
2936 	return req_entries - num_remain;
2937 
2938 fail_desc_get:
2939 	spin_lock_bh(&rx_ring->idr_lock);
2940 	idr_remove(&rx_ring->bufs_idr, buf_id);
2941 	spin_unlock_bh(&rx_ring->idr_lock);
2942 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2943 			 DMA_FROM_DEVICE);
2944 	dev_kfree_skb_any(skb);
2945 	ath11k_hal_srng_access_end(ab, srng);
2946 	spin_unlock_bh(&srng->lock);
2947 
2948 	return req_entries - num_remain;
2949 }
2950 
2951 #define ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP 32535
2952 
2953 static void
ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data * pmon,struct hal_tlv_hdr * tlv)2954 ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data *pmon,
2955 					 struct hal_tlv_hdr *tlv)
2956 {
2957 	struct hal_rx_ppdu_start *ppdu_start;
2958 	u16 ppdu_id_diff, ppdu_id, tlv_len;
2959 	u8 *ptr;
2960 
2961 	/* PPDU id is part of second tlv, move ptr to second tlv */
2962 	tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl);
2963 	ptr = (u8 *)tlv;
2964 	ptr += sizeof(*tlv) + tlv_len;
2965 	tlv = (struct hal_tlv_hdr *)ptr;
2966 
2967 	if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_PPDU_START)
2968 		return;
2969 
2970 	ptr += sizeof(*tlv);
2971 	ppdu_start = (struct hal_rx_ppdu_start *)ptr;
2972 	ppdu_id = FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID,
2973 			    __le32_to_cpu(ppdu_start->info0));
2974 
2975 	if (pmon->sw_mon_entries.ppdu_id < ppdu_id) {
2976 		pmon->buf_state = DP_MON_STATUS_LEAD;
2977 		ppdu_id_diff = ppdu_id - pmon->sw_mon_entries.ppdu_id;
2978 		if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
2979 			pmon->buf_state = DP_MON_STATUS_LAG;
2980 	} else if (pmon->sw_mon_entries.ppdu_id > ppdu_id) {
2981 		pmon->buf_state = DP_MON_STATUS_LAG;
2982 		ppdu_id_diff = pmon->sw_mon_entries.ppdu_id - ppdu_id;
2983 		if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
2984 			pmon->buf_state = DP_MON_STATUS_LEAD;
2985 	}
2986 }
2987 
2988 static enum dp_mon_status_buf_state
ath11k_dp_rx_mon_buf_done(struct ath11k_base * ab,struct hal_srng * srng,struct dp_rxdma_ring * rx_ring)2989 ath11k_dp_rx_mon_buf_done(struct ath11k_base *ab, struct hal_srng *srng,
2990 			  struct dp_rxdma_ring *rx_ring)
2991 {
2992 	struct ath11k_skb_rxcb *rxcb;
2993 	struct hal_tlv_hdr *tlv;
2994 	struct sk_buff *skb;
2995 	void *status_desc;
2996 	dma_addr_t paddr;
2997 	u32 cookie;
2998 	int buf_id;
2999 	u8 rbm;
3000 
3001 	status_desc = ath11k_hal_srng_src_next_peek(ab, srng);
3002 	if (!status_desc)
3003 		return DP_MON_STATUS_NO_DMA;
3004 
3005 	ath11k_hal_rx_buf_addr_info_get(status_desc, &paddr, &cookie, &rbm);
3006 
3007 	buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3008 
3009 	spin_lock_bh(&rx_ring->idr_lock);
3010 	skb = idr_find(&rx_ring->bufs_idr, buf_id);
3011 	spin_unlock_bh(&rx_ring->idr_lock);
3012 
3013 	if (!skb)
3014 		return DP_MON_STATUS_NO_DMA;
3015 
3016 	rxcb = ATH11K_SKB_RXCB(skb);
3017 	dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3018 				skb->len + skb_tailroom(skb),
3019 				DMA_FROM_DEVICE);
3020 
3021 	tlv = (struct hal_tlv_hdr *)skb->data;
3022 	if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_STATUS_BUFFER_DONE)
3023 		return DP_MON_STATUS_NO_DMA;
3024 
3025 	return DP_MON_STATUS_REPLINISH;
3026 }
3027 
ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base * ab,int mac_id,int * budget,struct sk_buff_head * skb_list)3028 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
3029 					     int *budget, struct sk_buff_head *skb_list)
3030 {
3031 	struct ath11k *ar;
3032 	const struct ath11k_hw_hal_params *hal_params;
3033 	enum dp_mon_status_buf_state reap_status;
3034 	struct ath11k_pdev_dp *dp;
3035 	struct dp_rxdma_ring *rx_ring;
3036 	struct ath11k_mon_data *pmon;
3037 	struct hal_srng *srng;
3038 	void *rx_mon_status_desc;
3039 	struct sk_buff *skb;
3040 	struct ath11k_skb_rxcb *rxcb;
3041 	struct hal_tlv_hdr *tlv;
3042 	u32 cookie;
3043 	int buf_id, srng_id;
3044 	dma_addr_t paddr;
3045 	u8 rbm;
3046 	int num_buffs_reaped = 0;
3047 
3048 	ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
3049 	dp = &ar->dp;
3050 	pmon = &dp->mon_data;
3051 	srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
3052 	rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
3053 
3054 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
3055 
3056 	spin_lock_bh(&srng->lock);
3057 
3058 	ath11k_hal_srng_access_begin(ab, srng);
3059 	while (*budget) {
3060 		*budget -= 1;
3061 		rx_mon_status_desc =
3062 			ath11k_hal_srng_src_peek(ab, srng);
3063 		if (!rx_mon_status_desc) {
3064 			pmon->buf_state = DP_MON_STATUS_REPLINISH;
3065 			break;
3066 		}
3067 
3068 		ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
3069 						&cookie, &rbm);
3070 		if (paddr) {
3071 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3072 
3073 			spin_lock_bh(&rx_ring->idr_lock);
3074 			skb = idr_find(&rx_ring->bufs_idr, buf_id);
3075 			spin_unlock_bh(&rx_ring->idr_lock);
3076 
3077 			if (!skb) {
3078 				ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
3079 					    buf_id);
3080 				pmon->buf_state = DP_MON_STATUS_REPLINISH;
3081 				goto move_next;
3082 			}
3083 
3084 			rxcb = ATH11K_SKB_RXCB(skb);
3085 
3086 			dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3087 						skb->len + skb_tailroom(skb),
3088 						DMA_FROM_DEVICE);
3089 
3090 			tlv = (struct hal_tlv_hdr *)skb->data;
3091 			if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
3092 					HAL_RX_STATUS_BUFFER_DONE) {
3093 				ath11k_warn(ab, "mon status DONE not set %lx, buf_id %d\n",
3094 					    FIELD_GET(HAL_TLV_HDR_TAG,
3095 						      tlv->tl), buf_id);
3096 				/* RxDMA status done bit might not be set even
3097 				 * though tp is moved by HW.
3098 				 */
3099 
3100 				/* If done status is missing:
3101 				 * 1. As per MAC team's suggestion,
3102 				 *    when HP + 1 entry is peeked and if DMA
3103 				 *    is not done and if HP + 2 entry's DMA done
3104 				 *    is set. skip HP + 1 entry and
3105 				 *    start processing in next interrupt.
3106 				 * 2. If HP + 2 entry's DMA done is not set,
3107 				 *    poll onto HP + 1 entry DMA done to be set.
3108 				 *    Check status for same buffer for next time
3109 				 *    dp_rx_mon_status_srng_process
3110 				 */
3111 
3112 				reap_status = ath11k_dp_rx_mon_buf_done(ab, srng,
3113 									rx_ring);
3114 				if (reap_status == DP_MON_STATUS_NO_DMA)
3115 					continue;
3116 
3117 				spin_lock_bh(&rx_ring->idr_lock);
3118 				idr_remove(&rx_ring->bufs_idr, buf_id);
3119 				spin_unlock_bh(&rx_ring->idr_lock);
3120 
3121 				dma_unmap_single(ab->dev, rxcb->paddr,
3122 						 skb->len + skb_tailroom(skb),
3123 						 DMA_FROM_DEVICE);
3124 
3125 				dev_kfree_skb_any(skb);
3126 				pmon->buf_state = DP_MON_STATUS_REPLINISH;
3127 				goto move_next;
3128 			}
3129 
3130 			spin_lock_bh(&rx_ring->idr_lock);
3131 			idr_remove(&rx_ring->bufs_idr, buf_id);
3132 			spin_unlock_bh(&rx_ring->idr_lock);
3133 			if (ab->hw_params.full_monitor_mode) {
3134 				ath11k_dp_rx_mon_update_status_buf_state(pmon, tlv);
3135 				if (paddr == pmon->mon_status_paddr)
3136 					pmon->buf_state = DP_MON_STATUS_MATCH;
3137 			}
3138 
3139 			dma_unmap_single(ab->dev, rxcb->paddr,
3140 					 skb->len + skb_tailroom(skb),
3141 					 DMA_FROM_DEVICE);
3142 
3143 			__skb_queue_tail(skb_list, skb);
3144 		} else {
3145 			pmon->buf_state = DP_MON_STATUS_REPLINISH;
3146 		}
3147 move_next:
3148 		skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
3149 							&buf_id);
3150 
3151 		if (!skb) {
3152 			hal_params = ab->hw_params.hal_params;
3153 			ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
3154 							hal_params->rx_buf_rbm);
3155 			num_buffs_reaped++;
3156 			break;
3157 		}
3158 		rxcb = ATH11K_SKB_RXCB(skb);
3159 
3160 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
3161 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3162 
3163 		ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
3164 						cookie,
3165 						ab->hw_params.hal_params->rx_buf_rbm);
3166 		ath11k_hal_srng_src_get_next_entry(ab, srng);
3167 		num_buffs_reaped++;
3168 	}
3169 	ath11k_hal_srng_access_end(ab, srng);
3170 	spin_unlock_bh(&srng->lock);
3171 
3172 	return num_buffs_reaped;
3173 }
3174 
ath11k_dp_rx_frag_timer(struct timer_list * timer)3175 static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
3176 {
3177 	struct dp_rx_tid *rx_tid = timer_container_of(rx_tid, timer,
3178 						      frag_timer);
3179 
3180 	spin_lock_bh(&rx_tid->ab->base_lock);
3181 	if (rx_tid->last_frag_no &&
3182 	    rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
3183 		spin_unlock_bh(&rx_tid->ab->base_lock);
3184 		return;
3185 	}
3186 	ath11k_dp_rx_frags_cleanup(rx_tid, true);
3187 	spin_unlock_bh(&rx_tid->ab->base_lock);
3188 }
3189 
ath11k_peer_rx_frag_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id)3190 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
3191 {
3192 	struct ath11k_base *ab = ar->ab;
3193 	struct crypto_shash *tfm;
3194 	struct ath11k_peer *peer;
3195 	struct dp_rx_tid *rx_tid;
3196 	int i;
3197 
3198 	tfm = crypto_alloc_shash("michael_mic", 0, 0);
3199 	if (IS_ERR(tfm)) {
3200 		ath11k_warn(ab, "failed to allocate michael_mic shash: %ld\n",
3201 			    PTR_ERR(tfm));
3202 		return PTR_ERR(tfm);
3203 	}
3204 
3205 	spin_lock_bh(&ab->base_lock);
3206 
3207 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
3208 	if (!peer) {
3209 		ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
3210 		spin_unlock_bh(&ab->base_lock);
3211 		crypto_free_shash(tfm);
3212 		return -ENOENT;
3213 	}
3214 
3215 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
3216 		rx_tid = &peer->rx_tid[i];
3217 		rx_tid->ab = ab;
3218 		timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
3219 		skb_queue_head_init(&rx_tid->rx_frags);
3220 	}
3221 
3222 	peer->tfm_mmic = tfm;
3223 	peer->dp_setup_done = true;
3224 	spin_unlock_bh(&ab->base_lock);
3225 
3226 	return 0;
3227 }
3228 
ath11k_dp_rx_h_michael_mic(struct crypto_shash * tfm,u8 * key,struct ieee80211_hdr * hdr,u8 * data,size_t data_len,u8 * mic)3229 static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
3230 				      struct ieee80211_hdr *hdr, u8 *data,
3231 				      size_t data_len, u8 *mic)
3232 {
3233 	SHASH_DESC_ON_STACK(desc, tfm);
3234 	u8 mic_hdr[16] = {0};
3235 	u8 tid = 0;
3236 	int ret;
3237 
3238 	if (!tfm)
3239 		return -EINVAL;
3240 
3241 	desc->tfm = tfm;
3242 
3243 	ret = crypto_shash_setkey(tfm, key, 8);
3244 	if (ret)
3245 		goto out;
3246 
3247 	ret = crypto_shash_init(desc);
3248 	if (ret)
3249 		goto out;
3250 
3251 	/* TKIP MIC header */
3252 	memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
3253 	memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
3254 	if (ieee80211_is_data_qos(hdr->frame_control))
3255 		tid = ieee80211_get_tid(hdr);
3256 	mic_hdr[12] = tid;
3257 
3258 	ret = crypto_shash_update(desc, mic_hdr, 16);
3259 	if (ret)
3260 		goto out;
3261 	ret = crypto_shash_update(desc, data, data_len);
3262 	if (ret)
3263 		goto out;
3264 	ret = crypto_shash_final(desc, mic);
3265 out:
3266 	shash_desc_zero(desc);
3267 	return ret;
3268 }
3269 
ath11k_dp_rx_h_verify_tkip_mic(struct ath11k * ar,struct ath11k_peer * peer,struct sk_buff * msdu)3270 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
3271 					  struct sk_buff *msdu)
3272 {
3273 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3274 	struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
3275 	struct ieee80211_key_conf *key_conf;
3276 	struct ieee80211_hdr *hdr;
3277 	u8 mic[IEEE80211_CCMP_MIC_LEN];
3278 	int head_len, tail_len, ret;
3279 	size_t data_len;
3280 	u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3281 	u8 *key, *data;
3282 	u8 key_idx;
3283 
3284 	if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) !=
3285 	    HAL_ENCRYPT_TYPE_TKIP_MIC)
3286 		return 0;
3287 
3288 	hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3289 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
3290 	head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
3291 	tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3292 
3293 	if (!is_multicast_ether_addr(hdr->addr1))
3294 		key_idx = peer->ucast_keyidx;
3295 	else
3296 		key_idx = peer->mcast_keyidx;
3297 
3298 	key_conf = peer->keys[key_idx];
3299 
3300 	data = msdu->data + head_len;
3301 	data_len = msdu->len - head_len - tail_len;
3302 	key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3303 
3304 	ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
3305 	if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3306 		goto mic_fail;
3307 
3308 	return 0;
3309 
3310 mic_fail:
3311 	(ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
3312 	(ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
3313 
3314 	rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3315 		    RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3316 	skb_pull(msdu, hal_rx_desc_sz);
3317 
3318 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3319 	ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
3320 			       HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3321 	ieee80211_rx(ar->hw, msdu);
3322 	return -EINVAL;
3323 }
3324 
ath11k_dp_rx_h_undecap_frag(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)3325 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
3326 					enum hal_encrypt_type enctype, u32 flags)
3327 {
3328 	struct ieee80211_hdr *hdr;
3329 	size_t hdr_len;
3330 	size_t crypto_len;
3331 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3332 
3333 	if (!flags)
3334 		return;
3335 
3336 	hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3337 
3338 	if (flags & RX_FLAG_MIC_STRIPPED)
3339 		skb_trim(msdu, msdu->len -
3340 			 ath11k_dp_rx_crypto_mic_len(ar, enctype));
3341 
3342 	if (flags & RX_FLAG_ICV_STRIPPED)
3343 		skb_trim(msdu, msdu->len -
3344 			 ath11k_dp_rx_crypto_icv_len(ar, enctype));
3345 
3346 	if (flags & RX_FLAG_IV_STRIPPED) {
3347 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
3348 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
3349 
3350 		memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len,
3351 			(void *)msdu->data + hal_rx_desc_sz, hdr_len);
3352 		skb_pull(msdu, crypto_len);
3353 	}
3354 }
3355 
ath11k_dp_rx_h_defrag(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)3356 static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
3357 				 struct ath11k_peer *peer,
3358 				 struct dp_rx_tid *rx_tid,
3359 				 struct sk_buff **defrag_skb)
3360 {
3361 	struct hal_rx_desc *rx_desc;
3362 	struct sk_buff *skb, *first_frag, *last_frag;
3363 	struct ieee80211_hdr *hdr;
3364 	struct rx_attention *rx_attention;
3365 	enum hal_encrypt_type enctype;
3366 	bool is_decrypted = false;
3367 	int msdu_len = 0;
3368 	int extra_space;
3369 	u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3370 
3371 	first_frag = skb_peek(&rx_tid->rx_frags);
3372 	last_frag = skb_peek_tail(&rx_tid->rx_frags);
3373 
3374 	skb_queue_walk(&rx_tid->rx_frags, skb) {
3375 		flags = 0;
3376 		rx_desc = (struct hal_rx_desc *)skb->data;
3377 		hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3378 
3379 		enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
3380 		if (enctype != HAL_ENCRYPT_TYPE_OPEN) {
3381 			rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
3382 			is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
3383 		}
3384 
3385 		if (is_decrypted) {
3386 			if (skb != first_frag)
3387 				flags |=  RX_FLAG_IV_STRIPPED;
3388 			if (skb != last_frag)
3389 				flags |= RX_FLAG_ICV_STRIPPED |
3390 					 RX_FLAG_MIC_STRIPPED;
3391 		}
3392 
3393 		/* RX fragments are always raw packets */
3394 		if (skb != last_frag)
3395 			skb_trim(skb, skb->len - FCS_LEN);
3396 		ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3397 
3398 		if (skb != first_frag)
3399 			skb_pull(skb, hal_rx_desc_sz +
3400 				      ieee80211_hdrlen(hdr->frame_control));
3401 		msdu_len += skb->len;
3402 	}
3403 
3404 	extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3405 	if (extra_space > 0 &&
3406 	    (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3407 		return -ENOMEM;
3408 
3409 	__skb_unlink(first_frag, &rx_tid->rx_frags);
3410 	while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3411 		skb_put_data(first_frag, skb->data, skb->len);
3412 		dev_kfree_skb_any(skb);
3413 	}
3414 
3415 	hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
3416 	hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3417 	ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
3418 
3419 	if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3420 		first_frag = NULL;
3421 
3422 	*defrag_skb = first_frag;
3423 	return 0;
3424 }
3425 
ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k * ar,struct dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3426 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
3427 					      struct sk_buff *defrag_skb)
3428 {
3429 	struct ath11k_base *ab = ar->ab;
3430 	struct ath11k_pdev_dp *dp = &ar->dp;
3431 	struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
3432 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3433 	struct hal_reo_entrance_ring *reo_ent_ring;
3434 	struct hal_reo_dest_ring *reo_dest_ring;
3435 	struct dp_link_desc_bank *link_desc_banks;
3436 	struct hal_rx_msdu_link *msdu_link;
3437 	struct hal_rx_msdu_details *msdu0;
3438 	struct hal_srng *srng;
3439 	dma_addr_t paddr;
3440 	u32 desc_bank, msdu_info, mpdu_info;
3441 	u32 dst_idx, cookie, hal_rx_desc_sz;
3442 	int ret, buf_id;
3443 
3444 	hal_rx_desc_sz = ab->hw_params.hal_desc_sz;
3445 	link_desc_banks = ab->dp.link_desc_banks;
3446 	reo_dest_ring = rx_tid->dst_ring_desc;
3447 
3448 	ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3449 	msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3450 			(paddr - link_desc_banks[desc_bank].paddr));
3451 	msdu0 = &msdu_link->msdu_link[0];
3452 	dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
3453 	memset(msdu0, 0, sizeof(*msdu0));
3454 
3455 	msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
3456 		    FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
3457 		    FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
3458 		    FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
3459 			       defrag_skb->len - hal_rx_desc_sz) |
3460 		    FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
3461 		    FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
3462 		    FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
3463 	msdu0->rx_msdu_info.info0 = msdu_info;
3464 
3465 	/* change msdu len in hal rx desc */
3466 	ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3467 
3468 	paddr = dma_map_single(ab->dev, defrag_skb->data,
3469 			       defrag_skb->len + skb_tailroom(defrag_skb),
3470 			       DMA_TO_DEVICE);
3471 	if (dma_mapping_error(ab->dev, paddr))
3472 		return -ENOMEM;
3473 
3474 	spin_lock_bh(&rx_refill_ring->idr_lock);
3475 	buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
3476 			   rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
3477 	spin_unlock_bh(&rx_refill_ring->idr_lock);
3478 	if (buf_id < 0) {
3479 		ret = -ENOMEM;
3480 		goto err_unmap_dma;
3481 	}
3482 
3483 	ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
3484 	cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
3485 		 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3486 
3487 	ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie,
3488 					ab->hw_params.hal_params->rx_buf_rbm);
3489 
3490 	/* Fill mpdu details into reo entrance ring */
3491 	srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
3492 
3493 	spin_lock_bh(&srng->lock);
3494 	ath11k_hal_srng_access_begin(ab, srng);
3495 
3496 	reo_ent_ring = (struct hal_reo_entrance_ring *)
3497 			ath11k_hal_srng_src_get_next_entry(ab, srng);
3498 	if (!reo_ent_ring) {
3499 		ath11k_hal_srng_access_end(ab, srng);
3500 		spin_unlock_bh(&srng->lock);
3501 		ret = -ENOSPC;
3502 		goto err_free_idr;
3503 	}
3504 	memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3505 
3506 	ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3507 	ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
3508 					HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
3509 
3510 	mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
3511 		    FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
3512 		    FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
3513 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
3514 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
3515 		    FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
3516 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
3517 
3518 	reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
3519 	reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
3520 	reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
3521 	reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
3522 					 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
3523 						   reo_dest_ring->info0)) |
3524 			      FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
3525 	ath11k_hal_srng_access_end(ab, srng);
3526 	spin_unlock_bh(&srng->lock);
3527 
3528 	return 0;
3529 
3530 err_free_idr:
3531 	spin_lock_bh(&rx_refill_ring->idr_lock);
3532 	idr_remove(&rx_refill_ring->bufs_idr, buf_id);
3533 	spin_unlock_bh(&rx_refill_ring->idr_lock);
3534 err_unmap_dma:
3535 	dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3536 			 DMA_TO_DEVICE);
3537 	return ret;
3538 }
3539 
ath11k_dp_rx_h_cmp_frags(struct ath11k * ar,struct sk_buff * a,struct sk_buff * b)3540 static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar,
3541 				    struct sk_buff *a, struct sk_buff *b)
3542 {
3543 	int frag1, frag2;
3544 
3545 	frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a);
3546 	frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b);
3547 
3548 	return frag1 - frag2;
3549 }
3550 
ath11k_dp_rx_h_sort_frags(struct ath11k * ar,struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3551 static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar,
3552 				      struct sk_buff_head *frag_list,
3553 				      struct sk_buff *cur_frag)
3554 {
3555 	struct sk_buff *skb;
3556 	int cmp;
3557 
3558 	skb_queue_walk(frag_list, skb) {
3559 		cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag);
3560 		if (cmp < 0)
3561 			continue;
3562 		__skb_queue_before(frag_list, skb, cur_frag);
3563 		return;
3564 	}
3565 	__skb_queue_tail(frag_list, cur_frag);
3566 }
3567 
ath11k_dp_rx_h_get_pn(struct ath11k * ar,struct sk_buff * skb)3568 static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb)
3569 {
3570 	struct ieee80211_hdr *hdr;
3571 	u64 pn = 0;
3572 	u8 *ehdr;
3573 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3574 
3575 	hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3576 	ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3577 
3578 	pn = ehdr[0];
3579 	pn |= (u64)ehdr[1] << 8;
3580 	pn |= (u64)ehdr[4] << 16;
3581 	pn |= (u64)ehdr[5] << 24;
3582 	pn |= (u64)ehdr[6] << 32;
3583 	pn |= (u64)ehdr[7] << 40;
3584 
3585 	return pn;
3586 }
3587 
3588 static bool
ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k * ar,struct dp_rx_tid * rx_tid)3589 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
3590 {
3591 	enum hal_encrypt_type encrypt_type;
3592 	struct sk_buff *first_frag, *skb;
3593 	struct hal_rx_desc *desc;
3594 	u64 last_pn;
3595 	u64 cur_pn;
3596 
3597 	first_frag = skb_peek(&rx_tid->rx_frags);
3598 	desc = (struct hal_rx_desc *)first_frag->data;
3599 
3600 	encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc);
3601 	if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3602 	    encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3603 	    encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3604 	    encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3605 		return true;
3606 
3607 	last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag);
3608 	skb_queue_walk(&rx_tid->rx_frags, skb) {
3609 		if (skb == first_frag)
3610 			continue;
3611 
3612 		cur_pn = ath11k_dp_rx_h_get_pn(ar, skb);
3613 		if (cur_pn != last_pn + 1)
3614 			return false;
3615 		last_pn = cur_pn;
3616 	}
3617 	return true;
3618 }
3619 
ath11k_dp_rx_frag_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,u32 * ring_desc)3620 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
3621 				    struct sk_buff *msdu,
3622 				    u32 *ring_desc)
3623 {
3624 	struct ath11k_base *ab = ar->ab;
3625 	struct hal_rx_desc *rx_desc;
3626 	struct ath11k_peer *peer;
3627 	struct dp_rx_tid *rx_tid;
3628 	struct sk_buff *defrag_skb = NULL;
3629 	u32 peer_id;
3630 	u16 seqno, frag_no;
3631 	u8 tid;
3632 	int ret = 0;
3633 	bool more_frags;
3634 	bool is_mcbc;
3635 
3636 	rx_desc = (struct hal_rx_desc *)msdu->data;
3637 	peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
3638 	tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc);
3639 	seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
3640 	frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu);
3641 	more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu);
3642 	is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
3643 
3644 	/* Multicast/Broadcast fragments are not expected */
3645 	if (is_mcbc)
3646 		return -EINVAL;
3647 
3648 	if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) ||
3649 	    !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) ||
3650 	    tid > IEEE80211_NUM_TIDS)
3651 		return -EINVAL;
3652 
3653 	/* received unfragmented packet in reo
3654 	 * exception ring, this shouldn't happen
3655 	 * as these packets typically come from
3656 	 * reo2sw srngs.
3657 	 */
3658 	if (WARN_ON_ONCE(!frag_no && !more_frags))
3659 		return -EINVAL;
3660 
3661 	spin_lock_bh(&ab->base_lock);
3662 	peer = ath11k_peer_find_by_id(ab, peer_id);
3663 	if (!peer) {
3664 		ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3665 			    peer_id);
3666 		ret = -ENOENT;
3667 		goto out_unlock;
3668 	}
3669 	if (!peer->dp_setup_done) {
3670 		ath11k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n",
3671 			    peer->addr, peer_id);
3672 		ret = -ENOENT;
3673 		goto out_unlock;
3674 	}
3675 
3676 	rx_tid = &peer->rx_tid[tid];
3677 
3678 	if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3679 	    skb_queue_empty(&rx_tid->rx_frags)) {
3680 		/* Flush stored fragments and start a new sequence */
3681 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
3682 		rx_tid->cur_sn = seqno;
3683 	}
3684 
3685 	if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3686 		/* Fragment already present */
3687 		ret = -EINVAL;
3688 		goto out_unlock;
3689 	}
3690 
3691 	if (!rx_tid->rx_frag_bitmap || (frag_no > __fls(rx_tid->rx_frag_bitmap)))
3692 		__skb_queue_tail(&rx_tid->rx_frags, msdu);
3693 	else
3694 		ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu);
3695 
3696 	rx_tid->rx_frag_bitmap |= BIT(frag_no);
3697 	if (!more_frags)
3698 		rx_tid->last_frag_no = frag_no;
3699 
3700 	if (frag_no == 0) {
3701 		rx_tid->dst_ring_desc = kmemdup(ring_desc,
3702 						sizeof(*rx_tid->dst_ring_desc),
3703 						GFP_ATOMIC);
3704 		if (!rx_tid->dst_ring_desc) {
3705 			ret = -ENOMEM;
3706 			goto out_unlock;
3707 		}
3708 	} else {
3709 		ath11k_dp_rx_link_desc_return(ab, ring_desc,
3710 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3711 	}
3712 
3713 	if (!rx_tid->last_frag_no ||
3714 	    rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3715 		mod_timer(&rx_tid->frag_timer, jiffies +
3716 					       ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
3717 		goto out_unlock;
3718 	}
3719 
3720 	spin_unlock_bh(&ab->base_lock);
3721 	timer_delete_sync(&rx_tid->frag_timer);
3722 	spin_lock_bh(&ab->base_lock);
3723 
3724 	peer = ath11k_peer_find_by_id(ab, peer_id);
3725 	if (!peer)
3726 		goto err_frags_cleanup;
3727 
3728 	if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3729 		goto err_frags_cleanup;
3730 
3731 	if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3732 		goto err_frags_cleanup;
3733 
3734 	if (!defrag_skb)
3735 		goto err_frags_cleanup;
3736 
3737 	if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3738 		goto err_frags_cleanup;
3739 
3740 	ath11k_dp_rx_frags_cleanup(rx_tid, false);
3741 	goto out_unlock;
3742 
3743 err_frags_cleanup:
3744 	dev_kfree_skb_any(defrag_skb);
3745 	ath11k_dp_rx_frags_cleanup(rx_tid, true);
3746 out_unlock:
3747 	spin_unlock_bh(&ab->base_lock);
3748 	return ret;
3749 }
3750 
3751 static int
ath11k_dp_process_rx_err_buf(struct ath11k * ar,u32 * ring_desc,int buf_id,bool drop)3752 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
3753 {
3754 	struct ath11k_pdev_dp *dp = &ar->dp;
3755 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
3756 	struct sk_buff *msdu;
3757 	struct ath11k_skb_rxcb *rxcb;
3758 	struct hal_rx_desc *rx_desc;
3759 	u8 *hdr_status;
3760 	u16 msdu_len;
3761 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3762 
3763 	spin_lock_bh(&rx_ring->idr_lock);
3764 	msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3765 	if (!msdu) {
3766 		ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
3767 			    buf_id);
3768 		spin_unlock_bh(&rx_ring->idr_lock);
3769 		return -EINVAL;
3770 	}
3771 
3772 	idr_remove(&rx_ring->bufs_idr, buf_id);
3773 	spin_unlock_bh(&rx_ring->idr_lock);
3774 
3775 	rxcb = ATH11K_SKB_RXCB(msdu);
3776 	dma_unmap_single(ar->ab->dev, rxcb->paddr,
3777 			 msdu->len + skb_tailroom(msdu),
3778 			 DMA_FROM_DEVICE);
3779 
3780 	if (drop) {
3781 		dev_kfree_skb_any(msdu);
3782 		return 0;
3783 	}
3784 
3785 	rcu_read_lock();
3786 	if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3787 		dev_kfree_skb_any(msdu);
3788 		goto exit;
3789 	}
3790 
3791 	if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
3792 		dev_kfree_skb_any(msdu);
3793 		goto exit;
3794 	}
3795 
3796 	rx_desc = (struct hal_rx_desc *)msdu->data;
3797 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc);
3798 	if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3799 		hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
3800 		ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3801 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
3802 				sizeof(struct ieee80211_hdr));
3803 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
3804 				sizeof(struct hal_rx_desc));
3805 		dev_kfree_skb_any(msdu);
3806 		goto exit;
3807 	}
3808 
3809 	skb_put(msdu, hal_rx_desc_sz + msdu_len);
3810 
3811 	if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
3812 		dev_kfree_skb_any(msdu);
3813 		ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
3814 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3815 	}
3816 exit:
3817 	rcu_read_unlock();
3818 	return 0;
3819 }
3820 
ath11k_dp_process_rx_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3821 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
3822 			     int budget)
3823 {
3824 	u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3825 	struct dp_link_desc_bank *link_desc_banks;
3826 	enum hal_rx_buf_return_buf_manager rbm;
3827 	int tot_n_bufs_reaped, quota, ret, i;
3828 	int n_bufs_reaped[MAX_RADIOS] = {0};
3829 	struct dp_rxdma_ring *rx_ring;
3830 	struct dp_srng *reo_except;
3831 	u32 desc_bank, num_msdus;
3832 	struct hal_srng *srng;
3833 	struct ath11k_dp *dp;
3834 	void *link_desc_va;
3835 	int buf_id, mac_id;
3836 	struct ath11k *ar;
3837 	dma_addr_t paddr;
3838 	u32 *desc;
3839 	bool is_frag;
3840 	u8 drop = 0;
3841 
3842 	tot_n_bufs_reaped = 0;
3843 	quota = budget;
3844 
3845 	dp = &ab->dp;
3846 	reo_except = &dp->reo_except_ring;
3847 	link_desc_banks = dp->link_desc_banks;
3848 
3849 	srng = &ab->hal.srng_list[reo_except->ring_id];
3850 
3851 	spin_lock_bh(&srng->lock);
3852 
3853 	ath11k_hal_srng_access_begin(ab, srng);
3854 
3855 	while (budget &&
3856 	       (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
3857 		struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
3858 
3859 		ab->soc_stats.err_ring_pkts++;
3860 		ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
3861 						    &desc_bank);
3862 		if (ret) {
3863 			ath11k_warn(ab, "failed to parse error reo desc %d\n",
3864 				    ret);
3865 			continue;
3866 		}
3867 		link_desc_va = link_desc_banks[desc_bank].vaddr +
3868 			       (paddr - link_desc_banks[desc_bank].paddr);
3869 		ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3870 						 &rbm);
3871 		if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
3872 		    rbm != HAL_RX_BUF_RBM_SW1_BM &&
3873 		    rbm != HAL_RX_BUF_RBM_SW3_BM) {
3874 			ab->soc_stats.invalid_rbm++;
3875 			ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
3876 			ath11k_dp_rx_link_desc_return(ab, desc,
3877 						      HAL_WBM_REL_BM_ACT_REL_MSDU);
3878 			continue;
3879 		}
3880 
3881 		is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
3882 
3883 		/* Process only rx fragments with one msdu per link desc below, and drop
3884 		 * msdu's indicated due to error reasons.
3885 		 */
3886 		if (!is_frag || num_msdus > 1) {
3887 			drop = 1;
3888 			/* Return the link desc back to wbm idle list */
3889 			ath11k_dp_rx_link_desc_return(ab, desc,
3890 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3891 		}
3892 
3893 		for (i = 0; i < num_msdus; i++) {
3894 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
3895 					   msdu_cookies[i]);
3896 
3897 			mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
3898 					   msdu_cookies[i]);
3899 
3900 			ar = ab->pdevs[mac_id].ar;
3901 
3902 			if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
3903 				n_bufs_reaped[mac_id]++;
3904 				tot_n_bufs_reaped++;
3905 			}
3906 		}
3907 
3908 		if (tot_n_bufs_reaped >= quota) {
3909 			tot_n_bufs_reaped = quota;
3910 			goto exit;
3911 		}
3912 
3913 		budget = quota - tot_n_bufs_reaped;
3914 	}
3915 
3916 exit:
3917 	ath11k_hal_srng_access_end(ab, srng);
3918 
3919 	spin_unlock_bh(&srng->lock);
3920 
3921 	for (i = 0; i <  ab->num_radios; i++) {
3922 		if (!n_bufs_reaped[i])
3923 			continue;
3924 
3925 		ar = ab->pdevs[i].ar;
3926 		rx_ring = &ar->dp.rx_refill_buf_ring;
3927 
3928 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
3929 					   ab->hw_params.hal_params->rx_buf_rbm);
3930 	}
3931 
3932 	return tot_n_bufs_reaped;
3933 }
3934 
ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k * ar,int msdu_len,struct sk_buff_head * msdu_list)3935 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
3936 					     int msdu_len,
3937 					     struct sk_buff_head *msdu_list)
3938 {
3939 	struct sk_buff *skb, *tmp;
3940 	struct ath11k_skb_rxcb *rxcb;
3941 	int n_buffs;
3942 
3943 	n_buffs = DIV_ROUND_UP(msdu_len,
3944 			       (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz));
3945 
3946 	skb_queue_walk_safe(msdu_list, skb, tmp) {
3947 		rxcb = ATH11K_SKB_RXCB(skb);
3948 		if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3949 		    rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3950 			if (!n_buffs)
3951 				break;
3952 			__skb_unlink(skb, msdu_list);
3953 			dev_kfree_skb_any(skb);
3954 			n_buffs--;
3955 		}
3956 	}
3957 }
3958 
ath11k_dp_rx_h_null_q_desc(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3959 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
3960 				      struct ieee80211_rx_status *status,
3961 				      struct sk_buff_head *msdu_list)
3962 {
3963 	u16 msdu_len;
3964 	struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3965 	struct rx_attention *rx_attention;
3966 	u8 l3pad_bytes;
3967 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3968 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3969 
3970 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
3971 
3972 	if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
3973 		/* First buffer will be freed by the caller, so deduct it's length */
3974 		msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
3975 		ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3976 		return -EINVAL;
3977 	}
3978 
3979 	rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc);
3980 	if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
3981 		ath11k_warn(ar->ab,
3982 			    "msdu_done bit not set in null_q_des processing\n");
3983 		__skb_queue_purge(msdu_list);
3984 		return -EIO;
3985 	}
3986 
3987 	/* Handle NULL queue descriptor violations arising out a missing
3988 	 * REO queue for a given peer or a given TID. This typically
3989 	 * may happen if a packet is received on a QOS enabled TID before the
3990 	 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3991 	 * it may also happen for MC/BC frames if they are not routed to the
3992 	 * non-QOS TID queue, in the absence of any other default TID queue.
3993 	 * This error can show up both in a REO destination or WBM release ring.
3994 	 */
3995 
3996 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
3997 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
3998 
3999 	if (rxcb->is_frag) {
4000 		skb_pull(msdu, hal_rx_desc_sz);
4001 	} else {
4002 		l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
4003 
4004 		if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
4005 			return -EINVAL;
4006 
4007 		skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
4008 		skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
4009 	}
4010 	ath11k_dp_rx_h_ppdu(ar, desc, status);
4011 
4012 	ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
4013 
4014 	rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc);
4015 
4016 	/* Please note that caller will having the access to msdu and completing
4017 	 * rx with mac80211. Need not worry about cleaning up amsdu_list.
4018 	 */
4019 
4020 	return 0;
4021 }
4022 
ath11k_dp_rx_h_reo_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)4023 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
4024 				   struct ieee80211_rx_status *status,
4025 				   struct sk_buff_head *msdu_list)
4026 {
4027 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4028 	bool drop = false;
4029 
4030 	ar->ab->soc_stats.reo_error[rxcb->err_code]++;
4031 
4032 	switch (rxcb->err_code) {
4033 	case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
4034 		if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
4035 			drop = true;
4036 		break;
4037 	case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
4038 		/* TODO: Do not drop PN failed packets in the driver;
4039 		 * instead, it is good to drop such packets in mac80211
4040 		 * after incrementing the replay counters.
4041 		 */
4042 		fallthrough;
4043 	default:
4044 		/* TODO: Review other errors and process them to mac80211
4045 		 * as appropriate.
4046 		 */
4047 		drop = true;
4048 		break;
4049 	}
4050 
4051 	return drop;
4052 }
4053 
ath11k_dp_rx_h_tkip_mic_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4054 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
4055 					struct ieee80211_rx_status *status)
4056 {
4057 	u16 msdu_len;
4058 	struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
4059 	u8 l3pad_bytes;
4060 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4061 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
4062 
4063 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
4064 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
4065 
4066 	l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
4067 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
4068 	skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
4069 	skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
4070 
4071 	ath11k_dp_rx_h_ppdu(ar, desc, status);
4072 
4073 	status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
4074 			 RX_FLAG_DECRYPTED);
4075 
4076 	ath11k_dp_rx_h_undecap(ar, msdu, desc,
4077 			       HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
4078 }
4079 
ath11k_dp_rx_h_rxdma_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4080 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar,  struct sk_buff *msdu,
4081 				     struct ieee80211_rx_status *status)
4082 {
4083 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4084 	bool drop = false;
4085 
4086 	ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
4087 
4088 	switch (rxcb->err_code) {
4089 	case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
4090 		ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
4091 		break;
4092 	default:
4093 		/* TODO: Review other rxdma error code to check if anything is
4094 		 * worth reporting to mac80211
4095 		 */
4096 		drop = true;
4097 		break;
4098 	}
4099 
4100 	return drop;
4101 }
4102 
ath11k_dp_rx_wbm_err(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)4103 static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
4104 				 struct napi_struct *napi,
4105 				 struct sk_buff *msdu,
4106 				 struct sk_buff_head *msdu_list)
4107 {
4108 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4109 	struct ieee80211_rx_status rxs = {0};
4110 	bool drop = true;
4111 
4112 	switch (rxcb->err_rel_src) {
4113 	case HAL_WBM_REL_SRC_MODULE_REO:
4114 		drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
4115 		break;
4116 	case HAL_WBM_REL_SRC_MODULE_RXDMA:
4117 		drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
4118 		break;
4119 	default:
4120 		/* msdu will get freed */
4121 		break;
4122 	}
4123 
4124 	if (drop) {
4125 		dev_kfree_skb_any(msdu);
4126 		return;
4127 	}
4128 
4129 	ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
4130 }
4131 
ath11k_dp_rx_process_wbm_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)4132 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
4133 				 struct napi_struct *napi, int budget)
4134 {
4135 	struct ath11k *ar;
4136 	struct ath11k_dp *dp = &ab->dp;
4137 	struct dp_rxdma_ring *rx_ring;
4138 	struct hal_rx_wbm_rel_info err_info;
4139 	struct hal_srng *srng;
4140 	struct sk_buff *msdu;
4141 	struct sk_buff_head msdu_list[MAX_RADIOS];
4142 	struct ath11k_skb_rxcb *rxcb;
4143 	u32 *rx_desc;
4144 	int buf_id, mac_id;
4145 	int num_buffs_reaped[MAX_RADIOS] = {0};
4146 	int total_num_buffs_reaped = 0;
4147 	int ret, i;
4148 
4149 	for (i = 0; i < ab->num_radios; i++)
4150 		__skb_queue_head_init(&msdu_list[i]);
4151 
4152 	srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
4153 
4154 	spin_lock_bh(&srng->lock);
4155 
4156 	ath11k_hal_srng_access_begin(ab, srng);
4157 
4158 	while (budget) {
4159 		rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
4160 		if (!rx_desc)
4161 			break;
4162 
4163 		ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
4164 		if (ret) {
4165 			ath11k_warn(ab,
4166 				    "failed to parse rx error in wbm_rel ring desc %d\n",
4167 				    ret);
4168 			continue;
4169 		}
4170 
4171 		buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
4172 		mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
4173 
4174 		ar = ab->pdevs[mac_id].ar;
4175 		rx_ring = &ar->dp.rx_refill_buf_ring;
4176 
4177 		spin_lock_bh(&rx_ring->idr_lock);
4178 		msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4179 		if (!msdu) {
4180 			ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
4181 				    buf_id, mac_id);
4182 			spin_unlock_bh(&rx_ring->idr_lock);
4183 			continue;
4184 		}
4185 
4186 		idr_remove(&rx_ring->bufs_idr, buf_id);
4187 		spin_unlock_bh(&rx_ring->idr_lock);
4188 
4189 		rxcb = ATH11K_SKB_RXCB(msdu);
4190 		dma_unmap_single(ab->dev, rxcb->paddr,
4191 				 msdu->len + skb_tailroom(msdu),
4192 				 DMA_FROM_DEVICE);
4193 
4194 		num_buffs_reaped[mac_id]++;
4195 		total_num_buffs_reaped++;
4196 		budget--;
4197 
4198 		if (err_info.push_reason !=
4199 		    HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4200 			dev_kfree_skb_any(msdu);
4201 			continue;
4202 		}
4203 
4204 		rxcb->err_rel_src = err_info.err_rel_src;
4205 		rxcb->err_code = err_info.err_code;
4206 		rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
4207 		__skb_queue_tail(&msdu_list[mac_id], msdu);
4208 	}
4209 
4210 	ath11k_hal_srng_access_end(ab, srng);
4211 
4212 	spin_unlock_bh(&srng->lock);
4213 
4214 	if (!total_num_buffs_reaped)
4215 		goto done;
4216 
4217 	for (i = 0; i <  ab->num_radios; i++) {
4218 		if (!num_buffs_reaped[i])
4219 			continue;
4220 
4221 		ar = ab->pdevs[i].ar;
4222 		rx_ring = &ar->dp.rx_refill_buf_ring;
4223 
4224 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
4225 					   ab->hw_params.hal_params->rx_buf_rbm);
4226 	}
4227 
4228 	rcu_read_lock();
4229 	for (i = 0; i <  ab->num_radios; i++) {
4230 		if (!rcu_dereference(ab->pdevs_active[i])) {
4231 			__skb_queue_purge(&msdu_list[i]);
4232 			continue;
4233 		}
4234 
4235 		ar = ab->pdevs[i].ar;
4236 
4237 		if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
4238 			__skb_queue_purge(&msdu_list[i]);
4239 			continue;
4240 		}
4241 
4242 		while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
4243 			ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
4244 	}
4245 	rcu_read_unlock();
4246 done:
4247 	return total_num_buffs_reaped;
4248 }
4249 
ath11k_dp_process_rxdma_err(struct ath11k_base * ab,int mac_id,int budget)4250 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
4251 {
4252 	struct ath11k *ar;
4253 	struct dp_srng *err_ring;
4254 	struct dp_rxdma_ring *rx_ring;
4255 	struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
4256 	struct hal_srng *srng;
4257 	u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
4258 	enum hal_rx_buf_return_buf_manager rbm;
4259 	enum hal_reo_entr_rxdma_ecode rxdma_err_code;
4260 	struct ath11k_skb_rxcb *rxcb;
4261 	struct sk_buff *skb;
4262 	struct hal_reo_entrance_ring *entr_ring;
4263 	void *desc;
4264 	int num_buf_freed = 0;
4265 	int quota = budget;
4266 	dma_addr_t paddr;
4267 	u32 desc_bank;
4268 	void *link_desc_va;
4269 	int num_msdus;
4270 	int i;
4271 	int buf_id;
4272 
4273 	ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
4274 	err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
4275 									  mac_id)];
4276 	rx_ring = &ar->dp.rx_refill_buf_ring;
4277 
4278 	srng = &ab->hal.srng_list[err_ring->ring_id];
4279 
4280 	spin_lock_bh(&srng->lock);
4281 
4282 	ath11k_hal_srng_access_begin(ab, srng);
4283 
4284 	while (quota-- &&
4285 	       (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4286 		ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
4287 
4288 		entr_ring = (struct hal_reo_entrance_ring *)desc;
4289 		rxdma_err_code =
4290 			FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4291 				  entr_ring->info1);
4292 		ab->soc_stats.rxdma_error[rxdma_err_code]++;
4293 
4294 		link_desc_va = link_desc_banks[desc_bank].vaddr +
4295 			       (paddr - link_desc_banks[desc_bank].paddr);
4296 		ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
4297 						 msdu_cookies, &rbm);
4298 
4299 		for (i = 0; i < num_msdus; i++) {
4300 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4301 					   msdu_cookies[i]);
4302 
4303 			spin_lock_bh(&rx_ring->idr_lock);
4304 			skb = idr_find(&rx_ring->bufs_idr, buf_id);
4305 			if (!skb) {
4306 				ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
4307 					    buf_id);
4308 				spin_unlock_bh(&rx_ring->idr_lock);
4309 				continue;
4310 			}
4311 
4312 			idr_remove(&rx_ring->bufs_idr, buf_id);
4313 			spin_unlock_bh(&rx_ring->idr_lock);
4314 
4315 			rxcb = ATH11K_SKB_RXCB(skb);
4316 			dma_unmap_single(ab->dev, rxcb->paddr,
4317 					 skb->len + skb_tailroom(skb),
4318 					 DMA_FROM_DEVICE);
4319 			dev_kfree_skb_any(skb);
4320 
4321 			num_buf_freed++;
4322 		}
4323 
4324 		ath11k_dp_rx_link_desc_return(ab, desc,
4325 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4326 	}
4327 
4328 	ath11k_hal_srng_access_end(ab, srng);
4329 
4330 	spin_unlock_bh(&srng->lock);
4331 
4332 	if (num_buf_freed)
4333 		ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
4334 					   ab->hw_params.hal_params->rx_buf_rbm);
4335 
4336 	return budget - quota;
4337 }
4338 
ath11k_dp_process_reo_status(struct ath11k_base * ab)4339 void ath11k_dp_process_reo_status(struct ath11k_base *ab)
4340 {
4341 	struct ath11k_dp *dp = &ab->dp;
4342 	struct hal_srng *srng;
4343 	struct dp_reo_cmd *cmd, *tmp;
4344 	bool found = false;
4345 	u32 *reo_desc;
4346 	u16 tag;
4347 	struct hal_reo_status reo_status;
4348 
4349 	srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4350 
4351 	memset(&reo_status, 0, sizeof(reo_status));
4352 
4353 	spin_lock_bh(&srng->lock);
4354 
4355 	ath11k_hal_srng_access_begin(ab, srng);
4356 
4357 	while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4358 		tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
4359 
4360 		switch (tag) {
4361 		case HAL_REO_GET_QUEUE_STATS_STATUS:
4362 			ath11k_hal_reo_status_queue_stats(ab, reo_desc,
4363 							  &reo_status);
4364 			break;
4365 		case HAL_REO_FLUSH_QUEUE_STATUS:
4366 			ath11k_hal_reo_flush_queue_status(ab, reo_desc,
4367 							  &reo_status);
4368 			break;
4369 		case HAL_REO_FLUSH_CACHE_STATUS:
4370 			ath11k_hal_reo_flush_cache_status(ab, reo_desc,
4371 							  &reo_status);
4372 			break;
4373 		case HAL_REO_UNBLOCK_CACHE_STATUS:
4374 			ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
4375 							  &reo_status);
4376 			break;
4377 		case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4378 			ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
4379 								 &reo_status);
4380 			break;
4381 		case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4382 			ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
4383 								  &reo_status);
4384 			break;
4385 		case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4386 			ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
4387 								  &reo_status);
4388 			break;
4389 		default:
4390 			ath11k_warn(ab, "Unknown reo status type %d\n", tag);
4391 			continue;
4392 		}
4393 
4394 		spin_lock_bh(&dp->reo_cmd_lock);
4395 		list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4396 			if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4397 				found = true;
4398 				list_del(&cmd->list);
4399 				break;
4400 			}
4401 		}
4402 		spin_unlock_bh(&dp->reo_cmd_lock);
4403 
4404 		if (found) {
4405 			cmd->handler(dp, (void *)&cmd->data,
4406 				     reo_status.uniform_hdr.cmd_status);
4407 			kfree(cmd);
4408 		}
4409 
4410 		found = false;
4411 	}
4412 
4413 	ath11k_hal_srng_access_end(ab, srng);
4414 
4415 	spin_unlock_bh(&srng->lock);
4416 }
4417 
ath11k_dp_rx_pdev_free(struct ath11k_base * ab,int mac_id)4418 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
4419 {
4420 	struct ath11k *ar = ab->pdevs[mac_id].ar;
4421 
4422 	ath11k_dp_rx_pdev_srng_free(ar);
4423 	ath11k_dp_rxdma_pdev_buf_free(ar);
4424 }
4425 
ath11k_dp_rx_pdev_alloc(struct ath11k_base * ab,int mac_id)4426 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
4427 {
4428 	struct ath11k *ar = ab->pdevs[mac_id].ar;
4429 	struct ath11k_pdev_dp *dp = &ar->dp;
4430 	u32 ring_id;
4431 	int i;
4432 	int ret;
4433 
4434 	ret = ath11k_dp_rx_pdev_srng_alloc(ar);
4435 	if (ret) {
4436 		ath11k_warn(ab, "failed to setup rx srngs\n");
4437 		return ret;
4438 	}
4439 
4440 	ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
4441 	if (ret) {
4442 		ath11k_warn(ab, "failed to setup rxdma ring\n");
4443 		return ret;
4444 	}
4445 
4446 	ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4447 	ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
4448 	if (ret) {
4449 		ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4450 			    ret);
4451 		return ret;
4452 	}
4453 
4454 	if (ab->hw_params.rx_mac_buf_ring) {
4455 		for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4456 			ring_id = dp->rx_mac_buf_ring[i].ring_id;
4457 			ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4458 							  mac_id + i, HAL_RXDMA_BUF);
4459 			if (ret) {
4460 				ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4461 					    i, ret);
4462 				return ret;
4463 			}
4464 		}
4465 	}
4466 
4467 	for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4468 		ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4469 		ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4470 						  mac_id + i, HAL_RXDMA_DST);
4471 		if (ret) {
4472 			ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4473 				    i, ret);
4474 			return ret;
4475 		}
4476 	}
4477 
4478 	if (!ab->hw_params.rxdma1_enable)
4479 		goto config_refill_ring;
4480 
4481 	ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4482 	ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4483 					  mac_id, HAL_RXDMA_MONITOR_BUF);
4484 	if (ret) {
4485 		ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4486 			    ret);
4487 		return ret;
4488 	}
4489 	ret = ath11k_dp_tx_htt_srng_setup(ab,
4490 					  dp->rxdma_mon_dst_ring.ring_id,
4491 					  mac_id, HAL_RXDMA_MONITOR_DST);
4492 	if (ret) {
4493 		ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4494 			    ret);
4495 		return ret;
4496 	}
4497 	ret = ath11k_dp_tx_htt_srng_setup(ab,
4498 					  dp->rxdma_mon_desc_ring.ring_id,
4499 					  mac_id, HAL_RXDMA_MONITOR_DESC);
4500 	if (ret) {
4501 		ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4502 			    ret);
4503 		return ret;
4504 	}
4505 
4506 config_refill_ring:
4507 	for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4508 		ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
4509 		ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
4510 						  HAL_RXDMA_MONITOR_STATUS);
4511 		if (ret) {
4512 			ath11k_warn(ab,
4513 				    "failed to configure mon_status_refill_ring%d %d\n",
4514 				    i, ret);
4515 			return ret;
4516 		}
4517 	}
4518 
4519 	return 0;
4520 }
4521 
ath11k_dp_mon_set_frag_len(u32 * total_len,u32 * frag_len)4522 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
4523 {
4524 	if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
4525 		*frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
4526 		*total_len -= *frag_len;
4527 	} else {
4528 		*frag_len = *total_len;
4529 		*total_len = 0;
4530 	}
4531 }
4532 
4533 static
ath11k_dp_rx_monitor_link_desc_return(struct ath11k * ar,void * p_last_buf_addr_info,u8 mac_id)4534 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
4535 					  void *p_last_buf_addr_info,
4536 					  u8 mac_id)
4537 {
4538 	struct ath11k_pdev_dp *dp = &ar->dp;
4539 	struct dp_srng *dp_srng;
4540 	void *hal_srng;
4541 	void *src_srng_desc;
4542 	int ret = 0;
4543 
4544 	if (ar->ab->hw_params.rxdma1_enable) {
4545 		dp_srng = &dp->rxdma_mon_desc_ring;
4546 		hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4547 	} else {
4548 		dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
4549 		hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4550 	}
4551 
4552 	ath11k_hal_srng_access_begin(ar->ab, hal_srng);
4553 
4554 	src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
4555 
4556 	if (src_srng_desc) {
4557 		struct ath11k_buffer_addr *src_desc = src_srng_desc;
4558 
4559 		*src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
4560 	} else {
4561 		ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4562 			   "Monitor Link Desc Ring %d Full", mac_id);
4563 		ret = -ENOMEM;
4564 	}
4565 
4566 	ath11k_hal_srng_access_end(ar->ab, hal_srng);
4567 	return ret;
4568 }
4569 
4570 static
ath11k_dp_rx_mon_next_link_desc_get(void * rx_msdu_link_desc,dma_addr_t * paddr,u32 * sw_cookie,u8 * rbm,void ** pp_buf_addr_info)4571 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
4572 					 dma_addr_t *paddr, u32 *sw_cookie,
4573 					 u8 *rbm,
4574 					 void **pp_buf_addr_info)
4575 {
4576 	struct hal_rx_msdu_link *msdu_link = rx_msdu_link_desc;
4577 	struct ath11k_buffer_addr *buf_addr_info;
4578 
4579 	buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
4580 
4581 	ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
4582 
4583 	*pp_buf_addr_info = (void *)buf_addr_info;
4584 }
4585 
ath11k_dp_pkt_set_pktlen(struct sk_buff * skb,u32 len)4586 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
4587 {
4588 	if (skb->len > len) {
4589 		skb_trim(skb, len);
4590 	} else {
4591 		if (skb_tailroom(skb) < len - skb->len) {
4592 			if ((pskb_expand_head(skb, 0,
4593 					      len - skb->len - skb_tailroom(skb),
4594 					      GFP_ATOMIC))) {
4595 				dev_kfree_skb_any(skb);
4596 				return -ENOMEM;
4597 			}
4598 		}
4599 		skb_put(skb, (len - skb->len));
4600 	}
4601 	return 0;
4602 }
4603 
ath11k_hal_rx_msdu_list_get(struct ath11k * ar,void * msdu_link_desc,struct hal_rx_msdu_list * msdu_list,u16 * num_msdus)4604 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
4605 					void *msdu_link_desc,
4606 					struct hal_rx_msdu_list *msdu_list,
4607 					u16 *num_msdus)
4608 {
4609 	struct hal_rx_msdu_details *msdu_details = NULL;
4610 	struct rx_msdu_desc *msdu_desc_info = NULL;
4611 	struct hal_rx_msdu_link *msdu_link = NULL;
4612 	int i;
4613 	u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
4614 	u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
4615 	u8  tmp  = 0;
4616 
4617 	msdu_link = msdu_link_desc;
4618 	msdu_details = &msdu_link->msdu_link[0];
4619 
4620 	for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
4621 		if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4622 			      msdu_details[i].buf_addr_info.info0) == 0) {
4623 			msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
4624 			msdu_desc_info->info0 |= last;
4625 			;
4626 			break;
4627 		}
4628 		msdu_desc_info = &msdu_details[i].rx_msdu_info;
4629 
4630 		if (!i)
4631 			msdu_desc_info->info0 |= first;
4632 		else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
4633 			msdu_desc_info->info0 |= last;
4634 		msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
4635 		msdu_list->msdu_info[i].msdu_len =
4636 			 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
4637 		msdu_list->sw_cookie[i] =
4638 			FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
4639 				  msdu_details[i].buf_addr_info.info1);
4640 		tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
4641 				msdu_details[i].buf_addr_info.info1);
4642 		msdu_list->rbm[i] = tmp;
4643 	}
4644 	*num_msdus = i;
4645 }
4646 
ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id,u32 * ppdu_id,u32 * rx_bufs_used)4647 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
4648 					u32 *rx_bufs_used)
4649 {
4650 	u32 ret = 0;
4651 
4652 	if ((*ppdu_id < msdu_ppdu_id) &&
4653 	    ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
4654 		*ppdu_id = msdu_ppdu_id;
4655 		ret = msdu_ppdu_id;
4656 	} else if ((*ppdu_id > msdu_ppdu_id) &&
4657 		((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
4658 		/* mon_dst is behind than mon_status
4659 		 * skip dst_ring and free it
4660 		 */
4661 		*rx_bufs_used += 1;
4662 		*ppdu_id = msdu_ppdu_id;
4663 		ret = msdu_ppdu_id;
4664 	}
4665 	return ret;
4666 }
4667 
ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info * info,bool * is_frag,u32 * total_len,u32 * frag_len,u32 * msdu_cnt)4668 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
4669 				      bool *is_frag, u32 *total_len,
4670 				      u32 *frag_len, u32 *msdu_cnt)
4671 {
4672 	if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
4673 		if (!*is_frag) {
4674 			*total_len = info->msdu_len;
4675 			*is_frag = true;
4676 		}
4677 		ath11k_dp_mon_set_frag_len(total_len,
4678 					   frag_len);
4679 	} else {
4680 		if (*is_frag) {
4681 			ath11k_dp_mon_set_frag_len(total_len,
4682 						   frag_len);
4683 		} else {
4684 			*frag_len = info->msdu_len;
4685 		}
4686 		*is_frag = false;
4687 		*msdu_cnt -= 1;
4688 	}
4689 }
4690 
4691 /* clang stack usage explodes if this is inlined */
4692 static noinline_for_stack
ath11k_dp_rx_mon_mpdu_pop(struct ath11k * ar,int mac_id,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,u32 * npackets,u32 * ppdu_id)4693 u32 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
4694 			      void *ring_entry, struct sk_buff **head_msdu,
4695 			      struct sk_buff **tail_msdu, u32 *npackets,
4696 			      u32 *ppdu_id)
4697 {
4698 	struct ath11k_pdev_dp *dp = &ar->dp;
4699 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4700 	struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
4701 	struct sk_buff *msdu = NULL, *last = NULL;
4702 	struct hal_rx_msdu_list msdu_list;
4703 	void *p_buf_addr_info, *p_last_buf_addr_info;
4704 	struct hal_rx_desc *rx_desc;
4705 	void *rx_msdu_link_desc;
4706 	dma_addr_t paddr;
4707 	u16 num_msdus = 0;
4708 	u32 rx_buf_size, rx_pkt_offset, sw_cookie;
4709 	u32 rx_bufs_used = 0, i = 0;
4710 	u32 msdu_ppdu_id = 0, msdu_cnt = 0;
4711 	u32 total_len = 0, frag_len = 0;
4712 	bool is_frag, is_first_msdu;
4713 	bool drop_mpdu = false;
4714 	struct ath11k_skb_rxcb *rxcb;
4715 	struct hal_reo_entrance_ring *ent_desc = ring_entry;
4716 	int buf_id;
4717 	u32 rx_link_buf_info[2];
4718 	u8 rbm;
4719 
4720 	if (!ar->ab->hw_params.rxdma1_enable)
4721 		rx_ring = &dp->rx_refill_buf_ring;
4722 
4723 	ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
4724 					    &sw_cookie,
4725 					    &p_last_buf_addr_info, &rbm,
4726 					    &msdu_cnt);
4727 
4728 	if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
4729 		      ent_desc->info1) ==
4730 		      HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4731 		u8 rxdma_err =
4732 			FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4733 				  ent_desc->info1);
4734 		if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
4735 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
4736 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
4737 			drop_mpdu = true;
4738 			pmon->rx_mon_stats.dest_mpdu_drop++;
4739 		}
4740 	}
4741 
4742 	is_frag = false;
4743 	is_first_msdu = true;
4744 
4745 	do {
4746 		if (pmon->mon_last_linkdesc_paddr == paddr) {
4747 			pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
4748 			return rx_bufs_used;
4749 		}
4750 
4751 		if (ar->ab->hw_params.rxdma1_enable)
4752 			rx_msdu_link_desc =
4753 				(void *)pmon->link_desc_banks[sw_cookie].vaddr +
4754 				(paddr - pmon->link_desc_banks[sw_cookie].paddr);
4755 		else
4756 			rx_msdu_link_desc =
4757 				(void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4758 				(paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
4759 
4760 		ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
4761 					    &num_msdus);
4762 
4763 		for (i = 0; i < num_msdus; i++) {
4764 			u32 l2_hdr_offset;
4765 
4766 			if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
4767 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4768 					   "i %d last_cookie %d is same\n",
4769 					   i, pmon->mon_last_buf_cookie);
4770 				drop_mpdu = true;
4771 				pmon->rx_mon_stats.dup_mon_buf_cnt++;
4772 				continue;
4773 			}
4774 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4775 					   msdu_list.sw_cookie[i]);
4776 
4777 			spin_lock_bh(&rx_ring->idr_lock);
4778 			msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4779 			spin_unlock_bh(&rx_ring->idr_lock);
4780 			if (!msdu) {
4781 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4782 					   "msdu_pop: invalid buf_id %d\n", buf_id);
4783 				goto next_msdu;
4784 			}
4785 			rxcb = ATH11K_SKB_RXCB(msdu);
4786 			if (!rxcb->unmapped) {
4787 				dma_unmap_single(ar->ab->dev, rxcb->paddr,
4788 						 msdu->len +
4789 						 skb_tailroom(msdu),
4790 						 DMA_FROM_DEVICE);
4791 				rxcb->unmapped = 1;
4792 			}
4793 			if (drop_mpdu) {
4794 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4795 					   "i %d drop msdu %p *ppdu_id %x\n",
4796 					   i, msdu, *ppdu_id);
4797 				dev_kfree_skb_any(msdu);
4798 				msdu = NULL;
4799 				goto next_msdu;
4800 			}
4801 
4802 			rx_desc = (struct hal_rx_desc *)msdu->data;
4803 
4804 			rx_pkt_offset = sizeof(struct hal_rx_desc);
4805 			l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
4806 
4807 			if (is_first_msdu) {
4808 				if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
4809 					drop_mpdu = true;
4810 					dev_kfree_skb_any(msdu);
4811 					msdu = NULL;
4812 					pmon->mon_last_linkdesc_paddr = paddr;
4813 					goto next_msdu;
4814 				}
4815 
4816 				msdu_ppdu_id =
4817 					ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc);
4818 
4819 				if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
4820 								 ppdu_id,
4821 								 &rx_bufs_used)) {
4822 					if (rx_bufs_used) {
4823 						drop_mpdu = true;
4824 						dev_kfree_skb_any(msdu);
4825 						msdu = NULL;
4826 						goto next_msdu;
4827 					}
4828 					return rx_bufs_used;
4829 				}
4830 				pmon->mon_last_linkdesc_paddr = paddr;
4831 				is_first_msdu = false;
4832 			}
4833 			ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
4834 						  &is_frag, &total_len,
4835 						  &frag_len, &msdu_cnt);
4836 			rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
4837 
4838 			ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
4839 
4840 			if (!(*head_msdu))
4841 				*head_msdu = msdu;
4842 			else if (last)
4843 				last->next = msdu;
4844 
4845 			last = msdu;
4846 next_msdu:
4847 			pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
4848 			rx_bufs_used++;
4849 			spin_lock_bh(&rx_ring->idr_lock);
4850 			idr_remove(&rx_ring->bufs_idr, buf_id);
4851 			spin_unlock_bh(&rx_ring->idr_lock);
4852 		}
4853 
4854 		ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
4855 
4856 		ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
4857 						    &sw_cookie, &rbm,
4858 						    &p_buf_addr_info);
4859 
4860 		if (ar->ab->hw_params.rxdma1_enable) {
4861 			if (ath11k_dp_rx_monitor_link_desc_return(ar,
4862 								  p_last_buf_addr_info,
4863 								  dp->mac_id))
4864 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4865 					   "dp_rx_monitor_link_desc_return failed");
4866 		} else {
4867 			ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
4868 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4869 		}
4870 
4871 		p_last_buf_addr_info = p_buf_addr_info;
4872 
4873 	} while (paddr && msdu_cnt);
4874 
4875 	if (last)
4876 		last->next = NULL;
4877 
4878 	*tail_msdu = msdu;
4879 
4880 	if (msdu_cnt == 0)
4881 		*npackets = 1;
4882 
4883 	return rx_bufs_used;
4884 }
4885 
ath11k_dp_rx_msdus_set_payload(struct ath11k * ar,struct sk_buff * msdu)4886 static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu)
4887 {
4888 	u32 rx_pkt_offset, l2_hdr_offset;
4889 
4890 	rx_pkt_offset = ar->ab->hw_params.hal_desc_sz;
4891 	l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab,
4892 						      (struct hal_rx_desc *)msdu->data);
4893 	skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
4894 }
4895 
4896 static struct sk_buff *
ath11k_dp_rx_mon_merg_msdus(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * last_msdu,struct ieee80211_rx_status * rxs,bool * fcs_err)4897 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
4898 			    u32 mac_id, struct sk_buff *head_msdu,
4899 			    struct sk_buff *last_msdu,
4900 			    struct ieee80211_rx_status *rxs, bool *fcs_err)
4901 {
4902 	struct ath11k_base *ab = ar->ab;
4903 	struct sk_buff *msdu, *prev_buf;
4904 	struct hal_rx_desc *rx_desc;
4905 	char *hdr_desc;
4906 	u8 *dest, decap_format;
4907 	struct ieee80211_hdr_3addr *wh;
4908 	struct rx_attention *rx_attention;
4909 	u32 err_bitmap;
4910 
4911 	if (!head_msdu)
4912 		goto err_merge_fail;
4913 
4914 	rx_desc = (struct hal_rx_desc *)head_msdu->data;
4915 	rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc);
4916 	err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
4917 
4918 	if (err_bitmap & DP_RX_MPDU_ERR_FCS)
4919 		*fcs_err = true;
4920 
4921 	if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention))
4922 		return NULL;
4923 
4924 	decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc);
4925 
4926 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
4927 
4928 	if (decap_format == DP_RX_DECAP_TYPE_RAW) {
4929 		ath11k_dp_rx_msdus_set_payload(ar, head_msdu);
4930 
4931 		prev_buf = head_msdu;
4932 		msdu = head_msdu->next;
4933 
4934 		while (msdu) {
4935 			ath11k_dp_rx_msdus_set_payload(ar, msdu);
4936 
4937 			prev_buf = msdu;
4938 			msdu = msdu->next;
4939 		}
4940 
4941 		prev_buf->next = NULL;
4942 
4943 		skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
4944 	} else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
4945 		u8 qos_pkt = 0;
4946 
4947 		rx_desc = (struct hal_rx_desc *)head_msdu->data;
4948 		hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
4949 
4950 		/* Base size */
4951 		wh = (struct ieee80211_hdr_3addr *)hdr_desc;
4952 
4953 		if (ieee80211_is_data_qos(wh->frame_control))
4954 			qos_pkt = 1;
4955 
4956 		msdu = head_msdu;
4957 
4958 		while (msdu) {
4959 			ath11k_dp_rx_msdus_set_payload(ar, msdu);
4960 			if (qos_pkt) {
4961 				dest = skb_push(msdu, sizeof(__le16));
4962 				if (!dest)
4963 					goto err_merge_fail;
4964 				memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr));
4965 			}
4966 			prev_buf = msdu;
4967 			msdu = msdu->next;
4968 		}
4969 		dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
4970 		if (!dest)
4971 			goto err_merge_fail;
4972 
4973 		ath11k_dbg(ab, ATH11K_DBG_DATA,
4974 			   "mpdu_buf %p mpdu_buf->len %u",
4975 			   prev_buf, prev_buf->len);
4976 	} else {
4977 		ath11k_dbg(ab, ATH11K_DBG_DATA,
4978 			   "decap format %d is not supported!\n",
4979 			   decap_format);
4980 		goto err_merge_fail;
4981 	}
4982 
4983 	return head_msdu;
4984 
4985 err_merge_fail:
4986 	return NULL;
4987 }
4988 
4989 static void
ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)4990 ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status,
4991 				u8 *rtap_buf)
4992 {
4993 	u32 rtap_len = 0;
4994 
4995 	put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]);
4996 	rtap_len += 2;
4997 
4998 	put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]);
4999 	rtap_len += 2;
5000 
5001 	put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]);
5002 	rtap_len += 2;
5003 
5004 	put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]);
5005 	rtap_len += 2;
5006 
5007 	put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]);
5008 	rtap_len += 2;
5009 
5010 	put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]);
5011 }
5012 
5013 static void
ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)5014 ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status,
5015 				   u8 *rtap_buf)
5016 {
5017 	u32 rtap_len = 0;
5018 
5019 	put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]);
5020 	rtap_len += 2;
5021 
5022 	put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]);
5023 	rtap_len += 2;
5024 
5025 	rtap_buf[rtap_len] = rx_status->he_RU[0];
5026 	rtap_len += 1;
5027 
5028 	rtap_buf[rtap_len] = rx_status->he_RU[1];
5029 	rtap_len += 1;
5030 
5031 	rtap_buf[rtap_len] = rx_status->he_RU[2];
5032 	rtap_len += 1;
5033 
5034 	rtap_buf[rtap_len] = rx_status->he_RU[3];
5035 }
5036 
ath11k_update_radiotap(struct ath11k * ar,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * mon_skb,struct ieee80211_rx_status * rxs)5037 static void ath11k_update_radiotap(struct ath11k *ar,
5038 				   struct hal_rx_mon_ppdu_info *ppduinfo,
5039 				   struct sk_buff *mon_skb,
5040 				   struct ieee80211_rx_status *rxs)
5041 {
5042 	struct ieee80211_supported_band *sband;
5043 	u8 *ptr = NULL;
5044 
5045 	rxs->flag |= RX_FLAG_MACTIME_START;
5046 	rxs->signal = ppduinfo->rssi_comb + ATH11K_DEFAULT_NOISE_FLOOR;
5047 
5048 	if (ppduinfo->nss)
5049 		rxs->nss = ppduinfo->nss;
5050 
5051 	if (ppduinfo->he_mu_flags) {
5052 		rxs->flag |= RX_FLAG_RADIOTAP_HE_MU;
5053 		rxs->encoding = RX_ENC_HE;
5054 		ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu));
5055 		ath11k_dp_rx_update_radiotap_he_mu(ppduinfo, ptr);
5056 	} else if (ppduinfo->he_flags) {
5057 		rxs->flag |= RX_FLAG_RADIOTAP_HE;
5058 		rxs->encoding = RX_ENC_HE;
5059 		ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he));
5060 		ath11k_dp_rx_update_radiotap_he(ppduinfo, ptr);
5061 		rxs->rate_idx = ppduinfo->rate;
5062 	} else if (ppduinfo->vht_flags) {
5063 		rxs->encoding = RX_ENC_VHT;
5064 		rxs->rate_idx = ppduinfo->rate;
5065 	} else if (ppduinfo->ht_flags) {
5066 		rxs->encoding = RX_ENC_HT;
5067 		rxs->rate_idx = ppduinfo->rate;
5068 	} else {
5069 		rxs->encoding = RX_ENC_LEGACY;
5070 		sband = &ar->mac.sbands[rxs->band];
5071 		rxs->rate_idx = ath11k_mac_hw_rate_to_idx(sband, ppduinfo->rate,
5072 							  ppduinfo->cck_flag);
5073 	}
5074 
5075 	rxs->mactime = ppduinfo->tsft;
5076 }
5077 
ath11k_dp_rx_mon_deliver(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * tail_msdu,struct napi_struct * napi)5078 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
5079 				    struct sk_buff *head_msdu,
5080 				    struct hal_rx_mon_ppdu_info *ppduinfo,
5081 				    struct sk_buff *tail_msdu,
5082 				    struct napi_struct *napi)
5083 {
5084 	struct ath11k_pdev_dp *dp = &ar->dp;
5085 	struct sk_buff *mon_skb, *skb_next, *header;
5086 	struct ieee80211_rx_status *rxs = &dp->rx_status;
5087 	bool fcs_err = false;
5088 
5089 	mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
5090 					      tail_msdu, rxs, &fcs_err);
5091 
5092 	if (!mon_skb)
5093 		goto mon_deliver_fail;
5094 
5095 	header = mon_skb;
5096 
5097 	rxs->flag = 0;
5098 
5099 	if (fcs_err)
5100 		rxs->flag = RX_FLAG_FAILED_FCS_CRC;
5101 
5102 	do {
5103 		skb_next = mon_skb->next;
5104 		if (!skb_next)
5105 			rxs->flag &= ~RX_FLAG_AMSDU_MORE;
5106 		else
5107 			rxs->flag |= RX_FLAG_AMSDU_MORE;
5108 
5109 		if (mon_skb == header) {
5110 			header = NULL;
5111 			rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
5112 		} else {
5113 			rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
5114 		}
5115 		rxs->flag |= RX_FLAG_ONLY_MONITOR;
5116 		ath11k_update_radiotap(ar, ppduinfo, mon_skb, rxs);
5117 
5118 		ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs);
5119 		mon_skb = skb_next;
5120 	} while (mon_skb);
5121 	rxs->flag = 0;
5122 
5123 	return 0;
5124 
5125 mon_deliver_fail:
5126 	mon_skb = head_msdu;
5127 	while (mon_skb) {
5128 		skb_next = mon_skb->next;
5129 		dev_kfree_skb_any(mon_skb);
5130 		mon_skb = skb_next;
5131 	}
5132 	return -EINVAL;
5133 }
5134 
5135 /* The destination ring processing is stuck if the destination is not
5136  * moving while status ring moves 16 PPDU. The destination ring processing
5137  * skips this destination ring PPDU as a workaround.
5138  */
5139 #define MON_DEST_RING_STUCK_MAX_CNT 16
5140 
ath11k_dp_rx_mon_dest_process(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)5141 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
5142 					  u32 quota, struct napi_struct *napi)
5143 {
5144 	struct ath11k_pdev_dp *dp = &ar->dp;
5145 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5146 	const struct ath11k_hw_hal_params *hal_params;
5147 	void *ring_entry;
5148 	struct hal_srng *mon_dst_srng;
5149 	u32 ppdu_id;
5150 	u32 rx_bufs_used;
5151 	u32 ring_id;
5152 	struct ath11k_pdev_mon_stats *rx_mon_stats;
5153 	u32	 npackets = 0;
5154 	u32 mpdu_rx_bufs_used;
5155 
5156 	if (ar->ab->hw_params.rxdma1_enable)
5157 		ring_id = dp->rxdma_mon_dst_ring.ring_id;
5158 	else
5159 		ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
5160 
5161 	mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
5162 
5163 	spin_lock_bh(&pmon->mon_lock);
5164 
5165 	spin_lock_bh(&mon_dst_srng->lock);
5166 	ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5167 
5168 	ppdu_id = pmon->mon_ppdu_info.ppdu_id;
5169 	rx_bufs_used = 0;
5170 	rx_mon_stats = &pmon->rx_mon_stats;
5171 
5172 	while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5173 		struct sk_buff *head_msdu, *tail_msdu;
5174 
5175 		head_msdu = NULL;
5176 		tail_msdu = NULL;
5177 
5178 		mpdu_rx_bufs_used = ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
5179 							      &head_msdu,
5180 							      &tail_msdu,
5181 							      &npackets, &ppdu_id);
5182 
5183 		rx_bufs_used += mpdu_rx_bufs_used;
5184 
5185 		if (mpdu_rx_bufs_used) {
5186 			dp->mon_dest_ring_stuck_cnt = 0;
5187 		} else {
5188 			dp->mon_dest_ring_stuck_cnt++;
5189 			rx_mon_stats->dest_mon_not_reaped++;
5190 		}
5191 
5192 		if (dp->mon_dest_ring_stuck_cnt > MON_DEST_RING_STUCK_MAX_CNT) {
5193 			rx_mon_stats->dest_mon_stuck++;
5194 			ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5195 				   "status ring ppdu_id=%d dest ring ppdu_id=%d mon_dest_ring_stuck_cnt=%d dest_mon_not_reaped=%u dest_mon_stuck=%u\n",
5196 				   pmon->mon_ppdu_info.ppdu_id, ppdu_id,
5197 				   dp->mon_dest_ring_stuck_cnt,
5198 				   rx_mon_stats->dest_mon_not_reaped,
5199 				   rx_mon_stats->dest_mon_stuck);
5200 			pmon->mon_ppdu_info.ppdu_id = ppdu_id;
5201 			continue;
5202 		}
5203 
5204 		if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
5205 			pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5206 			ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5207 				   "dest_rx: new ppdu_id %x != status ppdu_id %x dest_mon_not_reaped = %u dest_mon_stuck = %u\n",
5208 				   ppdu_id, pmon->mon_ppdu_info.ppdu_id,
5209 				   rx_mon_stats->dest_mon_not_reaped,
5210 				   rx_mon_stats->dest_mon_stuck);
5211 			break;
5212 		}
5213 		if (head_msdu && tail_msdu) {
5214 			ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
5215 						 &pmon->mon_ppdu_info,
5216 						 tail_msdu, napi);
5217 			rx_mon_stats->dest_mpdu_done++;
5218 		}
5219 
5220 		ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5221 								mon_dst_srng);
5222 	}
5223 	ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5224 	spin_unlock_bh(&mon_dst_srng->lock);
5225 
5226 	spin_unlock_bh(&pmon->mon_lock);
5227 
5228 	if (rx_bufs_used) {
5229 		rx_mon_stats->dest_ppdu_done++;
5230 		hal_params = ar->ab->hw_params.hal_params;
5231 
5232 		if (ar->ab->hw_params.rxdma1_enable)
5233 			ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5234 						   &dp->rxdma_mon_buf_ring,
5235 						   rx_bufs_used,
5236 						   hal_params->rx_buf_rbm);
5237 		else
5238 			ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5239 						   &dp->rx_refill_buf_ring,
5240 						   rx_bufs_used,
5241 						   hal_params->rx_buf_rbm);
5242 	}
5243 }
5244 
ath11k_dp_rx_process_mon_status(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5245 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
5246 				    struct napi_struct *napi, int budget)
5247 {
5248 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5249 	enum hal_rx_mon_status hal_status;
5250 	struct sk_buff *skb;
5251 	struct sk_buff_head skb_list;
5252 	struct ath11k_peer *peer;
5253 	struct ath11k_sta *arsta;
5254 	int num_buffs_reaped = 0;
5255 	u32 rx_buf_sz;
5256 	u16 log_type;
5257 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&ar->dp.mon_data;
5258 	struct ath11k_pdev_mon_stats *rx_mon_stats = &pmon->rx_mon_stats;
5259 	struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
5260 
5261 	__skb_queue_head_init(&skb_list);
5262 
5263 	num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
5264 							     &skb_list);
5265 	if (!num_buffs_reaped)
5266 		goto exit;
5267 
5268 	memset(ppdu_info, 0, sizeof(*ppdu_info));
5269 	ppdu_info->peer_id = HAL_INVALID_PEERID;
5270 
5271 	while ((skb = __skb_dequeue(&skb_list))) {
5272 		if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) {
5273 			log_type = ATH11K_PKTLOG_TYPE_LITE_RX;
5274 			rx_buf_sz = DP_RX_BUFFER_SIZE_LITE;
5275 		} else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) {
5276 			log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF;
5277 			rx_buf_sz = DP_RX_BUFFER_SIZE;
5278 		} else {
5279 			log_type = ATH11K_PKTLOG_TYPE_INVALID;
5280 			rx_buf_sz = 0;
5281 		}
5282 
5283 		if (log_type != ATH11K_PKTLOG_TYPE_INVALID)
5284 			trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5285 
5286 		memset(ppdu_info, 0, sizeof(*ppdu_info));
5287 		ppdu_info->peer_id = HAL_INVALID_PEERID;
5288 		hal_status = ath11k_hal_rx_parse_mon_status(ab, ppdu_info, skb);
5289 
5290 		if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5291 		    pmon->mon_ppdu_status == DP_PPDU_STATUS_START &&
5292 		    hal_status == HAL_TLV_STATUS_PPDU_DONE) {
5293 			rx_mon_stats->status_ppdu_done++;
5294 			pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
5295 			if (!ab->hw_params.full_monitor_mode) {
5296 				ath11k_dp_rx_mon_dest_process(ar, mac_id,
5297 							      budget, napi);
5298 				pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5299 			}
5300 		}
5301 
5302 		if (ppdu_info->peer_id == HAL_INVALID_PEERID ||
5303 		    hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
5304 			dev_kfree_skb_any(skb);
5305 			continue;
5306 		}
5307 
5308 		rcu_read_lock();
5309 		spin_lock_bh(&ab->base_lock);
5310 		peer = ath11k_peer_find_by_id(ab, ppdu_info->peer_id);
5311 
5312 		if (!peer || !peer->sta) {
5313 			ath11k_dbg(ab, ATH11K_DBG_DATA,
5314 				   "failed to find the peer with peer_id %d\n",
5315 				   ppdu_info->peer_id);
5316 			goto next_skb;
5317 		}
5318 
5319 		arsta = ath11k_sta_to_arsta(peer->sta);
5320 		ath11k_dp_rx_update_peer_stats(arsta, ppdu_info);
5321 
5322 		if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
5323 			trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5324 
5325 next_skb:
5326 		spin_unlock_bh(&ab->base_lock);
5327 		rcu_read_unlock();
5328 
5329 		dev_kfree_skb_any(skb);
5330 		memset(ppdu_info, 0, sizeof(*ppdu_info));
5331 		ppdu_info->peer_id = HAL_INVALID_PEERID;
5332 	}
5333 exit:
5334 	return num_buffs_reaped;
5335 }
5336 
5337 static u32
ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k * ar,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,struct hal_sw_mon_ring_entries * sw_mon_entries)5338 ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k *ar,
5339 			       void *ring_entry, struct sk_buff **head_msdu,
5340 			       struct sk_buff **tail_msdu,
5341 			       struct hal_sw_mon_ring_entries *sw_mon_entries)
5342 {
5343 	struct ath11k_pdev_dp *dp = &ar->dp;
5344 	struct ath11k_mon_data *pmon = &dp->mon_data;
5345 	struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
5346 	struct sk_buff *msdu = NULL, *last = NULL;
5347 	struct hal_sw_monitor_ring *sw_desc = ring_entry;
5348 	struct hal_rx_msdu_list msdu_list;
5349 	struct hal_rx_desc *rx_desc;
5350 	struct ath11k_skb_rxcb *rxcb;
5351 	void *rx_msdu_link_desc;
5352 	void *p_buf_addr_info, *p_last_buf_addr_info;
5353 	int buf_id, i = 0;
5354 	u32 rx_buf_size, rx_pkt_offset, l2_hdr_offset;
5355 	u32 rx_bufs_used = 0, msdu_cnt = 0;
5356 	u32 total_len = 0, frag_len = 0, sw_cookie;
5357 	u16 num_msdus = 0;
5358 	u8 rxdma_err, rbm;
5359 	bool is_frag, is_first_msdu;
5360 	bool drop_mpdu = false;
5361 
5362 	ath11k_hal_rx_sw_mon_ring_buf_paddr_get(ring_entry, sw_mon_entries);
5363 
5364 	sw_cookie = sw_mon_entries->mon_dst_sw_cookie;
5365 	sw_mon_entries->end_of_ppdu = false;
5366 	sw_mon_entries->drop_ppdu = false;
5367 	p_last_buf_addr_info = sw_mon_entries->dst_buf_addr_info;
5368 	msdu_cnt = sw_mon_entries->msdu_cnt;
5369 
5370 	sw_mon_entries->end_of_ppdu =
5371 		FIELD_GET(HAL_SW_MON_RING_INFO0_END_OF_PPDU, sw_desc->info0);
5372 	if (sw_mon_entries->end_of_ppdu)
5373 		return rx_bufs_used;
5374 
5375 	if (FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON,
5376 		      sw_desc->info0) ==
5377 		      HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
5378 		rxdma_err =
5379 			FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE,
5380 				  sw_desc->info0);
5381 		if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
5382 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
5383 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
5384 			pmon->rx_mon_stats.dest_mpdu_drop++;
5385 			drop_mpdu = true;
5386 		}
5387 	}
5388 
5389 	is_frag = false;
5390 	is_first_msdu = true;
5391 
5392 	do {
5393 		rx_msdu_link_desc =
5394 			(u8 *)pmon->link_desc_banks[sw_cookie].vaddr +
5395 			(sw_mon_entries->mon_dst_paddr -
5396 			 pmon->link_desc_banks[sw_cookie].paddr);
5397 
5398 		ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
5399 					    &num_msdus);
5400 
5401 		for (i = 0; i < num_msdus; i++) {
5402 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
5403 					   msdu_list.sw_cookie[i]);
5404 
5405 			spin_lock_bh(&rx_ring->idr_lock);
5406 			msdu = idr_find(&rx_ring->bufs_idr, buf_id);
5407 			if (!msdu) {
5408 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5409 					   "full mon msdu_pop: invalid buf_id %d\n",
5410 					    buf_id);
5411 				spin_unlock_bh(&rx_ring->idr_lock);
5412 				goto next_msdu;
5413 			}
5414 			idr_remove(&rx_ring->bufs_idr, buf_id);
5415 			spin_unlock_bh(&rx_ring->idr_lock);
5416 
5417 			rxcb = ATH11K_SKB_RXCB(msdu);
5418 			if (!rxcb->unmapped) {
5419 				dma_unmap_single(ar->ab->dev, rxcb->paddr,
5420 						 msdu->len +
5421 						 skb_tailroom(msdu),
5422 						 DMA_FROM_DEVICE);
5423 				rxcb->unmapped = 1;
5424 			}
5425 			if (drop_mpdu) {
5426 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5427 					   "full mon: i %d drop msdu %p *ppdu_id %x\n",
5428 					   i, msdu, sw_mon_entries->ppdu_id);
5429 				dev_kfree_skb_any(msdu);
5430 				msdu_cnt--;
5431 				goto next_msdu;
5432 			}
5433 
5434 			rx_desc = (struct hal_rx_desc *)msdu->data;
5435 
5436 			rx_pkt_offset = sizeof(struct hal_rx_desc);
5437 			l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
5438 
5439 			if (is_first_msdu) {
5440 				if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
5441 					drop_mpdu = true;
5442 					dev_kfree_skb_any(msdu);
5443 					msdu = NULL;
5444 					goto next_msdu;
5445 				}
5446 				is_first_msdu = false;
5447 			}
5448 
5449 			ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
5450 						  &is_frag, &total_len,
5451 						  &frag_len, &msdu_cnt);
5452 
5453 			rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
5454 
5455 			ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
5456 
5457 			if (!(*head_msdu))
5458 				*head_msdu = msdu;
5459 			else if (last)
5460 				last->next = msdu;
5461 
5462 			last = msdu;
5463 next_msdu:
5464 			rx_bufs_used++;
5465 		}
5466 
5467 		ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc,
5468 						    &sw_mon_entries->mon_dst_paddr,
5469 						    &sw_mon_entries->mon_dst_sw_cookie,
5470 						    &rbm,
5471 						    &p_buf_addr_info);
5472 
5473 		if (ath11k_dp_rx_monitor_link_desc_return(ar,
5474 							  p_last_buf_addr_info,
5475 							  dp->mac_id))
5476 			ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5477 				   "full mon: dp_rx_monitor_link_desc_return failed\n");
5478 
5479 		p_last_buf_addr_info = p_buf_addr_info;
5480 
5481 	} while (sw_mon_entries->mon_dst_paddr && msdu_cnt);
5482 
5483 	if (last)
5484 		last->next = NULL;
5485 
5486 	*tail_msdu = msdu;
5487 
5488 	return rx_bufs_used;
5489 }
5490 
ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu,struct sk_buff * head,struct sk_buff * tail)5491 static int ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp *dp,
5492 					      struct dp_full_mon_mpdu *mon_mpdu,
5493 					      struct sk_buff *head,
5494 					      struct sk_buff *tail)
5495 {
5496 	mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
5497 	if (!mon_mpdu)
5498 		return -ENOMEM;
5499 
5500 	list_add_tail(&mon_mpdu->list, &dp->dp_full_mon_mpdu_list);
5501 	mon_mpdu->head = head;
5502 	mon_mpdu->tail = tail;
5503 
5504 	return 0;
5505 }
5506 
ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu)5507 static void ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp *dp,
5508 					    struct dp_full_mon_mpdu *mon_mpdu)
5509 {
5510 	struct dp_full_mon_mpdu *tmp;
5511 	struct sk_buff *tmp_msdu, *skb_next;
5512 
5513 	if (list_empty(&dp->dp_full_mon_mpdu_list))
5514 		return;
5515 
5516 	list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5517 		list_del(&mon_mpdu->list);
5518 
5519 		tmp_msdu = mon_mpdu->head;
5520 		while (tmp_msdu) {
5521 			skb_next = tmp_msdu->next;
5522 			dev_kfree_skb_any(tmp_msdu);
5523 			tmp_msdu = skb_next;
5524 		}
5525 
5526 		kfree(mon_mpdu);
5527 	}
5528 }
5529 
ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k * ar,int mac_id,struct ath11k_mon_data * pmon,struct napi_struct * napi)5530 static int ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k *ar,
5531 					      int mac_id,
5532 					      struct ath11k_mon_data *pmon,
5533 					      struct napi_struct *napi)
5534 {
5535 	struct ath11k_pdev_mon_stats *rx_mon_stats;
5536 	struct dp_full_mon_mpdu *tmp;
5537 	struct dp_full_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
5538 	struct sk_buff *head_msdu, *tail_msdu;
5539 	struct ath11k_base *ab = ar->ab;
5540 	struct ath11k_dp *dp = &ab->dp;
5541 	int ret;
5542 
5543 	rx_mon_stats = &pmon->rx_mon_stats;
5544 
5545 	list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5546 		list_del(&mon_mpdu->list);
5547 		head_msdu = mon_mpdu->head;
5548 		tail_msdu = mon_mpdu->tail;
5549 		if (head_msdu && tail_msdu) {
5550 			ret = ath11k_dp_rx_mon_deliver(ar, mac_id, head_msdu,
5551 						       &pmon->mon_ppdu_info,
5552 						       tail_msdu, napi);
5553 			rx_mon_stats->dest_mpdu_done++;
5554 			ath11k_dbg(ar->ab, ATH11K_DBG_DATA, "full mon: deliver ppdu\n");
5555 		}
5556 		kfree(mon_mpdu);
5557 	}
5558 
5559 	return ret;
5560 }
5561 
5562 static int
ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5563 ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base *ab, int mac_id,
5564 					  struct napi_struct *napi, int budget)
5565 {
5566 	struct ath11k *ar = ab->pdevs[mac_id].ar;
5567 	struct ath11k_pdev_dp *dp = &ar->dp;
5568 	struct ath11k_mon_data *pmon = &dp->mon_data;
5569 	struct hal_sw_mon_ring_entries *sw_mon_entries;
5570 	int quota = 0, work = 0, count;
5571 
5572 	sw_mon_entries = &pmon->sw_mon_entries;
5573 
5574 	while (pmon->hold_mon_dst_ring) {
5575 		quota = ath11k_dp_rx_process_mon_status(ab, mac_id,
5576 							napi, 1);
5577 		if (pmon->buf_state == DP_MON_STATUS_MATCH) {
5578 			count = sw_mon_entries->status_buf_count;
5579 			if (count > 1) {
5580 				quota += ath11k_dp_rx_process_mon_status(ab, mac_id,
5581 									 napi, count);
5582 			}
5583 
5584 			ath11k_dp_rx_full_mon_deliver_ppdu(ar, dp->mac_id,
5585 							   pmon, napi);
5586 			pmon->hold_mon_dst_ring = false;
5587 		} else if (!pmon->mon_status_paddr ||
5588 			   pmon->buf_state == DP_MON_STATUS_LEAD) {
5589 			sw_mon_entries->drop_ppdu = true;
5590 			pmon->hold_mon_dst_ring = false;
5591 		}
5592 
5593 		if (!quota)
5594 			break;
5595 
5596 		work += quota;
5597 	}
5598 
5599 	if (sw_mon_entries->drop_ppdu)
5600 		ath11k_dp_rx_full_mon_drop_ppdu(&ab->dp, pmon->mon_mpdu);
5601 
5602 	return work;
5603 }
5604 
ath11k_dp_full_mon_process_rx(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5605 static int ath11k_dp_full_mon_process_rx(struct ath11k_base *ab, int mac_id,
5606 					 struct napi_struct *napi, int budget)
5607 {
5608 	struct ath11k *ar = ab->pdevs[mac_id].ar;
5609 	struct ath11k_pdev_dp *dp = &ar->dp;
5610 	struct ath11k_mon_data *pmon = &dp->mon_data;
5611 	struct hal_sw_mon_ring_entries *sw_mon_entries;
5612 	struct ath11k_pdev_mon_stats *rx_mon_stats;
5613 	struct sk_buff *head_msdu, *tail_msdu;
5614 	struct hal_srng *mon_dst_srng;
5615 	void *ring_entry;
5616 	u32 rx_bufs_used = 0, mpdu_rx_bufs_used;
5617 	int quota = 0, ret;
5618 	bool break_dst_ring = false;
5619 
5620 	spin_lock_bh(&pmon->mon_lock);
5621 
5622 	sw_mon_entries = &pmon->sw_mon_entries;
5623 	rx_mon_stats = &pmon->rx_mon_stats;
5624 
5625 	if (pmon->hold_mon_dst_ring) {
5626 		spin_unlock_bh(&pmon->mon_lock);
5627 		goto reap_status_ring;
5628 	}
5629 
5630 	mon_dst_srng = &ar->ab->hal.srng_list[dp->rxdma_mon_dst_ring.ring_id];
5631 	spin_lock_bh(&mon_dst_srng->lock);
5632 
5633 	ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5634 	while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5635 		head_msdu = NULL;
5636 		tail_msdu = NULL;
5637 
5638 		mpdu_rx_bufs_used = ath11k_dp_rx_full_mon_mpdu_pop(ar, ring_entry,
5639 								   &head_msdu,
5640 								   &tail_msdu,
5641 								   sw_mon_entries);
5642 		rx_bufs_used += mpdu_rx_bufs_used;
5643 
5644 		if (!sw_mon_entries->end_of_ppdu) {
5645 			if (head_msdu) {
5646 				ret = ath11k_dp_rx_full_mon_prepare_mpdu(&ab->dp,
5647 									 pmon->mon_mpdu,
5648 									 head_msdu,
5649 									 tail_msdu);
5650 				if (ret)
5651 					break_dst_ring = true;
5652 			}
5653 
5654 			goto next_entry;
5655 		} else {
5656 			if (!sw_mon_entries->ppdu_id &&
5657 			    !sw_mon_entries->mon_status_paddr) {
5658 				break_dst_ring = true;
5659 				goto next_entry;
5660 			}
5661 		}
5662 
5663 		rx_mon_stats->dest_ppdu_done++;
5664 		pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5665 		pmon->buf_state = DP_MON_STATUS_LAG;
5666 		pmon->mon_status_paddr = sw_mon_entries->mon_status_paddr;
5667 		pmon->hold_mon_dst_ring = true;
5668 next_entry:
5669 		ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5670 								mon_dst_srng);
5671 		if (break_dst_ring)
5672 			break;
5673 	}
5674 
5675 	ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5676 	spin_unlock_bh(&mon_dst_srng->lock);
5677 	spin_unlock_bh(&pmon->mon_lock);
5678 
5679 	if (rx_bufs_used) {
5680 		ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5681 					   &dp->rxdma_mon_buf_ring,
5682 					   rx_bufs_used,
5683 					   HAL_RX_BUF_RBM_SW3_BM);
5684 	}
5685 
5686 reap_status_ring:
5687 	quota = ath11k_dp_rx_process_full_mon_status_ring(ab, mac_id,
5688 							  napi, budget);
5689 
5690 	return quota;
5691 }
5692 
ath11k_dp_rx_process_mon_rings(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5693 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
5694 				   struct napi_struct *napi, int budget)
5695 {
5696 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5697 	int ret = 0;
5698 
5699 	if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5700 	    ab->hw_params.full_monitor_mode)
5701 		ret = ath11k_dp_full_mon_process_rx(ab, mac_id, napi, budget);
5702 	else
5703 		ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
5704 
5705 	return ret;
5706 }
5707 
ath11k_dp_rx_pdev_mon_status_attach(struct ath11k * ar)5708 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
5709 {
5710 	struct ath11k_pdev_dp *dp = &ar->dp;
5711 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5712 
5713 	pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5714 
5715 	memset(&pmon->rx_mon_stats, 0,
5716 	       sizeof(pmon->rx_mon_stats));
5717 	return 0;
5718 }
5719 
ath11k_dp_rx_pdev_mon_attach(struct ath11k * ar)5720 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
5721 {
5722 	struct ath11k_pdev_dp *dp = &ar->dp;
5723 	struct ath11k_mon_data *pmon = &dp->mon_data;
5724 	struct hal_srng *mon_desc_srng = NULL;
5725 	struct dp_srng *dp_srng;
5726 	int ret = 0;
5727 	u32 n_link_desc = 0;
5728 
5729 	ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
5730 	if (ret) {
5731 		ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
5732 		return ret;
5733 	}
5734 
5735 	/* if rxdma1_enable is false, no need to setup
5736 	 * rxdma_mon_desc_ring.
5737 	 */
5738 	if (!ar->ab->hw_params.rxdma1_enable)
5739 		return 0;
5740 
5741 	dp_srng = &dp->rxdma_mon_desc_ring;
5742 	n_link_desc = dp_srng->size /
5743 		ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
5744 	mon_desc_srng =
5745 		&ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
5746 
5747 	ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
5748 					HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
5749 					n_link_desc);
5750 	if (ret) {
5751 		ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
5752 		return ret;
5753 	}
5754 	pmon->mon_last_linkdesc_paddr = 0;
5755 	pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
5756 	spin_lock_init(&pmon->mon_lock);
5757 
5758 	return 0;
5759 }
5760 
ath11k_dp_mon_link_free(struct ath11k * ar)5761 static int ath11k_dp_mon_link_free(struct ath11k *ar)
5762 {
5763 	struct ath11k_pdev_dp *dp = &ar->dp;
5764 	struct ath11k_mon_data *pmon = &dp->mon_data;
5765 
5766 	ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
5767 				    HAL_RXDMA_MONITOR_DESC,
5768 				    &dp->rxdma_mon_desc_ring);
5769 	return 0;
5770 }
5771 
ath11k_dp_rx_pdev_mon_detach(struct ath11k * ar)5772 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
5773 {
5774 	ath11k_dp_mon_link_free(ar);
5775 	return 0;
5776 }
5777 
ath11k_dp_rx_pktlog_start(struct ath11k_base * ab)5778 int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab)
5779 {
5780 	/* start reap timer */
5781 	mod_timer(&ab->mon_reap_timer,
5782 		  jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
5783 
5784 	return 0;
5785 }
5786 
ath11k_dp_rx_pktlog_stop(struct ath11k_base * ab,bool stop_timer)5787 int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer)
5788 {
5789 	int ret;
5790 
5791 	if (stop_timer)
5792 		timer_delete_sync(&ab->mon_reap_timer);
5793 
5794 	/* reap all the monitor related rings */
5795 	ret = ath11k_dp_purge_mon_ring(ab);
5796 	if (ret) {
5797 		ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret);
5798 		return ret;
5799 	}
5800 
5801 	return 0;
5802 }
5803