1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Cirrus Logic CS48L32 audio DSP. 4 * 5 * Copyright (C) 2016-2018, 2020, 2022, 2025 Cirrus Logic, Inc. and 6 * Cirrus Logic International Semiconductor Ltd. 7 */ 8 #ifndef SND_SOC_CS48L32_H 9 #define SND_SOC_CS48L32_H 10 11 #include <linux/bits.h> 12 #include <sound/soc.h> 13 #include "wm_adsp.h" 14 15 #define CS48L32_SILICON_ID 0x48a32 16 17 #define CS48L32_32K_MCLK1 0 18 19 #define CS48L32_SFT_RESET_MAGIC 0x5a000000 20 #define CS48L32_SOFT_RESET_US 2000 21 #define CS48L32_HARD_RESET_MIN_US 1000 22 23 #define CS48L32_SEEN_BOOT_DONE BIT(0) 24 #define CS48L32_BOOT_TIMEOUT_US 25000 25 26 #define CS48L32_ASP_ENABLES1 0x00 27 #define CS48L32_ASP_CONTROL1 0x04 28 #define CS48L32_ASP_CONTROL2 0x08 29 #define CS48L32_ASP_CONTROL3 0x0c 30 #define CS48L32_ASP_FRAME_CONTROL1 0x10 31 #define CS48L32_ASP_FRAME_CONTROL2 0x14 32 #define CS48L32_ASP_FRAME_CONTROL5 0x20 33 #define CS48L32_ASP_FRAME_CONTROL6 0x24 34 #define CS48L32_ASP_DATA_CONTROL1 0x30 35 #define CS48L32_ASP_DATA_CONTROL5 0x40 36 #define CS48L32_SYSCLK_RATE_6MHZ 0 37 #define CS48L32_SYSCLK_RATE_12MHZ 1 38 #define CS48L32_SYSCLK_RATE_24MHZ 2 39 #define CS48L32_SYSCLK_RATE_49MHZ 3 40 #define CS48L32_SYSCLK_RATE_98MHZ 4 41 #define CS48L32_FLLHJ_INT_MAX_N 1023 42 #define CS48L32_FLLHJ_INT_MIN_N 1 43 #define CS48L32_FLLHJ_FRAC_MAX_N 255 44 #define CS48L32_FLLHJ_FRAC_MIN_N 2 45 #define CS48L32_FLLHJ_LP_INT_MODE_THRESH 100000 46 #define CS48L32_FLLHJ_LOW_THRESH 192000 47 #define CS48L32_FLLHJ_MID_THRESH 1152000 48 #define CS48L32_FLLHJ_MAX_THRESH 13000000 49 #define CS48L32_FLLHJ_LOW_GAINS 0x23f0 50 #define CS48L32_FLLHJ_MID_GAINS 0x22f2 51 #define CS48L32_FLLHJ_HIGH_GAINS 0x21f0 52 #define CS48L32_FLL_MAX_FOUT 50000000 53 #define CS48L32_FLL_MAX_REFDIV 8 54 #define CS48L32_FLL_CONTROL1_OFFS 0x00 55 #define CS48L32_FLL_CONTROL2_OFFS 0x04 56 #define CS48L32_FLL_CONTROL3_OFFS 0x08 57 #define CS48L32_FLL_CONTROL4_OFFS 0x0c 58 #define CS48L32_FLL_CONTROL5_OFFS 0x10 59 #define CS48L32_FLL_CONTROL6_OFFS 0x14 60 #define CS48L32_FLL_DIGITAL_TEST2_OFFS 0x34 61 #define CS48L32_FLL_GPIO_CLOCK_OFFS 0xa0 62 #define CS48L32_DSP_CLOCK_FREQ_OFFS 0x00000 63 #define CS48L32_ASP_FMT_DSP_MODE_A 0 64 #define CS48L32_ASP_FMT_DSP_MODE_B 1 65 #define CS48L32_ASP_FMT_I2S_MODE 2 66 #define CS48L32_ASP_FMT_LEFT_JUSTIFIED_MODE 3 67 #define CS48L32_HALO_SAMPLE_RATE_RX1 0x00080 68 #define CS48L32_HALO_SAMPLE_RATE_TX1 0x00280 69 #define CS48L32_HALO_DSP_RATE_MASK 0x1f 70 71 #define CS48L32_PDMCLK_SRC_IN1_PDMCLK 0x0 72 #define CS48L32_PDMCLK_SRC_IN2_PDMCLK 0x1 73 #define CS48L32_PDMCLK_SRC_IN3_PDMCLK 0x2 74 #define CS48L32_PDMCLK_SRC_IN4_PDMCLK 0x3 75 #define CS48L32_PDMCLK_SRC_AUXPDM1_CLK 0x8 76 #define CS48L32_PDMCLK_SRC_AUXPDM2_CLK 0x9 77 78 #define CS48L32_MAX_DAI 6 79 #define CS48L32_MAX_INPUT 4 80 #define CS48L32_MAX_ANALOG_INPUT 2 81 #define CS48L32_MAX_IN_MUX_WAYS 2 82 #define CS48L32_MAX_ASP 2 83 84 #define CS48L32_EQ_BLOCK_SZ 60 85 #define CS48L32_N_EQ_BLOCKS 4 86 87 #define CS48L32_DSP_N_RX_CHANNELS 8 88 #define CS48L32_DSP_N_TX_CHANNELS 8 89 90 #define CS48L32_LHPF_MAX_COEFF 4095 91 #define CS48L32_EQ_MAX_COEFF 4095 92 93 #define CS48L32_MIXER_CONTROLS(name, base) \ 94 SOC_SINGLE_RANGE_TLV(name " Input 1 Volume", base, \ 95 CS48L32_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ 96 cs48l32_mixer_tlv), \ 97 SOC_SINGLE_RANGE_TLV(name " Input 2 Volume", base + 4, \ 98 CS48L32_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ 99 cs48l32_mixer_tlv), \ 100 SOC_SINGLE_RANGE_TLV(name " Input 3 Volume", base + 8, \ 101 CS48L32_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ 102 cs48l32_mixer_tlv), \ 103 SOC_SINGLE_RANGE_TLV(name " Input 4 Volume", base + 12, \ 104 CS48L32_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ 105 cs48l32_mixer_tlv) 106 107 #define CS48L32_MUX_ENUM_DECL(name, reg) \ 108 SOC_VALUE_ENUM_SINGLE_DECL( \ 109 name, reg, 0, CS48L32_MIXER_SRC_MASK, \ 110 cs48l32_mixer_texts, cs48l32_mixer_values) 111 112 #define CS48L32_MUX_CTL_DECL(name) \ 113 const struct snd_kcontrol_new name##_mux = SOC_DAPM_ENUM("Route", name##_enum) 114 115 #define CS48L32_MUX_ENUMS(name, base_reg) \ 116 static CS48L32_MUX_ENUM_DECL(name##_enum, base_reg); \ 117 static CS48L32_MUX_CTL_DECL(name) 118 119 #define CS48L32_MIXER_ENUMS(name, base_reg) \ 120 CS48L32_MUX_ENUMS(name##_in1, base_reg); \ 121 CS48L32_MUX_ENUMS(name##_in2, base_reg + 4); \ 122 CS48L32_MUX_ENUMS(name##_in3, base_reg + 8); \ 123 CS48L32_MUX_ENUMS(name##_in4, base_reg + 12) 124 125 #define CS48L32_MUX(name, ctrl) SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl) 126 127 #define CS48L32_MUX_WIDGETS(name, name_str) CS48L32_MUX(name_str " Input 1", &name##_mux) 128 129 #define CS48L32_MIXER_WIDGETS(name, name_str) \ 130 CS48L32_MUX(name_str " Input 1", &name##_in1_mux), \ 131 CS48L32_MUX(name_str " Input 2", &name##_in2_mux), \ 132 CS48L32_MUX(name_str " Input 3", &name##_in3_mux), \ 133 CS48L32_MUX(name_str " Input 4", &name##_in4_mux), \ 134 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0) 135 136 #define CS48L32_MUX_ROUTES(widget, name) \ 137 { widget, NULL, name " Input 1" }, \ 138 CS48L32_MIXER_INPUT_ROUTES(name " Input 1") 139 140 #define CS48L32_MIXER_ROUTES(widget, name) \ 141 { widget, NULL, name " Mixer" }, \ 142 { name " Mixer", NULL, name " Input 1" }, \ 143 { name " Mixer", NULL, name " Input 2" }, \ 144 { name " Mixer", NULL, name " Input 3" }, \ 145 { name " Mixer", NULL, name " Input 4" }, \ 146 CS48L32_MIXER_INPUT_ROUTES(name " Input 1"), \ 147 CS48L32_MIXER_INPUT_ROUTES(name " Input 2"), \ 148 CS48L32_MIXER_INPUT_ROUTES(name " Input 3"), \ 149 CS48L32_MIXER_INPUT_ROUTES(name " Input 4") 150 151 #define CS48L32_DSP_ROUTES_1_8_SYSCLK(name) \ 152 { name, NULL, name " Preloader" }, \ 153 { name, NULL, "SYSCLK" }, \ 154 { name " Preload", NULL, name " Preloader" }, \ 155 CS48L32_MIXER_ROUTES(name, name "RX1"), \ 156 CS48L32_MIXER_ROUTES(name, name "RX2"), \ 157 CS48L32_MIXER_ROUTES(name, name "RX3"), \ 158 CS48L32_MIXER_ROUTES(name, name "RX4"), \ 159 CS48L32_MIXER_ROUTES(name, name "RX5"), \ 160 CS48L32_MIXER_ROUTES(name, name "RX6"), \ 161 CS48L32_MIXER_ROUTES(name, name "RX7"), \ 162 CS48L32_MIXER_ROUTES(name, name "RX8") \ 163 164 #define CS48L32_DSP_ROUTES_1_8(name) \ 165 { name, NULL, "DSPCLK" }, \ 166 CS48L32_DSP_ROUTES_1_8_SYSCLK(name) \ 167 168 #define CS48L32_RATE_CONTROL(name, domain) SOC_ENUM(name, cs48l32_sample_rate[(domain) - 1]) 169 170 #define CS48L32_RATE_ENUM(name, enum) \ 171 SOC_ENUM_EXT(name, enum, snd_soc_get_enum_double, cs48l32_rate_put) 172 173 #define CS48L32_DSP_RATE_CONTROL(name, num) \ 174 SOC_ENUM_EXT(name " Rate", cs48l32_dsp_rate_enum[num], \ 175 cs48l32_dsp_rate_get, cs48l32_dsp_rate_put) 176 177 #define CS48L32_EQ_COEFF_CONTROL(xname, xreg, xbase, xshift) \ 178 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 179 .info = cs48l32_eq_coeff_info, .get = cs48l32_eq_coeff_get, \ 180 .put = cs48l32_eq_coeff_put, .private_value = \ 181 (unsigned long)&(struct cs48l32_eq_control) { .reg = xreg,\ 182 .shift = xshift, .block_base = xbase, .max = 65535 } } 183 184 #define CS48L32_EQ_REG_NAME_PASTER(eq, band, type) \ 185 CS48L32_ ## eq ## _ ## band ## _ ## type 186 187 #define CS48L32_EQ_BAND_COEFF_CONTROLS(name, band) \ 188 CS48L32_EQ_COEFF_CONTROL(#name " " #band " A", \ 189 CS48L32_EQ_REG_NAME_PASTER(name, band, COEFF1), \ 190 CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ 191 0), \ 192 CS48L32_EQ_COEFF_CONTROL(#name " " #band " B", \ 193 CS48L32_EQ_REG_NAME_PASTER(name, band, COEFF1), \ 194 CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ 195 16), \ 196 CS48L32_EQ_COEFF_CONTROL(#name " " #band " C", \ 197 CS48L32_EQ_REG_NAME_PASTER(name, band, COEFF2), \ 198 CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ 199 0), \ 200 CS48L32_EQ_COEFF_CONTROL(#name " " #band " PG", \ 201 CS48L32_EQ_REG_NAME_PASTER(name, band, PG), \ 202 CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ 203 0) 204 205 #define CS48L32_EQ_COEFF_CONTROLS(name) \ 206 CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND1), \ 207 CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND2), \ 208 CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND3), \ 209 CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND4), \ 210 CS48L32_EQ_COEFF_CONTROL(#name " BAND5 A", \ 211 CS48L32_EQ_REG_NAME_PASTER(name, BAND5, COEFF1), \ 212 CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ 213 0), \ 214 CS48L32_EQ_COEFF_CONTROL(#name " BAND5 B", \ 215 CS48L32_EQ_REG_NAME_PASTER(name, BAND5, COEFF1), \ 216 CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ 217 16), \ 218 CS48L32_EQ_COEFF_CONTROL(#name " BAND5 PG", \ 219 CS48L32_EQ_REG_NAME_PASTER(name, BAND5, PG), \ 220 CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ 221 0) 222 223 #define CS48L32_LHPF_CONTROL(xname, xbase) \ 224 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 225 .info = snd_soc_bytes_info, .get = snd_soc_bytes_get, \ 226 .put = cs48l32_lhpf_coeff_put, .private_value = \ 227 ((unsigned long)&(struct soc_bytes) { .base = xbase, \ 228 .num_regs = 1 }) } 229 230 /* these have a subseq number so they run after SYSCLK and DSPCLK widgets */ 231 #define CS48L32_DSP_FREQ_WIDGET_EV(name, num, event) \ 232 SND_SOC_DAPM_SUPPLY_S(name "FREQ", 100, SND_SOC_NOPM, num, 0, \ 233 event, SND_SOC_DAPM_POST_PMU) 234 235 #define CS48L32_RATES SNDRV_PCM_RATE_KNOT 236 237 #define CS48L32_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 238 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 239 240 #define CS48L32_MIXER_INPUT_ROUTES(name) \ 241 { name, "Tone Generator 1", "Tone Generator 1" }, \ 242 { name, "Tone Generator 2", "Tone Generator 2" }, \ 243 { name, "Noise Generator", "Noise Generator" }, \ 244 { name, "IN1L", "IN1L PGA" }, \ 245 { name, "IN1R", "IN1R PGA" }, \ 246 { name, "IN2L", "IN2L PGA" }, \ 247 { name, "IN2R", "IN2R PGA" }, \ 248 { name, "ASP1RX1", "ASP1RX1" }, \ 249 { name, "ASP1RX2", "ASP1RX2" }, \ 250 { name, "ASP1RX3", "ASP1RX3" }, \ 251 { name, "ASP1RX4", "ASP1RX4" }, \ 252 { name, "ASP1RX5", "ASP1RX5" }, \ 253 { name, "ASP1RX6", "ASP1RX6" }, \ 254 { name, "ASP1RX7", "ASP1RX7" }, \ 255 { name, "ASP1RX8", "ASP1RX8" }, \ 256 { name, "ASP2RX1", "ASP2RX1" }, \ 257 { name, "ASP2RX2", "ASP2RX2" }, \ 258 { name, "ASP2RX3", "ASP2RX3" }, \ 259 { name, "ASP2RX4", "ASP2RX4" }, \ 260 { name, "ISRC1DEC1", "ISRC1DEC1" }, \ 261 { name, "ISRC1DEC2", "ISRC1DEC2" }, \ 262 { name, "ISRC1DEC3", "ISRC1DEC3" }, \ 263 { name, "ISRC1DEC4", "ISRC1DEC4" }, \ 264 { name, "ISRC1INT1", "ISRC1INT1" }, \ 265 { name, "ISRC1INT2", "ISRC1INT2" }, \ 266 { name, "ISRC1INT3", "ISRC1INT3" }, \ 267 { name, "ISRC1INT4", "ISRC1INT4" }, \ 268 { name, "ISRC2DEC1", "ISRC2DEC1" }, \ 269 { name, "ISRC2DEC2", "ISRC2DEC2" }, \ 270 { name, "ISRC2INT1", "ISRC2INT1" }, \ 271 { name, "ISRC2INT2", "ISRC2INT2" }, \ 272 { name, "ISRC3DEC1", "ISRC3DEC1" }, \ 273 { name, "ISRC3DEC2", "ISRC3DEC2" }, \ 274 { name, "ISRC3INT1", "ISRC3INT1" }, \ 275 { name, "ISRC3INT2", "ISRC3INT2" }, \ 276 { name, "EQ1", "EQ1" }, \ 277 { name, "EQ2", "EQ2" }, \ 278 { name, "EQ3", "EQ3" }, \ 279 { name, "EQ4", "EQ4" }, \ 280 { name, "DRC1L", "DRC1L" }, \ 281 { name, "DRC1R", "DRC1R" }, \ 282 { name, "DRC2L", "DRC2L" }, \ 283 { name, "DRC2R", "DRC2R" }, \ 284 { name, "LHPF1", "LHPF1" }, \ 285 { name, "LHPF2", "LHPF2" }, \ 286 { name, "LHPF3", "LHPF3" }, \ 287 { name, "LHPF4", "LHPF4" }, \ 288 { name, "Ultrasonic 1", "Ultrasonic 1" }, \ 289 { name, "Ultrasonic 2", "Ultrasonic 2" }, \ 290 { name, "DSP1.1", "DSP1" }, \ 291 { name, "DSP1.2", "DSP1" }, \ 292 { name, "DSP1.3", "DSP1" }, \ 293 { name, "DSP1.4", "DSP1" }, \ 294 { name, "DSP1.5", "DSP1" }, \ 295 { name, "DSP1.6", "DSP1" }, \ 296 { name, "DSP1.7", "DSP1" }, \ 297 { name, "DSP1.8", "DSP1" } 298 299 struct cs48l32_enum { 300 struct soc_enum mixer_enum; 301 int val; 302 }; 303 304 struct cs48l32_eq_control { 305 unsigned int reg; 306 unsigned int shift; 307 unsigned int block_base; 308 unsigned int max; 309 }; 310 311 struct cs48l32_dai_priv { 312 int clk; 313 struct snd_pcm_hw_constraint_list constraint; 314 }; 315 316 struct cs48l32_dsp_power_reg_block { 317 unsigned int start; 318 unsigned int end; 319 }; 320 321 struct cs48l32_dsp_power_regs { 322 const unsigned int *pwd; 323 unsigned int n_pwd; 324 const struct cs48l32_dsp_power_reg_block *ext; 325 unsigned int n_ext; 326 }; 327 328 struct cs48l32; 329 struct cs48l32_codec; 330 struct spi_device; 331 332 struct cs48l32_fll_cfg { 333 int n; 334 unsigned int theta; 335 unsigned int lambda; 336 int refdiv; 337 int fratio; 338 int gain; 339 int alt_gain; 340 }; 341 342 struct cs48l32_fll { 343 struct cs48l32_codec *codec; 344 int id; 345 unsigned int base; 346 347 unsigned int sts_addr; 348 unsigned int sts_mask; 349 unsigned int fout; 350 int ref_src; 351 unsigned int ref_freq; 352 353 struct cs48l32_fll_cfg ref_cfg; 354 }; 355 356 struct cs48l32_codec { 357 struct wm_adsp dsp; /* must be first */ 358 struct cs48l32 core; 359 int sysclk; 360 int dspclk; 361 struct cs48l32_dai_priv dai[CS48L32_MAX_DAI]; 362 struct cs48l32_fll fll; 363 364 unsigned int in_up_pending; 365 unsigned int in_vu_reg; 366 367 struct mutex rate_lock; 368 369 u8 dsp_dma_rates[CS48L32_DSP_N_RX_CHANNELS + CS48L32_DSP_N_TX_CHANNELS]; 370 371 u8 in_type[CS48L32_MAX_ANALOG_INPUT][CS48L32_MAX_IN_MUX_WAYS]; 372 u8 pdm_sup[CS48L32_MAX_ANALOG_INPUT]; 373 u8 tdm_width[CS48L32_MAX_ASP]; 374 u8 tdm_slots[CS48L32_MAX_ASP]; 375 376 unsigned int eq_mode[CS48L32_N_EQ_BLOCKS]; 377 __be16 eq_coefficients[CS48L32_N_EQ_BLOCKS][CS48L32_EQ_BLOCK_SZ / 2]; 378 379 const struct cs48l32_dsp_power_regs *dsp_power_regs; 380 }; 381 382 #define cs48l32_fll_err(_fll, fmt, ...) \ 383 dev_err(_fll->codec->core.dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) 384 #define cs48l32_fll_warn(_fll, fmt, ...) \ 385 dev_warn(_fll->codec->core.dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) 386 #define cs48l32_fll_dbg(_fll, fmt, ...) \ 387 dev_dbg(_fll->codec->core.dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) 388 389 #define cs48l32_asp_err(_dai, fmt, ...) \ 390 dev_err(_dai->component->dev, "ASP%d: " fmt, _dai->id, ##__VA_ARGS__) 391 #define cs48l32_asp_warn(_dai, fmt, ...) \ 392 dev_warn(_dai->component->dev, "ASP%d: " fmt, _dai->id, ##__VA_ARGS__) 393 #define cs48l32_asp_dbg(_dai, fmt, ...) \ 394 dev_dbg(_dai->component->dev, "ASP%d: " fmt, _dai->id, ##__VA_ARGS__) 395 396 int cs48l32_apply_patch(struct cs48l32 *cs48l32); 397 int cs48l32_create_regmap(struct spi_device *spi, struct cs48l32 *cs48l32); 398 int cs48l32_enable_asp1_pins(struct cs48l32_codec *cs48l32_codec); 399 int cs48l32_enable_asp2_pins(struct cs48l32_codec *cs48l32_codec); 400 int cs48l32_micvdd_voltage_index(u32 voltage); 401 int cs48l32_micbias1_voltage_index(u32 voltage); 402 403 #endif 404