1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) ST-Ericsson SA 2012 4 * 5 * Author: Ola Lilja <ola.o.lilja@stericsson.com>, 6 * Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>, 7 * Roger Nilsson <roger.xr.nilsson@stericsson.com>, 8 * for ST-Ericsson. 9 * 10 * Based on the early work done by: 11 * Mikko J. Lehto <mikko.lehto@symbio.com>, 12 * Mikko Sarmanne <mikko.sarmanne@symbio.com>, 13 * Jarmo K. Kuronen <jarmo.kuronen@symbio.com>, 14 * for ST-Ericsson. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/slab.h> 21 #include <linux/moduleparam.h> 22 #include <linux/init.h> 23 #include <linux/delay.h> 24 #include <linux/pm.h> 25 #include <linux/platform_device.h> 26 #include <linux/mutex.h> 27 #include <linux/mfd/abx500/ab8500.h> 28 #include <linux/mfd/abx500.h> 29 #include <linux/mfd/abx500/ab8500-sysctrl.h> 30 #include <linux/mfd/abx500/ab8500-codec.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/of.h> 33 34 #include <sound/core.h> 35 #include <sound/pcm.h> 36 #include <sound/pcm_params.h> 37 #include <sound/initval.h> 38 #include <sound/soc.h> 39 #include <sound/soc-dapm.h> 40 #include <sound/tlv.h> 41 42 #include "ab8500-codec.h" 43 44 /* Macrocell value definitions */ 45 #define CLK_32K_OUT2_DISABLE 0x01 46 #define INACTIVE_RESET_AUDIO 0x02 47 #define ENABLE_AUDIO_CLK_TO_AUDIO_BLK 0x10 48 #define ENABLE_VINTCORE12_SUPPLY 0x04 49 #define GPIO27_DIR_OUTPUT 0x04 50 #define GPIO29_DIR_OUTPUT 0x10 51 #define GPIO31_DIR_OUTPUT 0x40 52 53 /* Macrocell register definitions */ 54 #define AB8500_GPIO_DIR4_REG 0x13 /* Bank AB8500_MISC */ 55 56 /* Nr of FIR/IIR-coeff banks in ANC-block */ 57 #define AB8500_NR_OF_ANC_COEFF_BANKS 2 58 59 /* Minimum duration to keep ANC IIR Init bit high or 60 low before proceeding with the configuration sequence */ 61 #define AB8500_ANC_SM_DELAY 2000 62 63 /* Sidetone states */ 64 static const char * const enum_sid_state[] = { 65 "Unconfigured", 66 "Apply FIR", 67 "FIR is configured", 68 }; 69 enum sid_state { 70 SID_UNCONFIGURED = 0, 71 SID_APPLY_FIR = 1, 72 SID_FIR_CONFIGURED = 2, 73 }; 74 75 /* Private data for AB8500 device-driver */ 76 struct ab8500_codec_drvdata { 77 struct regmap *regmap; 78 struct mutex ctrl_lock; 79 80 /* Sidetone */ 81 enum sid_state sid_status; 82 }; 83 84 static inline const char *amic_micbias_str(enum amic_micbias micbias) 85 { 86 switch (micbias) { 87 case AMIC_MICBIAS_VAMIC1: 88 return "VAMIC1"; 89 case AMIC_MICBIAS_VAMIC2: 90 return "VAMIC2"; 91 default: 92 return "Unknown"; 93 } 94 } 95 96 static inline const char *amic_type_str(enum amic_type type) 97 { 98 switch (type) { 99 case AMIC_TYPE_DIFFERENTIAL: 100 return "DIFFERENTIAL"; 101 case AMIC_TYPE_SINGLE_ENDED: 102 return "SINGLE ENDED"; 103 default: 104 return "Unknown"; 105 } 106 } 107 108 /* 109 * Read'n'write functions 110 */ 111 112 /* Read a register from the audio-bank of AB8500 */ 113 static int ab8500_codec_read_reg(void *context, unsigned int reg, 114 unsigned int *value) 115 { 116 struct device *dev = context; 117 int status; 118 119 u8 value8; 120 status = abx500_get_register_interruptible(dev, AB8500_AUDIO, 121 reg, &value8); 122 *value = (unsigned int)value8; 123 124 return status; 125 } 126 127 /* Write to a register in the audio-bank of AB8500 */ 128 static int ab8500_codec_write_reg(void *context, unsigned int reg, 129 unsigned int value) 130 { 131 struct device *dev = context; 132 133 return abx500_set_register_interruptible(dev, AB8500_AUDIO, 134 reg, value); 135 } 136 137 static const struct regmap_config ab8500_codec_regmap = { 138 .reg_read = ab8500_codec_read_reg, 139 .reg_write = ab8500_codec_write_reg, 140 }; 141 142 /* 143 * Controls - DAPM 144 */ 145 146 /* Earpiece */ 147 148 /* Earpiece source selector */ 149 static const char * const enum_ear_lineout_source[] = {"Headset Left", 150 "Speaker Left"}; 151 static SOC_ENUM_SINGLE_DECL(dapm_enum_ear_lineout_source, AB8500_DMICFILTCONF, 152 AB8500_DMICFILTCONF_DA3TOEAR, enum_ear_lineout_source); 153 static const struct snd_kcontrol_new dapm_ear_lineout_source = 154 SOC_DAPM_ENUM("Earpiece or LineOut Mono Source", 155 dapm_enum_ear_lineout_source); 156 157 /* LineOut */ 158 159 /* LineOut source selector */ 160 static const char * const enum_lineout_source[] = {"Mono Path", "Stereo Path"}; 161 static SOC_ENUM_DOUBLE_DECL(dapm_enum_lineout_source, AB8500_ANACONF5, 162 AB8500_ANACONF5_HSLDACTOLOL, 163 AB8500_ANACONF5_HSRDACTOLOR, enum_lineout_source); 164 static const struct snd_kcontrol_new dapm_lineout_source[] = { 165 SOC_DAPM_ENUM("LineOut Source", dapm_enum_lineout_source), 166 }; 167 168 /* Handsfree */ 169 170 /* Speaker Left - ANC selector */ 171 static const char * const enum_HFx_sel[] = {"Audio Path", "ANC"}; 172 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFl_sel, AB8500_DIGMULTCONF2, 173 AB8500_DIGMULTCONF2_HFLSEL, enum_HFx_sel); 174 static const struct snd_kcontrol_new dapm_HFl_select[] = { 175 SOC_DAPM_ENUM("Speaker Left Source", dapm_enum_HFl_sel), 176 }; 177 178 /* Speaker Right - ANC selector */ 179 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFr_sel, AB8500_DIGMULTCONF2, 180 AB8500_DIGMULTCONF2_HFRSEL, enum_HFx_sel); 181 static const struct snd_kcontrol_new dapm_HFr_select[] = { 182 SOC_DAPM_ENUM("Speaker Right Source", dapm_enum_HFr_sel), 183 }; 184 185 /* Mic 1 */ 186 187 /* Mic 1 - Mic 1a or 1b selector */ 188 static const char * const enum_mic1ab_sel[] = {"Mic 1b", "Mic 1a"}; 189 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic1ab_sel, AB8500_ANACONF3, 190 AB8500_ANACONF3_MIC1SEL, enum_mic1ab_sel); 191 static const struct snd_kcontrol_new dapm_mic1ab_mux[] = { 192 SOC_DAPM_ENUM("Mic 1a or 1b Select", dapm_enum_mic1ab_sel), 193 }; 194 195 /* Mic 1 - AD3 - Mic 1 or DMic 3 selector */ 196 static const char * const enum_ad3_sel[] = {"Mic 1", "DMic 3"}; 197 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad3_sel, AB8500_DIGMULTCONF1, 198 AB8500_DIGMULTCONF1_AD3SEL, enum_ad3_sel); 199 static const struct snd_kcontrol_new dapm_ad3_select[] = { 200 SOC_DAPM_ENUM("AD3 Source Select", dapm_enum_ad3_sel), 201 }; 202 203 /* Mic 1 - AD6 - Mic 1 or DMic 6 selector */ 204 static const char * const enum_ad6_sel[] = {"Mic 1", "DMic 6"}; 205 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad6_sel, AB8500_DIGMULTCONF1, 206 AB8500_DIGMULTCONF1_AD6SEL, enum_ad6_sel); 207 static const struct snd_kcontrol_new dapm_ad6_select[] = { 208 SOC_DAPM_ENUM("AD6 Source Select", dapm_enum_ad6_sel), 209 }; 210 211 /* Mic 2 */ 212 213 /* Mic 2 - AD5 - Mic 2 or DMic 5 selector */ 214 static const char * const enum_ad5_sel[] = {"Mic 2", "DMic 5"}; 215 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad5_sel, AB8500_DIGMULTCONF1, 216 AB8500_DIGMULTCONF1_AD5SEL, enum_ad5_sel); 217 static const struct snd_kcontrol_new dapm_ad5_select[] = { 218 SOC_DAPM_ENUM("AD5 Source Select", dapm_enum_ad5_sel), 219 }; 220 221 /* LineIn */ 222 223 /* LineIn left - AD1 - LineIn Left or DMic 1 selector */ 224 static const char * const enum_ad1_sel[] = {"LineIn Left", "DMic 1"}; 225 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad1_sel, AB8500_DIGMULTCONF1, 226 AB8500_DIGMULTCONF1_AD1SEL, enum_ad1_sel); 227 static const struct snd_kcontrol_new dapm_ad1_select[] = { 228 SOC_DAPM_ENUM("AD1 Source Select", dapm_enum_ad1_sel), 229 }; 230 231 /* LineIn right - Mic 2 or LineIn Right selector */ 232 static const char * const enum_mic2lr_sel[] = {"Mic 2", "LineIn Right"}; 233 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic2lr_sel, AB8500_ANACONF3, 234 AB8500_ANACONF3_LINRSEL, enum_mic2lr_sel); 235 static const struct snd_kcontrol_new dapm_mic2lr_select[] = { 236 SOC_DAPM_ENUM("Mic 2 or LINR Select", dapm_enum_mic2lr_sel), 237 }; 238 239 /* LineIn right - AD2 - LineIn Right or DMic2 selector */ 240 static const char * const enum_ad2_sel[] = {"LineIn Right", "DMic 2"}; 241 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad2_sel, AB8500_DIGMULTCONF1, 242 AB8500_DIGMULTCONF1_AD2SEL, enum_ad2_sel); 243 static const struct snd_kcontrol_new dapm_ad2_select[] = { 244 SOC_DAPM_ENUM("AD2 Source Select", dapm_enum_ad2_sel), 245 }; 246 247 248 /* ANC */ 249 250 static const char * const enum_anc_in_sel[] = {"Mic 1 / DMic 6", 251 "Mic 2 / DMic 5"}; 252 static SOC_ENUM_SINGLE_DECL(dapm_enum_anc_in_sel, AB8500_DMICFILTCONF, 253 AB8500_DMICFILTCONF_ANCINSEL, enum_anc_in_sel); 254 static const struct snd_kcontrol_new dapm_anc_in_select[] = { 255 SOC_DAPM_ENUM("ANC Source", dapm_enum_anc_in_sel), 256 }; 257 258 /* ANC - Enable/Disable */ 259 static const struct snd_kcontrol_new dapm_anc_enable[] = { 260 SOC_DAPM_SINGLE("Switch", AB8500_ANCCONF1, 261 AB8500_ANCCONF1_ENANC, 0, 0), 262 }; 263 264 /* ANC to Earpiece - Mute */ 265 static const struct snd_kcontrol_new dapm_anc_ear_mute[] = { 266 SOC_DAPM_SINGLE("Switch", AB8500_DIGMULTCONF1, 267 AB8500_DIGMULTCONF1_ANCSEL, 1, 0), 268 }; 269 270 271 272 /* Sidetone left */ 273 274 /* Sidetone left - Input selector */ 275 static const char * const enum_stfir1_in_sel[] = { 276 "LineIn Left", "LineIn Right", "Mic 1", "Headset Left" 277 }; 278 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir1_in_sel, AB8500_DIGMULTCONF2, 279 AB8500_DIGMULTCONF2_FIRSID1SEL, enum_stfir1_in_sel); 280 static const struct snd_kcontrol_new dapm_stfir1_in_select[] = { 281 SOC_DAPM_ENUM("Sidetone Left Source", dapm_enum_stfir1_in_sel), 282 }; 283 284 /* Sidetone right path */ 285 286 /* Sidetone right - Input selector */ 287 static const char * const enum_stfir2_in_sel[] = { 288 "LineIn Right", "Mic 1", "DMic 4", "Headset Right" 289 }; 290 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir2_in_sel, AB8500_DIGMULTCONF2, 291 AB8500_DIGMULTCONF2_FIRSID2SEL, enum_stfir2_in_sel); 292 static const struct snd_kcontrol_new dapm_stfir2_in_select[] = { 293 SOC_DAPM_ENUM("Sidetone Right Source", dapm_enum_stfir2_in_sel), 294 }; 295 296 /* Vibra */ 297 298 static const char * const enum_pwm2vibx[] = {"Audio Path", "PWM Generator"}; 299 300 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib1, AB8500_PWMGENCONF1, 301 AB8500_PWMGENCONF1_PWMTOVIB1, enum_pwm2vibx); 302 303 static const struct snd_kcontrol_new dapm_pwm2vib1[] = { 304 SOC_DAPM_ENUM("Vibra 1 Controller", dapm_enum_pwm2vib1), 305 }; 306 307 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib2, AB8500_PWMGENCONF1, 308 AB8500_PWMGENCONF1_PWMTOVIB2, enum_pwm2vibx); 309 310 static const struct snd_kcontrol_new dapm_pwm2vib2[] = { 311 SOC_DAPM_ENUM("Vibra 2 Controller", dapm_enum_pwm2vib2), 312 }; 313 314 /* 315 * DAPM-widgets 316 */ 317 318 static const struct snd_soc_dapm_widget ab8500_dapm_widgets[] = { 319 320 /* Clocks */ 321 SND_SOC_DAPM_CLOCK_SUPPLY("audioclk"), 322 323 /* Regulators */ 324 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AUD", 0, 0), 325 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC1", 0, 0), 326 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC2", 0, 0), 327 SND_SOC_DAPM_REGULATOR_SUPPLY("V-DMIC", 0, 0), 328 329 /* Power */ 330 SND_SOC_DAPM_SUPPLY("Audio Power", 331 AB8500_POWERUP, AB8500_POWERUP_POWERUP, 0, 332 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 333 SND_SOC_DAPM_SUPPLY("Audio Analog Power", 334 AB8500_POWERUP, AB8500_POWERUP_ENANA, 0, 335 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 336 337 /* Main supply node */ 338 SND_SOC_DAPM_SUPPLY("Main Supply", SND_SOC_NOPM, 0, 0, 339 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 340 341 /* DA/AD */ 342 343 SND_SOC_DAPM_INPUT("ADC Input"), 344 SND_SOC_DAPM_ADC("ADC", "ab8500_0c", SND_SOC_NOPM, 0, 0), 345 346 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), 347 SND_SOC_DAPM_OUTPUT("DAC Output"), 348 349 SND_SOC_DAPM_AIF_IN("DA_IN1", NULL, 0, SND_SOC_NOPM, 0, 0), 350 SND_SOC_DAPM_AIF_IN("DA_IN2", NULL, 0, SND_SOC_NOPM, 0, 0), 351 SND_SOC_DAPM_AIF_IN("DA_IN3", NULL, 0, SND_SOC_NOPM, 0, 0), 352 SND_SOC_DAPM_AIF_IN("DA_IN4", NULL, 0, SND_SOC_NOPM, 0, 0), 353 SND_SOC_DAPM_AIF_IN("DA_IN5", NULL, 0, SND_SOC_NOPM, 0, 0), 354 SND_SOC_DAPM_AIF_IN("DA_IN6", NULL, 0, SND_SOC_NOPM, 0, 0), 355 SND_SOC_DAPM_AIF_OUT("AD_OUT1", NULL, 0, SND_SOC_NOPM, 0, 0), 356 SND_SOC_DAPM_AIF_OUT("AD_OUT2", NULL, 0, SND_SOC_NOPM, 0, 0), 357 SND_SOC_DAPM_AIF_OUT("AD_OUT3", NULL, 0, SND_SOC_NOPM, 0, 0), 358 SND_SOC_DAPM_AIF_OUT("AD_OUT4", NULL, 0, SND_SOC_NOPM, 0, 0), 359 SND_SOC_DAPM_AIF_OUT("AD_OUT57", NULL, 0, SND_SOC_NOPM, 0, 0), 360 SND_SOC_DAPM_AIF_OUT("AD_OUT68", NULL, 0, SND_SOC_NOPM, 0, 0), 361 362 /* Headset path */ 363 364 SND_SOC_DAPM_SUPPLY("Charge Pump", AB8500_ANACONF5, 365 AB8500_ANACONF5_ENCPHS, 0, NULL, 0), 366 367 SND_SOC_DAPM_DAC("DA1 Enable", "ab8500_0p", 368 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA1, 0), 369 SND_SOC_DAPM_DAC("DA2 Enable", "ab8500_0p", 370 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA2, 0), 371 372 SND_SOC_DAPM_PGA("HSL Digital Volume", SND_SOC_NOPM, 0, 0, 373 NULL, 0), 374 SND_SOC_DAPM_PGA("HSR Digital Volume", SND_SOC_NOPM, 0, 0, 375 NULL, 0), 376 377 SND_SOC_DAPM_DAC("HSL DAC", "ab8500_0p", 378 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSL, 0), 379 SND_SOC_DAPM_DAC("HSR DAC", "ab8500_0p", 380 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSR, 0), 381 SND_SOC_DAPM_MIXER("HSL DAC Mute", AB8500_MUTECONF, 382 AB8500_MUTECONF_MUTDACHSL, 1, 383 NULL, 0), 384 SND_SOC_DAPM_MIXER("HSR DAC Mute", AB8500_MUTECONF, 385 AB8500_MUTECONF_MUTDACHSR, 1, 386 NULL, 0), 387 SND_SOC_DAPM_DAC("HSL DAC Driver", "ab8500_0p", 388 AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSL, 0), 389 SND_SOC_DAPM_DAC("HSR DAC Driver", "ab8500_0p", 390 AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSR, 0), 391 392 SND_SOC_DAPM_MIXER("HSL Mute", 393 AB8500_MUTECONF, AB8500_MUTECONF_MUTHSL, 1, 394 NULL, 0), 395 SND_SOC_DAPM_MIXER("HSR Mute", 396 AB8500_MUTECONF, AB8500_MUTECONF_MUTHSR, 1, 397 NULL, 0), 398 SND_SOC_DAPM_MIXER("HSL Enable", 399 AB8500_ANACONF4, AB8500_ANACONF4_ENHSL, 0, 400 NULL, 0), 401 SND_SOC_DAPM_MIXER("HSR Enable", 402 AB8500_ANACONF4, AB8500_ANACONF4_ENHSR, 0, 403 NULL, 0), 404 SND_SOC_DAPM_PGA("HSL Volume", 405 SND_SOC_NOPM, 0, 0, 406 NULL, 0), 407 SND_SOC_DAPM_PGA("HSR Volume", 408 SND_SOC_NOPM, 0, 0, 409 NULL, 0), 410 411 SND_SOC_DAPM_OUTPUT("Headset Left"), 412 SND_SOC_DAPM_OUTPUT("Headset Right"), 413 414 /* LineOut path */ 415 416 SND_SOC_DAPM_MUX("LineOut Source", 417 SND_SOC_NOPM, 0, 0, dapm_lineout_source), 418 419 SND_SOC_DAPM_MIXER("LOL Disable HFL", 420 AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 1, 421 NULL, 0), 422 SND_SOC_DAPM_MIXER("LOR Disable HFR", 423 AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 1, 424 NULL, 0), 425 426 SND_SOC_DAPM_MIXER("LOL Enable", 427 AB8500_ANACONF5, AB8500_ANACONF5_ENLOL, 0, 428 NULL, 0), 429 SND_SOC_DAPM_MIXER("LOR Enable", 430 AB8500_ANACONF5, AB8500_ANACONF5_ENLOR, 0, 431 NULL, 0), 432 433 SND_SOC_DAPM_OUTPUT("LineOut Left"), 434 SND_SOC_DAPM_OUTPUT("LineOut Right"), 435 436 /* Earpiece path */ 437 438 SND_SOC_DAPM_MUX("Earpiece or LineOut Mono Source", 439 SND_SOC_NOPM, 0, 0, &dapm_ear_lineout_source), 440 SND_SOC_DAPM_MIXER("EAR DAC", 441 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACEAR, 0, 442 NULL, 0), 443 SND_SOC_DAPM_MIXER("EAR Mute", 444 AB8500_MUTECONF, AB8500_MUTECONF_MUTEAR, 1, 445 NULL, 0), 446 SND_SOC_DAPM_MIXER("EAR Enable", 447 AB8500_ANACONF4, AB8500_ANACONF4_ENEAR, 0, 448 NULL, 0), 449 450 SND_SOC_DAPM_OUTPUT("Earpiece"), 451 452 /* Handsfree path */ 453 454 SND_SOC_DAPM_MIXER("DA3 Channel Volume", 455 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA3, 0, 456 NULL, 0), 457 SND_SOC_DAPM_MIXER("DA4 Channel Volume", 458 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA4, 0, 459 NULL, 0), 460 SND_SOC_DAPM_MUX("Speaker Left Source", 461 SND_SOC_NOPM, 0, 0, dapm_HFl_select), 462 SND_SOC_DAPM_MUX("Speaker Right Source", 463 SND_SOC_NOPM, 0, 0, dapm_HFr_select), 464 SND_SOC_DAPM_MIXER("HFL DAC", AB8500_DAPATHCONF, 465 AB8500_DAPATHCONF_ENDACHFL, 0, 466 NULL, 0), 467 SND_SOC_DAPM_MIXER("HFR DAC", 468 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHFR, 0, 469 NULL, 0), 470 SND_SOC_DAPM_MIXER("DA4 or ANC path to HfR", 471 AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFREN, 0, 472 NULL, 0), 473 SND_SOC_DAPM_MIXER("DA3 or ANC path to HfL", 474 AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFLEN, 0, 475 NULL, 0), 476 SND_SOC_DAPM_MIXER("HFL Enable", 477 AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 0, 478 NULL, 0), 479 SND_SOC_DAPM_MIXER("HFR Enable", 480 AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 0, 481 NULL, 0), 482 483 SND_SOC_DAPM_OUTPUT("Speaker Left"), 484 SND_SOC_DAPM_OUTPUT("Speaker Right"), 485 486 /* Vibrator path */ 487 488 SND_SOC_DAPM_INPUT("PWMGEN1"), 489 SND_SOC_DAPM_INPUT("PWMGEN2"), 490 491 SND_SOC_DAPM_MIXER("DA5 Channel Volume", 492 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA5, 0, 493 NULL, 0), 494 SND_SOC_DAPM_MIXER("DA6 Channel Volume", 495 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA6, 0, 496 NULL, 0), 497 SND_SOC_DAPM_MIXER("VIB1 DAC", 498 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB1, 0, 499 NULL, 0), 500 SND_SOC_DAPM_MIXER("VIB2 DAC", 501 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB2, 0, 502 NULL, 0), 503 SND_SOC_DAPM_MUX("Vibra 1 Controller", 504 SND_SOC_NOPM, 0, 0, dapm_pwm2vib1), 505 SND_SOC_DAPM_MUX("Vibra 2 Controller", 506 SND_SOC_NOPM, 0, 0, dapm_pwm2vib2), 507 SND_SOC_DAPM_MIXER("VIB1 Enable", 508 AB8500_ANACONF4, AB8500_ANACONF4_ENVIB1, 0, 509 NULL, 0), 510 SND_SOC_DAPM_MIXER("VIB2 Enable", 511 AB8500_ANACONF4, AB8500_ANACONF4_ENVIB2, 0, 512 NULL, 0), 513 514 SND_SOC_DAPM_OUTPUT("Vibra 1"), 515 SND_SOC_DAPM_OUTPUT("Vibra 2"), 516 517 /* Mic 1 */ 518 519 SND_SOC_DAPM_INPUT("Mic 1"), 520 521 SND_SOC_DAPM_MUX("Mic 1a or 1b Select", 522 SND_SOC_NOPM, 0, 0, dapm_mic1ab_mux), 523 SND_SOC_DAPM_MIXER("MIC1 Mute", 524 AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC1, 1, 525 NULL, 0), 526 SND_SOC_DAPM_MIXER("MIC1A V-AMICx Enable", 527 AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0, 528 NULL, 0), 529 SND_SOC_DAPM_MIXER("MIC1B V-AMICx Enable", 530 AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0, 531 NULL, 0), 532 SND_SOC_DAPM_MIXER("MIC1 ADC", 533 AB8500_ANACONF3, AB8500_ANACONF3_ENADCMIC, 0, 534 NULL, 0), 535 SND_SOC_DAPM_MUX("AD3 Source Select", 536 SND_SOC_NOPM, 0, 0, dapm_ad3_select), 537 SND_SOC_DAPM_MIXER("AD3 Channel Volume", 538 SND_SOC_NOPM, 0, 0, 539 NULL, 0), 540 SND_SOC_DAPM_MIXER("AD3 Enable", 541 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34, 0, 542 NULL, 0), 543 544 /* Mic 2 */ 545 546 SND_SOC_DAPM_INPUT("Mic 2"), 547 548 SND_SOC_DAPM_MIXER("MIC2 Mute", 549 AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC2, 1, 550 NULL, 0), 551 SND_SOC_DAPM_MIXER("MIC2 V-AMICx Enable", AB8500_ANACONF2, 552 AB8500_ANACONF2_ENMIC2, 0, 553 NULL, 0), 554 555 /* LineIn */ 556 557 SND_SOC_DAPM_INPUT("LineIn Left"), 558 SND_SOC_DAPM_INPUT("LineIn Right"), 559 560 SND_SOC_DAPM_MIXER("LINL Mute", 561 AB8500_ANACONF2, AB8500_ANACONF2_MUTLINL, 1, 562 NULL, 0), 563 SND_SOC_DAPM_MIXER("LINR Mute", 564 AB8500_ANACONF2, AB8500_ANACONF2_MUTLINR, 1, 565 NULL, 0), 566 SND_SOC_DAPM_MIXER("LINL Enable", AB8500_ANACONF2, 567 AB8500_ANACONF2_ENLINL, 0, 568 NULL, 0), 569 SND_SOC_DAPM_MIXER("LINR Enable", AB8500_ANACONF2, 570 AB8500_ANACONF2_ENLINR, 0, 571 NULL, 0), 572 573 /* LineIn Bypass path */ 574 SND_SOC_DAPM_MIXER("LINL to HSL Volume", 575 SND_SOC_NOPM, 0, 0, 576 NULL, 0), 577 SND_SOC_DAPM_MIXER("LINR to HSR Volume", 578 SND_SOC_NOPM, 0, 0, 579 NULL, 0), 580 581 /* LineIn, Mic 2 */ 582 SND_SOC_DAPM_MUX("Mic 2 or LINR Select", 583 SND_SOC_NOPM, 0, 0, dapm_mic2lr_select), 584 SND_SOC_DAPM_MIXER("LINL ADC", AB8500_ANACONF3, 585 AB8500_ANACONF3_ENADCLINL, 0, 586 NULL, 0), 587 SND_SOC_DAPM_MIXER("LINR ADC", AB8500_ANACONF3, 588 AB8500_ANACONF3_ENADCLINR, 0, 589 NULL, 0), 590 SND_SOC_DAPM_MUX("AD1 Source Select", 591 SND_SOC_NOPM, 0, 0, dapm_ad1_select), 592 SND_SOC_DAPM_MUX("AD2 Source Select", 593 SND_SOC_NOPM, 0, 0, dapm_ad2_select), 594 SND_SOC_DAPM_MIXER("AD1 Channel Volume", 595 SND_SOC_NOPM, 0, 0, 596 NULL, 0), 597 SND_SOC_DAPM_MIXER("AD2 Channel Volume", 598 SND_SOC_NOPM, 0, 0, 599 NULL, 0), 600 601 SND_SOC_DAPM_MIXER("AD12 Enable", 602 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD12, 0, 603 NULL, 0), 604 605 /* HD Capture path */ 606 607 SND_SOC_DAPM_MUX("AD5 Source Select", 608 SND_SOC_NOPM, 0, 0, dapm_ad5_select), 609 SND_SOC_DAPM_MUX("AD6 Source Select", 610 SND_SOC_NOPM, 0, 0, dapm_ad6_select), 611 SND_SOC_DAPM_MIXER("AD5 Channel Volume", 612 SND_SOC_NOPM, 0, 0, 613 NULL, 0), 614 SND_SOC_DAPM_MIXER("AD6 Channel Volume", 615 SND_SOC_NOPM, 0, 0, 616 NULL, 0), 617 SND_SOC_DAPM_MIXER("AD57 Enable", 618 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0, 619 NULL, 0), 620 SND_SOC_DAPM_MIXER("AD68 Enable", 621 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0, 622 NULL, 0), 623 624 /* Digital Microphone path */ 625 626 SND_SOC_DAPM_INPUT("DMic 1"), 627 SND_SOC_DAPM_INPUT("DMic 2"), 628 SND_SOC_DAPM_INPUT("DMic 3"), 629 SND_SOC_DAPM_INPUT("DMic 4"), 630 SND_SOC_DAPM_INPUT("DMic 5"), 631 SND_SOC_DAPM_INPUT("DMic 6"), 632 633 SND_SOC_DAPM_MIXER("DMIC1", 634 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC1, 0, 635 NULL, 0), 636 SND_SOC_DAPM_MIXER("DMIC2", 637 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC2, 0, 638 NULL, 0), 639 SND_SOC_DAPM_MIXER("DMIC3", 640 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC3, 0, 641 NULL, 0), 642 SND_SOC_DAPM_MIXER("DMIC4", 643 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC4, 0, 644 NULL, 0), 645 SND_SOC_DAPM_MIXER("DMIC5", 646 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC5, 0, 647 NULL, 0), 648 SND_SOC_DAPM_MIXER("DMIC6", 649 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC6, 0, 650 NULL, 0), 651 SND_SOC_DAPM_MIXER("AD4 Channel Volume", 652 SND_SOC_NOPM, 0, 0, 653 NULL, 0), 654 SND_SOC_DAPM_MIXER("AD4 Enable", 655 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34, 656 0, NULL, 0), 657 658 /* Acoustical Noise Cancellation path */ 659 660 SND_SOC_DAPM_INPUT("ANC Configure Input"), 661 SND_SOC_DAPM_OUTPUT("ANC Configure Output"), 662 663 SND_SOC_DAPM_MUX("ANC Source", 664 SND_SOC_NOPM, 0, 0, 665 dapm_anc_in_select), 666 SND_SOC_DAPM_SWITCH("ANC", 667 SND_SOC_NOPM, 0, 0, 668 dapm_anc_enable), 669 SND_SOC_DAPM_SWITCH("ANC to Earpiece", 670 SND_SOC_NOPM, 0, 0, 671 dapm_anc_ear_mute), 672 673 /* Sidetone Filter path */ 674 675 SND_SOC_DAPM_MUX("Sidetone Left Source", 676 SND_SOC_NOPM, 0, 0, 677 dapm_stfir1_in_select), 678 SND_SOC_DAPM_MUX("Sidetone Right Source", 679 SND_SOC_NOPM, 0, 0, 680 dapm_stfir2_in_select), 681 SND_SOC_DAPM_MIXER("STFIR1 Control", 682 SND_SOC_NOPM, 0, 0, 683 NULL, 0), 684 SND_SOC_DAPM_MIXER("STFIR2 Control", 685 SND_SOC_NOPM, 0, 0, 686 NULL, 0), 687 SND_SOC_DAPM_MIXER("STFIR1 Volume", 688 SND_SOC_NOPM, 0, 0, 689 NULL, 0), 690 SND_SOC_DAPM_MIXER("STFIR2 Volume", 691 SND_SOC_NOPM, 0, 0, 692 NULL, 0), 693 }; 694 695 /* 696 * DAPM-routes 697 */ 698 static const struct snd_soc_dapm_route ab8500_dapm_routes[] = { 699 /* Power AB8500 audio-block when AD/DA is active */ 700 {"Main Supply", NULL, "V-AUD"}, 701 {"Main Supply", NULL, "audioclk"}, 702 {"Main Supply", NULL, "Audio Power"}, 703 {"Main Supply", NULL, "Audio Analog Power"}, 704 705 {"DAC", NULL, "ab8500_0p"}, 706 {"DAC", NULL, "Main Supply"}, 707 {"ADC", NULL, "ab8500_0c"}, 708 {"ADC", NULL, "Main Supply"}, 709 710 /* ANC Configure */ 711 {"ANC Configure Input", NULL, "Main Supply"}, 712 {"ANC Configure Output", NULL, "ANC Configure Input"}, 713 714 /* AD/DA */ 715 {"ADC", NULL, "ADC Input"}, 716 {"DAC Output", NULL, "DAC"}, 717 718 /* Powerup charge pump if DA1/2 is in use */ 719 720 {"DA_IN1", NULL, "ab8500_0p"}, 721 {"DA_IN1", NULL, "Charge Pump"}, 722 {"DA_IN2", NULL, "ab8500_0p"}, 723 {"DA_IN2", NULL, "Charge Pump"}, 724 725 /* Headset path */ 726 727 {"DA1 Enable", NULL, "DA_IN1"}, 728 {"DA2 Enable", NULL, "DA_IN2"}, 729 730 {"HSL Digital Volume", NULL, "DA1 Enable"}, 731 {"HSR Digital Volume", NULL, "DA2 Enable"}, 732 733 {"HSL DAC", NULL, "HSL Digital Volume"}, 734 {"HSR DAC", NULL, "HSR Digital Volume"}, 735 736 {"HSL DAC Mute", NULL, "HSL DAC"}, 737 {"HSR DAC Mute", NULL, "HSR DAC"}, 738 739 {"HSL DAC Driver", NULL, "HSL DAC Mute"}, 740 {"HSR DAC Driver", NULL, "HSR DAC Mute"}, 741 742 {"HSL Mute", NULL, "HSL DAC Driver"}, 743 {"HSR Mute", NULL, "HSR DAC Driver"}, 744 745 {"HSL Enable", NULL, "HSL Mute"}, 746 {"HSR Enable", NULL, "HSR Mute"}, 747 748 {"HSL Volume", NULL, "HSL Enable"}, 749 {"HSR Volume", NULL, "HSR Enable"}, 750 751 {"Headset Left", NULL, "HSL Volume"}, 752 {"Headset Right", NULL, "HSR Volume"}, 753 754 /* HF or LineOut path */ 755 756 {"DA_IN3", NULL, "ab8500_0p"}, 757 {"DA3 Channel Volume", NULL, "DA_IN3"}, 758 {"DA_IN4", NULL, "ab8500_0p"}, 759 {"DA4 Channel Volume", NULL, "DA_IN4"}, 760 761 {"Speaker Left Source", "Audio Path", "DA3 Channel Volume"}, 762 {"Speaker Right Source", "Audio Path", "DA4 Channel Volume"}, 763 764 {"DA3 or ANC path to HfL", NULL, "Speaker Left Source"}, 765 {"DA4 or ANC path to HfR", NULL, "Speaker Right Source"}, 766 767 /* HF path */ 768 769 {"HFL DAC", NULL, "DA3 or ANC path to HfL"}, 770 {"HFR DAC", NULL, "DA4 or ANC path to HfR"}, 771 772 {"HFL Enable", NULL, "HFL DAC"}, 773 {"HFR Enable", NULL, "HFR DAC"}, 774 775 {"Speaker Left", NULL, "HFL Enable"}, 776 {"Speaker Right", NULL, "HFR Enable"}, 777 778 /* Earpiece path */ 779 780 {"Earpiece or LineOut Mono Source", "Headset Left", 781 "HSL Digital Volume"}, 782 {"Earpiece or LineOut Mono Source", "Speaker Left", 783 "DA3 or ANC path to HfL"}, 784 785 {"EAR DAC", NULL, "Earpiece or LineOut Mono Source"}, 786 787 {"EAR Mute", NULL, "EAR DAC"}, 788 789 {"EAR Enable", NULL, "EAR Mute"}, 790 791 {"Earpiece", NULL, "EAR Enable"}, 792 793 /* LineOut path stereo */ 794 795 {"LineOut Source", "Stereo Path", "HSL DAC Driver"}, 796 {"LineOut Source", "Stereo Path", "HSR DAC Driver"}, 797 798 /* LineOut path mono */ 799 800 {"LineOut Source", "Mono Path", "EAR DAC"}, 801 802 /* LineOut path */ 803 804 {"LOL Disable HFL", NULL, "LineOut Source"}, 805 {"LOR Disable HFR", NULL, "LineOut Source"}, 806 807 {"LOL Enable", NULL, "LOL Disable HFL"}, 808 {"LOR Enable", NULL, "LOR Disable HFR"}, 809 810 {"LineOut Left", NULL, "LOL Enable"}, 811 {"LineOut Right", NULL, "LOR Enable"}, 812 813 /* Vibrator path */ 814 815 {"DA_IN5", NULL, "ab8500_0p"}, 816 {"DA5 Channel Volume", NULL, "DA_IN5"}, 817 {"DA_IN6", NULL, "ab8500_0p"}, 818 {"DA6 Channel Volume", NULL, "DA_IN6"}, 819 820 {"VIB1 DAC", NULL, "DA5 Channel Volume"}, 821 {"VIB2 DAC", NULL, "DA6 Channel Volume"}, 822 823 {"Vibra 1 Controller", "Audio Path", "VIB1 DAC"}, 824 {"Vibra 2 Controller", "Audio Path", "VIB2 DAC"}, 825 {"Vibra 1 Controller", "PWM Generator", "PWMGEN1"}, 826 {"Vibra 2 Controller", "PWM Generator", "PWMGEN2"}, 827 828 {"VIB1 Enable", NULL, "Vibra 1 Controller"}, 829 {"VIB2 Enable", NULL, "Vibra 2 Controller"}, 830 831 {"Vibra 1", NULL, "VIB1 Enable"}, 832 {"Vibra 2", NULL, "VIB2 Enable"}, 833 834 835 /* Mic 2 */ 836 837 {"MIC2 V-AMICx Enable", NULL, "Mic 2"}, 838 839 /* LineIn */ 840 {"LINL Mute", NULL, "LineIn Left"}, 841 {"LINR Mute", NULL, "LineIn Right"}, 842 843 {"LINL Enable", NULL, "LINL Mute"}, 844 {"LINR Enable", NULL, "LINR Mute"}, 845 846 /* LineIn, Mic 2 */ 847 {"Mic 2 or LINR Select", "LineIn Right", "LINR Enable"}, 848 {"Mic 2 or LINR Select", "Mic 2", "MIC2 V-AMICx Enable"}, 849 850 {"LINL ADC", NULL, "LINL Enable"}, 851 {"LINR ADC", NULL, "Mic 2 or LINR Select"}, 852 853 {"AD1 Source Select", "LineIn Left", "LINL ADC"}, 854 {"AD2 Source Select", "LineIn Right", "LINR ADC"}, 855 856 {"AD1 Channel Volume", NULL, "AD1 Source Select"}, 857 {"AD2 Channel Volume", NULL, "AD2 Source Select"}, 858 859 {"AD12 Enable", NULL, "AD1 Channel Volume"}, 860 {"AD12 Enable", NULL, "AD2 Channel Volume"}, 861 862 {"AD_OUT1", NULL, "ab8500_0c"}, 863 {"AD_OUT1", NULL, "AD12 Enable"}, 864 {"AD_OUT2", NULL, "ab8500_0c"}, 865 {"AD_OUT2", NULL, "AD12 Enable"}, 866 867 /* Mic 1 */ 868 869 {"MIC1 Mute", NULL, "Mic 1"}, 870 871 {"MIC1A V-AMICx Enable", NULL, "MIC1 Mute"}, 872 {"MIC1B V-AMICx Enable", NULL, "MIC1 Mute"}, 873 874 {"Mic 1a or 1b Select", "Mic 1a", "MIC1A V-AMICx Enable"}, 875 {"Mic 1a or 1b Select", "Mic 1b", "MIC1B V-AMICx Enable"}, 876 877 {"MIC1 ADC", NULL, "Mic 1a or 1b Select"}, 878 879 {"AD3 Source Select", "Mic 1", "MIC1 ADC"}, 880 881 {"AD3 Channel Volume", NULL, "AD3 Source Select"}, 882 883 {"AD3 Enable", NULL, "AD3 Channel Volume"}, 884 885 {"AD_OUT3", NULL, "ab8500_0c"}, 886 {"AD_OUT3", NULL, "AD3 Enable"}, 887 888 /* HD Capture path */ 889 890 {"AD5 Source Select", "Mic 2", "LINR ADC"}, 891 {"AD6 Source Select", "Mic 1", "MIC1 ADC"}, 892 893 {"AD5 Channel Volume", NULL, "AD5 Source Select"}, 894 {"AD6 Channel Volume", NULL, "AD6 Source Select"}, 895 896 {"AD57 Enable", NULL, "AD5 Channel Volume"}, 897 {"AD68 Enable", NULL, "AD6 Channel Volume"}, 898 899 {"AD_OUT57", NULL, "ab8500_0c"}, 900 {"AD_OUT57", NULL, "AD57 Enable"}, 901 {"AD_OUT68", NULL, "ab8500_0c"}, 902 {"AD_OUT68", NULL, "AD68 Enable"}, 903 904 /* Digital Microphone path */ 905 906 {"DMic 1", NULL, "V-DMIC"}, 907 {"DMic 2", NULL, "V-DMIC"}, 908 {"DMic 3", NULL, "V-DMIC"}, 909 {"DMic 4", NULL, "V-DMIC"}, 910 {"DMic 5", NULL, "V-DMIC"}, 911 {"DMic 6", NULL, "V-DMIC"}, 912 913 {"AD1 Source Select", NULL, "DMic 1"}, 914 {"AD2 Source Select", NULL, "DMic 2"}, 915 {"AD3 Source Select", NULL, "DMic 3"}, 916 {"AD5 Source Select", NULL, "DMic 5"}, 917 {"AD6 Source Select", NULL, "DMic 6"}, 918 919 {"AD4 Channel Volume", NULL, "DMic 4"}, 920 {"AD4 Enable", NULL, "AD4 Channel Volume"}, 921 922 {"AD_OUT4", NULL, "ab8500_0c"}, 923 {"AD_OUT4", NULL, "AD4 Enable"}, 924 925 /* LineIn Bypass path */ 926 927 {"LINL to HSL Volume", NULL, "LINL Enable"}, 928 {"LINR to HSR Volume", NULL, "LINR Enable"}, 929 930 {"HSL DAC Driver", NULL, "LINL to HSL Volume"}, 931 {"HSR DAC Driver", NULL, "LINR to HSR Volume"}, 932 933 /* ANC path (Acoustic Noise Cancellation) */ 934 935 {"ANC Source", "Mic 2 / DMic 5", "AD5 Channel Volume"}, 936 {"ANC Source", "Mic 1 / DMic 6", "AD6 Channel Volume"}, 937 938 {"ANC", "Switch", "ANC Source"}, 939 940 {"Speaker Left Source", "ANC", "ANC"}, 941 {"Speaker Right Source", "ANC", "ANC"}, 942 {"ANC to Earpiece", "Switch", "ANC"}, 943 944 {"HSL Digital Volume", NULL, "ANC to Earpiece"}, 945 946 /* Sidetone Filter path */ 947 948 {"Sidetone Left Source", "LineIn Left", "AD12 Enable"}, 949 {"Sidetone Left Source", "LineIn Right", "AD12 Enable"}, 950 {"Sidetone Left Source", "Mic 1", "AD3 Enable"}, 951 {"Sidetone Left Source", "Headset Left", "DA_IN1"}, 952 {"Sidetone Right Source", "LineIn Right", "AD12 Enable"}, 953 {"Sidetone Right Source", "Mic 1", "AD3 Enable"}, 954 {"Sidetone Right Source", "DMic 4", "AD4 Enable"}, 955 {"Sidetone Right Source", "Headset Right", "DA_IN2"}, 956 957 {"STFIR1 Control", NULL, "Sidetone Left Source"}, 958 {"STFIR2 Control", NULL, "Sidetone Right Source"}, 959 960 {"STFIR1 Volume", NULL, "STFIR1 Control"}, 961 {"STFIR2 Volume", NULL, "STFIR2 Control"}, 962 963 {"DA1 Enable", NULL, "STFIR1 Volume"}, 964 {"DA2 Enable", NULL, "STFIR2 Volume"}, 965 }; 966 967 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1a_vamicx[] = { 968 {"MIC1A V-AMICx Enable", NULL, "V-AMIC1"}, 969 {"MIC1A V-AMICx Enable", NULL, "V-AMIC2"}, 970 }; 971 972 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1b_vamicx[] = { 973 {"MIC1B V-AMICx Enable", NULL, "V-AMIC1"}, 974 {"MIC1B V-AMICx Enable", NULL, "V-AMIC2"}, 975 }; 976 977 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic2_vamicx[] = { 978 {"MIC2 V-AMICx Enable", NULL, "V-AMIC1"}, 979 {"MIC2 V-AMICx Enable", NULL, "V-AMIC2"}, 980 }; 981 982 /* 983 * Control-events 984 */ 985 986 static int sid_status_control_get(struct snd_kcontrol *kcontrol, 987 struct snd_ctl_elem_value *ucontrol) 988 { 989 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 990 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev); 991 992 mutex_lock(&drvdata->ctrl_lock); 993 ucontrol->value.enumerated.item[0] = drvdata->sid_status; 994 mutex_unlock(&drvdata->ctrl_lock); 995 996 return 0; 997 } 998 999 /* Write sidetone FIR-coefficients configuration sequence */ 1000 static int sid_status_control_put(struct snd_kcontrol *kcontrol, 1001 struct snd_ctl_elem_value *ucontrol) 1002 { 1003 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1004 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev); 1005 unsigned int param, sidconf; 1006 int status = 1; 1007 1008 dev_dbg(component->dev, "%s: Enter\n", __func__); 1009 1010 if (ucontrol->value.enumerated.item[0] != SID_APPLY_FIR) { 1011 dev_err(component->dev, 1012 "%s: ERROR: This control supports '%s' only!\n", 1013 __func__, enum_sid_state[SID_APPLY_FIR]); 1014 return -EIO; 1015 } 1016 1017 mutex_lock(&drvdata->ctrl_lock); 1018 1019 sidconf = snd_soc_component_read(component, AB8500_SIDFIRCONF); 1020 if (((sidconf & BIT(AB8500_SIDFIRCONF_FIRSIDBUSY)) != 0)) { 1021 if ((sidconf & BIT(AB8500_SIDFIRCONF_ENFIRSIDS)) == 0) { 1022 dev_err(component->dev, "%s: Sidetone busy while off!\n", 1023 __func__); 1024 status = -EPERM; 1025 } else { 1026 status = -EBUSY; 1027 } 1028 goto out; 1029 } 1030 1031 snd_soc_component_write(component, AB8500_SIDFIRADR, 0); 1032 1033 for (param = 0; param < AB8500_SID_FIR_COEFFS; param++) { 1034 snd_soc_component_write(component, AB8500_SIDFIRCOEF1, 0); 1035 snd_soc_component_write(component, AB8500_SIDFIRCOEF2, 0); 1036 } 1037 1038 snd_soc_component_update_bits(component, AB8500_SIDFIRADR, 1039 BIT(AB8500_SIDFIRADR_FIRSIDSET), 1040 BIT(AB8500_SIDFIRADR_FIRSIDSET)); 1041 snd_soc_component_update_bits(component, AB8500_SIDFIRADR, 1042 BIT(AB8500_SIDFIRADR_FIRSIDSET), 0); 1043 1044 drvdata->sid_status = SID_FIR_CONFIGURED; 1045 1046 out: 1047 mutex_unlock(&drvdata->ctrl_lock); 1048 1049 dev_dbg(component->dev, "%s: Exit\n", __func__); 1050 1051 return status; 1052 } 1053 1054 /* 1055 * Controls - Non-DAPM ASoC 1056 */ 1057 1058 static DECLARE_TLV_DB_SCALE(adx_dig_gain_tlv, -3200, 100, 1); 1059 /* -32dB = Mute */ 1060 1061 static DECLARE_TLV_DB_SCALE(dax_dig_gain_tlv, -6300, 100, 1); 1062 /* -63dB = Mute */ 1063 1064 static DECLARE_TLV_DB_SCALE(hs_ear_dig_gain_tlv, -100, 100, 1); 1065 /* -1dB = Mute */ 1066 1067 static const DECLARE_TLV_DB_RANGE(hs_gain_tlv, 1068 0, 3, TLV_DB_SCALE_ITEM(-3200, 400, 0), 1069 4, 15, TLV_DB_SCALE_ITEM(-1800, 200, 0) 1070 ); 1071 1072 static DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0); 1073 1074 static DECLARE_TLV_DB_SCALE(lin_gain_tlv, -1000, 200, 0); 1075 1076 static DECLARE_TLV_DB_SCALE(lin2hs_gain_tlv, -3800, 200, 1); 1077 /* -38dB = Mute */ 1078 1079 static const char * const enum_hsfadspeed[] = {"2ms", "0.5ms", "10.6ms", 1080 "5ms"}; 1081 static SOC_ENUM_SINGLE_DECL(soc_enum_hsfadspeed, 1082 AB8500_DIGMICCONF, AB8500_DIGMICCONF_HSFADSPEED, enum_hsfadspeed); 1083 1084 static const char * const enum_envdetthre[] = { 1085 "250mV", "300mV", "350mV", "400mV", 1086 "450mV", "500mV", "550mV", "600mV", 1087 "650mV", "700mV", "750mV", "800mV", 1088 "850mV", "900mV", "950mV", "1.00V" }; 1089 static SOC_ENUM_SINGLE_DECL(soc_enum_envdeththre, 1090 AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETHTHRE, enum_envdetthre); 1091 static SOC_ENUM_SINGLE_DECL(soc_enum_envdetlthre, 1092 AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETLTHRE, enum_envdetthre); 1093 static const char * const enum_envdettime[] = { 1094 "26.6us", "53.2us", "106us", "213us", 1095 "426us", "851us", "1.70ms", "3.40ms", 1096 "6.81ms", "13.6ms", "27.2ms", "54.5ms", 1097 "109ms", "218ms", "436ms", "872ms" }; 1098 static SOC_ENUM_SINGLE_DECL(soc_enum_envdettime, 1099 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETTIME, enum_envdettime); 1100 1101 static const char * const enum_sinc31[] = {"Sinc 3", "Sinc 1"}; 1102 static SOC_ENUM_SINGLE_DECL(soc_enum_hsesinc, AB8500_HSLEARDIGGAIN, 1103 AB8500_HSLEARDIGGAIN_HSSINC1, enum_sinc31); 1104 1105 static const char * const enum_fadespeed[] = {"1ms", "4ms", "8ms", "16ms"}; 1106 static SOC_ENUM_SINGLE_DECL(soc_enum_fadespeed, AB8500_HSRDIGGAIN, 1107 AB8500_HSRDIGGAIN_FADESPEED, enum_fadespeed); 1108 1109 /* Earpiece */ 1110 1111 static const char * const enum_lowpow[] = {"Normal", "Low Power"}; 1112 static SOC_ENUM_SINGLE_DECL(soc_enum_eardaclowpow, AB8500_ANACONF1, 1113 AB8500_ANACONF1_EARDACLOWPOW, enum_lowpow); 1114 static SOC_ENUM_SINGLE_DECL(soc_enum_eardrvlowpow, AB8500_ANACONF1, 1115 AB8500_ANACONF1_EARDRVLOWPOW, enum_lowpow); 1116 1117 static const char * const enum_av_mode[] = {"Audio", "Voice"}; 1118 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad12voice, AB8500_ADFILTCONF, 1119 AB8500_ADFILTCONF_AD1VOICE, AB8500_ADFILTCONF_AD2VOICE, enum_av_mode); 1120 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad34voice, AB8500_ADFILTCONF, 1121 AB8500_ADFILTCONF_AD3VOICE, AB8500_ADFILTCONF_AD4VOICE, enum_av_mode); 1122 1123 /* DA */ 1124 1125 static SOC_ENUM_SINGLE_DECL(soc_enum_da12voice, 1126 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DA12VOICE, 1127 enum_av_mode); 1128 static SOC_ENUM_SINGLE_DECL(soc_enum_da34voice, 1129 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DA34VOICE, 1130 enum_av_mode); 1131 static SOC_ENUM_SINGLE_DECL(soc_enum_da56voice, 1132 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DA56VOICE, 1133 enum_av_mode); 1134 1135 static const char * const enum_da2hslr[] = {"Sidetone", "Audio Path"}; 1136 static SOC_ENUM_DOUBLE_DECL(soc_enum_da2hslr, AB8500_DIGMULTCONF1, 1137 AB8500_DIGMULTCONF1_DATOHSLEN, 1138 AB8500_DIGMULTCONF1_DATOHSREN, enum_da2hslr); 1139 1140 static const char * const enum_sinc53[] = {"Sinc 5", "Sinc 3"}; 1141 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic12sinc, AB8500_DMICFILTCONF, 1142 AB8500_DMICFILTCONF_DMIC1SINC3, 1143 AB8500_DMICFILTCONF_DMIC2SINC3, enum_sinc53); 1144 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic34sinc, AB8500_DMICFILTCONF, 1145 AB8500_DMICFILTCONF_DMIC3SINC3, 1146 AB8500_DMICFILTCONF_DMIC4SINC3, enum_sinc53); 1147 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic56sinc, AB8500_DMICFILTCONF, 1148 AB8500_DMICFILTCONF_DMIC5SINC3, 1149 AB8500_DMICFILTCONF_DMIC6SINC3, enum_sinc53); 1150 1151 /* Digital interface - DA from slot mapping */ 1152 static const char * const enum_da_from_slot_map[] = {"SLOT0", 1153 "SLOT1", 1154 "SLOT2", 1155 "SLOT3", 1156 "SLOT4", 1157 "SLOT5", 1158 "SLOT6", 1159 "SLOT7", 1160 "SLOT8", 1161 "SLOT9", 1162 "SLOT10", 1163 "SLOT11", 1164 "SLOT12", 1165 "SLOT13", 1166 "SLOT14", 1167 "SLOT15", 1168 "SLOT16", 1169 "SLOT17", 1170 "SLOT18", 1171 "SLOT19", 1172 "SLOT20", 1173 "SLOT21", 1174 "SLOT22", 1175 "SLOT23", 1176 "SLOT24", 1177 "SLOT25", 1178 "SLOT26", 1179 "SLOT27", 1180 "SLOT28", 1181 "SLOT29", 1182 "SLOT30", 1183 "SLOT31"}; 1184 static SOC_ENUM_SINGLE_DECL(soc_enum_da1slotmap, 1185 AB8500_DASLOTCONF1, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1186 enum_da_from_slot_map); 1187 static SOC_ENUM_SINGLE_DECL(soc_enum_da2slotmap, 1188 AB8500_DASLOTCONF2, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1189 enum_da_from_slot_map); 1190 static SOC_ENUM_SINGLE_DECL(soc_enum_da3slotmap, 1191 AB8500_DASLOTCONF3, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1192 enum_da_from_slot_map); 1193 static SOC_ENUM_SINGLE_DECL(soc_enum_da4slotmap, 1194 AB8500_DASLOTCONF4, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1195 enum_da_from_slot_map); 1196 static SOC_ENUM_SINGLE_DECL(soc_enum_da5slotmap, 1197 AB8500_DASLOTCONF5, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1198 enum_da_from_slot_map); 1199 static SOC_ENUM_SINGLE_DECL(soc_enum_da6slotmap, 1200 AB8500_DASLOTCONF6, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1201 enum_da_from_slot_map); 1202 static SOC_ENUM_SINGLE_DECL(soc_enum_da7slotmap, 1203 AB8500_DASLOTCONF7, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1204 enum_da_from_slot_map); 1205 static SOC_ENUM_SINGLE_DECL(soc_enum_da8slotmap, 1206 AB8500_DASLOTCONF8, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1207 enum_da_from_slot_map); 1208 1209 /* Digital interface - AD to slot mapping */ 1210 static const char * const enum_ad_to_slot_map[] = {"AD_OUT1", 1211 "AD_OUT2", 1212 "AD_OUT3", 1213 "AD_OUT4", 1214 "AD_OUT5", 1215 "AD_OUT6", 1216 "AD_OUT7", 1217 "AD_OUT8", 1218 "zeroes", 1219 "zeroes", 1220 "zeroes", 1221 "zeroes", 1222 "tristate", 1223 "tristate", 1224 "tristate", 1225 "tristate"}; 1226 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot0map, 1227 AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_EVEN_SHIFT, 1228 enum_ad_to_slot_map); 1229 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot1map, 1230 AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_ODD_SHIFT, 1231 enum_ad_to_slot_map); 1232 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot2map, 1233 AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_EVEN_SHIFT, 1234 enum_ad_to_slot_map); 1235 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot3map, 1236 AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_ODD_SHIFT, 1237 enum_ad_to_slot_map); 1238 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot4map, 1239 AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_EVEN_SHIFT, 1240 enum_ad_to_slot_map); 1241 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot5map, 1242 AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_ODD_SHIFT, 1243 enum_ad_to_slot_map); 1244 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot6map, 1245 AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_EVEN_SHIFT, 1246 enum_ad_to_slot_map); 1247 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot7map, 1248 AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_ODD_SHIFT, 1249 enum_ad_to_slot_map); 1250 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot8map, 1251 AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_EVEN_SHIFT, 1252 enum_ad_to_slot_map); 1253 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot9map, 1254 AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_ODD_SHIFT, 1255 enum_ad_to_slot_map); 1256 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot10map, 1257 AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_EVEN_SHIFT, 1258 enum_ad_to_slot_map); 1259 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot11map, 1260 AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_ODD_SHIFT, 1261 enum_ad_to_slot_map); 1262 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot12map, 1263 AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_EVEN_SHIFT, 1264 enum_ad_to_slot_map); 1265 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot13map, 1266 AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_ODD_SHIFT, 1267 enum_ad_to_slot_map); 1268 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot14map, 1269 AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_EVEN_SHIFT, 1270 enum_ad_to_slot_map); 1271 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot15map, 1272 AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_ODD_SHIFT, 1273 enum_ad_to_slot_map); 1274 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot16map, 1275 AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_EVEN_SHIFT, 1276 enum_ad_to_slot_map); 1277 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot17map, 1278 AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_ODD_SHIFT, 1279 enum_ad_to_slot_map); 1280 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot18map, 1281 AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_EVEN_SHIFT, 1282 enum_ad_to_slot_map); 1283 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot19map, 1284 AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_ODD_SHIFT, 1285 enum_ad_to_slot_map); 1286 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot20map, 1287 AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_EVEN_SHIFT, 1288 enum_ad_to_slot_map); 1289 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot21map, 1290 AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_ODD_SHIFT, 1291 enum_ad_to_slot_map); 1292 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot22map, 1293 AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_EVEN_SHIFT, 1294 enum_ad_to_slot_map); 1295 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot23map, 1296 AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_ODD_SHIFT, 1297 enum_ad_to_slot_map); 1298 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot24map, 1299 AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_EVEN_SHIFT, 1300 enum_ad_to_slot_map); 1301 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot25map, 1302 AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_ODD_SHIFT, 1303 enum_ad_to_slot_map); 1304 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot26map, 1305 AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_EVEN_SHIFT, 1306 enum_ad_to_slot_map); 1307 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot27map, 1308 AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_ODD_SHIFT, 1309 enum_ad_to_slot_map); 1310 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot28map, 1311 AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_EVEN_SHIFT, 1312 enum_ad_to_slot_map); 1313 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot29map, 1314 AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_ODD_SHIFT, 1315 enum_ad_to_slot_map); 1316 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot30map, 1317 AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_EVEN_SHIFT, 1318 enum_ad_to_slot_map); 1319 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot31map, 1320 AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_ODD_SHIFT, 1321 enum_ad_to_slot_map); 1322 1323 /* Digital interface - Burst mode */ 1324 static const char * const enum_mask[] = {"Unmasked", "Masked"}; 1325 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomask, 1326 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOMASK, 1327 enum_mask); 1328 static const char * const enum_bitclk0[] = {"19_2_MHz", "38_4_MHz"}; 1329 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifo19m2, 1330 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFO19M2, 1331 enum_bitclk0); 1332 static const char * const enum_slavemaster[] = {"Slave", "Master"}; 1333 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomast, 1334 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOMAST_SHIFT, 1335 enum_slavemaster); 1336 1337 /* Sidetone */ 1338 static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_sidstate, enum_sid_state); 1339 1340 /* ANC */ 1341 1342 static struct snd_kcontrol_new ab8500_ctrls[] = { 1343 /* Charge pump */ 1344 SOC_ENUM("Charge Pump High Threshold For Low Voltage", 1345 soc_enum_envdeththre), 1346 SOC_ENUM("Charge Pump Low Threshold For Low Voltage", 1347 soc_enum_envdetlthre), 1348 SOC_SINGLE("Charge Pump Envelope Detection Switch", 1349 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETCPEN, 1350 1, 0), 1351 SOC_ENUM("Charge Pump Envelope Detection Decay Time", 1352 soc_enum_envdettime), 1353 1354 /* Headset */ 1355 SOC_ENUM("Headset Mode", soc_enum_da12voice), 1356 SOC_SINGLE("Headset High Pass Switch", 1357 AB8500_ANACONF1, AB8500_ANACONF1_HSHPEN, 1358 1, 0), 1359 SOC_SINGLE("Headset Low Power Switch", 1360 AB8500_ANACONF1, AB8500_ANACONF1_HSLOWPOW, 1361 1, 0), 1362 SOC_SINGLE("Headset DAC Low Power Switch", 1363 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW1, 1364 1, 0), 1365 SOC_SINGLE("Headset DAC Drv Low Power Switch", 1366 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW0, 1367 1, 0), 1368 SOC_ENUM("Headset Fade Speed", soc_enum_hsfadspeed), 1369 SOC_ENUM("Headset Source", soc_enum_da2hslr), 1370 SOC_ENUM("Headset Filter", soc_enum_hsesinc), 1371 SOC_DOUBLE_R_TLV("Headset Master Volume", 1372 AB8500_DADIGGAIN1, AB8500_DADIGGAIN2, 1373 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv), 1374 SOC_DOUBLE_R_TLV("Headset Digital Volume", 1375 AB8500_HSLEARDIGGAIN, AB8500_HSRDIGGAIN, 1376 0, AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX, 1, hs_ear_dig_gain_tlv), 1377 SOC_DOUBLE_TLV("Headset Volume", 1378 AB8500_ANAGAIN3, 1379 AB8500_ANAGAIN3_HSLGAIN, AB8500_ANAGAIN3_HSRGAIN, 1380 AB8500_ANAGAIN3_HSXGAIN_MAX, 1, hs_gain_tlv), 1381 1382 /* Earpiece */ 1383 SOC_ENUM("Earpiece DAC Mode", 1384 soc_enum_eardaclowpow), 1385 SOC_ENUM("Earpiece DAC Drv Mode", 1386 soc_enum_eardrvlowpow), 1387 1388 /* HandsFree */ 1389 SOC_ENUM("HF Mode", soc_enum_da34voice), 1390 SOC_SINGLE("HF and Headset Swap Switch", 1391 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_SWAPDA12_34, 1392 1, 0), 1393 SOC_DOUBLE("HF Low EMI Mode Switch", 1394 AB8500_CLASSDCONF1, 1395 AB8500_CLASSDCONF1_HFLSWAPEN, AB8500_CLASSDCONF1_HFRSWAPEN, 1396 1, 0), 1397 SOC_DOUBLE("HF FIR Bypass Switch", 1398 AB8500_CLASSDCONF2, 1399 AB8500_CLASSDCONF2_FIRBYP0, AB8500_CLASSDCONF2_FIRBYP1, 1400 1, 0), 1401 SOC_DOUBLE("HF High Volume Switch", 1402 AB8500_CLASSDCONF2, 1403 AB8500_CLASSDCONF2_HIGHVOLEN0, AB8500_CLASSDCONF2_HIGHVOLEN1, 1404 1, 0), 1405 SOC_SINGLE("HF L and R Bridge Switch", 1406 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLHF, 1407 1, 0), 1408 SOC_DOUBLE_R_TLV("HF Master Volume", 1409 AB8500_DADIGGAIN3, AB8500_DADIGGAIN4, 1410 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv), 1411 1412 /* Vibra */ 1413 SOC_DOUBLE("Vibra High Volume Switch", 1414 AB8500_CLASSDCONF2, 1415 AB8500_CLASSDCONF2_HIGHVOLEN2, AB8500_CLASSDCONF2_HIGHVOLEN3, 1416 1, 0), 1417 SOC_DOUBLE("Vibra Low EMI Mode Switch", 1418 AB8500_CLASSDCONF1, 1419 AB8500_CLASSDCONF1_VIB1SWAPEN, AB8500_CLASSDCONF1_VIB2SWAPEN, 1420 1, 0), 1421 SOC_DOUBLE("Vibra FIR Bypass Switch", 1422 AB8500_CLASSDCONF2, 1423 AB8500_CLASSDCONF2_FIRBYP2, AB8500_CLASSDCONF2_FIRBYP3, 1424 1, 0), 1425 SOC_ENUM("Vibra Mode", soc_enum_da56voice), 1426 SOC_DOUBLE_R("Vibra PWM Duty Cycle N", 1427 AB8500_PWMGENCONF3, AB8500_PWMGENCONF5, 1428 AB8500_PWMGENCONFX_PWMVIBXDUTCYC, 1429 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0), 1430 SOC_DOUBLE_R("Vibra PWM Duty Cycle P", 1431 AB8500_PWMGENCONF2, AB8500_PWMGENCONF4, 1432 AB8500_PWMGENCONFX_PWMVIBXDUTCYC, 1433 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0), 1434 SOC_SINGLE("Vibra 1 and 2 Bridge Switch", 1435 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLVIB, 1436 1, 0), 1437 SOC_DOUBLE_R_TLV("Vibra Master Volume", 1438 AB8500_DADIGGAIN5, AB8500_DADIGGAIN6, 1439 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv), 1440 1441 /* HandsFree, Vibra */ 1442 SOC_SINGLE("ClassD High Pass Volume", 1443 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHHPGAIN, 1444 AB8500_CLASSDCONF3_DITHHPGAIN_MAX, 0), 1445 SOC_SINGLE("ClassD White Volume", 1446 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHWGAIN, 1447 AB8500_CLASSDCONF3_DITHWGAIN_MAX, 0), 1448 1449 /* Mic 1, Mic 2, LineIn */ 1450 SOC_DOUBLE_R_TLV("Mic Master Volume", 1451 AB8500_ADDIGGAIN3, AB8500_ADDIGGAIN4, 1452 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv), 1453 1454 /* Mic 1 */ 1455 SOC_SINGLE_TLV("Mic 1", 1456 AB8500_ANAGAIN1, 1457 AB8500_ANAGAINX_MICXGAIN, 1458 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv), 1459 SOC_SINGLE("Mic 1 Low Power Switch", 1460 AB8500_ANAGAIN1, AB8500_ANAGAINX_LOWPOWMICX, 1461 1, 0), 1462 1463 /* Mic 2 */ 1464 SOC_DOUBLE("Mic High Pass Switch", 1465 AB8500_ADFILTCONF, 1466 AB8500_ADFILTCONF_AD3NH, AB8500_ADFILTCONF_AD4NH, 1467 1, 1), 1468 SOC_ENUM("Mic Mode", soc_enum_ad34voice), 1469 SOC_ENUM("Mic Filter", soc_enum_dmic34sinc), 1470 SOC_SINGLE_TLV("Mic 2", 1471 AB8500_ANAGAIN2, 1472 AB8500_ANAGAINX_MICXGAIN, 1473 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv), 1474 SOC_SINGLE("Mic 2 Low Power Switch", 1475 AB8500_ANAGAIN2, AB8500_ANAGAINX_LOWPOWMICX, 1476 1, 0), 1477 1478 /* LineIn */ 1479 SOC_DOUBLE("LineIn High Pass Switch", 1480 AB8500_ADFILTCONF, 1481 AB8500_ADFILTCONF_AD1NH, AB8500_ADFILTCONF_AD2NH, 1482 1, 1), 1483 SOC_ENUM("LineIn Filter", soc_enum_dmic12sinc), 1484 SOC_ENUM("LineIn Mode", soc_enum_ad12voice), 1485 SOC_DOUBLE_R_TLV("LineIn Master Volume", 1486 AB8500_ADDIGGAIN1, AB8500_ADDIGGAIN2, 1487 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv), 1488 SOC_DOUBLE_TLV("LineIn", 1489 AB8500_ANAGAIN4, 1490 AB8500_ANAGAIN4_LINLGAIN, AB8500_ANAGAIN4_LINRGAIN, 1491 AB8500_ANAGAIN4_LINXGAIN_MAX, 0, lin_gain_tlv), 1492 SOC_DOUBLE_R_TLV("LineIn to Headset Volume", 1493 AB8500_DIGLINHSLGAIN, AB8500_DIGLINHSRGAIN, 1494 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN, 1495 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX, 1496 1, lin2hs_gain_tlv), 1497 1498 /* DMic */ 1499 SOC_ENUM("DMic Filter", soc_enum_dmic56sinc), 1500 SOC_DOUBLE_R_TLV("DMic Master Volume", 1501 AB8500_ADDIGGAIN5, AB8500_ADDIGGAIN6, 1502 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv), 1503 1504 /* Digital gains */ 1505 SOC_ENUM("Digital Gain Fade Speed", soc_enum_fadespeed), 1506 1507 /* Analog loopback */ 1508 SOC_DOUBLE_R_TLV("Analog Loopback Volume", 1509 AB8500_ADDIGLOOPGAIN1, AB8500_ADDIGLOOPGAIN2, 1510 0, AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX, 1, dax_dig_gain_tlv), 1511 1512 /* Digital interface - DA from slot mapping */ 1513 SOC_ENUM("Digital Interface DA 1 From Slot Map", soc_enum_da1slotmap), 1514 SOC_ENUM("Digital Interface DA 2 From Slot Map", soc_enum_da2slotmap), 1515 SOC_ENUM("Digital Interface DA 3 From Slot Map", soc_enum_da3slotmap), 1516 SOC_ENUM("Digital Interface DA 4 From Slot Map", soc_enum_da4slotmap), 1517 SOC_ENUM("Digital Interface DA 5 From Slot Map", soc_enum_da5slotmap), 1518 SOC_ENUM("Digital Interface DA 6 From Slot Map", soc_enum_da6slotmap), 1519 SOC_ENUM("Digital Interface DA 7 From Slot Map", soc_enum_da7slotmap), 1520 SOC_ENUM("Digital Interface DA 8 From Slot Map", soc_enum_da8slotmap), 1521 1522 /* Digital interface - AD to slot mapping */ 1523 SOC_ENUM("Digital Interface AD To Slot 0 Map", soc_enum_adslot0map), 1524 SOC_ENUM("Digital Interface AD To Slot 1 Map", soc_enum_adslot1map), 1525 SOC_ENUM("Digital Interface AD To Slot 2 Map", soc_enum_adslot2map), 1526 SOC_ENUM("Digital Interface AD To Slot 3 Map", soc_enum_adslot3map), 1527 SOC_ENUM("Digital Interface AD To Slot 4 Map", soc_enum_adslot4map), 1528 SOC_ENUM("Digital Interface AD To Slot 5 Map", soc_enum_adslot5map), 1529 SOC_ENUM("Digital Interface AD To Slot 6 Map", soc_enum_adslot6map), 1530 SOC_ENUM("Digital Interface AD To Slot 7 Map", soc_enum_adslot7map), 1531 SOC_ENUM("Digital Interface AD To Slot 8 Map", soc_enum_adslot8map), 1532 SOC_ENUM("Digital Interface AD To Slot 9 Map", soc_enum_adslot9map), 1533 SOC_ENUM("Digital Interface AD To Slot 10 Map", soc_enum_adslot10map), 1534 SOC_ENUM("Digital Interface AD To Slot 11 Map", soc_enum_adslot11map), 1535 SOC_ENUM("Digital Interface AD To Slot 12 Map", soc_enum_adslot12map), 1536 SOC_ENUM("Digital Interface AD To Slot 13 Map", soc_enum_adslot13map), 1537 SOC_ENUM("Digital Interface AD To Slot 14 Map", soc_enum_adslot14map), 1538 SOC_ENUM("Digital Interface AD To Slot 15 Map", soc_enum_adslot15map), 1539 SOC_ENUM("Digital Interface AD To Slot 16 Map", soc_enum_adslot16map), 1540 SOC_ENUM("Digital Interface AD To Slot 17 Map", soc_enum_adslot17map), 1541 SOC_ENUM("Digital Interface AD To Slot 18 Map", soc_enum_adslot18map), 1542 SOC_ENUM("Digital Interface AD To Slot 19 Map", soc_enum_adslot19map), 1543 SOC_ENUM("Digital Interface AD To Slot 20 Map", soc_enum_adslot20map), 1544 SOC_ENUM("Digital Interface AD To Slot 21 Map", soc_enum_adslot21map), 1545 SOC_ENUM("Digital Interface AD To Slot 22 Map", soc_enum_adslot22map), 1546 SOC_ENUM("Digital Interface AD To Slot 23 Map", soc_enum_adslot23map), 1547 SOC_ENUM("Digital Interface AD To Slot 24 Map", soc_enum_adslot24map), 1548 SOC_ENUM("Digital Interface AD To Slot 25 Map", soc_enum_adslot25map), 1549 SOC_ENUM("Digital Interface AD To Slot 26 Map", soc_enum_adslot26map), 1550 SOC_ENUM("Digital Interface AD To Slot 27 Map", soc_enum_adslot27map), 1551 SOC_ENUM("Digital Interface AD To Slot 28 Map", soc_enum_adslot28map), 1552 SOC_ENUM("Digital Interface AD To Slot 29 Map", soc_enum_adslot29map), 1553 SOC_ENUM("Digital Interface AD To Slot 30 Map", soc_enum_adslot30map), 1554 SOC_ENUM("Digital Interface AD To Slot 31 Map", soc_enum_adslot31map), 1555 1556 /* Digital interface - Loopback */ 1557 SOC_SINGLE("Digital Interface AD 1 Loopback Switch", 1558 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DAI7TOADO1, 1559 1, 0), 1560 SOC_SINGLE("Digital Interface AD 2 Loopback Switch", 1561 AB8500_DASLOTCONF2, AB8500_DASLOTCONF2_DAI8TOADO2, 1562 1, 0), 1563 SOC_SINGLE("Digital Interface AD 3 Loopback Switch", 1564 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DAI7TOADO3, 1565 1, 0), 1566 SOC_SINGLE("Digital Interface AD 4 Loopback Switch", 1567 AB8500_DASLOTCONF4, AB8500_DASLOTCONF4_DAI8TOADO4, 1568 1, 0), 1569 SOC_SINGLE("Digital Interface AD 5 Loopback Switch", 1570 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DAI7TOADO5, 1571 1, 0), 1572 SOC_SINGLE("Digital Interface AD 6 Loopback Switch", 1573 AB8500_DASLOTCONF6, AB8500_DASLOTCONF6_DAI8TOADO6, 1574 1, 0), 1575 SOC_SINGLE("Digital Interface AD 7 Loopback Switch", 1576 AB8500_DASLOTCONF7, AB8500_DASLOTCONF7_DAI8TOADO7, 1577 1, 0), 1578 SOC_SINGLE("Digital Interface AD 8 Loopback Switch", 1579 AB8500_DASLOTCONF8, AB8500_DASLOTCONF8_DAI7TOADO8, 1580 1, 0), 1581 1582 /* Digital interface - Burst FIFO */ 1583 SOC_SINGLE("Digital Interface 0 FIFO Enable Switch", 1584 AB8500_DIGIFCONF3, AB8500_DIGIFCONF3_IF0BFIFOEN, 1585 1, 0), 1586 SOC_ENUM("Burst FIFO Mask", soc_enum_bfifomask), 1587 SOC_ENUM("Burst FIFO Bit-clock Frequency", soc_enum_bfifo19m2), 1588 SOC_SINGLE("Burst FIFO Threshold", 1589 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOINT_SHIFT, 1590 AB8500_FIFOCONF1_BFIFOINT_MAX, 0), 1591 SOC_SINGLE("Burst FIFO Length", 1592 AB8500_FIFOCONF2, AB8500_FIFOCONF2_BFIFOTX_SHIFT, 1593 AB8500_FIFOCONF2_BFIFOTX_MAX, 0), 1594 SOC_SINGLE("Burst FIFO EOS Extra Slots", 1595 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOEXSL_SHIFT, 1596 AB8500_FIFOCONF3_BFIFOEXSL_MAX, 0), 1597 SOC_SINGLE("Burst FIFO FS Extra Bit-clocks", 1598 AB8500_FIFOCONF3, AB8500_FIFOCONF3_PREBITCLK0_SHIFT, 1599 AB8500_FIFOCONF3_PREBITCLK0_MAX, 0), 1600 SOC_ENUM("Burst FIFO Interface Mode", soc_enum_bfifomast), 1601 1602 SOC_SINGLE("Burst FIFO Interface Switch", 1603 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFORUN_SHIFT, 1604 1, 0), 1605 SOC_SINGLE("Burst FIFO Switch Frame Number", 1606 AB8500_FIFOCONF4, AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT, 1607 AB8500_FIFOCONF4_BFIFOFRAMSW_MAX, 0), 1608 SOC_SINGLE("Burst FIFO Wake Up Delay", 1609 AB8500_FIFOCONF5, AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT, 1610 AB8500_FIFOCONF5_BFIFOWAKEUP_MAX, 0), 1611 SOC_SINGLE("Burst FIFO Samples In FIFO", 1612 AB8500_FIFOCONF6, AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT, 1613 AB8500_FIFOCONF6_BFIFOSAMPLE_MAX, 0), 1614 1615 /* ANC */ 1616 SOC_SINGLE_XR_SX("ANC Warp Delay Shift", 1617 AB8500_ANCCONF2, 1, AB8500_ANCCONF2_SHIFT, 1618 AB8500_ANCCONF2_MIN, AB8500_ANCCONF2_MAX, 0), 1619 SOC_SINGLE_XR_SX("ANC FIR Output Shift", 1620 AB8500_ANCCONF3, 1, AB8500_ANCCONF3_SHIFT, 1621 AB8500_ANCCONF3_MIN, AB8500_ANCCONF3_MAX, 0), 1622 SOC_SINGLE_XR_SX("ANC IIR Output Shift", 1623 AB8500_ANCCONF4, 1, AB8500_ANCCONF4_SHIFT, 1624 AB8500_ANCCONF4_MIN, AB8500_ANCCONF4_MAX, 0), 1625 SOC_SINGLE_XR_SX("ANC Warp Delay", 1626 AB8500_ANCCONF9, 2, AB8500_ANC_WARP_DELAY_SHIFT, 1627 AB8500_ANC_WARP_DELAY_MIN, AB8500_ANC_WARP_DELAY_MAX, 0), 1628 1629 /* Sidetone */ 1630 SOC_ENUM_EXT("Sidetone Status", soc_enum_sidstate, 1631 sid_status_control_get, sid_status_control_put), 1632 SOC_SINGLE_STROBE("Sidetone Reset", 1633 AB8500_SIDFIRADR, AB8500_SIDFIRADR_FIRSIDSET, 0), 1634 }; 1635 1636 /* 1637 * Extended interface for codec-driver 1638 */ 1639 1640 static int ab8500_audio_init_audioblock(struct snd_soc_component *component) 1641 { 1642 int status; 1643 1644 dev_dbg(component->dev, "%s: Enter.\n", __func__); 1645 1646 /* Reset audio-registers and disable 32kHz-clock output 2 */ 1647 status = ab8500_sysctrl_write(AB8500_STW4500CTRL3, 1648 AB8500_STW4500CTRL3_CLK32KOUT2DIS | 1649 AB8500_STW4500CTRL3_RESETAUDN, 1650 AB8500_STW4500CTRL3_RESETAUDN); 1651 if (status < 0) 1652 return status; 1653 1654 return 0; 1655 } 1656 1657 static int ab8500_audio_setup_mics(struct snd_soc_component *component, 1658 struct amic_settings *amics) 1659 { 1660 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1661 u8 value8; 1662 unsigned int value; 1663 int status; 1664 const struct snd_soc_dapm_route *route; 1665 1666 dev_dbg(component->dev, "%s: Enter.\n", __func__); 1667 1668 /* Set DMic-clocks to outputs */ 1669 status = abx500_get_register_interruptible(component->dev, AB8500_MISC, 1670 AB8500_GPIO_DIR4_REG, 1671 &value8); 1672 if (status < 0) 1673 return status; 1674 value = value8 | GPIO27_DIR_OUTPUT | GPIO29_DIR_OUTPUT | 1675 GPIO31_DIR_OUTPUT; 1676 status = abx500_set_register_interruptible(component->dev, 1677 AB8500_MISC, 1678 AB8500_GPIO_DIR4_REG, 1679 value); 1680 if (status < 0) 1681 return status; 1682 1683 /* Attach regulators to AMic DAPM-paths */ 1684 dev_dbg(component->dev, "%s: Mic 1a regulator: %s\n", __func__, 1685 amic_micbias_str(amics->mic1a_micbias)); 1686 route = &ab8500_dapm_routes_mic1a_vamicx[amics->mic1a_micbias]; 1687 status = snd_soc_dapm_add_routes(dapm, route, 1); 1688 dev_dbg(component->dev, "%s: Mic 1b regulator: %s\n", __func__, 1689 amic_micbias_str(amics->mic1b_micbias)); 1690 route = &ab8500_dapm_routes_mic1b_vamicx[amics->mic1b_micbias]; 1691 status |= snd_soc_dapm_add_routes(dapm, route, 1); 1692 dev_dbg(component->dev, "%s: Mic 2 regulator: %s\n", __func__, 1693 amic_micbias_str(amics->mic2_micbias)); 1694 route = &ab8500_dapm_routes_mic2_vamicx[amics->mic2_micbias]; 1695 status |= snd_soc_dapm_add_routes(dapm, route, 1); 1696 if (status < 0) { 1697 dev_err(component->dev, 1698 "%s: Failed to add AMic-regulator DAPM-routes (%d).\n", 1699 __func__, status); 1700 return status; 1701 } 1702 1703 /* Set AMic-configuration */ 1704 dev_dbg(component->dev, "%s: Mic 1 mic-type: %s\n", __func__, 1705 amic_type_str(amics->mic1_type)); 1706 snd_soc_component_update_bits(component, AB8500_ANAGAIN1, AB8500_ANAGAINX_ENSEMICX, 1707 amics->mic1_type == AMIC_TYPE_DIFFERENTIAL ? 1708 0 : AB8500_ANAGAINX_ENSEMICX); 1709 dev_dbg(component->dev, "%s: Mic 2 mic-type: %s\n", __func__, 1710 amic_type_str(amics->mic2_type)); 1711 snd_soc_component_update_bits(component, AB8500_ANAGAIN2, AB8500_ANAGAINX_ENSEMICX, 1712 amics->mic2_type == AMIC_TYPE_DIFFERENTIAL ? 1713 0 : AB8500_ANAGAINX_ENSEMICX); 1714 1715 return 0; 1716 } 1717 1718 static int ab8500_audio_set_ear_cmv(struct snd_soc_component *component, 1719 enum ear_cm_voltage ear_cmv) 1720 { 1721 char *cmv_str; 1722 1723 switch (ear_cmv) { 1724 case EAR_CMV_0_95V: 1725 cmv_str = "0.95V"; 1726 break; 1727 case EAR_CMV_1_10V: 1728 cmv_str = "1.10V"; 1729 break; 1730 case EAR_CMV_1_27V: 1731 cmv_str = "1.27V"; 1732 break; 1733 case EAR_CMV_1_58V: 1734 cmv_str = "1.58V"; 1735 break; 1736 default: 1737 dev_err(component->dev, 1738 "%s: Unknown earpiece CM-voltage (%d)!\n", 1739 __func__, (int)ear_cmv); 1740 return -EINVAL; 1741 } 1742 dev_dbg(component->dev, "%s: Earpiece CM-voltage: %s\n", __func__, 1743 cmv_str); 1744 snd_soc_component_update_bits(component, AB8500_ANACONF1, AB8500_ANACONF1_EARSELCM, 1745 ear_cmv); 1746 1747 return 0; 1748 } 1749 1750 static int ab8500_audio_set_bit_delay(struct snd_soc_dai *dai, 1751 unsigned int delay) 1752 { 1753 unsigned int mask, val; 1754 struct snd_soc_component *component = dai->component; 1755 1756 mask = BIT(AB8500_DIGIFCONF2_IF0DEL); 1757 val = 0; 1758 1759 switch (delay) { 1760 case 0: 1761 break; 1762 case 1: 1763 val |= BIT(AB8500_DIGIFCONF2_IF0DEL); 1764 break; 1765 default: 1766 dev_err(dai->component->dev, 1767 "%s: ERROR: Unsupported bit-delay (0x%x)!\n", 1768 __func__, delay); 1769 return -EINVAL; 1770 } 1771 1772 dev_dbg(dai->component->dev, "%s: IF0 Bit-delay: %d bits.\n", 1773 __func__, delay); 1774 snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val); 1775 1776 return 0; 1777 } 1778 1779 /* Gates clocking according format mask */ 1780 static int ab8500_codec_set_dai_clock_gate(struct snd_soc_component *component, 1781 unsigned int fmt) 1782 { 1783 unsigned int mask; 1784 unsigned int val; 1785 1786 mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) | 1787 BIT(AB8500_DIGIFCONF1_ENFSBITCLK0); 1788 1789 val = BIT(AB8500_DIGIFCONF1_ENMASTGEN); 1790 1791 switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) { 1792 case SND_SOC_DAIFMT_CONT: /* continuous clock */ 1793 dev_dbg(component->dev, "%s: IF0 Clock is continuous.\n", 1794 __func__); 1795 val |= BIT(AB8500_DIGIFCONF1_ENFSBITCLK0); 1796 break; 1797 case SND_SOC_DAIFMT_GATED: /* clock is gated */ 1798 dev_dbg(component->dev, "%s: IF0 Clock is gated.\n", 1799 __func__); 1800 break; 1801 default: 1802 dev_err(component->dev, 1803 "%s: ERROR: Unsupported clock mask (0x%x)!\n", 1804 __func__, fmt & SND_SOC_DAIFMT_CLOCK_MASK); 1805 return -EINVAL; 1806 } 1807 1808 snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val); 1809 1810 return 0; 1811 } 1812 1813 static int ab8500_codec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1814 { 1815 unsigned int mask; 1816 unsigned int val; 1817 struct snd_soc_component *component = dai->component; 1818 int status; 1819 1820 dev_dbg(component->dev, "%s: Enter (fmt = 0x%x)\n", __func__, fmt); 1821 1822 mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) | 1823 BIT(AB8500_DIGIFCONF3_IF1CLKTOIF0CLK) | 1824 BIT(AB8500_DIGIFCONF3_IF0BFIFOEN) | 1825 BIT(AB8500_DIGIFCONF3_IF0MASTER); 1826 val = 0; 1827 1828 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1829 case SND_SOC_DAIFMT_CBP_CFP: 1830 dev_dbg(dai->component->dev, 1831 "%s: IF0 Master-mode: AB8500 provider.\n", __func__); 1832 val |= BIT(AB8500_DIGIFCONF3_IF0MASTER); 1833 break; 1834 case SND_SOC_DAIFMT_CBC_CFC: 1835 dev_dbg(dai->component->dev, 1836 "%s: IF0 Master-mode: AB8500 consumer.\n", __func__); 1837 break; 1838 case SND_SOC_DAIFMT_CBC_CFP: 1839 case SND_SOC_DAIFMT_CBP_CFC: 1840 dev_err(dai->component->dev, 1841 "%s: ERROR: The device is either a provider or a consumer.\n", 1842 __func__); 1843 fallthrough; 1844 default: 1845 dev_err(dai->component->dev, 1846 "%s: ERROR: Unsupporter clocking mask 0x%x\n", 1847 __func__, fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK); 1848 return -EINVAL; 1849 } 1850 1851 snd_soc_component_update_bits(component, AB8500_DIGIFCONF3, mask, val); 1852 1853 /* Set clock gating */ 1854 status = ab8500_codec_set_dai_clock_gate(component, fmt); 1855 if (status) { 1856 dev_err(dai->component->dev, 1857 "%s: ERROR: Failed to set clock gate (%d).\n", 1858 __func__, status); 1859 return status; 1860 } 1861 1862 /* Setting data transfer format */ 1863 1864 mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) | 1865 BIT(AB8500_DIGIFCONF2_IF0FORMAT1) | 1866 BIT(AB8500_DIGIFCONF2_FSYNC0P) | 1867 BIT(AB8500_DIGIFCONF2_BITCLK0P); 1868 val = 0; 1869 1870 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1871 case SND_SOC_DAIFMT_I2S: /* I2S mode */ 1872 dev_dbg(dai->component->dev, "%s: IF0 Protocol: I2S\n", __func__); 1873 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1); 1874 ab8500_audio_set_bit_delay(dai, 0); 1875 break; 1876 1877 case SND_SOC_DAIFMT_DSP_A: /* L data MSB after FRM LRC */ 1878 dev_dbg(dai->component->dev, 1879 "%s: IF0 Protocol: DSP A (TDM)\n", __func__); 1880 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0); 1881 ab8500_audio_set_bit_delay(dai, 1); 1882 break; 1883 1884 case SND_SOC_DAIFMT_DSP_B: /* L data MSB during FRM LRC */ 1885 dev_dbg(dai->component->dev, 1886 "%s: IF0 Protocol: DSP B (TDM)\n", __func__); 1887 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0); 1888 ab8500_audio_set_bit_delay(dai, 0); 1889 break; 1890 1891 default: 1892 dev_err(dai->component->dev, 1893 "%s: ERROR: Unsupported format (0x%x)!\n", 1894 __func__, fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1895 return -EINVAL; 1896 } 1897 1898 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1899 case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */ 1900 dev_dbg(dai->component->dev, 1901 "%s: IF0: Normal bit clock, normal frame\n", 1902 __func__); 1903 break; 1904 case SND_SOC_DAIFMT_NB_IF: /* normal BCLK + inv FRM */ 1905 dev_dbg(dai->component->dev, 1906 "%s: IF0: Normal bit clock, inverted frame\n", 1907 __func__); 1908 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P); 1909 break; 1910 case SND_SOC_DAIFMT_IB_NF: /* invert BCLK + nor FRM */ 1911 dev_dbg(dai->component->dev, 1912 "%s: IF0: Inverted bit clock, normal frame\n", 1913 __func__); 1914 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P); 1915 break; 1916 case SND_SOC_DAIFMT_IB_IF: /* invert BCLK + FRM */ 1917 dev_dbg(dai->component->dev, 1918 "%s: IF0: Inverted bit clock, inverted frame\n", 1919 __func__); 1920 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P); 1921 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P); 1922 break; 1923 default: 1924 dev_err(dai->component->dev, 1925 "%s: ERROR: Unsupported INV mask 0x%x\n", 1926 __func__, fmt & SND_SOC_DAIFMT_INV_MASK); 1927 return -EINVAL; 1928 } 1929 1930 snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val); 1931 1932 return 0; 1933 } 1934 1935 static int ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai *dai, 1936 unsigned int tx_mask, unsigned int rx_mask, 1937 int slots, int slot_width) 1938 { 1939 struct snd_soc_component *component = dai->component; 1940 unsigned int val, mask, slot, slots_active; 1941 1942 mask = BIT(AB8500_DIGIFCONF2_IF0WL0) | 1943 BIT(AB8500_DIGIFCONF2_IF0WL1); 1944 val = 0; 1945 1946 switch (slot_width) { 1947 case 16: 1948 break; 1949 case 20: 1950 val |= BIT(AB8500_DIGIFCONF2_IF0WL0); 1951 break; 1952 case 24: 1953 val |= BIT(AB8500_DIGIFCONF2_IF0WL1); 1954 break; 1955 case 32: 1956 val |= BIT(AB8500_DIGIFCONF2_IF0WL1) | 1957 BIT(AB8500_DIGIFCONF2_IF0WL0); 1958 break; 1959 default: 1960 dev_err(dai->component->dev, "%s: Unsupported slot-width 0x%x\n", 1961 __func__, slot_width); 1962 return -EINVAL; 1963 } 1964 1965 dev_dbg(dai->component->dev, "%s: IF0 slot-width: %d bits.\n", 1966 __func__, slot_width); 1967 snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val); 1968 1969 /* Setup TDM clocking according to slot count */ 1970 dev_dbg(dai->component->dev, "%s: Slots, total: %d\n", __func__, slots); 1971 mask = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) | 1972 BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1); 1973 switch (slots) { 1974 case 2: 1975 val = AB8500_MASK_NONE; 1976 break; 1977 case 4: 1978 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0); 1979 break; 1980 case 8: 1981 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1); 1982 break; 1983 case 16: 1984 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) | 1985 BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1); 1986 break; 1987 default: 1988 dev_err(dai->component->dev, 1989 "%s: ERROR: Unsupported number of slots (%d)!\n", 1990 __func__, slots); 1991 return -EINVAL; 1992 } 1993 snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val); 1994 1995 /* Setup TDM DA according to active tx slots */ 1996 1997 if (tx_mask & ~0xff) 1998 return -EINVAL; 1999 2000 mask = AB8500_DASLOTCONFX_SLTODAX_MASK; 2001 tx_mask = tx_mask << AB8500_DA_DATA0_OFFSET; 2002 slots_active = hweight32(tx_mask); 2003 2004 dev_dbg(dai->component->dev, "%s: Slots, active, TX: %d\n", __func__, 2005 slots_active); 2006 2007 switch (slots_active) { 2008 case 0: 2009 break; 2010 case 1: 2011 slot = ffs(tx_mask); 2012 snd_soc_component_update_bits(component, AB8500_DASLOTCONF1, mask, slot); 2013 snd_soc_component_update_bits(component, AB8500_DASLOTCONF3, mask, slot); 2014 snd_soc_component_update_bits(component, AB8500_DASLOTCONF2, mask, slot); 2015 snd_soc_component_update_bits(component, AB8500_DASLOTCONF4, mask, slot); 2016 break; 2017 case 2: 2018 slot = ffs(tx_mask); 2019 snd_soc_component_update_bits(component, AB8500_DASLOTCONF1, mask, slot); 2020 snd_soc_component_update_bits(component, AB8500_DASLOTCONF3, mask, slot); 2021 slot = fls(tx_mask); 2022 snd_soc_component_update_bits(component, AB8500_DASLOTCONF2, mask, slot); 2023 snd_soc_component_update_bits(component, AB8500_DASLOTCONF4, mask, slot); 2024 break; 2025 case 8: 2026 dev_dbg(dai->component->dev, 2027 "%s: In 8-channel mode DA-from-slot mapping is set manually.", 2028 __func__); 2029 break; 2030 default: 2031 dev_err(dai->component->dev, 2032 "%s: Unsupported number of active TX-slots (%d)!\n", 2033 __func__, slots_active); 2034 return -EINVAL; 2035 } 2036 2037 /* Setup TDM AD according to active RX-slots */ 2038 2039 if (rx_mask & ~0xff) 2040 return -EINVAL; 2041 2042 rx_mask = rx_mask << AB8500_AD_DATA0_OFFSET; 2043 slots_active = hweight32(rx_mask); 2044 2045 dev_dbg(dai->component->dev, "%s: Slots, active, RX: %d\n", __func__, 2046 slots_active); 2047 2048 switch (slots_active) { 2049 case 0: 2050 break; 2051 case 1: 2052 slot = ffs(rx_mask); 2053 snd_soc_component_update_bits(component, AB8500_ADSLOTSEL(slot), 2054 AB8500_MASK_SLOT(slot), 2055 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot)); 2056 break; 2057 case 2: 2058 slot = ffs(rx_mask); 2059 snd_soc_component_update_bits(component, 2060 AB8500_ADSLOTSEL(slot), 2061 AB8500_MASK_SLOT(slot), 2062 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot)); 2063 slot = fls(rx_mask); 2064 snd_soc_component_update_bits(component, 2065 AB8500_ADSLOTSEL(slot), 2066 AB8500_MASK_SLOT(slot), 2067 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT2, slot)); 2068 break; 2069 case 8: 2070 dev_dbg(dai->component->dev, 2071 "%s: In 8-channel mode AD-to-slot mapping is set manually.", 2072 __func__); 2073 break; 2074 default: 2075 dev_err(dai->component->dev, 2076 "%s: Unsupported number of active RX-slots (%d)!\n", 2077 __func__, slots_active); 2078 return -EINVAL; 2079 } 2080 2081 return 0; 2082 } 2083 2084 static const struct snd_soc_dai_ops ab8500_codec_ops = { 2085 .set_fmt = ab8500_codec_set_dai_fmt, 2086 .set_tdm_slot = ab8500_codec_set_dai_tdm_slot, 2087 }; 2088 2089 static struct snd_soc_dai_driver ab8500_codec_dai[] = { 2090 { 2091 .name = "ab8500-codec-dai.0", 2092 .id = 0, 2093 .playback = { 2094 .stream_name = "ab8500_0p", 2095 .channels_min = 1, 2096 .channels_max = 8, 2097 .rates = AB8500_SUPPORTED_RATE, 2098 .formats = AB8500_SUPPORTED_FMT, 2099 }, 2100 .ops = &ab8500_codec_ops, 2101 .symmetric_rate = 1 2102 }, 2103 { 2104 .name = "ab8500-codec-dai.1", 2105 .id = 1, 2106 .capture = { 2107 .stream_name = "ab8500_0c", 2108 .channels_min = 1, 2109 .channels_max = 8, 2110 .rates = AB8500_SUPPORTED_RATE, 2111 .formats = AB8500_SUPPORTED_FMT, 2112 }, 2113 .ops = &ab8500_codec_ops, 2114 .symmetric_rate = 1 2115 } 2116 }; 2117 2118 static void ab8500_codec_of_probe(struct device *dev, struct device_node *np, 2119 struct ab8500_codec_platform_data *codec) 2120 { 2121 u32 value; 2122 2123 if (of_property_read_bool(np, "stericsson,amic1-type-single-ended")) 2124 codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED; 2125 else 2126 codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL; 2127 2128 if (of_property_read_bool(np, "stericsson,amic2-type-single-ended")) 2129 codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED; 2130 else 2131 codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL; 2132 2133 /* Has a non-standard Vamic been requested? */ 2134 if (of_property_read_bool(np, "stericsson,amic1a-bias-vamic2")) 2135 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2; 2136 else 2137 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1; 2138 2139 if (of_property_read_bool(np, "stericsson,amic1b-bias-vamic2")) 2140 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2; 2141 else 2142 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1; 2143 2144 if (of_property_read_bool(np, "stericsson,amic2-bias-vamic1")) 2145 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1; 2146 else 2147 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2; 2148 2149 if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) { 2150 switch (value) { 2151 case 950 : 2152 codec->ear_cmv = EAR_CMV_0_95V; 2153 break; 2154 case 1100 : 2155 codec->ear_cmv = EAR_CMV_1_10V; 2156 break; 2157 case 1270 : 2158 codec->ear_cmv = EAR_CMV_1_27V; 2159 break; 2160 case 1580 : 2161 codec->ear_cmv = EAR_CMV_1_58V; 2162 break; 2163 default : 2164 codec->ear_cmv = EAR_CMV_UNKNOWN; 2165 dev_err(dev, "Unsuitable earpiece voltage found in DT\n"); 2166 } 2167 } else { 2168 dev_warn(dev, "No earpiece voltage found in DT - using default\n"); 2169 codec->ear_cmv = EAR_CMV_0_95V; 2170 } 2171 } 2172 2173 static int ab8500_codec_probe(struct snd_soc_component *component) 2174 { 2175 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2176 struct device *dev = component->dev; 2177 struct device_node *np = dev->of_node; 2178 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(dev); 2179 struct ab8500_codec_platform_data codec_pdata; 2180 int status; 2181 2182 dev_dbg(dev, "%s: Enter.\n", __func__); 2183 2184 ab8500_codec_of_probe(dev, np, &codec_pdata); 2185 2186 status = ab8500_audio_setup_mics(component, &codec_pdata.amics); 2187 if (status < 0) { 2188 pr_err("%s: Failed to setup mics (%d)!\n", __func__, status); 2189 return status; 2190 } 2191 status = ab8500_audio_set_ear_cmv(component, codec_pdata.ear_cmv); 2192 if (status < 0) { 2193 pr_err("%s: Failed to set earpiece CM-voltage (%d)!\n", 2194 __func__, status); 2195 return status; 2196 } 2197 2198 status = ab8500_audio_init_audioblock(component); 2199 if (status < 0) { 2200 dev_err(dev, "%s: failed to init audio-block (%d)!\n", 2201 __func__, status); 2202 return status; 2203 } 2204 2205 /* Override HW-defaults */ 2206 snd_soc_component_write(component, AB8500_ANACONF5, 2207 BIT(AB8500_ANACONF5_HSAUTOEN)); 2208 snd_soc_component_write(component, AB8500_SHORTCIRCONF, 2209 BIT(AB8500_SHORTCIRCONF_HSZCDDIS)); 2210 2211 snd_soc_dapm_disable_pin(dapm, "ANC Configure Input"); 2212 2213 mutex_init(&drvdata->ctrl_lock); 2214 2215 return status; 2216 } 2217 2218 static const struct snd_soc_component_driver ab8500_component_driver = { 2219 .probe = ab8500_codec_probe, 2220 .controls = ab8500_ctrls, 2221 .num_controls = ARRAY_SIZE(ab8500_ctrls), 2222 .dapm_widgets = ab8500_dapm_widgets, 2223 .num_dapm_widgets = ARRAY_SIZE(ab8500_dapm_widgets), 2224 .dapm_routes = ab8500_dapm_routes, 2225 .num_dapm_routes = ARRAY_SIZE(ab8500_dapm_routes), 2226 .idle_bias_on = 1, 2227 .use_pmdown_time = 1, 2228 .endianness = 1, 2229 }; 2230 2231 static int ab8500_codec_driver_probe(struct platform_device *pdev) 2232 { 2233 int status; 2234 struct ab8500_codec_drvdata *drvdata; 2235 2236 dev_dbg(&pdev->dev, "%s: Enter.\n", __func__); 2237 2238 /* Create driver private-data struct */ 2239 drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_codec_drvdata), 2240 GFP_KERNEL); 2241 if (!drvdata) 2242 return -ENOMEM; 2243 drvdata->sid_status = SID_UNCONFIGURED; 2244 dev_set_drvdata(&pdev->dev, drvdata); 2245 2246 drvdata->regmap = devm_regmap_init(&pdev->dev, NULL, &pdev->dev, 2247 &ab8500_codec_regmap); 2248 if (IS_ERR(drvdata->regmap)) { 2249 status = PTR_ERR(drvdata->regmap); 2250 dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n", 2251 __func__, status); 2252 return status; 2253 } 2254 2255 dev_dbg(&pdev->dev, "%s: Register codec.\n", __func__); 2256 status = devm_snd_soc_register_component(&pdev->dev, 2257 &ab8500_component_driver, 2258 ab8500_codec_dai, 2259 ARRAY_SIZE(ab8500_codec_dai)); 2260 if (status < 0) 2261 dev_err(&pdev->dev, 2262 "%s: Error: Failed to register codec (%d).\n", 2263 __func__, status); 2264 2265 return status; 2266 } 2267 2268 static struct platform_driver ab8500_codec_platform_driver = { 2269 .driver = { 2270 .name = "ab8500-codec", 2271 }, 2272 .probe = ab8500_codec_driver_probe, 2273 }; 2274 module_platform_driver(ab8500_codec_platform_driver); 2275 2276 MODULE_DESCRIPTION("ASoC AB8500 codec driver"); 2277 MODULE_LICENSE("GPL v2"); 2278