1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5 */
6
7 #include <linux/fips.h>
8 #include <linux/ieee80211.h>
9 #include <linux/kernel.h>
10 #include <linux/skbuff.h>
11 #include "core.h"
12 #include "debug.h"
13 #include "debugfs_htt_stats.h"
14 #include "debugfs_sta.h"
15 #include "hal_desc.h"
16 #include "hw.h"
17 #include "dp_rx.h"
18 #include "hal_rx.h"
19 #include "dp_tx.h"
20 #include "peer.h"
21
22 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
23
24 static inline
ath11k_dp_rx_h_80211_hdr(struct ath11k_base * ab,struct hal_rx_desc * desc)25 u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc)
26 {
27 return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc);
28 }
29
30 static inline
ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base * ab,struct hal_rx_desc * desc)31 enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab,
32 struct hal_rx_desc *desc)
33 {
34 if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc))
35 return HAL_ENCRYPT_TYPE_OPEN;
36
37 return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc);
38 }
39
ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base * ab,struct hal_rx_desc * desc)40 static inline u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab,
41 struct hal_rx_desc *desc)
42 {
43 return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc);
44 }
45
46 static inline
ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base * ab,struct hal_rx_desc * desc)47 bool ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base *ab,
48 struct hal_rx_desc *desc)
49 {
50 return ab->hw_params.hw_ops->rx_desc_get_ldpc_support(desc);
51 }
52
53 static inline
ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base * ab,struct hal_rx_desc * desc)54 u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab,
55 struct hal_rx_desc *desc)
56 {
57 return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc);
58 }
59
60 static inline
ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)61 bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab,
62 struct hal_rx_desc *desc)
63 {
64 return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
65 }
66
ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)67 static inline bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab,
68 struct hal_rx_desc *desc)
69 {
70 return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc);
71 }
72
ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base * ab,struct sk_buff * skb)73 static inline bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab,
74 struct sk_buff *skb)
75 {
76 struct ieee80211_hdr *hdr;
77
78 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
79 return ieee80211_has_morefrags(hdr->frame_control);
80 }
81
ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base * ab,struct sk_buff * skb)82 static inline u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab,
83 struct sk_buff *skb)
84 {
85 struct ieee80211_hdr *hdr;
86
87 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
88 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
89 }
90
ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base * ab,struct hal_rx_desc * desc)91 static inline u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab,
92 struct hal_rx_desc *desc)
93 {
94 return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc);
95 }
96
ath11k_dp_rx_get_attention(struct ath11k_base * ab,struct hal_rx_desc * desc)97 static inline void *ath11k_dp_rx_get_attention(struct ath11k_base *ab,
98 struct hal_rx_desc *desc)
99 {
100 return ab->hw_params.hw_ops->rx_desc_get_attention(desc);
101 }
102
ath11k_dp_rx_h_attn_msdu_done(struct rx_attention * attn)103 static inline bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn)
104 {
105 return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
106 __le32_to_cpu(attn->info2));
107 }
108
ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention * attn)109 static inline bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn)
110 {
111 return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
112 __le32_to_cpu(attn->info1));
113 }
114
ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention * attn)115 static inline bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn)
116 {
117 return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
118 __le32_to_cpu(attn->info1));
119 }
120
ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention * attn)121 static inline bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn)
122 {
123 return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
124 __le32_to_cpu(attn->info2)) ==
125 RX_DESC_DECRYPT_STATUS_CODE_OK);
126 }
127
ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention * attn)128 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn)
129 {
130 u32 info = __le32_to_cpu(attn->info1);
131 u32 errmap = 0;
132
133 if (info & RX_ATTENTION_INFO1_FCS_ERR)
134 errmap |= DP_RX_MPDU_ERR_FCS;
135
136 if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
137 errmap |= DP_RX_MPDU_ERR_DECRYPT;
138
139 if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
140 errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
141
142 if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
143 errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
144
145 if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
146 errmap |= DP_RX_MPDU_ERR_OVERFLOW;
147
148 if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
149 errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
150
151 if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
152 errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
153
154 return errmap;
155 }
156
ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base * ab,struct hal_rx_desc * desc)157 static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab,
158 struct hal_rx_desc *desc)
159 {
160 struct rx_attention *rx_attention;
161 u32 errmap;
162
163 rx_attention = ath11k_dp_rx_get_attention(ab, desc);
164 errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
165
166 return errmap & DP_RX_MPDU_ERR_MSDU_LEN;
167 }
168
ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc)169 static inline u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab,
170 struct hal_rx_desc *desc)
171 {
172 return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc);
173 }
174
ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base * ab,struct hal_rx_desc * desc)175 static inline u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab,
176 struct hal_rx_desc *desc)
177 {
178 return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc);
179 }
180
ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base * ab,struct hal_rx_desc * desc)181 static inline u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab,
182 struct hal_rx_desc *desc)
183 {
184 return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc);
185 }
186
ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base * ab,struct hal_rx_desc * desc)187 static inline u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab,
188 struct hal_rx_desc *desc)
189 {
190 return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc);
191 }
192
ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base * ab,struct hal_rx_desc * desc)193 static inline u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab,
194 struct hal_rx_desc *desc)
195 {
196 return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc);
197 }
198
ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base * ab,struct hal_rx_desc * desc)199 static inline u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab,
200 struct hal_rx_desc *desc)
201 {
202 return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc);
203 }
204
ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base * ab,struct hal_rx_desc * desc)205 static inline u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab,
206 struct hal_rx_desc *desc)
207 {
208 return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc));
209 }
210
ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base * ab,struct hal_rx_desc * desc)211 static inline u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab,
212 struct hal_rx_desc *desc)
213 {
214 return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc);
215 }
216
ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base * ab,struct hal_rx_desc * desc)217 static inline u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab,
218 struct hal_rx_desc *desc)
219 {
220 return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc);
221 }
222
ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base * ab,struct hal_rx_desc * desc)223 static inline u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab,
224 struct hal_rx_desc *desc)
225 {
226 return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc);
227 }
228
ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)229 static inline bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab,
230 struct hal_rx_desc *desc)
231 {
232 return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc);
233 }
234
ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base * ab,struct hal_rx_desc * desc)235 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab,
236 struct hal_rx_desc *desc)
237 {
238 return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc);
239 }
240
ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base * ab,struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)241 static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab,
242 struct hal_rx_desc *fdesc,
243 struct hal_rx_desc *ldesc)
244 {
245 ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc);
246 }
247
ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention * attn)248 static inline u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn)
249 {
250 return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
251 __le32_to_cpu(attn->info1));
252 }
253
ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)254 static inline u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab,
255 struct hal_rx_desc *rx_desc)
256 {
257 u8 *rx_pkt_hdr;
258
259 rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc);
260
261 return rx_pkt_hdr;
262 }
263
ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)264 static inline bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab,
265 struct hal_rx_desc *rx_desc)
266 {
267 u32 tlv_tag;
268
269 tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc);
270
271 return tlv_tag == HAL_RX_MPDU_START;
272 }
273
ath11k_dp_rxdesc_get_ppduid(struct ath11k_base * ab,struct hal_rx_desc * rx_desc)274 static inline u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab,
275 struct hal_rx_desc *rx_desc)
276 {
277 return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc);
278 }
279
ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base * ab,struct hal_rx_desc * desc,u16 len)280 static inline void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab,
281 struct hal_rx_desc *desc,
282 u16 len)
283 {
284 ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len);
285 }
286
ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base * ab,struct hal_rx_desc * desc)287 static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab,
288 struct hal_rx_desc *desc)
289 {
290 struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc);
291
292 return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) &&
293 (!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST,
294 __le32_to_cpu(attn->info1)));
295 }
296
ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base * ab,struct hal_rx_desc * desc)297 static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab,
298 struct hal_rx_desc *desc)
299 {
300 return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc);
301 }
302
ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base * ab,struct hal_rx_desc * desc)303 static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab,
304 struct hal_rx_desc *desc)
305 {
306 return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc);
307 }
308
ath11k_dp_service_mon_ring(struct timer_list * t)309 static void ath11k_dp_service_mon_ring(struct timer_list *t)
310 {
311 struct ath11k_base *ab = timer_container_of(ab, t, mon_reap_timer);
312 int i;
313
314 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++)
315 ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
316
317 mod_timer(&ab->mon_reap_timer, jiffies +
318 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
319 }
320
ath11k_dp_purge_mon_ring(struct ath11k_base * ab)321 static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab)
322 {
323 int i, reaped = 0;
324 unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS);
325
326 do {
327 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++)
328 reaped += ath11k_dp_rx_process_mon_rings(ab, i,
329 NULL,
330 DP_MON_SERVICE_BUDGET);
331
332 /* nothing more to reap */
333 if (reaped < DP_MON_SERVICE_BUDGET)
334 return 0;
335
336 } while (time_before(jiffies, timeout));
337
338 ath11k_warn(ab, "dp mon ring purge timeout");
339
340 return -ETIMEDOUT;
341 }
342
343 /* Returns number of Rx buffers replenished */
ath11k_dp_rxbufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)344 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
345 struct dp_rxdma_ring *rx_ring,
346 int req_entries,
347 enum hal_rx_buf_return_buf_manager mgr)
348 {
349 struct hal_srng *srng;
350 u32 *desc;
351 struct sk_buff *skb;
352 int num_free;
353 int num_remain;
354 int buf_id;
355 u32 cookie;
356 dma_addr_t paddr;
357
358 req_entries = min(req_entries, rx_ring->bufs_max);
359
360 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
361
362 spin_lock_bh(&srng->lock);
363
364 ath11k_hal_srng_access_begin(ab, srng);
365
366 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
367 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
368 req_entries = num_free;
369
370 req_entries = min(num_free, req_entries);
371 num_remain = req_entries;
372
373 while (num_remain > 0) {
374 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
375 DP_RX_BUFFER_ALIGN_SIZE);
376 if (!skb)
377 break;
378
379 if (!IS_ALIGNED((unsigned long)skb->data,
380 DP_RX_BUFFER_ALIGN_SIZE)) {
381 skb_pull(skb,
382 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
383 skb->data);
384 }
385
386 paddr = dma_map_single(ab->dev, skb->data,
387 skb->len + skb_tailroom(skb),
388 DMA_FROM_DEVICE);
389 if (dma_mapping_error(ab->dev, paddr))
390 goto fail_free_skb;
391
392 spin_lock_bh(&rx_ring->idr_lock);
393 buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 1,
394 (rx_ring->bufs_max * 3) + 1, GFP_ATOMIC);
395 spin_unlock_bh(&rx_ring->idr_lock);
396 if (buf_id <= 0)
397 goto fail_dma_unmap;
398
399 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
400 if (!desc)
401 goto fail_idr_remove;
402
403 ATH11K_SKB_RXCB(skb)->paddr = paddr;
404
405 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
406 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
407
408 num_remain--;
409
410 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
411 }
412
413 ath11k_hal_srng_access_end(ab, srng);
414
415 spin_unlock_bh(&srng->lock);
416
417 return req_entries - num_remain;
418
419 fail_idr_remove:
420 spin_lock_bh(&rx_ring->idr_lock);
421 idr_remove(&rx_ring->bufs_idr, buf_id);
422 spin_unlock_bh(&rx_ring->idr_lock);
423 fail_dma_unmap:
424 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
425 DMA_FROM_DEVICE);
426 fail_free_skb:
427 dev_kfree_skb_any(skb);
428
429 ath11k_hal_srng_access_end(ab, srng);
430
431 spin_unlock_bh(&srng->lock);
432
433 return req_entries - num_remain;
434 }
435
ath11k_dp_rxdma_buf_ring_free(struct ath11k * ar,struct dp_rxdma_ring * rx_ring)436 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
437 struct dp_rxdma_ring *rx_ring)
438 {
439 struct sk_buff *skb;
440 int buf_id;
441
442 spin_lock_bh(&rx_ring->idr_lock);
443 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
444 idr_remove(&rx_ring->bufs_idr, buf_id);
445 /* TODO: Understand where internal driver does this dma_unmap
446 * of rxdma_buffer.
447 */
448 dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
449 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
450 dev_kfree_skb_any(skb);
451 }
452
453 idr_destroy(&rx_ring->bufs_idr);
454 spin_unlock_bh(&rx_ring->idr_lock);
455
456 return 0;
457 }
458
ath11k_dp_rxdma_pdev_buf_free(struct ath11k * ar)459 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
460 {
461 struct ath11k_pdev_dp *dp = &ar->dp;
462 struct ath11k_base *ab = ar->ab;
463 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
464 int i;
465
466 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
467
468 rx_ring = &dp->rxdma_mon_buf_ring;
469 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
470
471 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
472 rx_ring = &dp->rx_mon_status_refill_ring[i];
473 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
474 }
475
476 return 0;
477 }
478
ath11k_dp_rxdma_ring_buf_setup(struct ath11k * ar,struct dp_rxdma_ring * rx_ring,u32 ringtype)479 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
480 struct dp_rxdma_ring *rx_ring,
481 u32 ringtype)
482 {
483 struct ath11k_pdev_dp *dp = &ar->dp;
484 int num_entries;
485
486 num_entries = rx_ring->refill_buf_ring.size /
487 ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
488
489 rx_ring->bufs_max = num_entries;
490 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
491 ar->ab->hw_params.hal_params->rx_buf_rbm);
492 return 0;
493 }
494
ath11k_dp_rxdma_pdev_buf_setup(struct ath11k * ar)495 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
496 {
497 struct ath11k_pdev_dp *dp = &ar->dp;
498 struct ath11k_base *ab = ar->ab;
499 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
500 int i;
501
502 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
503
504 if (ar->ab->hw_params.rxdma1_enable) {
505 rx_ring = &dp->rxdma_mon_buf_ring;
506 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
507 }
508
509 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
510 rx_ring = &dp->rx_mon_status_refill_ring[i];
511 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
512 }
513
514 return 0;
515 }
516
ath11k_dp_rx_pdev_srng_free(struct ath11k * ar)517 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
518 {
519 struct ath11k_pdev_dp *dp = &ar->dp;
520 struct ath11k_base *ab = ar->ab;
521 int i;
522
523 ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
524
525 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
526 if (ab->hw_params.rx_mac_buf_ring)
527 ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
528
529 ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
530 ath11k_dp_srng_cleanup(ab,
531 &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
532 }
533
534 ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
535 }
536
ath11k_dp_pdev_reo_cleanup(struct ath11k_base * ab)537 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
538 {
539 struct ath11k_dp *dp = &ab->dp;
540 int i;
541
542 for (i = 0; i < DP_REO_DST_RING_MAX; i++)
543 ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
544 }
545
ath11k_dp_pdev_reo_setup(struct ath11k_base * ab)546 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
547 {
548 struct ath11k_dp *dp = &ab->dp;
549 int ret;
550 int i;
551
552 for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
553 ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
554 HAL_REO_DST, i, 0,
555 DP_REO_DST_RING_SIZE);
556 if (ret) {
557 ath11k_warn(ab, "failed to setup reo_dst_ring\n");
558 goto err_reo_cleanup;
559 }
560 }
561
562 return 0;
563
564 err_reo_cleanup:
565 ath11k_dp_pdev_reo_cleanup(ab);
566
567 return ret;
568 }
569
ath11k_dp_rx_pdev_srng_alloc(struct ath11k * ar)570 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
571 {
572 struct ath11k_pdev_dp *dp = &ar->dp;
573 struct ath11k_base *ab = ar->ab;
574 struct dp_srng *srng = NULL;
575 int i;
576 int ret;
577
578 ret = ath11k_dp_srng_setup(ar->ab,
579 &dp->rx_refill_buf_ring.refill_buf_ring,
580 HAL_RXDMA_BUF, 0,
581 dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
582 if (ret) {
583 ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
584 return ret;
585 }
586
587 if (ar->ab->hw_params.rx_mac_buf_ring) {
588 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
589 ret = ath11k_dp_srng_setup(ar->ab,
590 &dp->rx_mac_buf_ring[i],
591 HAL_RXDMA_BUF, 1,
592 dp->mac_id + i, 1024);
593 if (ret) {
594 ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
595 i);
596 return ret;
597 }
598 }
599 }
600
601 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
602 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
603 HAL_RXDMA_DST, 0, dp->mac_id + i,
604 DP_RXDMA_ERR_DST_RING_SIZE);
605 if (ret) {
606 ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
607 return ret;
608 }
609 }
610
611 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
612 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
613 ret = ath11k_dp_srng_setup(ar->ab,
614 srng,
615 HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
616 DP_RXDMA_MON_STATUS_RING_SIZE);
617 if (ret) {
618 ath11k_warn(ar->ab,
619 "failed to setup rx_mon_status_refill_ring %d\n", i);
620 return ret;
621 }
622 }
623
624 /* if rxdma1_enable is false, then it doesn't need
625 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
626 * and rxdma_mon_desc_ring.
627 * init reap timer for QCA6390.
628 */
629 if (!ar->ab->hw_params.rxdma1_enable) {
630 //init mon status buffer reap timer
631 timer_setup(&ar->ab->mon_reap_timer,
632 ath11k_dp_service_mon_ring, 0);
633 return 0;
634 }
635
636 ret = ath11k_dp_srng_setup(ar->ab,
637 &dp->rxdma_mon_buf_ring.refill_buf_ring,
638 HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
639 DP_RXDMA_MONITOR_BUF_RING_SIZE);
640 if (ret) {
641 ath11k_warn(ar->ab,
642 "failed to setup HAL_RXDMA_MONITOR_BUF\n");
643 return ret;
644 }
645
646 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
647 HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
648 DP_RXDMA_MONITOR_DST_RING_SIZE);
649 if (ret) {
650 ath11k_warn(ar->ab,
651 "failed to setup HAL_RXDMA_MONITOR_DST\n");
652 return ret;
653 }
654
655 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
656 HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
657 DP_RXDMA_MONITOR_DESC_RING_SIZE);
658 if (ret) {
659 ath11k_warn(ar->ab,
660 "failed to setup HAL_RXDMA_MONITOR_DESC\n");
661 return ret;
662 }
663
664 return 0;
665 }
666
ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base * ab)667 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
668 {
669 struct ath11k_dp *dp = &ab->dp;
670 struct dp_reo_cmd *cmd, *tmp;
671 struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
672 struct dp_rx_tid *rx_tid;
673
674 spin_lock_bh(&dp->reo_cmd_lock);
675 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
676 list_del(&cmd->list);
677 rx_tid = &cmd->data;
678 if (rx_tid->vaddr_unaligned) {
679 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
680 rx_tid->vaddr_unaligned,
681 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
682 rx_tid->vaddr_unaligned = NULL;
683 }
684 kfree(cmd);
685 }
686
687 list_for_each_entry_safe(cmd_cache, tmp_cache,
688 &dp->reo_cmd_cache_flush_list, list) {
689 list_del(&cmd_cache->list);
690 dp->reo_cmd_cache_flush_count--;
691 rx_tid = &cmd_cache->data;
692 if (rx_tid->vaddr_unaligned) {
693 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
694 rx_tid->vaddr_unaligned,
695 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
696 rx_tid->vaddr_unaligned = NULL;
697 }
698 kfree(cmd_cache);
699 }
700 spin_unlock_bh(&dp->reo_cmd_lock);
701 }
702
ath11k_dp_reo_cmd_free(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)703 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
704 enum hal_reo_cmd_status status)
705 {
706 struct dp_rx_tid *rx_tid = ctx;
707
708 if (status != HAL_REO_CMD_SUCCESS)
709 ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
710 rx_tid->tid, status);
711 if (rx_tid->vaddr_unaligned) {
712 dma_free_noncoherent(dp->ab->dev, rx_tid->unaligned_size,
713 rx_tid->vaddr_unaligned,
714 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
715 rx_tid->vaddr_unaligned = NULL;
716 }
717 }
718
ath11k_dp_reo_cache_flush(struct ath11k_base * ab,struct dp_rx_tid * rx_tid)719 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
720 struct dp_rx_tid *rx_tid)
721 {
722 struct ath11k_hal_reo_cmd cmd = {};
723 unsigned long tot_desc_sz, desc_sz;
724 int ret;
725
726 tot_desc_sz = rx_tid->size;
727 desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
728
729 while (tot_desc_sz > desc_sz) {
730 tot_desc_sz -= desc_sz;
731 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
732 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
733 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
734 HAL_REO_CMD_FLUSH_CACHE, &cmd,
735 NULL);
736 if (ret)
737 ath11k_warn(ab,
738 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
739 rx_tid->tid, ret);
740 }
741
742 memset(&cmd, 0, sizeof(cmd));
743 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
744 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
745 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
746 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
747 HAL_REO_CMD_FLUSH_CACHE,
748 &cmd, ath11k_dp_reo_cmd_free);
749 if (ret) {
750 ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
751 rx_tid->tid, ret);
752 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
753 rx_tid->vaddr_unaligned,
754 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
755 rx_tid->vaddr_unaligned = NULL;
756 }
757 }
758
ath11k_dp_rx_tid_del_func(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)759 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
760 enum hal_reo_cmd_status status)
761 {
762 struct ath11k_base *ab = dp->ab;
763 struct dp_rx_tid *rx_tid = ctx;
764 struct dp_reo_cache_flush_elem *elem, *tmp;
765
766 if (status == HAL_REO_CMD_DRAIN) {
767 goto free_desc;
768 } else if (status != HAL_REO_CMD_SUCCESS) {
769 /* Shouldn't happen! Cleanup in case of other failure? */
770 ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
771 rx_tid->tid, status);
772 return;
773 }
774
775 elem = kzalloc_obj(*elem, GFP_ATOMIC);
776 if (!elem)
777 goto free_desc;
778
779 elem->ts = jiffies;
780 memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
781
782 spin_lock_bh(&dp->reo_cmd_lock);
783 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
784 dp->reo_cmd_cache_flush_count++;
785
786 /* Flush and invalidate aged REO desc from HW cache */
787 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
788 list) {
789 if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
790 time_after(jiffies, elem->ts +
791 msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
792 list_del(&elem->list);
793 dp->reo_cmd_cache_flush_count--;
794 spin_unlock_bh(&dp->reo_cmd_lock);
795
796 ath11k_dp_reo_cache_flush(ab, &elem->data);
797 kfree(elem);
798 spin_lock_bh(&dp->reo_cmd_lock);
799 }
800 }
801 spin_unlock_bh(&dp->reo_cmd_lock);
802
803 return;
804 free_desc:
805 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
806 rx_tid->vaddr_unaligned,
807 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
808 rx_tid->vaddr_unaligned = NULL;
809 }
810
ath11k_peer_rx_tid_delete(struct ath11k * ar,struct ath11k_peer * peer,u8 tid)811 void ath11k_peer_rx_tid_delete(struct ath11k *ar,
812 struct ath11k_peer *peer, u8 tid)
813 {
814 struct ath11k_hal_reo_cmd cmd = {};
815 struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
816 int ret;
817
818 if (!rx_tid->active)
819 return;
820
821 rx_tid->active = false;
822
823 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
824 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
825 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
826 cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
827 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
828 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
829 ath11k_dp_rx_tid_del_func);
830 if (ret) {
831 if (ret != -ESHUTDOWN)
832 ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
833 tid, ret);
834 dma_free_noncoherent(ar->ab->dev, rx_tid->unaligned_size,
835 rx_tid->vaddr_unaligned,
836 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
837 rx_tid->vaddr_unaligned = NULL;
838 }
839
840 rx_tid->paddr = 0;
841 rx_tid->paddr_unaligned = 0;
842 rx_tid->size = 0;
843 rx_tid->unaligned_size = 0;
844 }
845
ath11k_dp_rx_link_desc_return(struct ath11k_base * ab,u32 * link_desc,enum hal_wbm_rel_bm_act action)846 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
847 u32 *link_desc,
848 enum hal_wbm_rel_bm_act action)
849 {
850 struct ath11k_dp *dp = &ab->dp;
851 struct hal_srng *srng;
852 u32 *desc;
853 int ret = 0;
854
855 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
856
857 spin_lock_bh(&srng->lock);
858
859 ath11k_hal_srng_access_begin(ab, srng);
860
861 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
862 if (!desc) {
863 ret = -ENOBUFS;
864 goto exit;
865 }
866
867 ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
868 action);
869
870 exit:
871 ath11k_hal_srng_access_end(ab, srng);
872
873 spin_unlock_bh(&srng->lock);
874
875 return ret;
876 }
877
ath11k_dp_rx_frags_cleanup(struct dp_rx_tid * rx_tid,bool rel_link_desc)878 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
879 {
880 struct ath11k_base *ab = rx_tid->ab;
881
882 lockdep_assert_held(&ab->base_lock);
883
884 if (rx_tid->dst_ring_desc) {
885 if (rel_link_desc)
886 ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
887 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
888 kfree(rx_tid->dst_ring_desc);
889 rx_tid->dst_ring_desc = NULL;
890 }
891
892 rx_tid->cur_sn = 0;
893 rx_tid->last_frag_no = 0;
894 rx_tid->rx_frag_bitmap = 0;
895 __skb_queue_purge(&rx_tid->rx_frags);
896 }
897
ath11k_peer_frags_flush(struct ath11k * ar,struct ath11k_peer * peer)898 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
899 {
900 struct dp_rx_tid *rx_tid;
901 int i;
902
903 lockdep_assert_held(&ar->ab->base_lock);
904
905 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
906 rx_tid = &peer->rx_tid[i];
907
908 spin_unlock_bh(&ar->ab->base_lock);
909 timer_delete_sync(&rx_tid->frag_timer);
910 spin_lock_bh(&ar->ab->base_lock);
911
912 ath11k_dp_rx_frags_cleanup(rx_tid, true);
913 }
914 }
915
ath11k_peer_rx_tid_cleanup(struct ath11k * ar,struct ath11k_peer * peer)916 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
917 {
918 struct dp_rx_tid *rx_tid;
919 int i;
920
921 lockdep_assert_held(&ar->ab->base_lock);
922
923 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
924 rx_tid = &peer->rx_tid[i];
925
926 ath11k_peer_rx_tid_delete(ar, peer, i);
927 ath11k_dp_rx_frags_cleanup(rx_tid, true);
928
929 spin_unlock_bh(&ar->ab->base_lock);
930 timer_delete_sync(&rx_tid->frag_timer);
931 spin_lock_bh(&ar->ab->base_lock);
932 }
933 }
934
ath11k_peer_rx_tid_reo_update(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)935 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
936 struct ath11k_peer *peer,
937 struct dp_rx_tid *rx_tid,
938 u32 ba_win_sz, u16 ssn,
939 bool update_ssn)
940 {
941 struct ath11k_hal_reo_cmd cmd = {};
942 int ret;
943
944 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
945 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
946 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
947 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
948 cmd.ba_window_size = ba_win_sz;
949
950 if (update_ssn) {
951 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
952 cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
953 }
954
955 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
956 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
957 NULL);
958 if (ret) {
959 ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
960 rx_tid->tid, ret);
961 return ret;
962 }
963
964 rx_tid->ba_win_sz = ba_win_sz;
965
966 return 0;
967 }
968
ath11k_dp_rx_tid_mem_free(struct ath11k_base * ab,const u8 * peer_mac,int vdev_id,u8 tid)969 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
970 const u8 *peer_mac, int vdev_id, u8 tid)
971 {
972 struct ath11k_peer *peer;
973 struct dp_rx_tid *rx_tid;
974
975 spin_lock_bh(&ab->base_lock);
976
977 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
978 if (!peer) {
979 ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
980 goto unlock_exit;
981 }
982
983 rx_tid = &peer->rx_tid[tid];
984 if (!rx_tid->active)
985 goto unlock_exit;
986
987 dma_free_noncoherent(ab->dev, rx_tid->unaligned_size, rx_tid->vaddr_unaligned,
988 rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
989 rx_tid->vaddr_unaligned = NULL;
990
991 rx_tid->active = false;
992
993 unlock_exit:
994 spin_unlock_bh(&ab->base_lock);
995 }
996
ath11k_peer_rx_tid_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)997 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
998 u8 tid, u32 ba_win_sz, u16 ssn,
999 enum hal_pn_type pn_type)
1000 {
1001 struct ath11k_base *ab = ar->ab;
1002 struct ath11k_peer *peer;
1003 struct dp_rx_tid *rx_tid;
1004 u32 hw_desc_sz, *vaddr;
1005 void *vaddr_unaligned;
1006 dma_addr_t paddr;
1007 int ret;
1008
1009 spin_lock_bh(&ab->base_lock);
1010
1011 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
1012 if (!peer) {
1013 ath11k_warn(ab, "failed to find the peer %pM to set up rx tid\n",
1014 peer_mac);
1015 spin_unlock_bh(&ab->base_lock);
1016 return -ENOENT;
1017 }
1018
1019 rx_tid = &peer->rx_tid[tid];
1020 /* Update the tid queue if it is already setup */
1021 if (rx_tid->active) {
1022 paddr = rx_tid->paddr;
1023 ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
1024 ba_win_sz, ssn, true);
1025 spin_unlock_bh(&ab->base_lock);
1026 if (ret) {
1027 ath11k_warn(ab, "failed to update reo for peer %pM rx tid %d\n: %d",
1028 peer_mac, tid, ret);
1029 return ret;
1030 }
1031
1032 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1033 peer_mac, paddr,
1034 tid, 1, ba_win_sz);
1035 if (ret)
1036 ath11k_warn(ab, "failed to send wmi rx reorder queue for peer %pM tid %d: %d\n",
1037 peer_mac, tid, ret);
1038 return ret;
1039 }
1040
1041 rx_tid->tid = tid;
1042
1043 rx_tid->ba_win_sz = ba_win_sz;
1044
1045 /* TODO: Optimize the memory allocation for qos tid based on
1046 * the actual BA window size in REO tid update path.
1047 */
1048 if (tid == HAL_DESC_REO_NON_QOS_TID)
1049 hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
1050 else
1051 hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
1052
1053 rx_tid->unaligned_size = hw_desc_sz + HAL_LINK_DESC_ALIGN - 1;
1054 vaddr_unaligned = dma_alloc_noncoherent(ab->dev, rx_tid->unaligned_size, &paddr,
1055 DMA_BIDIRECTIONAL, GFP_ATOMIC);
1056 if (!vaddr_unaligned) {
1057 spin_unlock_bh(&ab->base_lock);
1058 return -ENOMEM;
1059 }
1060
1061 rx_tid->vaddr_unaligned = vaddr_unaligned;
1062 vaddr = PTR_ALIGN(vaddr_unaligned, HAL_LINK_DESC_ALIGN);
1063 rx_tid->paddr_unaligned = paddr;
1064 rx_tid->paddr = rx_tid->paddr_unaligned + ((unsigned long)vaddr -
1065 (unsigned long)rx_tid->vaddr_unaligned);
1066 ath11k_hal_reo_qdesc_setup(vaddr, tid, ba_win_sz, ssn, pn_type);
1067 rx_tid->size = hw_desc_sz;
1068 rx_tid->active = true;
1069
1070 /* After dma_alloc_noncoherent, vaddr is being modified for reo qdesc setup.
1071 * Since these changes are not reflected in the device, driver now needs to
1072 * explicitly call dma_sync_single_for_device.
1073 */
1074 dma_sync_single_for_device(ab->dev, rx_tid->paddr,
1075 rx_tid->size,
1076 DMA_TO_DEVICE);
1077 spin_unlock_bh(&ab->base_lock);
1078
1079 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, rx_tid->paddr,
1080 tid, 1, ba_win_sz);
1081 if (ret) {
1082 ath11k_warn(ar->ab, "failed to setup rx reorder queue for peer %pM tid %d: %d\n",
1083 peer_mac, tid, ret);
1084 ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
1085 }
1086
1087 return ret;
1088 }
1089
ath11k_dp_rx_ampdu_start(struct ath11k * ar,struct ieee80211_ampdu_params * params)1090 int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
1091 struct ieee80211_ampdu_params *params)
1092 {
1093 struct ath11k_base *ab = ar->ab;
1094 struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta);
1095 int vdev_id = arsta->arvif->vdev_id;
1096 int ret;
1097
1098 ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
1099 params->tid, params->buf_size,
1100 params->ssn, arsta->pn_type);
1101 if (ret)
1102 ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
1103
1104 return ret;
1105 }
1106
ath11k_dp_rx_ampdu_stop(struct ath11k * ar,struct ieee80211_ampdu_params * params)1107 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
1108 struct ieee80211_ampdu_params *params)
1109 {
1110 struct ath11k_base *ab = ar->ab;
1111 struct ath11k_peer *peer;
1112 struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta);
1113 struct dp_rx_tid *rx_tid;
1114 int vdev_id = arsta->arvif->vdev_id;
1115 int ret;
1116
1117 spin_lock_bh(&ab->base_lock);
1118
1119 peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
1120 if (!peer) {
1121 ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1122 spin_unlock_bh(&ab->base_lock);
1123 return -ENOENT;
1124 }
1125
1126 rx_tid = &peer->rx_tid[params->tid];
1127
1128 if (!rx_tid->active) {
1129 spin_unlock_bh(&ab->base_lock);
1130 return 0;
1131 }
1132
1133 ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid, 1, 0, false);
1134 spin_unlock_bh(&ab->base_lock);
1135 if (ret) {
1136 ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1137 params->tid, ret);
1138 return ret;
1139 }
1140
1141 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1142 params->sta->addr,
1143 rx_tid->paddr,
1144 params->tid, 1, 1);
1145 if (ret)
1146 ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
1147 ret);
1148
1149 return ret;
1150 }
1151
ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1152 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
1153 const u8 *peer_addr,
1154 enum set_key_cmd key_cmd,
1155 struct ieee80211_key_conf *key)
1156 {
1157 struct ath11k *ar = arvif->ar;
1158 struct ath11k_base *ab = ar->ab;
1159 struct ath11k_hal_reo_cmd cmd = {};
1160 struct ath11k_peer *peer;
1161 struct dp_rx_tid *rx_tid;
1162 u8 tid;
1163 int ret = 0;
1164
1165 /* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1166 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1167 * for now.
1168 */
1169 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1170 return 0;
1171
1172 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
1173 cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
1174 HAL_REO_CMD_UPD0_PN_SIZE |
1175 HAL_REO_CMD_UPD0_PN_VALID |
1176 HAL_REO_CMD_UPD0_PN_CHECK |
1177 HAL_REO_CMD_UPD0_SVLD;
1178
1179 switch (key->cipher) {
1180 case WLAN_CIPHER_SUITE_TKIP:
1181 case WLAN_CIPHER_SUITE_CCMP:
1182 case WLAN_CIPHER_SUITE_CCMP_256:
1183 case WLAN_CIPHER_SUITE_GCMP:
1184 case WLAN_CIPHER_SUITE_GCMP_256:
1185 if (key_cmd == SET_KEY) {
1186 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1187 cmd.pn_size = 48;
1188 }
1189 break;
1190 default:
1191 break;
1192 }
1193
1194 spin_lock_bh(&ab->base_lock);
1195
1196 peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
1197 if (!peer) {
1198 ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
1199 spin_unlock_bh(&ab->base_lock);
1200 return -ENOENT;
1201 }
1202
1203 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1204 rx_tid = &peer->rx_tid[tid];
1205 if (!rx_tid->active)
1206 continue;
1207 cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1208 cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1209 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
1210 HAL_REO_CMD_UPDATE_RX_QUEUE,
1211 &cmd, NULL);
1212 if (ret) {
1213 ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
1214 tid, ret);
1215 break;
1216 }
1217 }
1218
1219 spin_unlock_bh(&ab->base_lock);
1220
1221 return ret;
1222 }
1223
ath11k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1224 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1225 u16 peer_id)
1226 {
1227 int i;
1228
1229 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1230 if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1231 if (peer_id == ppdu_stats->user_stats[i].peer_id)
1232 return i;
1233 } else {
1234 return i;
1235 }
1236 }
1237
1238 return -EINVAL;
1239 }
1240
ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1241 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
1242 u16 tag, u16 len, const void *ptr,
1243 void *data)
1244 {
1245 struct htt_ppdu_stats_info *ppdu_info;
1246 struct htt_ppdu_user_stats *user_stats;
1247 int cur_user;
1248 u16 peer_id;
1249
1250 ppdu_info = data;
1251
1252 switch (tag) {
1253 case HTT_PPDU_STATS_TAG_COMMON:
1254 if (len < sizeof(struct htt_ppdu_stats_common)) {
1255 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1256 len, tag);
1257 return -EINVAL;
1258 }
1259 memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
1260 sizeof(struct htt_ppdu_stats_common));
1261 break;
1262 case HTT_PPDU_STATS_TAG_USR_RATE:
1263 if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1264 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1265 len, tag);
1266 return -EINVAL;
1267 }
1268
1269 peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1270 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1271 peer_id);
1272 if (cur_user < 0)
1273 return -EINVAL;
1274 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1275 user_stats->peer_id = peer_id;
1276 user_stats->is_valid_peer_id = true;
1277 memcpy((void *)&user_stats->rate, ptr,
1278 sizeof(struct htt_ppdu_stats_user_rate));
1279 user_stats->tlv_flags |= BIT(tag);
1280 break;
1281 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1282 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1283 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1284 len, tag);
1285 return -EINVAL;
1286 }
1287
1288 peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1289 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1290 peer_id);
1291 if (cur_user < 0)
1292 return -EINVAL;
1293 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1294 user_stats->peer_id = peer_id;
1295 user_stats->is_valid_peer_id = true;
1296 memcpy((void *)&user_stats->cmpltn_cmn, ptr,
1297 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1298 user_stats->tlv_flags |= BIT(tag);
1299 break;
1300 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1301 if (len <
1302 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1303 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1304 len, tag);
1305 return -EINVAL;
1306 }
1307
1308 peer_id =
1309 ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1310 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1311 peer_id);
1312 if (cur_user < 0)
1313 return -EINVAL;
1314 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1315 user_stats->peer_id = peer_id;
1316 user_stats->is_valid_peer_id = true;
1317 memcpy((void *)&user_stats->ack_ba, ptr,
1318 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1319 user_stats->tlv_flags |= BIT(tag);
1320 break;
1321 }
1322 return 0;
1323 }
1324
ath11k_dp_htt_tlv_iter(struct ath11k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath11k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1325 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
1326 int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
1327 const void *ptr, void *data),
1328 void *data)
1329 {
1330 const struct htt_tlv *tlv;
1331 const void *begin = ptr;
1332 u16 tlv_tag, tlv_len;
1333 int ret = -EINVAL;
1334
1335 while (len > 0) {
1336 if (len < sizeof(*tlv)) {
1337 ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1338 ptr - begin, len, sizeof(*tlv));
1339 return -EINVAL;
1340 }
1341 tlv = (struct htt_tlv *)ptr;
1342 tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
1343 tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
1344 ptr += sizeof(*tlv);
1345 len -= sizeof(*tlv);
1346
1347 if (tlv_len > len) {
1348 ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1349 tlv_tag, ptr - begin, len, tlv_len);
1350 return -EINVAL;
1351 }
1352 ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1353 if (ret == -ENOMEM)
1354 return ret;
1355
1356 ptr += tlv_len;
1357 len -= tlv_len;
1358 }
1359 return 0;
1360 }
1361
1362 static void
ath11k_update_per_peer_tx_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1363 ath11k_update_per_peer_tx_stats(struct ath11k *ar,
1364 struct htt_ppdu_stats *ppdu_stats, u8 user)
1365 {
1366 struct ath11k_base *ab = ar->ab;
1367 struct ath11k_peer *peer;
1368 struct ieee80211_sta *sta;
1369 struct ath11k_sta *arsta;
1370 struct htt_ppdu_stats_user_rate *user_rate;
1371 struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1372 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1373 struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1374 int ret;
1375 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1376 u32 succ_bytes = 0;
1377 u16 rate = 0, succ_pkts = 0;
1378 u32 tx_duration = 0;
1379 u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1380 bool is_ampdu = false;
1381
1382 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1383 return;
1384
1385 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1386 is_ampdu =
1387 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1388
1389 if (usr_stats->tlv_flags &
1390 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1391 succ_bytes = usr_stats->ack_ba.success_bytes;
1392 succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
1393 usr_stats->ack_ba.info);
1394 tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
1395 usr_stats->ack_ba.info);
1396 }
1397
1398 if (common->fes_duration_us)
1399 tx_duration = common->fes_duration_us;
1400
1401 user_rate = &usr_stats->rate;
1402 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1403 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1404 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1405 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1406 sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1407 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1408
1409 /* Note: If host configured fixed rates and in some other special
1410 * cases, the broadcast/management frames are sent in different rates.
1411 * Firmware rate's control to be skipped for this?
1412 */
1413
1414 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
1415 ath11k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
1416 return;
1417 }
1418
1419 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
1420 ath11k_warn(ab, "Invalid VHT mcs %d peer stats", mcs);
1421 return;
1422 }
1423
1424 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
1425 ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1426 mcs, nss);
1427 return;
1428 }
1429
1430 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1431 ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
1432 flags,
1433 &rate_idx,
1434 &rate);
1435 if (ret < 0)
1436 return;
1437 }
1438
1439 rcu_read_lock();
1440 spin_lock_bh(&ab->base_lock);
1441 peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
1442
1443 if (!peer || !peer->sta) {
1444 spin_unlock_bh(&ab->base_lock);
1445 rcu_read_unlock();
1446 return;
1447 }
1448
1449 sta = peer->sta;
1450 arsta = ath11k_sta_to_arsta(sta);
1451
1452 memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1453
1454 switch (flags) {
1455 case WMI_RATE_PREAMBLE_OFDM:
1456 arsta->txrate.legacy = rate;
1457 break;
1458 case WMI_RATE_PREAMBLE_CCK:
1459 arsta->txrate.legacy = rate;
1460 break;
1461 case WMI_RATE_PREAMBLE_HT:
1462 arsta->txrate.mcs = mcs + 8 * (nss - 1);
1463 arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1464 if (sgi)
1465 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1466 break;
1467 case WMI_RATE_PREAMBLE_VHT:
1468 arsta->txrate.mcs = mcs;
1469 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1470 if (sgi)
1471 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1472 break;
1473 case WMI_RATE_PREAMBLE_HE:
1474 arsta->txrate.mcs = mcs;
1475 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1476 arsta->txrate.he_dcm = dcm;
1477 arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
1478 arsta->txrate.he_ru_alloc = ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc
1479 ((user_rate->ru_end -
1480 user_rate->ru_start) + 1);
1481 break;
1482 }
1483
1484 arsta->txrate.nss = nss;
1485
1486 arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
1487 arsta->tx_duration += tx_duration;
1488 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1489
1490 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1491 * So skip peer stats update for mgmt packets.
1492 */
1493 if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1494 memset(peer_stats, 0, sizeof(*peer_stats));
1495 peer_stats->succ_pkts = succ_pkts;
1496 peer_stats->succ_bytes = succ_bytes;
1497 peer_stats->is_ampdu = is_ampdu;
1498 peer_stats->duration = tx_duration;
1499 peer_stats->ba_fails =
1500 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1501 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1502
1503 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
1504 ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
1505 }
1506
1507 spin_unlock_bh(&ab->base_lock);
1508 rcu_read_unlock();
1509 }
1510
ath11k_htt_update_ppdu_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats)1511 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
1512 struct htt_ppdu_stats *ppdu_stats)
1513 {
1514 u8 user;
1515
1516 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1517 ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1518 }
1519
1520 static
ath11k_dp_htt_get_ppdu_desc(struct ath11k * ar,u32 ppdu_id)1521 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
1522 u32 ppdu_id)
1523 {
1524 struct htt_ppdu_stats_info *ppdu_info;
1525
1526 lockdep_assert_held(&ar->data_lock);
1527
1528 if (!list_empty(&ar->ppdu_stats_info)) {
1529 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1530 if (ppdu_info->ppdu_id == ppdu_id)
1531 return ppdu_info;
1532 }
1533
1534 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1535 ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1536 typeof(*ppdu_info), list);
1537 list_del(&ppdu_info->list);
1538 ar->ppdu_stat_list_depth--;
1539 ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1540 kfree(ppdu_info);
1541 }
1542 }
1543
1544 ppdu_info = kzalloc_obj(*ppdu_info, GFP_ATOMIC);
1545 if (!ppdu_info)
1546 return NULL;
1547
1548 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1549 ar->ppdu_stat_list_depth++;
1550
1551 return ppdu_info;
1552 }
1553
ath11k_htt_pull_ppdu_stats(struct ath11k_base * ab,struct sk_buff * skb)1554 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
1555 struct sk_buff *skb)
1556 {
1557 struct ath11k_htt_ppdu_stats_msg *msg;
1558 struct htt_ppdu_stats_info *ppdu_info;
1559 struct ath11k *ar;
1560 int ret;
1561 u8 pdev_id;
1562 u32 ppdu_id, len;
1563
1564 msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
1565 len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
1566 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
1567 ppdu_id = msg->ppdu_id;
1568
1569 rcu_read_lock();
1570 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1571 if (!ar) {
1572 ret = -EINVAL;
1573 goto out;
1574 }
1575
1576 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
1577 trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
1578
1579 spin_lock_bh(&ar->data_lock);
1580 ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1581 if (!ppdu_info) {
1582 ret = -EINVAL;
1583 goto out_unlock_data;
1584 }
1585
1586 ppdu_info->ppdu_id = ppdu_id;
1587 ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
1588 ath11k_htt_tlv_ppdu_stats_parse,
1589 (void *)ppdu_info);
1590 if (ret) {
1591 ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
1592 goto out_unlock_data;
1593 }
1594
1595 out_unlock_data:
1596 spin_unlock_bh(&ar->data_lock);
1597
1598 out:
1599 rcu_read_unlock();
1600
1601 return ret;
1602 }
1603
ath11k_htt_pktlog(struct ath11k_base * ab,struct sk_buff * skb)1604 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
1605 {
1606 struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
1607 struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
1608 struct ath11k *ar;
1609 u8 pdev_id;
1610
1611 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
1612
1613 rcu_read_lock();
1614
1615 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1616 if (!ar) {
1617 ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
1618 goto out;
1619 }
1620
1621 trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
1622 ar->ab->pktlog_defs_checksum);
1623
1624 out:
1625 rcu_read_unlock();
1626 }
1627
ath11k_htt_backpressure_event_handler(struct ath11k_base * ab,struct sk_buff * skb)1628 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
1629 struct sk_buff *skb)
1630 {
1631 u32 *data = (u32 *)skb->data;
1632 u8 pdev_id, ring_type, ring_id, pdev_idx;
1633 u16 hp, tp;
1634 u32 backpressure_time;
1635 struct ath11k_bp_stats *bp_stats;
1636
1637 pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
1638 ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
1639 ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
1640 ++data;
1641
1642 hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
1643 tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
1644 ++data;
1645
1646 backpressure_time = *data;
1647
1648 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
1649 pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
1650
1651 if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
1652 if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
1653 return;
1654
1655 bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
1656 } else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
1657 pdev_idx = DP_HW2SW_MACID(pdev_id);
1658
1659 if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
1660 return;
1661
1662 bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
1663 } else {
1664 ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
1665 ring_type);
1666 return;
1667 }
1668
1669 spin_lock_bh(&ab->base_lock);
1670 bp_stats->hp = hp;
1671 bp_stats->tp = tp;
1672 bp_stats->count++;
1673 bp_stats->jiffies = jiffies;
1674 spin_unlock_bh(&ab->base_lock);
1675 }
1676
ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base * ab,struct sk_buff * skb)1677 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
1678 struct sk_buff *skb)
1679 {
1680 struct ath11k_dp *dp = &ab->dp;
1681 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1682 enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
1683 u16 peer_id;
1684 u8 vdev_id;
1685 u8 mac_addr[ETH_ALEN];
1686 u16 peer_mac_h16;
1687 u16 ast_hash;
1688 u16 hw_peer_id;
1689
1690 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1691
1692 switch (type) {
1693 case HTT_T2H_MSG_TYPE_VERSION_CONF:
1694 dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
1695 resp->version_msg.version);
1696 dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
1697 resp->version_msg.version);
1698 complete(&dp->htt_tgt_version_received);
1699 break;
1700 case HTT_T2H_MSG_TYPE_PEER_MAP:
1701 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1702 resp->peer_map_ev.info);
1703 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1704 resp->peer_map_ev.info);
1705 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1706 resp->peer_map_ev.info1);
1707 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1708 peer_mac_h16, mac_addr);
1709 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1710 break;
1711 case HTT_T2H_MSG_TYPE_PEER_MAP2:
1712 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1713 resp->peer_map_ev.info);
1714 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1715 resp->peer_map_ev.info);
1716 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1717 resp->peer_map_ev.info1);
1718 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1719 peer_mac_h16, mac_addr);
1720 ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
1721 resp->peer_map_ev.info2);
1722 hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID,
1723 resp->peer_map_ev.info1);
1724 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1725 hw_peer_id);
1726 break;
1727 case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1728 case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1729 peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
1730 resp->peer_unmap_ev.info);
1731 ath11k_peer_unmap_event(ab, peer_id);
1732 break;
1733 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1734 ath11k_htt_pull_ppdu_stats(ab, skb);
1735 break;
1736 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1737 ath11k_debugfs_htt_ext_stats_handler(ab, skb);
1738 break;
1739 case HTT_T2H_MSG_TYPE_PKTLOG:
1740 ath11k_htt_pktlog(ab, skb);
1741 break;
1742 case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
1743 ath11k_htt_backpressure_event_handler(ab, skb);
1744 break;
1745 default:
1746 ath11k_warn(ab, "htt event %d not handled\n", type);
1747 break;
1748 }
1749
1750 dev_kfree_skb_any(skb);
1751 }
1752
ath11k_dp_rx_msdu_coalesce(struct ath11k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1753 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
1754 struct sk_buff_head *msdu_list,
1755 struct sk_buff *first, struct sk_buff *last,
1756 u8 l3pad_bytes, int msdu_len)
1757 {
1758 struct ath11k_base *ab = ar->ab;
1759 struct sk_buff *skb;
1760 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1761 int buf_first_hdr_len, buf_first_len;
1762 struct hal_rx_desc *ldesc;
1763 int space_extra, rem_len, buf_len;
1764 bool is_continuation;
1765 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
1766
1767 /* As the msdu is spread across multiple rx buffers,
1768 * find the offset to the start of msdu for computing
1769 * the length of the msdu in the first buffer.
1770 */
1771 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1772 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1773
1774 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1775 skb_put(first, buf_first_hdr_len + msdu_len);
1776 skb_pull(first, buf_first_hdr_len);
1777 return 0;
1778 }
1779
1780 ldesc = (struct hal_rx_desc *)last->data;
1781 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc);
1782 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc);
1783
1784 /* MSDU spans over multiple buffers because the length of the MSDU
1785 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1786 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1787 */
1788 skb_put(first, DP_RX_BUFFER_SIZE);
1789 skb_pull(first, buf_first_hdr_len);
1790
1791 /* When an MSDU spread over multiple buffers attention, MSDU_END and
1792 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
1793 */
1794 ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1795
1796 space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1797 if (space_extra > 0 &&
1798 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1799 /* Free up all buffers of the MSDU */
1800 while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1801 rxcb = ATH11K_SKB_RXCB(skb);
1802 if (!rxcb->is_continuation) {
1803 dev_kfree_skb_any(skb);
1804 break;
1805 }
1806 dev_kfree_skb_any(skb);
1807 }
1808 return -ENOMEM;
1809 }
1810
1811 rem_len = msdu_len - buf_first_len;
1812 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1813 rxcb = ATH11K_SKB_RXCB(skb);
1814 is_continuation = rxcb->is_continuation;
1815 if (is_continuation)
1816 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1817 else
1818 buf_len = rem_len;
1819
1820 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1821 WARN_ON_ONCE(1);
1822 dev_kfree_skb_any(skb);
1823 return -EINVAL;
1824 }
1825
1826 skb_put(skb, buf_len + hal_rx_desc_sz);
1827 skb_pull(skb, hal_rx_desc_sz);
1828 skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1829 buf_len);
1830 dev_kfree_skb_any(skb);
1831
1832 rem_len -= buf_len;
1833 if (!is_continuation)
1834 break;
1835 }
1836
1837 return 0;
1838 }
1839
ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1840 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1841 struct sk_buff *first)
1842 {
1843 struct sk_buff *skb;
1844 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1845
1846 if (!rxcb->is_continuation)
1847 return first;
1848
1849 skb_queue_walk(msdu_list, skb) {
1850 rxcb = ATH11K_SKB_RXCB(skb);
1851 if (!rxcb->is_continuation)
1852 return skb;
1853 }
1854
1855 return NULL;
1856 }
1857
ath11k_dp_rx_h_csum_offload(struct ath11k * ar,struct sk_buff * msdu)1858 static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu)
1859 {
1860 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1861 struct rx_attention *rx_attention;
1862 bool ip_csum_fail, l4_csum_fail;
1863
1864 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc);
1865 ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention);
1866 l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention);
1867
1868 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1869 CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1870 }
1871
ath11k_dp_rx_crypto_mic_len(struct ath11k * ar,enum hal_encrypt_type enctype)1872 int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar, enum hal_encrypt_type enctype)
1873 {
1874 switch (enctype) {
1875 case HAL_ENCRYPT_TYPE_OPEN:
1876 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1877 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1878 return 0;
1879 case HAL_ENCRYPT_TYPE_CCMP_128:
1880 return IEEE80211_CCMP_MIC_LEN;
1881 case HAL_ENCRYPT_TYPE_CCMP_256:
1882 return IEEE80211_CCMP_256_MIC_LEN;
1883 case HAL_ENCRYPT_TYPE_GCMP_128:
1884 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1885 return IEEE80211_GCMP_MIC_LEN;
1886 case HAL_ENCRYPT_TYPE_WEP_40:
1887 case HAL_ENCRYPT_TYPE_WEP_104:
1888 case HAL_ENCRYPT_TYPE_WEP_128:
1889 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1890 case HAL_ENCRYPT_TYPE_WAPI:
1891 break;
1892 }
1893
1894 ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1895 return 0;
1896 }
1897
ath11k_dp_rx_crypto_param_len(struct ath11k * ar,enum hal_encrypt_type enctype)1898 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
1899 enum hal_encrypt_type enctype)
1900 {
1901 switch (enctype) {
1902 case HAL_ENCRYPT_TYPE_OPEN:
1903 return 0;
1904 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1905 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1906 return IEEE80211_TKIP_IV_LEN;
1907 case HAL_ENCRYPT_TYPE_CCMP_128:
1908 return IEEE80211_CCMP_HDR_LEN;
1909 case HAL_ENCRYPT_TYPE_CCMP_256:
1910 return IEEE80211_CCMP_256_HDR_LEN;
1911 case HAL_ENCRYPT_TYPE_GCMP_128:
1912 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1913 return IEEE80211_GCMP_HDR_LEN;
1914 case HAL_ENCRYPT_TYPE_WEP_40:
1915 case HAL_ENCRYPT_TYPE_WEP_104:
1916 case HAL_ENCRYPT_TYPE_WEP_128:
1917 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1918 case HAL_ENCRYPT_TYPE_WAPI:
1919 break;
1920 }
1921
1922 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1923 return 0;
1924 }
1925
ath11k_dp_rx_crypto_icv_len(struct ath11k * ar,enum hal_encrypt_type enctype)1926 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
1927 enum hal_encrypt_type enctype)
1928 {
1929 switch (enctype) {
1930 case HAL_ENCRYPT_TYPE_OPEN:
1931 case HAL_ENCRYPT_TYPE_CCMP_128:
1932 case HAL_ENCRYPT_TYPE_CCMP_256:
1933 case HAL_ENCRYPT_TYPE_GCMP_128:
1934 case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1935 return 0;
1936 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1937 case HAL_ENCRYPT_TYPE_TKIP_MIC:
1938 return IEEE80211_TKIP_ICV_LEN;
1939 case HAL_ENCRYPT_TYPE_WEP_40:
1940 case HAL_ENCRYPT_TYPE_WEP_104:
1941 case HAL_ENCRYPT_TYPE_WEP_128:
1942 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1943 case HAL_ENCRYPT_TYPE_WAPI:
1944 break;
1945 }
1946
1947 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1948 return 0;
1949 }
1950
ath11k_dp_rx_h_undecap_nwifi(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)1951 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
1952 struct sk_buff *msdu,
1953 u8 *first_hdr,
1954 enum hal_encrypt_type enctype,
1955 struct ieee80211_rx_status *status)
1956 {
1957 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1958 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1959 struct ieee80211_hdr *hdr;
1960 size_t hdr_len;
1961 u8 da[ETH_ALEN];
1962 u8 sa[ETH_ALEN];
1963 u16 qos_ctl = 0;
1964 u8 *qos;
1965
1966 /* copy SA & DA and pull decapped header */
1967 hdr = (struct ieee80211_hdr *)msdu->data;
1968 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1969 ether_addr_copy(da, ieee80211_get_DA(hdr));
1970 ether_addr_copy(sa, ieee80211_get_SA(hdr));
1971 skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
1972
1973 if (rxcb->is_first_msdu) {
1974 /* original 802.11 header is valid for the first msdu
1975 * hence we can reuse the same header
1976 */
1977 hdr = (struct ieee80211_hdr *)first_hdr;
1978 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1979
1980 /* Each A-MSDU subframe will be reported as a separate MSDU,
1981 * so strip the A-MSDU bit from QoS Ctl.
1982 */
1983 if (ieee80211_is_data_qos(hdr->frame_control)) {
1984 qos = ieee80211_get_qos_ctl(hdr);
1985 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
1986 }
1987 } else {
1988 /* Rebuild qos header if this is a middle/last msdu */
1989 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
1990
1991 /* Reset the order bit as the HT_Control header is stripped */
1992 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
1993
1994 qos_ctl = rxcb->tid;
1995
1996 if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc))
1997 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
1998
1999 /* TODO Add other QoS ctl fields when required */
2000
2001 /* copy decap header before overwriting for reuse below */
2002 memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
2003 }
2004
2005 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2006 memcpy(skb_push(msdu,
2007 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2008 (void *)hdr + hdr_len,
2009 ath11k_dp_rx_crypto_param_len(ar, enctype));
2010 }
2011
2012 if (!rxcb->is_first_msdu) {
2013 memcpy(skb_push(msdu,
2014 IEEE80211_QOS_CTL_LEN), &qos_ctl,
2015 IEEE80211_QOS_CTL_LEN);
2016 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
2017 return;
2018 }
2019
2020 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2021
2022 /* original 802.11 header has a different DA and in
2023 * case of 4addr it may also have different SA
2024 */
2025 hdr = (struct ieee80211_hdr *)msdu->data;
2026 ether_addr_copy(ieee80211_get_DA(hdr), da);
2027 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2028 }
2029
ath11k_dp_rx_h_undecap_raw(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2030 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
2031 enum hal_encrypt_type enctype,
2032 struct ieee80211_rx_status *status,
2033 bool decrypted)
2034 {
2035 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2036 struct ieee80211_hdr *hdr;
2037 size_t hdr_len;
2038 size_t crypto_len;
2039
2040 if (!rxcb->is_first_msdu ||
2041 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2042 WARN_ON_ONCE(1);
2043 return;
2044 }
2045
2046 skb_trim(msdu, msdu->len - FCS_LEN);
2047
2048 if (!decrypted)
2049 return;
2050
2051 hdr = (void *)msdu->data;
2052
2053 /* Tail */
2054 if (status->flag & RX_FLAG_IV_STRIPPED) {
2055 skb_trim(msdu, msdu->len -
2056 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2057
2058 skb_trim(msdu, msdu->len -
2059 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2060 } else {
2061 /* MIC */
2062 if (status->flag & RX_FLAG_MIC_STRIPPED)
2063 skb_trim(msdu, msdu->len -
2064 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2065
2066 /* ICV */
2067 if (status->flag & RX_FLAG_ICV_STRIPPED)
2068 skb_trim(msdu, msdu->len -
2069 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2070 }
2071
2072 /* MMIC */
2073 if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2074 !ieee80211_has_morefrags(hdr->frame_control) &&
2075 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2076 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2077
2078 /* Head */
2079 if (status->flag & RX_FLAG_IV_STRIPPED) {
2080 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2081 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2082
2083 memmove((void *)msdu->data + crypto_len,
2084 (void *)msdu->data, hdr_len);
2085 skb_pull(msdu, crypto_len);
2086 }
2087 }
2088
ath11k_dp_rx_h_find_rfc1042(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype)2089 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
2090 struct sk_buff *msdu,
2091 enum hal_encrypt_type enctype)
2092 {
2093 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2094 struct ieee80211_hdr *hdr;
2095 size_t hdr_len, crypto_len;
2096 void *rfc1042;
2097 bool is_amsdu;
2098
2099 is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
2100 hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc);
2101 rfc1042 = hdr;
2102
2103 if (rxcb->is_first_msdu) {
2104 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2105 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2106
2107 rfc1042 += hdr_len + crypto_len;
2108 }
2109
2110 if (is_amsdu)
2111 rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
2112
2113 return rfc1042;
2114 }
2115
ath11k_dp_rx_h_undecap_eth(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2116 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
2117 struct sk_buff *msdu,
2118 u8 *first_hdr,
2119 enum hal_encrypt_type enctype,
2120 struct ieee80211_rx_status *status)
2121 {
2122 struct ieee80211_hdr *hdr;
2123 struct ethhdr *eth;
2124 size_t hdr_len;
2125 u8 da[ETH_ALEN];
2126 u8 sa[ETH_ALEN];
2127 void *rfc1042;
2128
2129 rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
2130 if (WARN_ON_ONCE(!rfc1042))
2131 return;
2132
2133 /* pull decapped header and copy SA & DA */
2134 eth = (struct ethhdr *)msdu->data;
2135 ether_addr_copy(da, eth->h_dest);
2136 ether_addr_copy(sa, eth->h_source);
2137 skb_pull(msdu, sizeof(struct ethhdr));
2138
2139 /* push rfc1042/llc/snap */
2140 memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
2141 sizeof(struct ath11k_dp_rfc1042_hdr));
2142
2143 /* push original 802.11 header */
2144 hdr = (struct ieee80211_hdr *)first_hdr;
2145 hdr_len = ieee80211_hdrlen(hdr->frame_control);
2146
2147 if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2148 memcpy(skb_push(msdu,
2149 ath11k_dp_rx_crypto_param_len(ar, enctype)),
2150 (void *)hdr + hdr_len,
2151 ath11k_dp_rx_crypto_param_len(ar, enctype));
2152 }
2153
2154 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2155
2156 /* original 802.11 header has a different DA and in
2157 * case of 4addr it may also have different SA
2158 */
2159 hdr = (struct ieee80211_hdr *)msdu->data;
2160 ether_addr_copy(ieee80211_get_DA(hdr), da);
2161 ether_addr_copy(ieee80211_get_SA(hdr), sa);
2162 }
2163
ath11k_dp_rx_h_undecap(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2164 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
2165 struct hal_rx_desc *rx_desc,
2166 enum hal_encrypt_type enctype,
2167 struct ieee80211_rx_status *status,
2168 bool decrypted)
2169 {
2170 u8 *first_hdr;
2171 u8 decap;
2172 struct ethhdr *ehdr;
2173
2174 first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
2175 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc);
2176
2177 switch (decap) {
2178 case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2179 ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
2180 enctype, status);
2181 break;
2182 case DP_RX_DECAP_TYPE_RAW:
2183 ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2184 decrypted);
2185 break;
2186 case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2187 ehdr = (struct ethhdr *)msdu->data;
2188
2189 /* mac80211 allows fast path only for authorized STA */
2190 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
2191 ATH11K_SKB_RXCB(msdu)->is_eapol = true;
2192 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2193 enctype, status);
2194 break;
2195 }
2196
2197 /* PN for mcast packets will be validated in mac80211;
2198 * remove eth header and add 802.11 header.
2199 */
2200 if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted)
2201 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2202 enctype, status);
2203 break;
2204 case DP_RX_DECAP_TYPE_8023:
2205 /* TODO: Handle undecap for these formats */
2206 break;
2207 }
2208 }
2209
2210 static struct ath11k_peer *
ath11k_dp_rx_h_find_peer(struct ath11k_base * ab,struct sk_buff * msdu)2211 ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu)
2212 {
2213 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2214 struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2215 struct ath11k_peer *peer = NULL;
2216
2217 lockdep_assert_held(&ab->base_lock);
2218
2219 peer = ath11k_peer_find_by_id(ab, rxcb->peer_id);
2220
2221 if (peer)
2222 return peer;
2223
2224 if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
2225 return NULL;
2226
2227 peer = ath11k_peer_find_by_addr(ab,
2228 ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc));
2229 return peer;
2230 }
2231
ath11k_dp_rx_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2232 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
2233 struct sk_buff *msdu,
2234 struct hal_rx_desc *rx_desc,
2235 struct ieee80211_rx_status *rx_status)
2236 {
2237 bool fill_crypto_hdr;
2238 enum hal_encrypt_type enctype;
2239 bool is_decrypted = false;
2240 struct ath11k_skb_rxcb *rxcb;
2241 struct ieee80211_hdr *hdr;
2242 struct ath11k_peer *peer;
2243 struct rx_attention *rx_attention;
2244 u32 err_bitmap;
2245
2246 /* PN for multicast packets will be checked in mac80211 */
2247 rxcb = ATH11K_SKB_RXCB(msdu);
2248 fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
2249 rxcb->is_mcbc = fill_crypto_hdr;
2250
2251 if (rxcb->is_mcbc) {
2252 rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
2253 rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
2254 }
2255
2256 spin_lock_bh(&ar->ab->base_lock);
2257 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2258 if (peer) {
2259 if (rxcb->is_mcbc)
2260 enctype = peer->sec_type_grp;
2261 else
2262 enctype = peer->sec_type;
2263 } else {
2264 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
2265 }
2266 spin_unlock_bh(&ar->ab->base_lock);
2267
2268 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
2269 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
2270 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2271 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
2272
2273 /* Clear per-MPDU flags while leaving per-PPDU flags intact */
2274 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2275 RX_FLAG_MMIC_ERROR |
2276 RX_FLAG_DECRYPTED |
2277 RX_FLAG_IV_STRIPPED |
2278 RX_FLAG_MMIC_STRIPPED);
2279
2280 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
2281 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2282 if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
2283 rx_status->flag |= RX_FLAG_MMIC_ERROR;
2284
2285 if (is_decrypted) {
2286 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2287
2288 if (fill_crypto_hdr)
2289 rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2290 RX_FLAG_ICV_STRIPPED;
2291 else
2292 rx_status->flag |= RX_FLAG_IV_STRIPPED |
2293 RX_FLAG_PN_VALIDATED;
2294 }
2295
2296 ath11k_dp_rx_h_csum_offload(ar, msdu);
2297 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
2298 enctype, rx_status, is_decrypted);
2299
2300 if (!is_decrypted || fill_crypto_hdr)
2301 return;
2302
2303 if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) !=
2304 DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
2305 hdr = (void *)msdu->data;
2306 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2307 }
2308 }
2309
ath11k_dp_rx_h_rate(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2310 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2311 struct ieee80211_rx_status *rx_status)
2312 {
2313 struct ieee80211_supported_band *sband;
2314 enum rx_msdu_start_pkt_type pkt_type;
2315 u8 bw;
2316 u8 rate_mcs, nss;
2317 u8 sgi;
2318 bool is_cck, is_ldpc;
2319
2320 pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc);
2321 bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc);
2322 rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc);
2323 nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc);
2324 sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc);
2325
2326 switch (pkt_type) {
2327 case RX_MSDU_START_PKT_TYPE_11A:
2328 case RX_MSDU_START_PKT_TYPE_11B:
2329 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2330 sband = &ar->mac.sbands[rx_status->band];
2331 rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
2332 is_cck);
2333 break;
2334 case RX_MSDU_START_PKT_TYPE_11N:
2335 rx_status->encoding = RX_ENC_HT;
2336 if (rate_mcs > ATH11K_HT_MCS_MAX) {
2337 ath11k_warn(ar->ab,
2338 "Received with invalid mcs in HT mode %d\n",
2339 rate_mcs);
2340 break;
2341 }
2342 rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2343 if (sgi)
2344 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2345 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2346 break;
2347 case RX_MSDU_START_PKT_TYPE_11AC:
2348 rx_status->encoding = RX_ENC_VHT;
2349 rx_status->rate_idx = rate_mcs;
2350 if (rate_mcs > ATH11K_VHT_MCS_MAX) {
2351 ath11k_warn(ar->ab,
2352 "Received with invalid mcs in VHT mode %d\n",
2353 rate_mcs);
2354 break;
2355 }
2356 rx_status->nss = nss;
2357 if (sgi)
2358 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2359 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2360 is_ldpc = ath11k_dp_rx_h_msdu_start_ldpc_support(ar->ab, rx_desc);
2361 if (is_ldpc)
2362 rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
2363 break;
2364 case RX_MSDU_START_PKT_TYPE_11AX:
2365 rx_status->rate_idx = rate_mcs;
2366 if (rate_mcs > ATH11K_HE_MCS_MAX) {
2367 ath11k_warn(ar->ab,
2368 "Received with invalid mcs in HE mode %d\n",
2369 rate_mcs);
2370 break;
2371 }
2372 rx_status->encoding = RX_ENC_HE;
2373 rx_status->nss = nss;
2374 rx_status->he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
2375 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2376 break;
2377 }
2378 }
2379
ath11k_dp_rx_h_ppdu(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2380 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2381 struct ieee80211_rx_status *rx_status)
2382 {
2383 u8 channel_num;
2384 u32 center_freq, meta_data;
2385 struct ieee80211_channel *channel;
2386
2387 rx_status->freq = 0;
2388 rx_status->rate_idx = 0;
2389 rx_status->nss = 0;
2390 rx_status->encoding = RX_ENC_LEGACY;
2391 rx_status->bw = RATE_INFO_BW_20;
2392
2393 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2394
2395 meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc);
2396 channel_num = meta_data;
2397 center_freq = meta_data >> 16;
2398
2399 if (center_freq >= ATH11K_MIN_6G_FREQ &&
2400 center_freq <= ATH11K_MAX_6G_FREQ) {
2401 rx_status->band = NL80211_BAND_6GHZ;
2402 rx_status->freq = center_freq;
2403 } else if (channel_num >= 1 && channel_num <= 14) {
2404 rx_status->band = NL80211_BAND_2GHZ;
2405 } else if (channel_num >= 36 && channel_num <= 177) {
2406 rx_status->band = NL80211_BAND_5GHZ;
2407 } else {
2408 spin_lock_bh(&ar->data_lock);
2409 channel = ar->rx_channel;
2410 if (channel) {
2411 rx_status->band = channel->band;
2412 channel_num =
2413 ieee80211_frequency_to_channel(channel->center_freq);
2414 }
2415 spin_unlock_bh(&ar->data_lock);
2416 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
2417 rx_desc, sizeof(struct hal_rx_desc));
2418 }
2419
2420 if (rx_status->band != NL80211_BAND_6GHZ)
2421 rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2422 rx_status->band);
2423
2424 ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
2425 }
2426
ath11k_dp_rx_deliver_msdu(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct ieee80211_rx_status * status)2427 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
2428 struct sk_buff *msdu,
2429 struct ieee80211_rx_status *status)
2430 {
2431 static const struct ieee80211_radiotap_he known = {
2432 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2433 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2434 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2435 };
2436 struct ieee80211_rx_status *rx_status;
2437 struct ieee80211_radiotap_he *he = NULL;
2438 struct ieee80211_sta *pubsta = NULL;
2439 struct ath11k_peer *peer;
2440 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2441 u8 decap = DP_RX_DECAP_TYPE_RAW;
2442 bool is_mcbc = rxcb->is_mcbc;
2443 bool is_eapol = rxcb->is_eapol;
2444
2445 if (status->encoding == RX_ENC_HE &&
2446 !(status->flag & RX_FLAG_RADIOTAP_HE) &&
2447 !(status->flag & RX_FLAG_SKIP_MONITOR)) {
2448 he = skb_push(msdu, sizeof(known));
2449 memcpy(he, &known, sizeof(known));
2450 status->flag |= RX_FLAG_RADIOTAP_HE;
2451 }
2452
2453 if (!(status->flag & RX_FLAG_ONLY_MONITOR))
2454 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc);
2455
2456 spin_lock_bh(&ar->ab->base_lock);
2457 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2458 if (peer && peer->sta)
2459 pubsta = peer->sta;
2460 spin_unlock_bh(&ar->ab->base_lock);
2461
2462 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
2463 "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2464 msdu,
2465 msdu->len,
2466 peer ? peer->addr : NULL,
2467 rxcb->tid,
2468 is_mcbc ? "mcast" : "ucast",
2469 rxcb->seq_no,
2470 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2471 (status->encoding == RX_ENC_HT) ? "ht" : "",
2472 (status->encoding == RX_ENC_VHT) ? "vht" : "",
2473 (status->encoding == RX_ENC_HE) ? "he" : "",
2474 (status->bw == RATE_INFO_BW_40) ? "40" : "",
2475 (status->bw == RATE_INFO_BW_80) ? "80" : "",
2476 (status->bw == RATE_INFO_BW_160) ? "160" : "",
2477 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2478 status->rate_idx,
2479 status->nss,
2480 status->freq,
2481 status->band, status->flag,
2482 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2483 !!(status->flag & RX_FLAG_MMIC_ERROR),
2484 !!(status->flag & RX_FLAG_AMSDU_MORE));
2485
2486 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
2487 msdu->data, msdu->len);
2488
2489 rx_status = IEEE80211_SKB_RXCB(msdu);
2490 *rx_status = *status;
2491
2492 /* TODO: trace rx packet */
2493
2494 /* PN for multicast packets are not validate in HW,
2495 * so skip 802.3 rx path
2496 * Also, fast_rx expects the STA to be authorized, hence
2497 * eapol packets are sent in slow path.
2498 */
2499 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
2500 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2501 rx_status->flag |= RX_FLAG_8023;
2502
2503 ieee80211_rx_napi(ar->hw, pubsta, msdu, napi);
2504 }
2505
ath11k_dp_rx_process_msdu(struct ath11k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list,struct ieee80211_rx_status * rx_status)2506 static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
2507 struct sk_buff *msdu,
2508 struct sk_buff_head *msdu_list,
2509 struct ieee80211_rx_status *rx_status)
2510 {
2511 struct ath11k_base *ab = ar->ab;
2512 struct hal_rx_desc *rx_desc, *lrx_desc;
2513 struct rx_attention *rx_attention;
2514 struct ath11k_skb_rxcb *rxcb;
2515 struct sk_buff *last_buf;
2516 u8 l3_pad_bytes;
2517 u8 *hdr_status;
2518 u16 msdu_len;
2519 int ret;
2520 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
2521
2522 last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2523 if (!last_buf) {
2524 ath11k_warn(ab,
2525 "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
2526 ret = -EIO;
2527 goto free_out;
2528 }
2529
2530 rx_desc = (struct hal_rx_desc *)msdu->data;
2531 if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) {
2532 ath11k_warn(ar->ab, "msdu len not valid\n");
2533 ret = -EIO;
2534 goto free_out;
2535 }
2536
2537 lrx_desc = (struct hal_rx_desc *)last_buf->data;
2538 rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc);
2539 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
2540 ath11k_warn(ab, "msdu_done bit in attention is not set\n");
2541 ret = -EIO;
2542 goto free_out;
2543 }
2544
2545 rxcb = ATH11K_SKB_RXCB(msdu);
2546 rxcb->rx_desc = rx_desc;
2547 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc);
2548 l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc);
2549
2550 if (rxcb->is_frag) {
2551 skb_pull(msdu, hal_rx_desc_sz);
2552 } else if (!rxcb->is_continuation) {
2553 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2554 hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc);
2555 ret = -EINVAL;
2556 ath11k_warn(ab, "invalid msdu len %u\n", msdu_len);
2557 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
2558 sizeof(struct ieee80211_hdr));
2559 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
2560 sizeof(struct hal_rx_desc));
2561 goto free_out;
2562 }
2563 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2564 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2565 } else {
2566 ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
2567 msdu, last_buf,
2568 l3_pad_bytes, msdu_len);
2569 if (ret) {
2570 ath11k_warn(ab,
2571 "failed to coalesce msdu rx buffer%d\n", ret);
2572 goto free_out;
2573 }
2574 }
2575
2576 ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
2577 ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
2578
2579 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2580
2581 return 0;
2582
2583 free_out:
2584 return ret;
2585 }
2586
ath11k_dp_rx_process_received_packets(struct ath11k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int mac_id)2587 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
2588 struct napi_struct *napi,
2589 struct sk_buff_head *msdu_list,
2590 int mac_id)
2591 {
2592 struct sk_buff *msdu;
2593 struct ath11k *ar;
2594 struct ieee80211_rx_status rx_status = {};
2595 int ret;
2596
2597 if (skb_queue_empty(msdu_list))
2598 return;
2599
2600 if (unlikely(!rcu_access_pointer(ab->pdevs_active[mac_id]))) {
2601 __skb_queue_purge(msdu_list);
2602 return;
2603 }
2604
2605 ar = ab->pdevs[mac_id].ar;
2606 if (unlikely(test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags))) {
2607 __skb_queue_purge(msdu_list);
2608 return;
2609 }
2610
2611 while ((msdu = __skb_dequeue(msdu_list))) {
2612 ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
2613 if (unlikely(ret)) {
2614 ath11k_dbg(ab, ATH11K_DBG_DATA,
2615 "Unable to process msdu %d", ret);
2616 dev_kfree_skb_any(msdu);
2617 continue;
2618 }
2619
2620 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
2621 }
2622 }
2623
ath11k_dp_process_rx(struct ath11k_base * ab,int ring_id,struct napi_struct * napi,int budget)2624 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
2625 struct napi_struct *napi, int budget)
2626 {
2627 struct ath11k_dp *dp = &ab->dp;
2628 struct dp_rxdma_ring *rx_ring;
2629 int num_buffs_reaped[MAX_RADIOS] = {};
2630 struct sk_buff_head msdu_list[MAX_RADIOS];
2631 struct ath11k_skb_rxcb *rxcb;
2632 int total_msdu_reaped = 0;
2633 struct hal_srng *srng;
2634 struct sk_buff *msdu;
2635 bool done = false;
2636 int buf_id, mac_id;
2637 struct ath11k *ar;
2638 struct hal_reo_dest_ring *desc;
2639 enum hal_reo_dest_ring_push_reason push_reason;
2640 u32 cookie;
2641 int i;
2642
2643 for (i = 0; i < MAX_RADIOS; i++)
2644 __skb_queue_head_init(&msdu_list[i]);
2645
2646 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2647
2648 spin_lock_bh(&srng->lock);
2649
2650 try_again:
2651 ath11k_hal_srng_access_begin(ab, srng);
2652
2653 while (likely(desc =
2654 (struct hal_reo_dest_ring *)ath11k_hal_srng_dst_get_next_entry(ab,
2655 srng))) {
2656 cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
2657 desc->buf_addr_info.info1);
2658 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
2659 cookie);
2660 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
2661
2662 if (unlikely(buf_id == 0))
2663 continue;
2664
2665 ar = ab->pdevs[mac_id].ar;
2666 rx_ring = &ar->dp.rx_refill_buf_ring;
2667 spin_lock_bh(&rx_ring->idr_lock);
2668 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
2669 if (unlikely(!msdu)) {
2670 ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
2671 buf_id);
2672 spin_unlock_bh(&rx_ring->idr_lock);
2673 continue;
2674 }
2675
2676 idr_remove(&rx_ring->bufs_idr, buf_id);
2677 spin_unlock_bh(&rx_ring->idr_lock);
2678
2679 rxcb = ATH11K_SKB_RXCB(msdu);
2680 dma_unmap_single(ab->dev, rxcb->paddr,
2681 msdu->len + skb_tailroom(msdu),
2682 DMA_FROM_DEVICE);
2683
2684 num_buffs_reaped[mac_id]++;
2685
2686 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
2687 desc->info0);
2688 if (unlikely(push_reason !=
2689 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) {
2690 dev_kfree_skb_any(msdu);
2691 ab->soc_stats.hal_reo_error[ring_id]++;
2692 continue;
2693 }
2694
2695 rxcb->is_first_msdu = !!(desc->rx_msdu_info.info0 &
2696 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2697 rxcb->is_last_msdu = !!(desc->rx_msdu_info.info0 &
2698 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2699 rxcb->is_continuation = !!(desc->rx_msdu_info.info0 &
2700 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2701 rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID,
2702 desc->rx_mpdu_info.meta_data);
2703 rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM,
2704 desc->rx_mpdu_info.info0);
2705 rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
2706 desc->info0);
2707
2708 rxcb->mac_id = mac_id;
2709 __skb_queue_tail(&msdu_list[mac_id], msdu);
2710
2711 if (rxcb->is_continuation) {
2712 done = false;
2713 } else {
2714 total_msdu_reaped++;
2715 done = true;
2716 }
2717
2718 if (total_msdu_reaped >= budget)
2719 break;
2720 }
2721
2722 /* Hw might have updated the head pointer after we cached it.
2723 * In this case, even though there are entries in the ring we'll
2724 * get rx_desc NULL. Give the read another try with updated cached
2725 * head pointer so that we can reap complete MPDU in the current
2726 * rx processing.
2727 */
2728 if (unlikely(!done && ath11k_hal_srng_dst_num_free(ab, srng, true))) {
2729 ath11k_hal_srng_access_end(ab, srng);
2730 goto try_again;
2731 }
2732
2733 ath11k_hal_srng_access_end(ab, srng);
2734
2735 spin_unlock_bh(&srng->lock);
2736
2737 if (unlikely(!total_msdu_reaped))
2738 goto exit;
2739
2740 for (i = 0; i < ab->num_radios; i++) {
2741 if (!num_buffs_reaped[i])
2742 continue;
2743
2744 ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list[i], i);
2745
2746 ar = ab->pdevs[i].ar;
2747 rx_ring = &ar->dp.rx_refill_buf_ring;
2748
2749 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
2750 ab->hw_params.hal_params->rx_buf_rbm);
2751 }
2752 exit:
2753 return total_msdu_reaped;
2754 }
2755
ath11k_dp_rx_update_peer_stats(struct ath11k_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2756 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
2757 struct hal_rx_mon_ppdu_info *ppdu_info)
2758 {
2759 struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
2760 u32 num_msdu;
2761 int i;
2762
2763 if (!rx_stats)
2764 return;
2765
2766 arsta->rssi_comb = ppdu_info->rssi_comb;
2767 ewma_avg_rssi_add(&arsta->avg_rssi, ppdu_info->rssi_comb);
2768
2769 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2770 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2771
2772 rx_stats->num_msdu += num_msdu;
2773 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2774 ppdu_info->tcp_ack_msdu_count;
2775 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2776 rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2777
2778 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2779 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2780 ppdu_info->nss = 1;
2781 ppdu_info->mcs = HAL_RX_MAX_MCS;
2782 ppdu_info->tid = IEEE80211_NUM_TIDS;
2783 }
2784
2785 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
2786 rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
2787
2788 if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
2789 rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
2790
2791 if (ppdu_info->gi < HAL_RX_GI_MAX)
2792 rx_stats->gi_count[ppdu_info->gi] += num_msdu;
2793
2794 if (ppdu_info->bw < HAL_RX_BW_MAX)
2795 rx_stats->bw_count[ppdu_info->bw] += num_msdu;
2796
2797 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2798 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2799
2800 if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2801 rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2802
2803 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2804 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2805
2806 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2807 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2808
2809 if (ppdu_info->is_stbc)
2810 rx_stats->stbc_count += num_msdu;
2811
2812 if (ppdu_info->beamformed)
2813 rx_stats->beamformed_count += num_msdu;
2814
2815 if (ppdu_info->num_mpdu_fcs_ok > 1)
2816 rx_stats->ampdu_msdu_count += num_msdu;
2817 else
2818 rx_stats->non_ampdu_msdu_count += num_msdu;
2819
2820 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2821 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2822 rx_stats->dcm_count += ppdu_info->dcm;
2823 rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
2824
2825 BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) >
2826 ARRAY_SIZE(ppdu_info->rssi_chain_pri20));
2827
2828 for (i = 0; i < ARRAY_SIZE(arsta->chain_signal); i++)
2829 arsta->chain_signal[i] = ppdu_info->rssi_chain_pri20[i];
2830
2831 rx_stats->rx_duration += ppdu_info->rx_duration;
2832 arsta->rx_duration = rx_stats->rx_duration;
2833 }
2834
ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base * ab,struct dp_rxdma_ring * rx_ring,int * buf_id)2835 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
2836 struct dp_rxdma_ring *rx_ring,
2837 int *buf_id)
2838 {
2839 struct sk_buff *skb;
2840 dma_addr_t paddr;
2841
2842 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
2843 DP_RX_BUFFER_ALIGN_SIZE);
2844
2845 if (!skb)
2846 goto fail_alloc_skb;
2847
2848 if (!IS_ALIGNED((unsigned long)skb->data,
2849 DP_RX_BUFFER_ALIGN_SIZE)) {
2850 skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2851 skb->data);
2852 }
2853
2854 paddr = dma_map_single(ab->dev, skb->data,
2855 skb->len + skb_tailroom(skb),
2856 DMA_FROM_DEVICE);
2857 if (unlikely(dma_mapping_error(ab->dev, paddr)))
2858 goto fail_free_skb;
2859
2860 spin_lock_bh(&rx_ring->idr_lock);
2861 *buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
2862 rx_ring->bufs_max, GFP_ATOMIC);
2863 spin_unlock_bh(&rx_ring->idr_lock);
2864 if (*buf_id < 0)
2865 goto fail_dma_unmap;
2866
2867 ATH11K_SKB_RXCB(skb)->paddr = paddr;
2868 return skb;
2869
2870 fail_dma_unmap:
2871 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2872 DMA_FROM_DEVICE);
2873 fail_free_skb:
2874 dev_kfree_skb_any(skb);
2875 fail_alloc_skb:
2876 return NULL;
2877 }
2878
ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)2879 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
2880 struct dp_rxdma_ring *rx_ring,
2881 int req_entries,
2882 enum hal_rx_buf_return_buf_manager mgr)
2883 {
2884 struct hal_srng *srng;
2885 u32 *desc;
2886 struct sk_buff *skb;
2887 int num_free;
2888 int num_remain;
2889 int buf_id;
2890 u32 cookie;
2891 dma_addr_t paddr;
2892
2893 req_entries = min(req_entries, rx_ring->bufs_max);
2894
2895 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2896
2897 spin_lock_bh(&srng->lock);
2898
2899 ath11k_hal_srng_access_begin(ab, srng);
2900
2901 num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
2902
2903 req_entries = min(num_free, req_entries);
2904 num_remain = req_entries;
2905
2906 while (num_remain > 0) {
2907 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2908 &buf_id);
2909 if (!skb)
2910 break;
2911 paddr = ATH11K_SKB_RXCB(skb)->paddr;
2912
2913 desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
2914 if (!desc)
2915 goto fail_desc_get;
2916
2917 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2918 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2919
2920 num_remain--;
2921
2922 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
2923 }
2924
2925 ath11k_hal_srng_access_end(ab, srng);
2926
2927 spin_unlock_bh(&srng->lock);
2928
2929 return req_entries - num_remain;
2930
2931 fail_desc_get:
2932 spin_lock_bh(&rx_ring->idr_lock);
2933 idr_remove(&rx_ring->bufs_idr, buf_id);
2934 spin_unlock_bh(&rx_ring->idr_lock);
2935 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2936 DMA_FROM_DEVICE);
2937 dev_kfree_skb_any(skb);
2938 ath11k_hal_srng_access_end(ab, srng);
2939 spin_unlock_bh(&srng->lock);
2940
2941 return req_entries - num_remain;
2942 }
2943
2944 #define ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP 32535
2945
2946 static void
ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data * pmon,struct hal_tlv_hdr * tlv)2947 ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data *pmon,
2948 struct hal_tlv_hdr *tlv)
2949 {
2950 struct hal_rx_ppdu_start *ppdu_start;
2951 u16 ppdu_id_diff, ppdu_id, tlv_len;
2952 u8 *ptr;
2953
2954 /* PPDU id is part of second tlv, move ptr to second tlv */
2955 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl);
2956 ptr = (u8 *)tlv;
2957 ptr += sizeof(*tlv) + tlv_len;
2958 tlv = (struct hal_tlv_hdr *)ptr;
2959
2960 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_PPDU_START)
2961 return;
2962
2963 ptr += sizeof(*tlv);
2964 ppdu_start = (struct hal_rx_ppdu_start *)ptr;
2965 ppdu_id = FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID,
2966 __le32_to_cpu(ppdu_start->info0));
2967
2968 if (pmon->sw_mon_entries.ppdu_id < ppdu_id) {
2969 pmon->buf_state = DP_MON_STATUS_LEAD;
2970 ppdu_id_diff = ppdu_id - pmon->sw_mon_entries.ppdu_id;
2971 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
2972 pmon->buf_state = DP_MON_STATUS_LAG;
2973 } else if (pmon->sw_mon_entries.ppdu_id > ppdu_id) {
2974 pmon->buf_state = DP_MON_STATUS_LAG;
2975 ppdu_id_diff = pmon->sw_mon_entries.ppdu_id - ppdu_id;
2976 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
2977 pmon->buf_state = DP_MON_STATUS_LEAD;
2978 }
2979 }
2980
2981 static enum dp_mon_status_buf_state
ath11k_dp_rx_mon_buf_done(struct ath11k_base * ab,struct hal_srng * srng,struct dp_rxdma_ring * rx_ring)2982 ath11k_dp_rx_mon_buf_done(struct ath11k_base *ab, struct hal_srng *srng,
2983 struct dp_rxdma_ring *rx_ring)
2984 {
2985 struct ath11k_skb_rxcb *rxcb;
2986 struct hal_tlv_hdr *tlv;
2987 struct sk_buff *skb;
2988 void *status_desc;
2989 dma_addr_t paddr;
2990 u32 cookie;
2991 int buf_id;
2992 u8 rbm;
2993
2994 status_desc = ath11k_hal_srng_src_next_peek(ab, srng);
2995 if (!status_desc)
2996 return DP_MON_STATUS_NO_DMA;
2997
2998 ath11k_hal_rx_buf_addr_info_get(status_desc, &paddr, &cookie, &rbm);
2999
3000 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3001
3002 spin_lock_bh(&rx_ring->idr_lock);
3003 skb = idr_find(&rx_ring->bufs_idr, buf_id);
3004 spin_unlock_bh(&rx_ring->idr_lock);
3005
3006 if (!skb)
3007 return DP_MON_STATUS_NO_DMA;
3008
3009 rxcb = ATH11K_SKB_RXCB(skb);
3010 dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3011 skb->len + skb_tailroom(skb),
3012 DMA_FROM_DEVICE);
3013
3014 tlv = (struct hal_tlv_hdr *)skb->data;
3015 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_STATUS_BUFFER_DONE)
3016 return DP_MON_STATUS_NO_DMA;
3017
3018 return DP_MON_STATUS_REPLINISH;
3019 }
3020
ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base * ab,int mac_id,int * budget,struct sk_buff_head * skb_list)3021 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
3022 int *budget, struct sk_buff_head *skb_list)
3023 {
3024 struct ath11k *ar;
3025 const struct ath11k_hw_hal_params *hal_params;
3026 enum dp_mon_status_buf_state reap_status;
3027 struct ath11k_pdev_dp *dp;
3028 struct dp_rxdma_ring *rx_ring;
3029 struct ath11k_mon_data *pmon;
3030 struct hal_srng *srng;
3031 void *rx_mon_status_desc;
3032 struct sk_buff *skb;
3033 struct ath11k_skb_rxcb *rxcb;
3034 struct hal_tlv_hdr *tlv;
3035 u32 cookie;
3036 int buf_id, srng_id;
3037 dma_addr_t paddr;
3038 u8 rbm;
3039 int num_buffs_reaped = 0;
3040
3041 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
3042 dp = &ar->dp;
3043 pmon = &dp->mon_data;
3044 srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
3045 rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
3046
3047 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
3048
3049 spin_lock_bh(&srng->lock);
3050
3051 ath11k_hal_srng_access_begin(ab, srng);
3052 while (*budget) {
3053 *budget -= 1;
3054 rx_mon_status_desc =
3055 ath11k_hal_srng_src_peek(ab, srng);
3056 if (!rx_mon_status_desc) {
3057 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3058 break;
3059 }
3060
3061 ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
3062 &cookie, &rbm);
3063 if (paddr) {
3064 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3065
3066 spin_lock_bh(&rx_ring->idr_lock);
3067 skb = idr_find(&rx_ring->bufs_idr, buf_id);
3068 spin_unlock_bh(&rx_ring->idr_lock);
3069
3070 if (!skb) {
3071 ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
3072 buf_id);
3073 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3074 goto move_next;
3075 }
3076
3077 rxcb = ATH11K_SKB_RXCB(skb);
3078
3079 dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3080 skb->len + skb_tailroom(skb),
3081 DMA_FROM_DEVICE);
3082
3083 tlv = (struct hal_tlv_hdr *)skb->data;
3084 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
3085 HAL_RX_STATUS_BUFFER_DONE) {
3086 ath11k_warn(ab, "mon status DONE not set %lx, buf_id %d\n",
3087 FIELD_GET(HAL_TLV_HDR_TAG,
3088 tlv->tl), buf_id);
3089 /* RxDMA status done bit might not be set even
3090 * though tp is moved by HW.
3091 */
3092
3093 /* If done status is missing:
3094 * 1. As per MAC team's suggestion,
3095 * when HP + 1 entry is peeked and if DMA
3096 * is not done and if HP + 2 entry's DMA done
3097 * is set. skip HP + 1 entry and
3098 * start processing in next interrupt.
3099 * 2. If HP + 2 entry's DMA done is not set,
3100 * poll onto HP + 1 entry DMA done to be set.
3101 * Check status for same buffer for next time
3102 * dp_rx_mon_status_srng_process
3103 */
3104
3105 reap_status = ath11k_dp_rx_mon_buf_done(ab, srng,
3106 rx_ring);
3107 if (reap_status == DP_MON_STATUS_NO_DMA)
3108 continue;
3109
3110 spin_lock_bh(&rx_ring->idr_lock);
3111 idr_remove(&rx_ring->bufs_idr, buf_id);
3112 spin_unlock_bh(&rx_ring->idr_lock);
3113
3114 dma_unmap_single(ab->dev, rxcb->paddr,
3115 skb->len + skb_tailroom(skb),
3116 DMA_FROM_DEVICE);
3117
3118 dev_kfree_skb_any(skb);
3119 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3120 goto move_next;
3121 }
3122
3123 spin_lock_bh(&rx_ring->idr_lock);
3124 idr_remove(&rx_ring->bufs_idr, buf_id);
3125 spin_unlock_bh(&rx_ring->idr_lock);
3126 if (ab->hw_params.full_monitor_mode) {
3127 ath11k_dp_rx_mon_update_status_buf_state(pmon, tlv);
3128 if (paddr == pmon->mon_status_paddr)
3129 pmon->buf_state = DP_MON_STATUS_MATCH;
3130 }
3131
3132 dma_unmap_single(ab->dev, rxcb->paddr,
3133 skb->len + skb_tailroom(skb),
3134 DMA_FROM_DEVICE);
3135
3136 __skb_queue_tail(skb_list, skb);
3137 } else {
3138 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3139 }
3140 move_next:
3141 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
3142 &buf_id);
3143
3144 if (!skb) {
3145 hal_params = ab->hw_params.hal_params;
3146 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
3147 hal_params->rx_buf_rbm);
3148 num_buffs_reaped++;
3149 break;
3150 }
3151 rxcb = ATH11K_SKB_RXCB(skb);
3152
3153 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
3154 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3155
3156 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
3157 cookie,
3158 ab->hw_params.hal_params->rx_buf_rbm);
3159 ath11k_hal_srng_src_get_next_entry(ab, srng);
3160 num_buffs_reaped++;
3161 }
3162 ath11k_hal_srng_access_end(ab, srng);
3163 spin_unlock_bh(&srng->lock);
3164
3165 return num_buffs_reaped;
3166 }
3167
ath11k_dp_rx_frag_timer(struct timer_list * timer)3168 static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
3169 {
3170 struct dp_rx_tid *rx_tid = timer_container_of(rx_tid, timer,
3171 frag_timer);
3172
3173 spin_lock_bh(&rx_tid->ab->base_lock);
3174 if (rx_tid->last_frag_no &&
3175 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
3176 spin_unlock_bh(&rx_tid->ab->base_lock);
3177 return;
3178 }
3179 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3180 spin_unlock_bh(&rx_tid->ab->base_lock);
3181 }
3182
ath11k_peer_rx_frag_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id)3183 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
3184 {
3185 struct ath11k_base *ab = ar->ab;
3186 struct ath11k_peer *peer;
3187 struct dp_rx_tid *rx_tid;
3188 int i;
3189
3190 if (fips_enabled) {
3191 ath11k_warn(ab, "This driver is disabled due to FIPS\n");
3192 return -ENOENT;
3193 }
3194
3195 spin_lock_bh(&ab->base_lock);
3196
3197 peer = ath11k_peer_find(ab, vdev_id, peer_mac);
3198 if (!peer) {
3199 ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
3200 spin_unlock_bh(&ab->base_lock);
3201 return -ENOENT;
3202 }
3203
3204 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
3205 rx_tid = &peer->rx_tid[i];
3206 rx_tid->ab = ab;
3207 timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
3208 skb_queue_head_init(&rx_tid->rx_frags);
3209 }
3210
3211 peer->dp_setup_done = true;
3212 spin_unlock_bh(&ab->base_lock);
3213
3214 return 0;
3215 }
3216
ath11k_dp_rx_h_verify_tkip_mic(struct ath11k * ar,struct ath11k_peer * peer,struct sk_buff * msdu)3217 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
3218 struct sk_buff *msdu)
3219 {
3220 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3221 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
3222 struct ieee80211_key_conf *key_conf;
3223 struct ieee80211_hdr *hdr;
3224 u8 mic[IEEE80211_CCMP_MIC_LEN];
3225 int head_len, tail_len;
3226 size_t data_len;
3227 u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3228 u8 *key, *data;
3229 u8 key_idx;
3230
3231 if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) !=
3232 HAL_ENCRYPT_TYPE_TKIP_MIC)
3233 return 0;
3234
3235 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3236 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3237 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
3238 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3239
3240 if (!is_multicast_ether_addr(hdr->addr1))
3241 key_idx = peer->ucast_keyidx;
3242 else
3243 key_idx = peer->mcast_keyidx;
3244
3245 key_conf = peer->keys[key_idx];
3246
3247 data = msdu->data + head_len;
3248 data_len = msdu->len - head_len - tail_len;
3249 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3250
3251 michael_mic(key, hdr, data, data_len, mic);
3252 if (memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3253 goto mic_fail;
3254
3255 return 0;
3256
3257 mic_fail:
3258 (ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
3259 (ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
3260
3261 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3262 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3263 skb_pull(msdu, hal_rx_desc_sz);
3264
3265 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3266 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
3267 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3268 ieee80211_rx(ar->hw, msdu);
3269 return -EINVAL;
3270 }
3271
ath11k_dp_rx_h_undecap_frag(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)3272 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
3273 enum hal_encrypt_type enctype, u32 flags)
3274 {
3275 struct ieee80211_hdr *hdr;
3276 size_t hdr_len;
3277 size_t crypto_len;
3278 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3279
3280 if (!flags)
3281 return;
3282
3283 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3284
3285 if (flags & RX_FLAG_MIC_STRIPPED)
3286 skb_trim(msdu, msdu->len -
3287 ath11k_dp_rx_crypto_mic_len(ar, enctype));
3288
3289 if (flags & RX_FLAG_ICV_STRIPPED)
3290 skb_trim(msdu, msdu->len -
3291 ath11k_dp_rx_crypto_icv_len(ar, enctype));
3292
3293 if (flags & RX_FLAG_IV_STRIPPED) {
3294 hdr_len = ieee80211_hdrlen(hdr->frame_control);
3295 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
3296
3297 memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len,
3298 (void *)msdu->data + hal_rx_desc_sz, hdr_len);
3299 skb_pull(msdu, crypto_len);
3300 }
3301 }
3302
ath11k_dp_rx_h_defrag(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)3303 static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
3304 struct ath11k_peer *peer,
3305 struct dp_rx_tid *rx_tid,
3306 struct sk_buff **defrag_skb)
3307 {
3308 struct hal_rx_desc *rx_desc;
3309 struct sk_buff *skb, *first_frag, *last_frag;
3310 struct ieee80211_hdr *hdr;
3311 struct rx_attention *rx_attention;
3312 enum hal_encrypt_type enctype;
3313 bool is_decrypted = false;
3314 int msdu_len = 0;
3315 int extra_space;
3316 u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3317
3318 first_frag = skb_peek(&rx_tid->rx_frags);
3319 last_frag = skb_peek_tail(&rx_tid->rx_frags);
3320
3321 skb_queue_walk(&rx_tid->rx_frags, skb) {
3322 flags = 0;
3323 rx_desc = (struct hal_rx_desc *)skb->data;
3324 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3325
3326 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
3327 if (enctype != HAL_ENCRYPT_TYPE_OPEN) {
3328 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
3329 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
3330 }
3331
3332 if (is_decrypted) {
3333 if (skb != first_frag)
3334 flags |= RX_FLAG_IV_STRIPPED;
3335 if (skb != last_frag)
3336 flags |= RX_FLAG_ICV_STRIPPED |
3337 RX_FLAG_MIC_STRIPPED;
3338 }
3339
3340 /* RX fragments are always raw packets */
3341 if (skb != last_frag)
3342 skb_trim(skb, skb->len - FCS_LEN);
3343 ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3344
3345 if (skb != first_frag)
3346 skb_pull(skb, hal_rx_desc_sz +
3347 ieee80211_hdrlen(hdr->frame_control));
3348 msdu_len += skb->len;
3349 }
3350
3351 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3352 if (extra_space > 0 &&
3353 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3354 return -ENOMEM;
3355
3356 __skb_unlink(first_frag, &rx_tid->rx_frags);
3357 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3358 skb_put_data(first_frag, skb->data, skb->len);
3359 dev_kfree_skb_any(skb);
3360 }
3361
3362 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
3363 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3364 ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
3365
3366 if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3367 first_frag = NULL;
3368
3369 *defrag_skb = first_frag;
3370 return 0;
3371 }
3372
ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k * ar,struct dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3373 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
3374 struct sk_buff *defrag_skb)
3375 {
3376 struct ath11k_base *ab = ar->ab;
3377 struct ath11k_pdev_dp *dp = &ar->dp;
3378 struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
3379 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3380 struct hal_reo_entrance_ring *reo_ent_ring;
3381 struct hal_reo_dest_ring *reo_dest_ring;
3382 struct dp_link_desc_bank *link_desc_banks;
3383 struct hal_rx_msdu_link *msdu_link;
3384 struct hal_rx_msdu_details *msdu0;
3385 struct hal_srng *srng;
3386 dma_addr_t paddr;
3387 u32 desc_bank, msdu_info, mpdu_info;
3388 u32 dst_idx, cookie, hal_rx_desc_sz;
3389 int ret, buf_id;
3390
3391 hal_rx_desc_sz = ab->hw_params.hal_desc_sz;
3392 link_desc_banks = ab->dp.link_desc_banks;
3393 reo_dest_ring = rx_tid->dst_ring_desc;
3394
3395 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3396 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3397 (paddr - link_desc_banks[desc_bank].paddr));
3398 msdu0 = &msdu_link->msdu_link[0];
3399 dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
3400 memset(msdu0, 0, sizeof(*msdu0));
3401
3402 msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
3403 FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
3404 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
3405 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
3406 defrag_skb->len - hal_rx_desc_sz) |
3407 FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
3408 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
3409 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
3410 msdu0->rx_msdu_info.info0 = msdu_info;
3411
3412 /* change msdu len in hal rx desc */
3413 ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3414
3415 paddr = dma_map_single(ab->dev, defrag_skb->data,
3416 defrag_skb->len + skb_tailroom(defrag_skb),
3417 DMA_TO_DEVICE);
3418 if (dma_mapping_error(ab->dev, paddr))
3419 return -ENOMEM;
3420
3421 spin_lock_bh(&rx_refill_ring->idr_lock);
3422 buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
3423 rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
3424 spin_unlock_bh(&rx_refill_ring->idr_lock);
3425 if (buf_id < 0) {
3426 ret = -ENOMEM;
3427 goto err_unmap_dma;
3428 }
3429
3430 ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
3431 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
3432 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3433
3434 ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie,
3435 ab->hw_params.hal_params->rx_buf_rbm);
3436
3437 /* Fill mpdu details into reo entrance ring */
3438 srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
3439
3440 spin_lock_bh(&srng->lock);
3441 ath11k_hal_srng_access_begin(ab, srng);
3442
3443 reo_ent_ring = (struct hal_reo_entrance_ring *)
3444 ath11k_hal_srng_src_get_next_entry(ab, srng);
3445 if (!reo_ent_ring) {
3446 ath11k_hal_srng_access_end(ab, srng);
3447 spin_unlock_bh(&srng->lock);
3448 ret = -ENOSPC;
3449 goto err_free_idr;
3450 }
3451 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3452
3453 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3454 ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
3455 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
3456
3457 mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
3458 FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
3459 FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
3460 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
3461 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
3462 FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
3463 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
3464
3465 reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
3466 reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
3467 reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
3468 reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
3469 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
3470 reo_dest_ring->info0)) |
3471 FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
3472 ath11k_hal_srng_access_end(ab, srng);
3473 spin_unlock_bh(&srng->lock);
3474
3475 return 0;
3476
3477 err_free_idr:
3478 spin_lock_bh(&rx_refill_ring->idr_lock);
3479 idr_remove(&rx_refill_ring->bufs_idr, buf_id);
3480 spin_unlock_bh(&rx_refill_ring->idr_lock);
3481 err_unmap_dma:
3482 dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3483 DMA_TO_DEVICE);
3484 return ret;
3485 }
3486
ath11k_dp_rx_h_cmp_frags(struct ath11k * ar,struct sk_buff * a,struct sk_buff * b)3487 static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar,
3488 struct sk_buff *a, struct sk_buff *b)
3489 {
3490 int frag1, frag2;
3491
3492 frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a);
3493 frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b);
3494
3495 return frag1 - frag2;
3496 }
3497
ath11k_dp_rx_h_sort_frags(struct ath11k * ar,struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3498 static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar,
3499 struct sk_buff_head *frag_list,
3500 struct sk_buff *cur_frag)
3501 {
3502 struct sk_buff *skb;
3503 int cmp;
3504
3505 skb_queue_walk(frag_list, skb) {
3506 cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag);
3507 if (cmp < 0)
3508 continue;
3509 __skb_queue_before(frag_list, skb, cur_frag);
3510 return;
3511 }
3512 __skb_queue_tail(frag_list, cur_frag);
3513 }
3514
ath11k_dp_rx_h_get_pn(struct ath11k * ar,struct sk_buff * skb)3515 static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb)
3516 {
3517 struct ieee80211_hdr *hdr;
3518 u64 pn = 0;
3519 u8 *ehdr;
3520 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3521
3522 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3523 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3524
3525 pn = ehdr[0];
3526 pn |= (u64)ehdr[1] << 8;
3527 pn |= (u64)ehdr[4] << 16;
3528 pn |= (u64)ehdr[5] << 24;
3529 pn |= (u64)ehdr[6] << 32;
3530 pn |= (u64)ehdr[7] << 40;
3531
3532 return pn;
3533 }
3534
3535 static bool
ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k * ar,struct dp_rx_tid * rx_tid)3536 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
3537 {
3538 enum hal_encrypt_type encrypt_type;
3539 struct sk_buff *first_frag, *skb;
3540 struct hal_rx_desc *desc;
3541 u64 last_pn;
3542 u64 cur_pn;
3543
3544 first_frag = skb_peek(&rx_tid->rx_frags);
3545 desc = (struct hal_rx_desc *)first_frag->data;
3546
3547 encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc);
3548 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3549 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3550 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3551 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3552 return true;
3553
3554 last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag);
3555 skb_queue_walk(&rx_tid->rx_frags, skb) {
3556 if (skb == first_frag)
3557 continue;
3558
3559 cur_pn = ath11k_dp_rx_h_get_pn(ar, skb);
3560 if (cur_pn != last_pn + 1)
3561 return false;
3562 last_pn = cur_pn;
3563 }
3564 return true;
3565 }
3566
ath11k_dp_rx_frag_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,u32 * ring_desc)3567 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
3568 struct sk_buff *msdu,
3569 u32 *ring_desc)
3570 {
3571 struct ath11k_base *ab = ar->ab;
3572 struct hal_rx_desc *rx_desc;
3573 struct ath11k_peer *peer;
3574 struct dp_rx_tid *rx_tid;
3575 struct sk_buff *defrag_skb = NULL;
3576 u32 peer_id;
3577 u16 seqno, frag_no;
3578 u8 tid;
3579 int ret = 0;
3580 bool more_frags;
3581 bool is_mcbc;
3582
3583 rx_desc = (struct hal_rx_desc *)msdu->data;
3584 peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
3585 tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc);
3586 seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
3587 frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu);
3588 more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu);
3589 is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
3590
3591 /* Multicast/Broadcast fragments are not expected */
3592 if (is_mcbc)
3593 return -EINVAL;
3594
3595 if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) ||
3596 !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) ||
3597 tid > IEEE80211_NUM_TIDS)
3598 return -EINVAL;
3599
3600 /* received unfragmented packet in reo
3601 * exception ring, this shouldn't happen
3602 * as these packets typically come from
3603 * reo2sw srngs.
3604 */
3605 if (WARN_ON_ONCE(!frag_no && !more_frags))
3606 return -EINVAL;
3607
3608 spin_lock_bh(&ab->base_lock);
3609 peer = ath11k_peer_find_by_id(ab, peer_id);
3610 if (!peer) {
3611 ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3612 peer_id);
3613 ret = -ENOENT;
3614 goto out_unlock;
3615 }
3616 if (!peer->dp_setup_done) {
3617 ath11k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n",
3618 peer->addr, peer_id);
3619 ret = -ENOENT;
3620 goto out_unlock;
3621 }
3622
3623 rx_tid = &peer->rx_tid[tid];
3624
3625 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3626 skb_queue_empty(&rx_tid->rx_frags)) {
3627 /* Flush stored fragments and start a new sequence */
3628 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3629 rx_tid->cur_sn = seqno;
3630 }
3631
3632 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3633 /* Fragment already present */
3634 ret = -EINVAL;
3635 goto out_unlock;
3636 }
3637
3638 if (!rx_tid->rx_frag_bitmap || (frag_no > __fls(rx_tid->rx_frag_bitmap)))
3639 __skb_queue_tail(&rx_tid->rx_frags, msdu);
3640 else
3641 ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu);
3642
3643 rx_tid->rx_frag_bitmap |= BIT(frag_no);
3644 if (!more_frags)
3645 rx_tid->last_frag_no = frag_no;
3646
3647 if (frag_no == 0) {
3648 rx_tid->dst_ring_desc = kmemdup(ring_desc,
3649 sizeof(*rx_tid->dst_ring_desc),
3650 GFP_ATOMIC);
3651 if (!rx_tid->dst_ring_desc) {
3652 ret = -ENOMEM;
3653 goto out_unlock;
3654 }
3655 } else {
3656 ath11k_dp_rx_link_desc_return(ab, ring_desc,
3657 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3658 }
3659
3660 if (!rx_tid->last_frag_no ||
3661 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3662 mod_timer(&rx_tid->frag_timer, jiffies +
3663 ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
3664 goto out_unlock;
3665 }
3666
3667 spin_unlock_bh(&ab->base_lock);
3668 timer_delete_sync(&rx_tid->frag_timer);
3669 spin_lock_bh(&ab->base_lock);
3670
3671 peer = ath11k_peer_find_by_id(ab, peer_id);
3672 if (!peer)
3673 goto err_frags_cleanup;
3674
3675 if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3676 goto err_frags_cleanup;
3677
3678 if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3679 goto err_frags_cleanup;
3680
3681 if (!defrag_skb)
3682 goto err_frags_cleanup;
3683
3684 if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3685 goto err_frags_cleanup;
3686
3687 ath11k_dp_rx_frags_cleanup(rx_tid, false);
3688 goto out_unlock;
3689
3690 err_frags_cleanup:
3691 dev_kfree_skb_any(defrag_skb);
3692 ath11k_dp_rx_frags_cleanup(rx_tid, true);
3693 out_unlock:
3694 spin_unlock_bh(&ab->base_lock);
3695 return ret;
3696 }
3697
3698 static int
ath11k_dp_process_rx_err_buf(struct ath11k * ar,u32 * ring_desc,int buf_id,bool drop)3699 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
3700 {
3701 struct ath11k_pdev_dp *dp = &ar->dp;
3702 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
3703 struct sk_buff *msdu;
3704 struct ath11k_skb_rxcb *rxcb;
3705 struct hal_rx_desc *rx_desc;
3706 u8 *hdr_status;
3707 u16 msdu_len;
3708 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3709
3710 spin_lock_bh(&rx_ring->idr_lock);
3711 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3712 if (!msdu) {
3713 ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
3714 buf_id);
3715 spin_unlock_bh(&rx_ring->idr_lock);
3716 return -EINVAL;
3717 }
3718
3719 idr_remove(&rx_ring->bufs_idr, buf_id);
3720 spin_unlock_bh(&rx_ring->idr_lock);
3721
3722 rxcb = ATH11K_SKB_RXCB(msdu);
3723 dma_unmap_single(ar->ab->dev, rxcb->paddr,
3724 msdu->len + skb_tailroom(msdu),
3725 DMA_FROM_DEVICE);
3726
3727 if (drop) {
3728 dev_kfree_skb_any(msdu);
3729 return 0;
3730 }
3731
3732 rcu_read_lock();
3733 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3734 dev_kfree_skb_any(msdu);
3735 goto exit;
3736 }
3737
3738 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
3739 dev_kfree_skb_any(msdu);
3740 goto exit;
3741 }
3742
3743 rx_desc = (struct hal_rx_desc *)msdu->data;
3744 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc);
3745 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3746 hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
3747 ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3748 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
3749 sizeof(struct ieee80211_hdr));
3750 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
3751 sizeof(struct hal_rx_desc));
3752 dev_kfree_skb_any(msdu);
3753 goto exit;
3754 }
3755
3756 skb_put(msdu, hal_rx_desc_sz + msdu_len);
3757
3758 if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
3759 dev_kfree_skb_any(msdu);
3760 ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
3761 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3762 }
3763 exit:
3764 rcu_read_unlock();
3765 return 0;
3766 }
3767
ath11k_dp_process_rx_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3768 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
3769 int budget)
3770 {
3771 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3772 struct dp_link_desc_bank *link_desc_banks;
3773 enum hal_rx_buf_return_buf_manager rbm;
3774 int tot_n_bufs_reaped, quota, ret, i;
3775 int n_bufs_reaped[MAX_RADIOS] = {};
3776 struct dp_rxdma_ring *rx_ring;
3777 struct dp_srng *reo_except;
3778 u32 desc_bank, num_msdus;
3779 struct hal_srng *srng;
3780 struct ath11k_dp *dp;
3781 void *link_desc_va;
3782 int buf_id, mac_id;
3783 struct ath11k *ar;
3784 dma_addr_t paddr;
3785 u32 *desc;
3786 bool is_frag;
3787 u8 drop = 0;
3788
3789 tot_n_bufs_reaped = 0;
3790 quota = budget;
3791
3792 dp = &ab->dp;
3793 reo_except = &dp->reo_except_ring;
3794 link_desc_banks = dp->link_desc_banks;
3795
3796 srng = &ab->hal.srng_list[reo_except->ring_id];
3797
3798 spin_lock_bh(&srng->lock);
3799
3800 ath11k_hal_srng_access_begin(ab, srng);
3801
3802 while (budget &&
3803 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
3804 struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
3805
3806 ab->soc_stats.err_ring_pkts++;
3807 ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
3808 &desc_bank);
3809 if (ret) {
3810 ath11k_warn(ab, "failed to parse error reo desc %d\n",
3811 ret);
3812 continue;
3813 }
3814 link_desc_va = link_desc_banks[desc_bank].vaddr +
3815 (paddr - link_desc_banks[desc_bank].paddr);
3816 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3817 &rbm);
3818 if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
3819 rbm != HAL_RX_BUF_RBM_SW1_BM &&
3820 rbm != HAL_RX_BUF_RBM_SW3_BM) {
3821 ab->soc_stats.invalid_rbm++;
3822 ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
3823 ath11k_dp_rx_link_desc_return(ab, desc,
3824 HAL_WBM_REL_BM_ACT_REL_MSDU);
3825 continue;
3826 }
3827
3828 is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
3829
3830 /* Process only rx fragments with one msdu per link desc below, and drop
3831 * msdu's indicated due to error reasons.
3832 */
3833 if (!is_frag || num_msdus > 1) {
3834 drop = 1;
3835 /* Return the link desc back to wbm idle list */
3836 ath11k_dp_rx_link_desc_return(ab, desc,
3837 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3838 }
3839
3840 for (i = 0; i < num_msdus; i++) {
3841 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
3842 msdu_cookies[i]);
3843
3844 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
3845 msdu_cookies[i]);
3846
3847 ar = ab->pdevs[mac_id].ar;
3848
3849 if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
3850 n_bufs_reaped[mac_id]++;
3851 tot_n_bufs_reaped++;
3852 }
3853 }
3854
3855 if (tot_n_bufs_reaped >= quota) {
3856 tot_n_bufs_reaped = quota;
3857 goto exit;
3858 }
3859
3860 budget = quota - tot_n_bufs_reaped;
3861 }
3862
3863 exit:
3864 ath11k_hal_srng_access_end(ab, srng);
3865
3866 spin_unlock_bh(&srng->lock);
3867
3868 for (i = 0; i < ab->num_radios; i++) {
3869 if (!n_bufs_reaped[i])
3870 continue;
3871
3872 ar = ab->pdevs[i].ar;
3873 rx_ring = &ar->dp.rx_refill_buf_ring;
3874
3875 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
3876 ab->hw_params.hal_params->rx_buf_rbm);
3877 }
3878
3879 return tot_n_bufs_reaped;
3880 }
3881
ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k * ar,int msdu_len,struct sk_buff_head * msdu_list)3882 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
3883 int msdu_len,
3884 struct sk_buff_head *msdu_list)
3885 {
3886 struct sk_buff *skb, *tmp;
3887 struct ath11k_skb_rxcb *rxcb;
3888 int n_buffs;
3889
3890 n_buffs = DIV_ROUND_UP(msdu_len,
3891 (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz));
3892
3893 skb_queue_walk_safe(msdu_list, skb, tmp) {
3894 rxcb = ATH11K_SKB_RXCB(skb);
3895 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3896 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3897 if (!n_buffs)
3898 break;
3899 __skb_unlink(skb, msdu_list);
3900 dev_kfree_skb_any(skb);
3901 n_buffs--;
3902 }
3903 }
3904 }
3905
ath11k_dp_rx_h_null_q_desc(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3906 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
3907 struct ieee80211_rx_status *status,
3908 struct sk_buff_head *msdu_list)
3909 {
3910 u16 msdu_len;
3911 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3912 struct rx_attention *rx_attention;
3913 u8 l3pad_bytes;
3914 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3915 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3916
3917 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
3918
3919 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
3920 /* First buffer will be freed by the caller, so deduct it's length */
3921 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
3922 ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3923 return -EINVAL;
3924 }
3925
3926 rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc);
3927 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
3928 ath11k_warn(ar->ab,
3929 "msdu_done bit not set in null_q_des processing\n");
3930 __skb_queue_purge(msdu_list);
3931 return -EIO;
3932 }
3933
3934 /* Handle NULL queue descriptor violations arising out a missing
3935 * REO queue for a given peer or a given TID. This typically
3936 * may happen if a packet is received on a QOS enabled TID before the
3937 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3938 * it may also happen for MC/BC frames if they are not routed to the
3939 * non-QOS TID queue, in the absence of any other default TID queue.
3940 * This error can show up both in a REO destination or WBM release ring.
3941 */
3942
3943 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
3944 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
3945
3946 if (rxcb->is_frag) {
3947 skb_pull(msdu, hal_rx_desc_sz);
3948 } else {
3949 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
3950
3951 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
3952 return -EINVAL;
3953
3954 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3955 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3956 }
3957 ath11k_dp_rx_h_ppdu(ar, desc, status);
3958
3959 ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
3960
3961 rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc);
3962
3963 /* Please note that caller will having the access to msdu and completing
3964 * rx with mac80211. Need not worry about cleaning up amsdu_list.
3965 */
3966
3967 return 0;
3968 }
3969
ath11k_dp_rx_h_reo_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3970 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
3971 struct ieee80211_rx_status *status,
3972 struct sk_buff_head *msdu_list)
3973 {
3974 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3975 bool drop = false;
3976
3977 ar->ab->soc_stats.reo_error[rxcb->err_code]++;
3978
3979 switch (rxcb->err_code) {
3980 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
3981 if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
3982 drop = true;
3983 break;
3984 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
3985 /* TODO: Do not drop PN failed packets in the driver;
3986 * instead, it is good to drop such packets in mac80211
3987 * after incrementing the replay counters.
3988 */
3989 fallthrough;
3990 default:
3991 /* TODO: Review other errors and process them to mac80211
3992 * as appropriate.
3993 */
3994 drop = true;
3995 break;
3996 }
3997
3998 return drop;
3999 }
4000
ath11k_dp_rx_h_tkip_mic_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4001 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
4002 struct ieee80211_rx_status *status)
4003 {
4004 u16 msdu_len;
4005 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
4006 u8 l3pad_bytes;
4007 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4008 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
4009
4010 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
4011 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
4012
4013 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
4014 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
4015 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
4016 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
4017
4018 ath11k_dp_rx_h_ppdu(ar, desc, status);
4019
4020 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
4021 RX_FLAG_DECRYPTED);
4022
4023 ath11k_dp_rx_h_undecap(ar, msdu, desc,
4024 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
4025 }
4026
ath11k_dp_rx_h_rxdma_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)4027 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu,
4028 struct ieee80211_rx_status *status)
4029 {
4030 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4031 bool drop = false;
4032
4033 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
4034
4035 switch (rxcb->err_code) {
4036 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
4037 ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
4038 break;
4039 default:
4040 /* TODO: Review other rxdma error code to check if anything is
4041 * worth reporting to mac80211
4042 */
4043 drop = true;
4044 break;
4045 }
4046
4047 return drop;
4048 }
4049
ath11k_dp_rx_wbm_err(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)4050 static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
4051 struct napi_struct *napi,
4052 struct sk_buff *msdu,
4053 struct sk_buff_head *msdu_list)
4054 {
4055 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4056 struct ieee80211_rx_status rxs = {};
4057 bool drop = true;
4058
4059 switch (rxcb->err_rel_src) {
4060 case HAL_WBM_REL_SRC_MODULE_REO:
4061 drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
4062 break;
4063 case HAL_WBM_REL_SRC_MODULE_RXDMA:
4064 drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
4065 break;
4066 default:
4067 /* msdu will get freed */
4068 break;
4069 }
4070
4071 if (drop) {
4072 dev_kfree_skb_any(msdu);
4073 return;
4074 }
4075
4076 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
4077 }
4078
ath11k_dp_rx_process_wbm_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)4079 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
4080 struct napi_struct *napi, int budget)
4081 {
4082 struct ath11k *ar;
4083 struct ath11k_dp *dp = &ab->dp;
4084 struct dp_rxdma_ring *rx_ring;
4085 struct hal_rx_wbm_rel_info err_info;
4086 struct hal_srng *srng;
4087 struct sk_buff *msdu;
4088 struct sk_buff_head msdu_list[MAX_RADIOS];
4089 struct ath11k_skb_rxcb *rxcb;
4090 u32 *rx_desc;
4091 int buf_id, mac_id;
4092 int num_buffs_reaped[MAX_RADIOS] = {};
4093 int total_num_buffs_reaped = 0;
4094 int ret, i;
4095
4096 for (i = 0; i < ab->num_radios; i++)
4097 __skb_queue_head_init(&msdu_list[i]);
4098
4099 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
4100
4101 spin_lock_bh(&srng->lock);
4102
4103 ath11k_hal_srng_access_begin(ab, srng);
4104
4105 while (budget) {
4106 rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
4107 if (!rx_desc)
4108 break;
4109
4110 ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
4111 if (ret) {
4112 ath11k_warn(ab,
4113 "failed to parse rx error in wbm_rel ring desc %d\n",
4114 ret);
4115 continue;
4116 }
4117
4118 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
4119 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
4120
4121 ar = ab->pdevs[mac_id].ar;
4122 rx_ring = &ar->dp.rx_refill_buf_ring;
4123
4124 spin_lock_bh(&rx_ring->idr_lock);
4125 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4126 if (!msdu) {
4127 ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
4128 buf_id, mac_id);
4129 spin_unlock_bh(&rx_ring->idr_lock);
4130 continue;
4131 }
4132
4133 idr_remove(&rx_ring->bufs_idr, buf_id);
4134 spin_unlock_bh(&rx_ring->idr_lock);
4135
4136 rxcb = ATH11K_SKB_RXCB(msdu);
4137 dma_unmap_single(ab->dev, rxcb->paddr,
4138 msdu->len + skb_tailroom(msdu),
4139 DMA_FROM_DEVICE);
4140
4141 num_buffs_reaped[mac_id]++;
4142 total_num_buffs_reaped++;
4143 budget--;
4144
4145 if (err_info.push_reason !=
4146 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4147 dev_kfree_skb_any(msdu);
4148 continue;
4149 }
4150
4151 rxcb->err_rel_src = err_info.err_rel_src;
4152 rxcb->err_code = err_info.err_code;
4153 rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
4154 __skb_queue_tail(&msdu_list[mac_id], msdu);
4155 }
4156
4157 ath11k_hal_srng_access_end(ab, srng);
4158
4159 spin_unlock_bh(&srng->lock);
4160
4161 if (!total_num_buffs_reaped)
4162 goto done;
4163
4164 for (i = 0; i < ab->num_radios; i++) {
4165 if (!num_buffs_reaped[i])
4166 continue;
4167
4168 ar = ab->pdevs[i].ar;
4169 rx_ring = &ar->dp.rx_refill_buf_ring;
4170
4171 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
4172 ab->hw_params.hal_params->rx_buf_rbm);
4173 }
4174
4175 rcu_read_lock();
4176 for (i = 0; i < ab->num_radios; i++) {
4177 if (!rcu_dereference(ab->pdevs_active[i])) {
4178 __skb_queue_purge(&msdu_list[i]);
4179 continue;
4180 }
4181
4182 ar = ab->pdevs[i].ar;
4183
4184 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
4185 __skb_queue_purge(&msdu_list[i]);
4186 continue;
4187 }
4188
4189 while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
4190 ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
4191 }
4192 rcu_read_unlock();
4193 done:
4194 return total_num_buffs_reaped;
4195 }
4196
ath11k_dp_process_rxdma_err(struct ath11k_base * ab,int mac_id,int budget)4197 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
4198 {
4199 struct ath11k *ar;
4200 struct dp_srng *err_ring;
4201 struct dp_rxdma_ring *rx_ring;
4202 struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
4203 struct hal_srng *srng;
4204 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
4205 enum hal_rx_buf_return_buf_manager rbm;
4206 enum hal_reo_entr_rxdma_ecode rxdma_err_code;
4207 struct ath11k_skb_rxcb *rxcb;
4208 struct sk_buff *skb;
4209 struct hal_reo_entrance_ring *entr_ring;
4210 void *desc;
4211 int num_buf_freed = 0;
4212 int quota = budget;
4213 dma_addr_t paddr;
4214 u32 desc_bank;
4215 void *link_desc_va;
4216 int num_msdus;
4217 int i;
4218 int buf_id;
4219
4220 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
4221 err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
4222 mac_id)];
4223 rx_ring = &ar->dp.rx_refill_buf_ring;
4224
4225 srng = &ab->hal.srng_list[err_ring->ring_id];
4226
4227 spin_lock_bh(&srng->lock);
4228
4229 ath11k_hal_srng_access_begin(ab, srng);
4230
4231 while (quota-- &&
4232 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4233 ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
4234
4235 entr_ring = (struct hal_reo_entrance_ring *)desc;
4236 rxdma_err_code =
4237 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4238 entr_ring->info1);
4239 ab->soc_stats.rxdma_error[rxdma_err_code]++;
4240
4241 link_desc_va = link_desc_banks[desc_bank].vaddr +
4242 (paddr - link_desc_banks[desc_bank].paddr);
4243 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
4244 msdu_cookies, &rbm);
4245
4246 for (i = 0; i < num_msdus; i++) {
4247 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4248 msdu_cookies[i]);
4249
4250 spin_lock_bh(&rx_ring->idr_lock);
4251 skb = idr_find(&rx_ring->bufs_idr, buf_id);
4252 if (!skb) {
4253 ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
4254 buf_id);
4255 spin_unlock_bh(&rx_ring->idr_lock);
4256 continue;
4257 }
4258
4259 idr_remove(&rx_ring->bufs_idr, buf_id);
4260 spin_unlock_bh(&rx_ring->idr_lock);
4261
4262 rxcb = ATH11K_SKB_RXCB(skb);
4263 dma_unmap_single(ab->dev, rxcb->paddr,
4264 skb->len + skb_tailroom(skb),
4265 DMA_FROM_DEVICE);
4266 dev_kfree_skb_any(skb);
4267
4268 num_buf_freed++;
4269 }
4270
4271 ath11k_dp_rx_link_desc_return(ab, desc,
4272 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4273 }
4274
4275 ath11k_hal_srng_access_end(ab, srng);
4276
4277 spin_unlock_bh(&srng->lock);
4278
4279 if (num_buf_freed)
4280 ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
4281 ab->hw_params.hal_params->rx_buf_rbm);
4282
4283 return budget - quota;
4284 }
4285
ath11k_dp_process_reo_status(struct ath11k_base * ab)4286 void ath11k_dp_process_reo_status(struct ath11k_base *ab)
4287 {
4288 struct ath11k_dp *dp = &ab->dp;
4289 struct hal_srng *srng;
4290 struct dp_reo_cmd *cmd, *tmp;
4291 bool found = false;
4292 u32 *reo_desc;
4293 u16 tag;
4294 struct hal_reo_status reo_status;
4295
4296 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4297
4298 memset(&reo_status, 0, sizeof(reo_status));
4299
4300 spin_lock_bh(&srng->lock);
4301
4302 ath11k_hal_srng_access_begin(ab, srng);
4303
4304 while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4305 tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
4306
4307 switch (tag) {
4308 case HAL_REO_GET_QUEUE_STATS_STATUS:
4309 ath11k_hal_reo_status_queue_stats(ab, reo_desc,
4310 &reo_status);
4311 break;
4312 case HAL_REO_FLUSH_QUEUE_STATUS:
4313 ath11k_hal_reo_flush_queue_status(ab, reo_desc,
4314 &reo_status);
4315 break;
4316 case HAL_REO_FLUSH_CACHE_STATUS:
4317 ath11k_hal_reo_flush_cache_status(ab, reo_desc,
4318 &reo_status);
4319 break;
4320 case HAL_REO_UNBLOCK_CACHE_STATUS:
4321 ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
4322 &reo_status);
4323 break;
4324 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4325 ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
4326 &reo_status);
4327 break;
4328 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4329 ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
4330 &reo_status);
4331 break;
4332 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4333 ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
4334 &reo_status);
4335 break;
4336 default:
4337 ath11k_warn(ab, "Unknown reo status type %d\n", tag);
4338 continue;
4339 }
4340
4341 spin_lock_bh(&dp->reo_cmd_lock);
4342 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4343 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4344 found = true;
4345 list_del(&cmd->list);
4346 break;
4347 }
4348 }
4349 spin_unlock_bh(&dp->reo_cmd_lock);
4350
4351 if (found) {
4352 cmd->handler(dp, (void *)&cmd->data,
4353 reo_status.uniform_hdr.cmd_status);
4354 kfree(cmd);
4355 }
4356
4357 found = false;
4358 }
4359
4360 ath11k_hal_srng_access_end(ab, srng);
4361
4362 spin_unlock_bh(&srng->lock);
4363 }
4364
ath11k_dp_rx_pdev_free(struct ath11k_base * ab,int mac_id)4365 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
4366 {
4367 struct ath11k *ar = ab->pdevs[mac_id].ar;
4368
4369 ath11k_dp_rx_pdev_srng_free(ar);
4370 ath11k_dp_rxdma_pdev_buf_free(ar);
4371 }
4372
ath11k_dp_rx_pdev_alloc(struct ath11k_base * ab,int mac_id)4373 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
4374 {
4375 struct ath11k *ar = ab->pdevs[mac_id].ar;
4376 struct ath11k_pdev_dp *dp = &ar->dp;
4377 u32 ring_id;
4378 int i;
4379 int ret;
4380
4381 ret = ath11k_dp_rx_pdev_srng_alloc(ar);
4382 if (ret) {
4383 ath11k_warn(ab, "failed to setup rx srngs\n");
4384 return ret;
4385 }
4386
4387 ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
4388 if (ret) {
4389 ath11k_warn(ab, "failed to setup rxdma ring\n");
4390 return ret;
4391 }
4392
4393 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4394 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
4395 if (ret) {
4396 ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4397 ret);
4398 return ret;
4399 }
4400
4401 if (ab->hw_params.rx_mac_buf_ring) {
4402 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4403 ring_id = dp->rx_mac_buf_ring[i].ring_id;
4404 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4405 mac_id + i, HAL_RXDMA_BUF);
4406 if (ret) {
4407 ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4408 i, ret);
4409 return ret;
4410 }
4411 }
4412 }
4413
4414 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4415 ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4416 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4417 mac_id + i, HAL_RXDMA_DST);
4418 if (ret) {
4419 ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4420 i, ret);
4421 return ret;
4422 }
4423 }
4424
4425 if (!ab->hw_params.rxdma1_enable)
4426 goto config_refill_ring;
4427
4428 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4429 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4430 mac_id, HAL_RXDMA_MONITOR_BUF);
4431 if (ret) {
4432 ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4433 ret);
4434 return ret;
4435 }
4436 ret = ath11k_dp_tx_htt_srng_setup(ab,
4437 dp->rxdma_mon_dst_ring.ring_id,
4438 mac_id, HAL_RXDMA_MONITOR_DST);
4439 if (ret) {
4440 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4441 ret);
4442 return ret;
4443 }
4444 ret = ath11k_dp_tx_htt_srng_setup(ab,
4445 dp->rxdma_mon_desc_ring.ring_id,
4446 mac_id, HAL_RXDMA_MONITOR_DESC);
4447 if (ret) {
4448 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4449 ret);
4450 return ret;
4451 }
4452
4453 config_refill_ring:
4454 for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
4455 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
4456 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
4457 HAL_RXDMA_MONITOR_STATUS);
4458 if (ret) {
4459 ath11k_warn(ab,
4460 "failed to configure mon_status_refill_ring%d %d\n",
4461 i, ret);
4462 return ret;
4463 }
4464 }
4465
4466 return 0;
4467 }
4468
ath11k_dp_mon_set_frag_len(u32 * total_len,u32 * frag_len)4469 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
4470 {
4471 if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
4472 *frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
4473 *total_len -= *frag_len;
4474 } else {
4475 *frag_len = *total_len;
4476 *total_len = 0;
4477 }
4478 }
4479
4480 static
ath11k_dp_rx_monitor_link_desc_return(struct ath11k * ar,void * p_last_buf_addr_info,u8 mac_id)4481 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
4482 void *p_last_buf_addr_info,
4483 u8 mac_id)
4484 {
4485 struct ath11k_pdev_dp *dp = &ar->dp;
4486 struct dp_srng *dp_srng;
4487 void *hal_srng;
4488 void *src_srng_desc;
4489 int ret = 0;
4490
4491 if (ar->ab->hw_params.rxdma1_enable) {
4492 dp_srng = &dp->rxdma_mon_desc_ring;
4493 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4494 } else {
4495 dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
4496 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4497 }
4498
4499 ath11k_hal_srng_access_begin(ar->ab, hal_srng);
4500
4501 src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
4502
4503 if (src_srng_desc) {
4504 struct ath11k_buffer_addr *src_desc = src_srng_desc;
4505
4506 *src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
4507 } else {
4508 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4509 "Monitor Link Desc Ring %d Full", mac_id);
4510 ret = -ENOMEM;
4511 }
4512
4513 ath11k_hal_srng_access_end(ar->ab, hal_srng);
4514 return ret;
4515 }
4516
4517 static
ath11k_dp_rx_mon_next_link_desc_get(void * rx_msdu_link_desc,dma_addr_t * paddr,u32 * sw_cookie,u8 * rbm,void ** pp_buf_addr_info)4518 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
4519 dma_addr_t *paddr, u32 *sw_cookie,
4520 u8 *rbm,
4521 void **pp_buf_addr_info)
4522 {
4523 struct hal_rx_msdu_link *msdu_link = rx_msdu_link_desc;
4524 struct ath11k_buffer_addr *buf_addr_info;
4525
4526 buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
4527
4528 ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
4529
4530 *pp_buf_addr_info = (void *)buf_addr_info;
4531 }
4532
ath11k_dp_pkt_set_pktlen(struct sk_buff * skb,u32 len)4533 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
4534 {
4535 if (skb->len > len) {
4536 skb_trim(skb, len);
4537 } else {
4538 if (skb_tailroom(skb) < len - skb->len) {
4539 if ((pskb_expand_head(skb, 0,
4540 len - skb->len - skb_tailroom(skb),
4541 GFP_ATOMIC))) {
4542 dev_kfree_skb_any(skb);
4543 return -ENOMEM;
4544 }
4545 }
4546 skb_put(skb, (len - skb->len));
4547 }
4548 return 0;
4549 }
4550
ath11k_hal_rx_msdu_list_get(struct ath11k * ar,void * msdu_link_desc,struct hal_rx_msdu_list * msdu_list,u16 * num_msdus)4551 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
4552 void *msdu_link_desc,
4553 struct hal_rx_msdu_list *msdu_list,
4554 u16 *num_msdus)
4555 {
4556 struct hal_rx_msdu_details *msdu_details = NULL;
4557 struct rx_msdu_desc *msdu_desc_info = NULL;
4558 struct hal_rx_msdu_link *msdu_link = NULL;
4559 int i;
4560 u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
4561 u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
4562 u8 tmp = 0;
4563
4564 msdu_link = msdu_link_desc;
4565 msdu_details = &msdu_link->msdu_link[0];
4566
4567 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
4568 if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4569 msdu_details[i].buf_addr_info.info0) == 0) {
4570 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
4571 msdu_desc_info->info0 |= last;
4572 break;
4573 }
4574 msdu_desc_info = &msdu_details[i].rx_msdu_info;
4575
4576 if (!i)
4577 msdu_desc_info->info0 |= first;
4578 else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
4579 msdu_desc_info->info0 |= last;
4580 msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
4581 msdu_list->msdu_info[i].msdu_len =
4582 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
4583 msdu_list->sw_cookie[i] =
4584 FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
4585 msdu_details[i].buf_addr_info.info1);
4586 tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
4587 msdu_details[i].buf_addr_info.info1);
4588 msdu_list->rbm[i] = tmp;
4589 }
4590 *num_msdus = i;
4591 }
4592
ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id,u32 * ppdu_id,u32 * rx_bufs_used)4593 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
4594 u32 *rx_bufs_used)
4595 {
4596 u32 ret = 0;
4597
4598 if ((*ppdu_id < msdu_ppdu_id) &&
4599 ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
4600 *ppdu_id = msdu_ppdu_id;
4601 ret = msdu_ppdu_id;
4602 } else if ((*ppdu_id > msdu_ppdu_id) &&
4603 ((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
4604 /* mon_dst is behind than mon_status
4605 * skip dst_ring and free it
4606 */
4607 *rx_bufs_used += 1;
4608 *ppdu_id = msdu_ppdu_id;
4609 ret = msdu_ppdu_id;
4610 }
4611 return ret;
4612 }
4613
ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info * info,bool * is_frag,u32 * total_len,u32 * frag_len,u32 * msdu_cnt)4614 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
4615 bool *is_frag, u32 *total_len,
4616 u32 *frag_len, u32 *msdu_cnt)
4617 {
4618 if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
4619 if (!*is_frag) {
4620 *total_len = info->msdu_len;
4621 *is_frag = true;
4622 }
4623 ath11k_dp_mon_set_frag_len(total_len,
4624 frag_len);
4625 } else {
4626 if (*is_frag) {
4627 ath11k_dp_mon_set_frag_len(total_len,
4628 frag_len);
4629 } else {
4630 *frag_len = info->msdu_len;
4631 }
4632 *is_frag = false;
4633 *msdu_cnt -= 1;
4634 }
4635 }
4636
4637 /* clang stack usage explodes if this is inlined */
4638 static noinline_for_stack
ath11k_dp_rx_mon_mpdu_pop(struct ath11k * ar,int mac_id,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,u32 * npackets,u32 * ppdu_id)4639 u32 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
4640 void *ring_entry, struct sk_buff **head_msdu,
4641 struct sk_buff **tail_msdu, u32 *npackets,
4642 u32 *ppdu_id)
4643 {
4644 struct ath11k_pdev_dp *dp = &ar->dp;
4645 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4646 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
4647 struct sk_buff *msdu = NULL, *last = NULL;
4648 struct hal_rx_msdu_list msdu_list;
4649 void *p_buf_addr_info, *p_last_buf_addr_info;
4650 struct hal_rx_desc *rx_desc;
4651 void *rx_msdu_link_desc;
4652 dma_addr_t paddr;
4653 u16 num_msdus = 0;
4654 u32 rx_buf_size, rx_pkt_offset, sw_cookie;
4655 u32 rx_bufs_used = 0, i = 0;
4656 u32 msdu_ppdu_id = 0, msdu_cnt = 0;
4657 u32 total_len = 0, frag_len = 0;
4658 bool is_frag, is_first_msdu;
4659 bool drop_mpdu = false;
4660 struct ath11k_skb_rxcb *rxcb;
4661 struct hal_reo_entrance_ring *ent_desc = ring_entry;
4662 int buf_id;
4663 u32 rx_link_buf_info[2];
4664 u8 rbm;
4665
4666 if (!ar->ab->hw_params.rxdma1_enable)
4667 rx_ring = &dp->rx_refill_buf_ring;
4668
4669 ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
4670 &sw_cookie,
4671 &p_last_buf_addr_info, &rbm,
4672 &msdu_cnt);
4673
4674 if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
4675 ent_desc->info1) ==
4676 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4677 u8 rxdma_err =
4678 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4679 ent_desc->info1);
4680 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
4681 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
4682 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
4683 drop_mpdu = true;
4684 pmon->rx_mon_stats.dest_mpdu_drop++;
4685 }
4686 }
4687
4688 is_frag = false;
4689 is_first_msdu = true;
4690
4691 do {
4692 if (pmon->mon_last_linkdesc_paddr == paddr) {
4693 pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
4694 return rx_bufs_used;
4695 }
4696
4697 if (ar->ab->hw_params.rxdma1_enable)
4698 rx_msdu_link_desc =
4699 (void *)pmon->link_desc_banks[sw_cookie].vaddr +
4700 (paddr - pmon->link_desc_banks[sw_cookie].paddr);
4701 else
4702 rx_msdu_link_desc =
4703 (void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4704 (paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
4705
4706 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
4707 &num_msdus);
4708
4709 for (i = 0; i < num_msdus; i++) {
4710 u32 l2_hdr_offset;
4711
4712 if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
4713 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4714 "i %d last_cookie %d is same\n",
4715 i, pmon->mon_last_buf_cookie);
4716 drop_mpdu = true;
4717 pmon->rx_mon_stats.dup_mon_buf_cnt++;
4718 continue;
4719 }
4720 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4721 msdu_list.sw_cookie[i]);
4722
4723 spin_lock_bh(&rx_ring->idr_lock);
4724 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4725 spin_unlock_bh(&rx_ring->idr_lock);
4726 if (!msdu) {
4727 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4728 "msdu_pop: invalid buf_id %d\n", buf_id);
4729 goto next_msdu;
4730 }
4731 rxcb = ATH11K_SKB_RXCB(msdu);
4732 if (!rxcb->unmapped) {
4733 dma_unmap_single(ar->ab->dev, rxcb->paddr,
4734 msdu->len +
4735 skb_tailroom(msdu),
4736 DMA_FROM_DEVICE);
4737 rxcb->unmapped = 1;
4738 }
4739 if (drop_mpdu) {
4740 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4741 "i %d drop msdu %p *ppdu_id %x\n",
4742 i, msdu, *ppdu_id);
4743 dev_kfree_skb_any(msdu);
4744 msdu = NULL;
4745 goto next_msdu;
4746 }
4747
4748 rx_desc = (struct hal_rx_desc *)msdu->data;
4749
4750 rx_pkt_offset = sizeof(struct hal_rx_desc);
4751 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
4752
4753 if (is_first_msdu) {
4754 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
4755 drop_mpdu = true;
4756 dev_kfree_skb_any(msdu);
4757 msdu = NULL;
4758 pmon->mon_last_linkdesc_paddr = paddr;
4759 goto next_msdu;
4760 }
4761
4762 msdu_ppdu_id =
4763 ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc);
4764
4765 if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
4766 ppdu_id,
4767 &rx_bufs_used)) {
4768 if (rx_bufs_used) {
4769 drop_mpdu = true;
4770 dev_kfree_skb_any(msdu);
4771 msdu = NULL;
4772 goto next_msdu;
4773 }
4774 return rx_bufs_used;
4775 }
4776 pmon->mon_last_linkdesc_paddr = paddr;
4777 is_first_msdu = false;
4778 }
4779 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
4780 &is_frag, &total_len,
4781 &frag_len, &msdu_cnt);
4782 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
4783
4784 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
4785
4786 if (!(*head_msdu))
4787 *head_msdu = msdu;
4788 else if (last)
4789 last->next = msdu;
4790
4791 last = msdu;
4792 next_msdu:
4793 pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
4794 rx_bufs_used++;
4795 spin_lock_bh(&rx_ring->idr_lock);
4796 idr_remove(&rx_ring->bufs_idr, buf_id);
4797 spin_unlock_bh(&rx_ring->idr_lock);
4798 }
4799
4800 ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
4801
4802 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
4803 &sw_cookie, &rbm,
4804 &p_buf_addr_info);
4805
4806 if (ar->ab->hw_params.rxdma1_enable) {
4807 if (ath11k_dp_rx_monitor_link_desc_return(ar,
4808 p_last_buf_addr_info,
4809 dp->mac_id))
4810 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4811 "dp_rx_monitor_link_desc_return failed");
4812 } else {
4813 ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
4814 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4815 }
4816
4817 p_last_buf_addr_info = p_buf_addr_info;
4818
4819 } while (paddr && msdu_cnt);
4820
4821 if (last)
4822 last->next = NULL;
4823
4824 *tail_msdu = msdu;
4825
4826 if (msdu_cnt == 0)
4827 *npackets = 1;
4828
4829 return rx_bufs_used;
4830 }
4831
ath11k_dp_rx_msdus_set_payload(struct ath11k * ar,struct sk_buff * msdu)4832 static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu)
4833 {
4834 u32 rx_pkt_offset, l2_hdr_offset;
4835
4836 rx_pkt_offset = ar->ab->hw_params.hal_desc_sz;
4837 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab,
4838 (struct hal_rx_desc *)msdu->data);
4839 skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
4840 }
4841
4842 static struct sk_buff *
ath11k_dp_rx_mon_merg_msdus(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * last_msdu,struct ieee80211_rx_status * rxs,bool * fcs_err)4843 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
4844 u32 mac_id, struct sk_buff *head_msdu,
4845 struct sk_buff *last_msdu,
4846 struct ieee80211_rx_status *rxs, bool *fcs_err)
4847 {
4848 struct ath11k_base *ab = ar->ab;
4849 struct sk_buff *msdu, *prev_buf;
4850 struct hal_rx_desc *rx_desc;
4851 char *hdr_desc;
4852 u8 *dest, decap_format;
4853 struct ieee80211_hdr_3addr *wh;
4854 struct rx_attention *rx_attention;
4855 u32 err_bitmap;
4856
4857 if (!head_msdu)
4858 goto err_merge_fail;
4859
4860 rx_desc = (struct hal_rx_desc *)head_msdu->data;
4861 rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc);
4862 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
4863
4864 if (err_bitmap & DP_RX_MPDU_ERR_FCS)
4865 *fcs_err = true;
4866
4867 if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention))
4868 return NULL;
4869
4870 decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc);
4871
4872 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
4873
4874 if (decap_format == DP_RX_DECAP_TYPE_RAW) {
4875 ath11k_dp_rx_msdus_set_payload(ar, head_msdu);
4876
4877 prev_buf = head_msdu;
4878 msdu = head_msdu->next;
4879
4880 while (msdu) {
4881 ath11k_dp_rx_msdus_set_payload(ar, msdu);
4882
4883 prev_buf = msdu;
4884 msdu = msdu->next;
4885 }
4886
4887 prev_buf->next = NULL;
4888
4889 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
4890 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
4891 u8 qos_pkt = 0;
4892
4893 rx_desc = (struct hal_rx_desc *)head_msdu->data;
4894 hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
4895
4896 /* Base size */
4897 wh = (struct ieee80211_hdr_3addr *)hdr_desc;
4898
4899 if (ieee80211_is_data_qos(wh->frame_control))
4900 qos_pkt = 1;
4901
4902 msdu = head_msdu;
4903
4904 while (msdu) {
4905 ath11k_dp_rx_msdus_set_payload(ar, msdu);
4906 if (qos_pkt) {
4907 dest = skb_push(msdu, sizeof(__le16));
4908 if (!dest)
4909 goto err_merge_fail;
4910 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr));
4911 }
4912 prev_buf = msdu;
4913 msdu = msdu->next;
4914 }
4915 dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
4916 if (!dest)
4917 goto err_merge_fail;
4918
4919 ath11k_dbg(ab, ATH11K_DBG_DATA,
4920 "mpdu_buf %p mpdu_buf->len %u",
4921 prev_buf, prev_buf->len);
4922 } else {
4923 ath11k_dbg(ab, ATH11K_DBG_DATA,
4924 "decap format %d is not supported!\n",
4925 decap_format);
4926 goto err_merge_fail;
4927 }
4928
4929 return head_msdu;
4930
4931 err_merge_fail:
4932 return NULL;
4933 }
4934
4935 static void
ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)4936 ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status,
4937 u8 *rtap_buf)
4938 {
4939 u32 rtap_len = 0;
4940
4941 put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]);
4942 rtap_len += 2;
4943
4944 put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]);
4945 rtap_len += 2;
4946
4947 put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]);
4948 rtap_len += 2;
4949
4950 put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]);
4951 rtap_len += 2;
4952
4953 put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]);
4954 rtap_len += 2;
4955
4956 put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]);
4957 }
4958
4959 static void
ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info * rx_status,u8 * rtap_buf)4960 ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status,
4961 u8 *rtap_buf)
4962 {
4963 u32 rtap_len = 0;
4964
4965 put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]);
4966 rtap_len += 2;
4967
4968 put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]);
4969 rtap_len += 2;
4970
4971 rtap_buf[rtap_len] = rx_status->he_RU[0];
4972 rtap_len += 1;
4973
4974 rtap_buf[rtap_len] = rx_status->he_RU[1];
4975 rtap_len += 1;
4976
4977 rtap_buf[rtap_len] = rx_status->he_RU[2];
4978 rtap_len += 1;
4979
4980 rtap_buf[rtap_len] = rx_status->he_RU[3];
4981 }
4982
ath11k_update_radiotap(struct ath11k * ar,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * mon_skb,struct ieee80211_rx_status * rxs)4983 static void ath11k_update_radiotap(struct ath11k *ar,
4984 struct hal_rx_mon_ppdu_info *ppduinfo,
4985 struct sk_buff *mon_skb,
4986 struct ieee80211_rx_status *rxs)
4987 {
4988 struct ieee80211_supported_band *sband;
4989 u8 *ptr = NULL;
4990
4991 rxs->flag |= RX_FLAG_MACTIME_START;
4992 rxs->signal = ppduinfo->rssi_comb + ATH11K_DEFAULT_NOISE_FLOOR;
4993
4994 if (ppduinfo->nss)
4995 rxs->nss = ppduinfo->nss;
4996
4997 if (ppduinfo->he_mu_flags) {
4998 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU;
4999 rxs->encoding = RX_ENC_HE;
5000 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu));
5001 ath11k_dp_rx_update_radiotap_he_mu(ppduinfo, ptr);
5002 } else if (ppduinfo->he_flags) {
5003 rxs->flag |= RX_FLAG_RADIOTAP_HE;
5004 rxs->encoding = RX_ENC_HE;
5005 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he));
5006 ath11k_dp_rx_update_radiotap_he(ppduinfo, ptr);
5007 rxs->rate_idx = ppduinfo->rate;
5008 } else if (ppduinfo->vht_flags) {
5009 rxs->encoding = RX_ENC_VHT;
5010 rxs->rate_idx = ppduinfo->rate;
5011 } else if (ppduinfo->ht_flags) {
5012 rxs->encoding = RX_ENC_HT;
5013 rxs->rate_idx = ppduinfo->rate;
5014 } else {
5015 rxs->encoding = RX_ENC_LEGACY;
5016 sband = &ar->mac.sbands[rxs->band];
5017 rxs->rate_idx = ath11k_mac_hw_rate_to_idx(sband, ppduinfo->rate,
5018 ppduinfo->cck_flag);
5019 }
5020
5021 rxs->mactime = ppduinfo->tsft;
5022 }
5023
ath11k_dp_rx_mon_deliver(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct hal_rx_mon_ppdu_info * ppduinfo,struct sk_buff * tail_msdu,struct napi_struct * napi)5024 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
5025 struct sk_buff *head_msdu,
5026 struct hal_rx_mon_ppdu_info *ppduinfo,
5027 struct sk_buff *tail_msdu,
5028 struct napi_struct *napi)
5029 {
5030 struct ath11k_pdev_dp *dp = &ar->dp;
5031 struct sk_buff *mon_skb, *skb_next, *header;
5032 struct ieee80211_rx_status *rxs = &dp->rx_status;
5033 bool fcs_err = false;
5034
5035 mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
5036 tail_msdu, rxs, &fcs_err);
5037
5038 if (!mon_skb)
5039 goto mon_deliver_fail;
5040
5041 header = mon_skb;
5042
5043 rxs->flag = 0;
5044
5045 if (fcs_err)
5046 rxs->flag = RX_FLAG_FAILED_FCS_CRC;
5047
5048 do {
5049 skb_next = mon_skb->next;
5050 if (!skb_next)
5051 rxs->flag &= ~RX_FLAG_AMSDU_MORE;
5052 else
5053 rxs->flag |= RX_FLAG_AMSDU_MORE;
5054
5055 if (mon_skb == header) {
5056 header = NULL;
5057 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
5058 } else {
5059 rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
5060 }
5061 rxs->flag |= RX_FLAG_ONLY_MONITOR;
5062 ath11k_update_radiotap(ar, ppduinfo, mon_skb, rxs);
5063
5064 ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs);
5065 mon_skb = skb_next;
5066 } while (mon_skb);
5067 rxs->flag = 0;
5068
5069 return 0;
5070
5071 mon_deliver_fail:
5072 mon_skb = head_msdu;
5073 while (mon_skb) {
5074 skb_next = mon_skb->next;
5075 dev_kfree_skb_any(mon_skb);
5076 mon_skb = skb_next;
5077 }
5078 return -EINVAL;
5079 }
5080
5081 /* The destination ring processing is stuck if the destination is not
5082 * moving while status ring moves 16 PPDU. The destination ring processing
5083 * skips this destination ring PPDU as a workaround.
5084 */
5085 #define MON_DEST_RING_STUCK_MAX_CNT 16
5086
ath11k_dp_rx_mon_dest_process(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)5087 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
5088 u32 quota, struct napi_struct *napi)
5089 {
5090 struct ath11k_pdev_dp *dp = &ar->dp;
5091 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5092 const struct ath11k_hw_hal_params *hal_params;
5093 void *ring_entry;
5094 struct hal_srng *mon_dst_srng;
5095 u32 ppdu_id;
5096 u32 rx_bufs_used;
5097 u32 ring_id;
5098 struct ath11k_pdev_mon_stats *rx_mon_stats;
5099 u32 npackets = 0;
5100 u32 mpdu_rx_bufs_used;
5101
5102 if (ar->ab->hw_params.rxdma1_enable)
5103 ring_id = dp->rxdma_mon_dst_ring.ring_id;
5104 else
5105 ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
5106
5107 mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
5108
5109 spin_lock_bh(&pmon->mon_lock);
5110
5111 spin_lock_bh(&mon_dst_srng->lock);
5112 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5113
5114 ppdu_id = pmon->mon_ppdu_info.ppdu_id;
5115 rx_bufs_used = 0;
5116 rx_mon_stats = &pmon->rx_mon_stats;
5117
5118 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5119 struct sk_buff *head_msdu, *tail_msdu;
5120
5121 head_msdu = NULL;
5122 tail_msdu = NULL;
5123
5124 mpdu_rx_bufs_used = ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
5125 &head_msdu,
5126 &tail_msdu,
5127 &npackets, &ppdu_id);
5128
5129 rx_bufs_used += mpdu_rx_bufs_used;
5130
5131 if (mpdu_rx_bufs_used) {
5132 dp->mon_dest_ring_stuck_cnt = 0;
5133 } else {
5134 dp->mon_dest_ring_stuck_cnt++;
5135 rx_mon_stats->dest_mon_not_reaped++;
5136 }
5137
5138 if (dp->mon_dest_ring_stuck_cnt > MON_DEST_RING_STUCK_MAX_CNT) {
5139 rx_mon_stats->dest_mon_stuck++;
5140 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5141 "status ring ppdu_id=%d dest ring ppdu_id=%d mon_dest_ring_stuck_cnt=%d dest_mon_not_reaped=%u dest_mon_stuck=%u\n",
5142 pmon->mon_ppdu_info.ppdu_id, ppdu_id,
5143 dp->mon_dest_ring_stuck_cnt,
5144 rx_mon_stats->dest_mon_not_reaped,
5145 rx_mon_stats->dest_mon_stuck);
5146 pmon->mon_ppdu_info.ppdu_id = ppdu_id;
5147 continue;
5148 }
5149
5150 if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
5151 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5152 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5153 "dest_rx: new ppdu_id %x != status ppdu_id %x dest_mon_not_reaped = %u dest_mon_stuck = %u\n",
5154 ppdu_id, pmon->mon_ppdu_info.ppdu_id,
5155 rx_mon_stats->dest_mon_not_reaped,
5156 rx_mon_stats->dest_mon_stuck);
5157 break;
5158 }
5159 if (head_msdu && tail_msdu) {
5160 ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
5161 &pmon->mon_ppdu_info,
5162 tail_msdu, napi);
5163 rx_mon_stats->dest_mpdu_done++;
5164 }
5165
5166 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5167 mon_dst_srng);
5168 }
5169 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5170 spin_unlock_bh(&mon_dst_srng->lock);
5171
5172 spin_unlock_bh(&pmon->mon_lock);
5173
5174 if (rx_bufs_used) {
5175 rx_mon_stats->dest_ppdu_done++;
5176 hal_params = ar->ab->hw_params.hal_params;
5177
5178 if (ar->ab->hw_params.rxdma1_enable)
5179 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5180 &dp->rxdma_mon_buf_ring,
5181 rx_bufs_used,
5182 hal_params->rx_buf_rbm);
5183 else
5184 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5185 &dp->rx_refill_buf_ring,
5186 rx_bufs_used,
5187 hal_params->rx_buf_rbm);
5188 }
5189 }
5190
ath11k_dp_rx_process_mon_status(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5191 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
5192 struct napi_struct *napi, int budget)
5193 {
5194 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5195 enum hal_rx_mon_status hal_status;
5196 struct sk_buff *skb;
5197 struct sk_buff_head skb_list;
5198 struct ath11k_peer *peer;
5199 struct ath11k_sta *arsta;
5200 int num_buffs_reaped = 0;
5201 u32 rx_buf_sz;
5202 u16 log_type;
5203 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&ar->dp.mon_data;
5204 struct ath11k_pdev_mon_stats *rx_mon_stats = &pmon->rx_mon_stats;
5205 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
5206
5207 __skb_queue_head_init(&skb_list);
5208
5209 num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
5210 &skb_list);
5211 if (!num_buffs_reaped)
5212 goto exit;
5213
5214 memset(ppdu_info, 0, sizeof(*ppdu_info));
5215 ppdu_info->peer_id = HAL_INVALID_PEERID;
5216
5217 while ((skb = __skb_dequeue(&skb_list))) {
5218 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) {
5219 log_type = ATH11K_PKTLOG_TYPE_LITE_RX;
5220 rx_buf_sz = DP_RX_BUFFER_SIZE_LITE;
5221 } else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) {
5222 log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF;
5223 rx_buf_sz = DP_RX_BUFFER_SIZE;
5224 } else {
5225 log_type = ATH11K_PKTLOG_TYPE_INVALID;
5226 rx_buf_sz = 0;
5227 }
5228
5229 if (log_type != ATH11K_PKTLOG_TYPE_INVALID)
5230 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5231
5232 memset(ppdu_info, 0, sizeof(*ppdu_info));
5233 ppdu_info->peer_id = HAL_INVALID_PEERID;
5234 hal_status = ath11k_hal_rx_parse_mon_status(ab, ppdu_info, skb);
5235
5236 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5237 pmon->mon_ppdu_status == DP_PPDU_STATUS_START &&
5238 hal_status == HAL_TLV_STATUS_PPDU_DONE) {
5239 rx_mon_stats->status_ppdu_done++;
5240 pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
5241 if (!ab->hw_params.full_monitor_mode) {
5242 ath11k_dp_rx_mon_dest_process(ar, mac_id,
5243 budget, napi);
5244 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5245 }
5246 }
5247
5248 if (ppdu_info->peer_id == HAL_INVALID_PEERID ||
5249 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
5250 dev_kfree_skb_any(skb);
5251 continue;
5252 }
5253
5254 rcu_read_lock();
5255 spin_lock_bh(&ab->base_lock);
5256 peer = ath11k_peer_find_by_id(ab, ppdu_info->peer_id);
5257
5258 if (!peer || !peer->sta) {
5259 ath11k_dbg(ab, ATH11K_DBG_DATA,
5260 "failed to find the peer with peer_id %d\n",
5261 ppdu_info->peer_id);
5262 goto next_skb;
5263 }
5264
5265 arsta = ath11k_sta_to_arsta(peer->sta);
5266 ath11k_dp_rx_update_peer_stats(arsta, ppdu_info);
5267
5268 if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
5269 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
5270
5271 next_skb:
5272 spin_unlock_bh(&ab->base_lock);
5273 rcu_read_unlock();
5274
5275 dev_kfree_skb_any(skb);
5276 memset(ppdu_info, 0, sizeof(*ppdu_info));
5277 ppdu_info->peer_id = HAL_INVALID_PEERID;
5278 }
5279 exit:
5280 return num_buffs_reaped;
5281 }
5282
5283 static u32
ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k * ar,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,struct hal_sw_mon_ring_entries * sw_mon_entries)5284 ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k *ar,
5285 void *ring_entry, struct sk_buff **head_msdu,
5286 struct sk_buff **tail_msdu,
5287 struct hal_sw_mon_ring_entries *sw_mon_entries)
5288 {
5289 struct ath11k_pdev_dp *dp = &ar->dp;
5290 struct ath11k_mon_data *pmon = &dp->mon_data;
5291 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
5292 struct sk_buff *msdu = NULL, *last = NULL;
5293 struct hal_sw_monitor_ring *sw_desc = ring_entry;
5294 struct hal_rx_msdu_list msdu_list;
5295 struct hal_rx_desc *rx_desc;
5296 struct ath11k_skb_rxcb *rxcb;
5297 void *rx_msdu_link_desc;
5298 void *p_buf_addr_info, *p_last_buf_addr_info;
5299 int buf_id, i = 0;
5300 u32 rx_buf_size, rx_pkt_offset, l2_hdr_offset;
5301 u32 rx_bufs_used = 0, msdu_cnt = 0;
5302 u32 total_len = 0, frag_len = 0, sw_cookie;
5303 u16 num_msdus = 0;
5304 u8 rxdma_err, rbm;
5305 bool is_frag, is_first_msdu;
5306 bool drop_mpdu = false;
5307
5308 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(ring_entry, sw_mon_entries);
5309
5310 sw_cookie = sw_mon_entries->mon_dst_sw_cookie;
5311 sw_mon_entries->end_of_ppdu = false;
5312 sw_mon_entries->drop_ppdu = false;
5313 p_last_buf_addr_info = sw_mon_entries->dst_buf_addr_info;
5314 msdu_cnt = sw_mon_entries->msdu_cnt;
5315
5316 sw_mon_entries->end_of_ppdu =
5317 FIELD_GET(HAL_SW_MON_RING_INFO0_END_OF_PPDU, sw_desc->info0);
5318 if (sw_mon_entries->end_of_ppdu)
5319 return rx_bufs_used;
5320
5321 if (FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON,
5322 sw_desc->info0) ==
5323 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
5324 rxdma_err =
5325 FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE,
5326 sw_desc->info0);
5327 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
5328 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
5329 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
5330 pmon->rx_mon_stats.dest_mpdu_drop++;
5331 drop_mpdu = true;
5332 }
5333 }
5334
5335 is_frag = false;
5336 is_first_msdu = true;
5337
5338 do {
5339 rx_msdu_link_desc =
5340 (u8 *)pmon->link_desc_banks[sw_cookie].vaddr +
5341 (sw_mon_entries->mon_dst_paddr -
5342 pmon->link_desc_banks[sw_cookie].paddr);
5343
5344 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
5345 &num_msdus);
5346
5347 for (i = 0; i < num_msdus; i++) {
5348 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
5349 msdu_list.sw_cookie[i]);
5350
5351 spin_lock_bh(&rx_ring->idr_lock);
5352 msdu = idr_find(&rx_ring->bufs_idr, buf_id);
5353 if (!msdu) {
5354 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5355 "full mon msdu_pop: invalid buf_id %d\n",
5356 buf_id);
5357 spin_unlock_bh(&rx_ring->idr_lock);
5358 goto next_msdu;
5359 }
5360 idr_remove(&rx_ring->bufs_idr, buf_id);
5361 spin_unlock_bh(&rx_ring->idr_lock);
5362
5363 rxcb = ATH11K_SKB_RXCB(msdu);
5364 if (!rxcb->unmapped) {
5365 dma_unmap_single(ar->ab->dev, rxcb->paddr,
5366 msdu->len +
5367 skb_tailroom(msdu),
5368 DMA_FROM_DEVICE);
5369 rxcb->unmapped = 1;
5370 }
5371 if (drop_mpdu) {
5372 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5373 "full mon: i %d drop msdu %p *ppdu_id %x\n",
5374 i, msdu, sw_mon_entries->ppdu_id);
5375 dev_kfree_skb_any(msdu);
5376 msdu_cnt--;
5377 goto next_msdu;
5378 }
5379
5380 rx_desc = (struct hal_rx_desc *)msdu->data;
5381
5382 rx_pkt_offset = sizeof(struct hal_rx_desc);
5383 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
5384
5385 if (is_first_msdu) {
5386 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
5387 drop_mpdu = true;
5388 dev_kfree_skb_any(msdu);
5389 msdu = NULL;
5390 goto next_msdu;
5391 }
5392 is_first_msdu = false;
5393 }
5394
5395 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
5396 &is_frag, &total_len,
5397 &frag_len, &msdu_cnt);
5398
5399 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
5400
5401 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
5402
5403 if (!(*head_msdu))
5404 *head_msdu = msdu;
5405 else if (last)
5406 last->next = msdu;
5407
5408 last = msdu;
5409 next_msdu:
5410 rx_bufs_used++;
5411 }
5412
5413 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc,
5414 &sw_mon_entries->mon_dst_paddr,
5415 &sw_mon_entries->mon_dst_sw_cookie,
5416 &rbm,
5417 &p_buf_addr_info);
5418
5419 if (ath11k_dp_rx_monitor_link_desc_return(ar,
5420 p_last_buf_addr_info,
5421 dp->mac_id))
5422 ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5423 "full mon: dp_rx_monitor_link_desc_return failed\n");
5424
5425 p_last_buf_addr_info = p_buf_addr_info;
5426
5427 } while (sw_mon_entries->mon_dst_paddr && msdu_cnt);
5428
5429 if (last)
5430 last->next = NULL;
5431
5432 *tail_msdu = msdu;
5433
5434 return rx_bufs_used;
5435 }
5436
ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu,struct sk_buff * head,struct sk_buff * tail)5437 static int ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp *dp,
5438 struct dp_full_mon_mpdu *mon_mpdu,
5439 struct sk_buff *head,
5440 struct sk_buff *tail)
5441 {
5442 mon_mpdu = kzalloc_obj(*mon_mpdu, GFP_ATOMIC);
5443 if (!mon_mpdu)
5444 return -ENOMEM;
5445
5446 list_add_tail(&mon_mpdu->list, &dp->dp_full_mon_mpdu_list);
5447 mon_mpdu->head = head;
5448 mon_mpdu->tail = tail;
5449
5450 return 0;
5451 }
5452
ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp * dp,struct dp_full_mon_mpdu * mon_mpdu)5453 static void ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp *dp,
5454 struct dp_full_mon_mpdu *mon_mpdu)
5455 {
5456 struct dp_full_mon_mpdu *tmp;
5457 struct sk_buff *tmp_msdu, *skb_next;
5458
5459 if (list_empty(&dp->dp_full_mon_mpdu_list))
5460 return;
5461
5462 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5463 list_del(&mon_mpdu->list);
5464
5465 tmp_msdu = mon_mpdu->head;
5466 while (tmp_msdu) {
5467 skb_next = tmp_msdu->next;
5468 dev_kfree_skb_any(tmp_msdu);
5469 tmp_msdu = skb_next;
5470 }
5471
5472 kfree(mon_mpdu);
5473 }
5474 }
5475
ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k * ar,int mac_id,struct ath11k_mon_data * pmon,struct napi_struct * napi)5476 static int ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k *ar,
5477 int mac_id,
5478 struct ath11k_mon_data *pmon,
5479 struct napi_struct *napi)
5480 {
5481 struct ath11k_pdev_mon_stats *rx_mon_stats;
5482 struct dp_full_mon_mpdu *tmp;
5483 struct dp_full_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
5484 struct sk_buff *head_msdu, *tail_msdu;
5485 struct ath11k_base *ab = ar->ab;
5486 struct ath11k_dp *dp = &ab->dp;
5487 int ret;
5488
5489 rx_mon_stats = &pmon->rx_mon_stats;
5490
5491 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5492 list_del(&mon_mpdu->list);
5493 head_msdu = mon_mpdu->head;
5494 tail_msdu = mon_mpdu->tail;
5495 if (head_msdu && tail_msdu) {
5496 ret = ath11k_dp_rx_mon_deliver(ar, mac_id, head_msdu,
5497 &pmon->mon_ppdu_info,
5498 tail_msdu, napi);
5499 rx_mon_stats->dest_mpdu_done++;
5500 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, "full mon: deliver ppdu\n");
5501 }
5502 kfree(mon_mpdu);
5503 }
5504
5505 return ret;
5506 }
5507
5508 static int
ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5509 ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base *ab, int mac_id,
5510 struct napi_struct *napi, int budget)
5511 {
5512 struct ath11k *ar = ab->pdevs[mac_id].ar;
5513 struct ath11k_pdev_dp *dp = &ar->dp;
5514 struct ath11k_mon_data *pmon = &dp->mon_data;
5515 struct hal_sw_mon_ring_entries *sw_mon_entries;
5516 int quota = 0, work = 0, count;
5517
5518 sw_mon_entries = &pmon->sw_mon_entries;
5519
5520 while (pmon->hold_mon_dst_ring) {
5521 quota = ath11k_dp_rx_process_mon_status(ab, mac_id,
5522 napi, 1);
5523 if (pmon->buf_state == DP_MON_STATUS_MATCH) {
5524 count = sw_mon_entries->status_buf_count;
5525 if (count > 1) {
5526 quota += ath11k_dp_rx_process_mon_status(ab, mac_id,
5527 napi, count);
5528 }
5529
5530 ath11k_dp_rx_full_mon_deliver_ppdu(ar, dp->mac_id,
5531 pmon, napi);
5532 pmon->hold_mon_dst_ring = false;
5533 } else if (!pmon->mon_status_paddr ||
5534 pmon->buf_state == DP_MON_STATUS_LEAD) {
5535 sw_mon_entries->drop_ppdu = true;
5536 pmon->hold_mon_dst_ring = false;
5537 }
5538
5539 if (!quota)
5540 break;
5541
5542 work += quota;
5543 }
5544
5545 if (sw_mon_entries->drop_ppdu)
5546 ath11k_dp_rx_full_mon_drop_ppdu(&ab->dp, pmon->mon_mpdu);
5547
5548 return work;
5549 }
5550
ath11k_dp_full_mon_process_rx(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5551 static int ath11k_dp_full_mon_process_rx(struct ath11k_base *ab, int mac_id,
5552 struct napi_struct *napi, int budget)
5553 {
5554 struct ath11k *ar = ab->pdevs[mac_id].ar;
5555 struct ath11k_pdev_dp *dp = &ar->dp;
5556 struct ath11k_mon_data *pmon = &dp->mon_data;
5557 struct hal_sw_mon_ring_entries *sw_mon_entries;
5558 struct ath11k_pdev_mon_stats *rx_mon_stats;
5559 struct sk_buff *head_msdu, *tail_msdu;
5560 struct hal_srng *mon_dst_srng;
5561 void *ring_entry;
5562 u32 rx_bufs_used = 0, mpdu_rx_bufs_used;
5563 int quota = 0, ret;
5564 bool break_dst_ring = false;
5565
5566 spin_lock_bh(&pmon->mon_lock);
5567
5568 sw_mon_entries = &pmon->sw_mon_entries;
5569 rx_mon_stats = &pmon->rx_mon_stats;
5570
5571 if (pmon->hold_mon_dst_ring) {
5572 spin_unlock_bh(&pmon->mon_lock);
5573 goto reap_status_ring;
5574 }
5575
5576 mon_dst_srng = &ar->ab->hal.srng_list[dp->rxdma_mon_dst_ring.ring_id];
5577 spin_lock_bh(&mon_dst_srng->lock);
5578
5579 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5580 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5581 head_msdu = NULL;
5582 tail_msdu = NULL;
5583
5584 mpdu_rx_bufs_used = ath11k_dp_rx_full_mon_mpdu_pop(ar, ring_entry,
5585 &head_msdu,
5586 &tail_msdu,
5587 sw_mon_entries);
5588 rx_bufs_used += mpdu_rx_bufs_used;
5589
5590 if (!sw_mon_entries->end_of_ppdu) {
5591 if (head_msdu) {
5592 ret = ath11k_dp_rx_full_mon_prepare_mpdu(&ab->dp,
5593 pmon->mon_mpdu,
5594 head_msdu,
5595 tail_msdu);
5596 if (ret)
5597 break_dst_ring = true;
5598 }
5599
5600 goto next_entry;
5601 } else {
5602 if (!sw_mon_entries->ppdu_id &&
5603 !sw_mon_entries->mon_status_paddr) {
5604 break_dst_ring = true;
5605 goto next_entry;
5606 }
5607 }
5608
5609 rx_mon_stats->dest_ppdu_done++;
5610 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5611 pmon->buf_state = DP_MON_STATUS_LAG;
5612 pmon->mon_status_paddr = sw_mon_entries->mon_status_paddr;
5613 pmon->hold_mon_dst_ring = true;
5614 next_entry:
5615 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5616 mon_dst_srng);
5617 if (break_dst_ring)
5618 break;
5619 }
5620
5621 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5622 spin_unlock_bh(&mon_dst_srng->lock);
5623 spin_unlock_bh(&pmon->mon_lock);
5624
5625 if (rx_bufs_used) {
5626 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5627 &dp->rxdma_mon_buf_ring,
5628 rx_bufs_used,
5629 HAL_RX_BUF_RBM_SW3_BM);
5630 }
5631
5632 reap_status_ring:
5633 quota = ath11k_dp_rx_process_full_mon_status_ring(ab, mac_id,
5634 napi, budget);
5635
5636 return quota;
5637 }
5638
ath11k_dp_rx_process_mon_rings(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)5639 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
5640 struct napi_struct *napi, int budget)
5641 {
5642 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5643 int ret = 0;
5644
5645 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5646 ab->hw_params.full_monitor_mode)
5647 ret = ath11k_dp_full_mon_process_rx(ab, mac_id, napi, budget);
5648 else
5649 ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
5650
5651 return ret;
5652 }
5653
ath11k_dp_rx_pdev_mon_status_attach(struct ath11k * ar)5654 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
5655 {
5656 struct ath11k_pdev_dp *dp = &ar->dp;
5657 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5658
5659 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5660
5661 memset(&pmon->rx_mon_stats, 0,
5662 sizeof(pmon->rx_mon_stats));
5663 return 0;
5664 }
5665
ath11k_dp_rx_pdev_mon_attach(struct ath11k * ar)5666 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
5667 {
5668 struct ath11k_pdev_dp *dp = &ar->dp;
5669 struct ath11k_mon_data *pmon = &dp->mon_data;
5670 struct hal_srng *mon_desc_srng = NULL;
5671 struct dp_srng *dp_srng;
5672 int ret = 0;
5673 u32 n_link_desc = 0;
5674
5675 ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
5676 if (ret) {
5677 ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
5678 return ret;
5679 }
5680
5681 /* if rxdma1_enable is false, no need to setup
5682 * rxdma_mon_desc_ring.
5683 */
5684 if (!ar->ab->hw_params.rxdma1_enable)
5685 return 0;
5686
5687 dp_srng = &dp->rxdma_mon_desc_ring;
5688 n_link_desc = dp_srng->size /
5689 ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
5690 mon_desc_srng =
5691 &ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
5692
5693 ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
5694 HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
5695 n_link_desc);
5696 if (ret) {
5697 ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
5698 return ret;
5699 }
5700 pmon->mon_last_linkdesc_paddr = 0;
5701 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
5702 spin_lock_init(&pmon->mon_lock);
5703
5704 return 0;
5705 }
5706
ath11k_dp_mon_link_free(struct ath11k * ar)5707 static int ath11k_dp_mon_link_free(struct ath11k *ar)
5708 {
5709 struct ath11k_pdev_dp *dp = &ar->dp;
5710 struct ath11k_mon_data *pmon = &dp->mon_data;
5711
5712 ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
5713 HAL_RXDMA_MONITOR_DESC,
5714 &dp->rxdma_mon_desc_ring);
5715 return 0;
5716 }
5717
ath11k_dp_rx_pdev_mon_detach(struct ath11k * ar)5718 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
5719 {
5720 ath11k_dp_mon_link_free(ar);
5721 return 0;
5722 }
5723
ath11k_dp_rx_pktlog_start(struct ath11k_base * ab)5724 int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab)
5725 {
5726 /* start reap timer */
5727 mod_timer(&ab->mon_reap_timer,
5728 jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
5729
5730 return 0;
5731 }
5732
ath11k_dp_rx_pktlog_stop(struct ath11k_base * ab,bool stop_timer)5733 int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer)
5734 {
5735 int ret;
5736
5737 if (stop_timer)
5738 timer_delete_sync(&ab->mon_reap_timer);
5739
5740 /* reap all the monitor related rings */
5741 ret = ath11k_dp_purge_mon_ring(ab);
5742 if (ret) {
5743 ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret);
5744 return ret;
5745 }
5746
5747 return 0;
5748 }
5749