1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
4 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/errno.h>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/netdevice.h>
12
13 #include "wq_enet_desc.h"
14 #include "rq_enet_desc.h"
15 #include "cq_enet_desc.h"
16 #include "vnic_resource.h"
17 #include "vnic_enet.h"
18 #include "vnic_dev.h"
19 #include "vnic_wq.h"
20 #include "vnic_rq.h"
21 #include "vnic_cq.h"
22 #include "vnic_intr.h"
23 #include "vnic_stats.h"
24 #include "vnic_nic.h"
25 #include "vnic_rss.h"
26 #include "enic_res.h"
27 #include "enic.h"
28
enic_get_vnic_config(struct enic * enic)29 int enic_get_vnic_config(struct enic *enic)
30 {
31 struct vnic_enet_config *c = &enic->config;
32 int err;
33
34 err = vnic_dev_get_mac_addr(enic->vdev, enic->mac_addr);
35 if (err) {
36 dev_err(enic_get_dev(enic),
37 "Error getting MAC addr, %d\n", err);
38 return err;
39 }
40
41 #define GET_CONFIG(m) \
42 do { \
43 err = vnic_dev_spec(enic->vdev, \
44 offsetof(struct vnic_enet_config, m), \
45 sizeof(c->m), &c->m); \
46 if (err) { \
47 dev_err(enic_get_dev(enic), \
48 "Error getting %s, %d\n", #m, err); \
49 return err; \
50 } \
51 } while (0)
52
53 GET_CONFIG(flags);
54 GET_CONFIG(wq_desc_count);
55 GET_CONFIG(rq_desc_count);
56 GET_CONFIG(mtu);
57 GET_CONFIG(intr_timer_type);
58 GET_CONFIG(intr_mode);
59 GET_CONFIG(intr_timer_usec);
60 GET_CONFIG(loop_tag);
61 GET_CONFIG(num_arfs);
62 GET_CONFIG(mq_subvnic_count);
63 GET_CONFIG(max_rq_ring);
64 GET_CONFIG(max_wq_ring);
65 GET_CONFIG(max_cq_ring);
66
67 if (!c->max_wq_ring)
68 c->max_wq_ring = ENIC_MAX_WQ_DESCS_DEFAULT;
69 if (!c->max_rq_ring)
70 c->max_rq_ring = ENIC_MAX_RQ_DESCS_DEFAULT;
71 if (!c->max_cq_ring)
72 c->max_cq_ring = ENIC_MAX_CQ_DESCS_DEFAULT;
73
74 c->wq_desc_count =
75 min_t(u32, c->max_wq_ring,
76 max_t(u32, ENIC_MIN_WQ_DESCS, c->wq_desc_count));
77 c->wq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */
78
79 c->rq_desc_count =
80 min_t(u32, c->max_rq_ring,
81 max_t(u32, ENIC_MIN_RQ_DESCS, c->rq_desc_count));
82 c->rq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */
83
84 if (c->mtu == 0)
85 c->mtu = 1500;
86 c->mtu = min_t(u16, ENIC_MAX_MTU, max_t(u16, ENIC_MIN_MTU, c->mtu));
87
88 c->intr_timer_usec = min_t(u32, c->intr_timer_usec,
89 vnic_dev_get_intr_coal_timer_max(enic->vdev));
90
91 dev_info(enic_get_dev(enic),
92 "vNIC MAC addr %pM wq/rq %d/%d max wq/rq/cq %d/%d/%d mtu %d\n",
93 enic->mac_addr, c->wq_desc_count, c->rq_desc_count,
94 c->max_wq_ring, c->max_rq_ring, c->max_cq_ring, c->mtu);
95
96 dev_info(enic_get_dev(enic), "vNIC csum tx/rx %s/%s "
97 "tso/lro %s/%s rss %s intr mode %s type %s timer %d usec "
98 "loopback tag 0x%04x\n",
99 ENIC_SETTING(enic, TXCSUM) ? "yes" : "no",
100 ENIC_SETTING(enic, RXCSUM) ? "yes" : "no",
101 ENIC_SETTING(enic, TSO) ? "yes" : "no",
102 ENIC_SETTING(enic, LRO) ? "yes" : "no",
103 ENIC_SETTING(enic, RSS) ? "yes" : "no",
104 c->intr_mode == VENET_INTR_MODE_INTX ? "INTx" :
105 c->intr_mode == VENET_INTR_MODE_MSI ? "MSI" :
106 c->intr_mode == VENET_INTR_MODE_ANY ? "any" :
107 "unknown",
108 c->intr_timer_type == VENET_INTR_TYPE_MIN ? "min" :
109 c->intr_timer_type == VENET_INTR_TYPE_IDLE ? "idle" :
110 "unknown",
111 c->intr_timer_usec,
112 c->loop_tag);
113
114 return 0;
115 }
116
enic_add_vlan(struct enic * enic,u16 vlanid)117 int enic_add_vlan(struct enic *enic, u16 vlanid)
118 {
119 u64 a0 = vlanid, a1 = 0;
120 int wait = 1000;
121 int err;
122
123 err = vnic_dev_cmd(enic->vdev, CMD_VLAN_ADD, &a0, &a1, wait);
124 if (err)
125 dev_err(enic_get_dev(enic), "Can't add vlan id, %d\n", err);
126
127 return err;
128 }
129
enic_del_vlan(struct enic * enic,u16 vlanid)130 int enic_del_vlan(struct enic *enic, u16 vlanid)
131 {
132 u64 a0 = vlanid, a1 = 0;
133 int wait = 1000;
134 int err;
135
136 err = vnic_dev_cmd(enic->vdev, CMD_VLAN_DEL, &a0, &a1, wait);
137 if (err)
138 dev_err(enic_get_dev(enic), "Can't delete vlan id, %d\n", err);
139
140 return err;
141 }
142
enic_set_nic_cfg(struct enic * enic,u8 rss_default_cpu,u8 rss_hash_type,u8 rss_hash_bits,u8 rss_base_cpu,u8 rss_enable,u8 tso_ipid_split_en,u8 ig_vlan_strip_en)143 int enic_set_nic_cfg(struct enic *enic, u8 rss_default_cpu, u8 rss_hash_type,
144 u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable, u8 tso_ipid_split_en,
145 u8 ig_vlan_strip_en)
146 {
147 enum vnic_devcmd_cmd cmd = CMD_NIC_CFG;
148 u64 a0, a1;
149 u32 nic_cfg;
150 int wait = 1000;
151
152 vnic_set_nic_cfg(&nic_cfg, rss_default_cpu,
153 rss_hash_type, rss_hash_bits, rss_base_cpu,
154 rss_enable, tso_ipid_split_en, ig_vlan_strip_en);
155
156 a0 = nic_cfg;
157 a1 = 0;
158
159 if (rss_hash_type & (NIC_CFG_RSS_HASH_TYPE_UDP_IPV4 |
160 NIC_CFG_RSS_HASH_TYPE_UDP_IPV6))
161 cmd = CMD_NIC_CFG_CHK;
162
163 return vnic_dev_cmd(enic->vdev, cmd, &a0, &a1, wait);
164 }
165
enic_set_rss_key(struct enic * enic,dma_addr_t key_pa,u64 len)166 int enic_set_rss_key(struct enic *enic, dma_addr_t key_pa, u64 len)
167 {
168 u64 a0 = (u64)key_pa, a1 = len;
169 int wait = 1000;
170
171 return vnic_dev_cmd(enic->vdev, CMD_RSS_KEY, &a0, &a1, wait);
172 }
173
enic_set_rss_cpu(struct enic * enic,dma_addr_t cpu_pa,u64 len)174 int enic_set_rss_cpu(struct enic *enic, dma_addr_t cpu_pa, u64 len)
175 {
176 u64 a0 = (u64)cpu_pa, a1 = len;
177 int wait = 1000;
178
179 return vnic_dev_cmd(enic->vdev, CMD_RSS_CPU, &a0, &a1, wait);
180 }
181
enic_free_vnic_resources(struct enic * enic)182 void enic_free_vnic_resources(struct enic *enic)
183 {
184 unsigned int i;
185
186 for (i = 0; i < enic->wq_count; i++)
187 vnic_wq_free(&enic->wq[i].vwq);
188 for (i = 0; i < enic->rq_count; i++)
189 vnic_rq_free(&enic->rq[i].vrq);
190 for (i = 0; i < enic->cq_count; i++)
191 vnic_cq_free(&enic->cq[i]);
192 for (i = 0; i < enic->intr_count; i++)
193 vnic_intr_free(&enic->intr[i]);
194 }
195
enic_get_res_counts(struct enic * enic)196 void enic_get_res_counts(struct enic *enic)
197 {
198 enic->wq_avail = vnic_dev_get_res_count(enic->vdev, RES_TYPE_WQ);
199 enic->rq_avail = vnic_dev_get_res_count(enic->vdev, RES_TYPE_RQ);
200 enic->cq_avail = vnic_dev_get_res_count(enic->vdev, RES_TYPE_CQ);
201 enic->intr_avail = vnic_dev_get_res_count(enic->vdev,
202 RES_TYPE_INTR_CTRL);
203
204 enic->wq_count = enic->wq_avail;
205 enic->rq_count = enic->rq_avail;
206 enic->cq_count = enic->cq_avail;
207 enic->intr_count = enic->intr_avail;
208
209 enic->has_admin_channel =
210 vnic_dev_get_res_count(enic->vdev, RES_TYPE_ADMIN_WQ) >= 1 &&
211 vnic_dev_get_res_count(enic->vdev, RES_TYPE_ADMIN_RQ) >= 1 &&
212 vnic_dev_get_res_count(enic->vdev, RES_TYPE_ADMIN_CQ) >=
213 ARRAY_SIZE(enic->admin_cq) &&
214 (enic_is_sriov_vf_v2(enic) ||
215 vnic_dev_get_res_count(enic->vdev, RES_TYPE_SRIOV_INTR) >= 1);
216
217 dev_info(enic_get_dev(enic),
218 "vNIC resources avail: wq %d rq %d cq %d intr %d admin %s\n",
219 enic->wq_avail, enic->rq_avail,
220 enic->cq_avail, enic->intr_avail,
221 enic->has_admin_channel ? "yes" : "no");
222 }
223
enic_init_vnic_resources(struct enic * enic)224 void enic_init_vnic_resources(struct enic *enic)
225 {
226 enum vnic_dev_intr_mode intr_mode;
227 unsigned int mask_on_assertion;
228 unsigned int interrupt_offset;
229 unsigned int error_interrupt_enable;
230 unsigned int error_interrupt_offset;
231 unsigned int cq_index;
232 unsigned int i;
233
234 intr_mode = vnic_dev_get_intr_mode(enic->vdev);
235
236 /* Init RQ/WQ resources.
237 *
238 * RQ[0 - n-1] point to CQ[0 - n-1]
239 * WQ[0 - m-1] point to CQ[n - n+m-1]
240 *
241 * Error interrupt is not enabled for MSI.
242 */
243
244 switch (intr_mode) {
245 case VNIC_DEV_INTR_MODE_INTX:
246 error_interrupt_enable = 1;
247 error_interrupt_offset = ENIC_LEGACY_ERR_INTR;
248 break;
249 case VNIC_DEV_INTR_MODE_MSIX:
250 error_interrupt_enable = 1;
251 error_interrupt_offset = enic_msix_err_intr(enic);
252 break;
253 default:
254 error_interrupt_enable = 0;
255 error_interrupt_offset = 0;
256 break;
257 }
258
259 for (i = 0; i < enic->rq_count; i++) {
260 cq_index = i;
261 vnic_rq_init(&enic->rq[i].vrq,
262 cq_index,
263 error_interrupt_enable,
264 error_interrupt_offset);
265 }
266
267 for (i = 0; i < enic->wq_count; i++) {
268 cq_index = enic->rq_count + i;
269 vnic_wq_init(&enic->wq[i].vwq,
270 cq_index,
271 error_interrupt_enable,
272 error_interrupt_offset);
273 }
274
275 /* Init CQ resources
276 *
277 * All CQs point to INTR[0] for INTx, MSI
278 * CQ[i] point to INTR[ENIC_MSIX_IO_INTR_BASE + i] for MSI-X
279 */
280
281 for (i = 0; i < enic->cq_count; i++) {
282
283 switch (intr_mode) {
284 case VNIC_DEV_INTR_MODE_MSIX:
285 interrupt_offset = ENIC_MSIX_IO_INTR_BASE + i;
286 break;
287 default:
288 interrupt_offset = 0;
289 break;
290 }
291
292 vnic_cq_init(&enic->cq[i],
293 0 /* flow_control_enable */,
294 1 /* color_enable */,
295 0 /* cq_head */,
296 0 /* cq_tail */,
297 1 /* cq_tail_color */,
298 1 /* interrupt_enable */,
299 1 /* cq_entry_enable */,
300 0 /* cq_message_enable */,
301 interrupt_offset,
302 0 /* cq_message_addr */);
303 }
304
305 /* Init INTR resources
306 *
307 * mask_on_assertion is not used for INTx due to the level-
308 * triggered nature of INTx
309 */
310
311 switch (intr_mode) {
312 case VNIC_DEV_INTR_MODE_MSI:
313 case VNIC_DEV_INTR_MODE_MSIX:
314 mask_on_assertion = 1;
315 break;
316 default:
317 mask_on_assertion = 0;
318 break;
319 }
320
321 for (i = 0; i < enic->intr_count; i++) {
322 vnic_intr_init(&enic->intr[i],
323 enic->config.intr_timer_usec,
324 enic->config.intr_timer_type,
325 mask_on_assertion);
326 }
327 }
328
enic_alloc_vnic_resources(struct enic * enic)329 int enic_alloc_vnic_resources(struct enic *enic)
330 {
331 enum vnic_dev_intr_mode intr_mode;
332 int rq_cq_desc_size;
333 unsigned int i;
334 int err;
335
336 intr_mode = vnic_dev_get_intr_mode(enic->vdev);
337
338 dev_info(enic_get_dev(enic), "vNIC resources used: "
339 "wq %d rq %d cq %d intr %d intr mode %s\n",
340 enic->wq_count, enic->rq_count,
341 enic->cq_count, enic->intr_count,
342 intr_mode == VNIC_DEV_INTR_MODE_INTX ? "legacy PCI INTx" :
343 intr_mode == VNIC_DEV_INTR_MODE_MSI ? "MSI" :
344 intr_mode == VNIC_DEV_INTR_MODE_MSIX ? "MSI-X" :
345 "unknown");
346
347 switch (enic->ext_cq) {
348 case ENIC_RQ_CQ_ENTRY_SIZE_16:
349 rq_cq_desc_size = 16;
350 break;
351 case ENIC_RQ_CQ_ENTRY_SIZE_32:
352 rq_cq_desc_size = 32;
353 break;
354 case ENIC_RQ_CQ_ENTRY_SIZE_64:
355 rq_cq_desc_size = 64;
356 break;
357 default:
358 dev_err(enic_get_dev(enic),
359 "Unable to determine rq cq desc size: %d",
360 enic->ext_cq);
361 err = -ENODEV;
362 goto err_out;
363 }
364
365 /* Allocate queue resources
366 */
367
368 for (i = 0; i < enic->wq_count; i++) {
369 err = vnic_wq_alloc(enic->vdev, &enic->wq[i].vwq, i,
370 enic->config.wq_desc_count,
371 sizeof(struct wq_enet_desc));
372 if (err)
373 goto err_out_cleanup;
374 }
375
376 for (i = 0; i < enic->rq_count; i++) {
377 err = vnic_rq_alloc(enic->vdev, &enic->rq[i].vrq, i,
378 enic->config.rq_desc_count,
379 sizeof(struct rq_enet_desc));
380 if (err)
381 goto err_out_cleanup;
382 }
383
384 for (i = 0; i < enic->cq_count; i++) {
385 if (i < enic->rq_count)
386 err = vnic_cq_alloc(enic->vdev, &enic->cq[i], i,
387 enic->config.rq_desc_count,
388 rq_cq_desc_size);
389 else
390 err = vnic_cq_alloc(enic->vdev, &enic->cq[i], i,
391 enic->config.wq_desc_count,
392 sizeof(struct cq_enet_wq_desc));
393 if (err)
394 goto err_out_cleanup;
395 }
396
397 for (i = 0; i < enic->intr_count; i++) {
398 err = vnic_intr_alloc(enic->vdev, &enic->intr[i], i);
399 if (err)
400 goto err_out_cleanup;
401 }
402
403 /* Hook remaining resource
404 */
405
406 enic->legacy_pba = vnic_dev_get_res(enic->vdev,
407 RES_TYPE_INTR_PBA_LEGACY, 0);
408 if (!enic->legacy_pba && intr_mode == VNIC_DEV_INTR_MODE_INTX) {
409 dev_err(enic_get_dev(enic),
410 "Failed to hook legacy pba resource\n");
411 err = -ENODEV;
412 goto err_out_cleanup;
413 }
414
415 return 0;
416
417 err_out_cleanup:
418 enic_free_vnic_resources(enic);
419 err_out:
420 return err;
421 }
422
423 /*
424 * CMD_CQ_ENTRY_SIZE_SET can fail on older hw generations that don't support
425 * that command
426 */
enic_ext_cq(struct enic * enic)427 void enic_ext_cq(struct enic *enic)
428 {
429 u64 a0 = CMD_CQ_ENTRY_SIZE_SET, a1 = 0;
430 int wait = 1000;
431 int ret;
432
433 spin_lock_bh(&enic->devcmd_lock);
434 ret = vnic_dev_cmd(enic->vdev, CMD_CAPABILITY, &a0, &a1, wait);
435 if (ret || a0) {
436 dev_info(&enic->pdev->dev,
437 "CMD_CQ_ENTRY_SIZE_SET not supported.");
438 enic->ext_cq = ENIC_RQ_CQ_ENTRY_SIZE_16;
439 goto out;
440 }
441 a1 &= VNIC_RQ_CQ_ENTRY_SIZE_ALL_BIT;
442 enic->ext_cq = fls(a1) - 1;
443 a0 = VNIC_RQ_ALL;
444 a1 = enic->ext_cq;
445 ret = vnic_dev_cmd(enic->vdev, CMD_CQ_ENTRY_SIZE_SET, &a0, &a1, wait);
446 if (ret) {
447 dev_info(&enic->pdev->dev, "CMD_CQ_ENTRY_SIZE_SET failed.");
448 enic->ext_cq = ENIC_RQ_CQ_ENTRY_SIZE_16;
449 }
450 out:
451 spin_unlock_bh(&enic->devcmd_lock);
452 dev_info(&enic->pdev->dev, "CQ entry size set to %d bytes",
453 16 << enic->ext_cq);
454 }
455