1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 */
5
6 #include "xe_wa.h"
7
8 #include <drm/drm_managed.h>
9 #include <kunit/visibility.h>
10 #include <linux/compiler_types.h>
11 #include <linux/fault-inject.h>
12
13 #include <generated/xe_device_wa_oob.h>
14 #include <generated/xe_wa_oob.h>
15
16 #include "regs/xe_engine_regs.h"
17 #include "regs/xe_gt_regs.h"
18 #include "regs/xe_guc_regs.h"
19 #include "regs/xe_regs.h"
20 #include "xe_device_types.h"
21 #include "xe_force_wake.h"
22 #include "xe_gt_types.h"
23 #include "xe_hw_engine_types.h"
24 #include "xe_mmio.h"
25 #include "xe_platform_types.h"
26 #include "xe_rtp.h"
27 #include "xe_sriov.h"
28 #include "xe_step.h"
29
30 /**
31 * DOC: Hardware workarounds
32 *
33 * Hardware workarounds are register programming documented to be executed in
34 * the driver that fall outside of the normal programming sequences for a
35 * platform. There are some basic categories of workarounds, depending on
36 * how/when they are applied:
37 *
38 * - LRC workarounds: workarounds that touch registers that are
39 * saved/restored to/from the HW context image. The list is emitted (via Load
40 * Register Immediate commands) once when initializing the device and saved in
41 * the default context. That default context is then used on every context
42 * creation to have a "primed golden context", i.e. a context image that
43 * already contains the changes needed to all the registers. See
44 * drivers/gpu/drm/xe/xe_lrc.c for default context handling.
45 *
46 * - Engine workarounds: the list of these WAs is applied whenever the specific
47 * engine is reset. It's also possible that a set of engine classes share a
48 * common power domain and they are reset together. This happens on some
49 * platforms with render and compute engines. In this case (at least) one of
50 * them need to keeep the workaround programming: the approach taken in the
51 * driver is to tie those workarounds to the first compute/render engine that
52 * is registered. When executing with GuC submission, engine resets are
53 * outside of kernel driver control, hence the list of registers involved is
54 * written once, on engine initialization, and then passed to GuC, that
55 * saves/restores their values before/after the reset takes place. See
56 * drivers/gpu/drm/xe/xe_guc_ads.c for reference.
57 *
58 * - GT workarounds: the list of these WAs is applied whenever these registers
59 * revert to their default values: on GPU reset, suspend/resume [1]_, etc.
60 *
61 * - Register whitelist: some workarounds need to be implemented in userspace,
62 * but need to touch privileged registers. The whitelist in the kernel
63 * instructs the hardware to allow the access to happen. From the kernel side,
64 * this is just a special case of a MMIO workaround (as we write the list of
65 * these to/be-whitelisted registers to some special HW registers).
66 *
67 * - Workaround batchbuffers: buffers that get executed automatically by the
68 * hardware on every HW context restore. These buffers are created and
69 * programmed in the default context so the hardware always go through those
70 * programming sequences when switching contexts. The support for workaround
71 * batchbuffers is enabled via these hardware mechanisms:
72 *
73 * #. INDIRECT_CTX (also known as **mid context restore bb**): A batchbuffer
74 * and an offset are provided in the default context, pointing the hardware
75 * to jump to that location when that offset is reached in the context
76 * restore. When a context is being restored, this is executed after the
77 * ring context, in the middle (or beginning) of the engine context image.
78 *
79 * #. BB_PER_CTX_PTR (also known as **post context restore bb**): A
80 * batchbuffer is provided in the default context, pointing the hardware to
81 * a buffer to continue executing after the engine registers are restored
82 * in a context restore sequence.
83 *
84 * Below is the timeline for a context restore sequence:
85 *
86 * .. code::
87 *
88 * INDIRECT_CTX_OFFSET
89 * |----------->|
90 * .------------.------------.-------------.------------.--------------.-----------.
91 * |Ring | Engine | Mid-context | Engine | Post-context | Ring |
92 * |Restore | Restore (1)| BB Restore | Restore (2)| BB Restore | Execution |
93 * `------------'------------'-------------'------------'--------------'-----------'
94 *
95 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from
96 * a central place. Those are peppered around the rest of the code, as needed.
97 * There's a central place to control which workarounds are enabled:
98 * drivers/gpu/drm/xe/xe_wa_oob.rules for GT workarounds and
99 * drivers/gpu/drm/xe/xe_device_wa_oob.rules for device/SoC workarounds.
100 * These files only record which workarounds are enabled: during early device
101 * initialization those rules are evaluated and recorded by the driver. Then
102 * later the driver checks with ``XE_GT_WA()`` and ``XE_DEVICE_WA()`` to
103 * implement them.
104 *
105 * .. [1] Technically, some registers are powercontext saved & restored, so they
106 * survive a suspend/resume. In practice, writing them again is not too
107 * costly and simplifies things, so it's the approach taken in the driver.
108 *
109 * .. note::
110 * Hardware workarounds in xe work the same way as in i915, with the
111 * difference of how they are maintained in the code. In xe it uses the
112 * xe_rtp infrastructure so the workarounds can be kept in tables, following
113 * a more declarative approach rather than procedural.
114 *
115 * .. note::
116 * When a workaround applies to every single known IP version in a range,
117 * the preferred handling is to use a single range-based RTP entry rather
118 * than individual entries for each version, even if some of the intermediate
119 * version numbers are currently unused. If a new intermediate IP version
120 * appears in the future and is enabled in the driver, any existing
121 * range-based entries that contain the new version number will need to be
122 * analyzed to determine whether their workarounds should apply to the new
123 * version, or whether any existing range based entries needs to be split
124 * into two entries that do not include the new intermediate version.
125 */
126
127 #undef XE_REG_MCR
128 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
129
130 __diag_push();
131 __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
132
133 VISIBLE_IF_KUNIT const struct xe_rtp_table_sr gt_was = XE_RTP_TABLE_SR(
134 /* Workarounds applying over a range of IPs */
135
136 { XE_RTP_NAME("14011060649"),
137 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
138 ENGINE_CLASS(VIDEO_DECODE),
139 FUNC(xe_rtp_match_even_instance)),
140 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
141 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
142 },
143 { XE_RTP_NAME("14011059788"),
144 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
145 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
146 },
147 { XE_RTP_NAME("14015795083"),
148 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)),
149 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
150 },
151 { XE_RTP_NAME("16021867713"),
152 XE_RTP_RULES(MEDIA_VERSION_RANGE(1300, 3002),
153 ENGINE_CLASS(VIDEO_DECODE)),
154 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
155 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
156 },
157 { XE_RTP_NAME("14019449301"),
158 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 2000), ENGINE_CLASS(VIDEO_DECODE)),
159 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
160 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
161 },
162 { XE_RTP_NAME("16028005424"),
163 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), OR,
164 MEDIA_VERSION_RANGE(1301, 3500)),
165 XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
166 },
167 { XE_RTP_NAME("14026578760"),
168 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, 3511), OR,
169 MEDIA_VERSION(3503)),
170 XE_RTP_ACTIONS(SET(GAMSTLB_CTRL, DIS_PEND_GPA_LINK))
171 },
172
173 /* DG1 */
174
175 { XE_RTP_NAME("1409420604"),
176 XE_RTP_RULES(PLATFORM(DG1)),
177 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
178 },
179 { XE_RTP_NAME("1408615072"),
180 XE_RTP_RULES(PLATFORM(DG1)),
181 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS))
182 },
183
184 /* DG2 */
185
186 { XE_RTP_NAME("22010523718"),
187 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
188 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
189 },
190 { XE_RTP_NAME("14011006942"),
191 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
192 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
193 },
194 { XE_RTP_NAME("14014830051"),
195 XE_RTP_RULES(PLATFORM(DG2)),
196 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
197 },
198 { XE_RTP_NAME("18018781329"),
199 XE_RTP_RULES(PLATFORM(DG2)),
200 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
201 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
202 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
203 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
204 },
205 { XE_RTP_NAME("1509235366"),
206 XE_RTP_RULES(PLATFORM(DG2)),
207 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL,
208 INVALIDATION_BROADCAST_MODE_DIS |
209 GLOBAL_INVALIDATION_MODE))
210 },
211
212 /* PVC */
213
214 { XE_RTP_NAME("18018781329"),
215 XE_RTP_RULES(PLATFORM(PVC)),
216 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
217 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
218 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
219 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
220 },
221 { XE_RTP_NAME("16016694945"),
222 XE_RTP_RULES(PLATFORM(PVC)),
223 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC))
224 },
225
226 /* Xe_LPG */
227
228 { XE_RTP_NAME("14018575942"),
229 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
230 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
231 },
232 { XE_RTP_NAME("22016670082"),
233 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
234 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))
235 },
236
237 /* Xe_LPM+ */
238
239 { XE_RTP_NAME("22016670082"),
240 XE_RTP_RULES(MEDIA_VERSION(1300)),
241 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
242 },
243
244 /* Xe2_LPM */
245
246 { XE_RTP_NAME("14017421178"),
247 XE_RTP_RULES(MEDIA_VERSION(2000),
248 ENGINE_CLASS(VIDEO_DECODE)),
249 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
250 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
251 },
252
253 /* Xe2_HPG */
254
255 { XE_RTP_NAME("16025250150"),
256 XE_RTP_RULES(GRAPHICS_VERSION(2001)),
257 XE_RTP_ACTIONS(FIELD_SET(LSN_VC_REG2,
258 LSN_LNI_WGT_MASK | LSN_LNE_WGT_MASK |
259 LSN_DIM_X_WGT_MASK | LSN_DIM_Y_WGT_MASK |
260 LSN_DIM_Z_WGT_MASK,
261 LSN_LNI_WGT(1) | LSN_LNE_WGT(1) |
262 LSN_DIM_X_WGT(1) | LSN_DIM_Y_WGT(1) |
263 LSN_DIM_Z_WGT(1)),
264 SET(LSC_CHICKEN_BIT_0_UDW, L3_128B_256B_WRT_DIS))
265 },
266
267 /* Xe3_LPG */
268
269 { XE_RTP_NAME("14021871409"),
270 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)),
271 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS))
272 },
273
274 /* Xe3_LPM */
275
276 { XE_RTP_NAME("16021865536"),
277 XE_RTP_RULES(MEDIA_VERSION_RANGE(3000, 3002),
278 ENGINE_CLASS(VIDEO_DECODE)),
279 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
280 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
281 },
282 { XE_RTP_NAME("14021486841"),
283 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0),
284 ENGINE_CLASS(VIDEO_DECODE)),
285 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)),
286 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
287 },
288
289 /* Xe3P_LPG */
290
291 { XE_RTP_NAME("14025160223"),
292 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
293 XE_RTP_ACTIONS(SET(MMIOATSREQLIMIT_GAM_WALK_3D,
294 DIS_ATS_WRONLY_PG))
295 },
296 { XE_RTP_NAME("14026144927, 16029437861, 14026127056"),
297 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
298 XE_RTP_ACTIONS(SET(L3SQCREG2, L3_SQ_DISABLE_COAMA_2WAY_COH |
299 L3_SQ_DISABLE_COAMA))
300 },
301 { XE_RTP_NAME("14025635424"),
302 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
303 XE_RTP_ACTIONS(SET(GAMSTLB_CTRL2, STLB_SINGLE_BANK_MODE))
304 },
305 { XE_RTP_NAME("16028005424"),
306 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
307 XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
308 },
309 );
310 EXPORT_SYMBOL_IF_KUNIT(gt_was);
311
312 static const struct xe_rtp_table_sr engine_was = XE_RTP_TABLE_SR(
313 /* Workarounds applying over a range of IPs */
314
315 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
316 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
317 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),
318 FF_TESSELATION_DOP_GATE_DISABLE))
319 },
320 { XE_RTP_NAME("1409804808"),
321 XE_RTP_RULES(GRAPHICS_VERSION(1200),
322 ENGINE_CLASS(RENDER),
323 IS_INTEGRATED),
324 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS))
325 },
326 { XE_RTP_NAME("14010229206, 1409085225"),
327 XE_RTP_RULES(GRAPHICS_VERSION(1200),
328 ENGINE_CLASS(RENDER),
329 IS_INTEGRATED),
330 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
331 },
332 { XE_RTP_NAME("1606931601"),
333 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
334 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ))
335 },
336 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),
337 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),
338 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE),
339 FF_DOP_CLOCK_GATE_DISABLE))
340 },
341 { XE_RTP_NAME("1406941453"),
342 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
343 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL))
344 },
345 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
346 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
347 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),
348 FFSC_PERCTX_PREEMPT_CTRL))
349 },
350 { XE_RTP_NAME("18032247524"),
351 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
352 FUNC(xe_rtp_match_first_render_or_compute)),
353 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
354 },
355 { XE_RTP_NAME("16018712365"),
356 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
357 FUNC(xe_rtp_match_first_render_or_compute)),
358 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
359 },
360 { XE_RTP_NAME("14020338487"),
361 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
362 FUNC(xe_rtp_match_first_render_or_compute)),
363 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
364 },
365 { XE_RTP_NAME("14018471104"),
366 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
367 FUNC(xe_rtp_match_first_render_or_compute)),
368 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
369 },
370 /*
371 * Although this workaround isn't required for the RCS, disabling these
372 * reports has no impact for our driver or the GuC, so we go ahead and
373 * apply this to all engines for simplicity.
374 */
375 { XE_RTP_NAME("16021639441"),
376 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), OR,
377 MEDIA_VERSION_RANGE(1301, 2000)),
378 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
379 GHWSP_CSB_REPORT_DIS |
380 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
381 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
382 },
383 { XE_RTP_NAME("14021402888"),
384 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3005), ENGINE_CLASS(RENDER)),
385 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
386 },
387 { XE_RTP_NAME("13012615864"),
388 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3005),
389 FUNC(xe_rtp_match_first_render_or_compute)),
390 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
391 },
392 { XE_RTP_NAME("18041344222"),
393 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3000),
394 FUNC(xe_rtp_match_first_render_or_compute),
395 FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
396 XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
397 },
398
399 /* TGL */
400
401 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
402 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
403 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
404 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
405 RC_SEMA_IDLE_MSG_DISABLE))
406 },
407
408 /* RKL */
409
410 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
411 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
412 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
413 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
414 RC_SEMA_IDLE_MSG_DISABLE))
415 },
416
417 /* ADL-P */
418
419 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
420 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)),
421 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
422 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
423 RC_SEMA_IDLE_MSG_DISABLE))
424 },
425
426 /* DG2 */
427
428 { XE_RTP_NAME("22013037850"),
429 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
430 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
431 DISABLE_128B_EVICTION_COMMAND_UDW))
432 },
433 { XE_RTP_NAME("22014226127"),
434 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
435 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
436 },
437 { XE_RTP_NAME("18017747507"),
438 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
439 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
440 POLYGON_TRIFAN_LINELOOP_DISABLE))
441 },
442 { XE_RTP_NAME("22012826095, 22013059131"),
443 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
444 FUNC(xe_rtp_match_first_render_or_compute)),
445 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
446 MAXREQS_PER_BANK,
447 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
448 },
449 { XE_RTP_NAME("22013059131"),
450 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
451 FUNC(xe_rtp_match_first_render_or_compute)),
452 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
453 },
454 { XE_RTP_NAME("14015227452"),
455 XE_RTP_RULES(PLATFORM(DG2),
456 FUNC(xe_rtp_match_first_render_or_compute)),
457 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
458 },
459 { XE_RTP_NAME("18028616096"),
460 XE_RTP_RULES(PLATFORM(DG2),
461 FUNC(xe_rtp_match_first_render_or_compute)),
462 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
463 },
464 { XE_RTP_NAME("22015475538"),
465 XE_RTP_RULES(PLATFORM(DG2),
466 FUNC(xe_rtp_match_first_render_or_compute)),
467 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
468 },
469 { XE_RTP_NAME("22012654132"),
470 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
471 FUNC(xe_rtp_match_first_render_or_compute)),
472 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
473 /*
474 * Register can't be read back for verification on
475 * DG2 due to Wa_14012342262
476 */
477 .read_mask = 0))
478 },
479 { XE_RTP_NAME("1509727124"),
480 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
481 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB))
482 },
483 { XE_RTP_NAME("22012856258"),
484 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
485 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))
486 },
487 { XE_RTP_NAME("22010960976, 14013347512"),
488 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
489 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
490 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK))
491 },
492 { XE_RTP_NAME("14015150844"),
493 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
494 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
495 XE_RTP_NOCHECK))
496 },
497
498 /* PVC */
499
500 { XE_RTP_NAME("22014226127"),
501 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
502 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
503 },
504 { XE_RTP_NAME("14015227452"),
505 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
506 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
507 },
508 { XE_RTP_NAME("18020744125"),
509 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute),
510 ENGINE_CLASS(COMPUTE)),
511 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0))
512 },
513
514 /* Xe_LPG */
515
516 { XE_RTP_NAME("14017856879"),
517 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
518 FUNC(xe_rtp_match_first_render_or_compute)),
519 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH))
520 },
521 { XE_RTP_NAME("14015150844"),
522 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
523 FUNC(xe_rtp_match_first_render_or_compute)),
524 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
525 XE_RTP_NOCHECK))
526 },
527 { XE_RTP_NAME("14020495402"),
528 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
529 FUNC(xe_rtp_match_first_render_or_compute)),
530 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING))
531 },
532
533 /* Xe2_LPG */
534
535 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */
536 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
537 FUNC(xe_rtp_match_first_render_or_compute)),
538 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
539 },
540 { XE_RTP_NAME("16018610683"),
541 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
542 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
543 },
544
545 /* Xe2_HPG */
546
547 { XE_RTP_NAME("16018737384"),
548 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2999),
549 FUNC(xe_rtp_match_first_render_or_compute)),
550 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
551 },
552 { XE_RTP_NAME("14019811474"),
553 XE_RTP_RULES(GRAPHICS_VERSION(2001),
554 FUNC(xe_rtp_match_first_render_or_compute)),
555 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
556 },
557 { XE_RTP_NAME("14021821874, 14022954250"),
558 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
559 FUNC(xe_rtp_match_first_render_or_compute)),
560 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
561 },
562
563 /* Xe3_LPG */
564
565 { XE_RTP_NAME("18034896535"),
566 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
567 FUNC(xe_rtp_match_first_render_or_compute)),
568 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
569 },
570 { XE_RTP_NAME("16024792527"),
571 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
572 FUNC(xe_rtp_match_first_render_or_compute)),
573 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER,
574 SMP_FORCE_128B_OVERFETCH))
575 },
576 { XE_RTP_NAME("14023061436"),
577 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005),
578 FUNC(xe_rtp_match_first_render_or_compute)),
579 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE))
580 },
581 { XE_RTP_NAME("16023105232"),
582 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR,
583 GRAPHICS_VERSION_RANGE(2001, 3001)),
584 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE,
585 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
586 },
587
588 /* Xe3p_LPG*/
589
590 { XE_RTP_NAME("22021149932, 14026290593"),
591 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
592 FUNC(xe_rtp_match_first_render_or_compute)),
593 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, SAMPLER_LD_LSC_DISABLE))
594 },
595 { XE_RTP_NAME("14025676848, 14026270459"),
596 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
597 FUNC(xe_rtp_match_first_render_or_compute)),
598 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE))
599 },
600 { XE_RTP_NAME("16028951944"),
601 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
602 FUNC(xe_rtp_match_first_render_or_compute)),
603 XE_RTP_ACTIONS(SET(ROW_CHICKEN5, CPSS_AWARE_DIS))
604 },
605
606 /* Xe3p_XPC */
607
608 { XE_RTP_NAME("14026999295"),
609 XE_RTP_RULES(GRAPHICS_VERSION(3511),
610 FUNC(xe_rtp_match_first_render_or_compute)),
611 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_EU_GRF_POISON_TO_LSC))
612 },
613 { XE_RTP_NAME("18044193044"),
614 XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
615 FUNC(xe_rtp_match_first_render_or_compute)),
616 XE_RTP_ACTIONS(SET(TDL_CHICKEN, BIT_APQ_OPT_DIS))
617 },
618 );
619
620 static const struct xe_rtp_table_sr lrc_was = XE_RTP_TABLE_SR(
621 { XE_RTP_NAME("16011163337"),
622 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
623 /* read verification is ignored due to 1608008084. */
624 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
625 FF_MODE2_GS_TIMER_MASK,
626 FF_MODE2_GS_TIMER_224))
627 },
628 { XE_RTP_NAME("1604555607"),
629 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
630 /* read verification is ignored due to 1608008084. */
631 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
632 FF_MODE2_TDS_TIMER_MASK,
633 FF_MODE2_TDS_TIMER_128))
634 },
635 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
636 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
637 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,
638 DISABLE_CPS_AWARE_COLOR_PIPE))
639 },
640 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
641 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
642 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),
643 PREEMPT_GPGPU_LEVEL_MASK,
644 PREEMPT_GPGPU_THREAD_GROUP_LEVEL))
645 },
646 { XE_RTP_NAME("1806527549"),
647 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
648 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE))
649 },
650 { XE_RTP_NAME("1606376872"),
651 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
652 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))
653 },
654 { XE_RTP_NAME("14019877138"),
655 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, 2004), ENGINE_CLASS(RENDER)),
656 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
657 },
658 { XE_RTP_NAME("14019386621"),
659 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
660 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
661 },
662 { XE_RTP_NAME("14019988906"),
663 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
664 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
665 },
666 { XE_RTP_NAME("18033852989"),
667 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
668 XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
669 },
670 { XE_RTP_NAME("15016589081"),
671 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)),
672 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
673 },
674 { XE_RTP_NAME("14026781792"),
675 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3510), ENGINE_CLASS(RENDER)),
676 XE_RTP_ACTIONS(SET(FF_MODE, DIS_TE_PATCH_CTRL))
677 },
678
679 /* DG1 */
680
681 { XE_RTP_NAME("1409044764"),
682 XE_RTP_RULES(PLATFORM(DG1)),
683 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3,
684 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN))
685 },
686 { XE_RTP_NAME("22010493298"),
687 XE_RTP_RULES(PLATFORM(DG1)),
688 XE_RTP_ACTIONS(SET(HIZ_CHICKEN,
689 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE))
690 },
691
692 /* DG2 */
693
694 { XE_RTP_NAME("16013271637"),
695 XE_RTP_RULES(PLATFORM(DG2)),
696 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,
697 MSC_MSAA_REODER_BUF_BYPASS_DISABLE))
698 },
699 { XE_RTP_NAME("14014947963"),
700 XE_RTP_RULES(PLATFORM(DG2)),
701 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
702 PREEMPTION_VERTEX_COUNT,
703 0x4000))
704 },
705 { XE_RTP_NAME("18018764978"),
706 XE_RTP_RULES(PLATFORM(DG2)),
707 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2,
708 SCOREBOARD_STALL_FLUSH_CONTROL))
709 },
710 { XE_RTP_NAME("18019271663"),
711 XE_RTP_RULES(PLATFORM(DG2)),
712 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
713 },
714
715 /* PVC */
716
717 { XE_RTP_NAME("16017236439"),
718 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),
719 FUNC(xe_rtp_match_even_instance)),
720 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0),
721 BCS_SWCTRL_DISABLE_256B,
722 XE_RTP_ACTION_FLAG(ENGINE_BASE))),
723 },
724
725 /* Xe_LPG */
726
727 { XE_RTP_NAME("18019271663"),
728 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
729 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
730 },
731
732 /* Xe2_LPG */
733
734 { XE_RTP_NAME("14021567978"),
735 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
736 ENGINE_CLASS(RENDER)),
737 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
738 },
739 { XE_RTP_NAME("14020756599"),
740 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR,
741 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)),
742 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
743 },
744 { XE_RTP_NAME("14021490052"),
745 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
746 XE_RTP_ACTIONS(SET(FF_MODE,
747 DIS_MESH_PARTIAL_AUTOSTRIP |
748 DIS_MESH_AUTOSTRIP),
749 SET(VFLSKPD,
750 DIS_PARTIAL_AUTOSTRIP |
751 DIS_AUTOSTRIP))
752 },
753
754 /* Xe2_HPG */
755
756 { XE_RTP_NAME("14020756599"),
757 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
758 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
759 },
760 { XE_RTP_NAME("14021490052"),
761 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
762 XE_RTP_ACTIONS(SET(FF_MODE,
763 DIS_MESH_PARTIAL_AUTOSTRIP |
764 DIS_MESH_AUTOSTRIP),
765 SET(VFLSKPD,
766 DIS_PARTIAL_AUTOSTRIP |
767 DIS_AUTOSTRIP))
768 },
769 { XE_RTP_NAME("22021007897"),
770 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
771 XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
772 },
773
774 /* Xe3_LPG */
775 { XE_RTP_NAME("14021490052"),
776 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
777 ENGINE_CLASS(RENDER)),
778 XE_RTP_ACTIONS(SET(FF_MODE,
779 DIS_MESH_PARTIAL_AUTOSTRIP |
780 DIS_MESH_AUTOSTRIP),
781 SET(VFLSKPD,
782 DIS_PARTIAL_AUTOSTRIP |
783 DIS_AUTOSTRIP))
784 },
785 { XE_RTP_NAME("22021007897"),
786 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)),
787 XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
788 },
789 { XE_RTP_NAME("14024681466"),
790 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)),
791 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, FAST_CLEAR_VALIGN_FIX))
792 },
793 { XE_RTP_NAME("15016589081"),
794 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
795 ENGINE_CLASS(RENDER)),
796 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
797 },
798 );
799
800 static const struct xe_rtp_entry oob_was_entries[] = {
801 #include <generated/xe_wa_oob.c>
802 };
803
804 static_assert(ARRAY_SIZE(oob_was_entries) == _XE_WA_OOB_COUNT);
805
806 VISIBLE_IF_KUNIT __maybe_unused const struct xe_rtp_table oob_was = {
807 .entries = oob_was_entries,
808 .n_entries = ARRAY_SIZE(oob_was_entries),
809 };
810 EXPORT_SYMBOL_IF_KUNIT(oob_was);
811
812 static const struct xe_rtp_entry device_oob_was_entries[] = {
813 #include <generated/xe_device_wa_oob.c>
814 };
815
816 static_assert(ARRAY_SIZE(device_oob_was_entries) == _XE_DEVICE_WA_OOB_COUNT);
817
818 VISIBLE_IF_KUNIT __maybe_unused const struct xe_rtp_table device_oob_was = {
819 .entries = device_oob_was_entries,
820 .n_entries = ARRAY_SIZE(device_oob_was_entries),
821 };
822 EXPORT_SYMBOL_IF_KUNIT(device_oob_was);
823
824 __diag_pop();
825
826 /**
827 * xe_wa_process_device_oob - process OOB workaround table
828 * @xe: device instance to process workarounds for
829 *
830 * process OOB workaround table for this device, marking in @xe the
831 * workarounds that are active.
832 */
833
xe_wa_process_device_oob(struct xe_device * xe)834 void xe_wa_process_device_oob(struct xe_device *xe)
835 {
836 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe);
837
838 xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, device_oob_was.n_entries);
839
840 xe->wa_active.oob_initialized = true;
841 xe_rtp_process(&ctx, &device_oob_was);
842 }
843
844 /**
845 * xe_wa_process_gt_oob - process GT OOB workaround table
846 * @gt: GT instance to process workarounds for
847 *
848 * Process OOB workaround table for this platform, marking in @gt the
849 * workarounds that are active.
850 */
xe_wa_process_gt_oob(struct xe_gt * gt)851 void xe_wa_process_gt_oob(struct xe_gt *gt)
852 {
853 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
854
855 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
856 oob_was.n_entries);
857 gt->wa_active.oob_initialized = true;
858 xe_rtp_process(&ctx, &oob_was);
859 }
860
861 /**
862 * xe_wa_process_gt - process GT workaround table
863 * @gt: GT instance to process workarounds for
864 *
865 * Process GT workaround table for this platform, saving in @gt all the
866 * workarounds that need to be applied at the GT level.
867 */
xe_wa_process_gt(struct xe_gt * gt)868 void xe_wa_process_gt(struct xe_gt *gt)
869 {
870 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
871
872 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
873 gt_was.n_entries);
874 xe_rtp_process_to_sr(&ctx, >_was, >->reg_sr, false);
875 }
876 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
877
878 /**
879 * xe_wa_process_engine - process engine workaround table
880 * @hwe: engine instance to process workarounds for
881 *
882 * Process engine workaround table for this platform, saving in @hwe all the
883 * workarounds that need to be applied at the engine level that match this
884 * engine.
885 */
xe_wa_process_engine(struct xe_hw_engine * hwe)886 void xe_wa_process_engine(struct xe_hw_engine *hwe)
887 {
888 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
889
890 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
891 engine_was.n_entries);
892 xe_rtp_process_to_sr(&ctx, &engine_was, &hwe->reg_sr, false);
893 }
894
895 /**
896 * xe_wa_process_lrc - process context workaround table
897 * @hwe: engine instance to process workarounds for
898 *
899 * Process context workaround table for this platform, saving in @hwe all the
900 * workarounds that need to be applied on context restore. These are workarounds
901 * touching registers that are part of the HW context image.
902 */
xe_wa_process_lrc(struct xe_hw_engine * hwe)903 void xe_wa_process_lrc(struct xe_hw_engine *hwe)
904 {
905 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
906
907 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
908 lrc_was.n_entries);
909 xe_rtp_process_to_sr(&ctx, &lrc_was, &hwe->reg_lrc, true);
910 }
911
912 /**
913 * xe_wa_device_init - initialize device with workaround oob bookkeeping
914 * @xe: Xe device instance to initialize
915 *
916 * Returns 0 for success, negative with error code otherwise
917 */
xe_wa_device_init(struct xe_device * xe)918 int xe_wa_device_init(struct xe_device *xe)
919 {
920 unsigned long *p;
921
922 p = drmm_kzalloc(&xe->drm,
923 sizeof(*p) * BITS_TO_LONGS(device_oob_was.n_entries),
924 GFP_KERNEL);
925
926 if (!p)
927 return -ENOMEM;
928
929 xe->wa_active.oob = p;
930
931 return 0;
932 }
933
934 /**
935 * xe_wa_gt_init - initialize gt with workaround bookkeeping
936 * @gt: GT instance to initialize
937 *
938 * Returns 0 for success, negative error code otherwise.
939 */
xe_wa_gt_init(struct xe_gt * gt)940 int xe_wa_gt_init(struct xe_gt *gt)
941 {
942 struct xe_device *xe = gt_to_xe(gt);
943 size_t n_oob, n_lrc, n_engine, n_gt, total;
944 unsigned long *p;
945
946 n_gt = BITS_TO_LONGS(gt_was.n_entries);
947 n_engine = BITS_TO_LONGS(engine_was.n_entries);
948 n_lrc = BITS_TO_LONGS(lrc_was.n_entries);
949 n_oob = BITS_TO_LONGS(oob_was.n_entries);
950 total = n_gt + n_engine + n_lrc + n_oob;
951
952 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
953 if (!p)
954 return -ENOMEM;
955
956 gt->wa_active.gt = p;
957 p += n_gt;
958 gt->wa_active.engine = p;
959 p += n_engine;
960 gt->wa_active.lrc = p;
961 p += n_lrc;
962 gt->wa_active.oob = p;
963
964 return 0;
965 }
966 ALLOW_ERROR_INJECTION(xe_wa_gt_init, ERRNO); /* See xe_pci_probe() */
967
xe_wa_device_dump(struct xe_device * xe,struct drm_printer * p)968 void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p)
969 {
970 size_t idx;
971
972 drm_printf(p, "Device OOB Workarounds\n");
973 for_each_set_bit(idx, xe->wa_active.oob, device_oob_was.n_entries)
974 if (device_oob_was.entries[idx].name)
975 drm_printf_indent(p, 1, "%s\n", device_oob_was.entries[idx].name);
976 }
977
978 /**
979 * xe_wa_gt_dump() - Dump GT workarounds into a drm printer.
980 * @gt: the &xe_gt
981 * @p: the &drm_printer
982 *
983 * Return: always 0.
984 */
xe_wa_gt_dump(struct xe_gt * gt,struct drm_printer * p)985 int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p)
986 {
987 size_t idx;
988
989 drm_printf(p, "GT Workarounds\n");
990 for_each_set_bit(idx, gt->wa_active.gt, gt_was.n_entries)
991 drm_printf_indent(p, 1, "%s\n", gt_was.entries[idx].name);
992
993 drm_puts(p, "\n");
994 drm_printf(p, "Engine Workarounds\n");
995 for_each_set_bit(idx, gt->wa_active.engine, engine_was.n_entries)
996 drm_printf_indent(p, 1, "%s\n", engine_was.entries[idx].name);
997
998 drm_puts(p, "\n");
999 drm_printf(p, "LRC Workarounds\n");
1000 for_each_set_bit(idx, gt->wa_active.lrc, lrc_was.n_entries)
1001 drm_printf_indent(p, 1, "%s\n", lrc_was.entries[idx].name);
1002
1003 drm_puts(p, "\n");
1004 drm_printf(p, "OOB Workarounds\n");
1005 for_each_set_bit(idx, gt->wa_active.oob, oob_was.n_entries)
1006 if (oob_was.entries[idx].name)
1007 drm_printf_indent(p, 1, "%s\n", oob_was.entries[idx].name);
1008 return 0;
1009 }
1010
1011 /*
1012 * Apply tile (non-GT, non-display) workarounds. Think very carefully before
1013 * adding anything to this function; most workarounds should be implemented
1014 * elsewhere. The programming here is primarily for sgunit/soc workarounds,
1015 * which are relatively rare. Since the registers these workarounds target are
1016 * outside the GT, they should only need to be applied once at device
1017 * probe/resume; they will not lose their values on any kind of GT or engine
1018 * reset.
1019 *
1020 * TODO: We may want to move this over to xe_rtp in the future once we have
1021 * enough workarounds to justify the work.
1022 */
xe_wa_apply_tile_workarounds(struct xe_tile * tile)1023 void xe_wa_apply_tile_workarounds(struct xe_tile *tile)
1024 {
1025 struct xe_mmio *mmio = &tile->mmio;
1026
1027 if (IS_SRIOV_VF(tile->xe))
1028 return;
1029
1030 if (XE_DEVICE_WA(tile->xe, 22010954014))
1031 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
1032 }
1033