1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 */
5
6 #include "xe_wa.h"
7
8 #include <drm/drm_managed.h>
9 #include <kunit/visibility.h>
10 #include <linux/compiler_types.h>
11 #include <linux/fault-inject.h>
12
13 #include <generated/xe_device_wa_oob.h>
14 #include <generated/xe_wa_oob.h>
15
16 #include "regs/xe_engine_regs.h"
17 #include "regs/xe_gt_regs.h"
18 #include "regs/xe_guc_regs.h"
19 #include "regs/xe_regs.h"
20 #include "xe_device_types.h"
21 #include "xe_force_wake.h"
22 #include "xe_gt_types.h"
23 #include "xe_hw_engine_types.h"
24 #include "xe_mmio.h"
25 #include "xe_platform_types.h"
26 #include "xe_rtp.h"
27 #include "xe_sriov.h"
28 #include "xe_step.h"
29
30 /**
31 * DOC: Hardware workarounds
32 *
33 * Hardware workarounds are register programming documented to be executed in
34 * the driver that fall outside of the normal programming sequences for a
35 * platform. There are some basic categories of workarounds, depending on
36 * how/when they are applied:
37 *
38 * - LRC workarounds: workarounds that touch registers that are
39 * saved/restored to/from the HW context image. The list is emitted (via Load
40 * Register Immediate commands) once when initializing the device and saved in
41 * the default context. That default context is then used on every context
42 * creation to have a "primed golden context", i.e. a context image that
43 * already contains the changes needed to all the registers. See
44 * drivers/gpu/drm/xe/xe_lrc.c for default context handling.
45 *
46 * - Engine workarounds: the list of these WAs is applied whenever the specific
47 * engine is reset. It's also possible that a set of engine classes share a
48 * common power domain and they are reset together. This happens on some
49 * platforms with render and compute engines. In this case (at least) one of
50 * them need to keeep the workaround programming: the approach taken in the
51 * driver is to tie those workarounds to the first compute/render engine that
52 * is registered. When executing with GuC submission, engine resets are
53 * outside of kernel driver control, hence the list of registers involved is
54 * written once, on engine initialization, and then passed to GuC, that
55 * saves/restores their values before/after the reset takes place. See
56 * drivers/gpu/drm/xe/xe_guc_ads.c for reference.
57 *
58 * - GT workarounds: the list of these WAs is applied whenever these registers
59 * revert to their default values: on GPU reset, suspend/resume [1]_, etc.
60 *
61 * - Register whitelist: some workarounds need to be implemented in userspace,
62 * but need to touch privileged registers. The whitelist in the kernel
63 * instructs the hardware to allow the access to happen. From the kernel side,
64 * this is just a special case of a MMIO workaround (as we write the list of
65 * these to/be-whitelisted registers to some special HW registers).
66 *
67 * - Workaround batchbuffers: buffers that get executed automatically by the
68 * hardware on every HW context restore. These buffers are created and
69 * programmed in the default context so the hardware always go through those
70 * programming sequences when switching contexts. The support for workaround
71 * batchbuffers is enabled via these hardware mechanisms:
72 *
73 * #. INDIRECT_CTX (also known as **mid context restore bb**): A batchbuffer
74 * and an offset are provided in the default context, pointing the hardware
75 * to jump to that location when that offset is reached in the context
76 * restore. When a context is being restored, this is executed after the
77 * ring context, in the middle (or beginning) of the engine context image.
78 *
79 * #. BB_PER_CTX_PTR (also known as **post context restore bb**): A
80 * batchbuffer is provided in the default context, pointing the hardware to
81 * a buffer to continue executing after the engine registers are restored
82 * in a context restore sequence.
83 *
84 * Below is the timeline for a context restore sequence:
85 *
86 * .. code::
87 *
88 * INDIRECT_CTX_OFFSET
89 * |----------->|
90 * .------------.------------.-------------.------------.--------------.-----------.
91 * |Ring | Engine | Mid-context | Engine | Post-context | Ring |
92 * |Restore | Restore (1)| BB Restore | Restore (2)| BB Restore | Execution |
93 * `------------'------------'-------------'------------'--------------'-----------'
94 *
95 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from
96 * a central place. Those are peppered around the rest of the code, as needed.
97 * There's a central place to control which workarounds are enabled:
98 * drivers/gpu/drm/xe/xe_wa_oob.rules for GT workarounds and
99 * drivers/gpu/drm/xe/xe_device_wa_oob.rules for device/SoC workarounds.
100 * These files only record which workarounds are enabled: during early device
101 * initialization those rules are evaluated and recorded by the driver. Then
102 * later the driver checks with ``XE_GT_WA()`` and ``XE_DEVICE_WA()`` to
103 * implement them.
104 *
105 * .. [1] Technically, some registers are powercontext saved & restored, so they
106 * survive a suspend/resume. In practice, writing them again is not too
107 * costly and simplifies things, so it's the approach taken in the driver.
108 *
109 * .. note::
110 * Hardware workarounds in xe work the same way as in i915, with the
111 * difference of how they are maintained in the code. In xe it uses the
112 * xe_rtp infrastructure so the workarounds can be kept in tables, following
113 * a more declarative approach rather than procedural.
114 */
115
116 #undef XE_REG_MCR
117 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
118
119 __diag_push();
120 __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
121
122 static const struct xe_rtp_entry_sr gt_was[] = {
123 { XE_RTP_NAME("14011060649"),
124 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),
125 ENGINE_CLASS(VIDEO_DECODE),
126 FUNC(xe_rtp_match_even_instance)),
127 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
128 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
129 },
130 { XE_RTP_NAME("14011059788"),
131 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
132 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
133 },
134 { XE_RTP_NAME("14015795083"),
135 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)),
136 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
137 },
138
139 /* DG1 */
140
141 { XE_RTP_NAME("1409420604"),
142 XE_RTP_RULES(PLATFORM(DG1)),
143 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
144 },
145 { XE_RTP_NAME("1408615072"),
146 XE_RTP_RULES(PLATFORM(DG1)),
147 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS))
148 },
149
150 /* DG2 */
151
152 { XE_RTP_NAME("22010523718"),
153 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
154 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))
155 },
156 { XE_RTP_NAME("14011006942"),
157 XE_RTP_RULES(SUBPLATFORM(DG2, G10)),
158 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))
159 },
160 { XE_RTP_NAME("14014830051"),
161 XE_RTP_RULES(PLATFORM(DG2)),
162 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))
163 },
164 { XE_RTP_NAME("18018781329"),
165 XE_RTP_RULES(PLATFORM(DG2)),
166 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
167 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
168 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
169 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
170 },
171 { XE_RTP_NAME("1509235366"),
172 XE_RTP_RULES(PLATFORM(DG2)),
173 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL,
174 INVALIDATION_BROADCAST_MODE_DIS |
175 GLOBAL_INVALIDATION_MODE))
176 },
177
178 /* PVC */
179
180 { XE_RTP_NAME("18018781329"),
181 XE_RTP_RULES(PLATFORM(PVC)),
182 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
183 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
184 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
185 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
186 },
187 { XE_RTP_NAME("16016694945"),
188 XE_RTP_RULES(PLATFORM(PVC)),
189 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC))
190 },
191
192 /* Xe_LPG */
193
194 { XE_RTP_NAME("14015795083"),
195 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)),
196 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))
197 },
198 { XE_RTP_NAME("14018575942"),
199 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
200 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
201 },
202 { XE_RTP_NAME("22016670082"),
203 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
204 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))
205 },
206
207 /* Xe_LPM+ */
208
209 { XE_RTP_NAME("16021867713"),
210 XE_RTP_RULES(MEDIA_VERSION(1300),
211 ENGINE_CLASS(VIDEO_DECODE)),
212 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
213 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
214 },
215 { XE_RTP_NAME("22016670082"),
216 XE_RTP_RULES(MEDIA_VERSION(1300)),
217 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
218 },
219
220 /* Xe2_LPM */
221
222 { XE_RTP_NAME("14017421178"),
223 XE_RTP_RULES(MEDIA_VERSION(2000),
224 ENGINE_CLASS(VIDEO_DECODE)),
225 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
226 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
227 },
228 { XE_RTP_NAME("16021867713"),
229 XE_RTP_RULES(MEDIA_VERSION(2000),
230 ENGINE_CLASS(VIDEO_DECODE)),
231 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
232 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
233 },
234 { XE_RTP_NAME("14019449301"),
235 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),
236 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
237 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
238 },
239
240 /* Xe2_HPG */
241
242 { XE_RTP_NAME("16025250150"),
243 XE_RTP_RULES(GRAPHICS_VERSION(2001)),
244 XE_RTP_ACTIONS(SET(LSN_VC_REG2,
245 LSN_LNI_WGT(1) |
246 LSN_LNE_WGT(1) |
247 LSN_DIM_X_WGT(1) |
248 LSN_DIM_Y_WGT(1) |
249 LSN_DIM_Z_WGT(1)))
250 },
251
252 /* Xe2_HPM */
253
254 { XE_RTP_NAME("16021867713"),
255 XE_RTP_RULES(MEDIA_VERSION(1301),
256 ENGINE_CLASS(VIDEO_DECODE)),
257 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
258 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
259 },
260 { XE_RTP_NAME("14019449301"),
261 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
262 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
263 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
264 },
265
266 /* Xe3_LPG */
267
268 { XE_RTP_NAME("14021871409"),
269 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)),
270 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS))
271 },
272
273 /* Xe3_LPM */
274
275 { XE_RTP_NAME("16021867713"),
276 XE_RTP_RULES(MEDIA_VERSION(3000),
277 ENGINE_CLASS(VIDEO_DECODE)),
278 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
279 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
280 },
281 { XE_RTP_NAME("16021865536"),
282 XE_RTP_RULES(MEDIA_VERSION(3000),
283 ENGINE_CLASS(VIDEO_DECODE)),
284 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
285 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
286 },
287 { XE_RTP_NAME("16021865536"),
288 XE_RTP_RULES(MEDIA_VERSION(3002),
289 ENGINE_CLASS(VIDEO_DECODE)),
290 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
291 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
292 },
293 { XE_RTP_NAME("16021867713"),
294 XE_RTP_RULES(MEDIA_VERSION(3002),
295 ENGINE_CLASS(VIDEO_DECODE)),
296 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
297 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
298 },
299 { XE_RTP_NAME("14021486841"),
300 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0),
301 ENGINE_CLASS(VIDEO_DECODE)),
302 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)),
303 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
304 },
305 { XE_RTP_NAME("16028005424"),
306 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005)),
307 XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
308 },
309 };
310
311 static const struct xe_rtp_entry_sr engine_was[] = {
312 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
313 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
314 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),
315 FF_TESSELATION_DOP_GATE_DISABLE))
316 },
317 { XE_RTP_NAME("1409804808"),
318 XE_RTP_RULES(GRAPHICS_VERSION(1200),
319 ENGINE_CLASS(RENDER),
320 IS_INTEGRATED),
321 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS))
322 },
323 { XE_RTP_NAME("14010229206, 1409085225"),
324 XE_RTP_RULES(GRAPHICS_VERSION(1200),
325 ENGINE_CLASS(RENDER),
326 IS_INTEGRATED),
327 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
328 },
329 { XE_RTP_NAME("1606931601"),
330 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
331 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ))
332 },
333 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),
334 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),
335 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE),
336 FF_DOP_CLOCK_GATE_DISABLE))
337 },
338 { XE_RTP_NAME("1406941453"),
339 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
340 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL))
341 },
342 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
343 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
344 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),
345 FFSC_PERCTX_PREEMPT_CTRL))
346 },
347
348 /* TGL */
349
350 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
351 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
352 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
353 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
354 RC_SEMA_IDLE_MSG_DISABLE))
355 },
356
357 /* RKL */
358
359 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
360 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
361 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
362 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
363 RC_SEMA_IDLE_MSG_DISABLE))
364 },
365
366 /* ADL-P */
367
368 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
369 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)),
370 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
371 WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
372 RC_SEMA_IDLE_MSG_DISABLE))
373 },
374
375 /* DG2 */
376
377 { XE_RTP_NAME("22013037850"),
378 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
379 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
380 DISABLE_128B_EVICTION_COMMAND_UDW))
381 },
382 { XE_RTP_NAME("22014226127"),
383 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
384 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
385 },
386 { XE_RTP_NAME("18017747507"),
387 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
388 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,
389 POLYGON_TRIFAN_LINELOOP_DISABLE))
390 },
391 { XE_RTP_NAME("22012826095, 22013059131"),
392 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
393 FUNC(xe_rtp_match_first_render_or_compute)),
394 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,
395 MAXREQS_PER_BANK,
396 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))
397 },
398 { XE_RTP_NAME("22013059131"),
399 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
400 FUNC(xe_rtp_match_first_render_or_compute)),
401 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
402 },
403 { XE_RTP_NAME("14015227452"),
404 XE_RTP_RULES(PLATFORM(DG2),
405 FUNC(xe_rtp_match_first_render_or_compute)),
406 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
407 },
408 { XE_RTP_NAME("18028616096"),
409 XE_RTP_RULES(PLATFORM(DG2),
410 FUNC(xe_rtp_match_first_render_or_compute)),
411 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
412 },
413 { XE_RTP_NAME("22015475538"),
414 XE_RTP_RULES(PLATFORM(DG2),
415 FUNC(xe_rtp_match_first_render_or_compute)),
416 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))
417 },
418 { XE_RTP_NAME("22012654132"),
419 XE_RTP_RULES(SUBPLATFORM(DG2, G11),
420 FUNC(xe_rtp_match_first_render_or_compute)),
421 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,
422 /*
423 * Register can't be read back for verification on
424 * DG2 due to Wa_14012342262
425 */
426 .read_mask = 0))
427 },
428 { XE_RTP_NAME("1509727124"),
429 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
430 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB))
431 },
432 { XE_RTP_NAME("22012856258"),
433 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
434 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))
435 },
436 { XE_RTP_NAME("22010960976, 14013347512"),
437 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
438 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,
439 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK))
440 },
441 { XE_RTP_NAME("14015150844"),
442 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),
443 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
444 XE_RTP_NOCHECK))
445 },
446
447 /* PVC */
448
449 { XE_RTP_NAME("22014226127"),
450 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
451 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))
452 },
453 { XE_RTP_NAME("14015227452"),
454 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),
455 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
456 },
457 { XE_RTP_NAME("18020744125"),
458 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute),
459 ENGINE_CLASS(COMPUTE)),
460 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0))
461 },
462 { XE_RTP_NAME("14014999345"),
463 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE),
464 GRAPHICS_STEP(B0, C0)),
465 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
466 },
467
468 /* Xe_LPG */
469
470 { XE_RTP_NAME("14017856879"),
471 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
472 FUNC(xe_rtp_match_first_render_or_compute)),
473 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH))
474 },
475 { XE_RTP_NAME("14015150844"),
476 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),
477 FUNC(xe_rtp_match_first_render_or_compute)),
478 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,
479 XE_RTP_NOCHECK))
480 },
481 { XE_RTP_NAME("14020495402"),
482 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274),
483 FUNC(xe_rtp_match_first_render_or_compute)),
484 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING))
485 },
486
487 /* Xe2_LPG */
488
489 { XE_RTP_NAME("18032247524"),
490 XE_RTP_RULES(GRAPHICS_VERSION(2004),
491 FUNC(xe_rtp_match_first_render_or_compute)),
492 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
493 },
494 { XE_RTP_NAME("16018712365"),
495 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
496 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
497 },
498 { XE_RTP_NAME("14020338487"),
499 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
500 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
501 },
502 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */
503 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004),
504 FUNC(xe_rtp_match_first_render_or_compute)),
505 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
506 },
507 { XE_RTP_NAME("14018471104"),
508 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
509 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
510 },
511 /*
512 * These two workarounds are the same, just applying to different
513 * engines. Although Wa_18032095049 (for the RCS) isn't required on
514 * all steppings, disabling these reports has no impact for our
515 * driver or the GuC, so we go ahead and treat it the same as
516 * Wa_16021639441 which does apply to all steppings.
517 */
518 { XE_RTP_NAME("18032095049, 16021639441"),
519 XE_RTP_RULES(GRAPHICS_VERSION(2004)),
520 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
521 GHWSP_CSB_REPORT_DIS |
522 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
523 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
524 },
525 { XE_RTP_NAME("16018610683"),
526 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),
527 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE))
528 },
529 { XE_RTP_NAME("14021402888"),
530 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
531 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
532 },
533 { XE_RTP_NAME("13012615864"),
534 XE_RTP_RULES(GRAPHICS_VERSION(2004),
535 FUNC(xe_rtp_match_first_render_or_compute)),
536 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
537 },
538
539 /* Xe2_HPG */
540
541 { XE_RTP_NAME("16018712365"),
542 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
543 FUNC(xe_rtp_match_first_render_or_compute)),
544 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))
545 },
546 { XE_RTP_NAME("16018737384"),
547 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
548 FUNC(xe_rtp_match_first_render_or_compute)),
549 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))
550 },
551 { XE_RTP_NAME("14020338487"),
552 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
553 FUNC(xe_rtp_match_first_render_or_compute)),
554 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
555 },
556 { XE_RTP_NAME("18032247524"),
557 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
558 FUNC(xe_rtp_match_first_render_or_compute)),
559 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))
560 },
561 { XE_RTP_NAME("14018471104"),
562 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
563 FUNC(xe_rtp_match_first_render_or_compute)),
564 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
565 },
566 /*
567 * Although this workaround isn't required for the RCS, disabling these
568 * reports has no impact for our driver or the GuC, so we go ahead and
569 * apply this to all engines for simplicity.
570 */
571 { XE_RTP_NAME("16021639441"),
572 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002)),
573 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
574 GHWSP_CSB_REPORT_DIS |
575 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
576 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
577 },
578 { XE_RTP_NAME("14019811474"),
579 XE_RTP_RULES(GRAPHICS_VERSION(2001),
580 FUNC(xe_rtp_match_first_render_or_compute)),
581 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
582 },
583 { XE_RTP_NAME("14021402888"),
584 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
585 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
586 },
587 { XE_RTP_NAME("14021821874, 14022954250"),
588 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
589 FUNC(xe_rtp_match_first_render_or_compute)),
590 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT))
591 },
592 { XE_RTP_NAME("13012615864"),
593 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
594 FUNC(xe_rtp_match_first_render_or_compute)),
595 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
596 },
597 { XE_RTP_NAME("18041344222"),
598 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
599 FUNC(xe_rtp_match_first_render_or_compute),
600 FUNC(xe_rtp_match_not_sriov_vf),
601 FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
602 XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
603 },
604
605 /* Xe2_LPM */
606
607 { XE_RTP_NAME("16021639441"),
608 XE_RTP_RULES(MEDIA_VERSION(2000)),
609 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
610 GHWSP_CSB_REPORT_DIS |
611 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
612 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
613 },
614
615 /* Xe2_HPM */
616
617 { XE_RTP_NAME("16021639441"),
618 XE_RTP_RULES(MEDIA_VERSION(1301)),
619 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
620 GHWSP_CSB_REPORT_DIS |
621 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
622 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
623 },
624
625 /* Xe3_LPG */
626
627 { XE_RTP_NAME("14021402888"),
628 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001),
629 FUNC(xe_rtp_match_first_render_or_compute)),
630 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
631 },
632 { XE_RTP_NAME("18034896535"),
633 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
634 FUNC(xe_rtp_match_first_render_or_compute)),
635 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))
636 },
637 { XE_RTP_NAME("16024792527"),
638 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
639 FUNC(xe_rtp_match_first_render_or_compute)),
640 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER,
641 SMP_FORCE_128B_OVERFETCH))
642 },
643 { XE_RTP_NAME("14023061436"),
644 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001),
645 FUNC(xe_rtp_match_first_render_or_compute), OR,
646 GRAPHICS_VERSION_RANGE(3003, 3005),
647 FUNC(xe_rtp_match_first_render_or_compute)),
648 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE))
649 },
650 { XE_RTP_NAME("13012615864"),
651 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), OR,
652 GRAPHICS_VERSION_RANGE(3003, 3005),
653 FUNC(xe_rtp_match_first_render_or_compute)),
654 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
655 },
656 { XE_RTP_NAME("16023105232"),
657 XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 3000), OR,
658 GRAPHICS_VERSION_RANGE(2001, 3001)),
659 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE,
660 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
661 },
662 { XE_RTP_NAME("14021402888"),
663 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3003, 3005), FUNC(xe_rtp_match_first_render_or_compute)),
664 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
665 },
666 { XE_RTP_NAME("18041344222"),
667 XE_RTP_RULES(GRAPHICS_VERSION(3000),
668 FUNC(xe_rtp_match_first_render_or_compute),
669 FUNC(xe_rtp_match_not_sriov_vf),
670 FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
671 XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
672 },
673 };
674
675 static const struct xe_rtp_entry_sr lrc_was[] = {
676 { XE_RTP_NAME("16011163337"),
677 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
678 /* read verification is ignored due to 1608008084. */
679 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
680 FF_MODE2_GS_TIMER_MASK,
681 FF_MODE2_GS_TIMER_224))
682 },
683 { XE_RTP_NAME("1604555607"),
684 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
685 /* read verification is ignored due to 1608008084. */
686 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,
687 FF_MODE2_TDS_TIMER_MASK,
688 FF_MODE2_TDS_TIMER_128))
689 },
690 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),
691 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
692 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,
693 DISABLE_CPS_AWARE_COLOR_PIPE))
694 },
695 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),
696 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
697 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),
698 PREEMPT_GPGPU_LEVEL_MASK,
699 PREEMPT_GPGPU_THREAD_GROUP_LEVEL))
700 },
701 { XE_RTP_NAME("1806527549"),
702 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
703 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE))
704 },
705 { XE_RTP_NAME("1606376872"),
706 XE_RTP_RULES(GRAPHICS_VERSION(1200)),
707 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))
708 },
709
710 /* DG1 */
711
712 { XE_RTP_NAME("1409044764"),
713 XE_RTP_RULES(PLATFORM(DG1)),
714 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3,
715 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN))
716 },
717 { XE_RTP_NAME("22010493298"),
718 XE_RTP_RULES(PLATFORM(DG1)),
719 XE_RTP_ACTIONS(SET(HIZ_CHICKEN,
720 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE))
721 },
722
723 /* DG2 */
724
725 { XE_RTP_NAME("16013271637"),
726 XE_RTP_RULES(PLATFORM(DG2)),
727 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,
728 MSC_MSAA_REODER_BUF_BYPASS_DISABLE))
729 },
730 { XE_RTP_NAME("14014947963"),
731 XE_RTP_RULES(PLATFORM(DG2)),
732 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,
733 PREEMPTION_VERTEX_COUNT,
734 0x4000))
735 },
736 { XE_RTP_NAME("18018764978"),
737 XE_RTP_RULES(PLATFORM(DG2)),
738 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2,
739 SCOREBOARD_STALL_FLUSH_CONTROL))
740 },
741 { XE_RTP_NAME("18019271663"),
742 XE_RTP_RULES(PLATFORM(DG2)),
743 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
744 },
745 { XE_RTP_NAME("14019877138"),
746 XE_RTP_RULES(PLATFORM(DG2)),
747 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
748 },
749
750 /* PVC */
751
752 { XE_RTP_NAME("16017236439"),
753 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),
754 FUNC(xe_rtp_match_even_instance)),
755 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0),
756 BCS_SWCTRL_DISABLE_256B,
757 XE_RTP_ACTION_FLAG(ENGINE_BASE))),
758 },
759
760 /* Xe_LPG */
761
762 { XE_RTP_NAME("18019271663"),
763 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),
764 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
765 },
766 { XE_RTP_NAME("14019877138"),
767 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)),
768 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
769 },
770
771 /* Xe2_LPG */
772
773 { XE_RTP_NAME("14019386621"),
774 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
775 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
776 },
777 { XE_RTP_NAME("14019877138"),
778 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
779 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
780 },
781 { XE_RTP_NAME("14019988906"),
782 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
783 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
784 },
785 { XE_RTP_NAME("18033852989"),
786 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
787 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
788 },
789 { XE_RTP_NAME("14021567978"),
790 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
791 ENGINE_CLASS(RENDER)),
792 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
793 },
794 { XE_RTP_NAME("14020756599"),
795 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR,
796 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)),
797 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
798 },
799 { XE_RTP_NAME("14021490052"),
800 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
801 XE_RTP_ACTIONS(SET(FF_MODE,
802 DIS_MESH_PARTIAL_AUTOSTRIP |
803 DIS_MESH_AUTOSTRIP),
804 SET(VFLSKPD,
805 DIS_PARTIAL_AUTOSTRIP |
806 DIS_AUTOSTRIP))
807 },
808 { XE_RTP_NAME("15016589081"),
809 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
810 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
811 },
812
813 /* Xe2_HPG */
814 { XE_RTP_NAME("15010599737"),
815 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
816 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN))
817 },
818 { XE_RTP_NAME("14019386621"),
819 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
820 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
821 },
822 { XE_RTP_NAME("14020756599"),
823 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
824 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
825 },
826 { XE_RTP_NAME("14019988906"),
827 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
828 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
829 },
830 { XE_RTP_NAME("14019877138"),
831 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
832 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
833 },
834 { XE_RTP_NAME("14021490052"),
835 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
836 XE_RTP_ACTIONS(SET(FF_MODE,
837 DIS_MESH_PARTIAL_AUTOSTRIP |
838 DIS_MESH_AUTOSTRIP),
839 SET(VFLSKPD,
840 DIS_PARTIAL_AUTOSTRIP |
841 DIS_AUTOSTRIP))
842 },
843 { XE_RTP_NAME("15016589081"),
844 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
845 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
846 },
847 { XE_RTP_NAME("22021007897"),
848 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
849 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
850 },
851 { XE_RTP_NAME("18033852989"),
852 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
853 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
854 },
855
856 /* Xe3_LPG */
857 { XE_RTP_NAME("14021490052"),
858 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
859 ENGINE_CLASS(RENDER)),
860 XE_RTP_ACTIONS(SET(FF_MODE,
861 DIS_MESH_PARTIAL_AUTOSTRIP |
862 DIS_MESH_AUTOSTRIP),
863 SET(VFLSKPD,
864 DIS_PARTIAL_AUTOSTRIP |
865 DIS_AUTOSTRIP))
866 },
867 { XE_RTP_NAME("22021007897"),
868 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)),
869 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
870 },
871 { XE_RTP_NAME("14024681466"),
872 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)),
873 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, FAST_CLEAR_VALIGN_FIX))
874 },
875 { XE_RTP_NAME("15016589081"),
876 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
877 ENGINE_CLASS(RENDER)),
878 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
879 },
880 };
881
882 static __maybe_unused const struct xe_rtp_entry oob_was[] = {
883 #include <generated/xe_wa_oob.c>
884 {}
885 };
886
887 static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
888
889 static __maybe_unused const struct xe_rtp_entry device_oob_was[] = {
890 #include <generated/xe_device_wa_oob.c>
891 {}
892 };
893
894 static_assert(ARRAY_SIZE(device_oob_was) - 1 == _XE_DEVICE_WA_OOB_COUNT);
895
896 __diag_pop();
897
898 /**
899 * xe_wa_process_device_oob - process OOB workaround table
900 * @xe: device instance to process workarounds for
901 *
902 * process OOB workaround table for this device, marking in @xe the
903 * workarounds that are active.
904 */
905
xe_wa_process_device_oob(struct xe_device * xe)906 void xe_wa_process_device_oob(struct xe_device *xe)
907 {
908 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe);
909
910 xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was));
911
912 xe->wa_active.oob_initialized = true;
913 xe_rtp_process(&ctx, device_oob_was);
914 }
915
916 /**
917 * xe_wa_process_gt_oob - process GT OOB workaround table
918 * @gt: GT instance to process workarounds for
919 *
920 * Process OOB workaround table for this platform, marking in @gt the
921 * workarounds that are active.
922 */
xe_wa_process_gt_oob(struct xe_gt * gt)923 void xe_wa_process_gt_oob(struct xe_gt *gt)
924 {
925 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
926
927 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob,
928 ARRAY_SIZE(oob_was));
929 gt->wa_active.oob_initialized = true;
930 xe_rtp_process(&ctx, oob_was);
931 }
932
933 /**
934 * xe_wa_process_gt - process GT workaround table
935 * @gt: GT instance to process workarounds for
936 *
937 * Process GT workaround table for this platform, saving in @gt all the
938 * workarounds that need to be applied at the GT level.
939 */
xe_wa_process_gt(struct xe_gt * gt)940 void xe_wa_process_gt(struct xe_gt *gt)
941 {
942 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);
943
944 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt,
945 ARRAY_SIZE(gt_was));
946 xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was), >->reg_sr);
947 }
948 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);
949
950 /**
951 * xe_wa_process_engine - process engine workaround table
952 * @hwe: engine instance to process workarounds for
953 *
954 * Process engine workaround table for this platform, saving in @hwe all the
955 * workarounds that need to be applied at the engine level that match this
956 * engine.
957 */
xe_wa_process_engine(struct xe_hw_engine * hwe)958 void xe_wa_process_engine(struct xe_hw_engine *hwe)
959 {
960 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
961
962 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine,
963 ARRAY_SIZE(engine_was));
964 xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was), &hwe->reg_sr);
965 }
966
967 /**
968 * xe_wa_process_lrc - process context workaround table
969 * @hwe: engine instance to process workarounds for
970 *
971 * Process context workaround table for this platform, saving in @hwe all the
972 * workarounds that need to be applied on context restore. These are workarounds
973 * touching registers that are part of the HW context image.
974 */
xe_wa_process_lrc(struct xe_hw_engine * hwe)975 void xe_wa_process_lrc(struct xe_hw_engine *hwe)
976 {
977 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
978
979 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc,
980 ARRAY_SIZE(lrc_was));
981 xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was), &hwe->reg_lrc);
982 }
983
984 /**
985 * xe_wa_device_init - initialize device with workaround oob bookkeeping
986 * @xe: Xe device instance to initialize
987 *
988 * Returns 0 for success, negative with error code otherwise
989 */
xe_wa_device_init(struct xe_device * xe)990 int xe_wa_device_init(struct xe_device *xe)
991 {
992 unsigned long *p;
993
994 p = drmm_kzalloc(&xe->drm,
995 sizeof(*p) * BITS_TO_LONGS(ARRAY_SIZE(device_oob_was)),
996 GFP_KERNEL);
997
998 if (!p)
999 return -ENOMEM;
1000
1001 xe->wa_active.oob = p;
1002
1003 return 0;
1004 }
1005
1006 /**
1007 * xe_wa_gt_init - initialize gt with workaround bookkeeping
1008 * @gt: GT instance to initialize
1009 *
1010 * Returns 0 for success, negative error code otherwise.
1011 */
xe_wa_gt_init(struct xe_gt * gt)1012 int xe_wa_gt_init(struct xe_gt *gt)
1013 {
1014 struct xe_device *xe = gt_to_xe(gt);
1015 size_t n_oob, n_lrc, n_engine, n_gt, total;
1016 unsigned long *p;
1017
1018 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));
1019 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));
1020 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));
1021 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));
1022 total = n_gt + n_engine + n_lrc + n_oob;
1023
1024 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL);
1025 if (!p)
1026 return -ENOMEM;
1027
1028 gt->wa_active.gt = p;
1029 p += n_gt;
1030 gt->wa_active.engine = p;
1031 p += n_engine;
1032 gt->wa_active.lrc = p;
1033 p += n_lrc;
1034 gt->wa_active.oob = p;
1035
1036 return 0;
1037 }
1038 ALLOW_ERROR_INJECTION(xe_wa_gt_init, ERRNO); /* See xe_pci_probe() */
1039
xe_wa_device_dump(struct xe_device * xe,struct drm_printer * p)1040 void xe_wa_device_dump(struct xe_device *xe, struct drm_printer *p)
1041 {
1042 size_t idx;
1043
1044 drm_printf(p, "Device OOB Workarounds\n");
1045 for_each_set_bit(idx, xe->wa_active.oob, ARRAY_SIZE(device_oob_was))
1046 if (device_oob_was[idx].name)
1047 drm_printf_indent(p, 1, "%s\n", device_oob_was[idx].name);
1048 }
1049
1050 /**
1051 * xe_wa_gt_dump() - Dump GT workarounds into a drm printer.
1052 * @gt: the &xe_gt
1053 * @p: the &drm_printer
1054 *
1055 * Return: always 0.
1056 */
xe_wa_gt_dump(struct xe_gt * gt,struct drm_printer * p)1057 int xe_wa_gt_dump(struct xe_gt *gt, struct drm_printer *p)
1058 {
1059 size_t idx;
1060
1061 drm_printf(p, "GT Workarounds\n");
1062 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was))
1063 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);
1064
1065 drm_puts(p, "\n");
1066 drm_printf(p, "Engine Workarounds\n");
1067 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was))
1068 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);
1069
1070 drm_puts(p, "\n");
1071 drm_printf(p, "LRC Workarounds\n");
1072 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was))
1073 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);
1074
1075 drm_puts(p, "\n");
1076 drm_printf(p, "OOB Workarounds\n");
1077 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
1078 if (oob_was[idx].name)
1079 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
1080 return 0;
1081 }
1082
1083 /*
1084 * Apply tile (non-GT, non-display) workarounds. Think very carefully before
1085 * adding anything to this function; most workarounds should be implemented
1086 * elsewhere. The programming here is primarily for sgunit/soc workarounds,
1087 * which are relatively rare. Since the registers these workarounds target are
1088 * outside the GT, they should only need to be applied once at device
1089 * probe/resume; they will not lose their values on any kind of GT or engine
1090 * reset.
1091 *
1092 * TODO: We may want to move this over to xe_rtp in the future once we have
1093 * enough workarounds to justify the work.
1094 */
xe_wa_apply_tile_workarounds(struct xe_tile * tile)1095 void xe_wa_apply_tile_workarounds(struct xe_tile *tile)
1096 {
1097 struct xe_mmio *mmio = &tile->mmio;
1098
1099 if (IS_SRIOV_VF(tile->xe))
1100 return;
1101
1102 if (XE_DEVICE_WA(tile->xe, 22010954014))
1103 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
1104 }
1105