1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* Copyright 2017-2019 NXP */
3
4 #include <linux/unaligned.h>
5 #include <linux/module.h>
6 #include <linux/of.h>
7 #include <linux/of_platform.h>
8 #include <linux/of_net.h>
9 #include <linux/pcs-lynx.h>
10 #include "enetc_ierb.h"
11 #include "enetc_pf_common.h"
12
13 #define ENETC_DRV_NAME_STR "ENETC PF driver"
14
enetc_pf_get_primary_mac_addr(struct enetc_hw * hw,int si,u8 * addr)15 static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr)
16 {
17 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si));
18 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si));
19
20 put_unaligned_le32(upper, addr);
21 put_unaligned_le16(lower, addr + 4);
22 }
23
enetc_pf_set_primary_mac_addr(struct enetc_hw * hw,int si,const u8 * addr)24 static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si,
25 const u8 *addr)
26 {
27 u32 upper = get_unaligned_le32(addr);
28 u16 lower = get_unaligned_le16(addr + 4);
29
30 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si));
31 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si));
32 }
33
enetc_pf_create_pcs(struct enetc_pf * pf,struct mii_bus * bus)34 static struct phylink_pcs *enetc_pf_create_pcs(struct enetc_pf *pf,
35 struct mii_bus *bus)
36 {
37 return lynx_pcs_create_mdiodev(bus, 0);
38 }
39
enetc_pf_destroy_pcs(struct phylink_pcs * pcs)40 static void enetc_pf_destroy_pcs(struct phylink_pcs *pcs)
41 {
42 lynx_pcs_destroy(pcs);
43 }
44
enetc_set_isol_vlan(struct enetc_hw * hw,int si,u16 vlan,u8 qos)45 static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos)
46 {
47 u32 val = 0;
48
49 if (vlan)
50 val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan;
51
52 enetc_port_wr(hw, ENETC_PSIVLANR(si), val);
53 }
54
enetc_add_mac_addr_em_filter(struct enetc_mac_filter * filter,const unsigned char * addr)55 static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter,
56 const unsigned char *addr)
57 {
58 /* add exact match addr */
59 ether_addr_copy(filter->mac_addr, addr);
60 filter->mac_addr_cnt++;
61 }
62
enetc_sync_mac_filters(struct enetc_pf * pf)63 static void enetc_sync_mac_filters(struct enetc_pf *pf)
64 {
65 struct enetc_mac_filter *f = pf->mac_filter;
66 struct enetc_si *si = pf->si;
67 int i, pos;
68
69 pos = EMETC_MAC_ADDR_FILT_RES;
70
71 for (i = 0; i < MADDR_TYPE; i++, f++) {
72 bool em = (f->mac_addr_cnt == 1) && (i == UC);
73 bool clear = !f->mac_addr_cnt;
74 u64 hash;
75
76 if (clear) {
77 if (i == UC) {
78 enetc_clear_mac_flt_entry(si, pos);
79 enetc_set_si_uc_hash_filter(si, 0, 0);
80 } else {
81 enetc_set_si_mc_hash_filter(si, 0, 0);
82 }
83
84 continue;
85 }
86
87 /* exact match filter */
88 if (em) {
89 int err;
90
91 enetc_set_si_uc_hash_filter(si, 0, 0);
92
93 err = enetc_set_mac_flt_entry(si, pos, f->mac_addr,
94 BIT(0));
95 if (!err)
96 continue;
97
98 /* fallback to HT filtering */
99 dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n",
100 err);
101 }
102
103 bitmap_to_arr64(&hash, f->mac_hash_table,
104 ENETC_MADDR_HASH_TBL_SZ);
105 /* hash table filter, clear EM filter for UC entries */
106 if (i == UC) {
107 enetc_clear_mac_flt_entry(si, pos);
108 enetc_set_si_uc_hash_filter(si, 0, hash);
109 } else {
110 enetc_set_si_mc_hash_filter(si, 0, hash);
111 }
112 }
113 }
114
enetc_pf_set_rx_mode(struct net_device * ndev)115 static void enetc_pf_set_rx_mode(struct net_device *ndev)
116 {
117 struct enetc_ndev_priv *priv = netdev_priv(ndev);
118 struct enetc_pf *pf = enetc_si_priv(priv->si);
119 bool uprom = false, mprom = false;
120 struct enetc_mac_filter *filter;
121 struct netdev_hw_addr *ha;
122 bool em;
123
124 if (ndev->flags & IFF_PROMISC) {
125 /* enable promisc mode for SI0 (PF) */
126 uprom = true;
127 mprom = true;
128 } else if (ndev->flags & IFF_ALLMULTI) {
129 /* enable multi cast promisc mode for SI0 (PF) */
130 mprom = true;
131 }
132
133 /* first 2 filter entries belong to PF */
134 if (!uprom) {
135 /* Update unicast filters */
136 filter = &pf->mac_filter[UC];
137 enetc_reset_mac_addr_filter(filter);
138
139 em = (netdev_uc_count(ndev) == 1);
140 netdev_for_each_uc_addr(ha, ndev) {
141 if (em) {
142 enetc_add_mac_addr_em_filter(filter, ha->addr);
143 break;
144 }
145
146 enetc_add_mac_addr_ht_filter(filter, ha->addr);
147 }
148 }
149
150 if (!mprom) {
151 /* Update multicast filters */
152 filter = &pf->mac_filter[MC];
153 enetc_reset_mac_addr_filter(filter);
154
155 netdev_for_each_mc_addr(ha, ndev) {
156 if (!is_multicast_ether_addr(ha->addr))
157 continue;
158
159 enetc_add_mac_addr_ht_filter(filter, ha->addr);
160 }
161 }
162
163 if (!uprom || !mprom)
164 /* update PF entries */
165 enetc_sync_mac_filters(pf);
166
167 enetc_set_si_uc_promisc(priv->si, 0, uprom);
168 enetc_set_si_mc_promisc(priv->si, 0, mprom);
169 }
170
enetc_set_loopback(struct net_device * ndev,bool en)171 static void enetc_set_loopback(struct net_device *ndev, bool en)
172 {
173 struct enetc_ndev_priv *priv = netdev_priv(ndev);
174 struct enetc_si *si = priv->si;
175 u32 reg;
176
177 reg = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
178 if (reg & ENETC_PM0_IFM_RG) {
179 /* RGMII mode */
180 reg = (reg & ~ENETC_PM0_IFM_RLP) |
181 (en ? ENETC_PM0_IFM_RLP : 0);
182 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, reg);
183 } else {
184 /* assume SGMII mode */
185 reg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
186 reg = (reg & ~ENETC_PM0_CMD_XGLP) |
187 (en ? ENETC_PM0_CMD_XGLP : 0);
188 reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |
189 (en ? ENETC_PM0_CMD_PHY_TX_EN : 0);
190 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, reg);
191 }
192 }
193
enetc_pf_set_vf_mac(struct net_device * ndev,int vf,u8 * mac)194 static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac)
195 {
196 struct enetc_ndev_priv *priv = netdev_priv(ndev);
197 struct enetc_pf *pf = enetc_si_priv(priv->si);
198 struct enetc_vf_state *vf_state;
199
200 if (vf >= pf->total_vfs)
201 return -EINVAL;
202
203 if (!is_valid_ether_addr(mac))
204 return -EADDRNOTAVAIL;
205
206 vf_state = &pf->vf_state[vf];
207
208 mutex_lock(&vf_state->lock);
209 vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC;
210 enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac);
211 mutex_unlock(&vf_state->lock);
212
213 return 0;
214 }
215
enetc_pf_set_vf_vlan(struct net_device * ndev,int vf,u16 vlan,u8 qos,__be16 proto)216 static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan,
217 u8 qos, __be16 proto)
218 {
219 struct enetc_ndev_priv *priv = netdev_priv(ndev);
220 struct enetc_pf *pf = enetc_si_priv(priv->si);
221
222 if (priv->si->errata & ENETC_ERR_VLAN_ISOL)
223 return -EOPNOTSUPP;
224
225 if (vf >= pf->total_vfs)
226 return -EINVAL;
227
228 if (proto != htons(ETH_P_8021Q))
229 /* only C-tags supported for now */
230 return -EPROTONOSUPPORT;
231
232 enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos);
233 return 0;
234 }
235
enetc_pf_set_vf_spoofchk(struct net_device * ndev,int vf,bool en)236 static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en)
237 {
238 struct enetc_ndev_priv *priv = netdev_priv(ndev);
239 struct enetc_pf *pf = enetc_si_priv(priv->si);
240 u32 cfgr;
241
242 if (vf >= pf->total_vfs)
243 return -EINVAL;
244
245 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1));
246 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0);
247 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr);
248
249 return 0;
250 }
251
enetc_port_assign_rfs_entries(struct enetc_si * si)252 static void enetc_port_assign_rfs_entries(struct enetc_si *si)
253 {
254 struct enetc_pf *pf = enetc_si_priv(si);
255 struct enetc_hw *hw = &si->hw;
256 int num_entries, vf_entries, i;
257 u32 val;
258
259 /* split RFS entries between functions */
260 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
261 num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val);
262 vf_entries = num_entries / (pf->total_vfs + 1);
263
264 for (i = 0; i < pf->total_vfs; i++)
265 enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries);
266 enetc_port_wr(hw, ENETC_PSIRFSCFGR(0),
267 num_entries - vf_entries * pf->total_vfs);
268
269 /* enable RFS on port */
270 enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE);
271 }
272
enetc_port_get_caps(struct enetc_si * si)273 static void enetc_port_get_caps(struct enetc_si *si)
274 {
275 struct enetc_hw *hw = &si->hw;
276 u32 val;
277
278 val = enetc_port_rd(hw, ENETC_PCAPR0);
279
280 if (val & ENETC_PCAPR0_QBV)
281 si->hw_features |= ENETC_SI_F_QBV;
282
283 if (val & ENETC_PCAPR0_QBU)
284 si->hw_features |= ENETC_SI_F_QBU;
285
286 if (val & ENETC_PCAPR0_PSFP)
287 si->hw_features |= ENETC_SI_F_PSFP;
288 }
289
enetc_port_si_configure(struct enetc_si * si)290 static void enetc_port_si_configure(struct enetc_si *si)
291 {
292 struct enetc_pf *pf = enetc_si_priv(si);
293 struct enetc_hw *hw = &si->hw;
294 int num_rings, i;
295 u32 val;
296
297 enetc_port_get_caps(si);
298
299 val = enetc_port_rd(hw, ENETC_PCAPR0);
300 num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val));
301
302 val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS);
303 val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS);
304
305 if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) {
306 val = ENETC_PSICFGR0_SET_TXBDR(num_rings);
307 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
308
309 dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n",
310 num_rings, ENETC_PF_NUM_RINGS);
311
312 num_rings = 0;
313 }
314
315 /* Add default one-time settings for SI0 (PF) */
316 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
317
318 enetc_port_wr(hw, ENETC_PSICFGR0(0), val);
319
320 if (num_rings)
321 num_rings -= ENETC_PF_NUM_RINGS;
322
323 /* Configure the SIs for each available VF */
324 val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
325 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE;
326
327 if (num_rings) {
328 num_rings /= pf->total_vfs;
329 val |= ENETC_PSICFGR0_SET_TXBDR(num_rings);
330 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
331 }
332
333 for (i = 0; i < pf->total_vfs; i++)
334 enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val);
335
336 /* Port level VLAN settings */
337 val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
338 enetc_port_wr(hw, ENETC_PVCLCTR, val);
339 /* use outer tag for VLAN filtering */
340 enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);
341 }
342
enetc_set_ptcmsdur(struct enetc_hw * hw,u32 * max_sdu)343 void enetc_set_ptcmsdur(struct enetc_hw *hw, u32 *max_sdu)
344 {
345 int tc;
346
347 for (tc = 0; tc < 8; tc++) {
348 u32 val = ENETC_MAC_MAXFRM_SIZE;
349
350 if (max_sdu[tc])
351 val = max_sdu[tc] + VLAN_ETH_HLEN;
352
353 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), val);
354 }
355 }
356
enetc_reset_ptcmsdur(struct enetc_hw * hw)357 void enetc_reset_ptcmsdur(struct enetc_hw *hw)
358 {
359 int tc;
360
361 for (tc = 0; tc < 8; tc++)
362 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE);
363 }
364
enetc_configure_port_mac(struct enetc_si * si)365 static void enetc_configure_port_mac(struct enetc_si *si)
366 {
367 struct enetc_hw *hw = &si->hw;
368
369 enetc_port_mac_wr(si, ENETC_PM0_MAXFRM,
370 ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));
371
372 enetc_reset_ptcmsdur(hw);
373
374 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
375 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
376
377 /* On LS1028A, the MAC RX FIFO defaults to 2, which is too high
378 * and may lead to RX lock-up under traffic. Set it to 1 instead,
379 * as recommended by the hardware team.
380 */
381 enetc_port_mac_wr(si, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
382 }
383
enetc_mac_config(struct enetc_si * si,phy_interface_t phy_mode)384 static void enetc_mac_config(struct enetc_si *si, phy_interface_t phy_mode)
385 {
386 u32 val;
387
388 if (phy_interface_mode_is_rgmii(phy_mode)) {
389 val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
390 val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK);
391 val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;
392 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
393 }
394
395 if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
396 val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;
397 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
398 }
399 }
400
enetc_mac_enable(struct enetc_si * si,bool en)401 static void enetc_mac_enable(struct enetc_si *si, bool en)
402 {
403 u32 val = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
404
405 val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
406 val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;
407
408 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, val);
409 }
410
enetc_configure_port(struct enetc_pf * pf)411 static void enetc_configure_port(struct enetc_pf *pf)
412 {
413 struct enetc_hw *hw = &pf->si->hw;
414
415 enetc_configure_port_mac(pf->si);
416
417 enetc_port_si_configure(pf->si);
418
419 /* set up hash key */
420 enetc_set_default_rss_key(pf);
421
422 /* split up RFS entries */
423 enetc_port_assign_rfs_entries(pf->si);
424 /* enforce VLAN promisc mode for all SIs */
425 for (int i = 0; i < pf->total_vfs + 1; i++)
426 enetc_set_si_vlan_promisc(pf->si, i, true);
427
428 enetc_port_wr(hw, ENETC_PSIPMMR, 0);
429
430 /* enable port */
431 enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN);
432 }
433
enetc_pf_set_features(struct net_device * ndev,netdev_features_t features)434 static int enetc_pf_set_features(struct net_device *ndev,
435 netdev_features_t features)
436 {
437 netdev_features_t changed = ndev->features ^ features;
438 struct enetc_ndev_priv *priv = netdev_priv(ndev);
439 int err;
440
441 if (changed & NETIF_F_HW_TC) {
442 err = enetc_set_psfp(ndev, !!(features & NETIF_F_HW_TC));
443 if (err)
444 return err;
445 }
446
447 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
448 bool promisc = !(features & NETIF_F_HW_VLAN_CTAG_FILTER);
449
450 enetc_set_si_vlan_promisc(priv->si, 0, promisc);
451 }
452
453 if (changed & NETIF_F_LOOPBACK)
454 enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK));
455
456 enetc_set_features(ndev, features);
457
458 return 0;
459 }
460
enetc_pf_setup_tc(struct net_device * ndev,enum tc_setup_type type,void * type_data)461 static int enetc_pf_setup_tc(struct net_device *ndev, enum tc_setup_type type,
462 void *type_data)
463 {
464 switch (type) {
465 case TC_QUERY_CAPS:
466 return enetc_qos_query_caps(ndev, type_data);
467 case TC_SETUP_QDISC_MQPRIO:
468 return enetc_setup_tc_mqprio(ndev, type_data);
469 case TC_SETUP_QDISC_TAPRIO:
470 return enetc_setup_tc_taprio(ndev, type_data);
471 case TC_SETUP_QDISC_CBS:
472 return enetc_setup_tc_cbs(ndev, type_data);
473 case TC_SETUP_QDISC_ETF:
474 return enetc_setup_tc_txtime(ndev, type_data);
475 case TC_SETUP_BLOCK:
476 return enetc_setup_tc_psfp(ndev, type_data);
477 default:
478 return -EOPNOTSUPP;
479 }
480 }
481
482 static const struct net_device_ops enetc_ndev_ops = {
483 .ndo_open = enetc_open,
484 .ndo_stop = enetc_close,
485 .ndo_start_xmit = enetc_xmit,
486 .ndo_get_stats = enetc_get_stats,
487 .ndo_set_mac_address = enetc_pf_set_mac_addr,
488 .ndo_set_rx_mode = enetc_pf_set_rx_mode,
489 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid,
490 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid,
491 .ndo_set_vf_mac = enetc_pf_set_vf_mac,
492 .ndo_set_vf_vlan = enetc_pf_set_vf_vlan,
493 .ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk,
494 .ndo_set_features = enetc_pf_set_features,
495 .ndo_eth_ioctl = enetc_ioctl,
496 .ndo_setup_tc = enetc_pf_setup_tc,
497 .ndo_bpf = enetc_setup_bpf,
498 .ndo_xdp_xmit = enetc_xdp_xmit,
499 .ndo_hwtstamp_get = enetc_hwtstamp_get,
500 .ndo_hwtstamp_set = enetc_hwtstamp_set,
501 };
502
503 static struct phylink_pcs *
enetc_pl_mac_select_pcs(struct phylink_config * config,phy_interface_t iface)504 enetc_pl_mac_select_pcs(struct phylink_config *config, phy_interface_t iface)
505 {
506 struct enetc_pf *pf = phylink_to_enetc_pf(config);
507
508 return pf->pcs;
509 }
510
enetc_pl_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)511 static void enetc_pl_mac_config(struct phylink_config *config,
512 unsigned int mode,
513 const struct phylink_link_state *state)
514 {
515 struct enetc_pf *pf = phylink_to_enetc_pf(config);
516
517 enetc_mac_config(pf->si, state->interface);
518 }
519
enetc_force_rgmii_mac(struct enetc_si * si,int speed,int duplex)520 static void enetc_force_rgmii_mac(struct enetc_si *si, int speed, int duplex)
521 {
522 u32 old_val, val;
523
524 old_val = val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE);
525
526 if (speed == SPEED_1000) {
527 val &= ~ENETC_PM0_IFM_SSP_MASK;
528 val |= ENETC_PM0_IFM_SSP_1000;
529 } else if (speed == SPEED_100) {
530 val &= ~ENETC_PM0_IFM_SSP_MASK;
531 val |= ENETC_PM0_IFM_SSP_100;
532 } else if (speed == SPEED_10) {
533 val &= ~ENETC_PM0_IFM_SSP_MASK;
534 val |= ENETC_PM0_IFM_SSP_10;
535 }
536
537 if (duplex == DUPLEX_FULL)
538 val |= ENETC_PM0_IFM_FULL_DPX;
539 else
540 val &= ~ENETC_PM0_IFM_FULL_DPX;
541
542 if (val == old_val)
543 return;
544
545 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val);
546 }
547
enetc_pl_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)548 static void enetc_pl_mac_link_up(struct phylink_config *config,
549 struct phy_device *phy, unsigned int mode,
550 phy_interface_t interface, int speed,
551 int duplex, bool tx_pause, bool rx_pause)
552 {
553 struct enetc_pf *pf = phylink_to_enetc_pf(config);
554 u32 pause_off_thresh = 0, pause_on_thresh = 0;
555 u32 init_quanta = 0, refresh_quanta = 0;
556 struct enetc_hw *hw = &pf->si->hw;
557 struct enetc_si *si = pf->si;
558 struct enetc_ndev_priv *priv;
559 u32 cmd_cfg;
560
561 priv = netdev_priv(pf->si->ndev);
562
563 if (pf->si->hw_features & ENETC_SI_F_QBV)
564 enetc_sched_speed_set(priv, speed);
565
566 if (!phylink_autoneg_inband(mode) &&
567 phy_interface_mode_is_rgmii(interface))
568 enetc_force_rgmii_mac(si, speed, duplex);
569
570 /* Flow control */
571 enetc_set_congestion_mode(priv, tx_pause);
572
573 if (tx_pause) {
574 /* When the port first enters congestion, send a PAUSE request
575 * with the maximum number of quanta. When the port exits
576 * congestion, it will automatically send a PAUSE frame with
577 * zero quanta.
578 */
579 init_quanta = 0xffff;
580
581 /* Also, set up the refresh timer to send follow-up PAUSE
582 * frames at half the quanta value, in case the congestion
583 * condition persists.
584 */
585 refresh_quanta = 0xffff / 2;
586
587 /* Start emitting PAUSE frames when 3 large frames (or more
588 * smaller frames) have accumulated in the FIFO waiting to be
589 * DMAed to the RX ring.
590 */
591 pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE;
592 pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE;
593 }
594
595 enetc_port_mac_wr(si, ENETC_PM0_PAUSE_QUANTA, init_quanta);
596 enetc_port_mac_wr(si, ENETC_PM0_PAUSE_THRESH, refresh_quanta);
597 enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);
598 enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);
599
600 cmd_cfg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG);
601
602 if (rx_pause)
603 cmd_cfg &= ~ENETC_PM0_PAUSE_IGN;
604 else
605 cmd_cfg |= ENETC_PM0_PAUSE_IGN;
606
607 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, cmd_cfg);
608
609 enetc_mac_enable(si, true);
610
611 if (si->hw_features & ENETC_SI_F_QBU)
612 enetc_mm_link_state_update(priv, true);
613 }
614
enetc_pl_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)615 static void enetc_pl_mac_link_down(struct phylink_config *config,
616 unsigned int mode,
617 phy_interface_t interface)
618 {
619 struct enetc_pf *pf = phylink_to_enetc_pf(config);
620 struct enetc_si *si = pf->si;
621 struct enetc_ndev_priv *priv;
622
623 priv = netdev_priv(si->ndev);
624
625 if (si->hw_features & ENETC_SI_F_QBU)
626 enetc_mm_link_state_update(priv, false);
627
628 enetc_mac_enable(si, false);
629 }
630
631 static const struct phylink_mac_ops enetc_mac_phylink_ops = {
632 .mac_select_pcs = enetc_pl_mac_select_pcs,
633 .mac_config = enetc_pl_mac_config,
634 .mac_link_up = enetc_pl_mac_link_up,
635 .mac_link_down = enetc_pl_mac_link_down,
636 };
637
638 /* Initialize the entire shared memory for the flow steering entries
639 * of this port (PF + VFs)
640 */
enetc_init_port_rfs_memory(struct enetc_si * si)641 static int enetc_init_port_rfs_memory(struct enetc_si *si)
642 {
643 struct enetc_cmd_rfse rfse = {0};
644 struct enetc_hw *hw = &si->hw;
645 int num_rfs, i, err = 0;
646 u32 val;
647
648 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
649 num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val);
650
651 for (i = 0; i < num_rfs; i++) {
652 err = enetc_set_fs_entry(si, &rfse, i);
653 if (err)
654 break;
655 }
656
657 return err;
658 }
659
enetc_init_port_rss_memory(struct enetc_si * si)660 static int enetc_init_port_rss_memory(struct enetc_si *si)
661 {
662 struct enetc_hw *hw = &si->hw;
663 int num_rss, err;
664 int *rss_table;
665 u32 val;
666
667 val = enetc_port_rd(hw, ENETC_PRSSCAPR);
668 num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val);
669 if (!num_rss)
670 return 0;
671
672 rss_table = kzalloc_objs(*rss_table, num_rss);
673 if (!rss_table)
674 return -ENOMEM;
675
676 err = enetc_set_rss_table(si, rss_table, num_rss);
677
678 kfree(rss_table);
679
680 return err;
681 }
682
enetc_pf_register_with_ierb(struct pci_dev * pdev)683 static int enetc_pf_register_with_ierb(struct pci_dev *pdev)
684 {
685 struct platform_device *ierb_pdev;
686 struct device_node *ierb_node;
687 int ret;
688
689 ierb_node = of_find_compatible_node(NULL, NULL,
690 "fsl,ls1028a-enetc-ierb");
691 if (!ierb_node)
692 return -ENODEV;
693
694 if (!of_device_is_available(ierb_node)) {
695 of_node_put(ierb_node);
696 return -ENODEV;
697 }
698
699 ierb_pdev = of_find_device_by_node(ierb_node);
700 of_node_put(ierb_node);
701
702 if (!ierb_pdev)
703 return -EPROBE_DEFER;
704
705 ret = enetc_ierb_register_pf(ierb_pdev, pdev);
706
707 put_device(&ierb_pdev->dev);
708
709 return ret;
710 }
711
712 static const struct enetc_si_ops enetc_psi_ops = {
713 .get_rss_table = enetc_get_rss_table,
714 .set_rss_table = enetc_set_rss_table,
715 };
716
enetc_psi_create(struct pci_dev * pdev)717 static struct enetc_si *enetc_psi_create(struct pci_dev *pdev)
718 {
719 struct enetc_si *si;
720 int err;
721
722 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(struct enetc_pf));
723 if (err) {
724 dev_err_probe(&pdev->dev, err, "PCI probing failed\n");
725 goto out;
726 }
727
728 si = pci_get_drvdata(pdev);
729 if (!si->hw.port || !si->hw.global) {
730 err = -ENODEV;
731 dev_err(&pdev->dev, "could not map PF space, probing a VF?\n");
732 goto out_pci_remove;
733 }
734
735 si->revision = enetc_get_ip_revision(&si->hw);
736 si->ops = &enetc_psi_ops;
737 err = enetc_get_driver_data(si);
738 if (err) {
739 dev_err(&pdev->dev, "Could not get PF driver data\n");
740 goto out_pci_remove;
741 }
742
743 err = enetc_setup_cbdr(si);
744 if (err)
745 goto out_pci_remove;
746
747 err = enetc_init_port_rfs_memory(si);
748 if (err) {
749 dev_err(&pdev->dev, "Failed to initialize RFS memory\n");
750 goto out_teardown_cbdr;
751 }
752
753 err = enetc_init_port_rss_memory(si);
754 if (err) {
755 dev_err(&pdev->dev, "Failed to initialize RSS memory\n");
756 goto out_teardown_cbdr;
757 }
758
759 return si;
760
761 out_teardown_cbdr:
762 enetc_teardown_cbdr(si);
763 out_pci_remove:
764 enetc_pci_remove(pdev);
765 out:
766 return ERR_PTR(err);
767 }
768
enetc_psi_destroy(struct pci_dev * pdev)769 static void enetc_psi_destroy(struct pci_dev *pdev)
770 {
771 struct enetc_si *si = pci_get_drvdata(pdev);
772
773 enetc_teardown_cbdr(si);
774 enetc_pci_remove(pdev);
775 }
776
777 static const struct enetc_pf_ops enetc_pf_ops = {
778 .set_si_primary_mac = enetc_pf_set_primary_mac_addr,
779 .get_si_primary_mac = enetc_pf_get_primary_mac_addr,
780 .create_pcs = enetc_pf_create_pcs,
781 .destroy_pcs = enetc_pf_destroy_pcs,
782 .enable_psfp = enetc_psfp_enable,
783 };
784
enetc_pf_probe(struct pci_dev * pdev,const struct pci_device_id * ent)785 static int enetc_pf_probe(struct pci_dev *pdev,
786 const struct pci_device_id *ent)
787 {
788 struct device_node *node = pdev->dev.of_node;
789 struct enetc_ndev_priv *priv;
790 struct net_device *ndev;
791 struct enetc_si *si;
792 struct enetc_pf *pf;
793 int err;
794
795 err = enetc_pf_register_with_ierb(pdev);
796 if (err == -EPROBE_DEFER)
797 return err;
798 if (err)
799 dev_warn(&pdev->dev,
800 "Could not register with IERB driver: %pe, please update the device tree\n",
801 ERR_PTR(err));
802
803 si = enetc_psi_create(pdev);
804 if (IS_ERR(si)) {
805 err = PTR_ERR(si);
806 goto err_psi_create;
807 }
808
809 pf = enetc_si_priv(si);
810 pf->si = si;
811 pf->ops = &enetc_pf_ops;
812
813 err = enetc_init_sriov_resources(pf);
814 if (err)
815 goto err_init_sriov_resources;
816
817 err = enetc_setup_mac_addresses(node, pf);
818 if (err)
819 goto err_setup_mac_addresses;
820
821 enetc_configure_port(pf);
822
823 enetc_get_si_caps(si);
824
825 ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS);
826 if (!ndev) {
827 err = -ENOMEM;
828 dev_err(&pdev->dev, "netdev creation failed\n");
829 goto err_alloc_netdev;
830 }
831
832 enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops);
833
834 priv = netdev_priv(ndev);
835
836 mutex_init(&priv->mm_lock);
837
838 enetc_init_si_rings_params(priv);
839
840 err = enetc_alloc_si_resources(priv);
841 if (err) {
842 dev_err(&pdev->dev, "SI resource alloc failed\n");
843 goto err_alloc_si_res;
844 }
845
846 err = enetc_configure_si(priv);
847 if (err) {
848 dev_err(&pdev->dev, "Failed to configure SI\n");
849 goto err_config_si;
850 }
851
852 err = enetc_alloc_msix(priv);
853 if (err) {
854 dev_err(&pdev->dev, "MSIX alloc failed\n");
855 goto err_alloc_msix;
856 }
857
858 err = of_get_phy_mode(node, &pf->if_mode);
859 if (err) {
860 dev_err(&pdev->dev, "Failed to read PHY mode\n");
861 goto err_phy_mode;
862 }
863
864 err = enetc_mdiobus_create(pf, node);
865 if (err)
866 goto err_mdiobus_create;
867
868 err = enetc_phylink_create(priv, node, &enetc_mac_phylink_ops);
869 if (err)
870 goto err_phylink_create;
871
872 err = register_netdev(ndev);
873 if (err)
874 goto err_reg_netdev;
875
876 return 0;
877
878 err_reg_netdev:
879 enetc_phylink_destroy(priv);
880 err_phylink_create:
881 enetc_mdiobus_destroy(pf);
882 err_mdiobus_create:
883 err_phy_mode:
884 enetc_free_msix(priv);
885 err_config_si:
886 err_alloc_msix:
887 enetc_free_si_resources(priv);
888 err_alloc_si_res:
889 si->ndev = NULL;
890 free_netdev(ndev);
891 err_alloc_netdev:
892 err_setup_mac_addresses:
893 err_init_sriov_resources:
894 enetc_psi_destroy(pdev);
895 err_psi_create:
896 return err;
897 }
898
enetc_pf_remove(struct pci_dev * pdev)899 static void enetc_pf_remove(struct pci_dev *pdev)
900 {
901 struct enetc_si *si = pci_get_drvdata(pdev);
902 struct enetc_pf *pf = enetc_si_priv(si);
903 struct enetc_ndev_priv *priv;
904
905 priv = netdev_priv(si->ndev);
906
907 if (pf->num_vfs)
908 enetc_sriov_configure(pdev, 0);
909
910 unregister_netdev(si->ndev);
911
912 enetc_phylink_destroy(priv);
913 enetc_mdiobus_destroy(pf);
914
915 enetc_free_msix(priv);
916
917 enetc_free_si_resources(priv);
918
919 free_netdev(si->ndev);
920 enetc_psi_destroy(pdev);
921 }
922
enetc_fixup_clear_rss_rfs(struct pci_dev * pdev)923 static void enetc_fixup_clear_rss_rfs(struct pci_dev *pdev)
924 {
925 struct device_node *node = pdev->dev.of_node;
926 struct enetc_si *si;
927
928 /* Only apply quirk for disabled functions. For the ones
929 * that are enabled, enetc_pf_probe() will apply it.
930 */
931 if (node && of_device_is_available(node))
932 return;
933
934 si = enetc_psi_create(pdev);
935 if (!IS_ERR(si))
936 enetc_psi_destroy(pdev);
937 }
938 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF,
939 enetc_fixup_clear_rss_rfs);
940
941 static const struct pci_device_id enetc_pf_id_table[] = {
942 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) },
943 { 0, } /* End of table. */
944 };
945 MODULE_DEVICE_TABLE(pci, enetc_pf_id_table);
946
947 static struct pci_driver enetc_pf_driver = {
948 .name = KBUILD_MODNAME,
949 .id_table = enetc_pf_id_table,
950 .probe = enetc_pf_probe,
951 .remove = enetc_pf_remove,
952 #ifdef CONFIG_PCI_IOV
953 .sriov_configure = enetc_sriov_configure,
954 #endif
955 };
956 module_pci_driver(enetc_pf_driver);
957
958 MODULE_DESCRIPTION(ENETC_DRV_NAME_STR);
959 MODULE_LICENSE("Dual BSD/GPL");
960