1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* Copyright 2017-2019 NXP */ 3 4 #include <linux/unaligned.h> 5 #include <linux/module.h> 6 #include <linux/of.h> 7 #include <linux/of_platform.h> 8 #include <linux/of_net.h> 9 #include <linux/pcs-lynx.h> 10 #include "enetc_ierb.h" 11 #include "enetc_pf_common.h" 12 13 #define ENETC_DRV_NAME_STR "ENETC PF driver" 14 15 static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr) 16 { 17 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si)); 18 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si)); 19 20 put_unaligned_le32(upper, addr); 21 put_unaligned_le16(lower, addr + 4); 22 } 23 24 static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si, 25 const u8 *addr) 26 { 27 u32 upper = get_unaligned_le32(addr); 28 u16 lower = get_unaligned_le16(addr + 4); 29 30 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si)); 31 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si)); 32 } 33 34 static struct phylink_pcs *enetc_pf_create_pcs(struct enetc_pf *pf, 35 struct mii_bus *bus) 36 { 37 return lynx_pcs_create_mdiodev(bus, 0); 38 } 39 40 static void enetc_pf_destroy_pcs(struct phylink_pcs *pcs) 41 { 42 lynx_pcs_destroy(pcs); 43 } 44 45 static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map) 46 { 47 u32 val = enetc_port_rd(hw, ENETC_PSIPVMR); 48 49 val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL); 50 enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val); 51 } 52 53 static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx) 54 { 55 pf->vlan_promisc_simap |= BIT(si_idx); 56 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap); 57 } 58 59 static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx) 60 { 61 pf->vlan_promisc_simap &= ~BIT(si_idx); 62 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap); 63 } 64 65 static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos) 66 { 67 u32 val = 0; 68 69 if (vlan) 70 val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan; 71 72 enetc_port_wr(hw, ENETC_PSIVLANR(si), val); 73 } 74 75 static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter, 76 const unsigned char *addr) 77 { 78 /* add exact match addr */ 79 ether_addr_copy(filter->mac_addr, addr); 80 filter->mac_addr_cnt++; 81 } 82 83 static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type) 84 { 85 bool err = si->errata & ENETC_ERR_UCMCSWP; 86 87 if (type == UC) { 88 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0); 89 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0); 90 } else { /* MC */ 91 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0); 92 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0); 93 } 94 } 95 96 static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type, 97 unsigned long hash) 98 { 99 bool err = si->errata & ENETC_ERR_UCMCSWP; 100 101 if (type == UC) { 102 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 103 lower_32_bits(hash)); 104 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 105 upper_32_bits(hash)); 106 } else { /* MC */ 107 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 108 lower_32_bits(hash)); 109 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 110 upper_32_bits(hash)); 111 } 112 } 113 114 static void enetc_sync_mac_filters(struct enetc_pf *pf) 115 { 116 struct enetc_mac_filter *f = pf->mac_filter; 117 struct enetc_si *si = pf->si; 118 int i, pos; 119 120 pos = EMETC_MAC_ADDR_FILT_RES; 121 122 for (i = 0; i < MADDR_TYPE; i++, f++) { 123 bool em = (f->mac_addr_cnt == 1) && (i == UC); 124 bool clear = !f->mac_addr_cnt; 125 126 if (clear) { 127 if (i == UC) 128 enetc_clear_mac_flt_entry(si, pos); 129 130 enetc_clear_mac_ht_flt(si, 0, i); 131 continue; 132 } 133 134 /* exact match filter */ 135 if (em) { 136 int err; 137 138 enetc_clear_mac_ht_flt(si, 0, UC); 139 140 err = enetc_set_mac_flt_entry(si, pos, f->mac_addr, 141 BIT(0)); 142 if (!err) 143 continue; 144 145 /* fallback to HT filtering */ 146 dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n", 147 err); 148 } 149 150 /* hash table filter, clear EM filter for UC entries */ 151 if (i == UC) 152 enetc_clear_mac_flt_entry(si, pos); 153 154 enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table); 155 } 156 } 157 158 static void enetc_pf_set_rx_mode(struct net_device *ndev) 159 { 160 struct enetc_ndev_priv *priv = netdev_priv(ndev); 161 struct enetc_pf *pf = enetc_si_priv(priv->si); 162 struct enetc_hw *hw = &priv->si->hw; 163 bool uprom = false, mprom = false; 164 struct enetc_mac_filter *filter; 165 struct netdev_hw_addr *ha; 166 u32 psipmr = 0; 167 bool em; 168 169 if (ndev->flags & IFF_PROMISC) { 170 /* enable promisc mode for SI0 (PF) */ 171 psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0); 172 uprom = true; 173 mprom = true; 174 } else if (ndev->flags & IFF_ALLMULTI) { 175 /* enable multi cast promisc mode for SI0 (PF) */ 176 psipmr = ENETC_PSIPMR_SET_MP(0); 177 mprom = true; 178 } 179 180 /* first 2 filter entries belong to PF */ 181 if (!uprom) { 182 /* Update unicast filters */ 183 filter = &pf->mac_filter[UC]; 184 enetc_reset_mac_addr_filter(filter); 185 186 em = (netdev_uc_count(ndev) == 1); 187 netdev_for_each_uc_addr(ha, ndev) { 188 if (em) { 189 enetc_add_mac_addr_em_filter(filter, ha->addr); 190 break; 191 } 192 193 enetc_add_mac_addr_ht_filter(filter, ha->addr); 194 } 195 } 196 197 if (!mprom) { 198 /* Update multicast filters */ 199 filter = &pf->mac_filter[MC]; 200 enetc_reset_mac_addr_filter(filter); 201 202 netdev_for_each_mc_addr(ha, ndev) { 203 if (!is_multicast_ether_addr(ha->addr)) 204 continue; 205 206 enetc_add_mac_addr_ht_filter(filter, ha->addr); 207 } 208 } 209 210 if (!uprom || !mprom) 211 /* update PF entries */ 212 enetc_sync_mac_filters(pf); 213 214 psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) & 215 ~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0)); 216 enetc_port_wr(hw, ENETC_PSIPMR, psipmr); 217 } 218 219 static void enetc_set_loopback(struct net_device *ndev, bool en) 220 { 221 struct enetc_ndev_priv *priv = netdev_priv(ndev); 222 struct enetc_si *si = priv->si; 223 u32 reg; 224 225 reg = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE); 226 if (reg & ENETC_PM0_IFM_RG) { 227 /* RGMII mode */ 228 reg = (reg & ~ENETC_PM0_IFM_RLP) | 229 (en ? ENETC_PM0_IFM_RLP : 0); 230 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, reg); 231 } else { 232 /* assume SGMII mode */ 233 reg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG); 234 reg = (reg & ~ENETC_PM0_CMD_XGLP) | 235 (en ? ENETC_PM0_CMD_XGLP : 0); 236 reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) | 237 (en ? ENETC_PM0_CMD_PHY_TX_EN : 0); 238 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, reg); 239 } 240 } 241 242 static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac) 243 { 244 struct enetc_ndev_priv *priv = netdev_priv(ndev); 245 struct enetc_pf *pf = enetc_si_priv(priv->si); 246 struct enetc_vf_state *vf_state; 247 248 if (vf >= pf->total_vfs) 249 return -EINVAL; 250 251 if (!is_valid_ether_addr(mac)) 252 return -EADDRNOTAVAIL; 253 254 vf_state = &pf->vf_state[vf]; 255 256 mutex_lock(&vf_state->lock); 257 vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC; 258 enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac); 259 mutex_unlock(&vf_state->lock); 260 261 return 0; 262 } 263 264 static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, 265 u8 qos, __be16 proto) 266 { 267 struct enetc_ndev_priv *priv = netdev_priv(ndev); 268 struct enetc_pf *pf = enetc_si_priv(priv->si); 269 270 if (priv->si->errata & ENETC_ERR_VLAN_ISOL) 271 return -EOPNOTSUPP; 272 273 if (vf >= pf->total_vfs) 274 return -EINVAL; 275 276 if (proto != htons(ETH_P_8021Q)) 277 /* only C-tags supported for now */ 278 return -EPROTONOSUPPORT; 279 280 enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos); 281 return 0; 282 } 283 284 static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en) 285 { 286 struct enetc_ndev_priv *priv = netdev_priv(ndev); 287 struct enetc_pf *pf = enetc_si_priv(priv->si); 288 u32 cfgr; 289 290 if (vf >= pf->total_vfs) 291 return -EINVAL; 292 293 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1)); 294 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0); 295 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr); 296 297 return 0; 298 } 299 300 static void enetc_port_assign_rfs_entries(struct enetc_si *si) 301 { 302 struct enetc_pf *pf = enetc_si_priv(si); 303 struct enetc_hw *hw = &si->hw; 304 int num_entries, vf_entries, i; 305 u32 val; 306 307 /* split RFS entries between functions */ 308 val = enetc_port_rd(hw, ENETC_PRFSCAPR); 309 num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val); 310 vf_entries = num_entries / (pf->total_vfs + 1); 311 312 for (i = 0; i < pf->total_vfs; i++) 313 enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries); 314 enetc_port_wr(hw, ENETC_PSIRFSCFGR(0), 315 num_entries - vf_entries * pf->total_vfs); 316 317 /* enable RFS on port */ 318 enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE); 319 } 320 321 static void enetc_port_get_caps(struct enetc_si *si) 322 { 323 struct enetc_hw *hw = &si->hw; 324 u32 val; 325 326 val = enetc_port_rd(hw, ENETC_PCAPR0); 327 328 if (val & ENETC_PCAPR0_QBV) 329 si->hw_features |= ENETC_SI_F_QBV; 330 331 if (val & ENETC_PCAPR0_QBU) 332 si->hw_features |= ENETC_SI_F_QBU; 333 334 if (val & ENETC_PCAPR0_PSFP) 335 si->hw_features |= ENETC_SI_F_PSFP; 336 } 337 338 static void enetc_port_si_configure(struct enetc_si *si) 339 { 340 struct enetc_pf *pf = enetc_si_priv(si); 341 struct enetc_hw *hw = &si->hw; 342 int num_rings, i; 343 u32 val; 344 345 enetc_port_get_caps(si); 346 347 val = enetc_port_rd(hw, ENETC_PCAPR0); 348 num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val)); 349 350 val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS); 351 val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS); 352 353 if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) { 354 val = ENETC_PSICFGR0_SET_TXBDR(num_rings); 355 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings); 356 357 dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n", 358 num_rings, ENETC_PF_NUM_RINGS); 359 360 num_rings = 0; 361 } 362 363 /* Add default one-time settings for SI0 (PF) */ 364 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 365 366 enetc_port_wr(hw, ENETC_PSICFGR0(0), val); 367 368 if (num_rings) 369 num_rings -= ENETC_PF_NUM_RINGS; 370 371 /* Configure the SIs for each available VF */ 372 val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 373 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE; 374 375 if (num_rings) { 376 num_rings /= pf->total_vfs; 377 val |= ENETC_PSICFGR0_SET_TXBDR(num_rings); 378 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings); 379 } 380 381 for (i = 0; i < pf->total_vfs; i++) 382 enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val); 383 384 /* Port level VLAN settings */ 385 val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 386 enetc_port_wr(hw, ENETC_PVCLCTR, val); 387 /* use outer tag for VLAN filtering */ 388 enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS); 389 } 390 391 void enetc_set_ptcmsdur(struct enetc_hw *hw, u32 *max_sdu) 392 { 393 int tc; 394 395 for (tc = 0; tc < 8; tc++) { 396 u32 val = ENETC_MAC_MAXFRM_SIZE; 397 398 if (max_sdu[tc]) 399 val = max_sdu[tc] + VLAN_ETH_HLEN; 400 401 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), val); 402 } 403 } 404 405 void enetc_reset_ptcmsdur(struct enetc_hw *hw) 406 { 407 int tc; 408 409 for (tc = 0; tc < 8; tc++) 410 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE); 411 } 412 413 static void enetc_configure_port_mac(struct enetc_si *si) 414 { 415 struct enetc_hw *hw = &si->hw; 416 417 enetc_port_mac_wr(si, ENETC_PM0_MAXFRM, 418 ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE)); 419 420 enetc_reset_ptcmsdur(hw); 421 422 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN | 423 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC); 424 425 /* On LS1028A, the MAC RX FIFO defaults to 2, which is too high 426 * and may lead to RX lock-up under traffic. Set it to 1 instead, 427 * as recommended by the hardware team. 428 */ 429 enetc_port_mac_wr(si, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL); 430 } 431 432 static void enetc_mac_config(struct enetc_si *si, phy_interface_t phy_mode) 433 { 434 u32 val; 435 436 if (phy_interface_mode_is_rgmii(phy_mode)) { 437 val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE); 438 val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK); 439 val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG; 440 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val); 441 } 442 443 if (phy_mode == PHY_INTERFACE_MODE_USXGMII) { 444 val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII; 445 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val); 446 } 447 } 448 449 static void enetc_mac_enable(struct enetc_si *si, bool en) 450 { 451 u32 val = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG); 452 453 val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); 454 val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0; 455 456 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, val); 457 } 458 459 static void enetc_configure_port(struct enetc_pf *pf) 460 { 461 struct enetc_hw *hw = &pf->si->hw; 462 463 enetc_configure_port_mac(pf->si); 464 465 enetc_port_si_configure(pf->si); 466 467 /* set up hash key */ 468 enetc_set_default_rss_key(pf); 469 470 /* split up RFS entries */ 471 enetc_port_assign_rfs_entries(pf->si); 472 473 /* enforce VLAN promisc mode for all SIs */ 474 pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL; 475 enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap); 476 477 enetc_port_wr(hw, ENETC_PSIPMR, 0); 478 479 /* enable port */ 480 enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN); 481 } 482 483 static int enetc_pf_set_features(struct net_device *ndev, 484 netdev_features_t features) 485 { 486 netdev_features_t changed = ndev->features ^ features; 487 struct enetc_ndev_priv *priv = netdev_priv(ndev); 488 int err; 489 490 if (changed & NETIF_F_HW_TC) { 491 err = enetc_set_psfp(ndev, !!(features & NETIF_F_HW_TC)); 492 if (err) 493 return err; 494 } 495 496 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 497 struct enetc_pf *pf = enetc_si_priv(priv->si); 498 499 if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER)) 500 enetc_disable_si_vlan_promisc(pf, 0); 501 else 502 enetc_enable_si_vlan_promisc(pf, 0); 503 } 504 505 if (changed & NETIF_F_LOOPBACK) 506 enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK)); 507 508 enetc_set_features(ndev, features); 509 510 return 0; 511 } 512 513 static int enetc_pf_setup_tc(struct net_device *ndev, enum tc_setup_type type, 514 void *type_data) 515 { 516 switch (type) { 517 case TC_QUERY_CAPS: 518 return enetc_qos_query_caps(ndev, type_data); 519 case TC_SETUP_QDISC_MQPRIO: 520 return enetc_setup_tc_mqprio(ndev, type_data); 521 case TC_SETUP_QDISC_TAPRIO: 522 return enetc_setup_tc_taprio(ndev, type_data); 523 case TC_SETUP_QDISC_CBS: 524 return enetc_setup_tc_cbs(ndev, type_data); 525 case TC_SETUP_QDISC_ETF: 526 return enetc_setup_tc_txtime(ndev, type_data); 527 case TC_SETUP_BLOCK: 528 return enetc_setup_tc_psfp(ndev, type_data); 529 default: 530 return -EOPNOTSUPP; 531 } 532 } 533 534 static const struct net_device_ops enetc_ndev_ops = { 535 .ndo_open = enetc_open, 536 .ndo_stop = enetc_close, 537 .ndo_start_xmit = enetc_xmit, 538 .ndo_get_stats = enetc_get_stats, 539 .ndo_set_mac_address = enetc_pf_set_mac_addr, 540 .ndo_set_rx_mode = enetc_pf_set_rx_mode, 541 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid, 542 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid, 543 .ndo_set_vf_mac = enetc_pf_set_vf_mac, 544 .ndo_set_vf_vlan = enetc_pf_set_vf_vlan, 545 .ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk, 546 .ndo_set_features = enetc_pf_set_features, 547 .ndo_eth_ioctl = enetc_ioctl, 548 .ndo_setup_tc = enetc_pf_setup_tc, 549 .ndo_bpf = enetc_setup_bpf, 550 .ndo_xdp_xmit = enetc_xdp_xmit, 551 .ndo_hwtstamp_get = enetc_hwtstamp_get, 552 .ndo_hwtstamp_set = enetc_hwtstamp_set, 553 }; 554 555 static struct phylink_pcs * 556 enetc_pl_mac_select_pcs(struct phylink_config *config, phy_interface_t iface) 557 { 558 struct enetc_pf *pf = phylink_to_enetc_pf(config); 559 560 return pf->pcs; 561 } 562 563 static void enetc_pl_mac_config(struct phylink_config *config, 564 unsigned int mode, 565 const struct phylink_link_state *state) 566 { 567 struct enetc_pf *pf = phylink_to_enetc_pf(config); 568 569 enetc_mac_config(pf->si, state->interface); 570 } 571 572 static void enetc_force_rgmii_mac(struct enetc_si *si, int speed, int duplex) 573 { 574 u32 old_val, val; 575 576 old_val = val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE); 577 578 if (speed == SPEED_1000) { 579 val &= ~ENETC_PM0_IFM_SSP_MASK; 580 val |= ENETC_PM0_IFM_SSP_1000; 581 } else if (speed == SPEED_100) { 582 val &= ~ENETC_PM0_IFM_SSP_MASK; 583 val |= ENETC_PM0_IFM_SSP_100; 584 } else if (speed == SPEED_10) { 585 val &= ~ENETC_PM0_IFM_SSP_MASK; 586 val |= ENETC_PM0_IFM_SSP_10; 587 } 588 589 if (duplex == DUPLEX_FULL) 590 val |= ENETC_PM0_IFM_FULL_DPX; 591 else 592 val &= ~ENETC_PM0_IFM_FULL_DPX; 593 594 if (val == old_val) 595 return; 596 597 enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val); 598 } 599 600 static void enetc_pl_mac_link_up(struct phylink_config *config, 601 struct phy_device *phy, unsigned int mode, 602 phy_interface_t interface, int speed, 603 int duplex, bool tx_pause, bool rx_pause) 604 { 605 struct enetc_pf *pf = phylink_to_enetc_pf(config); 606 u32 pause_off_thresh = 0, pause_on_thresh = 0; 607 u32 init_quanta = 0, refresh_quanta = 0; 608 struct enetc_hw *hw = &pf->si->hw; 609 struct enetc_si *si = pf->si; 610 struct enetc_ndev_priv *priv; 611 u32 rbmr, cmd_cfg; 612 int idx; 613 614 priv = netdev_priv(pf->si->ndev); 615 616 if (pf->si->hw_features & ENETC_SI_F_QBV) 617 enetc_sched_speed_set(priv, speed); 618 619 if (!phylink_autoneg_inband(mode) && 620 phy_interface_mode_is_rgmii(interface)) 621 enetc_force_rgmii_mac(si, speed, duplex); 622 623 /* Flow control */ 624 for (idx = 0; idx < priv->num_rx_rings; idx++) { 625 rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR); 626 627 if (tx_pause) 628 rbmr |= ENETC_RBMR_CM; 629 else 630 rbmr &= ~ENETC_RBMR_CM; 631 632 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr); 633 } 634 635 if (tx_pause) { 636 /* When the port first enters congestion, send a PAUSE request 637 * with the maximum number of quanta. When the port exits 638 * congestion, it will automatically send a PAUSE frame with 639 * zero quanta. 640 */ 641 init_quanta = 0xffff; 642 643 /* Also, set up the refresh timer to send follow-up PAUSE 644 * frames at half the quanta value, in case the congestion 645 * condition persists. 646 */ 647 refresh_quanta = 0xffff / 2; 648 649 /* Start emitting PAUSE frames when 3 large frames (or more 650 * smaller frames) have accumulated in the FIFO waiting to be 651 * DMAed to the RX ring. 652 */ 653 pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE; 654 pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE; 655 } 656 657 enetc_port_mac_wr(si, ENETC_PM0_PAUSE_QUANTA, init_quanta); 658 enetc_port_mac_wr(si, ENETC_PM0_PAUSE_THRESH, refresh_quanta); 659 enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh); 660 enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh); 661 662 cmd_cfg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG); 663 664 if (rx_pause) 665 cmd_cfg &= ~ENETC_PM0_PAUSE_IGN; 666 else 667 cmd_cfg |= ENETC_PM0_PAUSE_IGN; 668 669 enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, cmd_cfg); 670 671 enetc_mac_enable(si, true); 672 673 if (si->hw_features & ENETC_SI_F_QBU) 674 enetc_mm_link_state_update(priv, true); 675 } 676 677 static void enetc_pl_mac_link_down(struct phylink_config *config, 678 unsigned int mode, 679 phy_interface_t interface) 680 { 681 struct enetc_pf *pf = phylink_to_enetc_pf(config); 682 struct enetc_si *si = pf->si; 683 struct enetc_ndev_priv *priv; 684 685 priv = netdev_priv(si->ndev); 686 687 if (si->hw_features & ENETC_SI_F_QBU) 688 enetc_mm_link_state_update(priv, false); 689 690 enetc_mac_enable(si, false); 691 } 692 693 static const struct phylink_mac_ops enetc_mac_phylink_ops = { 694 .mac_select_pcs = enetc_pl_mac_select_pcs, 695 .mac_config = enetc_pl_mac_config, 696 .mac_link_up = enetc_pl_mac_link_up, 697 .mac_link_down = enetc_pl_mac_link_down, 698 }; 699 700 /* Initialize the entire shared memory for the flow steering entries 701 * of this port (PF + VFs) 702 */ 703 static int enetc_init_port_rfs_memory(struct enetc_si *si) 704 { 705 struct enetc_cmd_rfse rfse = {0}; 706 struct enetc_hw *hw = &si->hw; 707 int num_rfs, i, err = 0; 708 u32 val; 709 710 val = enetc_port_rd(hw, ENETC_PRFSCAPR); 711 num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val); 712 713 for (i = 0; i < num_rfs; i++) { 714 err = enetc_set_fs_entry(si, &rfse, i); 715 if (err) 716 break; 717 } 718 719 return err; 720 } 721 722 static int enetc_init_port_rss_memory(struct enetc_si *si) 723 { 724 struct enetc_hw *hw = &si->hw; 725 int num_rss, err; 726 int *rss_table; 727 u32 val; 728 729 val = enetc_port_rd(hw, ENETC_PRSSCAPR); 730 num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val); 731 if (!num_rss) 732 return 0; 733 734 rss_table = kzalloc_objs(*rss_table, num_rss); 735 if (!rss_table) 736 return -ENOMEM; 737 738 err = enetc_set_rss_table(si, rss_table, num_rss); 739 740 kfree(rss_table); 741 742 return err; 743 } 744 745 static int enetc_pf_register_with_ierb(struct pci_dev *pdev) 746 { 747 struct platform_device *ierb_pdev; 748 struct device_node *ierb_node; 749 int ret; 750 751 ierb_node = of_find_compatible_node(NULL, NULL, 752 "fsl,ls1028a-enetc-ierb"); 753 if (!ierb_node) 754 return -ENODEV; 755 756 if (!of_device_is_available(ierb_node)) { 757 of_node_put(ierb_node); 758 return -ENODEV; 759 } 760 761 ierb_pdev = of_find_device_by_node(ierb_node); 762 of_node_put(ierb_node); 763 764 if (!ierb_pdev) 765 return -EPROBE_DEFER; 766 767 ret = enetc_ierb_register_pf(ierb_pdev, pdev); 768 769 put_device(&ierb_pdev->dev); 770 771 return ret; 772 } 773 774 static const struct enetc_si_ops enetc_psi_ops = { 775 .get_rss_table = enetc_get_rss_table, 776 .set_rss_table = enetc_set_rss_table, 777 }; 778 779 static struct enetc_si *enetc_psi_create(struct pci_dev *pdev) 780 { 781 struct enetc_si *si; 782 int err; 783 784 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(struct enetc_pf)); 785 if (err) { 786 dev_err_probe(&pdev->dev, err, "PCI probing failed\n"); 787 goto out; 788 } 789 790 si = pci_get_drvdata(pdev); 791 if (!si->hw.port || !si->hw.global) { 792 err = -ENODEV; 793 dev_err(&pdev->dev, "could not map PF space, probing a VF?\n"); 794 goto out_pci_remove; 795 } 796 797 si->revision = enetc_get_ip_revision(&si->hw); 798 si->ops = &enetc_psi_ops; 799 err = enetc_get_driver_data(si); 800 if (err) { 801 dev_err(&pdev->dev, "Could not get PF driver data\n"); 802 goto out_pci_remove; 803 } 804 805 err = enetc_setup_cbdr(si); 806 if (err) 807 goto out_pci_remove; 808 809 err = enetc_init_port_rfs_memory(si); 810 if (err) { 811 dev_err(&pdev->dev, "Failed to initialize RFS memory\n"); 812 goto out_teardown_cbdr; 813 } 814 815 err = enetc_init_port_rss_memory(si); 816 if (err) { 817 dev_err(&pdev->dev, "Failed to initialize RSS memory\n"); 818 goto out_teardown_cbdr; 819 } 820 821 return si; 822 823 out_teardown_cbdr: 824 enetc_teardown_cbdr(si); 825 out_pci_remove: 826 enetc_pci_remove(pdev); 827 out: 828 return ERR_PTR(err); 829 } 830 831 static void enetc_psi_destroy(struct pci_dev *pdev) 832 { 833 struct enetc_si *si = pci_get_drvdata(pdev); 834 835 enetc_teardown_cbdr(si); 836 enetc_pci_remove(pdev); 837 } 838 839 static const struct enetc_pf_ops enetc_pf_ops = { 840 .set_si_primary_mac = enetc_pf_set_primary_mac_addr, 841 .get_si_primary_mac = enetc_pf_get_primary_mac_addr, 842 .create_pcs = enetc_pf_create_pcs, 843 .destroy_pcs = enetc_pf_destroy_pcs, 844 .enable_psfp = enetc_psfp_enable, 845 }; 846 847 static int enetc_pf_probe(struct pci_dev *pdev, 848 const struct pci_device_id *ent) 849 { 850 struct device_node *node = pdev->dev.of_node; 851 struct enetc_ndev_priv *priv; 852 struct net_device *ndev; 853 struct enetc_si *si; 854 struct enetc_pf *pf; 855 int err; 856 857 err = enetc_pf_register_with_ierb(pdev); 858 if (err == -EPROBE_DEFER) 859 return err; 860 if (err) 861 dev_warn(&pdev->dev, 862 "Could not register with IERB driver: %pe, please update the device tree\n", 863 ERR_PTR(err)); 864 865 si = enetc_psi_create(pdev); 866 if (IS_ERR(si)) { 867 err = PTR_ERR(si); 868 goto err_psi_create; 869 } 870 871 pf = enetc_si_priv(si); 872 pf->si = si; 873 pf->ops = &enetc_pf_ops; 874 875 err = enetc_init_sriov_resources(pf); 876 if (err) 877 goto err_init_sriov_resources; 878 879 err = enetc_setup_mac_addresses(node, pf); 880 if (err) 881 goto err_setup_mac_addresses; 882 883 enetc_configure_port(pf); 884 885 enetc_get_si_caps(si); 886 887 ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS); 888 if (!ndev) { 889 err = -ENOMEM; 890 dev_err(&pdev->dev, "netdev creation failed\n"); 891 goto err_alloc_netdev; 892 } 893 894 enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops); 895 896 priv = netdev_priv(ndev); 897 898 mutex_init(&priv->mm_lock); 899 900 enetc_init_si_rings_params(priv); 901 902 err = enetc_alloc_si_resources(priv); 903 if (err) { 904 dev_err(&pdev->dev, "SI resource alloc failed\n"); 905 goto err_alloc_si_res; 906 } 907 908 err = enetc_configure_si(priv); 909 if (err) { 910 dev_err(&pdev->dev, "Failed to configure SI\n"); 911 goto err_config_si; 912 } 913 914 err = enetc_alloc_msix(priv); 915 if (err) { 916 dev_err(&pdev->dev, "MSIX alloc failed\n"); 917 goto err_alloc_msix; 918 } 919 920 err = of_get_phy_mode(node, &pf->if_mode); 921 if (err) { 922 dev_err(&pdev->dev, "Failed to read PHY mode\n"); 923 goto err_phy_mode; 924 } 925 926 err = enetc_mdiobus_create(pf, node); 927 if (err) 928 goto err_mdiobus_create; 929 930 err = enetc_phylink_create(priv, node, &enetc_mac_phylink_ops); 931 if (err) 932 goto err_phylink_create; 933 934 err = register_netdev(ndev); 935 if (err) 936 goto err_reg_netdev; 937 938 return 0; 939 940 err_reg_netdev: 941 enetc_phylink_destroy(priv); 942 err_phylink_create: 943 enetc_mdiobus_destroy(pf); 944 err_mdiobus_create: 945 err_phy_mode: 946 enetc_free_msix(priv); 947 err_config_si: 948 err_alloc_msix: 949 enetc_free_si_resources(priv); 950 err_alloc_si_res: 951 si->ndev = NULL; 952 free_netdev(ndev); 953 err_alloc_netdev: 954 err_setup_mac_addresses: 955 err_init_sriov_resources: 956 enetc_psi_destroy(pdev); 957 err_psi_create: 958 return err; 959 } 960 961 static void enetc_pf_remove(struct pci_dev *pdev) 962 { 963 struct enetc_si *si = pci_get_drvdata(pdev); 964 struct enetc_pf *pf = enetc_si_priv(si); 965 struct enetc_ndev_priv *priv; 966 967 priv = netdev_priv(si->ndev); 968 969 if (pf->num_vfs) 970 enetc_sriov_configure(pdev, 0); 971 972 unregister_netdev(si->ndev); 973 974 enetc_phylink_destroy(priv); 975 enetc_mdiobus_destroy(pf); 976 977 enetc_free_msix(priv); 978 979 enetc_free_si_resources(priv); 980 981 free_netdev(si->ndev); 982 enetc_psi_destroy(pdev); 983 } 984 985 static void enetc_fixup_clear_rss_rfs(struct pci_dev *pdev) 986 { 987 struct device_node *node = pdev->dev.of_node; 988 struct enetc_si *si; 989 990 /* Only apply quirk for disabled functions. For the ones 991 * that are enabled, enetc_pf_probe() will apply it. 992 */ 993 if (node && of_device_is_available(node)) 994 return; 995 996 si = enetc_psi_create(pdev); 997 if (!IS_ERR(si)) 998 enetc_psi_destroy(pdev); 999 } 1000 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF, 1001 enetc_fixup_clear_rss_rfs); 1002 1003 static const struct pci_device_id enetc_pf_id_table[] = { 1004 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) }, 1005 { 0, } /* End of table. */ 1006 }; 1007 MODULE_DEVICE_TABLE(pci, enetc_pf_id_table); 1008 1009 static struct pci_driver enetc_pf_driver = { 1010 .name = KBUILD_MODNAME, 1011 .id_table = enetc_pf_id_table, 1012 .probe = enetc_pf_probe, 1013 .remove = enetc_pf_remove, 1014 #ifdef CONFIG_PCI_IOV 1015 .sriov_configure = enetc_sriov_configure, 1016 #endif 1017 }; 1018 module_pci_driver(enetc_pf_driver); 1019 1020 MODULE_DESCRIPTION(ENETC_DRV_NAME_STR); 1021 MODULE_LICENSE("Dual BSD/GPL"); 1022