1 // SPDX-License-Identifier: GPL-2.0-only
2 /* MCP23S08 SPI/I2C GPIO driver */
3
4 #include <linux/bitops.h>
5 #include <linux/kernel.h>
6 #include <linux/device.h>
7 #include <linux/mutex.h>
8 #include <linux/mod_devicetable.h>
9 #include <linux/module.h>
10 #include <linux/export.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/seq_file.h>
14 #include <linux/slab.h>
15 #include <asm/byteorder.h>
16 #include <linux/interrupt.h>
17 #include <linux/regmap.h>
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinconf-generic.h>
21
22 #include "pinctrl-mcp23s08.h"
23
24 /* Registers are all 8 bits wide.
25 *
26 * The mcp23s17 has twice as many bits, and can be configured to work
27 * with either 16 bit registers or with two adjacent 8 bit banks.
28 */
29 #define MCP_IODIR 0x00 /* init/reset: all ones */
30 #define MCP_IPOL 0x01
31 #define MCP_GPINTEN 0x02
32 #define MCP_DEFVAL 0x03
33 #define MCP_INTCON 0x04
34 #define MCP_IOCON 0x05
35 # define IOCON_MIRROR (1 << 6)
36 # define IOCON_SEQOP (1 << 5)
37 # define IOCON_HAEN (1 << 3)
38 # define IOCON_ODR (1 << 2)
39 # define IOCON_INTPOL (1 << 1)
40 # define IOCON_INTCC (1)
41 #define MCP_GPPU 0x06
42 #define MCP_INTF 0x07
43 #define MCP_INTCAP 0x08
44 #define MCP_GPIO 0x09
45 #define MCP_OLAT 0x0a
46
47 static const struct reg_default mcp23x08_defaults[] = {
48 {.reg = MCP_IODIR, .def = 0xff},
49 {.reg = MCP_IPOL, .def = 0x00},
50 {.reg = MCP_GPINTEN, .def = 0x00},
51 {.reg = MCP_DEFVAL, .def = 0x00},
52 {.reg = MCP_INTCON, .def = 0x00},
53 {.reg = MCP_IOCON, .def = 0x00},
54 {.reg = MCP_GPPU, .def = 0x00},
55 {.reg = MCP_OLAT, .def = 0x00},
56 };
57
58 static const struct regmap_range mcp23x08_volatile_range = {
59 .range_min = MCP_INTF,
60 .range_max = MCP_GPIO,
61 };
62
63 static const struct regmap_access_table mcp23x08_volatile_table = {
64 .yes_ranges = &mcp23x08_volatile_range,
65 .n_yes_ranges = 1,
66 };
67
68 static const struct regmap_range mcp23x08_precious_range = {
69 .range_min = MCP_GPIO,
70 .range_max = MCP_GPIO,
71 };
72
73 static const struct regmap_access_table mcp23x08_precious_table = {
74 .yes_ranges = &mcp23x08_precious_range,
75 .n_yes_ranges = 1,
76 };
77
78 const struct regmap_config mcp23x08_regmap = {
79 .reg_bits = 8,
80 .val_bits = 8,
81
82 .reg_stride = 1,
83 .volatile_table = &mcp23x08_volatile_table,
84 .precious_table = &mcp23x08_precious_table,
85 .reg_defaults = mcp23x08_defaults,
86 .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults),
87 .cache_type = REGCACHE_FLAT,
88 .max_register = MCP_OLAT,
89 .disable_locking = true, /* mcp->lock protects the regmap */
90 };
91 EXPORT_SYMBOL_GPL(mcp23x08_regmap);
92
93 static const struct reg_default mcp23x17_defaults[] = {
94 {.reg = MCP_IODIR << 1, .def = 0xffff},
95 {.reg = MCP_IPOL << 1, .def = 0x0000},
96 {.reg = MCP_GPINTEN << 1, .def = 0x0000},
97 {.reg = MCP_DEFVAL << 1, .def = 0x0000},
98 {.reg = MCP_INTCON << 1, .def = 0x0000},
99 {.reg = MCP_IOCON << 1, .def = 0x0000},
100 {.reg = MCP_GPPU << 1, .def = 0x0000},
101 {.reg = MCP_OLAT << 1, .def = 0x0000},
102 };
103
104 static const struct regmap_range mcp23x17_volatile_range = {
105 .range_min = MCP_INTF << 1,
106 .range_max = MCP_GPIO << 1,
107 };
108
109 static const struct regmap_access_table mcp23x17_volatile_table = {
110 .yes_ranges = &mcp23x17_volatile_range,
111 .n_yes_ranges = 1,
112 };
113
114 static const struct regmap_range mcp23x17_precious_range = {
115 .range_min = MCP_INTCAP << 1,
116 .range_max = MCP_GPIO << 1,
117 };
118
119 static const struct regmap_access_table mcp23x17_precious_table = {
120 .yes_ranges = &mcp23x17_precious_range,
121 .n_yes_ranges = 1,
122 };
123
124 const struct regmap_config mcp23x17_regmap = {
125 .reg_bits = 8,
126 .val_bits = 16,
127
128 .reg_stride = 2,
129 .max_register = MCP_OLAT << 1,
130 .volatile_table = &mcp23x17_volatile_table,
131 .precious_table = &mcp23x17_precious_table,
132 .reg_defaults = mcp23x17_defaults,
133 .num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults),
134 .cache_type = REGCACHE_FLAT,
135 .val_format_endian = REGMAP_ENDIAN_LITTLE,
136 .disable_locking = true, /* mcp->lock protects the regmap */
137 };
138 EXPORT_SYMBOL_GPL(mcp23x17_regmap);
139
mcp_read(struct mcp23s08 * mcp,unsigned int reg,unsigned int * val)140 static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)
141 {
142 return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);
143 }
144
mcp_write(struct mcp23s08 * mcp,unsigned int reg,unsigned int val)145 static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)
146 {
147 return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);
148 }
149
mcp_update_bits(struct mcp23s08 * mcp,unsigned int reg,unsigned int mask,unsigned int val)150 static int mcp_update_bits(struct mcp23s08 *mcp, unsigned int reg,
151 unsigned int mask, unsigned int val)
152 {
153 return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift,
154 mask, val);
155 }
156
mcp_set_bit(struct mcp23s08 * mcp,unsigned int reg,unsigned int pin,bool enabled)157 static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg,
158 unsigned int pin, bool enabled)
159 {
160 u16 mask = BIT(pin);
161 return mcp_update_bits(mcp, reg, mask, enabled ? mask : 0);
162 }
163
164 static const struct pinctrl_pin_desc mcp23x08_pins[] = {
165 PINCTRL_PIN(0, "gpio0"),
166 PINCTRL_PIN(1, "gpio1"),
167 PINCTRL_PIN(2, "gpio2"),
168 PINCTRL_PIN(3, "gpio3"),
169 PINCTRL_PIN(4, "gpio4"),
170 PINCTRL_PIN(5, "gpio5"),
171 PINCTRL_PIN(6, "gpio6"),
172 PINCTRL_PIN(7, "gpio7"),
173 };
174
175 static const struct pinctrl_pin_desc mcp23x17_pins[] = {
176 PINCTRL_PIN(0, "gpio0"),
177 PINCTRL_PIN(1, "gpio1"),
178 PINCTRL_PIN(2, "gpio2"),
179 PINCTRL_PIN(3, "gpio3"),
180 PINCTRL_PIN(4, "gpio4"),
181 PINCTRL_PIN(5, "gpio5"),
182 PINCTRL_PIN(6, "gpio6"),
183 PINCTRL_PIN(7, "gpio7"),
184 PINCTRL_PIN(8, "gpio8"),
185 PINCTRL_PIN(9, "gpio9"),
186 PINCTRL_PIN(10, "gpio10"),
187 PINCTRL_PIN(11, "gpio11"),
188 PINCTRL_PIN(12, "gpio12"),
189 PINCTRL_PIN(13, "gpio13"),
190 PINCTRL_PIN(14, "gpio14"),
191 PINCTRL_PIN(15, "gpio15"),
192 };
193
mcp_pinctrl_get_groups_count(struct pinctrl_dev * pctldev)194 static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
195 {
196 return 0;
197 }
198
mcp_pinctrl_get_group_name(struct pinctrl_dev * pctldev,unsigned int group)199 static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
200 unsigned int group)
201 {
202 return NULL;
203 }
204
mcp_pinctrl_get_group_pins(struct pinctrl_dev * pctldev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)205 static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
206 unsigned int group,
207 const unsigned int **pins,
208 unsigned int *num_pins)
209 {
210 return -ENOTSUPP;
211 }
212
213 static const struct pinctrl_ops mcp_pinctrl_ops = {
214 .get_groups_count = mcp_pinctrl_get_groups_count,
215 .get_group_name = mcp_pinctrl_get_group_name,
216 .get_group_pins = mcp_pinctrl_get_group_pins,
217 #ifdef CONFIG_OF
218 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
219 .dt_free_map = pinconf_generic_dt_free_map,
220 #endif
221 };
222
mcp_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)223 static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
224 unsigned long *config)
225 {
226 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
227 enum pin_config_param param = pinconf_to_config_param(*config);
228 unsigned int data, status;
229 int ret;
230
231 switch (param) {
232 case PIN_CONFIG_BIAS_PULL_UP:
233 mutex_lock(&mcp->lock);
234 ret = mcp_read(mcp, MCP_GPPU, &data);
235 mutex_unlock(&mcp->lock);
236 if (ret < 0)
237 return ret;
238 status = (data & BIT(pin)) ? 1 : 0;
239 break;
240 default:
241 return -ENOTSUPP;
242 }
243
244 *config = 0;
245
246 return status ? 0 : -EINVAL;
247 }
248
mcp_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)249 static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
250 unsigned long *configs, unsigned int num_configs)
251 {
252 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
253 enum pin_config_param param;
254 u32 arg;
255 int ret = 0;
256 int i;
257
258 for (i = 0; i < num_configs; i++) {
259 param = pinconf_to_config_param(configs[i]);
260 arg = pinconf_to_config_argument(configs[i]);
261
262 switch (param) {
263 case PIN_CONFIG_BIAS_PULL_UP:
264 mutex_lock(&mcp->lock);
265 ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
266 mutex_unlock(&mcp->lock);
267 break;
268 default:
269 dev_dbg(mcp->dev, "Invalid config param %04x\n", param);
270 return -ENOTSUPP;
271 }
272 }
273
274 return ret;
275 }
276
277 static const struct pinconf_ops mcp_pinconf_ops = {
278 .pin_config_get = mcp_pinconf_get,
279 .pin_config_set = mcp_pinconf_set,
280 .is_generic = true,
281 };
282
283 /*----------------------------------------------------------------------*/
284
mcp23s08_direction_input(struct gpio_chip * chip,unsigned offset)285 static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
286 {
287 struct mcp23s08 *mcp = gpiochip_get_data(chip);
288 int status;
289
290 mutex_lock(&mcp->lock);
291 status = mcp_set_bit(mcp, MCP_IODIR, offset, true);
292 mutex_unlock(&mcp->lock);
293
294 return status;
295 }
296
mcp23s08_get(struct gpio_chip * chip,unsigned offset)297 static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
298 {
299 struct mcp23s08 *mcp = gpiochip_get_data(chip);
300 int status, ret;
301
302 mutex_lock(&mcp->lock);
303
304 /* REVISIT reading this clears any IRQ ... */
305 ret = mcp_read(mcp, MCP_GPIO, &status);
306 if (ret < 0)
307 status = 0;
308 else {
309 mcp->cached_gpio = status;
310 status = !!(status & (1 << offset));
311 }
312
313 mutex_unlock(&mcp->lock);
314 return status;
315 }
316
mcp23s08_get_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)317 static int mcp23s08_get_multiple(struct gpio_chip *chip,
318 unsigned long *mask, unsigned long *bits)
319 {
320 struct mcp23s08 *mcp = gpiochip_get_data(chip);
321 unsigned int status;
322 int ret;
323
324 mutex_lock(&mcp->lock);
325
326 /* REVISIT reading this clears any IRQ ... */
327 ret = mcp_read(mcp, MCP_GPIO, &status);
328 if (ret < 0)
329 status = 0;
330 else {
331 mcp->cached_gpio = status;
332 *bits = status;
333 }
334
335 mutex_unlock(&mcp->lock);
336 return ret;
337 }
338
__mcp23s08_set(struct mcp23s08 * mcp,unsigned mask,bool value)339 static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value)
340 {
341 return mcp_update_bits(mcp, MCP_OLAT, mask, value ? mask : 0);
342 }
343
mcp23s08_set(struct gpio_chip * chip,unsigned offset,int value)344 static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
345 {
346 struct mcp23s08 *mcp = gpiochip_get_data(chip);
347 unsigned mask = BIT(offset);
348
349 mutex_lock(&mcp->lock);
350 __mcp23s08_set(mcp, mask, !!value);
351 mutex_unlock(&mcp->lock);
352 }
353
mcp23s08_set_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)354 static void mcp23s08_set_multiple(struct gpio_chip *chip,
355 unsigned long *mask, unsigned long *bits)
356 {
357 struct mcp23s08 *mcp = gpiochip_get_data(chip);
358
359 mutex_lock(&mcp->lock);
360 mcp_update_bits(mcp, MCP_OLAT, *mask, *bits);
361 mutex_unlock(&mcp->lock);
362 }
363
364 static int
mcp23s08_direction_output(struct gpio_chip * chip,unsigned offset,int value)365 mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
366 {
367 struct mcp23s08 *mcp = gpiochip_get_data(chip);
368 unsigned mask = BIT(offset);
369 int status;
370
371 mutex_lock(&mcp->lock);
372 status = __mcp23s08_set(mcp, mask, value);
373 if (status == 0) {
374 status = mcp_update_bits(mcp, MCP_IODIR, mask, 0);
375 }
376 mutex_unlock(&mcp->lock);
377 return status;
378 }
379
380 /*----------------------------------------------------------------------*/
mcp23s08_irq(int irq,void * data)381 static irqreturn_t mcp23s08_irq(int irq, void *data)
382 {
383 struct mcp23s08 *mcp = data;
384 int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval, gpinten;
385 bool need_unmask = false;
386 unsigned long int enabled_interrupts;
387 unsigned int child_irq;
388 bool intf_set, intcap_changed, gpio_bit_changed,
389 defval_changed, gpio_set;
390
391 mutex_lock(&mcp->lock);
392 if (mcp_read(mcp, MCP_INTF, &intf))
393 goto unlock;
394
395 if (intf == 0) {
396 /* There is no interrupt pending */
397 goto unlock;
398 }
399
400 if (mcp_read(mcp, MCP_INTCON, &intcon))
401 goto unlock;
402
403 if (mcp_read(mcp, MCP_GPINTEN, &gpinten))
404 goto unlock;
405
406 if (mcp_read(mcp, MCP_DEFVAL, &defval))
407 goto unlock;
408
409 /* Mask level interrupts to avoid their immediate reactivation after clearing */
410 if (intcon) {
411 need_unmask = true;
412 if (mcp_write(mcp, MCP_GPINTEN, gpinten & ~intcon))
413 goto unlock;
414 }
415
416 if (mcp_read(mcp, MCP_INTCAP, &intcap))
417 goto unlock;
418
419 /* This clears the interrupt(configurable on S18) */
420 if (mcp_read(mcp, MCP_GPIO, &gpio))
421 goto unlock;
422
423 gpio_orig = mcp->cached_gpio;
424 mcp->cached_gpio = gpio;
425 mutex_unlock(&mcp->lock);
426
427 dev_dbg(mcp->chip.parent,
428 "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n",
429 intcap, intf, gpio_orig, gpio);
430
431 enabled_interrupts = gpinten;
432 for_each_set_bit(i, &enabled_interrupts, mcp->chip.ngpio) {
433 /*
434 * We must check all of the inputs with enabled interrupts
435 * on the chip, otherwise we may not notice a change
436 * on more than one pin.
437 *
438 * On at least the mcp23s17, INTCAP is only updated
439 * one byte at a time(INTCAPA and INTCAPB are
440 * not written to at the same time - only on a per-bank
441 * basis).
442 *
443 * INTF only contains the single bit that caused the
444 * interrupt per-bank. On the mcp23s17, there is
445 * INTFA and INTFB. If two pins are changed on the A
446 * side at the same time, INTF will only have one bit
447 * set. If one pin on the A side and one pin on the B
448 * side are changed at the same time, INTF will have
449 * two bits set. Thus, INTF can't be the only check
450 * to see if the input has changed.
451 */
452
453 intf_set = intf & BIT(i);
454 if (i < 8 && intf_set)
455 intcap_mask = 0x00FF;
456 else if (i >= 8 && intf_set)
457 intcap_mask = 0xFF00;
458 else
459 intcap_mask = 0x00;
460
461 intcap_changed = (intcap_mask &
462 (intcap & BIT(i))) !=
463 (intcap_mask & (BIT(i) & gpio_orig));
464 gpio_set = BIT(i) & gpio;
465 gpio_bit_changed = (BIT(i) & gpio_orig) !=
466 (BIT(i) & gpio);
467 defval_changed = (BIT(i) & intcon) &&
468 ((BIT(i) & gpio) !=
469 (BIT(i) & defval));
470
471 if (((gpio_bit_changed || intcap_changed) &&
472 (BIT(i) & mcp->irq_rise) && gpio_set) ||
473 ((gpio_bit_changed || intcap_changed) &&
474 (BIT(i) & mcp->irq_fall) && !gpio_set) ||
475 defval_changed) {
476 child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
477 handle_nested_irq(child_irq);
478 }
479 }
480
481 if (need_unmask) {
482 mutex_lock(&mcp->lock);
483 goto unlock;
484 }
485
486 return IRQ_HANDLED;
487
488 unlock:
489 if (need_unmask)
490 if (mcp_write(mcp, MCP_GPINTEN, gpinten))
491 dev_err(mcp->chip.parent, "can't unmask GPINTEN\n");
492
493 mutex_unlock(&mcp->lock);
494 return IRQ_HANDLED;
495 }
496
mcp23s08_irq_mask(struct irq_data * data)497 static void mcp23s08_irq_mask(struct irq_data *data)
498 {
499 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
500 struct mcp23s08 *mcp = gpiochip_get_data(gc);
501 unsigned int pos = irqd_to_hwirq(data);
502
503 mcp_set_bit(mcp, MCP_GPINTEN, pos, false);
504 gpiochip_disable_irq(gc, pos);
505 }
506
mcp23s08_irq_unmask(struct irq_data * data)507 static void mcp23s08_irq_unmask(struct irq_data *data)
508 {
509 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
510 struct mcp23s08 *mcp = gpiochip_get_data(gc);
511 unsigned int pos = irqd_to_hwirq(data);
512
513 gpiochip_enable_irq(gc, pos);
514 mcp_set_bit(mcp, MCP_GPINTEN, pos, true);
515 }
516
mcp23s08_irq_set_type(struct irq_data * data,unsigned int type)517 static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
518 {
519 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
520 struct mcp23s08 *mcp = gpiochip_get_data(gc);
521 unsigned int pos = irqd_to_hwirq(data);
522
523 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
524 mcp_set_bit(mcp, MCP_INTCON, pos, false);
525 mcp->irq_rise |= BIT(pos);
526 mcp->irq_fall |= BIT(pos);
527 } else if (type & IRQ_TYPE_EDGE_RISING) {
528 mcp_set_bit(mcp, MCP_INTCON, pos, false);
529 mcp->irq_rise |= BIT(pos);
530 mcp->irq_fall &= ~BIT(pos);
531 } else if (type & IRQ_TYPE_EDGE_FALLING) {
532 mcp_set_bit(mcp, MCP_INTCON, pos, false);
533 mcp->irq_rise &= ~BIT(pos);
534 mcp->irq_fall |= BIT(pos);
535 } else if (type & IRQ_TYPE_LEVEL_HIGH) {
536 mcp_set_bit(mcp, MCP_INTCON, pos, true);
537 mcp_set_bit(mcp, MCP_DEFVAL, pos, false);
538 } else if (type & IRQ_TYPE_LEVEL_LOW) {
539 mcp_set_bit(mcp, MCP_INTCON, pos, true);
540 mcp_set_bit(mcp, MCP_DEFVAL, pos, true);
541 } else
542 return -EINVAL;
543
544 return 0;
545 }
546
mcp23s08_irq_bus_lock(struct irq_data * data)547 static void mcp23s08_irq_bus_lock(struct irq_data *data)
548 {
549 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
550 struct mcp23s08 *mcp = gpiochip_get_data(gc);
551
552 mutex_lock(&mcp->lock);
553 regcache_cache_only(mcp->regmap, true);
554 }
555
mcp23s08_irq_bus_unlock(struct irq_data * data)556 static void mcp23s08_irq_bus_unlock(struct irq_data *data)
557 {
558 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
559 struct mcp23s08 *mcp = gpiochip_get_data(gc);
560
561 regcache_cache_only(mcp->regmap, false);
562 regcache_sync(mcp->regmap);
563
564 mutex_unlock(&mcp->lock);
565 }
566
mcp23s08_irq_setup(struct mcp23s08 * mcp)567 static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
568 {
569 struct gpio_chip *chip = &mcp->chip;
570 int err;
571 unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
572
573 if (mcp->irq_active_high)
574 irqflags |= IRQF_TRIGGER_HIGH;
575 else
576 irqflags |= IRQF_TRIGGER_LOW;
577
578 err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
579 mcp23s08_irq,
580 irqflags, dev_name(chip->parent), mcp);
581 if (err != 0) {
582 dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
583 mcp->irq, err);
584 return err;
585 }
586
587 return 0;
588 }
589
mcp23s08_irq_print_chip(struct irq_data * d,struct seq_file * p)590 static void mcp23s08_irq_print_chip(struct irq_data *d, struct seq_file *p)
591 {
592 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
593 struct mcp23s08 *mcp = gpiochip_get_data(gc);
594
595 seq_puts(p, dev_name(mcp->dev));
596 }
597
598 static const struct irq_chip mcp23s08_irq_chip = {
599 .irq_mask = mcp23s08_irq_mask,
600 .irq_unmask = mcp23s08_irq_unmask,
601 .irq_set_type = mcp23s08_irq_set_type,
602 .irq_bus_lock = mcp23s08_irq_bus_lock,
603 .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,
604 .irq_print_chip = mcp23s08_irq_print_chip,
605 .flags = IRQCHIP_IMMUTABLE,
606 GPIOCHIP_IRQ_RESOURCE_HELPERS,
607 };
608
609 /*----------------------------------------------------------------------*/
610
mcp23s08_probe_one(struct mcp23s08 * mcp,struct device * dev,unsigned int addr,unsigned int type,unsigned int base)611 int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
612 unsigned int addr, unsigned int type, unsigned int base)
613 {
614 int status, ret;
615 bool mirror = false;
616 bool open_drain = false;
617
618 mutex_init(&mcp->lock);
619
620 mcp->dev = dev;
621 mcp->addr = addr;
622
623 mcp->irq_active_high = false;
624
625 mcp->chip.direction_input = mcp23s08_direction_input;
626 mcp->chip.get = mcp23s08_get;
627 mcp->chip.get_multiple = mcp23s08_get_multiple;
628 mcp->chip.direction_output = mcp23s08_direction_output;
629 mcp->chip.set = mcp23s08_set;
630 mcp->chip.set_multiple = mcp23s08_set_multiple;
631
632 mcp->chip.base = base;
633 mcp->chip.can_sleep = true;
634 mcp->chip.parent = dev;
635 mcp->chip.owner = THIS_MODULE;
636
637 mcp->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
638
639 /*
640 * Reset the chip - we don't really know what state it's in, so reset
641 * all pins to input first to prevent surprises.
642 */
643 ret = mcp_write(mcp, MCP_IODIR, mcp->chip.ngpio == 16 ? 0xFFFF : 0xFF);
644 if (ret < 0)
645 return ret;
646
647 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
648 * and MCP_IOCON.HAEN = 1, so we work with all chips.
649 */
650
651 ret = mcp_read(mcp, MCP_IOCON, &status);
652 if (ret < 0)
653 return dev_err_probe(dev, ret, "can't identify chip %d\n", addr);
654
655 mcp->irq_controller =
656 device_property_read_bool(dev, "interrupt-controller");
657 if (mcp->irq && mcp->irq_controller) {
658 mcp->irq_active_high =
659 device_property_read_bool(dev,
660 "microchip,irq-active-high");
661
662 mirror = device_property_read_bool(dev, "microchip,irq-mirror");
663 open_drain = device_property_read_bool(dev, "drive-open-drain");
664 }
665
666 if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
667 mcp->irq_active_high || open_drain) {
668 /* mcp23s17 has IOCON twice, make sure they are in sync */
669 status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
670 status |= IOCON_HAEN | (IOCON_HAEN << 8);
671 if (mcp->irq_active_high)
672 status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
673 else
674 status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
675
676 if (mirror)
677 status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
678
679 if (open_drain)
680 status |= IOCON_ODR | (IOCON_ODR << 8);
681
682 if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
683 status |= IOCON_INTCC | (IOCON_INTCC << 8);
684
685 ret = mcp_write(mcp, MCP_IOCON, status);
686 if (ret < 0)
687 return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr);
688 }
689
690 if (mcp->irq && mcp->irq_controller) {
691 struct gpio_irq_chip *girq = &mcp->chip.irq;
692
693 gpio_irq_chip_set_chip(girq, &mcp23s08_irq_chip);
694 /* This will let us handle the parent IRQ in the driver */
695 girq->parent_handler = NULL;
696 girq->num_parents = 0;
697 girq->parents = NULL;
698 girq->default_type = IRQ_TYPE_NONE;
699 girq->handler = handle_simple_irq;
700 girq->threaded = true;
701 }
702
703 ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
704 if (ret < 0)
705 return dev_err_probe(dev, ret, "can't add GPIO chip\n");
706
707 mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
708 mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
709 mcp->pinctrl_desc.npins = mcp->chip.ngpio;
710 if (mcp->pinctrl_desc.npins == 8)
711 mcp->pinctrl_desc.pins = mcp23x08_pins;
712 else if (mcp->pinctrl_desc.npins == 16)
713 mcp->pinctrl_desc.pins = mcp23x17_pins;
714 mcp->pinctrl_desc.owner = THIS_MODULE;
715
716 mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);
717 if (IS_ERR(mcp->pctldev))
718 return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n");
719
720 if (mcp->irq) {
721 ret = mcp23s08_irq_setup(mcp);
722 if (ret)
723 return dev_err_probe(dev, ret, "can't setup IRQ\n");
724 }
725
726 return 0;
727 }
728 EXPORT_SYMBOL_GPL(mcp23s08_probe_one);
729
730 MODULE_DESCRIPTION("MCP23S08 SPI/I2C GPIO driver");
731 MODULE_LICENSE("GPL");
732