1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "inc/clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/opp.h" 32 #include "inc/hw/link_encoder.h" 33 #include "inc/core_status.h" 34 35 struct pipe_ctx; 36 struct dc_state; 37 struct dc_stream_status; 38 struct dc_writeback_info; 39 struct dchub_init_data; 40 struct dc_static_screen_params; 41 struct resource_pool; 42 struct dc_phy_addr_space_config; 43 struct dc_virtual_addr_space_config; 44 struct dpp; 45 struct dce_hwseq; 46 struct link_resource; 47 struct dc_dmub_cmd; 48 struct pg_block_update; 49 struct drr_params; 50 51 struct subvp_pipe_control_lock_fast_params { 52 struct dc *dc; 53 bool lock; 54 bool subvp_immediate_flip; 55 }; 56 57 struct pipe_control_lock_params { 58 struct dc *dc; 59 struct pipe_ctx *pipe_ctx; 60 bool lock; 61 }; 62 63 struct set_flip_control_gsl_params { 64 struct pipe_ctx *pipe_ctx; 65 bool flip_immediate; 66 }; 67 68 struct program_triplebuffer_params { 69 const struct dc *dc; 70 struct pipe_ctx *pipe_ctx; 71 bool enableTripleBuffer; 72 }; 73 74 struct update_plane_addr_params { 75 struct dc *dc; 76 struct pipe_ctx *pipe_ctx; 77 }; 78 79 struct set_input_transfer_func_params { 80 struct dc *dc; 81 struct pipe_ctx *pipe_ctx; 82 struct dc_plane_state *plane_state; 83 }; 84 85 struct program_gamut_remap_params { 86 struct pipe_ctx *pipe_ctx; 87 }; 88 89 struct program_manual_trigger_params { 90 struct pipe_ctx *pipe_ctx; 91 }; 92 93 struct send_dmcub_cmd_params { 94 struct dc_context *ctx; 95 union dmub_rb_cmd *cmd; 96 enum dm_dmub_wait_type wait_type; 97 }; 98 99 struct setup_dpp_params { 100 struct pipe_ctx *pipe_ctx; 101 }; 102 103 struct program_bias_and_scale_params { 104 struct pipe_ctx *pipe_ctx; 105 }; 106 107 struct set_output_transfer_func_params { 108 struct dc *dc; 109 struct pipe_ctx *pipe_ctx; 110 const struct dc_stream_state *stream; 111 }; 112 113 struct update_visual_confirm_params { 114 struct dc *dc; 115 struct pipe_ctx *pipe_ctx; 116 int mpcc_id; 117 }; 118 119 struct power_on_mpc_mem_pwr_params { 120 struct mpc *mpc; 121 int mpcc_id; 122 bool power_on; 123 }; 124 125 struct set_output_csc_params { 126 struct mpc *mpc; 127 int opp_id; 128 const uint16_t *regval; 129 enum mpc_output_csc_mode ocsc_mode; 130 }; 131 132 struct set_ocsc_default_params { 133 struct mpc *mpc; 134 int opp_id; 135 enum dc_color_space color_space; 136 enum mpc_output_csc_mode ocsc_mode; 137 }; 138 139 struct subvp_save_surf_addr { 140 struct dc_dmub_srv *dc_dmub_srv; 141 const struct dc_plane_address *addr; 142 uint8_t subvp_index; 143 }; 144 145 struct wait_for_dcc_meta_propagation_params { 146 const struct dc *dc; 147 const struct pipe_ctx *top_pipe_to_program; 148 }; 149 150 struct fams2_global_control_lock_fast_params { 151 struct dc *dc; 152 bool is_required; 153 bool lock; 154 }; 155 156 union block_sequence_params { 157 struct update_plane_addr_params update_plane_addr_params; 158 struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params; 159 struct pipe_control_lock_params pipe_control_lock_params; 160 struct set_flip_control_gsl_params set_flip_control_gsl_params; 161 struct program_triplebuffer_params program_triplebuffer_params; 162 struct set_input_transfer_func_params set_input_transfer_func_params; 163 struct program_gamut_remap_params program_gamut_remap_params; 164 struct program_manual_trigger_params program_manual_trigger_params; 165 struct send_dmcub_cmd_params send_dmcub_cmd_params; 166 struct setup_dpp_params setup_dpp_params; 167 struct program_bias_and_scale_params program_bias_and_scale_params; 168 struct set_output_transfer_func_params set_output_transfer_func_params; 169 struct update_visual_confirm_params update_visual_confirm_params; 170 struct power_on_mpc_mem_pwr_params power_on_mpc_mem_pwr_params; 171 struct set_output_csc_params set_output_csc_params; 172 struct set_ocsc_default_params set_ocsc_default_params; 173 struct subvp_save_surf_addr subvp_save_surf_addr; 174 struct wait_for_dcc_meta_propagation_params wait_for_dcc_meta_propagation_params; 175 struct fams2_global_control_lock_fast_params fams2_global_control_lock_fast_params; 176 }; 177 178 enum block_sequence_func { 179 DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST = 0, 180 OPTC_PIPE_CONTROL_LOCK, 181 HUBP_SET_FLIP_CONTROL_GSL, 182 HUBP_PROGRAM_TRIPLEBUFFER, 183 HUBP_UPDATE_PLANE_ADDR, 184 DPP_SET_INPUT_TRANSFER_FUNC, 185 DPP_PROGRAM_GAMUT_REMAP, 186 OPTC_PROGRAM_MANUAL_TRIGGER, 187 DMUB_SEND_DMCUB_CMD, 188 DPP_SETUP_DPP, 189 DPP_PROGRAM_BIAS_AND_SCALE, 190 DPP_SET_OUTPUT_TRANSFER_FUNC, 191 MPC_UPDATE_VISUAL_CONFIRM, 192 MPC_POWER_ON_MPC_MEM_PWR, 193 MPC_SET_OUTPUT_CSC, 194 MPC_SET_OCSC_DEFAULT, 195 DMUB_SUBVP_SAVE_SURF_ADDR, 196 HUBP_WAIT_FOR_DCC_META_PROP, 197 DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST, 198 }; 199 200 struct block_sequence { 201 union block_sequence_params params; 202 enum block_sequence_func func; 203 }; 204 205 struct hw_sequencer_funcs { 206 void (*hardware_release)(struct dc *dc); 207 /* Embedded Display Related */ 208 void (*edp_power_control)(struct dc_link *link, bool enable); 209 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 210 void (*edp_wait_for_T12)(struct dc_link *link); 211 212 /* Pipe Programming Related */ 213 void (*init_hw)(struct dc *dc); 214 void (*power_down_on_boot)(struct dc *dc); 215 void (*enable_accelerated_mode)(struct dc *dc, 216 struct dc_state *context); 217 enum dc_status (*apply_ctx_to_hw)(struct dc *dc, 218 struct dc_state *context); 219 void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx); 220 void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank); 221 void (*apply_ctx_for_surface)(struct dc *dc, 222 const struct dc_stream_state *stream, 223 int num_planes, struct dc_state *context); 224 void (*program_front_end_for_ctx)(struct dc *dc, 225 struct dc_state *context); 226 void (*wait_for_pending_cleared)(struct dc *dc, 227 struct dc_state *context); 228 void (*post_unlock_program_front_end)(struct dc *dc, 229 struct dc_state *context); 230 void (*update_plane_addr)(const struct dc *dc, 231 struct pipe_ctx *pipe_ctx); 232 void (*update_dchub)(struct dce_hwseq *hws, 233 struct dchub_init_data *dh_data); 234 void (*wait_for_mpcc_disconnect)(struct dc *dc, 235 struct resource_pool *res_pool, 236 struct pipe_ctx *pipe_ctx); 237 void (*edp_backlight_control)( 238 struct dc_link *link, 239 bool enable); 240 void (*program_triplebuffer)(const struct dc *dc, 241 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 242 void (*update_pending_status)(struct pipe_ctx *pipe_ctx); 243 void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable); 244 void (*clear_surface_dcc_and_tiling)(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling); 245 246 /* Pipe Lock Related */ 247 void (*pipe_control_lock)(struct dc *dc, 248 struct pipe_ctx *pipe, bool lock); 249 void (*interdependent_update_lock)(struct dc *dc, 250 struct dc_state *context, bool lock); 251 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx, 252 bool flip_immediate); 253 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock); 254 255 /* Timing Related */ 256 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 257 struct crtc_position *position); 258 int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); 259 void (*calc_vupdate_position)( 260 struct dc *dc, 261 struct pipe_ctx *pipe_ctx, 262 uint32_t *start_line, 263 uint32_t *end_line); 264 void (*enable_per_frame_crtc_position_reset)(struct dc *dc, 265 int group_size, struct pipe_ctx *grouped_pipes[]); 266 void (*enable_timing_synchronization)(struct dc *dc, 267 struct dc_state *state, 268 int group_index, int group_size, 269 struct pipe_ctx *grouped_pipes[]); 270 void (*enable_vblanks_synchronization)(struct dc *dc, 271 int group_index, int group_size, 272 struct pipe_ctx *grouped_pipes[]); 273 void (*setup_periodic_interrupt)(struct dc *dc, 274 struct pipe_ctx *pipe_ctx); 275 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 276 struct dc_crtc_timing_adjust adjust); 277 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 278 int num_pipes, 279 const struct dc_static_screen_params *events); 280 281 /* Stream Related */ 282 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 283 void (*disable_stream)(struct pipe_ctx *pipe_ctx); 284 void (*blank_stream)(struct pipe_ctx *pipe_ctx); 285 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 286 struct dc_link_settings *link_settings); 287 288 /* Bandwidth Related */ 289 void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context); 290 bool (*update_bandwidth)(struct dc *dc, struct dc_state *context); 291 void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context); 292 293 /* Infopacket Related */ 294 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 295 void (*send_immediate_sdp_message)( 296 struct pipe_ctx *pipe_ctx, 297 const uint8_t *custom_sdp_message, 298 unsigned int sdp_message_size); 299 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 300 void (*set_dmdata_attributes)(struct pipe_ctx *pipe); 301 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); 302 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); 303 304 /* Cursor Related */ 305 void (*set_cursor_position)(struct pipe_ctx *pipe); 306 void (*set_cursor_attribute)(struct pipe_ctx *pipe); 307 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); 308 309 /* Colour Related */ 310 void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); 311 void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, 312 enum dc_color_space colorspace, 313 uint16_t *matrix, int opp_id); 314 void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx); 315 316 /* VM Related */ 317 int (*init_sys_ctx)(struct dce_hwseq *hws, 318 struct dc *dc, 319 struct dc_phy_addr_space_config *pa_config); 320 void (*init_vm_ctx)(struct dce_hwseq *hws, 321 struct dc *dc, 322 struct dc_virtual_addr_space_config *va_config, 323 int vmid); 324 325 /* Writeback Related */ 326 void (*update_writeback)(struct dc *dc, 327 struct dc_writeback_info *wb_info, 328 struct dc_state *context); 329 void (*enable_writeback)(struct dc *dc, 330 struct dc_writeback_info *wb_info, 331 struct dc_state *context); 332 void (*disable_writeback)(struct dc *dc, 333 unsigned int dwb_pipe_inst); 334 335 /* Clock Related */ 336 enum dc_status (*set_clock)(struct dc *dc, 337 enum dc_clock_type clock_type, 338 uint32_t clk_khz, uint32_t stepping); 339 void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type, 340 struct dc_clock_config *clock_cfg); 341 void (*optimize_pwr_state)(const struct dc *dc, 342 struct dc_state *context); 343 void (*exit_optimized_pwr_state)(const struct dc *dc, 344 struct dc_state *context); 345 void (*calculate_pix_rate_divider)(struct dc *dc, 346 struct dc_state *context, 347 const struct dc_stream_state *stream); 348 349 /* Audio Related */ 350 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); 351 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); 352 353 /* Stereo 3D Related */ 354 void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc); 355 356 /* HW State Logging Related */ 357 void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx); 358 void (*log_color_state)(struct dc *dc, 359 struct dc_log_buffer_ctx *log_ctx); 360 void (*get_hw_state)(struct dc *dc, char *pBuf, 361 unsigned int bufSize, unsigned int mask); 362 void (*clear_status_bits)(struct dc *dc, unsigned int mask); 363 364 bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx, 365 struct set_backlight_level_params *params); 366 367 void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx); 368 369 void (*set_pipe)(struct pipe_ctx *pipe_ctx); 370 371 void (*enable_dp_link_output)(struct dc_link *link, 372 const struct link_resource *link_res, 373 enum signal_type signal, 374 enum clock_source_id clock_source, 375 const struct dc_link_settings *link_settings); 376 void (*enable_tmds_link_output)(struct dc_link *link, 377 const struct link_resource *link_res, 378 enum signal_type signal, 379 enum clock_source_id clock_source, 380 enum dc_color_depth color_depth, 381 uint32_t pixel_clock); 382 void (*enable_lvds_link_output)(struct dc_link *link, 383 const struct link_resource *link_res, 384 enum clock_source_id clock_source, 385 uint32_t pixel_clock); 386 void (*disable_link_output)(struct dc_link *link, 387 const struct link_resource *link_res, 388 enum signal_type signal); 389 390 void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits); 391 392 /* Idle Optimization Related */ 393 bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable); 394 395 bool (*does_plane_fit_in_mall)(struct dc *dc, 396 unsigned int pitch, 397 unsigned int height, 398 enum surface_pixel_format format, 399 struct dc_cursor_attributes *cursor_attr); 400 void (*commit_subvp_config)(struct dc *dc, struct dc_state *context); 401 void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context); 402 void (*disable_phantom_streams)(struct dc *dc, struct dc_state *context); 403 void (*subvp_pipe_control_lock)(struct dc *dc, 404 struct dc_state *context, 405 bool lock, 406 bool should_lock_all_pipes, 407 struct pipe_ctx *top_pipe_to_program, 408 bool subvp_prev_use); 409 void (*subvp_pipe_control_lock_fast)(union block_sequence_params *params); 410 411 void (*z10_restore)(const struct dc *dc); 412 void (*z10_save_init)(struct dc *dc); 413 bool (*is_abm_supported)(struct dc *dc, 414 struct dc_state *context, struct dc_stream_state *stream); 415 416 void (*set_disp_pattern_generator)(const struct dc *dc, 417 struct pipe_ctx *pipe_ctx, 418 enum controller_dp_test_pattern test_pattern, 419 enum controller_dp_color_space color_space, 420 enum dc_color_depth color_depth, 421 const struct tg_color *solid_color, 422 int width, int height, int offset); 423 void (*blank_phantom)(struct dc *dc, 424 struct timing_generator *tg, 425 int width, 426 int height); 427 void (*update_visual_confirm_color)(struct dc *dc, 428 struct pipe_ctx *pipe_ctx, 429 int mpcc_id); 430 void (*update_phantom_vp_position)(struct dc *dc, 431 struct dc_state *context, 432 struct pipe_ctx *phantom_pipe); 433 void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe); 434 435 void (*calc_blocks_to_gate)(struct dc *dc, struct dc_state *context, 436 struct pg_block_update *update_state); 437 void (*calc_blocks_to_ungate)(struct dc *dc, struct dc_state *context, 438 struct pg_block_update *update_state); 439 void (*hw_block_power_up)(struct dc *dc, 440 struct pg_block_update *update_state); 441 void (*hw_block_power_down)(struct dc *dc, 442 struct pg_block_update *update_state); 443 void (*root_clock_control)(struct dc *dc, 444 struct pg_block_update *update_state, bool power_on); 445 bool (*is_pipe_topology_transition_seamless)(struct dc *dc, 446 const struct dc_state *cur_ctx, 447 const struct dc_state *new_ctx); 448 void (*wait_for_dcc_meta_propagation)(const struct dc *dc, 449 const struct pipe_ctx *top_pipe_to_program); 450 void (*fams2_global_control_lock)(struct dc *dc, 451 struct dc_state *context, 452 bool lock); 453 void (*fams2_update_config)(struct dc *dc, 454 struct dc_state *context, 455 bool enable); 456 void (*fams2_global_control_lock_fast)(union block_sequence_params *params); 457 void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max); 458 void (*program_outstanding_updates)(struct dc *dc, 459 struct dc_state *context); 460 void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); 461 void (*wait_for_all_pending_updates)(const struct pipe_ctx *pipe_ctx); 462 void (*detect_pipe_changes)(struct dc_state *old_state, 463 struct dc_state *new_state, 464 struct pipe_ctx *old_pipe, 465 struct pipe_ctx *new_pipe); 466 void (*enable_plane)(struct dc *dc, 467 struct pipe_ctx *pipe_ctx, 468 struct dc_state *context); 469 void (*update_dchubp_dpp)(struct dc *dc, 470 struct pipe_ctx *pipe_ctx, 471 struct dc_state *context); 472 void (*post_unlock_reset_opp)(struct dc *dc, 473 struct pipe_ctx *opp_head); 474 }; 475 476 void color_space_to_black_color( 477 const struct dc *dc, 478 enum dc_color_space colorspace, 479 struct tg_color *black_color); 480 481 bool hwss_wait_for_blank_complete( 482 struct timing_generator *tg); 483 484 const uint16_t *find_color_matrix( 485 enum dc_color_space color_space, 486 uint32_t *array_size); 487 488 void get_surface_tile_visual_confirm_color( 489 struct pipe_ctx *pipe_ctx, 490 struct tg_color *color); 491 void get_surface_visual_confirm_color( 492 const struct pipe_ctx *pipe_ctx, 493 struct tg_color *color); 494 495 void get_hdr_visual_confirm_color( 496 struct pipe_ctx *pipe_ctx, 497 struct tg_color *color); 498 void get_mpctree_visual_confirm_color( 499 struct pipe_ctx *pipe_ctx, 500 struct tg_color *color); 501 void get_vabc_visual_confirm_color( 502 struct pipe_ctx *pipe_ctx, 503 struct tg_color *color); 504 void get_subvp_visual_confirm_color( 505 struct pipe_ctx *pipe_ctx, 506 struct tg_color *color); 507 void get_fams2_visual_confirm_color( 508 struct dc *dc, 509 struct dc_state *context, 510 struct pipe_ctx *pipe_ctx, 511 struct tg_color *color); 512 513 void get_mclk_switch_visual_confirm_color( 514 struct pipe_ctx *pipe_ctx, 515 struct tg_color *color); 516 517 void get_cursor_visual_confirm_color( 518 struct pipe_ctx *pipe_ctx, 519 struct tg_color *color); 520 521 void get_dcc_visual_confirm_color( 522 struct dc *dc, 523 struct pipe_ctx *pipe_ctx, 524 struct tg_color *color); 525 526 void set_p_state_switch_method( 527 struct dc *dc, 528 struct dc_state *context, 529 struct pipe_ctx *pipe_ctx); 530 531 void set_drr_and_clear_adjust_pending( 532 struct pipe_ctx *pipe_ctx, 533 struct dc_stream_state *stream, 534 struct drr_params *params); 535 536 void hwss_execute_sequence(struct dc *dc, 537 struct block_sequence block_sequence[], 538 int num_steps); 539 540 void hwss_build_fast_sequence(struct dc *dc, 541 struct dc_dmub_cmd *dc_dmub_cmd, 542 unsigned int dmub_cmd_count, 543 struct block_sequence block_sequence[], 544 unsigned int *num_steps, 545 struct pipe_ctx *pipe_ctx, 546 struct dc_stream_status *stream_status, 547 struct dc_state *context); 548 549 void hwss_wait_for_all_blank_complete(struct dc *dc, 550 struct dc_state *context); 551 552 void hwss_wait_for_odm_update_pending_complete(struct dc *dc, 553 struct dc_state *context); 554 555 void hwss_wait_for_no_pipes_pending(struct dc *dc, 556 struct dc_state *context); 557 558 void hwss_wait_for_outstanding_hw_updates(struct dc *dc, 559 struct dc_state *dc_context); 560 561 void hwss_process_outstanding_hw_updates(struct dc *dc, 562 struct dc_state *dc_context); 563 564 void hwss_send_dmcub_cmd(union block_sequence_params *params); 565 566 void hwss_program_manual_trigger(union block_sequence_params *params); 567 568 void hwss_setup_dpp(union block_sequence_params *params); 569 570 void hwss_program_bias_and_scale(union block_sequence_params *params); 571 572 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params); 573 574 void hwss_set_output_csc(union block_sequence_params *params); 575 576 void hwss_set_ocsc_default(union block_sequence_params *params); 577 578 void hwss_subvp_save_surf_addr(union block_sequence_params *params); 579 580 #endif /* __DC_HW_SEQUENCER_H__ */ 581