1 /* 2 * Copyright 2015-2026 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "inc/clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/opp.h" 32 #include "inc/hw/link_encoder.h" 33 #include "inc/core_status.h" 34 #include "inc/hw/hw_shared.h" 35 #include "dsc/dsc.h" 36 37 struct pipe_ctx; 38 struct dc_state; 39 struct dc_stream_status; 40 struct dc_writeback_info; 41 struct dchub_init_data; 42 struct dc_static_screen_params; 43 struct resource_pool; 44 struct dc_phy_addr_space_config; 45 struct dc_virtual_addr_space_config; 46 struct dpp; 47 struct dce_hwseq; 48 struct link_resource; 49 struct dc_dmub_cmd; 50 struct pg_block_update; 51 struct drr_params; 52 struct dc_underflow_debug_data; 53 struct dsc_optc_config; 54 struct vm_system_aperture_param; 55 struct memory_qos; 56 struct subvp_pipe_control_lock_fast_params { 57 struct dc *dc; 58 bool lock; 59 bool subvp_immediate_flip; 60 }; 61 62 struct pipe_control_lock_params { 63 struct dc *dc; 64 struct pipe_ctx *pipe_ctx; 65 bool lock; 66 }; 67 68 struct set_flip_control_gsl_params { 69 struct hubp *hubp; 70 bool flip_immediate; 71 }; 72 73 struct program_triplebuffer_params { 74 const struct dc *dc; 75 struct pipe_ctx *pipe_ctx; 76 bool enableTripleBuffer; 77 }; 78 79 struct update_plane_addr_params { 80 struct dc *dc; 81 struct pipe_ctx *pipe_ctx; 82 }; 83 84 struct set_input_transfer_func_params { 85 struct dc *dc; 86 struct pipe_ctx *pipe_ctx; 87 struct dc_plane_state *plane_state; 88 }; 89 90 struct program_gamut_remap_params { 91 struct pipe_ctx *pipe_ctx; 92 }; 93 94 struct program_manual_trigger_params { 95 struct pipe_ctx *pipe_ctx; 96 }; 97 98 struct send_dmcub_cmd_params { 99 struct dc_context *ctx; 100 union dmub_rb_cmd *cmd; 101 enum dm_dmub_wait_type wait_type; 102 }; 103 104 struct setup_dpp_params { 105 struct pipe_ctx *pipe_ctx; 106 }; 107 108 struct program_bias_and_scale_params { 109 struct pipe_ctx *pipe_ctx; 110 }; 111 112 struct set_output_transfer_func_params { 113 struct dc *dc; 114 struct pipe_ctx *pipe_ctx; 115 const struct dc_stream_state *stream; 116 }; 117 118 struct update_visual_confirm_params { 119 struct dc *dc; 120 struct pipe_ctx *pipe_ctx; 121 int mpcc_id; 122 }; 123 124 struct power_on_mpc_mem_pwr_params { 125 struct mpc *mpc; 126 int mpcc_id; 127 bool power_on; 128 }; 129 130 struct set_output_csc_params { 131 struct mpc *mpc; 132 int opp_id; 133 const uint16_t *regval; 134 enum mpc_output_csc_mode ocsc_mode; 135 }; 136 137 struct set_ocsc_default_params { 138 struct mpc *mpc; 139 int opp_id; 140 enum dc_color_space color_space; 141 enum mpc_output_csc_mode ocsc_mode; 142 }; 143 144 struct subvp_save_surf_addr { 145 struct dc_dmub_srv *dc_dmub_srv; 146 const struct dc_plane_address *addr; 147 uint8_t subvp_index; 148 }; 149 150 struct wait_for_dcc_meta_propagation_params { 151 const struct dc *dc; 152 const struct pipe_ctx *top_pipe_to_program; 153 }; 154 155 struct dmub_hw_control_lock_fast_params { 156 struct dc *dc; 157 bool is_required; 158 bool lock; 159 }; 160 161 struct program_surface_config_params { 162 struct hubp *hubp; 163 enum surface_pixel_format format; 164 struct dc_tiling_info *tiling_info; 165 struct plane_size plane_size; 166 enum dc_rotation_angle rotation; 167 struct dc_plane_dcc_param *dcc; 168 bool horizontal_mirror; 169 int compat_level; 170 }; 171 172 struct program_mcache_id_and_split_coordinate { 173 struct hubp *hubp; 174 struct dml2_hubp_pipe_mcache_regs *mcache_regs; 175 }; 176 177 struct control_cm_hist_params { 178 struct dpp *dpp; 179 struct cm_hist_control cm_hist_control; 180 enum dc_color_space color_space; 181 }; 182 183 struct program_cursor_update_now_params { 184 struct dc *dc; 185 struct pipe_ctx *pipe_ctx; 186 }; 187 188 struct hubp_wait_pipe_read_start_params { 189 struct hubp *hubp; 190 }; 191 192 struct apply_update_flags_for_phantom_params { 193 struct pipe_ctx *pipe_ctx; 194 }; 195 196 struct update_phantom_vp_position_params { 197 struct dc *dc; 198 struct pipe_ctx *pipe_ctx; 199 struct dc_state *context; 200 }; 201 202 struct set_odm_combine_params { 203 struct timing_generator *tg; 204 int opp_inst[MAX_PIPES]; 205 int opp_head_count; 206 int odm_slice_width; 207 int last_odm_slice_width; 208 }; 209 210 struct set_odm_bypass_params { 211 struct timing_generator *tg; 212 const struct dc_crtc_timing *timing; 213 }; 214 215 struct opp_pipe_clock_control_params { 216 struct output_pixel_processor *opp; 217 bool enable; 218 }; 219 220 struct opp_program_left_edge_extra_pixel_params { 221 struct output_pixel_processor *opp; 222 enum dc_pixel_encoding pixel_encoding; 223 bool is_otg_master; 224 }; 225 226 struct dccg_set_dto_dscclk_params { 227 struct dccg *dccg; 228 int inst; 229 int num_slices_h; 230 }; 231 232 struct dsc_set_config_params { 233 struct display_stream_compressor *dsc; 234 struct dsc_config *dsc_cfg; 235 struct dsc_optc_config *dsc_optc_cfg; 236 }; 237 238 struct dsc_enable_params { 239 struct display_stream_compressor *dsc; 240 int opp_inst; 241 }; 242 243 struct tg_set_dsc_config_params { 244 struct timing_generator *tg; 245 struct dsc_optc_config *dsc_optc_cfg; 246 bool enable; 247 }; 248 249 struct dsc_disconnect_params { 250 struct display_stream_compressor *dsc; 251 }; 252 253 struct dsc_read_state_params { 254 struct display_stream_compressor *dsc; 255 struct dcn_dsc_state *dsc_state; 256 }; 257 258 struct dsc_calculate_and_set_config_params { 259 struct pipe_ctx *pipe_ctx; 260 struct dsc_optc_config dsc_optc_cfg; 261 bool enable; 262 int opp_cnt; 263 }; 264 265 struct dsc_enable_with_opp_params { 266 struct pipe_ctx *pipe_ctx; 267 }; 268 269 struct program_tg_params { 270 struct dc *dc; 271 struct pipe_ctx *pipe_ctx; 272 struct dc_state *context; 273 }; 274 275 struct tg_program_global_sync_params { 276 struct timing_generator *tg; 277 int vready_offset; 278 unsigned int vstartup_lines; 279 unsigned int vupdate_offset_pixels; 280 unsigned int vupdate_vupdate_width_pixels; 281 unsigned int pstate_keepout_start_lines; 282 }; 283 284 struct tg_wait_for_state_params { 285 struct timing_generator *tg; 286 enum crtc_state state; 287 }; 288 289 struct tg_set_vtg_params_params { 290 struct timing_generator *tg; 291 struct dc_crtc_timing *timing; 292 bool program_fp2; 293 }; 294 295 struct tg_set_gsl_params { 296 struct timing_generator *tg; 297 struct gsl_params gsl; 298 }; 299 300 struct tg_set_gsl_source_select_params { 301 struct timing_generator *tg; 302 int group_idx; 303 uint32_t gsl_ready_signal; 304 }; 305 306 struct setup_vupdate_interrupt_params { 307 struct dc *dc; 308 struct pipe_ctx *pipe_ctx; 309 }; 310 311 struct tg_setup_vertical_interrupt2_params { 312 struct timing_generator *tg; 313 int start_line; 314 }; 315 316 struct dpp_set_hdr_multiplier_params { 317 struct dpp *dpp; 318 uint32_t hw_mult; 319 }; 320 321 struct program_det_size_params { 322 struct hubbub *hubbub; 323 unsigned int hubp_inst; 324 unsigned int det_buffer_size_kb; 325 }; 326 327 struct program_det_segments_params { 328 struct hubbub *hubbub; 329 unsigned int hubp_inst; 330 unsigned int det_size; 331 }; 332 333 struct update_dchubp_dpp_params { 334 struct dc *dc; 335 struct pipe_ctx *pipe_ctx; 336 struct dc_state *context; 337 }; 338 339 struct opp_set_dyn_expansion_params { 340 struct output_pixel_processor *opp; 341 enum dc_color_space color_space; 342 enum dc_color_depth color_depth; 343 enum signal_type signal; 344 }; 345 346 struct opp_program_fmt_params { 347 struct output_pixel_processor *opp; 348 struct bit_depth_reduction_params *fmt_bit_depth; 349 struct clamping_and_pixel_encoding_params *clamping; 350 }; 351 352 struct opp_program_bit_depth_reduction_params { 353 struct output_pixel_processor *opp; 354 bool use_default_params; 355 struct pipe_ctx *pipe_ctx; 356 }; 357 358 struct opp_set_disp_pattern_generator_params { 359 struct output_pixel_processor *opp; 360 enum controller_dp_test_pattern test_pattern; 361 enum controller_dp_color_space color_space; 362 enum dc_color_depth color_depth; 363 struct tg_color solid_color; 364 bool use_solid_color; 365 int width; 366 int height; 367 int offset; 368 }; 369 370 struct set_abm_pipe_params { 371 struct dc *dc; 372 struct pipe_ctx *pipe_ctx; 373 }; 374 375 struct set_abm_level_params { 376 struct abm *abm; 377 unsigned int abm_level; 378 }; 379 380 struct set_abm_immediate_disable_params { 381 struct dc *dc; 382 struct pipe_ctx *pipe_ctx; 383 }; 384 385 struct set_disp_pattern_generator_params { 386 struct dc *dc; 387 struct pipe_ctx *pipe_ctx; 388 enum controller_dp_test_pattern test_pattern; 389 enum controller_dp_color_space color_space; 390 enum dc_color_depth color_depth; 391 const struct tg_color *solid_color; 392 int width; 393 int height; 394 int offset; 395 }; 396 397 struct mpc_update_blending_params { 398 struct mpc *mpc; 399 struct mpcc_blnd_cfg blnd_cfg; 400 int mpcc_id; 401 }; 402 403 struct mpc_assert_idle_mpcc_params { 404 struct mpc *mpc; 405 int mpcc_id; 406 }; 407 408 struct mpc_insert_plane_params { 409 struct mpc *mpc; 410 struct mpc_tree *mpc_tree_params; 411 struct mpcc_blnd_cfg blnd_cfg; 412 struct mpcc_sm_cfg *sm_cfg; 413 struct mpcc *insert_above_mpcc; 414 int dpp_id; 415 int mpcc_id; 416 }; 417 418 struct mpc_remove_mpcc_params { 419 struct mpc *mpc; 420 struct mpc_tree *mpc_tree_params; 421 struct mpcc *mpcc_to_remove; 422 }; 423 424 struct opp_set_mpcc_disconnect_pending_params { 425 struct output_pixel_processor *opp; 426 int mpcc_inst; 427 bool pending; 428 }; 429 430 struct dc_set_optimized_required_params { 431 struct dc *dc; 432 bool optimized_required; 433 }; 434 435 struct hubp_disconnect_params { 436 struct hubp *hubp; 437 }; 438 439 struct hubbub_force_pstate_change_control_params { 440 struct hubbub *hubbub; 441 bool enable; 442 bool wait; 443 }; 444 445 struct tg_enable_crtc_params { 446 struct timing_generator *tg; 447 }; 448 449 struct hubp_wait_flip_pending_params { 450 struct hubp *hubp; 451 unsigned int timeout_us; 452 unsigned int polling_interval_us; 453 }; 454 455 struct tg_wait_double_buffer_pending_params { 456 struct timing_generator *tg; 457 unsigned int timeout_us; 458 unsigned int polling_interval_us; 459 }; 460 461 struct update_force_pstate_params { 462 struct dc *dc; 463 struct dc_state *context; 464 }; 465 466 struct hubbub_apply_dedcn21_147_wa_params { 467 struct hubbub *hubbub; 468 }; 469 470 struct hubbub_allow_self_refresh_control_params { 471 struct hubbub *hubbub; 472 bool allow; 473 bool *disallow_self_refresh_applied; 474 }; 475 476 struct tg_get_frame_count_params { 477 struct timing_generator *tg; 478 unsigned int *frame_count; 479 }; 480 481 struct mpc_set_dwb_mux_params { 482 struct mpc *mpc; 483 int dwb_id; 484 int mpcc_id; 485 }; 486 487 struct mpc_disable_dwb_mux_params { 488 struct mpc *mpc; 489 unsigned int dwb_id; 490 }; 491 492 struct mcif_wb_config_buf_params { 493 struct mcif_wb *mcif_wb; 494 struct mcif_buf_params *mcif_buf_params; 495 unsigned int dest_height; 496 }; 497 498 struct mcif_wb_config_arb_params { 499 struct mcif_wb *mcif_wb; 500 struct mcif_arb_params *mcif_arb_params; 501 }; 502 503 struct mcif_wb_enable_params { 504 struct mcif_wb *mcif_wb; 505 }; 506 507 struct mcif_wb_disable_params { 508 struct mcif_wb *mcif_wb; 509 }; 510 511 struct dwbc_enable_params { 512 struct dwbc *dwb; 513 struct dc_dwb_params *dwb_params; 514 }; 515 516 struct dwbc_disable_params { 517 struct dwbc *dwb; 518 }; 519 520 struct dwbc_update_params { 521 struct dwbc *dwb; 522 struct dc_dwb_params *dwb_params; 523 }; 524 525 struct hubp_update_mall_sel_params { 526 struct hubp *hubp; 527 uint32_t mall_sel; 528 bool cache_cursor; 529 }; 530 531 struct hubp_prepare_subvp_buffering_params { 532 struct hubp *hubp; 533 bool enable; 534 }; 535 536 struct hubp_set_blank_en_params { 537 struct hubp *hubp; 538 bool enable; 539 }; 540 541 struct hubp_disable_control_params { 542 struct hubp *hubp; 543 bool disable; 544 }; 545 546 struct hubbub_soft_reset_params { 547 struct hubbub *hubbub; 548 void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset); 549 bool reset; 550 }; 551 552 struct hubp_clk_cntl_params { 553 struct hubp *hubp; 554 bool enable; 555 }; 556 557 struct hubp_init_params { 558 struct hubp *hubp; 559 }; 560 561 struct hubp_set_vm_system_aperture_settings_params { 562 struct hubp *hubp; 563 //struct vm_system_aperture_param apt; 564 PHYSICAL_ADDRESS_LOC sys_default; 565 PHYSICAL_ADDRESS_LOC sys_low; 566 PHYSICAL_ADDRESS_LOC sys_high; 567 }; 568 569 struct hubp_set_flip_int_params { 570 struct hubp *hubp; 571 }; 572 573 struct dpp_dppclk_control_params { 574 struct dpp *dpp; 575 bool dppclk_div; 576 bool enable; 577 }; 578 579 struct disable_phantom_crtc_params { 580 struct timing_generator *tg; 581 }; 582 583 struct dpp_pg_control_params { 584 struct dce_hwseq *hws; 585 unsigned int dpp_inst; 586 bool power_on; 587 }; 588 589 struct hubp_pg_control_params { 590 struct dce_hwseq *hws; 591 unsigned int hubp_inst; 592 bool power_on; 593 }; 594 595 struct hubp_reset_params { 596 struct hubp *hubp; 597 }; 598 599 struct dpp_reset_params { 600 struct dpp *dpp; 601 }; 602 603 struct dpp_root_clock_control_params { 604 struct dce_hwseq *hws; 605 unsigned int dpp_inst; 606 bool clock_on; 607 }; 608 609 struct dc_ip_request_cntl_params { 610 struct dc *dc; 611 bool enable; 612 }; 613 614 struct dsc_pg_status_params { 615 struct dce_hwseq *hws; 616 int dsc_inst; 617 bool is_ungated; 618 }; 619 620 struct dsc_wait_disconnect_pending_clear_params { 621 struct display_stream_compressor *dsc; 622 bool *is_ungated; 623 }; 624 625 struct dsc_disable_params { 626 struct display_stream_compressor *dsc; 627 bool *is_ungated; 628 }; 629 630 struct dccg_set_ref_dscclk_params { 631 struct dccg *dccg; 632 int dsc_inst; 633 bool *is_ungated; 634 }; 635 636 struct dccg_update_dpp_dto_params { 637 struct dccg *dccg; 638 int dpp_inst; 639 int dppclk_khz; 640 }; 641 642 struct hubp_vtg_sel_params { 643 struct hubp *hubp; 644 uint32_t otg_inst; 645 }; 646 647 struct hubp_setup2_params { 648 struct hubp *hubp; 649 struct dml2_dchub_per_pipe_register_set *hubp_regs; 650 union dml2_global_sync_programming *global_sync; 651 struct dc_crtc_timing *timing; 652 }; 653 654 struct hubp_setup_params { 655 struct hubp *hubp; 656 struct _vcs_dpi_display_dlg_regs_st *dlg_regs; 657 struct _vcs_dpi_display_ttu_regs_st *ttu_regs; 658 struct _vcs_dpi_display_rq_regs_st *rq_regs; 659 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest; 660 }; 661 662 struct hubp_set_unbounded_requesting_params { 663 struct hubp *hubp; 664 bool unbounded_req; 665 }; 666 667 struct hubp_setup_interdependent2_params { 668 struct hubp *hubp; 669 struct dml2_dchub_per_pipe_register_set *hubp_regs; 670 }; 671 672 struct hubp_setup_interdependent_params { 673 struct hubp *hubp; 674 struct _vcs_dpi_display_dlg_regs_st *dlg_regs; 675 struct _vcs_dpi_display_ttu_regs_st *ttu_regs; 676 }; 677 678 struct dpp_set_cursor_matrix_params { 679 struct dpp *dpp; 680 enum dc_color_space color_space; 681 struct dc_csc_transform *cursor_csc_color_matrix; 682 }; 683 684 struct mpc_update_mpcc_params { 685 struct dc *dc; 686 struct pipe_ctx *pipe_ctx; 687 }; 688 689 struct dpp_set_scaler_params { 690 struct dpp *dpp; 691 const struct scaler_data *scl_data; 692 }; 693 694 struct hubp_mem_program_viewport_params { 695 struct hubp *hubp; 696 const struct rect *viewport; 697 const struct rect *viewport_c; 698 }; 699 700 struct hubp_program_mcache_id_and_split_coordinate_params { 701 struct hubp *hubp; 702 struct mcache_regs_struct *mcache_regs; 703 }; 704 705 struct abort_cursor_offload_update_params { 706 struct dc *dc; 707 struct pipe_ctx *pipe_ctx; 708 }; 709 710 struct set_cursor_attribute_params { 711 struct dc *dc; 712 struct pipe_ctx *pipe_ctx; 713 }; 714 715 struct set_cursor_position_params { 716 struct dc *dc; 717 struct pipe_ctx *pipe_ctx; 718 }; 719 720 struct set_cursor_sdr_white_level_params { 721 struct dc *dc; 722 struct pipe_ctx *pipe_ctx; 723 }; 724 725 struct program_output_csc_params { 726 struct dc *dc; 727 struct pipe_ctx *pipe_ctx; 728 enum dc_color_space colorspace; 729 uint16_t *matrix; 730 int opp_id; 731 }; 732 733 struct hubp_set_blank_params { 734 struct hubp *hubp; 735 bool blank; 736 }; 737 738 struct phantom_hubp_post_enable_params { 739 struct hubp *hubp; 740 }; 741 742 union block_sequence_params { 743 struct update_plane_addr_params update_plane_addr_params; 744 struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params; 745 struct pipe_control_lock_params pipe_control_lock_params; 746 struct set_flip_control_gsl_params set_flip_control_gsl_params; 747 struct program_triplebuffer_params program_triplebuffer_params; 748 struct set_input_transfer_func_params set_input_transfer_func_params; 749 struct program_gamut_remap_params program_gamut_remap_params; 750 struct program_manual_trigger_params program_manual_trigger_params; 751 struct send_dmcub_cmd_params send_dmcub_cmd_params; 752 struct setup_dpp_params setup_dpp_params; 753 struct program_bias_and_scale_params program_bias_and_scale_params; 754 struct set_output_transfer_func_params set_output_transfer_func_params; 755 struct update_visual_confirm_params update_visual_confirm_params; 756 struct power_on_mpc_mem_pwr_params power_on_mpc_mem_pwr_params; 757 struct set_output_csc_params set_output_csc_params; 758 struct set_ocsc_default_params set_ocsc_default_params; 759 struct subvp_save_surf_addr subvp_save_surf_addr; 760 struct wait_for_dcc_meta_propagation_params wait_for_dcc_meta_propagation_params; 761 struct dmub_hw_control_lock_fast_params dmub_hw_control_lock_fast_params; 762 struct program_surface_config_params program_surface_config_params; 763 struct program_mcache_id_and_split_coordinate program_mcache_id_and_split_coordinate; 764 struct control_cm_hist_params control_cm_hist_params; 765 struct program_cursor_update_now_params program_cursor_update_now_params; 766 struct hubp_wait_pipe_read_start_params hubp_wait_pipe_read_start_params; 767 struct apply_update_flags_for_phantom_params apply_update_flags_for_phantom_params; 768 struct update_phantom_vp_position_params update_phantom_vp_position_params; 769 struct set_odm_combine_params set_odm_combine_params; 770 struct set_odm_bypass_params set_odm_bypass_params; 771 struct opp_pipe_clock_control_params opp_pipe_clock_control_params; 772 struct opp_program_left_edge_extra_pixel_params opp_program_left_edge_extra_pixel_params; 773 struct dccg_set_dto_dscclk_params dccg_set_dto_dscclk_params; 774 struct dsc_set_config_params dsc_set_config_params; 775 struct dsc_enable_params dsc_enable_params; 776 struct tg_set_dsc_config_params tg_set_dsc_config_params; 777 struct dsc_disconnect_params dsc_disconnect_params; 778 struct dsc_read_state_params dsc_read_state_params; 779 struct dsc_calculate_and_set_config_params dsc_calculate_and_set_config_params; 780 struct dsc_enable_with_opp_params dsc_enable_with_opp_params; 781 struct program_tg_params program_tg_params; 782 struct tg_program_global_sync_params tg_program_global_sync_params; 783 struct tg_wait_for_state_params tg_wait_for_state_params; 784 struct tg_set_vtg_params_params tg_set_vtg_params_params; 785 struct tg_setup_vertical_interrupt2_params tg_setup_vertical_interrupt2_params; 786 struct dpp_set_hdr_multiplier_params dpp_set_hdr_multiplier_params; 787 struct tg_set_gsl_params tg_set_gsl_params; 788 struct tg_set_gsl_source_select_params tg_set_gsl_source_select_params; 789 struct setup_vupdate_interrupt_params setup_vupdate_interrupt_params; 790 struct program_det_size_params program_det_size_params; 791 struct program_det_segments_params program_det_segments_params; 792 struct update_dchubp_dpp_params update_dchubp_dpp_params; 793 struct opp_set_dyn_expansion_params opp_set_dyn_expansion_params; 794 struct opp_program_fmt_params opp_program_fmt_params; 795 struct opp_program_bit_depth_reduction_params opp_program_bit_depth_reduction_params; 796 struct opp_set_disp_pattern_generator_params opp_set_disp_pattern_generator_params; 797 struct set_abm_pipe_params set_abm_pipe_params; 798 struct set_abm_level_params set_abm_level_params; 799 struct set_abm_immediate_disable_params set_abm_immediate_disable_params; 800 struct set_disp_pattern_generator_params set_disp_pattern_generator_params; 801 struct mpc_remove_mpcc_params mpc_remove_mpcc_params; 802 struct opp_set_mpcc_disconnect_pending_params opp_set_mpcc_disconnect_pending_params; 803 struct dc_set_optimized_required_params dc_set_optimized_required_params; 804 struct hubp_disconnect_params hubp_disconnect_params; 805 struct hubbub_force_pstate_change_control_params hubbub_force_pstate_change_control_params; 806 struct tg_enable_crtc_params tg_enable_crtc_params; 807 struct hubp_wait_flip_pending_params hubp_wait_flip_pending_params; 808 struct tg_wait_double_buffer_pending_params tg_wait_double_buffer_pending_params; 809 struct update_force_pstate_params update_force_pstate_params; 810 struct hubbub_apply_dedcn21_147_wa_params hubbub_apply_dedcn21_147_wa_params; 811 struct hubbub_allow_self_refresh_control_params hubbub_allow_self_refresh_control_params; 812 struct tg_get_frame_count_params tg_get_frame_count_params; 813 struct mpc_set_dwb_mux_params mpc_set_dwb_mux_params; 814 struct mpc_disable_dwb_mux_params mpc_disable_dwb_mux_params; 815 struct mcif_wb_config_buf_params mcif_wb_config_buf_params; 816 struct mcif_wb_config_arb_params mcif_wb_config_arb_params; 817 struct mcif_wb_enable_params mcif_wb_enable_params; 818 struct mcif_wb_disable_params mcif_wb_disable_params; 819 struct dwbc_enable_params dwbc_enable_params; 820 struct dwbc_disable_params dwbc_disable_params; 821 struct dwbc_update_params dwbc_update_params; 822 struct hubp_update_mall_sel_params hubp_update_mall_sel_params; 823 struct hubp_prepare_subvp_buffering_params hubp_prepare_subvp_buffering_params; 824 struct hubp_set_blank_en_params hubp_set_blank_en_params; 825 struct hubp_disable_control_params hubp_disable_control_params; 826 struct hubbub_soft_reset_params hubbub_soft_reset_params; 827 struct hubp_clk_cntl_params hubp_clk_cntl_params; 828 struct hubp_init_params hubp_init_params; 829 struct hubp_set_vm_system_aperture_settings_params hubp_set_vm_system_aperture_settings_params; 830 struct hubp_set_flip_int_params hubp_set_flip_int_params; 831 struct dpp_dppclk_control_params dpp_dppclk_control_params; 832 struct disable_phantom_crtc_params disable_phantom_crtc_params; 833 struct dpp_pg_control_params dpp_pg_control_params; 834 struct hubp_pg_control_params hubp_pg_control_params; 835 struct hubp_reset_params hubp_reset_params; 836 struct dpp_reset_params dpp_reset_params; 837 struct dpp_root_clock_control_params dpp_root_clock_control_params; 838 struct dc_ip_request_cntl_params dc_ip_request_cntl_params; 839 struct dsc_pg_status_params dsc_pg_status_params; 840 struct dsc_wait_disconnect_pending_clear_params dsc_wait_disconnect_pending_clear_params; 841 struct dsc_disable_params dsc_disable_params; 842 struct dccg_set_ref_dscclk_params dccg_set_ref_dscclk_params; 843 struct dccg_update_dpp_dto_params dccg_update_dpp_dto_params; 844 struct hubp_vtg_sel_params hubp_vtg_sel_params; 845 struct hubp_setup2_params hubp_setup2_params; 846 struct hubp_setup_params hubp_setup_params; 847 struct hubp_set_unbounded_requesting_params hubp_set_unbounded_requesting_params; 848 struct hubp_setup_interdependent2_params hubp_setup_interdependent2_params; 849 struct hubp_setup_interdependent_params hubp_setup_interdependent_params; 850 struct dpp_set_cursor_matrix_params dpp_set_cursor_matrix_params; 851 struct mpc_update_mpcc_params mpc_update_mpcc_params; 852 struct mpc_update_blending_params mpc_update_blending_params; 853 struct mpc_assert_idle_mpcc_params mpc_assert_idle_mpcc_params; 854 struct mpc_insert_plane_params mpc_insert_plane_params; 855 struct dpp_set_scaler_params dpp_set_scaler_params; 856 struct hubp_mem_program_viewport_params hubp_mem_program_viewport_params; 857 struct abort_cursor_offload_update_params abort_cursor_offload_update_params; 858 struct set_cursor_attribute_params set_cursor_attribute_params; 859 struct set_cursor_position_params set_cursor_position_params; 860 struct set_cursor_sdr_white_level_params set_cursor_sdr_white_level_params; 861 struct program_output_csc_params program_output_csc_params; 862 struct hubp_set_blank_params hubp_set_blank_params; 863 struct phantom_hubp_post_enable_params phantom_hubp_post_enable_params; 864 }; 865 866 enum block_sequence_func { 867 DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST = 0, 868 OPTC_PIPE_CONTROL_LOCK, 869 HUBP_SET_FLIP_CONTROL_GSL, 870 HUBP_PROGRAM_TRIPLEBUFFER, 871 HUBP_UPDATE_PLANE_ADDR, 872 DPP_SET_INPUT_TRANSFER_FUNC, 873 DPP_PROGRAM_GAMUT_REMAP, 874 OPTC_PROGRAM_MANUAL_TRIGGER, 875 DMUB_SEND_DMCUB_CMD, 876 DPP_SETUP_DPP, 877 DPP_PROGRAM_BIAS_AND_SCALE, 878 DPP_SET_OUTPUT_TRANSFER_FUNC, 879 DPP_SET_HDR_MULTIPLIER, 880 MPC_UPDATE_VISUAL_CONFIRM, 881 MPC_POWER_ON_MPC_MEM_PWR, 882 MPC_SET_OUTPUT_CSC, 883 MPC_SET_OCSC_DEFAULT, 884 DMUB_SUBVP_SAVE_SURF_ADDR, 885 HUBP_WAIT_FOR_DCC_META_PROP, 886 DMUB_HW_CONTROL_LOCK_FAST, 887 HUBP_PROGRAM_SURFACE_CONFIG, 888 HUBP_PROGRAM_MCACHE_ID, 889 DPP_PROGRAM_CM_HIST, 890 PROGRAM_CURSOR_UPDATE_NOW, 891 HUBP_WAIT_PIPE_READ_START, 892 HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM, 893 HWS_UPDATE_PHANTOM_VP_POSITION, 894 OPTC_SET_ODM_COMBINE, 895 OPTC_SET_ODM_BYPASS, 896 OPP_PIPE_CLOCK_CONTROL, 897 OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL, 898 DCCG_SET_DTO_DSCCLK, 899 DSC_SET_CONFIG, 900 DSC_ENABLE, 901 TG_SET_DSC_CONFIG, 902 DSC_DISCONNECT, 903 DSC_READ_STATE, 904 DSC_CALCULATE_AND_SET_CONFIG, 905 DSC_ENABLE_WITH_OPP, 906 TG_PROGRAM_GLOBAL_SYNC, 907 TG_WAIT_FOR_STATE, 908 TG_SET_VTG_PARAMS, 909 TG_SETUP_VERTICAL_INTERRUPT2, 910 HUBP_PROGRAM_DET_SIZE, 911 HUBP_PROGRAM_DET_SEGMENTS, 912 OPP_SET_DYN_EXPANSION, 913 OPP_PROGRAM_FMT, 914 OPP_PROGRAM_BIT_DEPTH_REDUCTION, 915 OPP_SET_DISP_PATTERN_GENERATOR, 916 ABM_SET_PIPE, 917 ABM_SET_LEVEL, 918 ABM_SET_IMMEDIATE_DISABLE, 919 MPC_REMOVE_MPCC, 920 OPP_SET_MPCC_DISCONNECT_PENDING, 921 DC_SET_OPTIMIZED_REQUIRED, 922 HUBP_DISCONNECT, 923 HUBBUB_FORCE_PSTATE_CHANGE_CONTROL, 924 TG_ENABLE_CRTC, 925 TG_SET_GSL, 926 TG_SET_GSL_SOURCE_SELECT, 927 HUBP_WAIT_FLIP_PENDING, 928 TG_WAIT_DOUBLE_BUFFER_PENDING, 929 UPDATE_FORCE_PSTATE, 930 PROGRAM_MALL_PIPE_CONFIG, 931 HUBBUB_APPLY_DEDCN21_147_WA, 932 HUBBUB_ALLOW_SELF_REFRESH_CONTROL, 933 TG_GET_FRAME_COUNT, 934 MPC_SET_DWB_MUX, 935 MPC_DISABLE_DWB_MUX, 936 MCIF_WB_CONFIG_BUF, 937 MCIF_WB_CONFIG_ARB, 938 MCIF_WB_ENABLE, 939 MCIF_WB_DISABLE, 940 DWBC_ENABLE, 941 DWBC_DISABLE, 942 DWBC_UPDATE, 943 HUBP_UPDATE_MALL_SEL, 944 HUBP_PREPARE_SUBVP_BUFFERING, 945 HUBP_SET_BLANK_EN, 946 HUBP_DISABLE_CONTROL, 947 HUBBUB_SOFT_RESET, 948 HUBP_CLK_CNTL, 949 HUBP_INIT, 950 HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS, 951 HUBP_SET_FLIP_INT, 952 DPP_DPPCLK_CONTROL, 953 DISABLE_PHANTOM_CRTC, 954 DSC_PG_STATUS, 955 DSC_WAIT_DISCONNECT_PENDING_CLEAR, 956 DSC_DISABLE, 957 DCCG_SET_REF_DSCCLK, 958 DPP_PG_CONTROL, 959 HUBP_PG_CONTROL, 960 HUBP_RESET, 961 DPP_RESET, 962 DPP_ROOT_CLOCK_CONTROL, 963 DC_IP_REQUEST_CNTL, 964 DCCG_UPDATE_DPP_DTO, 965 HUBP_VTG_SEL, 966 HUBP_SETUP2, 967 HUBP_SETUP, 968 HUBP_SET_UNBOUNDED_REQUESTING, 969 HUBP_SETUP_INTERDEPENDENT2, 970 HUBP_SETUP_INTERDEPENDENT, 971 DPP_SET_CURSOR_MATRIX, 972 MPC_UPDATE_BLENDING, 973 MPC_ASSERT_IDLE_MPCC, 974 MPC_INSERT_PLANE, 975 DPP_SET_SCALER, 976 HUBP_MEM_PROGRAM_VIEWPORT, 977 ABORT_CURSOR_OFFLOAD_UPDATE, 978 SET_CURSOR_ATTRIBUTE, 979 SET_CURSOR_POSITION, 980 SET_CURSOR_SDR_WHITE_LEVEL, 981 PROGRAM_OUTPUT_CSC, 982 HUBP_SET_LEGACY_TILING_COMPAT_LEVEL, 983 HUBP_SET_BLANK, 984 PHANTOM_HUBP_POST_ENABLE, 985 /* This must be the last value in this enum, add new ones above */ 986 HWSS_BLOCK_SEQUENCE_FUNC_COUNT 987 }; 988 989 struct block_sequence { 990 union block_sequence_params params; 991 enum block_sequence_func func; 992 }; 993 994 struct block_sequence_state { 995 struct block_sequence *steps; 996 unsigned int *num_steps; 997 }; 998 999 #define MAX_HWSS_BLOCK_SEQUENCE_SIZE (HWSS_BLOCK_SEQUENCE_FUNC_COUNT * MAX_PIPES) 1000 1001 struct hw_sequencer_funcs { 1002 void (*hardware_release)(struct dc *dc); 1003 /* Embedded Display Related */ 1004 void (*edp_power_control)(struct dc_link *link, bool enable); 1005 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 1006 void (*edp_wait_for_T12)(struct dc_link *link); 1007 1008 /* Pipe Programming Related */ 1009 void (*init_hw)(struct dc *dc); 1010 void (*power_down_on_boot)(struct dc *dc); 1011 void (*enable_accelerated_mode)(struct dc *dc, 1012 struct dc_state *context); 1013 enum dc_status (*apply_ctx_to_hw)(struct dc *dc, 1014 struct dc_state *context); 1015 void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx); 1016 void (*disable_plane_sequence)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx, 1017 struct block_sequence_state *seq_state); 1018 void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank); 1019 void (*apply_ctx_for_surface)(struct dc *dc, 1020 const struct dc_stream_state *stream, 1021 int num_planes, struct dc_state *context); 1022 void (*program_front_end_for_ctx)(struct dc *dc, 1023 struct dc_state *context); 1024 void (*wait_for_pending_cleared)(struct dc *dc, 1025 struct dc_state *context); 1026 void (*post_unlock_program_front_end)(struct dc *dc, 1027 struct dc_state *context); 1028 void (*update_plane_addr)(const struct dc *dc, 1029 struct pipe_ctx *pipe_ctx); 1030 void (*update_dchub)(struct dce_hwseq *hws, 1031 struct dchub_init_data *dh_data); 1032 void (*wait_for_mpcc_disconnect)(struct dc *dc, 1033 struct resource_pool *res_pool, 1034 struct pipe_ctx *pipe_ctx); 1035 void (*wait_for_mpcc_disconnect_sequence)(struct dc *dc, 1036 struct resource_pool *res_pool, 1037 struct pipe_ctx *pipe_ctx, 1038 struct block_sequence_state *seq_state); 1039 void (*edp_backlight_control)( 1040 struct dc_link *link, 1041 bool enable); 1042 void (*program_triplebuffer)(const struct dc *dc, 1043 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 1044 void (*update_pending_status)(struct pipe_ctx *pipe_ctx); 1045 void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable); 1046 void (*clear_surface_dcc_and_tiling)(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling); 1047 1048 /* Pipe Lock Related */ 1049 void (*pipe_control_lock)(struct dc *dc, 1050 struct pipe_ctx *pipe, bool lock); 1051 void (*interdependent_update_lock)(struct dc *dc, 1052 struct dc_state *context, bool lock); 1053 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx, 1054 bool flip_immediate); 1055 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock); 1056 1057 /* Timing Related */ 1058 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 1059 struct crtc_position *position); 1060 int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); 1061 void (*calc_vupdate_position)( 1062 struct dc *dc, 1063 struct pipe_ctx *pipe_ctx, 1064 uint32_t *start_line, 1065 uint32_t *end_line); 1066 void (*enable_per_frame_crtc_position_reset)(struct dc *dc, 1067 int group_size, struct pipe_ctx *grouped_pipes[]); 1068 void (*enable_timing_synchronization)(struct dc *dc, 1069 struct dc_state *state, 1070 int group_index, int group_size, 1071 struct pipe_ctx *grouped_pipes[]); 1072 void (*enable_vblanks_synchronization)(struct dc *dc, 1073 int group_index, int group_size, 1074 struct pipe_ctx *grouped_pipes[]); 1075 void (*setup_periodic_interrupt)(struct dc *dc, 1076 struct pipe_ctx *pipe_ctx); 1077 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 1078 struct dc_crtc_timing_adjust adjust); 1079 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 1080 int num_pipes, 1081 const struct dc_static_screen_params *events); 1082 1083 /* Stream Related */ 1084 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 1085 void (*disable_stream)(struct pipe_ctx *pipe_ctx); 1086 void (*blank_stream)(struct pipe_ctx *pipe_ctx); 1087 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 1088 struct dc_link_settings *link_settings); 1089 1090 /* Bandwidth Related */ 1091 void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context); 1092 bool (*update_bandwidth)(struct dc *dc, struct dc_state *context); 1093 void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context); 1094 1095 /* Infopacket Related */ 1096 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 1097 void (*send_immediate_sdp_message)( 1098 struct pipe_ctx *pipe_ctx, 1099 const uint8_t *custom_sdp_message, 1100 unsigned int sdp_message_size); 1101 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 1102 void (*set_dmdata_attributes)(struct pipe_ctx *pipe); 1103 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); 1104 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); 1105 1106 /* Cursor Related */ 1107 void (*set_cursor_position)(struct pipe_ctx *pipe); 1108 void (*set_cursor_attribute)(struct pipe_ctx *pipe); 1109 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); 1110 void (*abort_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe); 1111 void (*begin_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe); 1112 void (*commit_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe); 1113 void (*update_cursor_offload_pipe)(struct dc *dc, const struct pipe_ctx *pipe); 1114 void (*notify_cursor_offload_drr_update)(struct dc *dc, struct dc_state *context, 1115 const struct dc_stream_state *stream); 1116 void (*program_cursor_offload_now)(struct dc *dc, const struct pipe_ctx *pipe); 1117 1118 /* Colour Related */ 1119 void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); 1120 void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, 1121 enum dc_color_space colorspace, 1122 uint16_t *matrix, int opp_id); 1123 void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx); 1124 1125 /* VM Related */ 1126 int (*init_sys_ctx)(struct dce_hwseq *hws, 1127 struct dc *dc, 1128 struct dc_phy_addr_space_config *pa_config); 1129 void (*init_vm_ctx)(struct dce_hwseq *hws, 1130 struct dc *dc, 1131 struct dc_virtual_addr_space_config *va_config, 1132 int vmid); 1133 1134 /* Writeback Related */ 1135 void (*update_writeback)(struct dc *dc, 1136 struct dc_writeback_info *wb_info, 1137 struct dc_state *context); 1138 void (*enable_writeback)(struct dc *dc, 1139 struct dc_writeback_info *wb_info, 1140 struct dc_state *context); 1141 void (*disable_writeback)(struct dc *dc, 1142 unsigned int dwb_pipe_inst); 1143 1144 /* Clock Related */ 1145 enum dc_status (*set_clock)(struct dc *dc, 1146 enum dc_clock_type clock_type, 1147 uint32_t clk_khz, uint32_t stepping); 1148 void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type, 1149 struct dc_clock_config *clock_cfg); 1150 void (*optimize_pwr_state)(const struct dc *dc, 1151 struct dc_state *context); 1152 void (*exit_optimized_pwr_state)(const struct dc *dc, 1153 struct dc_state *context); 1154 void (*calculate_pix_rate_divider)(struct dc *dc, 1155 struct dc_state *context, 1156 const struct dc_stream_state *stream); 1157 1158 /* Audio Related */ 1159 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); 1160 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); 1161 1162 /* Stereo 3D Related */ 1163 void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc); 1164 1165 /* HW State Logging Related */ 1166 void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx); 1167 void (*log_color_state)(struct dc *dc, 1168 struct dc_log_buffer_ctx *log_ctx); 1169 void (*get_hw_state)(struct dc *dc, char *pBuf, 1170 unsigned int bufSize, unsigned int mask); 1171 void (*clear_status_bits)(struct dc *dc, unsigned int mask); 1172 1173 bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx, 1174 struct set_backlight_level_params *params); 1175 1176 void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx); 1177 1178 void (*set_pipe)(struct pipe_ctx *pipe_ctx); 1179 1180 void (*enable_dp_link_output)(struct dc_link *link, 1181 const struct link_resource *link_res, 1182 enum signal_type signal, 1183 enum clock_source_id clock_source, 1184 const struct dc_link_settings *link_settings); 1185 void (*enable_tmds_link_output)(struct dc_link *link, 1186 const struct link_resource *link_res, 1187 enum signal_type signal, 1188 enum clock_source_id clock_source, 1189 enum dc_color_depth color_depth, 1190 uint32_t pixel_clock); 1191 void (*enable_lvds_link_output)(struct dc_link *link, 1192 const struct link_resource *link_res, 1193 enum clock_source_id clock_source, 1194 uint32_t pixel_clock); 1195 void (*enable_analog_link_output)(struct dc_link *link, 1196 uint32_t pixel_clock); 1197 void (*disable_link_output)(struct dc_link *link, 1198 const struct link_resource *link_res, 1199 enum signal_type signal); 1200 bool (*dac_load_detect)(struct dc_link *link); 1201 void (*prepare_ddc)(struct dc_link *link); 1202 1203 void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits); 1204 1205 /* Idle Optimization Related */ 1206 bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable); 1207 1208 bool (*does_plane_fit_in_mall)(struct dc *dc, 1209 unsigned int pitch, 1210 unsigned int height, 1211 enum surface_pixel_format format, 1212 struct dc_cursor_attributes *cursor_attr); 1213 void (*commit_subvp_config)(struct dc *dc, struct dc_state *context); 1214 void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context); 1215 void (*disable_phantom_streams)(struct dc *dc, struct dc_state *context); 1216 void (*subvp_pipe_control_lock)(struct dc *dc, 1217 struct dc_state *context, 1218 bool lock, 1219 bool should_lock_all_pipes, 1220 struct pipe_ctx *top_pipe_to_program, 1221 bool subvp_prev_use); 1222 void (*subvp_pipe_control_lock_fast)(union block_sequence_params *params); 1223 1224 void (*z10_restore)(const struct dc *dc); 1225 void (*z10_save_init)(struct dc *dc); 1226 bool (*is_abm_supported)(struct dc *dc, 1227 struct dc_state *context, struct dc_stream_state *stream); 1228 1229 void (*set_disp_pattern_generator)(const struct dc *dc, 1230 struct pipe_ctx *pipe_ctx, 1231 enum controller_dp_test_pattern test_pattern, 1232 enum controller_dp_color_space color_space, 1233 enum dc_color_depth color_depth, 1234 const struct tg_color *solid_color, 1235 int width, int height, int offset); 1236 void (*blank_phantom)(struct dc *dc, 1237 struct timing_generator *tg, 1238 int width, 1239 int height); 1240 void (*update_visual_confirm_color)(struct dc *dc, 1241 struct pipe_ctx *pipe_ctx, 1242 int mpcc_id); 1243 void (*update_phantom_vp_position)(struct dc *dc, 1244 struct dc_state *context, 1245 struct pipe_ctx *phantom_pipe); 1246 void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe); 1247 1248 void (*calc_blocks_to_gate)(struct dc *dc, struct dc_state *context, 1249 struct pg_block_update *update_state); 1250 void (*calc_blocks_to_ungate)(struct dc *dc, struct dc_state *context, 1251 struct pg_block_update *update_state); 1252 void (*hw_block_power_up)(struct dc *dc, 1253 struct pg_block_update *update_state); 1254 void (*hw_block_power_down)(struct dc *dc, 1255 struct pg_block_update *update_state); 1256 void (*root_clock_control)(struct dc *dc, 1257 struct pg_block_update *update_state, bool power_on); 1258 bool (*is_pipe_topology_transition_seamless)(struct dc *dc, 1259 const struct dc_state *cur_ctx, 1260 const struct dc_state *new_ctx); 1261 void (*wait_for_dcc_meta_propagation)(const struct dc *dc, 1262 const struct pipe_ctx *top_pipe_to_program); 1263 void (*dmub_hw_control_lock)(struct dc *dc, 1264 struct dc_state *context, 1265 bool lock); 1266 void (*fams2_update_config)(struct dc *dc, 1267 struct dc_state *context, 1268 bool enable); 1269 void (*dmub_hw_control_lock_fast)(union block_sequence_params *params); 1270 void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max); 1271 void (*program_outstanding_updates)(struct dc *dc, 1272 struct dc_state *context); 1273 void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); 1274 void (*wait_for_all_pending_updates)(const struct pipe_ctx *pipe_ctx); 1275 void (*detect_pipe_changes)(struct dc_state *old_state, 1276 struct dc_state *new_state, 1277 struct pipe_ctx *old_pipe, 1278 struct pipe_ctx *new_pipe); 1279 void (*enable_plane)(struct dc *dc, 1280 struct pipe_ctx *pipe_ctx, 1281 struct dc_state *context); 1282 void (*enable_plane_sequence)(struct dc *dc, 1283 struct pipe_ctx *pipe_ctx, 1284 struct dc_state *context, 1285 struct block_sequence_state *seq_state); 1286 void (*update_dchubp_dpp)(struct dc *dc, 1287 struct pipe_ctx *pipe_ctx, 1288 struct dc_state *context); 1289 void (*update_dchubp_dpp_sequence)(struct dc *dc, 1290 struct pipe_ctx *pipe_ctx, 1291 struct dc_state *context, 1292 struct block_sequence_state *seq_state); 1293 void (*post_unlock_reset_opp)(struct dc *dc, 1294 struct pipe_ctx *opp_head); 1295 void (*post_unlock_reset_opp_sequence)( 1296 struct dc *dc, 1297 struct pipe_ctx *opp_head, 1298 struct block_sequence_state *seq_state); 1299 void (*get_underflow_debug_data)(const struct dc *dc, 1300 struct timing_generator *tg, 1301 struct dc_underflow_debug_data *out_data); 1302 1303 /** 1304 * measure_memory_qos - Measure memory QoS metrics 1305 * @dc: DC structure 1306 * @qos: Pointer to memory_qos struct to populate with measured values 1307 * 1308 * Populates the provided memory_qos struct with peak bandwidth, average bandwidth, 1309 * max latency, min latency, and average latency from hardware performance counters. 1310 */ 1311 void (*measure_memory_qos)(struct dc *dc, struct memory_qos *qos); 1312 1313 }; 1314 1315 void color_space_to_black_color( 1316 const struct dc *dc, 1317 enum dc_color_space colorspace, 1318 struct tg_color *black_color); 1319 1320 bool hwss_wait_for_blank_complete( 1321 struct timing_generator *tg); 1322 1323 const uint16_t *find_color_matrix( 1324 enum dc_color_space color_space, 1325 uint32_t *array_size); 1326 1327 void get_surface_tile_visual_confirm_color( 1328 struct pipe_ctx *pipe_ctx, 1329 struct tg_color *color); 1330 void get_surface_visual_confirm_color( 1331 const struct pipe_ctx *pipe_ctx, 1332 struct tg_color *color); 1333 1334 void get_hdr_visual_confirm_color( 1335 struct pipe_ctx *pipe_ctx, 1336 struct tg_color *color); 1337 void get_mpctree_visual_confirm_color( 1338 struct pipe_ctx *pipe_ctx, 1339 struct tg_color *color); 1340 void get_smartmux_visual_confirm_color( 1341 struct dc *dc, 1342 struct tg_color *color); 1343 void get_vabc_visual_confirm_color( 1344 struct pipe_ctx *pipe_ctx, 1345 struct tg_color *color); 1346 void get_subvp_visual_confirm_color( 1347 struct pipe_ctx *pipe_ctx, 1348 struct tg_color *color); 1349 void get_fams2_visual_confirm_color( 1350 struct dc *dc, 1351 struct dc_state *context, 1352 struct pipe_ctx *pipe_ctx, 1353 struct tg_color *color); 1354 1355 void get_mclk_switch_visual_confirm_color( 1356 struct pipe_ctx *pipe_ctx, 1357 struct tg_color *color); 1358 1359 void get_cursor_visual_confirm_color( 1360 struct pipe_ctx *pipe_ctx, 1361 struct tg_color *color); 1362 1363 void get_dcc_visual_confirm_color( 1364 struct dc *dc, 1365 struct pipe_ctx *pipe_ctx, 1366 struct tg_color *color); 1367 1368 void get_refresh_rate_confirm_color( 1369 struct pipe_ctx *pipe_ctx, 1370 struct tg_color *color); 1371 1372 void set_p_state_switch_method( 1373 struct dc *dc, 1374 struct dc_state *context, 1375 struct pipe_ctx *pipe_ctx); 1376 1377 void set_drr_and_clear_adjust_pending( 1378 struct pipe_ctx *pipe_ctx, 1379 struct dc_stream_state *stream, 1380 struct drr_params *params); 1381 1382 void hwss_execute_sequence(struct dc *dc, 1383 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], 1384 int num_steps); 1385 1386 void hwss_build_fast_sequence(struct dc *dc, 1387 struct dc_dmub_cmd *dc_dmub_cmd, 1388 unsigned int dmub_cmd_count, 1389 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], 1390 unsigned int *num_steps, 1391 struct pipe_ctx *pipe_ctx, 1392 struct dc_stream_status *stream_status, 1393 struct dc_state *context); 1394 1395 void hwss_wait_for_all_blank_complete(struct dc *dc, 1396 struct dc_state *context); 1397 1398 void hwss_wait_for_odm_update_pending_complete(struct dc *dc, 1399 struct dc_state *context); 1400 1401 void hwss_wait_for_no_pipes_pending(struct dc *dc, 1402 struct dc_state *context); 1403 1404 void hwss_wait_for_outstanding_hw_updates(struct dc *dc, 1405 struct dc_state *dc_context); 1406 1407 void hwss_process_outstanding_hw_updates(struct dc *dc, 1408 struct dc_state *dc_context); 1409 1410 void hwss_send_dmcub_cmd(union block_sequence_params *params); 1411 1412 void hwss_program_manual_trigger(union block_sequence_params *params); 1413 1414 void hwss_setup_dpp(union block_sequence_params *params); 1415 1416 void hwss_program_bias_and_scale(union block_sequence_params *params); 1417 1418 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params); 1419 1420 void hwss_set_output_csc(union block_sequence_params *params); 1421 1422 void hwss_set_ocsc_default(union block_sequence_params *params); 1423 1424 void hwss_subvp_save_surf_addr(union block_sequence_params *params); 1425 1426 void hwss_program_surface_config(union block_sequence_params *params); 1427 1428 void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *params); 1429 1430 void hwss_program_cm_hist(union block_sequence_params *params); 1431 1432 void hwss_set_odm_combine(union block_sequence_params *params); 1433 1434 void hwss_set_odm_bypass(union block_sequence_params *params); 1435 1436 void hwss_opp_pipe_clock_control(union block_sequence_params *params); 1437 1438 void hwss_opp_program_left_edge_extra_pixel(union block_sequence_params *params); 1439 1440 void hwss_blank_pixel_data(union block_sequence_params *params); 1441 1442 void hwss_dccg_set_dto_dscclk(union block_sequence_params *params); 1443 1444 void hwss_dsc_set_config(union block_sequence_params *params); 1445 1446 void hwss_dsc_enable(union block_sequence_params *params); 1447 1448 void hwss_tg_set_dsc_config(union block_sequence_params *params); 1449 1450 void hwss_dsc_disconnect(union block_sequence_params *params); 1451 1452 void hwss_dsc_read_state(union block_sequence_params *params); 1453 1454 void hwss_dsc_calculate_and_set_config(union block_sequence_params *params); 1455 1456 void hwss_dsc_enable_with_opp(union block_sequence_params *params); 1457 1458 void hwss_program_tg(union block_sequence_params *params); 1459 1460 void hwss_tg_program_global_sync(union block_sequence_params *params); 1461 1462 void hwss_tg_wait_for_state(union block_sequence_params *params); 1463 1464 void hwss_tg_set_vtg_params(union block_sequence_params *params); 1465 1466 void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params); 1467 1468 void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params); 1469 1470 void hwss_program_det_size(union block_sequence_params *params); 1471 1472 void hwss_program_det_segments(union block_sequence_params *params); 1473 1474 void hwss_opp_set_dyn_expansion(union block_sequence_params *params); 1475 1476 void hwss_opp_program_fmt(union block_sequence_params *params); 1477 1478 void hwss_opp_program_bit_depth_reduction(union block_sequence_params *params); 1479 1480 void hwss_opp_set_disp_pattern_generator(union block_sequence_params *params); 1481 1482 void hwss_set_abm_pipe(union block_sequence_params *params); 1483 1484 void hwss_set_abm_level(union block_sequence_params *params); 1485 1486 void hwss_set_abm_immediate_disable(union block_sequence_params *params); 1487 1488 void hwss_mpc_remove_mpcc(union block_sequence_params *params); 1489 1490 void hwss_opp_set_mpcc_disconnect_pending(union block_sequence_params *params); 1491 1492 void hwss_dc_set_optimized_required(union block_sequence_params *params); 1493 1494 void hwss_hubp_disconnect(union block_sequence_params *params); 1495 1496 void hwss_hubbub_force_pstate_change_control(union block_sequence_params *params); 1497 1498 void hwss_tg_enable_crtc(union block_sequence_params *params); 1499 1500 void hwss_tg_set_gsl(union block_sequence_params *params); 1501 1502 void hwss_tg_set_gsl_source_select(union block_sequence_params *params); 1503 1504 void hwss_hubp_wait_flip_pending(union block_sequence_params *params); 1505 1506 void hwss_tg_wait_double_buffer_pending(union block_sequence_params *params); 1507 1508 void hwss_update_force_pstate(union block_sequence_params *params); 1509 1510 void hwss_hubbub_apply_dedcn21_147_wa(union block_sequence_params *params); 1511 1512 void hwss_hubbub_allow_self_refresh_control(union block_sequence_params *params); 1513 1514 void hwss_tg_get_frame_count(union block_sequence_params *params); 1515 1516 void hwss_mpc_set_dwb_mux(union block_sequence_params *params); 1517 1518 void hwss_mpc_disable_dwb_mux(union block_sequence_params *params); 1519 1520 void hwss_mcif_wb_config_buf(union block_sequence_params *params); 1521 1522 void hwss_mcif_wb_config_arb(union block_sequence_params *params); 1523 1524 void hwss_mcif_wb_enable(union block_sequence_params *params); 1525 1526 void hwss_mcif_wb_disable(union block_sequence_params *params); 1527 1528 void hwss_dwbc_enable(union block_sequence_params *params); 1529 1530 void hwss_dwbc_disable(union block_sequence_params *params); 1531 1532 void hwss_dwbc_update(union block_sequence_params *params); 1533 1534 void hwss_hubp_update_mall_sel(union block_sequence_params *params); 1535 1536 void hwss_hubp_prepare_subvp_buffering(union block_sequence_params *params); 1537 1538 void hwss_hubp_set_blank_en(union block_sequence_params *params); 1539 1540 void hwss_hubp_disable_control(union block_sequence_params *params); 1541 1542 void hwss_hubbub_soft_reset(union block_sequence_params *params); 1543 1544 void hwss_hubp_clk_cntl(union block_sequence_params *params); 1545 1546 void hwss_hubp_init(union block_sequence_params *params); 1547 1548 void hwss_hubp_set_vm_system_aperture_settings(union block_sequence_params *params); 1549 1550 void hwss_hubp_set_flip_int(union block_sequence_params *params); 1551 1552 void hwss_dpp_dppclk_control(union block_sequence_params *params); 1553 1554 void hwss_disable_phantom_crtc(union block_sequence_params *params); 1555 1556 void hwss_dsc_pg_status(union block_sequence_params *params); 1557 1558 void hwss_dsc_wait_disconnect_pending_clear(union block_sequence_params *params); 1559 1560 void hwss_dsc_disable(union block_sequence_params *params); 1561 1562 void hwss_dccg_set_ref_dscclk(union block_sequence_params *params); 1563 1564 void hwss_dpp_pg_control(union block_sequence_params *params); 1565 1566 void hwss_hubp_pg_control(union block_sequence_params *params); 1567 1568 void hwss_hubp_reset(union block_sequence_params *params); 1569 1570 void hwss_dpp_reset(union block_sequence_params *params); 1571 1572 void hwss_dpp_root_clock_control(union block_sequence_params *params); 1573 1574 void hwss_dc_ip_request_cntl(union block_sequence_params *params); 1575 1576 void hwss_dccg_update_dpp_dto(union block_sequence_params *params); 1577 1578 void hwss_hubp_vtg_sel(union block_sequence_params *params); 1579 1580 void hwss_hubp_setup2(union block_sequence_params *params); 1581 1582 void hwss_hubp_setup(union block_sequence_params *params); 1583 1584 void hwss_hubp_set_unbounded_requesting(union block_sequence_params *params); 1585 1586 void hwss_hubp_setup_interdependent2(union block_sequence_params *params); 1587 1588 void hwss_hubp_setup_interdependent(union block_sequence_params *params); 1589 1590 void hwss_dpp_set_cursor_matrix(union block_sequence_params *params); 1591 1592 void hwss_mpc_update_mpcc(union block_sequence_params *params); 1593 1594 void hwss_mpc_update_blending(union block_sequence_params *params); 1595 1596 void hwss_mpc_assert_idle_mpcc(union block_sequence_params *params); 1597 1598 void hwss_mpc_insert_plane(union block_sequence_params *params); 1599 1600 void hwss_dpp_set_scaler(union block_sequence_params *params); 1601 1602 void hwss_hubp_mem_program_viewport(union block_sequence_params *params); 1603 1604 void hwss_abort_cursor_offload_update(union block_sequence_params *params); 1605 1606 void hwss_set_cursor_attribute(union block_sequence_params *params); 1607 1608 void hwss_set_cursor_position(union block_sequence_params *params); 1609 1610 void hwss_set_cursor_sdr_white_level(union block_sequence_params *params); 1611 1612 void hwss_program_output_csc(union block_sequence_params *params); 1613 1614 void hwss_hubp_set_legacy_tiling_compat_level(union block_sequence_params *params); 1615 1616 void hwss_hubp_set_blank(union block_sequence_params *params); 1617 1618 void hwss_phantom_hubp_post_enable(union block_sequence_params *params); 1619 1620 void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state, 1621 struct dc *dc, struct pipe_ctx *pipe_ctx, bool lock); 1622 1623 void hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state *seq_state, 1624 struct hubp *hubp, bool flip_immediate); 1625 1626 void hwss_add_hubp_program_triplebuffer(struct block_sequence_state *seq_state, 1627 struct dc *dc, struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 1628 1629 void hwss_add_hubp_update_plane_addr(struct block_sequence_state *seq_state, 1630 struct dc *dc, struct pipe_ctx *pipe_ctx); 1631 1632 void hwss_add_dpp_set_input_transfer_func(struct block_sequence_state *seq_state, 1633 struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state); 1634 1635 void hwss_add_dpp_program_gamut_remap(struct block_sequence_state *seq_state, 1636 struct pipe_ctx *pipe_ctx); 1637 1638 void hwss_add_dpp_program_bias_and_scale(struct block_sequence_state *seq_state, 1639 struct pipe_ctx *pipe_ctx); 1640 1641 void hwss_add_optc_program_manual_trigger(struct block_sequence_state *seq_state, 1642 struct pipe_ctx *pipe_ctx); 1643 1644 void hwss_add_dpp_set_output_transfer_func(struct block_sequence_state *seq_state, 1645 struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_stream_state *stream); 1646 1647 void hwss_add_mpc_update_visual_confirm(struct block_sequence_state *seq_state, 1648 struct dc *dc, struct pipe_ctx *pipe_ctx, int mpcc_id); 1649 1650 void hwss_add_mpc_power_on_mpc_mem_pwr(struct block_sequence_state *seq_state, 1651 struct mpc *mpc, int mpcc_id, bool power_on); 1652 1653 void hwss_add_mpc_set_output_csc(struct block_sequence_state *seq_state, 1654 struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode); 1655 1656 void hwss_add_mpc_set_ocsc_default(struct block_sequence_state *seq_state, 1657 struct mpc *mpc, int opp_id, enum dc_color_space colorspace, enum mpc_output_csc_mode ocsc_mode); 1658 1659 void hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state *seq_state, 1660 struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type); 1661 1662 void hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state *seq_state, 1663 struct dc_dmub_srv *dc_dmub_srv, struct dc_plane_address *addr, uint8_t subvp_index); 1664 1665 void hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state *seq_state, 1666 struct dc *dc, struct pipe_ctx *top_pipe_to_program); 1667 1668 void hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state *seq_state, 1669 struct hubp *hubp); 1670 1671 void hwss_add_hws_apply_update_flags_for_phantom(struct block_sequence_state *seq_state, 1672 struct pipe_ctx *pipe_ctx); 1673 1674 void hwss_add_hws_update_phantom_vp_position(struct block_sequence_state *seq_state, 1675 struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); 1676 1677 void hwss_add_optc_set_odm_combine(struct block_sequence_state *seq_state, 1678 struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count, 1679 int odm_slice_width, int last_odm_slice_width); 1680 1681 void hwss_add_optc_set_odm_bypass(struct block_sequence_state *seq_state, 1682 struct timing_generator *optc, struct dc_crtc_timing *timing); 1683 1684 void hwss_add_tg_program_global_sync(struct block_sequence_state *seq_state, 1685 struct timing_generator *tg, 1686 int vready_offset, 1687 unsigned int vstartup_lines, 1688 unsigned int vupdate_offset_pixels, 1689 unsigned int vupdate_vupdate_width_pixels, 1690 unsigned int pstate_keepout_start_lines); 1691 1692 void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state, 1693 struct timing_generator *tg, enum crtc_state state); 1694 1695 void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state, 1696 struct timing_generator *tg, struct dc_crtc_timing *dc_crtc_timing, bool program_fp2); 1697 1698 void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state, 1699 struct timing_generator *tg, int start_line); 1700 1701 void hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state *seq_state, 1702 struct dpp *dpp, uint32_t hw_mult); 1703 1704 void hwss_add_hubp_program_det_size(struct block_sequence_state *seq_state, 1705 struct hubbub *hubbub, unsigned int hubp_inst, unsigned int det_buffer_size_kb); 1706 1707 void hwss_add_hubp_program_mcache_id(struct block_sequence_state *seq_state, 1708 struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs); 1709 1710 void hwss_add_hubbub_force_pstate_change_control(struct block_sequence_state *seq_state, 1711 struct hubbub *hubbub, bool enable, bool wait); 1712 1713 void hwss_add_hubp_program_det_segments(struct block_sequence_state *seq_state, 1714 struct hubbub *hubbub, unsigned int hubp_inst, unsigned int det_size); 1715 1716 void hwss_add_opp_set_dyn_expansion(struct block_sequence_state *seq_state, 1717 struct output_pixel_processor *opp, enum dc_color_space color_sp, 1718 enum dc_color_depth color_dpth, enum signal_type signal); 1719 1720 void hwss_add_opp_program_fmt(struct block_sequence_state *seq_state, 1721 struct output_pixel_processor *opp, struct bit_depth_reduction_params *fmt_bit_depth, 1722 struct clamping_and_pixel_encoding_params *clamping); 1723 1724 void hwss_add_abm_set_pipe(struct block_sequence_state *seq_state, 1725 struct dc *dc, struct pipe_ctx *pipe_ctx); 1726 1727 void hwss_add_abm_set_level(struct block_sequence_state *seq_state, 1728 struct abm *abm, uint32_t abm_level); 1729 1730 void hwss_add_tg_enable_crtc(struct block_sequence_state *seq_state, 1731 struct timing_generator *tg); 1732 1733 void hwss_add_hubp_wait_flip_pending(struct block_sequence_state *seq_state, 1734 struct hubp *hubp, unsigned int timeout_us, unsigned int polling_interval_us); 1735 1736 void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_state, 1737 struct timing_generator *tg, unsigned int timeout_us, unsigned int polling_interval_us); 1738 1739 void hwss_add_dccg_set_dto_dscclk(struct block_sequence_state *seq_state, 1740 struct dccg *dccg, int inst, int num_slices_h); 1741 1742 void hwss_add_dsc_calculate_and_set_config(struct block_sequence_state *seq_state, 1743 struct pipe_ctx *pipe_ctx, bool enable, int opp_cnt); 1744 1745 void hwss_add_mpc_remove_mpcc(struct block_sequence_state *seq_state, 1746 struct mpc *mpc, struct mpc_tree *mpc_tree_params, struct mpcc *mpcc_to_remove); 1747 1748 void hwss_add_opp_set_mpcc_disconnect_pending(struct block_sequence_state *seq_state, 1749 struct output_pixel_processor *opp, int mpcc_inst, bool pending); 1750 1751 void hwss_add_hubp_disconnect(struct block_sequence_state *seq_state, 1752 struct hubp *hubp); 1753 1754 void hwss_add_dsc_enable_with_opp(struct block_sequence_state *seq_state, 1755 struct pipe_ctx *pipe_ctx); 1756 1757 void hwss_add_dsc_disconnect(struct block_sequence_state *seq_state, 1758 struct display_stream_compressor *dsc); 1759 1760 void hwss_add_dc_set_optimized_required(struct block_sequence_state *seq_state, 1761 struct dc *dc, bool optimized_required); 1762 1763 void hwss_add_abm_set_immediate_disable(struct block_sequence_state *seq_state, 1764 struct dc *dc, struct pipe_ctx *pipe_ctx); 1765 1766 void hwss_add_opp_set_disp_pattern_generator(struct block_sequence_state *seq_state, 1767 struct output_pixel_processor *opp, 1768 enum controller_dp_test_pattern test_pattern, 1769 enum controller_dp_color_space color_space, 1770 enum dc_color_depth color_depth, 1771 struct tg_color solid_color, 1772 bool use_solid_color, 1773 int width, 1774 int height, 1775 int offset); 1776 1777 void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_state, 1778 struct output_pixel_processor *opp, 1779 bool use_default_params, 1780 struct pipe_ctx *pipe_ctx); 1781 1782 void hwss_add_dpp_program_cm_hist(struct block_sequence_state *seq_state, 1783 struct dpp *dpp, 1784 struct cm_hist_control cm_hist_control, 1785 enum dc_color_space color_space); 1786 1787 void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state, 1788 struct dc *dc, 1789 bool enable); 1790 1791 void hwss_add_dwbc_update(struct block_sequence_state *seq_state, 1792 struct dwbc *dwb, 1793 struct dc_dwb_params *dwb_params); 1794 1795 void hwss_add_mcif_wb_config_buf(struct block_sequence_state *seq_state, 1796 struct mcif_wb *mcif_wb, 1797 struct mcif_buf_params *mcif_buf_params, 1798 unsigned int dest_height); 1799 1800 void hwss_add_mcif_wb_config_arb(struct block_sequence_state *seq_state, 1801 struct mcif_wb *mcif_wb, 1802 struct mcif_arb_params *mcif_arb_params); 1803 1804 void hwss_add_mcif_wb_enable(struct block_sequence_state *seq_state, 1805 struct mcif_wb *mcif_wb); 1806 1807 void hwss_add_mcif_wb_disable(struct block_sequence_state *seq_state, 1808 struct mcif_wb *mcif_wb); 1809 1810 void hwss_add_mpc_set_dwb_mux(struct block_sequence_state *seq_state, 1811 struct mpc *mpc, 1812 int dwb_id, 1813 int mpcc_id); 1814 1815 void hwss_add_mpc_disable_dwb_mux(struct block_sequence_state *seq_state, 1816 struct mpc *mpc, 1817 unsigned int dwb_id); 1818 1819 void hwss_add_dwbc_enable(struct block_sequence_state *seq_state, 1820 struct dwbc *dwb, 1821 struct dc_dwb_params *dwb_params); 1822 1823 void hwss_add_dwbc_disable(struct block_sequence_state *seq_state, 1824 struct dwbc *dwb); 1825 1826 void hwss_add_tg_set_gsl(struct block_sequence_state *seq_state, 1827 struct timing_generator *tg, 1828 struct gsl_params gsl); 1829 1830 void hwss_add_tg_set_gsl_source_select(struct block_sequence_state *seq_state, 1831 struct timing_generator *tg, 1832 int group_idx, 1833 uint32_t gsl_ready_signal); 1834 1835 void hwss_add_hubp_update_mall_sel(struct block_sequence_state *seq_state, 1836 struct hubp *hubp, 1837 uint32_t mall_sel, 1838 bool cache_cursor); 1839 1840 void hwss_add_hubp_prepare_subvp_buffering(struct block_sequence_state *seq_state, 1841 struct hubp *hubp, 1842 bool enable); 1843 1844 void hwss_add_hubp_set_blank_en(struct block_sequence_state *seq_state, 1845 struct hubp *hubp, 1846 bool enable); 1847 1848 void hwss_add_hubp_disable_control(struct block_sequence_state *seq_state, 1849 struct hubp *hubp, 1850 bool disable); 1851 1852 void hwss_add_hubbub_soft_reset(struct block_sequence_state *seq_state, 1853 struct hubbub *hubbub, 1854 void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset), 1855 bool reset); 1856 1857 void hwss_add_hubp_clk_cntl(struct block_sequence_state *seq_state, 1858 struct hubp *hubp, 1859 bool enable); 1860 1861 void hwss_add_dpp_dppclk_control(struct block_sequence_state *seq_state, 1862 struct dpp *dpp, 1863 bool dppclk_div, 1864 bool enable); 1865 1866 void hwss_add_disable_phantom_crtc(struct block_sequence_state *seq_state, 1867 struct timing_generator *tg); 1868 1869 void hwss_add_dsc_pg_status(struct block_sequence_state *seq_state, 1870 struct dce_hwseq *hws, 1871 int dsc_inst, 1872 bool is_ungated); 1873 1874 void hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state *seq_state, 1875 struct display_stream_compressor *dsc, 1876 bool *is_ungated); 1877 1878 void hwss_add_dsc_disable(struct block_sequence_state *seq_state, 1879 struct display_stream_compressor *dsc, 1880 bool *is_ungated); 1881 1882 void hwss_add_dccg_set_ref_dscclk(struct block_sequence_state *seq_state, 1883 struct dccg *dccg, 1884 int dsc_inst, 1885 bool *is_ungated); 1886 1887 void hwss_add_dpp_root_clock_control(struct block_sequence_state *seq_state, 1888 struct dce_hwseq *hws, 1889 unsigned int dpp_inst, 1890 bool clock_on); 1891 1892 void hwss_add_dpp_pg_control(struct block_sequence_state *seq_state, 1893 struct dce_hwseq *hws, 1894 unsigned int dpp_inst, 1895 bool power_on); 1896 1897 void hwss_add_hubp_pg_control(struct block_sequence_state *seq_state, 1898 struct dce_hwseq *hws, 1899 unsigned int hubp_inst, 1900 bool power_on); 1901 1902 void hwss_add_hubp_set_blank(struct block_sequence_state *seq_state, 1903 struct hubp *hubp, 1904 bool blank); 1905 1906 void hwss_add_hubp_init(struct block_sequence_state *seq_state, 1907 struct hubp *hubp); 1908 1909 void hwss_add_hubp_reset(struct block_sequence_state *seq_state, 1910 struct hubp *hubp); 1911 1912 void hwss_add_dpp_reset(struct block_sequence_state *seq_state, 1913 struct dpp *dpp); 1914 1915 void hwss_add_opp_pipe_clock_control(struct block_sequence_state *seq_state, 1916 struct output_pixel_processor *opp, 1917 bool enable); 1918 1919 void hwss_add_hubp_set_vm_system_aperture_settings(struct block_sequence_state *seq_state, 1920 struct hubp *hubp, 1921 uint64_t sys_default, 1922 uint64_t sys_low, 1923 uint64_t sys_high); 1924 1925 void hwss_add_hubp_set_flip_int(struct block_sequence_state *seq_state, 1926 struct hubp *hubp); 1927 1928 void hwss_add_dccg_update_dpp_dto(struct block_sequence_state *seq_state, 1929 struct dccg *dccg, 1930 int dpp_inst, 1931 int dppclk_khz); 1932 1933 void hwss_add_hubp_vtg_sel(struct block_sequence_state *seq_state, 1934 struct hubp *hubp, 1935 uint32_t otg_inst); 1936 1937 void hwss_add_hubp_setup2(struct block_sequence_state *seq_state, 1938 struct hubp *hubp, 1939 struct dml2_dchub_per_pipe_register_set *hubp_regs, 1940 union dml2_global_sync_programming *global_sync, 1941 struct dc_crtc_timing *timing); 1942 1943 void hwss_add_hubp_setup(struct block_sequence_state *seq_state, 1944 struct hubp *hubp, 1945 struct _vcs_dpi_display_dlg_regs_st *dlg_regs, 1946 struct _vcs_dpi_display_ttu_regs_st *ttu_regs, 1947 struct _vcs_dpi_display_rq_regs_st *rq_regs, 1948 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); 1949 1950 void hwss_add_hubp_set_unbounded_requesting(struct block_sequence_state *seq_state, 1951 struct hubp *hubp, 1952 bool unbounded_req); 1953 1954 void hwss_add_hubp_setup_interdependent2(struct block_sequence_state *seq_state, 1955 struct hubp *hubp, 1956 struct dml2_dchub_per_pipe_register_set *hubp_regs); 1957 1958 void hwss_add_hubp_setup_interdependent(struct block_sequence_state *seq_state, 1959 struct hubp *hubp, 1960 struct _vcs_dpi_display_dlg_regs_st *dlg_regs, 1961 struct _vcs_dpi_display_ttu_regs_st *ttu_regs); 1962 void hwss_add_hubp_program_surface_config(struct block_sequence_state *seq_state, 1963 struct hubp *hubp, 1964 enum surface_pixel_format format, 1965 struct dc_tiling_info *tiling_info, 1966 struct plane_size plane_size, 1967 enum dc_rotation_angle rotation, 1968 struct dc_plane_dcc_param *dcc, 1969 bool horizontal_mirror, 1970 int compat_level); 1971 1972 void hwss_add_dpp_setup_dpp(struct block_sequence_state *seq_state, 1973 struct pipe_ctx *pipe_ctx); 1974 1975 void hwss_add_dpp_set_cursor_matrix(struct block_sequence_state *seq_state, 1976 struct dpp *dpp, 1977 enum dc_color_space color_space, 1978 struct dc_csc_transform *cursor_csc_color_matrix); 1979 1980 void hwss_add_mpc_update_blending(struct block_sequence_state *seq_state, 1981 struct mpc *mpc, 1982 struct mpcc_blnd_cfg blnd_cfg, 1983 int mpcc_id); 1984 1985 void hwss_add_mpc_assert_idle_mpcc(struct block_sequence_state *seq_state, 1986 struct mpc *mpc, 1987 int mpcc_id); 1988 1989 void hwss_add_mpc_insert_plane(struct block_sequence_state *seq_state, 1990 struct mpc *mpc, 1991 struct mpc_tree *mpc_tree_params, 1992 struct mpcc_blnd_cfg blnd_cfg, 1993 struct mpcc_sm_cfg *sm_cfg, 1994 struct mpcc *insert_above_mpcc, 1995 int dpp_id, 1996 int mpcc_id); 1997 1998 void hwss_add_dpp_set_scaler(struct block_sequence_state *seq_state, 1999 struct dpp *dpp, 2000 const struct scaler_data *scl_data); 2001 2002 void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state, 2003 struct hubp *hubp, 2004 const struct rect *viewport, 2005 const struct rect *viewport_c); 2006 2007 void hwss_add_abort_cursor_offload_update(struct block_sequence_state *seq_state, 2008 struct dc *dc, 2009 struct pipe_ctx *pipe_ctx); 2010 2011 void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state, 2012 struct dc *dc, 2013 struct pipe_ctx *pipe_ctx); 2014 2015 void hwss_add_set_cursor_position(struct block_sequence_state *seq_state, 2016 struct dc *dc, 2017 struct pipe_ctx *pipe_ctx); 2018 2019 void hwss_add_set_cursor_sdr_white_level(struct block_sequence_state *seq_state, 2020 struct dc *dc, 2021 struct pipe_ctx *pipe_ctx); 2022 2023 void hwss_add_program_output_csc(struct block_sequence_state *seq_state, 2024 struct dc *dc, 2025 struct pipe_ctx *pipe_ctx, 2026 enum dc_color_space colorspace, 2027 uint16_t *matrix, 2028 int opp_id); 2029 2030 void hwss_add_phantom_hubp_post_enable(struct block_sequence_state *seq_state, 2031 struct hubp *hubp); 2032 2033 void hwss_add_update_force_pstate(struct block_sequence_state *seq_state, 2034 struct dc *dc, 2035 struct dc_state *context); 2036 2037 void hwss_add_hubbub_apply_dedcn21_147_wa(struct block_sequence_state *seq_state, 2038 struct hubbub *hubbub); 2039 2040 void hwss_add_hubbub_allow_self_refresh_control(struct block_sequence_state *seq_state, 2041 struct hubbub *hubbub, 2042 bool allow, 2043 bool *disallow_self_refresh_applied); 2044 2045 void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state, 2046 struct timing_generator *tg, 2047 unsigned int *frame_count); 2048 2049 void hwss_add_tg_set_dsc_config(struct block_sequence_state *seq_state, 2050 struct timing_generator *tg, 2051 struct dsc_optc_config *dsc_optc_cfg, 2052 bool enable); 2053 2054 void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq_state, 2055 struct output_pixel_processor *opp, 2056 enum dc_pixel_encoding pixel_encoding, 2057 bool is_otg_master); 2058 2059 #endif /* __DC_HW_SEQUENCER_H__ */ 2060