1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /*
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
4 */
5
6 #include "ena_com.h"
7
8 /*****************************************************************************/
9 /*****************************************************************************/
10
11 /* Timeout in micro-sec */
12 #define ADMIN_CMD_TIMEOUT_US (3000000)
13
14 #define ENA_ASYNC_QUEUE_DEPTH 16
15 #define ENA_ADMIN_QUEUE_DEPTH 32
16
17
18 #define ENA_CTRL_MAJOR 0
19 #define ENA_CTRL_MINOR 0
20 #define ENA_CTRL_SUB_MINOR 1
21
22 #define MIN_ENA_CTRL_VER \
23 (((ENA_CTRL_MAJOR) << \
24 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
25 ((ENA_CTRL_MINOR) << \
26 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
27 (ENA_CTRL_SUB_MINOR))
28
29 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x)))
30 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32))
31
32 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
33
34 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4
35
36 #define ENA_REGS_ADMIN_INTR_MASK 1
37
38 #define ENA_MAX_BACKOFF_DELAY_EXP 16U
39
40 #define ENA_MIN_ADMIN_POLL_US 100
41
42 #define ENA_MAX_ADMIN_POLL_US 5000
43
44 /*****************************************************************************/
45 /*****************************************************************************/
46 /*****************************************************************************/
47
48 enum ena_cmd_status {
49 ENA_CMD_SUBMITTED,
50 ENA_CMD_COMPLETED,
51 /* Abort - canceled by the driver */
52 ENA_CMD_ABORTED,
53 };
54
55 struct ena_comp_ctx {
56 struct completion wait_event;
57 struct ena_admin_acq_entry *user_cqe;
58 u32 comp_size;
59 enum ena_cmd_status status;
60 /* status from the device */
61 u8 comp_status;
62 u8 cmd_opcode;
63 bool occupied;
64 };
65
66 struct ena_com_stats_ctx {
67 struct ena_admin_aq_get_stats_cmd get_cmd;
68 struct ena_admin_acq_get_stats_resp get_resp;
69 };
70
ena_com_mem_addr_set(struct ena_com_dev * ena_dev,struct ena_common_mem_addr * ena_addr,dma_addr_t addr)71 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
72 struct ena_common_mem_addr *ena_addr,
73 dma_addr_t addr)
74 {
75 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
76 netdev_err(ena_dev->net_device,
77 "DMA address has more bits that the device supports\n");
78 return -EINVAL;
79 }
80
81 ena_addr->mem_addr_low = lower_32_bits(addr);
82 ena_addr->mem_addr_high = (u16)upper_32_bits(addr);
83
84 return 0;
85 }
86
ena_com_admin_init_sq(struct ena_com_admin_queue * admin_queue)87 static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue)
88 {
89 struct ena_com_dev *ena_dev = admin_queue->ena_dev;
90 struct ena_com_admin_sq *sq = &admin_queue->sq;
91 u16 size = ADMIN_SQ_SIZE(admin_queue->q_depth);
92
93 sq->entries = dma_alloc_coherent(admin_queue->q_dmadev, size, &sq->dma_addr, GFP_KERNEL);
94
95 if (!sq->entries) {
96 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
97 return -ENOMEM;
98 }
99
100 sq->head = 0;
101 sq->tail = 0;
102 sq->phase = 1;
103
104 sq->db_addr = NULL;
105
106 return 0;
107 }
108
ena_com_admin_init_cq(struct ena_com_admin_queue * admin_queue)109 static int ena_com_admin_init_cq(struct ena_com_admin_queue *admin_queue)
110 {
111 struct ena_com_dev *ena_dev = admin_queue->ena_dev;
112 struct ena_com_admin_cq *cq = &admin_queue->cq;
113 u16 size = ADMIN_CQ_SIZE(admin_queue->q_depth);
114
115 cq->entries = dma_alloc_coherent(admin_queue->q_dmadev, size, &cq->dma_addr, GFP_KERNEL);
116
117 if (!cq->entries) {
118 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
119 return -ENOMEM;
120 }
121
122 cq->head = 0;
123 cq->phase = 1;
124
125 return 0;
126 }
127
ena_com_admin_init_aenq(struct ena_com_dev * ena_dev,struct ena_aenq_handlers * aenq_handlers)128 static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev,
129 struct ena_aenq_handlers *aenq_handlers)
130 {
131 struct ena_com_aenq *aenq = &ena_dev->aenq;
132 u32 addr_low, addr_high, aenq_caps;
133 u16 size;
134
135 ena_dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
136 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
137 aenq->entries = dma_alloc_coherent(ena_dev->dmadev, size, &aenq->dma_addr, GFP_KERNEL);
138
139 if (!aenq->entries) {
140 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
141 return -ENOMEM;
142 }
143
144 aenq->head = aenq->q_depth;
145 aenq->phase = 1;
146
147 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
148 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
149
150 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
151 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
152
153 aenq_caps = 0;
154 aenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
155 aenq_caps |=
156 (sizeof(struct ena_admin_aenq_entry) << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
157 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
158 writel(aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
159
160 if (unlikely(!aenq_handlers)) {
161 netdev_err(ena_dev->net_device, "AENQ handlers pointer is NULL\n");
162 return -EINVAL;
163 }
164
165 aenq->aenq_handlers = aenq_handlers;
166
167 return 0;
168 }
169
comp_ctxt_release(struct ena_com_admin_queue * queue,struct ena_comp_ctx * comp_ctx)170 static void comp_ctxt_release(struct ena_com_admin_queue *queue,
171 struct ena_comp_ctx *comp_ctx)
172 {
173 comp_ctx->occupied = false;
174 atomic_dec(&queue->outstanding_cmds);
175 }
176
get_comp_ctxt(struct ena_com_admin_queue * admin_queue,u16 command_id,bool capture)177 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *admin_queue,
178 u16 command_id, bool capture)
179 {
180 if (unlikely(command_id >= admin_queue->q_depth)) {
181 netdev_err(admin_queue->ena_dev->net_device,
182 "Command id is larger than the queue size. cmd_id: %u queue size %d\n",
183 command_id, admin_queue->q_depth);
184 return NULL;
185 }
186
187 if (unlikely(!admin_queue->comp_ctx)) {
188 netdev_err(admin_queue->ena_dev->net_device, "Completion context is NULL\n");
189 return NULL;
190 }
191
192 if (unlikely(admin_queue->comp_ctx[command_id].occupied && capture)) {
193 netdev_err(admin_queue->ena_dev->net_device, "Completion context is occupied\n");
194 return NULL;
195 }
196
197 if (capture) {
198 atomic_inc(&admin_queue->outstanding_cmds);
199 admin_queue->comp_ctx[command_id].occupied = true;
200 }
201
202 return &admin_queue->comp_ctx[command_id];
203 }
204
__ena_com_submit_admin_cmd(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size_in_bytes,struct ena_admin_acq_entry * comp,size_t comp_size_in_bytes)205 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
206 struct ena_admin_aq_entry *cmd,
207 size_t cmd_size_in_bytes,
208 struct ena_admin_acq_entry *comp,
209 size_t comp_size_in_bytes)
210 {
211 struct ena_comp_ctx *comp_ctx;
212 u16 tail_masked, cmd_id;
213 u16 queue_size_mask;
214 u16 cnt;
215
216 queue_size_mask = admin_queue->q_depth - 1;
217
218 tail_masked = admin_queue->sq.tail & queue_size_mask;
219
220 /* In case of queue FULL */
221 cnt = (u16)atomic_read(&admin_queue->outstanding_cmds);
222 if (cnt >= admin_queue->q_depth) {
223 netdev_dbg(admin_queue->ena_dev->net_device, "Admin queue is full.\n");
224 admin_queue->stats.out_of_space++;
225 return ERR_PTR(-ENOSPC);
226 }
227
228 cmd_id = admin_queue->curr_cmd_id;
229
230 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
231 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
232
233 cmd->aq_common_descriptor.command_id |= cmd_id &
234 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
235
236 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
237 if (unlikely(!comp_ctx))
238 return ERR_PTR(-EINVAL);
239
240 comp_ctx->status = ENA_CMD_SUBMITTED;
241 comp_ctx->comp_size = (u32)comp_size_in_bytes;
242 comp_ctx->user_cqe = comp;
243 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
244
245 reinit_completion(&comp_ctx->wait_event);
246
247 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
248
249 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
250 queue_size_mask;
251
252 admin_queue->sq.tail++;
253 admin_queue->stats.submitted_cmd++;
254
255 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
256 admin_queue->sq.phase = !admin_queue->sq.phase;
257
258 writel(admin_queue->sq.tail, admin_queue->sq.db_addr);
259
260 return comp_ctx;
261 }
262
ena_com_init_comp_ctxt(struct ena_com_admin_queue * admin_queue)263 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *admin_queue)
264 {
265 struct ena_com_dev *ena_dev = admin_queue->ena_dev;
266 size_t size = admin_queue->q_depth * sizeof(struct ena_comp_ctx);
267 struct ena_comp_ctx *comp_ctx;
268 u16 i;
269
270 admin_queue->comp_ctx = devm_kzalloc(admin_queue->q_dmadev, size, GFP_KERNEL);
271 if (unlikely(!admin_queue->comp_ctx)) {
272 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
273 return -ENOMEM;
274 }
275
276 for (i = 0; i < admin_queue->q_depth; i++) {
277 comp_ctx = get_comp_ctxt(admin_queue, i, false);
278 if (comp_ctx)
279 init_completion(&comp_ctx->wait_event);
280 }
281
282 return 0;
283 }
284
ena_com_submit_admin_cmd(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size_in_bytes,struct ena_admin_acq_entry * comp,size_t comp_size_in_bytes)285 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
286 struct ena_admin_aq_entry *cmd,
287 size_t cmd_size_in_bytes,
288 struct ena_admin_acq_entry *comp,
289 size_t comp_size_in_bytes)
290 {
291 unsigned long flags = 0;
292 struct ena_comp_ctx *comp_ctx;
293
294 spin_lock_irqsave(&admin_queue->q_lock, flags);
295 if (unlikely(!admin_queue->running_state)) {
296 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
297 return ERR_PTR(-ENODEV);
298 }
299 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
300 cmd_size_in_bytes,
301 comp,
302 comp_size_in_bytes);
303 if (IS_ERR(comp_ctx))
304 admin_queue->running_state = false;
305 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
306
307 return comp_ctx;
308 }
309
ena_com_init_io_sq(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx,struct ena_com_io_sq * io_sq)310 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
311 struct ena_com_create_io_ctx *ctx,
312 struct ena_com_io_sq *io_sq)
313 {
314 size_t size;
315
316 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
317
318 io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits;
319 io_sq->desc_entry_size =
320 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
321 sizeof(struct ena_eth_io_tx_desc) :
322 sizeof(struct ena_eth_io_rx_desc);
323
324 size = io_sq->desc_entry_size * io_sq->q_depth;
325
326 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
327 io_sq->desc_addr.virt_addr =
328 dma_alloc_coherent(ena_dev->dmadev, size, &io_sq->desc_addr.phys_addr,
329 GFP_KERNEL);
330 if (!io_sq->desc_addr.virt_addr) {
331 io_sq->desc_addr.virt_addr =
332 dma_alloc_coherent(ena_dev->dmadev, size,
333 &io_sq->desc_addr.phys_addr, GFP_KERNEL);
334 }
335
336 if (!io_sq->desc_addr.virt_addr) {
337 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
338 return -ENOMEM;
339 }
340 }
341
342 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
343 /* Allocate bounce buffers */
344 io_sq->bounce_buf_ctrl.buffer_size =
345 ena_dev->llq_info.desc_list_entry_size;
346 io_sq->bounce_buf_ctrl.buffers_num =
347 ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
348 io_sq->bounce_buf_ctrl.next_to_use = 0;
349
350 size = (size_t)io_sq->bounce_buf_ctrl.buffer_size *
351 io_sq->bounce_buf_ctrl.buffers_num;
352
353 io_sq->bounce_buf_ctrl.base_buffer = devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
354 if (!io_sq->bounce_buf_ctrl.base_buffer)
355 io_sq->bounce_buf_ctrl.base_buffer =
356 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
357
358 if (!io_sq->bounce_buf_ctrl.base_buffer) {
359 netdev_err(ena_dev->net_device, "Bounce buffer memory allocation failed\n");
360 return -ENOMEM;
361 }
362
363 memcpy(&io_sq->llq_info, &ena_dev->llq_info,
364 sizeof(io_sq->llq_info));
365
366 /* Initiate the first bounce buffer */
367 io_sq->llq_buf_ctrl.curr_bounce_buf =
368 ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
369 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
370 0x0, io_sq->llq_info.desc_list_entry_size);
371 io_sq->llq_buf_ctrl.descs_left_in_line =
372 io_sq->llq_info.descs_num_before_header;
373 io_sq->disable_meta_caching =
374 io_sq->llq_info.disable_meta_caching;
375
376 if (io_sq->llq_info.max_entries_in_tx_burst > 0)
377 io_sq->entries_in_tx_burst_left =
378 io_sq->llq_info.max_entries_in_tx_burst;
379 }
380
381 io_sq->tail = 0;
382 io_sq->next_to_comp = 0;
383 io_sq->phase = 1;
384
385 return 0;
386 }
387
ena_com_init_io_cq(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx,struct ena_com_io_cq * io_cq)388 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
389 struct ena_com_create_io_ctx *ctx,
390 struct ena_com_io_cq *io_cq)
391 {
392 size_t size;
393
394 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
395
396 /* Use the basic completion descriptor for Rx */
397 io_cq->cdesc_entry_size_in_bytes =
398 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
399 sizeof(struct ena_eth_io_tx_cdesc) :
400 sizeof(struct ena_eth_io_rx_cdesc_base);
401
402 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
403
404 io_cq->cdesc_addr.virt_addr =
405 dma_alloc_coherent(ena_dev->dmadev, size, &io_cq->cdesc_addr.phys_addr, GFP_KERNEL);
406 if (!io_cq->cdesc_addr.virt_addr) {
407 io_cq->cdesc_addr.virt_addr =
408 dma_alloc_coherent(ena_dev->dmadev, size, &io_cq->cdesc_addr.phys_addr,
409 GFP_KERNEL);
410 }
411
412 if (!io_cq->cdesc_addr.virt_addr) {
413 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
414 return -ENOMEM;
415 }
416
417 io_cq->phase = 1;
418 io_cq->head = 0;
419
420 return 0;
421 }
422
ena_com_handle_single_admin_completion(struct ena_com_admin_queue * admin_queue,struct ena_admin_acq_entry * cqe)423 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
424 struct ena_admin_acq_entry *cqe)
425 {
426 struct ena_comp_ctx *comp_ctx;
427 u16 cmd_id;
428
429 cmd_id = cqe->acq_common_descriptor.command &
430 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
431
432 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
433 if (unlikely(!comp_ctx)) {
434 netdev_err(admin_queue->ena_dev->net_device,
435 "comp_ctx is NULL. Changing the admin queue running state\n");
436 admin_queue->running_state = false;
437 return;
438 }
439
440 comp_ctx->status = ENA_CMD_COMPLETED;
441 comp_ctx->comp_status = cqe->acq_common_descriptor.status;
442
443 if (comp_ctx->user_cqe)
444 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
445
446 if (!admin_queue->polling)
447 complete(&comp_ctx->wait_event);
448 }
449
ena_com_handle_admin_completion(struct ena_com_admin_queue * admin_queue)450 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
451 {
452 struct ena_admin_acq_entry *cqe = NULL;
453 u16 comp_num = 0;
454 u16 head_masked;
455 u8 phase;
456
457 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
458 phase = admin_queue->cq.phase;
459
460 cqe = &admin_queue->cq.entries[head_masked];
461
462 /* Go over all the completions */
463 while ((READ_ONCE(cqe->acq_common_descriptor.flags) &
464 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
465 /* Do not read the rest of the completion entry before the
466 * phase bit was validated
467 */
468 dma_rmb();
469 ena_com_handle_single_admin_completion(admin_queue, cqe);
470
471 head_masked++;
472 comp_num++;
473 if (unlikely(head_masked == admin_queue->q_depth)) {
474 head_masked = 0;
475 phase = !phase;
476 }
477
478 cqe = &admin_queue->cq.entries[head_masked];
479 }
480
481 admin_queue->cq.head += comp_num;
482 admin_queue->cq.phase = phase;
483 admin_queue->sq.head += comp_num;
484 admin_queue->stats.completed_cmd += comp_num;
485 }
486
ena_com_comp_status_to_errno(struct ena_com_admin_queue * admin_queue,u8 comp_status)487 static int ena_com_comp_status_to_errno(struct ena_com_admin_queue *admin_queue,
488 u8 comp_status)
489 {
490 if (unlikely(comp_status != 0))
491 netdev_err(admin_queue->ena_dev->net_device, "Admin command failed[%u]\n",
492 comp_status);
493
494 switch (comp_status) {
495 case ENA_ADMIN_SUCCESS:
496 return 0;
497 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
498 return -ENOMEM;
499 case ENA_ADMIN_UNSUPPORTED_OPCODE:
500 return -EOPNOTSUPP;
501 case ENA_ADMIN_BAD_OPCODE:
502 case ENA_ADMIN_MALFORMED_REQUEST:
503 case ENA_ADMIN_ILLEGAL_PARAMETER:
504 case ENA_ADMIN_UNKNOWN_ERROR:
505 return -EINVAL;
506 case ENA_ADMIN_RESOURCE_BUSY:
507 return -EAGAIN;
508 }
509
510 return -EINVAL;
511 }
512
ena_delay_exponential_backoff_us(u32 exp,u32 delay_us)513 static void ena_delay_exponential_backoff_us(u32 exp, u32 delay_us)
514 {
515 exp = min_t(u32, exp, ENA_MAX_BACKOFF_DELAY_EXP);
516 delay_us = max_t(u32, ENA_MIN_ADMIN_POLL_US, delay_us);
517 delay_us = min_t(u32, delay_us * (1U << exp), ENA_MAX_ADMIN_POLL_US);
518 usleep_range(delay_us, 2 * delay_us);
519 }
520
ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)521 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
522 struct ena_com_admin_queue *admin_queue)
523 {
524 unsigned long flags = 0;
525 unsigned long timeout;
526 int ret;
527 u32 exp = 0;
528
529 timeout = jiffies + usecs_to_jiffies(admin_queue->completion_timeout);
530
531 while (1) {
532 spin_lock_irqsave(&admin_queue->q_lock, flags);
533 ena_com_handle_admin_completion(admin_queue);
534 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
535
536 if (comp_ctx->status != ENA_CMD_SUBMITTED)
537 break;
538
539 if (time_is_before_jiffies(timeout)) {
540 netdev_err(admin_queue->ena_dev->net_device,
541 "Wait for completion (polling) timeout\n");
542 /* ENA didn't have any completion */
543 spin_lock_irqsave(&admin_queue->q_lock, flags);
544 admin_queue->stats.no_completion++;
545 admin_queue->running_state = false;
546 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
547
548 ret = -ETIME;
549 goto err;
550 }
551
552 ena_delay_exponential_backoff_us(exp++,
553 admin_queue->ena_dev->ena_min_poll_delay_us);
554 }
555
556 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
557 netdev_err(admin_queue->ena_dev->net_device, "Command was aborted\n");
558 spin_lock_irqsave(&admin_queue->q_lock, flags);
559 admin_queue->stats.aborted_cmd++;
560 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
561 ret = -ENODEV;
562 goto err;
563 }
564
565 WARN(comp_ctx->status != ENA_CMD_COMPLETED, "Invalid comp status %d\n", comp_ctx->status);
566
567 ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status);
568 err:
569 comp_ctxt_release(admin_queue, comp_ctx);
570 return ret;
571 }
572
573 /*
574 * Set the LLQ configurations of the firmware
575 *
576 * The driver provides only the enabled feature values to the device,
577 * which in turn, checks if they are supported.
578 */
ena_com_set_llq(struct ena_com_dev * ena_dev)579 static int ena_com_set_llq(struct ena_com_dev *ena_dev)
580 {
581 struct ena_com_admin_queue *admin_queue;
582 struct ena_admin_set_feat_cmd cmd;
583 struct ena_admin_set_feat_resp resp;
584 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
585 int ret;
586
587 memset(&cmd, 0x0, sizeof(cmd));
588 admin_queue = &ena_dev->admin_queue;
589
590 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
591 cmd.feat_common.feature_id = ENA_ADMIN_LLQ;
592
593 cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl;
594 cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl;
595 cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header;
596 cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl;
597
598 cmd.u.llq.accel_mode.u.set.enabled_flags =
599 BIT(ENA_ADMIN_DISABLE_META_CACHING) |
600 BIT(ENA_ADMIN_LIMIT_TX_BURST);
601
602 ret = ena_com_execute_admin_command(admin_queue,
603 (struct ena_admin_aq_entry *)&cmd,
604 sizeof(cmd),
605 (struct ena_admin_acq_entry *)&resp,
606 sizeof(resp));
607
608 if (unlikely(ret))
609 netdev_err(ena_dev->net_device, "Failed to set LLQ configurations: %d\n", ret);
610
611 return ret;
612 }
613
ena_com_config_llq_info(struct ena_com_dev * ena_dev,struct ena_admin_feature_llq_desc * llq_features,struct ena_llq_configurations * llq_default_cfg)614 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
615 struct ena_admin_feature_llq_desc *llq_features,
616 struct ena_llq_configurations *llq_default_cfg)
617 {
618 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
619 struct ena_admin_accel_mode_get llq_accel_mode_get;
620 u16 supported_feat;
621 int rc;
622
623 memset(llq_info, 0, sizeof(*llq_info));
624
625 supported_feat = llq_features->header_location_ctrl_supported;
626
627 if (likely(supported_feat & llq_default_cfg->llq_header_location)) {
628 llq_info->header_location_ctrl =
629 llq_default_cfg->llq_header_location;
630 } else {
631 netdev_err(ena_dev->net_device,
632 "Invalid header location control, supported: 0x%x\n", supported_feat);
633 return -EINVAL;
634 }
635
636 if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) {
637 supported_feat = llq_features->descriptors_stride_ctrl_supported;
638 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) {
639 llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl;
640 } else {
641 if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) {
642 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
643 } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) {
644 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
645 } else {
646 netdev_err(ena_dev->net_device,
647 "Invalid desc_stride_ctrl, supported: 0x%x\n",
648 supported_feat);
649 return -EINVAL;
650 }
651
652 netdev_err(ena_dev->net_device,
653 "Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
654 llq_default_cfg->llq_stride_ctrl, supported_feat,
655 llq_info->desc_stride_ctrl);
656 }
657 } else {
658 llq_info->desc_stride_ctrl = 0;
659 }
660
661 supported_feat = llq_features->entry_size_ctrl_supported;
662 if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) {
663 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size;
664 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value;
665 } else {
666 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) {
667 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
668 llq_info->desc_list_entry_size = 128;
669 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) {
670 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B;
671 llq_info->desc_list_entry_size = 192;
672 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) {
673 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B;
674 llq_info->desc_list_entry_size = 256;
675 } else {
676 netdev_err(ena_dev->net_device,
677 "Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat);
678 return -EINVAL;
679 }
680
681 netdev_err(ena_dev->net_device,
682 "Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
683 llq_default_cfg->llq_ring_entry_size, supported_feat,
684 llq_info->desc_list_entry_size);
685 }
686 if (unlikely(llq_info->desc_list_entry_size & 0x7)) {
687 /* The desc list entry size should be whole multiply of 8
688 * This requirement comes from __iowrite64_copy()
689 */
690 netdev_err(ena_dev->net_device, "Illegal entry size %d\n",
691 llq_info->desc_list_entry_size);
692 return -EINVAL;
693 }
694
695 if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)
696 llq_info->descs_per_entry = llq_info->desc_list_entry_size /
697 sizeof(struct ena_eth_io_tx_desc);
698 else
699 llq_info->descs_per_entry = 1;
700
701 supported_feat = llq_features->desc_num_before_header_supported;
702 if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) {
703 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header;
704 } else {
705 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) {
706 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
707 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) {
708 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1;
709 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) {
710 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4;
711 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) {
712 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8;
713 } else {
714 netdev_err(ena_dev->net_device,
715 "Invalid descs_num_before_header, supported: 0x%x\n",
716 supported_feat);
717 return -EINVAL;
718 }
719
720 netdev_err(ena_dev->net_device,
721 "Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
722 llq_default_cfg->llq_num_decs_before_header, supported_feat,
723 llq_info->descs_num_before_header);
724 }
725 /* Check for accelerated queue supported */
726 llq_accel_mode_get = llq_features->accel_mode.u.get;
727
728 llq_info->disable_meta_caching =
729 !!(llq_accel_mode_get.supported_flags &
730 BIT(ENA_ADMIN_DISABLE_META_CACHING));
731
732 if (llq_accel_mode_get.supported_flags & BIT(ENA_ADMIN_LIMIT_TX_BURST))
733 llq_info->max_entries_in_tx_burst =
734 llq_accel_mode_get.max_tx_burst_size /
735 llq_default_cfg->llq_ring_entry_size_value;
736
737 rc = ena_com_set_llq(ena_dev);
738 if (rc)
739 netdev_err(ena_dev->net_device, "Cannot set LLQ configuration: %d\n", rc);
740
741 return rc;
742 }
743
ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)744 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
745 struct ena_com_admin_queue *admin_queue)
746 {
747 unsigned long flags = 0;
748 int ret;
749
750 wait_for_completion_timeout(&comp_ctx->wait_event,
751 usecs_to_jiffies(admin_queue->completion_timeout));
752
753 /* In case the command wasn't completed find out the root cause.
754 * There might be 2 kinds of errors
755 * 1) No completion (timeout reached)
756 * 2) There is completion but the device didn't get any msi-x interrupt.
757 */
758 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
759 spin_lock_irqsave(&admin_queue->q_lock, flags);
760 ena_com_handle_admin_completion(admin_queue);
761 admin_queue->stats.no_completion++;
762 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
763
764 if (comp_ctx->status == ENA_CMD_COMPLETED) {
765 netdev_err(admin_queue->ena_dev->net_device,
766 "The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d)\n",
767 comp_ctx->cmd_opcode);
768 } else {
769 netdev_err(admin_queue->ena_dev->net_device,
770 "The ena device didn't send a completion for the admin cmd %d status %d\n",
771 comp_ctx->cmd_opcode, comp_ctx->status);
772 }
773 admin_queue->running_state = false;
774 ret = -ETIME;
775 goto err;
776 }
777
778 ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status);
779 err:
780 comp_ctxt_release(admin_queue, comp_ctx);
781 return ret;
782 }
783
784 /* This method read the hardware device register through posting writes
785 * and waiting for response
786 * On timeout the function will return ENA_MMIO_READ_TIMEOUT
787 */
ena_com_reg_bar_read32(struct ena_com_dev * ena_dev,u16 offset)788 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
789 {
790 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
791 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
792 mmio_read->read_resp;
793 u32 mmio_read_reg, ret, i;
794 unsigned long flags = 0;
795 u32 timeout = mmio_read->reg_read_to;
796
797 might_sleep();
798
799 if (timeout == 0)
800 timeout = ENA_REG_READ_TIMEOUT;
801
802 /* If readless is disabled, perform regular read */
803 if (!mmio_read->readless_supported)
804 return readl(ena_dev->reg_bar + offset);
805
806 spin_lock_irqsave(&mmio_read->lock, flags);
807 mmio_read->seq_num++;
808
809 read_resp->req_id = mmio_read->seq_num + 0xDEAD;
810 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
811 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
812 mmio_read_reg |= mmio_read->seq_num &
813 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
814
815 writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
816
817 for (i = 0; i < timeout; i++) {
818 if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num)
819 break;
820
821 udelay(1);
822 }
823
824 if (unlikely(i == timeout)) {
825 netdev_err(ena_dev->net_device,
826 "Reading reg failed for timeout. expected: req id[%u] offset[%u] actual: req id[%u] offset[%u]\n",
827 mmio_read->seq_num, offset, read_resp->req_id, read_resp->reg_off);
828 ret = ENA_MMIO_READ_TIMEOUT;
829 goto err;
830 }
831
832 if (read_resp->reg_off != offset) {
833 netdev_err(ena_dev->net_device, "Read failure: wrong offset provided\n");
834 ret = ENA_MMIO_READ_TIMEOUT;
835 } else {
836 ret = read_resp->reg_val;
837 }
838 err:
839 spin_unlock_irqrestore(&mmio_read->lock, flags);
840
841 return ret;
842 }
843
844 /* There are two types to wait for completion.
845 * Polling mode - wait until the completion is available.
846 * Async mode - wait on wait queue until the completion is ready
847 * (or the timeout expired).
848 * It is expected that the IRQ called ena_com_handle_admin_completion
849 * to mark the completions.
850 */
ena_com_wait_and_process_admin_cq(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)851 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
852 struct ena_com_admin_queue *admin_queue)
853 {
854 if (admin_queue->polling)
855 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
856 admin_queue);
857
858 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
859 admin_queue);
860 }
861
ena_com_destroy_io_sq(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq)862 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
863 struct ena_com_io_sq *io_sq)
864 {
865 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
866 struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
867 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
868 u8 direction;
869 int ret;
870
871 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
872
873 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
874 direction = ENA_ADMIN_SQ_DIRECTION_TX;
875 else
876 direction = ENA_ADMIN_SQ_DIRECTION_RX;
877
878 destroy_cmd.sq.sq_identity |= (direction <<
879 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
880 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
881
882 destroy_cmd.sq.sq_idx = io_sq->idx;
883 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
884
885 ret = ena_com_execute_admin_command(admin_queue,
886 (struct ena_admin_aq_entry *)&destroy_cmd,
887 sizeof(destroy_cmd),
888 (struct ena_admin_acq_entry *)&destroy_resp,
889 sizeof(destroy_resp));
890
891 if (unlikely(ret && (ret != -ENODEV)))
892 netdev_err(ena_dev->net_device, "Failed to destroy io sq error: %d\n", ret);
893
894 return ret;
895 }
896
ena_com_io_queue_free(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq,struct ena_com_io_cq * io_cq)897 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
898 struct ena_com_io_sq *io_sq,
899 struct ena_com_io_cq *io_cq)
900 {
901 size_t size;
902
903 if (io_cq->cdesc_addr.virt_addr) {
904 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
905
906 dma_free_coherent(ena_dev->dmadev, size, io_cq->cdesc_addr.virt_addr,
907 io_cq->cdesc_addr.phys_addr);
908
909 io_cq->cdesc_addr.virt_addr = NULL;
910 }
911
912 if (io_sq->desc_addr.virt_addr) {
913 size = io_sq->desc_entry_size * io_sq->q_depth;
914
915 dma_free_coherent(ena_dev->dmadev, size, io_sq->desc_addr.virt_addr,
916 io_sq->desc_addr.phys_addr);
917
918 io_sq->desc_addr.virt_addr = NULL;
919 }
920
921 if (io_sq->bounce_buf_ctrl.base_buffer) {
922 devm_kfree(ena_dev->dmadev, io_sq->bounce_buf_ctrl.base_buffer);
923 io_sq->bounce_buf_ctrl.base_buffer = NULL;
924 }
925 }
926
wait_for_reset_state(struct ena_com_dev * ena_dev,u32 timeout,u16 exp_state)927 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
928 u16 exp_state)
929 {
930 u32 val, exp = 0;
931 unsigned long timeout_stamp;
932
933 /* Convert timeout from resolution of 100ms to us resolution. */
934 timeout_stamp = jiffies + usecs_to_jiffies(100 * 1000 * timeout);
935
936 while (1) {
937 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
938
939 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
940 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n");
941 return -ETIME;
942 }
943
944 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
945 exp_state)
946 return 0;
947
948 if (time_is_before_jiffies(timeout_stamp))
949 return -ETIME;
950
951 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
952 }
953 }
954
ena_com_check_supported_feature_id(struct ena_com_dev * ena_dev,enum ena_admin_aq_feature_id feature_id)955 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
956 enum ena_admin_aq_feature_id feature_id)
957 {
958 u32 feature_mask = 1 << feature_id;
959
960 /* Device attributes is always supported */
961 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
962 !(ena_dev->supported_features & feature_mask))
963 return false;
964
965 return true;
966 }
967
ena_com_get_feature_ex(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * get_resp,enum ena_admin_aq_feature_id feature_id,dma_addr_t control_buf_dma_addr,u32 control_buff_size,u8 feature_ver)968 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
969 struct ena_admin_get_feat_resp *get_resp,
970 enum ena_admin_aq_feature_id feature_id,
971 dma_addr_t control_buf_dma_addr,
972 u32 control_buff_size,
973 u8 feature_ver)
974 {
975 struct ena_com_admin_queue *admin_queue;
976 struct ena_admin_get_feat_cmd get_cmd;
977 int ret;
978
979 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
980 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", feature_id);
981 return -EOPNOTSUPP;
982 }
983
984 memset(&get_cmd, 0x0, sizeof(get_cmd));
985 admin_queue = &ena_dev->admin_queue;
986
987 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
988
989 if (control_buff_size)
990 get_cmd.aq_common_descriptor.flags =
991 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
992 else
993 get_cmd.aq_common_descriptor.flags = 0;
994
995 ret = ena_com_mem_addr_set(ena_dev,
996 &get_cmd.control_buffer.address,
997 control_buf_dma_addr);
998 if (unlikely(ret)) {
999 netdev_err(ena_dev->net_device, "Memory address set failed\n");
1000 return ret;
1001 }
1002
1003 get_cmd.control_buffer.length = control_buff_size;
1004 get_cmd.feat_common.feature_version = feature_ver;
1005 get_cmd.feat_common.feature_id = feature_id;
1006
1007 ret = ena_com_execute_admin_command(admin_queue,
1008 (struct ena_admin_aq_entry *)
1009 &get_cmd,
1010 sizeof(get_cmd),
1011 (struct ena_admin_acq_entry *)
1012 get_resp,
1013 sizeof(*get_resp));
1014
1015 if (unlikely(ret))
1016 netdev_err(ena_dev->net_device,
1017 "Failed to submit get_feature command %d error: %d\n", feature_id, ret);
1018
1019 return ret;
1020 }
1021
ena_com_get_feature(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * get_resp,enum ena_admin_aq_feature_id feature_id,u8 feature_ver)1022 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
1023 struct ena_admin_get_feat_resp *get_resp,
1024 enum ena_admin_aq_feature_id feature_id,
1025 u8 feature_ver)
1026 {
1027 return ena_com_get_feature_ex(ena_dev,
1028 get_resp,
1029 feature_id,
1030 0,
1031 0,
1032 feature_ver);
1033 }
1034
ena_com_get_current_hash_function(struct ena_com_dev * ena_dev)1035 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev)
1036 {
1037 return ena_dev->rss.hash_func;
1038 }
1039
ena_com_hash_key_fill_default_key(struct ena_com_dev * ena_dev)1040 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev)
1041 {
1042 struct ena_admin_feature_rss_flow_hash_control *hash_key =
1043 (ena_dev->rss).hash_key;
1044
1045 netdev_rss_key_fill(&hash_key->key, sizeof(hash_key->key));
1046 /* The key buffer is stored in the device in an array of
1047 * uint32 elements.
1048 */
1049 hash_key->key_parts = ENA_ADMIN_RSS_KEY_PARTS;
1050 }
1051
ena_com_hash_key_allocate(struct ena_com_dev * ena_dev)1052 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
1053 {
1054 struct ena_rss *rss = &ena_dev->rss;
1055
1056 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_FUNCTION))
1057 return -EOPNOTSUPP;
1058
1059 rss->hash_key = dma_alloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_key),
1060 &rss->hash_key_dma_addr, GFP_KERNEL);
1061
1062 if (unlikely(!rss->hash_key))
1063 return -ENOMEM;
1064
1065 return 0;
1066 }
1067
ena_com_hash_key_destroy(struct ena_com_dev * ena_dev)1068 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
1069 {
1070 struct ena_rss *rss = &ena_dev->rss;
1071
1072 if (rss->hash_key)
1073 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), rss->hash_key,
1074 rss->hash_key_dma_addr);
1075 rss->hash_key = NULL;
1076 }
1077
ena_com_hash_ctrl_init(struct ena_com_dev * ena_dev)1078 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
1079 {
1080 struct ena_rss *rss = &ena_dev->rss;
1081
1082 rss->hash_ctrl = dma_alloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl),
1083 &rss->hash_ctrl_dma_addr, GFP_KERNEL);
1084
1085 if (unlikely(!rss->hash_ctrl))
1086 return -ENOMEM;
1087
1088 return 0;
1089 }
1090
ena_com_hash_ctrl_destroy(struct ena_com_dev * ena_dev)1091 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
1092 {
1093 struct ena_rss *rss = &ena_dev->rss;
1094
1095 if (rss->hash_ctrl)
1096 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), rss->hash_ctrl,
1097 rss->hash_ctrl_dma_addr);
1098 rss->hash_ctrl = NULL;
1099 }
1100
ena_com_indirect_table_allocate(struct ena_com_dev * ena_dev,u16 log_size)1101 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
1102 u16 log_size)
1103 {
1104 struct ena_rss *rss = &ena_dev->rss;
1105 struct ena_admin_get_feat_resp get_resp;
1106 size_t tbl_size;
1107 int ret;
1108
1109 ret = ena_com_get_feature(ena_dev, &get_resp,
1110 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG, 0);
1111 if (unlikely(ret))
1112 return ret;
1113
1114 if ((get_resp.u.ind_table.min_size > log_size) ||
1115 (get_resp.u.ind_table.max_size < log_size)) {
1116 netdev_err(ena_dev->net_device,
1117 "Indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
1118 1 << log_size, 1 << get_resp.u.ind_table.min_size,
1119 1 << get_resp.u.ind_table.max_size);
1120 return -EINVAL;
1121 }
1122
1123 tbl_size = (1ULL << log_size) *
1124 sizeof(struct ena_admin_rss_ind_table_entry);
1125
1126 rss->rss_ind_tbl = dma_alloc_coherent(ena_dev->dmadev, tbl_size, &rss->rss_ind_tbl_dma_addr,
1127 GFP_KERNEL);
1128 if (unlikely(!rss->rss_ind_tbl))
1129 goto mem_err1;
1130
1131 tbl_size = (1ULL << log_size) * sizeof(u16);
1132 rss->host_rss_ind_tbl = devm_kzalloc(ena_dev->dmadev, tbl_size, GFP_KERNEL);
1133 if (unlikely(!rss->host_rss_ind_tbl))
1134 goto mem_err2;
1135
1136 rss->tbl_log_size = log_size;
1137
1138 return 0;
1139
1140 mem_err2:
1141 tbl_size = (1ULL << log_size) *
1142 sizeof(struct ena_admin_rss_ind_table_entry);
1143
1144 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, rss->rss_ind_tbl_dma_addr);
1145 rss->rss_ind_tbl = NULL;
1146 mem_err1:
1147 rss->tbl_log_size = 0;
1148 return -ENOMEM;
1149 }
1150
ena_com_indirect_table_destroy(struct ena_com_dev * ena_dev)1151 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
1152 {
1153 struct ena_rss *rss = &ena_dev->rss;
1154 size_t tbl_size = (1ULL << rss->tbl_log_size) *
1155 sizeof(struct ena_admin_rss_ind_table_entry);
1156
1157 if (rss->rss_ind_tbl)
1158 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl,
1159 rss->rss_ind_tbl_dma_addr);
1160 rss->rss_ind_tbl = NULL;
1161
1162 if (rss->host_rss_ind_tbl)
1163 devm_kfree(ena_dev->dmadev, rss->host_rss_ind_tbl);
1164 rss->host_rss_ind_tbl = NULL;
1165 }
1166
ena_com_create_io_sq(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq,u16 cq_idx)1167 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1168 struct ena_com_io_sq *io_sq, u16 cq_idx)
1169 {
1170 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1171 struct ena_admin_aq_create_sq_cmd create_cmd;
1172 struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1173 u8 direction;
1174 int ret;
1175
1176 memset(&create_cmd, 0x0, sizeof(create_cmd));
1177
1178 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1179
1180 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1181 direction = ENA_ADMIN_SQ_DIRECTION_TX;
1182 else
1183 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1184
1185 create_cmd.sq_identity |= (direction <<
1186 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1187 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1188
1189 create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1190 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1191
1192 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1193 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1194 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1195
1196 create_cmd.sq_caps_3 |=
1197 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1198
1199 create_cmd.cq_idx = cq_idx;
1200 create_cmd.sq_depth = io_sq->q_depth;
1201
1202 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1203 ret = ena_com_mem_addr_set(ena_dev,
1204 &create_cmd.sq_ba,
1205 io_sq->desc_addr.phys_addr);
1206 if (unlikely(ret)) {
1207 netdev_err(ena_dev->net_device, "Memory address set failed\n");
1208 return ret;
1209 }
1210 }
1211
1212 ret = ena_com_execute_admin_command(admin_queue,
1213 (struct ena_admin_aq_entry *)&create_cmd,
1214 sizeof(create_cmd),
1215 (struct ena_admin_acq_entry *)&cmd_completion,
1216 sizeof(cmd_completion));
1217 if (unlikely(ret)) {
1218 netdev_err(ena_dev->net_device, "Failed to create IO SQ. error: %d\n", ret);
1219 return ret;
1220 }
1221
1222 io_sq->idx = cmd_completion.sq_idx;
1223
1224 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1225 (uintptr_t)cmd_completion.sq_doorbell_offset);
1226
1227 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1228 io_sq->desc_addr.pbuf_dev_addr =
1229 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1230 cmd_completion.llq_descriptors_offset);
1231 }
1232
1233 netdev_dbg(ena_dev->net_device, "Created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1234
1235 return ret;
1236 }
1237
ena_com_ind_tbl_convert_to_device(struct ena_com_dev * ena_dev)1238 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1239 {
1240 struct ena_rss *rss = &ena_dev->rss;
1241 struct ena_com_io_sq *io_sq;
1242 u16 qid;
1243 int i;
1244
1245 for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1246 qid = rss->host_rss_ind_tbl[i];
1247 if (qid >= ENA_TOTAL_NUM_QUEUES)
1248 return -EINVAL;
1249
1250 io_sq = &ena_dev->io_sq_queues[qid];
1251
1252 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1253 return -EINVAL;
1254
1255 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1256 }
1257
1258 return 0;
1259 }
1260
ena_com_update_intr_delay_resolution(struct ena_com_dev * ena_dev,u16 intr_delay_resolution)1261 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1262 u16 intr_delay_resolution)
1263 {
1264 u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution;
1265
1266 if (unlikely(!intr_delay_resolution)) {
1267 netdev_err(ena_dev->net_device,
1268 "Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1269 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;
1270 }
1271
1272 /* update Rx */
1273 ena_dev->intr_moder_rx_interval =
1274 ena_dev->intr_moder_rx_interval *
1275 prev_intr_delay_resolution /
1276 intr_delay_resolution;
1277
1278 /* update Tx */
1279 ena_dev->intr_moder_tx_interval =
1280 ena_dev->intr_moder_tx_interval *
1281 prev_intr_delay_resolution /
1282 intr_delay_resolution;
1283
1284 ena_dev->intr_delay_resolution = intr_delay_resolution;
1285 }
1286
1287 /*****************************************************************************/
1288 /******************************* API ******************************/
1289 /*****************************************************************************/
1290
ena_com_execute_admin_command(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size,struct ena_admin_acq_entry * comp,size_t comp_size)1291 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1292 struct ena_admin_aq_entry *cmd,
1293 size_t cmd_size,
1294 struct ena_admin_acq_entry *comp,
1295 size_t comp_size)
1296 {
1297 struct ena_comp_ctx *comp_ctx;
1298 int ret;
1299
1300 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1301 comp, comp_size);
1302 if (IS_ERR(comp_ctx)) {
1303 ret = PTR_ERR(comp_ctx);
1304 if (ret == -ENODEV)
1305 netdev_dbg(admin_queue->ena_dev->net_device,
1306 "Failed to submit command [%d]\n", ret);
1307 else
1308 netdev_err(admin_queue->ena_dev->net_device,
1309 "Failed to submit command [%d]\n", ret);
1310
1311 return ret;
1312 }
1313
1314 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1315 if (unlikely(ret)) {
1316 if (admin_queue->running_state)
1317 netdev_err(admin_queue->ena_dev->net_device,
1318 "Failed to process command. ret = %d\n", ret);
1319 else
1320 netdev_dbg(admin_queue->ena_dev->net_device,
1321 "Failed to process command. ret = %d\n", ret);
1322 }
1323 return ret;
1324 }
1325
ena_com_create_io_cq(struct ena_com_dev * ena_dev,struct ena_com_io_cq * io_cq)1326 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1327 struct ena_com_io_cq *io_cq)
1328 {
1329 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1330 struct ena_admin_aq_create_cq_cmd create_cmd;
1331 struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1332 int ret;
1333
1334 memset(&create_cmd, 0x0, sizeof(create_cmd));
1335
1336 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1337
1338 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1339 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1340 create_cmd.cq_caps_1 |=
1341 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1342
1343 create_cmd.msix_vector = io_cq->msix_vector;
1344 create_cmd.cq_depth = io_cq->q_depth;
1345
1346 ret = ena_com_mem_addr_set(ena_dev,
1347 &create_cmd.cq_ba,
1348 io_cq->cdesc_addr.phys_addr);
1349 if (unlikely(ret)) {
1350 netdev_err(ena_dev->net_device, "Memory address set failed\n");
1351 return ret;
1352 }
1353
1354 ret = ena_com_execute_admin_command(admin_queue,
1355 (struct ena_admin_aq_entry *)&create_cmd,
1356 sizeof(create_cmd),
1357 (struct ena_admin_acq_entry *)&cmd_completion,
1358 sizeof(cmd_completion));
1359 if (unlikely(ret)) {
1360 netdev_err(ena_dev->net_device, "Failed to create IO CQ. error: %d\n", ret);
1361 return ret;
1362 }
1363
1364 io_cq->idx = cmd_completion.cq_idx;
1365
1366 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1367 cmd_completion.cq_interrupt_unmask_register_offset);
1368
1369 if (cmd_completion.numa_node_register_offset)
1370 io_cq->numa_node_cfg_reg =
1371 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1372 cmd_completion.numa_node_register_offset);
1373
1374 netdev_dbg(ena_dev->net_device, "Created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1375
1376 return ret;
1377 }
1378
ena_com_get_io_handlers(struct ena_com_dev * ena_dev,u16 qid,struct ena_com_io_sq ** io_sq,struct ena_com_io_cq ** io_cq)1379 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1380 struct ena_com_io_sq **io_sq,
1381 struct ena_com_io_cq **io_cq)
1382 {
1383 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1384 netdev_err(ena_dev->net_device, "Invalid queue number %d but the max is %d\n", qid,
1385 ENA_TOTAL_NUM_QUEUES);
1386 return -EINVAL;
1387 }
1388
1389 *io_sq = &ena_dev->io_sq_queues[qid];
1390 *io_cq = &ena_dev->io_cq_queues[qid];
1391
1392 return 0;
1393 }
1394
ena_com_abort_admin_commands(struct ena_com_dev * ena_dev)1395 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1396 {
1397 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1398 struct ena_comp_ctx *comp_ctx;
1399 u16 i;
1400
1401 if (!admin_queue->comp_ctx)
1402 return;
1403
1404 for (i = 0; i < admin_queue->q_depth; i++) {
1405 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1406 if (unlikely(!comp_ctx))
1407 break;
1408
1409 comp_ctx->status = ENA_CMD_ABORTED;
1410
1411 complete(&comp_ctx->wait_event);
1412 }
1413 }
1414
ena_com_wait_for_abort_completion(struct ena_com_dev * ena_dev)1415 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1416 {
1417 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1418 unsigned long flags = 0;
1419 u32 exp = 0;
1420
1421 spin_lock_irqsave(&admin_queue->q_lock, flags);
1422 while (atomic_read(&admin_queue->outstanding_cmds) != 0) {
1423 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1424 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
1425 spin_lock_irqsave(&admin_queue->q_lock, flags);
1426 }
1427 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1428 }
1429
ena_com_destroy_io_cq(struct ena_com_dev * ena_dev,struct ena_com_io_cq * io_cq)1430 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1431 struct ena_com_io_cq *io_cq)
1432 {
1433 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1434 struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1435 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1436 int ret;
1437
1438 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1439
1440 destroy_cmd.cq_idx = io_cq->idx;
1441 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1442
1443 ret = ena_com_execute_admin_command(admin_queue,
1444 (struct ena_admin_aq_entry *)&destroy_cmd,
1445 sizeof(destroy_cmd),
1446 (struct ena_admin_acq_entry *)&destroy_resp,
1447 sizeof(destroy_resp));
1448
1449 if (unlikely(ret && (ret != -ENODEV)))
1450 netdev_err(ena_dev->net_device, "Failed to destroy IO CQ. error: %d\n", ret);
1451
1452 return ret;
1453 }
1454
ena_com_get_admin_running_state(struct ena_com_dev * ena_dev)1455 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1456 {
1457 return ena_dev->admin_queue.running_state;
1458 }
1459
ena_com_set_admin_running_state(struct ena_com_dev * ena_dev,bool state)1460 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1461 {
1462 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1463 unsigned long flags = 0;
1464
1465 spin_lock_irqsave(&admin_queue->q_lock, flags);
1466 ena_dev->admin_queue.running_state = state;
1467 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1468 }
1469
ena_com_admin_aenq_enable(struct ena_com_dev * ena_dev)1470 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1471 {
1472 u16 depth = ena_dev->aenq.q_depth;
1473
1474 WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1475
1476 /* Init head_db to mark that all entries in the queue
1477 * are initially available
1478 */
1479 writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1480 }
1481
ena_com_set_aenq_config(struct ena_com_dev * ena_dev,u32 groups_flag)1482 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1483 {
1484 struct ena_com_admin_queue *admin_queue;
1485 struct ena_admin_set_feat_cmd cmd;
1486 struct ena_admin_set_feat_resp resp;
1487 struct ena_admin_get_feat_resp get_resp;
1488 int ret;
1489
1490 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0);
1491 if (ret) {
1492 dev_info(ena_dev->dmadev, "Can't get aenq configuration\n");
1493 return ret;
1494 }
1495
1496 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1497 netdev_warn(ena_dev->net_device,
1498 "Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n",
1499 get_resp.u.aenq.supported_groups, groups_flag);
1500 return -EOPNOTSUPP;
1501 }
1502
1503 memset(&cmd, 0x0, sizeof(cmd));
1504 admin_queue = &ena_dev->admin_queue;
1505
1506 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1507 cmd.aq_common_descriptor.flags = 0;
1508 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1509 cmd.u.aenq.enabled_groups = groups_flag;
1510
1511 ret = ena_com_execute_admin_command(admin_queue,
1512 (struct ena_admin_aq_entry *)&cmd,
1513 sizeof(cmd),
1514 (struct ena_admin_acq_entry *)&resp,
1515 sizeof(resp));
1516
1517 if (unlikely(ret))
1518 netdev_err(ena_dev->net_device, "Failed to config AENQ ret: %d\n", ret);
1519
1520 return ret;
1521 }
1522
ena_com_get_dma_width(struct ena_com_dev * ena_dev)1523 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1524 {
1525 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1526 u32 width;
1527
1528 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1529 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n");
1530 return -ETIME;
1531 }
1532
1533 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1534 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1535
1536 netdev_dbg(ena_dev->net_device, "ENA dma width: %d\n", width);
1537
1538 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1539 netdev_err(ena_dev->net_device, "DMA width illegal value: %d\n", width);
1540 return -EINVAL;
1541 }
1542
1543 ena_dev->dma_addr_bits = width;
1544
1545 return width;
1546 }
1547
ena_com_validate_version(struct ena_com_dev * ena_dev)1548 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1549 {
1550 u32 ver;
1551 u32 ctrl_ver;
1552 u32 ctrl_ver_masked;
1553
1554 /* Make sure the ENA version and the controller version are at least
1555 * as the driver expects
1556 */
1557 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1558 ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1559 ENA_REGS_CONTROLLER_VERSION_OFF);
1560
1561 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) || (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1562 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n");
1563 return -ETIME;
1564 }
1565
1566 dev_info(ena_dev->dmadev, "ENA device version: %d.%d\n",
1567 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >> ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1568 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1569
1570 dev_info(ena_dev->dmadev, "ENA controller version: %d.%d.%d implementation version %d\n",
1571 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >>
1572 ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1573 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >>
1574 ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1575 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1576 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1577 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1578
1579 ctrl_ver_masked =
1580 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1581 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1582 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1583
1584 /* Validate the ctrl version without the implementation ID */
1585 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1586 netdev_err(ena_dev->net_device,
1587 "ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1588 return -1;
1589 }
1590
1591 return 0;
1592 }
1593
1594 static void
ena_com_free_ena_admin_queue_comp_ctx(struct ena_com_dev * ena_dev,struct ena_com_admin_queue * admin_queue)1595 ena_com_free_ena_admin_queue_comp_ctx(struct ena_com_dev *ena_dev,
1596 struct ena_com_admin_queue *admin_queue)
1597
1598 {
1599 if (!admin_queue->comp_ctx)
1600 return;
1601
1602 devm_kfree(ena_dev->dmadev, admin_queue->comp_ctx);
1603
1604 admin_queue->comp_ctx = NULL;
1605 }
1606
ena_com_admin_destroy(struct ena_com_dev * ena_dev)1607 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1608 {
1609 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1610 struct ena_com_admin_cq *cq = &admin_queue->cq;
1611 struct ena_com_admin_sq *sq = &admin_queue->sq;
1612 struct ena_com_aenq *aenq = &ena_dev->aenq;
1613 u16 size;
1614
1615 ena_com_free_ena_admin_queue_comp_ctx(ena_dev, admin_queue);
1616
1617 size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1618 if (sq->entries)
1619 dma_free_coherent(ena_dev->dmadev, size, sq->entries, sq->dma_addr);
1620 sq->entries = NULL;
1621
1622 size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1623 if (cq->entries)
1624 dma_free_coherent(ena_dev->dmadev, size, cq->entries, cq->dma_addr);
1625 cq->entries = NULL;
1626
1627 size = ADMIN_AENQ_SIZE(aenq->q_depth);
1628 if (ena_dev->aenq.entries)
1629 dma_free_coherent(ena_dev->dmadev, size, aenq->entries, aenq->dma_addr);
1630 aenq->entries = NULL;
1631 }
1632
ena_com_set_admin_polling_mode(struct ena_com_dev * ena_dev,bool polling)1633 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1634 {
1635 u32 mask_value = 0;
1636
1637 if (polling)
1638 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1639
1640 writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1641 ena_dev->admin_queue.polling = polling;
1642 }
1643
ena_com_mmio_reg_read_request_init(struct ena_com_dev * ena_dev)1644 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1645 {
1646 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1647
1648 spin_lock_init(&mmio_read->lock);
1649 mmio_read->read_resp = dma_alloc_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp),
1650 &mmio_read->read_resp_dma_addr, GFP_KERNEL);
1651 if (unlikely(!mmio_read->read_resp))
1652 goto err;
1653
1654 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1655
1656 mmio_read->read_resp->req_id = 0x0;
1657 mmio_read->seq_num = 0x0;
1658 mmio_read->readless_supported = true;
1659
1660 return 0;
1661
1662 err:
1663
1664 return -ENOMEM;
1665 }
1666
ena_com_set_mmio_read_mode(struct ena_com_dev * ena_dev,bool readless_supported)1667 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1668 {
1669 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1670
1671 mmio_read->readless_supported = readless_supported;
1672 }
1673
ena_com_mmio_reg_read_request_destroy(struct ena_com_dev * ena_dev)1674 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1675 {
1676 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1677
1678 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1679 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1680
1681 dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp), mmio_read->read_resp,
1682 mmio_read->read_resp_dma_addr);
1683
1684 mmio_read->read_resp = NULL;
1685 }
1686
ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev * ena_dev)1687 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1688 {
1689 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1690 u32 addr_low, addr_high;
1691
1692 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1693 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1694
1695 writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1696 writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1697 }
1698
ena_com_admin_init(struct ena_com_dev * ena_dev,struct ena_aenq_handlers * aenq_handlers)1699 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1700 struct ena_aenq_handlers *aenq_handlers)
1701 {
1702 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1703 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1704 int ret;
1705
1706 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1707
1708 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1709 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n");
1710 return -ETIME;
1711 }
1712
1713 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1714 netdev_err(ena_dev->net_device, "Device isn't ready, abort com init\n");
1715 return -ENODEV;
1716 }
1717
1718 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1719
1720 admin_queue->q_dmadev = ena_dev->dmadev;
1721 admin_queue->polling = false;
1722 admin_queue->curr_cmd_id = 0;
1723
1724 atomic_set(&admin_queue->outstanding_cmds, 0);
1725
1726 spin_lock_init(&admin_queue->q_lock);
1727
1728 ret = ena_com_init_comp_ctxt(admin_queue);
1729 if (ret)
1730 goto error;
1731
1732 ret = ena_com_admin_init_sq(admin_queue);
1733 if (ret)
1734 goto error;
1735
1736 ret = ena_com_admin_init_cq(admin_queue);
1737 if (ret)
1738 goto error;
1739
1740 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1741 ENA_REGS_AQ_DB_OFF);
1742
1743 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1744 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1745
1746 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1747 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1748
1749 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1750 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1751
1752 writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1753 writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1754
1755 aq_caps = 0;
1756 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1757 aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1758 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1759 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1760
1761 acq_caps = 0;
1762 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1763 acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1764 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1765 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1766
1767 writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1768 writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1769 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1770 if (ret)
1771 goto error;
1772
1773 admin_queue->ena_dev = ena_dev;
1774 admin_queue->running_state = true;
1775
1776 return 0;
1777 error:
1778 ena_com_admin_destroy(ena_dev);
1779
1780 return ret;
1781 }
1782
ena_com_create_io_queue(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx)1783 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1784 struct ena_com_create_io_ctx *ctx)
1785 {
1786 struct ena_com_io_sq *io_sq;
1787 struct ena_com_io_cq *io_cq;
1788 int ret;
1789
1790 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1791 netdev_err(ena_dev->net_device, "Qid (%d) is bigger than max num of queues (%d)\n",
1792 ctx->qid, ENA_TOTAL_NUM_QUEUES);
1793 return -EINVAL;
1794 }
1795
1796 io_sq = &ena_dev->io_sq_queues[ctx->qid];
1797 io_cq = &ena_dev->io_cq_queues[ctx->qid];
1798
1799 memset(io_sq, 0x0, sizeof(*io_sq));
1800 memset(io_cq, 0x0, sizeof(*io_cq));
1801
1802 /* Init CQ */
1803 io_cq->q_depth = ctx->queue_size;
1804 io_cq->direction = ctx->direction;
1805 io_cq->qid = ctx->qid;
1806
1807 io_cq->msix_vector = ctx->msix_vector;
1808
1809 io_sq->q_depth = ctx->queue_size;
1810 io_sq->direction = ctx->direction;
1811 io_sq->qid = ctx->qid;
1812
1813 io_sq->mem_queue_type = ctx->mem_queue_type;
1814
1815 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1816 /* header length is limited to 8 bits */
1817 io_sq->tx_max_header_size = min_t(u32, ena_dev->tx_max_header_size, SZ_256);
1818
1819 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1820 if (ret)
1821 goto error;
1822 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1823 if (ret)
1824 goto error;
1825
1826 ret = ena_com_create_io_cq(ena_dev, io_cq);
1827 if (ret)
1828 goto error;
1829
1830 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1831 if (ret)
1832 goto destroy_io_cq;
1833
1834 return 0;
1835
1836 destroy_io_cq:
1837 ena_com_destroy_io_cq(ena_dev, io_cq);
1838 error:
1839 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1840 return ret;
1841 }
1842
ena_com_destroy_io_queue(struct ena_com_dev * ena_dev,u16 qid)1843 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1844 {
1845 struct ena_com_io_sq *io_sq;
1846 struct ena_com_io_cq *io_cq;
1847
1848 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1849 netdev_err(ena_dev->net_device, "Qid (%d) is bigger than max num of queues (%d)\n",
1850 qid, ENA_TOTAL_NUM_QUEUES);
1851 return;
1852 }
1853
1854 io_sq = &ena_dev->io_sq_queues[qid];
1855 io_cq = &ena_dev->io_cq_queues[qid];
1856
1857 ena_com_destroy_io_sq(ena_dev, io_sq);
1858 ena_com_destroy_io_cq(ena_dev, io_cq);
1859
1860 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1861 }
1862
ena_com_get_link_params(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * resp)1863 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1864 struct ena_admin_get_feat_resp *resp)
1865 {
1866 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0);
1867 }
1868
ena_get_dev_stats(struct ena_com_dev * ena_dev,struct ena_com_stats_ctx * ctx,enum ena_admin_get_stats_type type)1869 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
1870 struct ena_com_stats_ctx *ctx,
1871 enum ena_admin_get_stats_type type)
1872 {
1873 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
1874 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
1875 struct ena_com_admin_queue *admin_queue;
1876 int ret;
1877
1878 admin_queue = &ena_dev->admin_queue;
1879
1880 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
1881 get_cmd->aq_common_descriptor.flags = 0;
1882 get_cmd->type = type;
1883
1884 ret = ena_com_execute_admin_command(admin_queue,
1885 (struct ena_admin_aq_entry *)get_cmd,
1886 sizeof(*get_cmd),
1887 (struct ena_admin_acq_entry *)get_resp,
1888 sizeof(*get_resp));
1889
1890 if (unlikely(ret))
1891 netdev_err(ena_dev->net_device, "Failed to get stats. error: %d\n", ret);
1892
1893 return ret;
1894 }
1895
ena_com_set_supported_customer_metrics(struct ena_com_dev * ena_dev)1896 static void ena_com_set_supported_customer_metrics(struct ena_com_dev *ena_dev)
1897 {
1898 struct ena_customer_metrics *customer_metrics;
1899 struct ena_com_stats_ctx ctx;
1900 int ret;
1901
1902 customer_metrics = &ena_dev->customer_metrics;
1903 if (!ena_com_get_cap(ena_dev, ENA_ADMIN_CUSTOMER_METRICS)) {
1904 customer_metrics->supported_metrics = ENA_ADMIN_CUSTOMER_METRICS_MIN_SUPPORT_MASK;
1905 return;
1906 }
1907
1908 memset(&ctx, 0x0, sizeof(ctx));
1909 ctx.get_cmd.requested_metrics = ENA_ADMIN_CUSTOMER_METRICS_SUPPORT_MASK;
1910 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_CUSTOMER_METRICS);
1911 if (likely(ret == 0))
1912 customer_metrics->supported_metrics =
1913 ctx.get_resp.u.customer_metrics.reported_metrics;
1914 else
1915 netdev_err(ena_dev->net_device,
1916 "Failed to query customer metrics support. error: %d\n", ret);
1917 }
1918
ena_com_get_dev_attr_feat(struct ena_com_dev * ena_dev,struct ena_com_dev_get_features_ctx * get_feat_ctx)1919 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1920 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1921 {
1922 struct ena_admin_get_feat_resp get_resp;
1923 int rc;
1924
1925 rc = ena_com_get_feature(ena_dev, &get_resp,
1926 ENA_ADMIN_DEVICE_ATTRIBUTES, 0);
1927 if (rc)
1928 return rc;
1929
1930 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1931 sizeof(get_resp.u.dev_attr));
1932
1933 ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1934 ena_dev->capabilities = get_resp.u.dev_attr.capabilities;
1935
1936 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1937 rc = ena_com_get_feature(ena_dev, &get_resp,
1938 ENA_ADMIN_MAX_QUEUES_EXT,
1939 ENA_FEATURE_MAX_QUEUE_EXT_VER);
1940 if (rc)
1941 return rc;
1942
1943 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER)
1944 return -EINVAL;
1945
1946 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext,
1947 sizeof(get_resp.u.max_queue_ext));
1948 ena_dev->tx_max_header_size =
1949 get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size;
1950 } else {
1951 rc = ena_com_get_feature(ena_dev, &get_resp,
1952 ENA_ADMIN_MAX_QUEUES_NUM, 0);
1953 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1954 sizeof(get_resp.u.max_queue));
1955 ena_dev->tx_max_header_size =
1956 get_resp.u.max_queue.max_header_size;
1957
1958 if (rc)
1959 return rc;
1960 }
1961
1962 rc = ena_com_get_feature(ena_dev, &get_resp,
1963 ENA_ADMIN_AENQ_CONFIG, 0);
1964 if (rc)
1965 return rc;
1966
1967 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1968 sizeof(get_resp.u.aenq));
1969
1970 rc = ena_com_get_feature(ena_dev, &get_resp,
1971 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
1972 if (rc)
1973 return rc;
1974
1975 memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
1976 sizeof(get_resp.u.offload));
1977
1978 /* Driver hints isn't mandatory admin command. So in case the
1979 * command isn't supported set driver hints to 0
1980 */
1981 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0);
1982
1983 if (!rc)
1984 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints, sizeof(get_resp.u.hw_hints));
1985 else if (rc == -EOPNOTSUPP)
1986 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints));
1987 else
1988 return rc;
1989
1990 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0);
1991 if (!rc)
1992 memcpy(&get_feat_ctx->llq, &get_resp.u.llq, sizeof(get_resp.u.llq));
1993 else if (rc == -EOPNOTSUPP)
1994 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
1995 else
1996 return rc;
1997
1998 ena_com_set_supported_customer_metrics(ena_dev);
1999
2000 return 0;
2001 }
2002
ena_com_admin_q_comp_intr_handler(struct ena_com_dev * ena_dev)2003 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
2004 {
2005 ena_com_handle_admin_completion(&ena_dev->admin_queue);
2006 }
2007
2008 /* ena_handle_specific_aenq_event:
2009 * return the handler that is relevant to the specific event group
2010 */
ena_com_get_specific_aenq_cb(struct ena_com_dev * ena_dev,u16 group)2011 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *ena_dev,
2012 u16 group)
2013 {
2014 struct ena_aenq_handlers *aenq_handlers = ena_dev->aenq.aenq_handlers;
2015
2016 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
2017 return aenq_handlers->handlers[group];
2018
2019 return aenq_handlers->unimplemented_handler;
2020 }
2021
2022 /* ena_aenq_intr_handler:
2023 * handles the aenq incoming events.
2024 * pop events from the queue and apply the specific handler
2025 */
ena_com_aenq_intr_handler(struct ena_com_dev * ena_dev,void * data)2026 void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data)
2027 {
2028 struct ena_admin_aenq_entry *aenq_e;
2029 struct ena_admin_aenq_common_desc *aenq_common;
2030 struct ena_com_aenq *aenq = &ena_dev->aenq;
2031 u64 timestamp;
2032 ena_aenq_handler handler_cb;
2033 u16 masked_head, processed = 0;
2034 u8 phase;
2035
2036 masked_head = aenq->head & (aenq->q_depth - 1);
2037 phase = aenq->phase;
2038 aenq_e = &aenq->entries[masked_head]; /* Get first entry */
2039 aenq_common = &aenq_e->aenq_common_desc;
2040
2041 /* Go over all the events */
2042 while ((READ_ONCE(aenq_common->flags) & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
2043 /* Make sure the phase bit (ownership) is as expected before
2044 * reading the rest of the descriptor.
2045 */
2046 dma_rmb();
2047
2048 timestamp = (u64)aenq_common->timestamp_low |
2049 ((u64)aenq_common->timestamp_high << 32);
2050
2051 netdev_dbg(ena_dev->net_device, "AENQ! Group[%x] Syndrome[%x] timestamp: [%llus]\n",
2052 aenq_common->group, aenq_common->syndrome, timestamp);
2053
2054 /* Handle specific event*/
2055 handler_cb = ena_com_get_specific_aenq_cb(ena_dev,
2056 aenq_common->group);
2057 handler_cb(data, aenq_e); /* call the actual event handler*/
2058
2059 /* Get next event entry */
2060 masked_head++;
2061 processed++;
2062
2063 if (unlikely(masked_head == aenq->q_depth)) {
2064 masked_head = 0;
2065 phase = !phase;
2066 }
2067 aenq_e = &aenq->entries[masked_head];
2068 aenq_common = &aenq_e->aenq_common_desc;
2069 }
2070
2071 aenq->head += processed;
2072 aenq->phase = phase;
2073
2074 /* Don't update aenq doorbell if there weren't any processed events */
2075 if (!processed)
2076 return;
2077
2078 /* write the aenq doorbell after all AENQ descriptors were read */
2079 mb();
2080 writel_relaxed((u32)aenq->head, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
2081 }
2082
ena_com_dev_reset(struct ena_com_dev * ena_dev,enum ena_regs_reset_reason_types reset_reason)2083 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
2084 enum ena_regs_reset_reason_types reset_reason)
2085 {
2086 u32 stat, timeout, cap, reset_val;
2087 int rc;
2088
2089 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
2090 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
2091
2092 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) || (cap == ENA_MMIO_READ_TIMEOUT))) {
2093 netdev_err(ena_dev->net_device, "Reg read32 timeout occurred\n");
2094 return -ETIME;
2095 }
2096
2097 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
2098 netdev_err(ena_dev->net_device, "Device isn't ready, can't reset device\n");
2099 return -EINVAL;
2100 }
2101
2102 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
2103 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
2104 if (timeout == 0) {
2105 netdev_err(ena_dev->net_device, "Invalid timeout value\n");
2106 return -EINVAL;
2107 }
2108
2109 /* start reset */
2110 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
2111 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
2112 ENA_REGS_DEV_CTL_RESET_REASON_MASK;
2113 writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2114
2115 /* Write again the MMIO read request address */
2116 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
2117
2118 rc = wait_for_reset_state(ena_dev, timeout,
2119 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
2120 if (rc != 0) {
2121 netdev_err(ena_dev->net_device, "Reset indication didn't turn on\n");
2122 return rc;
2123 }
2124
2125 /* reset done */
2126 writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2127 rc = wait_for_reset_state(ena_dev, timeout, 0);
2128 if (rc != 0) {
2129 netdev_err(ena_dev->net_device, "Reset indication didn't turn off\n");
2130 return rc;
2131 }
2132
2133 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
2134 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
2135 if (timeout)
2136 /* the resolution of timeout reg is 100ms */
2137 ena_dev->admin_queue.completion_timeout = timeout * 100000;
2138 else
2139 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2140
2141 return 0;
2142 }
2143
ena_com_get_eni_stats(struct ena_com_dev * ena_dev,struct ena_admin_eni_stats * stats)2144 int ena_com_get_eni_stats(struct ena_com_dev *ena_dev,
2145 struct ena_admin_eni_stats *stats)
2146 {
2147 struct ena_com_stats_ctx ctx;
2148 int ret;
2149
2150 if (!ena_com_get_cap(ena_dev, ENA_ADMIN_ENI_STATS)) {
2151 netdev_err(ena_dev->net_device, "Capability %d isn't supported\n",
2152 ENA_ADMIN_ENI_STATS);
2153 return -EOPNOTSUPP;
2154 }
2155
2156 memset(&ctx, 0x0, sizeof(ctx));
2157 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENI);
2158 if (likely(ret == 0))
2159 memcpy(stats, &ctx.get_resp.u.eni_stats,
2160 sizeof(ctx.get_resp.u.eni_stats));
2161
2162 return ret;
2163 }
2164
ena_com_get_ena_srd_info(struct ena_com_dev * ena_dev,struct ena_admin_ena_srd_info * info)2165 int ena_com_get_ena_srd_info(struct ena_com_dev *ena_dev,
2166 struct ena_admin_ena_srd_info *info)
2167 {
2168 struct ena_com_stats_ctx ctx;
2169 int ret;
2170
2171 if (!ena_com_get_cap(ena_dev, ENA_ADMIN_ENA_SRD_INFO)) {
2172 netdev_err(ena_dev->net_device, "Capability %d isn't supported\n",
2173 ENA_ADMIN_ENA_SRD_INFO);
2174 return -EOPNOTSUPP;
2175 }
2176
2177 memset(&ctx, 0x0, sizeof(ctx));
2178 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENA_SRD);
2179 if (likely(ret == 0))
2180 memcpy(info, &ctx.get_resp.u.ena_srd_info,
2181 sizeof(ctx.get_resp.u.ena_srd_info));
2182
2183 return ret;
2184 }
2185
ena_com_get_customer_metrics(struct ena_com_dev * ena_dev,char * buffer,u32 len)2186 int ena_com_get_customer_metrics(struct ena_com_dev *ena_dev, char *buffer, u32 len)
2187 {
2188 struct ena_admin_aq_get_stats_cmd *get_cmd;
2189 struct ena_com_stats_ctx ctx;
2190 int ret;
2191
2192 if (unlikely(len > ena_dev->customer_metrics.buffer_len)) {
2193 netdev_err(ena_dev->net_device,
2194 "Invalid buffer size %u. The given buffer is too big.\n", len);
2195 return -EINVAL;
2196 }
2197
2198 if (!ena_com_get_cap(ena_dev, ENA_ADMIN_CUSTOMER_METRICS)) {
2199 netdev_err(ena_dev->net_device, "Capability %d not supported.\n",
2200 ENA_ADMIN_CUSTOMER_METRICS);
2201 return -EOPNOTSUPP;
2202 }
2203
2204 if (!ena_dev->customer_metrics.supported_metrics) {
2205 netdev_err(ena_dev->net_device, "No supported customer metrics.\n");
2206 return -EOPNOTSUPP;
2207 }
2208
2209 get_cmd = &ctx.get_cmd;
2210 memset(&ctx, 0x0, sizeof(ctx));
2211 ret = ena_com_mem_addr_set(ena_dev,
2212 &get_cmd->u.control_buffer.address,
2213 ena_dev->customer_metrics.buffer_dma_addr);
2214 if (unlikely(ret)) {
2215 netdev_err(ena_dev->net_device, "Memory address set failed.\n");
2216 return ret;
2217 }
2218
2219 get_cmd->u.control_buffer.length = ena_dev->customer_metrics.buffer_len;
2220 get_cmd->requested_metrics = ena_dev->customer_metrics.supported_metrics;
2221 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_CUSTOMER_METRICS);
2222 if (likely(ret == 0))
2223 memcpy(buffer, ena_dev->customer_metrics.buffer_virt_addr, len);
2224 else
2225 netdev_err(ena_dev->net_device, "Failed to get customer metrics. error: %d\n", ret);
2226
2227 return ret;
2228 }
2229
ena_com_set_dev_mtu(struct ena_com_dev * ena_dev,u32 mtu)2230 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, u32 mtu)
2231 {
2232 struct ena_com_admin_queue *admin_queue;
2233 struct ena_admin_set_feat_cmd cmd;
2234 struct ena_admin_set_feat_resp resp;
2235 int ret;
2236
2237 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2238 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", ENA_ADMIN_MTU);
2239 return -EOPNOTSUPP;
2240 }
2241
2242 memset(&cmd, 0x0, sizeof(cmd));
2243 admin_queue = &ena_dev->admin_queue;
2244
2245 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2246 cmd.aq_common_descriptor.flags = 0;
2247 cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2248 cmd.u.mtu.mtu = mtu;
2249
2250 ret = ena_com_execute_admin_command(admin_queue,
2251 (struct ena_admin_aq_entry *)&cmd,
2252 sizeof(cmd),
2253 (struct ena_admin_acq_entry *)&resp,
2254 sizeof(resp));
2255
2256 if (unlikely(ret))
2257 netdev_err(ena_dev->net_device, "Failed to set mtu %d. error: %d\n", mtu, ret);
2258
2259 return ret;
2260 }
2261
ena_com_set_hash_function(struct ena_com_dev * ena_dev)2262 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2263 {
2264 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2265 struct ena_rss *rss = &ena_dev->rss;
2266 struct ena_admin_set_feat_cmd cmd;
2267 struct ena_admin_set_feat_resp resp;
2268 struct ena_admin_get_feat_resp get_resp;
2269 int ret;
2270
2271 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_FUNCTION)) {
2272 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
2273 ENA_ADMIN_RSS_HASH_FUNCTION);
2274 return -EOPNOTSUPP;
2275 }
2276
2277 /* Validate hash function is supported */
2278 ret = ena_com_get_feature(ena_dev, &get_resp,
2279 ENA_ADMIN_RSS_HASH_FUNCTION, 0);
2280 if (unlikely(ret))
2281 return ret;
2282
2283 if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) {
2284 netdev_err(ena_dev->net_device, "Func hash %d isn't supported by device, abort\n",
2285 rss->hash_func);
2286 return -EOPNOTSUPP;
2287 }
2288
2289 memset(&cmd, 0x0, sizeof(cmd));
2290
2291 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2292 cmd.aq_common_descriptor.flags =
2293 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2294 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2295 cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2296 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2297
2298 ret = ena_com_mem_addr_set(ena_dev,
2299 &cmd.control_buffer.address,
2300 rss->hash_key_dma_addr);
2301 if (unlikely(ret)) {
2302 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2303 return ret;
2304 }
2305
2306 cmd.control_buffer.length = sizeof(*rss->hash_key);
2307
2308 ret = ena_com_execute_admin_command(admin_queue,
2309 (struct ena_admin_aq_entry *)&cmd,
2310 sizeof(cmd),
2311 (struct ena_admin_acq_entry *)&resp,
2312 sizeof(resp));
2313 if (unlikely(ret)) {
2314 netdev_err(ena_dev->net_device, "Failed to set hash function %d. error: %d\n",
2315 rss->hash_func, ret);
2316 return -EINVAL;
2317 }
2318
2319 return 0;
2320 }
2321
ena_com_fill_hash_function(struct ena_com_dev * ena_dev,enum ena_admin_hash_functions func,const u8 * key,u16 key_len,u32 init_val)2322 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2323 enum ena_admin_hash_functions func,
2324 const u8 *key, u16 key_len, u32 init_val)
2325 {
2326 struct ena_admin_feature_rss_flow_hash_control *hash_key;
2327 struct ena_admin_get_feat_resp get_resp;
2328 enum ena_admin_hash_functions old_func;
2329 struct ena_rss *rss = &ena_dev->rss;
2330 int rc;
2331
2332 hash_key = rss->hash_key;
2333
2334 /* Make sure size is a mult of DWs */
2335 if (unlikely(key_len & 0x3))
2336 return -EINVAL;
2337
2338 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2339 ENA_ADMIN_RSS_HASH_FUNCTION,
2340 rss->hash_key_dma_addr,
2341 sizeof(*rss->hash_key), 0);
2342 if (unlikely(rc))
2343 return rc;
2344
2345 if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) {
2346 netdev_err(ena_dev->net_device, "Flow hash function %d isn't supported\n", func);
2347 return -EOPNOTSUPP;
2348 }
2349
2350 if ((func == ENA_ADMIN_TOEPLITZ) && key) {
2351 if (key_len != sizeof(hash_key->key)) {
2352 netdev_err(ena_dev->net_device,
2353 "key len (%u) doesn't equal the supported size (%zu)\n", key_len,
2354 sizeof(hash_key->key));
2355 return -EINVAL;
2356 }
2357 memcpy(hash_key->key, key, key_len);
2358 hash_key->key_parts = key_len / sizeof(hash_key->key[0]);
2359 }
2360
2361 rss->hash_init_val = init_val;
2362 old_func = rss->hash_func;
2363 rss->hash_func = func;
2364 rc = ena_com_set_hash_function(ena_dev);
2365
2366 /* Restore the old function */
2367 if (unlikely(rc))
2368 rss->hash_func = old_func;
2369
2370 return rc;
2371 }
2372
ena_com_get_hash_function(struct ena_com_dev * ena_dev,enum ena_admin_hash_functions * func)2373 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2374 enum ena_admin_hash_functions *func)
2375 {
2376 struct ena_rss *rss = &ena_dev->rss;
2377 struct ena_admin_get_feat_resp get_resp;
2378 int rc;
2379
2380 if (unlikely(!func))
2381 return -EINVAL;
2382
2383 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2384 ENA_ADMIN_RSS_HASH_FUNCTION,
2385 rss->hash_key_dma_addr,
2386 sizeof(*rss->hash_key), 0);
2387 if (unlikely(rc))
2388 return rc;
2389
2390 /* ffs() returns 1 in case the lsb is set */
2391 rss->hash_func = ffs(get_resp.u.flow_hash_func.selected_func);
2392 if (rss->hash_func)
2393 rss->hash_func--;
2394
2395 *func = rss->hash_func;
2396
2397 return 0;
2398 }
2399
ena_com_get_hash_key(struct ena_com_dev * ena_dev,u8 * key)2400 int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key)
2401 {
2402 struct ena_admin_feature_rss_flow_hash_control *hash_key =
2403 ena_dev->rss.hash_key;
2404
2405 if (key)
2406 memcpy(key, hash_key->key,
2407 (size_t)(hash_key->key_parts) * sizeof(hash_key->key[0]));
2408
2409 return 0;
2410 }
2411
ena_com_get_hash_ctrl(struct ena_com_dev * ena_dev,enum ena_admin_flow_hash_proto proto,u16 * fields)2412 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2413 enum ena_admin_flow_hash_proto proto,
2414 u16 *fields)
2415 {
2416 struct ena_rss *rss = &ena_dev->rss;
2417 struct ena_admin_get_feat_resp get_resp;
2418 int rc;
2419
2420 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2421 ENA_ADMIN_RSS_HASH_INPUT,
2422 rss->hash_ctrl_dma_addr,
2423 sizeof(*rss->hash_ctrl), 0);
2424 if (unlikely(rc))
2425 return rc;
2426
2427 if (fields)
2428 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2429
2430 return 0;
2431 }
2432
ena_com_set_hash_ctrl(struct ena_com_dev * ena_dev)2433 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2434 {
2435 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2436 struct ena_rss *rss = &ena_dev->rss;
2437 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2438 struct ena_admin_set_feat_cmd cmd;
2439 struct ena_admin_set_feat_resp resp;
2440 int ret;
2441
2442 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_INPUT)) {
2443 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
2444 ENA_ADMIN_RSS_HASH_INPUT);
2445 return -EOPNOTSUPP;
2446 }
2447
2448 memset(&cmd, 0x0, sizeof(cmd));
2449
2450 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2451 cmd.aq_common_descriptor.flags =
2452 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2453 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2454 cmd.u.flow_hash_input.enabled_input_sort =
2455 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2456 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2457
2458 ret = ena_com_mem_addr_set(ena_dev,
2459 &cmd.control_buffer.address,
2460 rss->hash_ctrl_dma_addr);
2461 if (unlikely(ret)) {
2462 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2463 return ret;
2464 }
2465 cmd.control_buffer.length = sizeof(*hash_ctrl);
2466
2467 ret = ena_com_execute_admin_command(admin_queue,
2468 (struct ena_admin_aq_entry *)&cmd,
2469 sizeof(cmd),
2470 (struct ena_admin_acq_entry *)&resp,
2471 sizeof(resp));
2472 if (unlikely(ret))
2473 netdev_err(ena_dev->net_device, "Failed to set hash input. error: %d\n", ret);
2474
2475 return ret;
2476 }
2477
ena_com_set_default_hash_ctrl(struct ena_com_dev * ena_dev)2478 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2479 {
2480 struct ena_rss *rss = &ena_dev->rss;
2481 struct ena_admin_feature_rss_hash_control *hash_ctrl =
2482 rss->hash_ctrl;
2483 u16 available_fields = 0;
2484 int rc, i;
2485
2486 /* Get the supported hash input */
2487 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2488 if (unlikely(rc))
2489 return rc;
2490
2491 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2492 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2493 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2494
2495 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2496 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2497 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2498
2499 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2500 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2501 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2502
2503 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2504 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2505 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2506
2507 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2508 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2509
2510 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2511 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2512
2513 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2514 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2515
2516 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2517 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2518
2519 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2520 available_fields = hash_ctrl->selected_fields[i].fields &
2521 hash_ctrl->supported_fields[i].fields;
2522 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2523 netdev_err(ena_dev->net_device,
2524 "Hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2525 i, hash_ctrl->supported_fields[i].fields,
2526 hash_ctrl->selected_fields[i].fields);
2527 return -EOPNOTSUPP;
2528 }
2529 }
2530
2531 rc = ena_com_set_hash_ctrl(ena_dev);
2532
2533 /* In case of failure, restore the old hash ctrl */
2534 if (unlikely(rc))
2535 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2536
2537 return rc;
2538 }
2539
ena_com_fill_hash_ctrl(struct ena_com_dev * ena_dev,enum ena_admin_flow_hash_proto proto,u16 hash_fields)2540 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2541 enum ena_admin_flow_hash_proto proto,
2542 u16 hash_fields)
2543 {
2544 struct ena_rss *rss = &ena_dev->rss;
2545 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2546 u16 supported_fields;
2547 int rc;
2548
2549 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2550 netdev_err(ena_dev->net_device, "Invalid proto num (%u)\n", proto);
2551 return -EINVAL;
2552 }
2553
2554 /* Get the ctrl table */
2555 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2556 if (unlikely(rc))
2557 return rc;
2558
2559 /* Make sure all the fields are supported */
2560 supported_fields = hash_ctrl->supported_fields[proto].fields;
2561 if ((hash_fields & supported_fields) != hash_fields) {
2562 netdev_err(ena_dev->net_device,
2563 "Proto %d doesn't support the required fields %x. supports only: %x\n",
2564 proto, hash_fields, supported_fields);
2565 }
2566
2567 hash_ctrl->selected_fields[proto].fields = hash_fields;
2568
2569 rc = ena_com_set_hash_ctrl(ena_dev);
2570
2571 /* In case of failure, restore the old hash ctrl */
2572 if (unlikely(rc))
2573 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2574
2575 return 0;
2576 }
2577
ena_com_indirect_table_fill_entry(struct ena_com_dev * ena_dev,u16 entry_idx,u16 entry_value)2578 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2579 u16 entry_idx, u16 entry_value)
2580 {
2581 struct ena_rss *rss = &ena_dev->rss;
2582
2583 if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2584 return -EINVAL;
2585
2586 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2587 return -EINVAL;
2588
2589 rss->host_rss_ind_tbl[entry_idx] = entry_value;
2590
2591 return 0;
2592 }
2593
ena_com_indirect_table_set(struct ena_com_dev * ena_dev)2594 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2595 {
2596 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2597 struct ena_rss *rss = &ena_dev->rss;
2598 struct ena_admin_set_feat_cmd cmd;
2599 struct ena_admin_set_feat_resp resp;
2600 int ret;
2601
2602 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG)) {
2603 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
2604 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG);
2605 return -EOPNOTSUPP;
2606 }
2607
2608 ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2609 if (ret) {
2610 netdev_err(ena_dev->net_device,
2611 "Failed to convert host indirection table to device table\n");
2612 return ret;
2613 }
2614
2615 memset(&cmd, 0x0, sizeof(cmd));
2616
2617 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2618 cmd.aq_common_descriptor.flags =
2619 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2620 cmd.feat_common.feature_id = ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG;
2621 cmd.u.ind_table.size = rss->tbl_log_size;
2622 cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2623
2624 ret = ena_com_mem_addr_set(ena_dev,
2625 &cmd.control_buffer.address,
2626 rss->rss_ind_tbl_dma_addr);
2627 if (unlikely(ret)) {
2628 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2629 return ret;
2630 }
2631
2632 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2633 sizeof(struct ena_admin_rss_ind_table_entry);
2634
2635 ret = ena_com_execute_admin_command(admin_queue,
2636 (struct ena_admin_aq_entry *)&cmd,
2637 sizeof(cmd),
2638 (struct ena_admin_acq_entry *)&resp,
2639 sizeof(resp));
2640
2641 if (unlikely(ret))
2642 netdev_err(ena_dev->net_device, "Failed to set indirect table. error: %d\n", ret);
2643
2644 return ret;
2645 }
2646
ena_com_indirect_table_get(struct ena_com_dev * ena_dev,u32 * ind_tbl)2647 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2648 {
2649 struct ena_rss *rss = &ena_dev->rss;
2650 struct ena_admin_get_feat_resp get_resp;
2651 u32 tbl_size;
2652 int i, rc;
2653
2654 tbl_size = (1ULL << rss->tbl_log_size) *
2655 sizeof(struct ena_admin_rss_ind_table_entry);
2656
2657 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2658 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG,
2659 rss->rss_ind_tbl_dma_addr,
2660 tbl_size, 0);
2661 if (unlikely(rc))
2662 return rc;
2663
2664 if (!ind_tbl)
2665 return 0;
2666
2667 for (i = 0; i < (1 << rss->tbl_log_size); i++)
2668 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2669
2670 return 0;
2671 }
2672
ena_com_rss_init(struct ena_com_dev * ena_dev,u16 indr_tbl_log_size)2673 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2674 {
2675 int rc;
2676
2677 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2678
2679 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2680 if (unlikely(rc))
2681 goto err_indr_tbl;
2682
2683 /* The following function might return unsupported in case the
2684 * device doesn't support setting the key / hash function. We can safely
2685 * ignore this error and have indirection table support only.
2686 */
2687 rc = ena_com_hash_key_allocate(ena_dev);
2688 if (likely(!rc))
2689 ena_com_hash_key_fill_default_key(ena_dev);
2690 else if (rc != -EOPNOTSUPP)
2691 goto err_hash_key;
2692
2693 rc = ena_com_hash_ctrl_init(ena_dev);
2694 if (unlikely(rc))
2695 goto err_hash_ctrl;
2696
2697 return 0;
2698
2699 err_hash_ctrl:
2700 ena_com_hash_key_destroy(ena_dev);
2701 err_hash_key:
2702 ena_com_indirect_table_destroy(ena_dev);
2703 err_indr_tbl:
2704
2705 return rc;
2706 }
2707
ena_com_rss_destroy(struct ena_com_dev * ena_dev)2708 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2709 {
2710 ena_com_indirect_table_destroy(ena_dev);
2711 ena_com_hash_key_destroy(ena_dev);
2712 ena_com_hash_ctrl_destroy(ena_dev);
2713
2714 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2715 }
2716
ena_com_allocate_host_info(struct ena_com_dev * ena_dev)2717 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2718 {
2719 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2720
2721 host_attr->host_info = dma_alloc_coherent(ena_dev->dmadev, SZ_4K,
2722 &host_attr->host_info_dma_addr, GFP_KERNEL);
2723 if (unlikely(!host_attr->host_info))
2724 return -ENOMEM;
2725
2726 host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR <<
2727 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
2728 (ENA_COMMON_SPEC_VERSION_MINOR));
2729
2730 return 0;
2731 }
2732
ena_com_allocate_debug_area(struct ena_com_dev * ena_dev,u32 debug_area_size)2733 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2734 u32 debug_area_size)
2735 {
2736 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2737
2738 host_attr->debug_area_virt_addr =
2739 dma_alloc_coherent(ena_dev->dmadev, debug_area_size,
2740 &host_attr->debug_area_dma_addr, GFP_KERNEL);
2741 if (unlikely(!host_attr->debug_area_virt_addr)) {
2742 host_attr->debug_area_size = 0;
2743 return -ENOMEM;
2744 }
2745
2746 host_attr->debug_area_size = debug_area_size;
2747
2748 return 0;
2749 }
2750
ena_com_allocate_customer_metrics_buffer(struct ena_com_dev * ena_dev)2751 int ena_com_allocate_customer_metrics_buffer(struct ena_com_dev *ena_dev)
2752 {
2753 struct ena_customer_metrics *customer_metrics = &ena_dev->customer_metrics;
2754
2755 customer_metrics->buffer_len = ENA_CUSTOMER_METRICS_BUFFER_SIZE;
2756 customer_metrics->buffer_virt_addr = NULL;
2757
2758 customer_metrics->buffer_virt_addr =
2759 dma_alloc_coherent(ena_dev->dmadev, customer_metrics->buffer_len,
2760 &customer_metrics->buffer_dma_addr, GFP_KERNEL);
2761 if (!customer_metrics->buffer_virt_addr) {
2762 customer_metrics->buffer_len = 0;
2763 return -ENOMEM;
2764 }
2765
2766 return 0;
2767 }
2768
ena_com_delete_host_info(struct ena_com_dev * ena_dev)2769 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2770 {
2771 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2772
2773 if (host_attr->host_info) {
2774 dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info,
2775 host_attr->host_info_dma_addr);
2776 host_attr->host_info = NULL;
2777 }
2778 }
2779
ena_com_delete_debug_area(struct ena_com_dev * ena_dev)2780 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2781 {
2782 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2783
2784 if (host_attr->debug_area_virt_addr) {
2785 dma_free_coherent(ena_dev->dmadev, host_attr->debug_area_size,
2786 host_attr->debug_area_virt_addr, host_attr->debug_area_dma_addr);
2787 host_attr->debug_area_virt_addr = NULL;
2788 }
2789 }
2790
ena_com_delete_customer_metrics_buffer(struct ena_com_dev * ena_dev)2791 void ena_com_delete_customer_metrics_buffer(struct ena_com_dev *ena_dev)
2792 {
2793 struct ena_customer_metrics *customer_metrics = &ena_dev->customer_metrics;
2794
2795 if (customer_metrics->buffer_virt_addr) {
2796 dma_free_coherent(ena_dev->dmadev, customer_metrics->buffer_len,
2797 customer_metrics->buffer_virt_addr,
2798 customer_metrics->buffer_dma_addr);
2799 customer_metrics->buffer_virt_addr = NULL;
2800 customer_metrics->buffer_len = 0;
2801 }
2802 }
2803
ena_com_set_host_attributes(struct ena_com_dev * ena_dev)2804 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2805 {
2806 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2807 struct ena_com_admin_queue *admin_queue;
2808 struct ena_admin_set_feat_cmd cmd;
2809 struct ena_admin_set_feat_resp resp;
2810
2811 int ret;
2812
2813 /* Host attribute config is called before ena_com_get_dev_attr_feat
2814 * so ena_com can't check if the feature is supported.
2815 */
2816
2817 memset(&cmd, 0x0, sizeof(cmd));
2818 admin_queue = &ena_dev->admin_queue;
2819
2820 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2821 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2822
2823 ret = ena_com_mem_addr_set(ena_dev,
2824 &cmd.u.host_attr.debug_ba,
2825 host_attr->debug_area_dma_addr);
2826 if (unlikely(ret)) {
2827 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2828 return ret;
2829 }
2830
2831 ret = ena_com_mem_addr_set(ena_dev,
2832 &cmd.u.host_attr.os_info_ba,
2833 host_attr->host_info_dma_addr);
2834 if (unlikely(ret)) {
2835 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2836 return ret;
2837 }
2838
2839 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2840
2841 ret = ena_com_execute_admin_command(admin_queue,
2842 (struct ena_admin_aq_entry *)&cmd,
2843 sizeof(cmd),
2844 (struct ena_admin_acq_entry *)&resp,
2845 sizeof(resp));
2846
2847 if (unlikely(ret))
2848 netdev_err(ena_dev->net_device, "Failed to set host attributes: %d\n", ret);
2849
2850 return ret;
2851 }
2852
2853 /* Interrupt moderation */
ena_com_interrupt_moderation_supported(struct ena_com_dev * ena_dev)2854 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2855 {
2856 return ena_com_check_supported_feature_id(ena_dev,
2857 ENA_ADMIN_INTERRUPT_MODERATION);
2858 }
2859
ena_com_update_nonadaptive_moderation_interval(struct ena_com_dev * ena_dev,u32 coalesce_usecs,u32 intr_delay_resolution,u32 * intr_moder_interval)2860 static int ena_com_update_nonadaptive_moderation_interval(struct ena_com_dev *ena_dev,
2861 u32 coalesce_usecs,
2862 u32 intr_delay_resolution,
2863 u32 *intr_moder_interval)
2864 {
2865 if (!intr_delay_resolution) {
2866 netdev_err(ena_dev->net_device, "Illegal interrupt delay granularity value\n");
2867 return -EFAULT;
2868 }
2869
2870 *intr_moder_interval = coalesce_usecs / intr_delay_resolution;
2871
2872 return 0;
2873 }
2874
ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev * ena_dev,u32 tx_coalesce_usecs)2875 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2876 u32 tx_coalesce_usecs)
2877 {
2878 return ena_com_update_nonadaptive_moderation_interval(ena_dev,
2879 tx_coalesce_usecs,
2880 ena_dev->intr_delay_resolution,
2881 &ena_dev->intr_moder_tx_interval);
2882 }
2883
ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev * ena_dev,u32 rx_coalesce_usecs)2884 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2885 u32 rx_coalesce_usecs)
2886 {
2887 return ena_com_update_nonadaptive_moderation_interval(ena_dev,
2888 rx_coalesce_usecs,
2889 ena_dev->intr_delay_resolution,
2890 &ena_dev->intr_moder_rx_interval);
2891 }
2892
ena_com_init_interrupt_moderation(struct ena_com_dev * ena_dev)2893 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2894 {
2895 struct ena_admin_get_feat_resp get_resp;
2896 u16 delay_resolution;
2897 int rc;
2898
2899 rc = ena_com_get_feature(ena_dev, &get_resp,
2900 ENA_ADMIN_INTERRUPT_MODERATION, 0);
2901
2902 if (rc) {
2903 if (rc == -EOPNOTSUPP) {
2904 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
2905 ENA_ADMIN_INTERRUPT_MODERATION);
2906 rc = 0;
2907 } else {
2908 netdev_err(ena_dev->net_device,
2909 "Failed to get interrupt moderation admin cmd. rc: %d\n", rc);
2910 }
2911
2912 /* no moderation supported, disable adaptive support */
2913 ena_com_disable_adaptive_moderation(ena_dev);
2914 return rc;
2915 }
2916
2917 /* if moderation is supported by device we set adaptive moderation */
2918 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2919 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2920
2921 /* Disable adaptive moderation by default - can be enabled later */
2922 ena_com_disable_adaptive_moderation(ena_dev);
2923
2924 return 0;
2925 }
2926
ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev * ena_dev)2927 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2928 {
2929 return ena_dev->intr_moder_tx_interval;
2930 }
2931
ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev * ena_dev)2932 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2933 {
2934 return ena_dev->intr_moder_rx_interval;
2935 }
2936
ena_com_config_dev_mode(struct ena_com_dev * ena_dev,struct ena_admin_feature_llq_desc * llq_features,struct ena_llq_configurations * llq_default_cfg)2937 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
2938 struct ena_admin_feature_llq_desc *llq_features,
2939 struct ena_llq_configurations *llq_default_cfg)
2940 {
2941 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
2942 int rc;
2943
2944 if (!llq_features->max_llq_num) {
2945 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
2946 return 0;
2947 }
2948
2949 rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg);
2950 if (rc)
2951 return rc;
2952
2953 ena_dev->tx_max_header_size = llq_info->desc_list_entry_size -
2954 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc));
2955
2956 if (unlikely(ena_dev->tx_max_header_size == 0)) {
2957 netdev_err(ena_dev->net_device, "The size of the LLQ entry is smaller than needed\n");
2958 return -EINVAL;
2959 }
2960
2961 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
2962
2963 return 0;
2964 }
2965