1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /*
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
4 */
5
6 #include "ena_com.h"
7
8 /*****************************************************************************/
9 /*****************************************************************************/
10
11 /* Timeout in micro-sec */
12 #define ADMIN_CMD_TIMEOUT_US (3000000)
13
14 #define ENA_ASYNC_QUEUE_DEPTH 16
15 #define ENA_ADMIN_QUEUE_DEPTH 32
16
17
18 #define ENA_CTRL_MAJOR 0
19 #define ENA_CTRL_MINOR 0
20 #define ENA_CTRL_SUB_MINOR 1
21
22 #define MIN_ENA_CTRL_VER \
23 (((ENA_CTRL_MAJOR) << \
24 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
25 ((ENA_CTRL_MINOR) << \
26 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
27 (ENA_CTRL_SUB_MINOR))
28
29 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x)))
30 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32))
31
32 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
33
34 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4
35
36 #define ENA_REGS_ADMIN_INTR_MASK 1
37
38 #define ENA_MAX_BACKOFF_DELAY_EXP 16U
39
40 #define ENA_MIN_ADMIN_POLL_US 100
41
42 #define ENA_MAX_ADMIN_POLL_US 5000
43
44 /* PHC definitions */
45 #define ENA_PHC_DEFAULT_EXPIRE_TIMEOUT_USEC 10
46 #define ENA_PHC_DEFAULT_BLOCK_TIMEOUT_USEC 1000
47 #define ENA_PHC_REQ_ID_OFFSET 0xDEAD
48 #define ENA_PHC_ERROR_FLAGS (ENA_ADMIN_PHC_ERROR_FLAG_TIMESTAMP)
49
50 /*****************************************************************************/
51 /*****************************************************************************/
52 /*****************************************************************************/
53
54 enum ena_cmd_status {
55 ENA_CMD_SUBMITTED,
56 ENA_CMD_COMPLETED,
57 /* Abort - canceled by the driver */
58 ENA_CMD_ABORTED,
59 };
60
61 struct ena_comp_ctx {
62 struct completion wait_event;
63 struct ena_admin_acq_entry *user_cqe;
64 u32 comp_size;
65 enum ena_cmd_status status;
66 /* status from the device */
67 u8 comp_status;
68 u8 cmd_opcode;
69 bool occupied;
70 };
71
72 struct ena_com_stats_ctx {
73 struct ena_admin_aq_get_stats_cmd get_cmd;
74 struct ena_admin_acq_get_stats_resp get_resp;
75 };
76
ena_com_mem_addr_set(struct ena_com_dev * ena_dev,struct ena_common_mem_addr * ena_addr,dma_addr_t addr)77 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
78 struct ena_common_mem_addr *ena_addr,
79 dma_addr_t addr)
80 {
81 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
82 netdev_err(ena_dev->net_device,
83 "DMA address has more bits that the device supports\n");
84 return -EINVAL;
85 }
86
87 ena_addr->mem_addr_low = lower_32_bits(addr);
88 ena_addr->mem_addr_high = (u16)upper_32_bits(addr);
89
90 return 0;
91 }
92
ena_com_admin_init_sq(struct ena_com_admin_queue * admin_queue)93 static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue)
94 {
95 struct ena_com_dev *ena_dev = admin_queue->ena_dev;
96 struct ena_com_admin_sq *sq = &admin_queue->sq;
97 u16 size = ADMIN_SQ_SIZE(admin_queue->q_depth);
98
99 sq->entries = dma_alloc_coherent(admin_queue->q_dmadev, size, &sq->dma_addr, GFP_KERNEL);
100
101 if (!sq->entries) {
102 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
103 return -ENOMEM;
104 }
105
106 sq->head = 0;
107 sq->tail = 0;
108 sq->phase = 1;
109
110 sq->db_addr = NULL;
111
112 return 0;
113 }
114
ena_com_admin_init_cq(struct ena_com_admin_queue * admin_queue)115 static int ena_com_admin_init_cq(struct ena_com_admin_queue *admin_queue)
116 {
117 struct ena_com_dev *ena_dev = admin_queue->ena_dev;
118 struct ena_com_admin_cq *cq = &admin_queue->cq;
119 u16 size = ADMIN_CQ_SIZE(admin_queue->q_depth);
120
121 cq->entries = dma_alloc_coherent(admin_queue->q_dmadev, size, &cq->dma_addr, GFP_KERNEL);
122
123 if (!cq->entries) {
124 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
125 return -ENOMEM;
126 }
127
128 cq->head = 0;
129 cq->phase = 1;
130
131 return 0;
132 }
133
ena_com_admin_init_aenq(struct ena_com_dev * ena_dev,struct ena_aenq_handlers * aenq_handlers)134 static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev,
135 struct ena_aenq_handlers *aenq_handlers)
136 {
137 struct ena_com_aenq *aenq = &ena_dev->aenq;
138 u32 addr_low, addr_high, aenq_caps;
139 u16 size;
140
141 ena_dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
142 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
143 aenq->entries = dma_alloc_coherent(ena_dev->dmadev, size, &aenq->dma_addr, GFP_KERNEL);
144
145 if (!aenq->entries) {
146 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
147 return -ENOMEM;
148 }
149
150 aenq->head = aenq->q_depth;
151 aenq->phase = 1;
152
153 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
154 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
155
156 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
157 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
158
159 aenq_caps = 0;
160 aenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
161 aenq_caps |=
162 (sizeof(struct ena_admin_aenq_entry) << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
163 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
164 writel(aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
165
166 if (unlikely(!aenq_handlers)) {
167 netdev_err(ena_dev->net_device, "AENQ handlers pointer is NULL\n");
168 return -EINVAL;
169 }
170
171 aenq->aenq_handlers = aenq_handlers;
172
173 return 0;
174 }
175
comp_ctxt_release(struct ena_com_admin_queue * queue,struct ena_comp_ctx * comp_ctx)176 static void comp_ctxt_release(struct ena_com_admin_queue *queue,
177 struct ena_comp_ctx *comp_ctx)
178 {
179 comp_ctx->occupied = false;
180 atomic_dec(&queue->outstanding_cmds);
181 }
182
get_comp_ctxt(struct ena_com_admin_queue * admin_queue,u16 command_id,bool capture)183 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *admin_queue,
184 u16 command_id, bool capture)
185 {
186 if (unlikely(command_id >= admin_queue->q_depth)) {
187 netdev_err(admin_queue->ena_dev->net_device,
188 "Command id is larger than the queue size. cmd_id: %u queue size %d\n",
189 command_id, admin_queue->q_depth);
190 return NULL;
191 }
192
193 if (unlikely(!admin_queue->comp_ctx)) {
194 netdev_err(admin_queue->ena_dev->net_device, "Completion context is NULL\n");
195 return NULL;
196 }
197
198 if (unlikely(admin_queue->comp_ctx[command_id].occupied && capture)) {
199 netdev_err(admin_queue->ena_dev->net_device, "Completion context is occupied\n");
200 return NULL;
201 }
202
203 if (capture) {
204 atomic_inc(&admin_queue->outstanding_cmds);
205 admin_queue->comp_ctx[command_id].occupied = true;
206 }
207
208 return &admin_queue->comp_ctx[command_id];
209 }
210
__ena_com_submit_admin_cmd(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size_in_bytes,struct ena_admin_acq_entry * comp,size_t comp_size_in_bytes)211 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
212 struct ena_admin_aq_entry *cmd,
213 size_t cmd_size_in_bytes,
214 struct ena_admin_acq_entry *comp,
215 size_t comp_size_in_bytes)
216 {
217 struct ena_comp_ctx *comp_ctx;
218 u16 tail_masked, cmd_id;
219 u16 queue_size_mask;
220 u16 cnt;
221
222 queue_size_mask = admin_queue->q_depth - 1;
223
224 tail_masked = admin_queue->sq.tail & queue_size_mask;
225
226 /* In case of queue FULL */
227 cnt = (u16)atomic_read(&admin_queue->outstanding_cmds);
228 if (cnt >= admin_queue->q_depth) {
229 netdev_dbg(admin_queue->ena_dev->net_device, "Admin queue is full.\n");
230 admin_queue->stats.out_of_space++;
231 return ERR_PTR(-ENOSPC);
232 }
233
234 cmd_id = admin_queue->curr_cmd_id;
235
236 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
237 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
238
239 cmd->aq_common_descriptor.command_id |= cmd_id &
240 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
241
242 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
243 if (unlikely(!comp_ctx))
244 return ERR_PTR(-EINVAL);
245
246 comp_ctx->status = ENA_CMD_SUBMITTED;
247 comp_ctx->comp_size = (u32)comp_size_in_bytes;
248 comp_ctx->user_cqe = comp;
249 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
250
251 reinit_completion(&comp_ctx->wait_event);
252
253 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
254
255 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
256 queue_size_mask;
257
258 admin_queue->sq.tail++;
259 admin_queue->stats.submitted_cmd++;
260
261 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
262 admin_queue->sq.phase = !admin_queue->sq.phase;
263
264 writel(admin_queue->sq.tail, admin_queue->sq.db_addr);
265
266 return comp_ctx;
267 }
268
ena_com_init_comp_ctxt(struct ena_com_admin_queue * admin_queue)269 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *admin_queue)
270 {
271 struct ena_com_dev *ena_dev = admin_queue->ena_dev;
272 size_t size = admin_queue->q_depth * sizeof(struct ena_comp_ctx);
273 struct ena_comp_ctx *comp_ctx;
274 u16 i;
275
276 admin_queue->comp_ctx = devm_kzalloc(admin_queue->q_dmadev, size, GFP_KERNEL);
277 if (unlikely(!admin_queue->comp_ctx)) {
278 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
279 return -ENOMEM;
280 }
281
282 for (i = 0; i < admin_queue->q_depth; i++) {
283 comp_ctx = get_comp_ctxt(admin_queue, i, false);
284 if (comp_ctx)
285 init_completion(&comp_ctx->wait_event);
286 }
287
288 return 0;
289 }
290
ena_com_submit_admin_cmd(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size_in_bytes,struct ena_admin_acq_entry * comp,size_t comp_size_in_bytes)291 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
292 struct ena_admin_aq_entry *cmd,
293 size_t cmd_size_in_bytes,
294 struct ena_admin_acq_entry *comp,
295 size_t comp_size_in_bytes)
296 {
297 unsigned long flags = 0;
298 struct ena_comp_ctx *comp_ctx;
299
300 spin_lock_irqsave(&admin_queue->q_lock, flags);
301 if (unlikely(!admin_queue->running_state)) {
302 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
303 return ERR_PTR(-ENODEV);
304 }
305 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
306 cmd_size_in_bytes,
307 comp,
308 comp_size_in_bytes);
309 if (IS_ERR(comp_ctx))
310 admin_queue->running_state = false;
311 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
312
313 return comp_ctx;
314 }
315
ena_com_init_io_sq(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx,struct ena_com_io_sq * io_sq)316 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
317 struct ena_com_create_io_ctx *ctx,
318 struct ena_com_io_sq *io_sq)
319 {
320 size_t size;
321
322 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
323
324 io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits;
325 io_sq->desc_entry_size =
326 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
327 sizeof(struct ena_eth_io_tx_desc) :
328 sizeof(struct ena_eth_io_rx_desc);
329
330 size = io_sq->desc_entry_size * io_sq->q_depth;
331
332 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
333 io_sq->desc_addr.virt_addr =
334 dma_alloc_coherent(ena_dev->dmadev, size, &io_sq->desc_addr.phys_addr,
335 GFP_KERNEL);
336 if (!io_sq->desc_addr.virt_addr) {
337 io_sq->desc_addr.virt_addr =
338 dma_alloc_coherent(ena_dev->dmadev, size,
339 &io_sq->desc_addr.phys_addr, GFP_KERNEL);
340 }
341
342 if (!io_sq->desc_addr.virt_addr) {
343 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
344 return -ENOMEM;
345 }
346 }
347
348 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
349 /* Allocate bounce buffers */
350 io_sq->bounce_buf_ctrl.buffer_size =
351 ena_dev->llq_info.desc_list_entry_size;
352 io_sq->bounce_buf_ctrl.buffers_num =
353 ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
354 io_sq->bounce_buf_ctrl.next_to_use = 0;
355
356 size = (size_t)io_sq->bounce_buf_ctrl.buffer_size *
357 io_sq->bounce_buf_ctrl.buffers_num;
358
359 io_sq->bounce_buf_ctrl.base_buffer = devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
360 if (!io_sq->bounce_buf_ctrl.base_buffer)
361 io_sq->bounce_buf_ctrl.base_buffer =
362 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
363
364 if (!io_sq->bounce_buf_ctrl.base_buffer) {
365 netdev_err(ena_dev->net_device, "Bounce buffer memory allocation failed\n");
366 return -ENOMEM;
367 }
368
369 memcpy(&io_sq->llq_info, &ena_dev->llq_info,
370 sizeof(io_sq->llq_info));
371
372 /* Initiate the first bounce buffer */
373 io_sq->llq_buf_ctrl.curr_bounce_buf =
374 ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
375 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
376 0x0, io_sq->llq_info.desc_list_entry_size);
377 io_sq->llq_buf_ctrl.descs_left_in_line =
378 io_sq->llq_info.descs_num_before_header;
379 io_sq->disable_meta_caching =
380 io_sq->llq_info.disable_meta_caching;
381
382 if (io_sq->llq_info.max_entries_in_tx_burst > 0)
383 io_sq->entries_in_tx_burst_left =
384 io_sq->llq_info.max_entries_in_tx_burst;
385 }
386
387 io_sq->tail = 0;
388 io_sq->next_to_comp = 0;
389 io_sq->phase = 1;
390
391 return 0;
392 }
393
ena_com_init_io_cq(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx,struct ena_com_io_cq * io_cq)394 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
395 struct ena_com_create_io_ctx *ctx,
396 struct ena_com_io_cq *io_cq)
397 {
398 size_t size;
399
400 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
401
402 /* Use the basic completion descriptor for Rx */
403 io_cq->cdesc_entry_size_in_bytes =
404 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
405 sizeof(struct ena_eth_io_tx_cdesc) :
406 sizeof(struct ena_eth_io_rx_cdesc_base);
407
408 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
409
410 io_cq->cdesc_addr.virt_addr =
411 dma_alloc_coherent(ena_dev->dmadev, size, &io_cq->cdesc_addr.phys_addr, GFP_KERNEL);
412 if (!io_cq->cdesc_addr.virt_addr) {
413 io_cq->cdesc_addr.virt_addr =
414 dma_alloc_coherent(ena_dev->dmadev, size, &io_cq->cdesc_addr.phys_addr,
415 GFP_KERNEL);
416 }
417
418 if (!io_cq->cdesc_addr.virt_addr) {
419 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
420 return -ENOMEM;
421 }
422
423 io_cq->phase = 1;
424 io_cq->head = 0;
425
426 return 0;
427 }
428
ena_com_handle_single_admin_completion(struct ena_com_admin_queue * admin_queue,struct ena_admin_acq_entry * cqe)429 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
430 struct ena_admin_acq_entry *cqe)
431 {
432 struct ena_comp_ctx *comp_ctx;
433 u16 cmd_id;
434
435 cmd_id = cqe->acq_common_descriptor.command &
436 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
437
438 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
439 if (unlikely(!comp_ctx)) {
440 netdev_err(admin_queue->ena_dev->net_device,
441 "comp_ctx is NULL. Changing the admin queue running state\n");
442 admin_queue->running_state = false;
443 return;
444 }
445
446 comp_ctx->status = ENA_CMD_COMPLETED;
447 comp_ctx->comp_status = cqe->acq_common_descriptor.status;
448
449 if (comp_ctx->user_cqe)
450 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
451
452 if (!admin_queue->polling)
453 complete(&comp_ctx->wait_event);
454 }
455
ena_com_handle_admin_completion(struct ena_com_admin_queue * admin_queue)456 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
457 {
458 struct ena_admin_acq_entry *cqe = NULL;
459 u16 comp_num = 0;
460 u16 head_masked;
461 u8 phase;
462
463 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
464 phase = admin_queue->cq.phase;
465
466 cqe = &admin_queue->cq.entries[head_masked];
467
468 /* Go over all the completions */
469 while ((READ_ONCE(cqe->acq_common_descriptor.flags) &
470 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
471 /* Do not read the rest of the completion entry before the
472 * phase bit was validated
473 */
474 dma_rmb();
475 ena_com_handle_single_admin_completion(admin_queue, cqe);
476
477 head_masked++;
478 comp_num++;
479 if (unlikely(head_masked == admin_queue->q_depth)) {
480 head_masked = 0;
481 phase = !phase;
482 }
483
484 cqe = &admin_queue->cq.entries[head_masked];
485 }
486
487 admin_queue->cq.head += comp_num;
488 admin_queue->cq.phase = phase;
489 admin_queue->sq.head += comp_num;
490 admin_queue->stats.completed_cmd += comp_num;
491 }
492
ena_com_comp_status_to_errno(struct ena_com_admin_queue * admin_queue,u8 comp_status)493 static int ena_com_comp_status_to_errno(struct ena_com_admin_queue *admin_queue,
494 u8 comp_status)
495 {
496 if (unlikely(comp_status != 0))
497 netdev_err(admin_queue->ena_dev->net_device, "Admin command failed[%u]\n",
498 comp_status);
499
500 switch (comp_status) {
501 case ENA_ADMIN_SUCCESS:
502 return 0;
503 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
504 return -ENOMEM;
505 case ENA_ADMIN_UNSUPPORTED_OPCODE:
506 return -EOPNOTSUPP;
507 case ENA_ADMIN_BAD_OPCODE:
508 case ENA_ADMIN_MALFORMED_REQUEST:
509 case ENA_ADMIN_ILLEGAL_PARAMETER:
510 case ENA_ADMIN_UNKNOWN_ERROR:
511 return -EINVAL;
512 case ENA_ADMIN_RESOURCE_BUSY:
513 return -EAGAIN;
514 }
515
516 return -EINVAL;
517 }
518
ena_delay_exponential_backoff_us(u32 exp,u32 delay_us)519 static void ena_delay_exponential_backoff_us(u32 exp, u32 delay_us)
520 {
521 exp = min_t(u32, exp, ENA_MAX_BACKOFF_DELAY_EXP);
522 delay_us = max_t(u32, ENA_MIN_ADMIN_POLL_US, delay_us);
523 delay_us = min_t(u32, delay_us * (1U << exp), ENA_MAX_ADMIN_POLL_US);
524 usleep_range(delay_us, 2 * delay_us);
525 }
526
ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)527 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
528 struct ena_com_admin_queue *admin_queue)
529 {
530 unsigned long flags = 0;
531 unsigned long timeout;
532 int ret;
533 u32 exp = 0;
534
535 timeout = jiffies + usecs_to_jiffies(admin_queue->completion_timeout);
536
537 while (1) {
538 spin_lock_irqsave(&admin_queue->q_lock, flags);
539 ena_com_handle_admin_completion(admin_queue);
540 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
541
542 if (comp_ctx->status != ENA_CMD_SUBMITTED)
543 break;
544
545 if (time_is_before_jiffies(timeout)) {
546 netdev_err(admin_queue->ena_dev->net_device,
547 "Wait for completion (polling) timeout\n");
548 /* ENA didn't have any completion */
549 spin_lock_irqsave(&admin_queue->q_lock, flags);
550 admin_queue->stats.no_completion++;
551 admin_queue->running_state = false;
552 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
553
554 ret = -ETIME;
555 goto err;
556 }
557
558 ena_delay_exponential_backoff_us(exp++,
559 admin_queue->ena_dev->ena_min_poll_delay_us);
560 }
561
562 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
563 netdev_err(admin_queue->ena_dev->net_device, "Command was aborted\n");
564 spin_lock_irqsave(&admin_queue->q_lock, flags);
565 admin_queue->stats.aborted_cmd++;
566 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
567 ret = -ENODEV;
568 goto err;
569 }
570
571 WARN(comp_ctx->status != ENA_CMD_COMPLETED, "Invalid comp status %d\n", comp_ctx->status);
572
573 ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status);
574 err:
575 comp_ctxt_release(admin_queue, comp_ctx);
576 return ret;
577 }
578
579 /*
580 * Set the LLQ configurations of the firmware
581 *
582 * The driver provides only the enabled feature values to the device,
583 * which in turn, checks if they are supported.
584 */
ena_com_set_llq(struct ena_com_dev * ena_dev)585 static int ena_com_set_llq(struct ena_com_dev *ena_dev)
586 {
587 struct ena_com_admin_queue *admin_queue;
588 struct ena_admin_set_feat_cmd cmd;
589 struct ena_admin_set_feat_resp resp;
590 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
591 int ret;
592
593 memset(&cmd, 0x0, sizeof(cmd));
594 admin_queue = &ena_dev->admin_queue;
595
596 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
597 cmd.feat_common.feature_id = ENA_ADMIN_LLQ;
598
599 cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl;
600 cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl;
601 cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header;
602 cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl;
603
604 cmd.u.llq.accel_mode.u.set.enabled_flags =
605 BIT(ENA_ADMIN_DISABLE_META_CACHING) |
606 BIT(ENA_ADMIN_LIMIT_TX_BURST);
607
608 ret = ena_com_execute_admin_command(admin_queue,
609 (struct ena_admin_aq_entry *)&cmd,
610 sizeof(cmd),
611 (struct ena_admin_acq_entry *)&resp,
612 sizeof(resp));
613
614 if (unlikely(ret))
615 netdev_err(ena_dev->net_device, "Failed to set LLQ configurations: %d\n", ret);
616
617 return ret;
618 }
619
ena_com_config_llq_info(struct ena_com_dev * ena_dev,struct ena_admin_feature_llq_desc * llq_features,struct ena_llq_configurations * llq_default_cfg)620 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
621 struct ena_admin_feature_llq_desc *llq_features,
622 struct ena_llq_configurations *llq_default_cfg)
623 {
624 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
625 struct ena_admin_accel_mode_get llq_accel_mode_get;
626 u16 supported_feat;
627 int rc;
628
629 memset(llq_info, 0, sizeof(*llq_info));
630
631 supported_feat = llq_features->header_location_ctrl_supported;
632
633 if (likely(supported_feat & llq_default_cfg->llq_header_location)) {
634 llq_info->header_location_ctrl =
635 llq_default_cfg->llq_header_location;
636 } else {
637 netdev_err(ena_dev->net_device,
638 "Invalid header location control, supported: 0x%x\n", supported_feat);
639 return -EINVAL;
640 }
641
642 if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) {
643 supported_feat = llq_features->descriptors_stride_ctrl_supported;
644 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) {
645 llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl;
646 } else {
647 if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) {
648 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
649 } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) {
650 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
651 } else {
652 netdev_err(ena_dev->net_device,
653 "Invalid desc_stride_ctrl, supported: 0x%x\n",
654 supported_feat);
655 return -EINVAL;
656 }
657
658 netdev_err(ena_dev->net_device,
659 "Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
660 llq_default_cfg->llq_stride_ctrl, supported_feat,
661 llq_info->desc_stride_ctrl);
662 }
663 } else {
664 llq_info->desc_stride_ctrl = 0;
665 }
666
667 supported_feat = llq_features->entry_size_ctrl_supported;
668 if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) {
669 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size;
670 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value;
671 } else {
672 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) {
673 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
674 llq_info->desc_list_entry_size = 128;
675 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) {
676 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B;
677 llq_info->desc_list_entry_size = 192;
678 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) {
679 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B;
680 llq_info->desc_list_entry_size = 256;
681 } else {
682 netdev_err(ena_dev->net_device,
683 "Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat);
684 return -EINVAL;
685 }
686
687 netdev_err(ena_dev->net_device,
688 "Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
689 llq_default_cfg->llq_ring_entry_size, supported_feat,
690 llq_info->desc_list_entry_size);
691 }
692 if (unlikely(llq_info->desc_list_entry_size & 0x7)) {
693 /* The desc list entry size should be whole multiply of 8
694 * This requirement comes from __iowrite64_copy()
695 */
696 netdev_err(ena_dev->net_device, "Illegal entry size %d\n",
697 llq_info->desc_list_entry_size);
698 return -EINVAL;
699 }
700
701 if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)
702 llq_info->descs_per_entry = llq_info->desc_list_entry_size /
703 sizeof(struct ena_eth_io_tx_desc);
704 else
705 llq_info->descs_per_entry = 1;
706
707 supported_feat = llq_features->desc_num_before_header_supported;
708 if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) {
709 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header;
710 } else {
711 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) {
712 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
713 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) {
714 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1;
715 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) {
716 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4;
717 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) {
718 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8;
719 } else {
720 netdev_err(ena_dev->net_device,
721 "Invalid descs_num_before_header, supported: 0x%x\n",
722 supported_feat);
723 return -EINVAL;
724 }
725
726 netdev_err(ena_dev->net_device,
727 "Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
728 llq_default_cfg->llq_num_decs_before_header, supported_feat,
729 llq_info->descs_num_before_header);
730 }
731 /* Check for accelerated queue supported */
732 llq_accel_mode_get = llq_features->accel_mode.u.get;
733
734 llq_info->disable_meta_caching =
735 !!(llq_accel_mode_get.supported_flags &
736 BIT(ENA_ADMIN_DISABLE_META_CACHING));
737
738 if (llq_accel_mode_get.supported_flags & BIT(ENA_ADMIN_LIMIT_TX_BURST))
739 llq_info->max_entries_in_tx_burst =
740 llq_accel_mode_get.max_tx_burst_size /
741 llq_default_cfg->llq_ring_entry_size_value;
742
743 rc = ena_com_set_llq(ena_dev);
744 if (rc)
745 netdev_err(ena_dev->net_device, "Cannot set LLQ configuration: %d\n", rc);
746
747 return rc;
748 }
749
ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)750 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
751 struct ena_com_admin_queue *admin_queue)
752 {
753 unsigned long flags = 0;
754 int ret;
755
756 wait_for_completion_timeout(&comp_ctx->wait_event,
757 usecs_to_jiffies(admin_queue->completion_timeout));
758
759 /* In case the command wasn't completed find out the root cause.
760 * There might be 2 kinds of errors
761 * 1) No completion (timeout reached)
762 * 2) There is completion but the device didn't get any msi-x interrupt.
763 */
764 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
765 spin_lock_irqsave(&admin_queue->q_lock, flags);
766 ena_com_handle_admin_completion(admin_queue);
767 admin_queue->stats.no_completion++;
768 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
769
770 if (comp_ctx->status == ENA_CMD_COMPLETED) {
771 netdev_err(admin_queue->ena_dev->net_device,
772 "The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d)\n",
773 comp_ctx->cmd_opcode);
774 } else {
775 netdev_err(admin_queue->ena_dev->net_device,
776 "The ena device didn't send a completion for the admin cmd %d status %d\n",
777 comp_ctx->cmd_opcode, comp_ctx->status);
778 }
779 admin_queue->running_state = false;
780 ret = -ETIME;
781 goto err;
782 }
783
784 ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status);
785 err:
786 comp_ctxt_release(admin_queue, comp_ctx);
787 return ret;
788 }
789
790 /* This method read the hardware device register through posting writes
791 * and waiting for response
792 * On timeout the function will return ENA_MMIO_READ_TIMEOUT
793 */
ena_com_reg_bar_read32(struct ena_com_dev * ena_dev,u16 offset)794 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
795 {
796 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
797 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
798 mmio_read->read_resp;
799 u32 mmio_read_reg, ret, i;
800 unsigned long flags = 0;
801 u32 timeout = mmio_read->reg_read_to;
802
803 might_sleep();
804
805 if (timeout == 0)
806 timeout = ENA_REG_READ_TIMEOUT;
807
808 /* If readless is disabled, perform regular read */
809 if (!mmio_read->readless_supported)
810 return readl(ena_dev->reg_bar + offset);
811
812 spin_lock_irqsave(&mmio_read->lock, flags);
813 mmio_read->seq_num++;
814
815 read_resp->req_id = mmio_read->seq_num + 0xDEAD;
816 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
817 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
818 mmio_read_reg |= mmio_read->seq_num &
819 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
820
821 writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
822
823 for (i = 0; i < timeout; i++) {
824 if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num)
825 break;
826
827 udelay(1);
828 }
829
830 if (unlikely(i == timeout)) {
831 netdev_err(ena_dev->net_device,
832 "Reading reg failed for timeout. expected: req id[%u] offset[%u] actual: req id[%u] offset[%u]\n",
833 mmio_read->seq_num, offset, read_resp->req_id, read_resp->reg_off);
834 ret = ENA_MMIO_READ_TIMEOUT;
835 goto err;
836 }
837
838 if (read_resp->reg_off != offset) {
839 netdev_err(ena_dev->net_device, "Read failure: wrong offset provided\n");
840 ret = ENA_MMIO_READ_TIMEOUT;
841 } else {
842 ret = read_resp->reg_val;
843 }
844 err:
845 spin_unlock_irqrestore(&mmio_read->lock, flags);
846
847 return ret;
848 }
849
850 /* There are two types to wait for completion.
851 * Polling mode - wait until the completion is available.
852 * Async mode - wait on wait queue until the completion is ready
853 * (or the timeout expired).
854 * It is expected that the IRQ called ena_com_handle_admin_completion
855 * to mark the completions.
856 */
ena_com_wait_and_process_admin_cq(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)857 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
858 struct ena_com_admin_queue *admin_queue)
859 {
860 if (admin_queue->polling)
861 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
862 admin_queue);
863
864 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
865 admin_queue);
866 }
867
ena_com_destroy_io_sq(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq)868 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
869 struct ena_com_io_sq *io_sq)
870 {
871 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
872 struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
873 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
874 u8 direction;
875 int ret;
876
877 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
878
879 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
880 direction = ENA_ADMIN_SQ_DIRECTION_TX;
881 else
882 direction = ENA_ADMIN_SQ_DIRECTION_RX;
883
884 destroy_cmd.sq.sq_identity |= (direction <<
885 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
886 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
887
888 destroy_cmd.sq.sq_idx = io_sq->idx;
889 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
890
891 ret = ena_com_execute_admin_command(admin_queue,
892 (struct ena_admin_aq_entry *)&destroy_cmd,
893 sizeof(destroy_cmd),
894 (struct ena_admin_acq_entry *)&destroy_resp,
895 sizeof(destroy_resp));
896
897 if (unlikely(ret && (ret != -ENODEV)))
898 netdev_err(ena_dev->net_device, "Failed to destroy io sq error: %d\n", ret);
899
900 return ret;
901 }
902
ena_com_io_queue_free(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq,struct ena_com_io_cq * io_cq)903 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
904 struct ena_com_io_sq *io_sq,
905 struct ena_com_io_cq *io_cq)
906 {
907 size_t size;
908
909 if (io_cq->cdesc_addr.virt_addr) {
910 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
911
912 dma_free_coherent(ena_dev->dmadev, size, io_cq->cdesc_addr.virt_addr,
913 io_cq->cdesc_addr.phys_addr);
914
915 io_cq->cdesc_addr.virt_addr = NULL;
916 }
917
918 if (io_sq->desc_addr.virt_addr) {
919 size = io_sq->desc_entry_size * io_sq->q_depth;
920
921 dma_free_coherent(ena_dev->dmadev, size, io_sq->desc_addr.virt_addr,
922 io_sq->desc_addr.phys_addr);
923
924 io_sq->desc_addr.virt_addr = NULL;
925 }
926
927 if (io_sq->bounce_buf_ctrl.base_buffer) {
928 devm_kfree(ena_dev->dmadev, io_sq->bounce_buf_ctrl.base_buffer);
929 io_sq->bounce_buf_ctrl.base_buffer = NULL;
930 }
931 }
932
wait_for_reset_state(struct ena_com_dev * ena_dev,u32 timeout,u16 exp_state)933 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
934 u16 exp_state)
935 {
936 u32 val, exp = 0;
937 unsigned long timeout_stamp;
938
939 /* Convert timeout from resolution of 100ms to us resolution. */
940 timeout_stamp = jiffies + usecs_to_jiffies(100 * 1000 * timeout);
941
942 while (1) {
943 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
944
945 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
946 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n");
947 return -ETIME;
948 }
949
950 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
951 exp_state)
952 return 0;
953
954 if (time_is_before_jiffies(timeout_stamp))
955 return -ETIME;
956
957 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
958 }
959 }
960
ena_com_check_supported_feature_id(struct ena_com_dev * ena_dev,enum ena_admin_aq_feature_id feature_id)961 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
962 enum ena_admin_aq_feature_id feature_id)
963 {
964 u32 feature_mask = 1 << feature_id;
965
966 /* Device attributes is always supported */
967 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
968 !(ena_dev->supported_features & feature_mask))
969 return false;
970
971 return true;
972 }
973
ena_com_get_feature_ex(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * get_resp,enum ena_admin_aq_feature_id feature_id,dma_addr_t control_buf_dma_addr,u32 control_buff_size,u8 feature_ver)974 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
975 struct ena_admin_get_feat_resp *get_resp,
976 enum ena_admin_aq_feature_id feature_id,
977 dma_addr_t control_buf_dma_addr,
978 u32 control_buff_size,
979 u8 feature_ver)
980 {
981 struct ena_com_admin_queue *admin_queue;
982 struct ena_admin_get_feat_cmd get_cmd;
983 int ret;
984
985 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
986 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", feature_id);
987 return -EOPNOTSUPP;
988 }
989
990 memset(&get_cmd, 0x0, sizeof(get_cmd));
991 admin_queue = &ena_dev->admin_queue;
992
993 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
994
995 if (control_buff_size)
996 get_cmd.aq_common_descriptor.flags =
997 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
998 else
999 get_cmd.aq_common_descriptor.flags = 0;
1000
1001 ret = ena_com_mem_addr_set(ena_dev,
1002 &get_cmd.control_buffer.address,
1003 control_buf_dma_addr);
1004 if (unlikely(ret)) {
1005 netdev_err(ena_dev->net_device, "Memory address set failed\n");
1006 return ret;
1007 }
1008
1009 get_cmd.control_buffer.length = control_buff_size;
1010 get_cmd.feat_common.feature_version = feature_ver;
1011 get_cmd.feat_common.feature_id = feature_id;
1012
1013 ret = ena_com_execute_admin_command(admin_queue,
1014 (struct ena_admin_aq_entry *)
1015 &get_cmd,
1016 sizeof(get_cmd),
1017 (struct ena_admin_acq_entry *)
1018 get_resp,
1019 sizeof(*get_resp));
1020
1021 if (unlikely(ret))
1022 netdev_err(ena_dev->net_device,
1023 "Failed to submit get_feature command %d error: %d\n", feature_id, ret);
1024
1025 return ret;
1026 }
1027
ena_com_get_feature(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * get_resp,enum ena_admin_aq_feature_id feature_id,u8 feature_ver)1028 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
1029 struct ena_admin_get_feat_resp *get_resp,
1030 enum ena_admin_aq_feature_id feature_id,
1031 u8 feature_ver)
1032 {
1033 return ena_com_get_feature_ex(ena_dev,
1034 get_resp,
1035 feature_id,
1036 0,
1037 0,
1038 feature_ver);
1039 }
1040
ena_com_get_current_hash_function(struct ena_com_dev * ena_dev)1041 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev)
1042 {
1043 return ena_dev->rss.hash_func;
1044 }
1045
ena_com_hash_key_fill_default_key(struct ena_com_dev * ena_dev)1046 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev)
1047 {
1048 struct ena_admin_feature_rss_flow_hash_control *hash_key =
1049 (ena_dev->rss).hash_key;
1050
1051 netdev_rss_key_fill(&hash_key->key, sizeof(hash_key->key));
1052 /* The key buffer is stored in the device in an array of
1053 * uint32 elements.
1054 */
1055 hash_key->key_parts = ENA_ADMIN_RSS_KEY_PARTS;
1056 }
1057
ena_com_hash_key_allocate(struct ena_com_dev * ena_dev)1058 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
1059 {
1060 struct ena_rss *rss = &ena_dev->rss;
1061
1062 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_FUNCTION))
1063 return -EOPNOTSUPP;
1064
1065 rss->hash_key = dma_alloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_key),
1066 &rss->hash_key_dma_addr, GFP_KERNEL);
1067
1068 if (unlikely(!rss->hash_key))
1069 return -ENOMEM;
1070
1071 return 0;
1072 }
1073
ena_com_hash_key_destroy(struct ena_com_dev * ena_dev)1074 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
1075 {
1076 struct ena_rss *rss = &ena_dev->rss;
1077
1078 if (rss->hash_key)
1079 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), rss->hash_key,
1080 rss->hash_key_dma_addr);
1081 rss->hash_key = NULL;
1082 }
1083
ena_com_hash_ctrl_init(struct ena_com_dev * ena_dev)1084 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
1085 {
1086 struct ena_rss *rss = &ena_dev->rss;
1087
1088 rss->hash_ctrl = dma_alloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl),
1089 &rss->hash_ctrl_dma_addr, GFP_KERNEL);
1090
1091 if (unlikely(!rss->hash_ctrl))
1092 return -ENOMEM;
1093
1094 return 0;
1095 }
1096
ena_com_hash_ctrl_destroy(struct ena_com_dev * ena_dev)1097 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
1098 {
1099 struct ena_rss *rss = &ena_dev->rss;
1100
1101 if (rss->hash_ctrl)
1102 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), rss->hash_ctrl,
1103 rss->hash_ctrl_dma_addr);
1104 rss->hash_ctrl = NULL;
1105 }
1106
ena_com_indirect_table_allocate(struct ena_com_dev * ena_dev,u16 log_size)1107 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
1108 u16 log_size)
1109 {
1110 struct ena_rss *rss = &ena_dev->rss;
1111 struct ena_admin_get_feat_resp get_resp;
1112 size_t tbl_size;
1113 int ret;
1114
1115 ret = ena_com_get_feature(ena_dev, &get_resp,
1116 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG, 0);
1117 if (unlikely(ret))
1118 return ret;
1119
1120 if ((get_resp.u.ind_table.min_size > log_size) ||
1121 (get_resp.u.ind_table.max_size < log_size)) {
1122 netdev_err(ena_dev->net_device,
1123 "Indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
1124 1 << log_size, 1 << get_resp.u.ind_table.min_size,
1125 1 << get_resp.u.ind_table.max_size);
1126 return -EINVAL;
1127 }
1128
1129 tbl_size = (1ULL << log_size) *
1130 sizeof(struct ena_admin_rss_ind_table_entry);
1131
1132 rss->rss_ind_tbl = dma_alloc_coherent(ena_dev->dmadev, tbl_size, &rss->rss_ind_tbl_dma_addr,
1133 GFP_KERNEL);
1134 if (unlikely(!rss->rss_ind_tbl))
1135 goto mem_err1;
1136
1137 tbl_size = (1ULL << log_size) * sizeof(u16);
1138 rss->host_rss_ind_tbl = devm_kzalloc(ena_dev->dmadev, tbl_size, GFP_KERNEL);
1139 if (unlikely(!rss->host_rss_ind_tbl))
1140 goto mem_err2;
1141
1142 rss->tbl_log_size = log_size;
1143
1144 return 0;
1145
1146 mem_err2:
1147 tbl_size = (1ULL << log_size) *
1148 sizeof(struct ena_admin_rss_ind_table_entry);
1149
1150 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, rss->rss_ind_tbl_dma_addr);
1151 rss->rss_ind_tbl = NULL;
1152 mem_err1:
1153 rss->tbl_log_size = 0;
1154 return -ENOMEM;
1155 }
1156
ena_com_indirect_table_destroy(struct ena_com_dev * ena_dev)1157 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
1158 {
1159 struct ena_rss *rss = &ena_dev->rss;
1160 size_t tbl_size = (1ULL << rss->tbl_log_size) *
1161 sizeof(struct ena_admin_rss_ind_table_entry);
1162
1163 if (rss->rss_ind_tbl)
1164 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl,
1165 rss->rss_ind_tbl_dma_addr);
1166 rss->rss_ind_tbl = NULL;
1167
1168 if (rss->host_rss_ind_tbl)
1169 devm_kfree(ena_dev->dmadev, rss->host_rss_ind_tbl);
1170 rss->host_rss_ind_tbl = NULL;
1171 }
1172
ena_com_create_io_sq(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq,u16 cq_idx)1173 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1174 struct ena_com_io_sq *io_sq, u16 cq_idx)
1175 {
1176 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1177 struct ena_admin_aq_create_sq_cmd create_cmd;
1178 struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1179 u8 direction;
1180 int ret;
1181
1182 memset(&create_cmd, 0x0, sizeof(create_cmd));
1183
1184 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1185
1186 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1187 direction = ENA_ADMIN_SQ_DIRECTION_TX;
1188 else
1189 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1190
1191 create_cmd.sq_identity |= (direction <<
1192 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1193 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1194
1195 create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1196 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1197
1198 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1199 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1200 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1201
1202 create_cmd.sq_caps_3 |=
1203 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1204
1205 create_cmd.cq_idx = cq_idx;
1206 create_cmd.sq_depth = io_sq->q_depth;
1207
1208 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1209 ret = ena_com_mem_addr_set(ena_dev,
1210 &create_cmd.sq_ba,
1211 io_sq->desc_addr.phys_addr);
1212 if (unlikely(ret)) {
1213 netdev_err(ena_dev->net_device, "Memory address set failed\n");
1214 return ret;
1215 }
1216 }
1217
1218 ret = ena_com_execute_admin_command(admin_queue,
1219 (struct ena_admin_aq_entry *)&create_cmd,
1220 sizeof(create_cmd),
1221 (struct ena_admin_acq_entry *)&cmd_completion,
1222 sizeof(cmd_completion));
1223 if (unlikely(ret)) {
1224 netdev_err(ena_dev->net_device, "Failed to create IO SQ. error: %d\n", ret);
1225 return ret;
1226 }
1227
1228 io_sq->idx = cmd_completion.sq_idx;
1229
1230 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1231 (uintptr_t)cmd_completion.sq_doorbell_offset);
1232
1233 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1234 io_sq->desc_addr.pbuf_dev_addr =
1235 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1236 cmd_completion.llq_descriptors_offset);
1237 }
1238
1239 netdev_dbg(ena_dev->net_device, "Created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1240
1241 return ret;
1242 }
1243
ena_com_ind_tbl_convert_to_device(struct ena_com_dev * ena_dev)1244 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1245 {
1246 struct ena_rss *rss = &ena_dev->rss;
1247 struct ena_com_io_sq *io_sq;
1248 u16 qid;
1249 int i;
1250
1251 for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1252 qid = rss->host_rss_ind_tbl[i];
1253 if (qid >= ENA_TOTAL_NUM_QUEUES)
1254 return -EINVAL;
1255
1256 io_sq = &ena_dev->io_sq_queues[qid];
1257
1258 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1259 return -EINVAL;
1260
1261 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1262 }
1263
1264 return 0;
1265 }
1266
ena_com_update_intr_delay_resolution(struct ena_com_dev * ena_dev,u16 intr_delay_resolution)1267 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1268 u16 intr_delay_resolution)
1269 {
1270 u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution;
1271
1272 if (unlikely(!intr_delay_resolution)) {
1273 netdev_err(ena_dev->net_device,
1274 "Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1275 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;
1276 }
1277
1278 /* update Rx */
1279 ena_dev->intr_moder_rx_interval =
1280 ena_dev->intr_moder_rx_interval *
1281 prev_intr_delay_resolution /
1282 intr_delay_resolution;
1283
1284 /* update Tx */
1285 ena_dev->intr_moder_tx_interval =
1286 ena_dev->intr_moder_tx_interval *
1287 prev_intr_delay_resolution /
1288 intr_delay_resolution;
1289
1290 ena_dev->intr_delay_resolution = intr_delay_resolution;
1291 }
1292
1293 /*****************************************************************************/
1294 /******************************* API ******************************/
1295 /*****************************************************************************/
1296
ena_com_execute_admin_command(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size,struct ena_admin_acq_entry * comp,size_t comp_size)1297 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1298 struct ena_admin_aq_entry *cmd,
1299 size_t cmd_size,
1300 struct ena_admin_acq_entry *comp,
1301 size_t comp_size)
1302 {
1303 struct ena_comp_ctx *comp_ctx;
1304 int ret;
1305
1306 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1307 comp, comp_size);
1308 if (IS_ERR(comp_ctx)) {
1309 ret = PTR_ERR(comp_ctx);
1310 if (ret == -ENODEV)
1311 netdev_dbg(admin_queue->ena_dev->net_device,
1312 "Failed to submit command [%d]\n", ret);
1313 else
1314 netdev_err(admin_queue->ena_dev->net_device,
1315 "Failed to submit command [%d]\n", ret);
1316
1317 return ret;
1318 }
1319
1320 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1321 if (unlikely(ret)) {
1322 if (admin_queue->running_state)
1323 netdev_err(admin_queue->ena_dev->net_device,
1324 "Failed to process command. ret = %d\n", ret);
1325 else
1326 netdev_dbg(admin_queue->ena_dev->net_device,
1327 "Failed to process command. ret = %d\n", ret);
1328 }
1329 return ret;
1330 }
1331
ena_com_create_io_cq(struct ena_com_dev * ena_dev,struct ena_com_io_cq * io_cq)1332 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1333 struct ena_com_io_cq *io_cq)
1334 {
1335 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1336 struct ena_admin_aq_create_cq_cmd create_cmd;
1337 struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1338 int ret;
1339
1340 memset(&create_cmd, 0x0, sizeof(create_cmd));
1341
1342 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1343
1344 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1345 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1346 create_cmd.cq_caps_1 |=
1347 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1348
1349 create_cmd.msix_vector = io_cq->msix_vector;
1350 create_cmd.cq_depth = io_cq->q_depth;
1351
1352 ret = ena_com_mem_addr_set(ena_dev,
1353 &create_cmd.cq_ba,
1354 io_cq->cdesc_addr.phys_addr);
1355 if (unlikely(ret)) {
1356 netdev_err(ena_dev->net_device, "Memory address set failed\n");
1357 return ret;
1358 }
1359
1360 ret = ena_com_execute_admin_command(admin_queue,
1361 (struct ena_admin_aq_entry *)&create_cmd,
1362 sizeof(create_cmd),
1363 (struct ena_admin_acq_entry *)&cmd_completion,
1364 sizeof(cmd_completion));
1365 if (unlikely(ret)) {
1366 netdev_err(ena_dev->net_device, "Failed to create IO CQ. error: %d\n", ret);
1367 return ret;
1368 }
1369
1370 io_cq->idx = cmd_completion.cq_idx;
1371
1372 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1373 cmd_completion.cq_interrupt_unmask_register_offset);
1374
1375 if (cmd_completion.numa_node_register_offset)
1376 io_cq->numa_node_cfg_reg =
1377 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1378 cmd_completion.numa_node_register_offset);
1379
1380 netdev_dbg(ena_dev->net_device, "Created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1381
1382 return ret;
1383 }
1384
ena_com_get_io_handlers(struct ena_com_dev * ena_dev,u16 qid,struct ena_com_io_sq ** io_sq,struct ena_com_io_cq ** io_cq)1385 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1386 struct ena_com_io_sq **io_sq,
1387 struct ena_com_io_cq **io_cq)
1388 {
1389 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1390 netdev_err(ena_dev->net_device, "Invalid queue number %d but the max is %d\n", qid,
1391 ENA_TOTAL_NUM_QUEUES);
1392 return -EINVAL;
1393 }
1394
1395 *io_sq = &ena_dev->io_sq_queues[qid];
1396 *io_cq = &ena_dev->io_cq_queues[qid];
1397
1398 return 0;
1399 }
1400
ena_com_abort_admin_commands(struct ena_com_dev * ena_dev)1401 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1402 {
1403 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1404 struct ena_comp_ctx *comp_ctx;
1405 u16 i;
1406
1407 if (!admin_queue->comp_ctx)
1408 return;
1409
1410 for (i = 0; i < admin_queue->q_depth; i++) {
1411 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1412 if (unlikely(!comp_ctx))
1413 break;
1414
1415 comp_ctx->status = ENA_CMD_ABORTED;
1416
1417 complete(&comp_ctx->wait_event);
1418 }
1419 }
1420
ena_com_wait_for_abort_completion(struct ena_com_dev * ena_dev)1421 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1422 {
1423 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1424 unsigned long flags = 0;
1425 u32 exp = 0;
1426
1427 spin_lock_irqsave(&admin_queue->q_lock, flags);
1428 while (atomic_read(&admin_queue->outstanding_cmds) != 0) {
1429 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1430 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
1431 spin_lock_irqsave(&admin_queue->q_lock, flags);
1432 }
1433 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1434 }
1435
ena_com_destroy_io_cq(struct ena_com_dev * ena_dev,struct ena_com_io_cq * io_cq)1436 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1437 struct ena_com_io_cq *io_cq)
1438 {
1439 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1440 struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1441 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1442 int ret;
1443
1444 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1445
1446 destroy_cmd.cq_idx = io_cq->idx;
1447 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1448
1449 ret = ena_com_execute_admin_command(admin_queue,
1450 (struct ena_admin_aq_entry *)&destroy_cmd,
1451 sizeof(destroy_cmd),
1452 (struct ena_admin_acq_entry *)&destroy_resp,
1453 sizeof(destroy_resp));
1454
1455 if (unlikely(ret && (ret != -ENODEV)))
1456 netdev_err(ena_dev->net_device, "Failed to destroy IO CQ. error: %d\n", ret);
1457
1458 return ret;
1459 }
1460
ena_com_get_admin_running_state(struct ena_com_dev * ena_dev)1461 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1462 {
1463 return ena_dev->admin_queue.running_state;
1464 }
1465
ena_com_set_admin_running_state(struct ena_com_dev * ena_dev,bool state)1466 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1467 {
1468 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1469 unsigned long flags = 0;
1470
1471 spin_lock_irqsave(&admin_queue->q_lock, flags);
1472 ena_dev->admin_queue.running_state = state;
1473 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1474 }
1475
ena_com_admin_aenq_enable(struct ena_com_dev * ena_dev)1476 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1477 {
1478 u16 depth = ena_dev->aenq.q_depth;
1479
1480 WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1481
1482 /* Init head_db to mark that all entries in the queue
1483 * are initially available
1484 */
1485 writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1486 }
1487
ena_com_set_aenq_config(struct ena_com_dev * ena_dev,u32 groups_flag)1488 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1489 {
1490 struct ena_com_admin_queue *admin_queue;
1491 struct ena_admin_set_feat_cmd cmd;
1492 struct ena_admin_set_feat_resp resp;
1493 struct ena_admin_get_feat_resp get_resp;
1494 int ret;
1495
1496 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0);
1497 if (ret) {
1498 dev_info(ena_dev->dmadev, "Can't get aenq configuration\n");
1499 return ret;
1500 }
1501
1502 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1503 netdev_warn(ena_dev->net_device,
1504 "Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n",
1505 get_resp.u.aenq.supported_groups, groups_flag);
1506 return -EOPNOTSUPP;
1507 }
1508
1509 memset(&cmd, 0x0, sizeof(cmd));
1510 admin_queue = &ena_dev->admin_queue;
1511
1512 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1513 cmd.aq_common_descriptor.flags = 0;
1514 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1515 cmd.u.aenq.enabled_groups = groups_flag;
1516
1517 ret = ena_com_execute_admin_command(admin_queue,
1518 (struct ena_admin_aq_entry *)&cmd,
1519 sizeof(cmd),
1520 (struct ena_admin_acq_entry *)&resp,
1521 sizeof(resp));
1522
1523 if (unlikely(ret))
1524 netdev_err(ena_dev->net_device, "Failed to config AENQ ret: %d\n", ret);
1525
1526 return ret;
1527 }
1528
ena_com_get_dma_width(struct ena_com_dev * ena_dev)1529 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1530 {
1531 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1532 u32 width;
1533
1534 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1535 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n");
1536 return -ETIME;
1537 }
1538
1539 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1540 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1541
1542 netdev_dbg(ena_dev->net_device, "ENA dma width: %d\n", width);
1543
1544 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1545 netdev_err(ena_dev->net_device, "DMA width illegal value: %d\n", width);
1546 return -EINVAL;
1547 }
1548
1549 ena_dev->dma_addr_bits = width;
1550
1551 return width;
1552 }
1553
ena_com_validate_version(struct ena_com_dev * ena_dev)1554 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1555 {
1556 u32 ver;
1557 u32 ctrl_ver;
1558 u32 ctrl_ver_masked;
1559
1560 /* Make sure the ENA version and the controller version are at least
1561 * as the driver expects
1562 */
1563 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1564 ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1565 ENA_REGS_CONTROLLER_VERSION_OFF);
1566
1567 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) || (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1568 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n");
1569 return -ETIME;
1570 }
1571
1572 dev_info(ena_dev->dmadev, "ENA device version: %d.%d\n",
1573 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >> ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1574 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1575
1576 dev_info(ena_dev->dmadev, "ENA controller version: %d.%d.%d implementation version %d\n",
1577 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >>
1578 ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1579 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >>
1580 ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1581 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1582 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1583 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1584
1585 ctrl_ver_masked =
1586 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1587 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1588 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1589
1590 /* Validate the ctrl version without the implementation ID */
1591 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1592 netdev_err(ena_dev->net_device,
1593 "ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1594 return -1;
1595 }
1596
1597 return 0;
1598 }
1599
1600 static void
ena_com_free_ena_admin_queue_comp_ctx(struct ena_com_dev * ena_dev,struct ena_com_admin_queue * admin_queue)1601 ena_com_free_ena_admin_queue_comp_ctx(struct ena_com_dev *ena_dev,
1602 struct ena_com_admin_queue *admin_queue)
1603
1604 {
1605 if (!admin_queue->comp_ctx)
1606 return;
1607
1608 devm_kfree(ena_dev->dmadev, admin_queue->comp_ctx);
1609
1610 admin_queue->comp_ctx = NULL;
1611 }
1612
ena_com_admin_destroy(struct ena_com_dev * ena_dev)1613 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1614 {
1615 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1616 struct ena_com_admin_cq *cq = &admin_queue->cq;
1617 struct ena_com_admin_sq *sq = &admin_queue->sq;
1618 struct ena_com_aenq *aenq = &ena_dev->aenq;
1619 u16 size;
1620
1621 ena_com_free_ena_admin_queue_comp_ctx(ena_dev, admin_queue);
1622
1623 size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1624 if (sq->entries)
1625 dma_free_coherent(ena_dev->dmadev, size, sq->entries, sq->dma_addr);
1626 sq->entries = NULL;
1627
1628 size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1629 if (cq->entries)
1630 dma_free_coherent(ena_dev->dmadev, size, cq->entries, cq->dma_addr);
1631 cq->entries = NULL;
1632
1633 size = ADMIN_AENQ_SIZE(aenq->q_depth);
1634 if (ena_dev->aenq.entries)
1635 dma_free_coherent(ena_dev->dmadev, size, aenq->entries, aenq->dma_addr);
1636 aenq->entries = NULL;
1637 }
1638
ena_com_set_admin_polling_mode(struct ena_com_dev * ena_dev,bool polling)1639 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1640 {
1641 u32 mask_value = 0;
1642
1643 if (polling)
1644 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1645
1646 writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1647 ena_dev->admin_queue.polling = polling;
1648 }
1649
ena_com_phc_supported(struct ena_com_dev * ena_dev)1650 bool ena_com_phc_supported(struct ena_com_dev *ena_dev)
1651 {
1652 return ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_PHC_CONFIG);
1653 }
1654
ena_com_phc_init(struct ena_com_dev * ena_dev)1655 int ena_com_phc_init(struct ena_com_dev *ena_dev)
1656 {
1657 struct ena_com_phc_info *phc = &ena_dev->phc;
1658
1659 memset(phc, 0x0, sizeof(*phc));
1660
1661 /* Allocate shared mem used PHC timestamp retrieved from device */
1662 phc->virt_addr = dma_alloc_coherent(ena_dev->dmadev,
1663 sizeof(*phc->virt_addr),
1664 &phc->phys_addr,
1665 GFP_KERNEL);
1666 if (unlikely(!phc->virt_addr))
1667 return -ENOMEM;
1668
1669 spin_lock_init(&phc->lock);
1670
1671 phc->virt_addr->req_id = 0;
1672 phc->virt_addr->timestamp = 0;
1673
1674 return 0;
1675 }
1676
ena_com_phc_config(struct ena_com_dev * ena_dev)1677 int ena_com_phc_config(struct ena_com_dev *ena_dev)
1678 {
1679 struct ena_com_phc_info *phc = &ena_dev->phc;
1680 struct ena_admin_get_feat_resp get_feat_resp;
1681 struct ena_admin_set_feat_resp set_feat_resp;
1682 struct ena_admin_set_feat_cmd set_feat_cmd;
1683 int ret = 0;
1684
1685 /* Get device PHC default configuration */
1686 ret = ena_com_get_feature(ena_dev,
1687 &get_feat_resp,
1688 ENA_ADMIN_PHC_CONFIG,
1689 0);
1690 if (unlikely(ret)) {
1691 netdev_err(ena_dev->net_device,
1692 "Failed to get PHC feature configuration, error: %d\n",
1693 ret);
1694 return ret;
1695 }
1696
1697 /* Supporting only readless PHC retrieval */
1698 if (get_feat_resp.u.phc.type != ENA_ADMIN_PHC_TYPE_READLESS) {
1699 netdev_err(ena_dev->net_device,
1700 "Unsupported PHC type, error: %d\n",
1701 -EOPNOTSUPP);
1702 return -EOPNOTSUPP;
1703 }
1704
1705 /* Update PHC doorbell offset according to device value,
1706 * used to write req_id to PHC bar
1707 */
1708 phc->doorbell_offset = get_feat_resp.u.phc.doorbell_offset;
1709
1710 /* Update PHC expire timeout according to device
1711 * or default driver value
1712 */
1713 phc->expire_timeout_usec = (get_feat_resp.u.phc.expire_timeout_usec) ?
1714 get_feat_resp.u.phc.expire_timeout_usec :
1715 ENA_PHC_DEFAULT_EXPIRE_TIMEOUT_USEC;
1716
1717 /* Update PHC block timeout according to device
1718 * or default driver value
1719 */
1720 phc->block_timeout_usec = (get_feat_resp.u.phc.block_timeout_usec) ?
1721 get_feat_resp.u.phc.block_timeout_usec :
1722 ENA_PHC_DEFAULT_BLOCK_TIMEOUT_USEC;
1723
1724 /* Sanity check - expire timeout must not exceed block timeout */
1725 if (phc->expire_timeout_usec > phc->block_timeout_usec)
1726 phc->expire_timeout_usec = phc->block_timeout_usec;
1727
1728 /* Prepare PHC feature command */
1729 memset(&set_feat_cmd, 0x0, sizeof(set_feat_cmd));
1730 set_feat_cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1731 set_feat_cmd.feat_common.feature_id = ENA_ADMIN_PHC_CONFIG;
1732 set_feat_cmd.u.phc.output_length = sizeof(*phc->virt_addr);
1733 ret = ena_com_mem_addr_set(ena_dev,
1734 &set_feat_cmd.u.phc.output_address,
1735 phc->phys_addr);
1736 if (unlikely(ret)) {
1737 netdev_err(ena_dev->net_device,
1738 "Failed setting PHC output address, error: %d\n",
1739 ret);
1740 return ret;
1741 }
1742
1743 /* Send PHC feature command to the device */
1744 ret = ena_com_execute_admin_command(&ena_dev->admin_queue,
1745 (struct ena_admin_aq_entry *)&set_feat_cmd,
1746 sizeof(set_feat_cmd),
1747 (struct ena_admin_acq_entry *)&set_feat_resp,
1748 sizeof(set_feat_resp));
1749
1750 if (unlikely(ret)) {
1751 netdev_err(ena_dev->net_device,
1752 "Failed to enable PHC, error: %d\n",
1753 ret);
1754 return ret;
1755 }
1756
1757 phc->active = true;
1758 netdev_dbg(ena_dev->net_device, "PHC is active in the device\n");
1759
1760 return ret;
1761 }
1762
ena_com_phc_destroy(struct ena_com_dev * ena_dev)1763 void ena_com_phc_destroy(struct ena_com_dev *ena_dev)
1764 {
1765 struct ena_com_phc_info *phc = &ena_dev->phc;
1766 unsigned long flags = 0;
1767
1768 /* In case PHC is not supported by the device, silently exiting */
1769 if (!phc->virt_addr)
1770 return;
1771
1772 spin_lock_irqsave(&phc->lock, flags);
1773 phc->active = false;
1774 spin_unlock_irqrestore(&phc->lock, flags);
1775
1776 dma_free_coherent(ena_dev->dmadev,
1777 sizeof(*phc->virt_addr),
1778 phc->virt_addr,
1779 phc->phys_addr);
1780 phc->virt_addr = NULL;
1781 }
1782
ena_com_phc_get_timestamp(struct ena_com_dev * ena_dev,u64 * timestamp)1783 int ena_com_phc_get_timestamp(struct ena_com_dev *ena_dev, u64 *timestamp)
1784 {
1785 const ktime_t zero_system_time = ktime_set(0, 0);
1786 struct ena_com_phc_info *phc = &ena_dev->phc;
1787 volatile struct ena_admin_phc_resp *resp;
1788 ktime_t expire_time;
1789 ktime_t block_time;
1790 unsigned long flags = 0;
1791 int ret = 0;
1792
1793 spin_lock_irqsave(&phc->lock, flags);
1794
1795 if (!phc->active) {
1796 spin_unlock_irqrestore(&phc->lock, flags);
1797 netdev_err(ena_dev->net_device, "PHC feature is not active in the device\n");
1798 return -EOPNOTSUPP;
1799 }
1800
1801 resp = ena_dev->phc.virt_addr;
1802
1803 /* Check if PHC is in blocked state */
1804 if (unlikely(ktime_compare(phc->system_time, zero_system_time))) {
1805 /* Check if blocking time expired */
1806 block_time = ktime_add_us(phc->system_time, phc->block_timeout_usec);
1807 if (!ktime_after(ktime_get(), block_time)) {
1808 /* PHC is still in blocked state, skip PHC request */
1809 phc->stats.phc_skp++;
1810 ret = -EBUSY;
1811 goto skip;
1812 }
1813
1814 /* PHC is in active state, update statistics according
1815 * to req_id and error_flags
1816 */
1817 if (READ_ONCE(resp->req_id) != phc->req_id) {
1818 /* Device didn't update req_id during blocking time,
1819 * this indicates on a device error
1820 */
1821 netdev_err(ena_dev->net_device,
1822 "PHC get time request 0x%x failed (device error)\n",
1823 phc->req_id);
1824 phc->stats.phc_err_dv++;
1825 } else if (resp->error_flags & ENA_PHC_ERROR_FLAGS) {
1826 /* Device updated req_id during blocking time but got
1827 * a PHC error, this occurs if device:
1828 * - exceeded the get time request limit
1829 * - received an invalid timestamp
1830 */
1831 netdev_err(ena_dev->net_device,
1832 "PHC get time request 0x%x failed (error 0x%x)\n",
1833 phc->req_id,
1834 resp->error_flags);
1835 phc->stats.phc_err_ts += !!(resp->error_flags &
1836 ENA_ADMIN_PHC_ERROR_FLAG_TIMESTAMP);
1837 } else {
1838 /* Device updated req_id during blocking time
1839 * with valid timestamp
1840 */
1841 phc->stats.phc_exp++;
1842 }
1843 }
1844
1845 /* Setting relative timeouts */
1846 phc->system_time = ktime_get();
1847 block_time = ktime_add_us(phc->system_time, phc->block_timeout_usec);
1848 expire_time = ktime_add_us(phc->system_time, phc->expire_timeout_usec);
1849
1850 /* We expect the device to return this req_id once
1851 * the new PHC timestamp is updated
1852 */
1853 phc->req_id++;
1854
1855 /* Initialize PHC shared memory with different req_id value
1856 * to be able to identify once the device changes it to req_id
1857 */
1858 resp->req_id = phc->req_id + ENA_PHC_REQ_ID_OFFSET;
1859
1860 /* Writing req_id to PHC bar */
1861 writel(phc->req_id, ena_dev->reg_bar + phc->doorbell_offset);
1862
1863 /* Stalling until the device updates req_id */
1864 while (1) {
1865 if (unlikely(ktime_after(ktime_get(), expire_time))) {
1866 /* Gave up waiting for updated req_id, PHC enters into
1867 * blocked state until passing blocking time,
1868 * during this time any get PHC timestamp will fail with
1869 * device busy error
1870 */
1871 ret = -EBUSY;
1872 break;
1873 }
1874
1875 /* Check if req_id was updated by the device */
1876 if (READ_ONCE(resp->req_id) != phc->req_id) {
1877 /* req_id was not updated by the device yet,
1878 * check again on next loop
1879 */
1880 continue;
1881 }
1882
1883 /* req_id was updated by the device which indicates that
1884 * PHC timestamp and error_flags are updated too,
1885 * checking errors before retrieving timestamp
1886 */
1887 if (unlikely(resp->error_flags & ENA_PHC_ERROR_FLAGS)) {
1888 /* Retrieved invalid PHC timestamp, PHC enters into
1889 * blocked state until passing blocking time,
1890 * during this time any get PHC timestamp requests
1891 * will fail with device busy error
1892 */
1893 ret = -EBUSY;
1894 break;
1895 }
1896
1897 /* PHC timestamp value is returned to the caller */
1898 *timestamp = resp->timestamp;
1899
1900 /* Update statistic on valid PHC timestamp retrieval */
1901 phc->stats.phc_cnt++;
1902
1903 /* This indicates PHC state is active */
1904 phc->system_time = zero_system_time;
1905 break;
1906 }
1907
1908 skip:
1909 spin_unlock_irqrestore(&phc->lock, flags);
1910
1911 return ret;
1912 }
1913
ena_com_mmio_reg_read_request_init(struct ena_com_dev * ena_dev)1914 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1915 {
1916 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1917
1918 spin_lock_init(&mmio_read->lock);
1919 mmio_read->read_resp = dma_alloc_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp),
1920 &mmio_read->read_resp_dma_addr, GFP_KERNEL);
1921 if (unlikely(!mmio_read->read_resp))
1922 goto err;
1923
1924 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1925
1926 mmio_read->read_resp->req_id = 0x0;
1927 mmio_read->seq_num = 0x0;
1928 mmio_read->readless_supported = true;
1929
1930 return 0;
1931
1932 err:
1933
1934 return -ENOMEM;
1935 }
1936
ena_com_set_mmio_read_mode(struct ena_com_dev * ena_dev,bool readless_supported)1937 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1938 {
1939 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1940
1941 mmio_read->readless_supported = readless_supported;
1942 }
1943
ena_com_mmio_reg_read_request_destroy(struct ena_com_dev * ena_dev)1944 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1945 {
1946 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1947
1948 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1949 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1950
1951 dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp), mmio_read->read_resp,
1952 mmio_read->read_resp_dma_addr);
1953
1954 mmio_read->read_resp = NULL;
1955 }
1956
ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev * ena_dev)1957 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1958 {
1959 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1960 u32 addr_low, addr_high;
1961
1962 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1963 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1964
1965 writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1966 writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1967 }
1968
ena_com_admin_init(struct ena_com_dev * ena_dev,struct ena_aenq_handlers * aenq_handlers)1969 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1970 struct ena_aenq_handlers *aenq_handlers)
1971 {
1972 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1973 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1974 int ret;
1975
1976 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1977
1978 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1979 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n");
1980 return -ETIME;
1981 }
1982
1983 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1984 netdev_err(ena_dev->net_device, "Device isn't ready, abort com init\n");
1985 return -ENODEV;
1986 }
1987
1988 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1989
1990 admin_queue->q_dmadev = ena_dev->dmadev;
1991 admin_queue->polling = false;
1992 admin_queue->curr_cmd_id = 0;
1993
1994 atomic_set(&admin_queue->outstanding_cmds, 0);
1995
1996 spin_lock_init(&admin_queue->q_lock);
1997
1998 ret = ena_com_init_comp_ctxt(admin_queue);
1999 if (ret)
2000 goto error;
2001
2002 ret = ena_com_admin_init_sq(admin_queue);
2003 if (ret)
2004 goto error;
2005
2006 ret = ena_com_admin_init_cq(admin_queue);
2007 if (ret)
2008 goto error;
2009
2010 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
2011 ENA_REGS_AQ_DB_OFF);
2012
2013 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
2014 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
2015
2016 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
2017 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
2018
2019 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
2020 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
2021
2022 writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
2023 writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
2024
2025 aq_caps = 0;
2026 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
2027 aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
2028 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
2029 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
2030
2031 acq_caps = 0;
2032 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
2033 acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
2034 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
2035 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
2036
2037 writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
2038 writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
2039 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
2040 if (ret)
2041 goto error;
2042
2043 admin_queue->ena_dev = ena_dev;
2044 admin_queue->running_state = true;
2045
2046 return 0;
2047 error:
2048 ena_com_admin_destroy(ena_dev);
2049
2050 return ret;
2051 }
2052
ena_com_create_io_queue(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx)2053 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
2054 struct ena_com_create_io_ctx *ctx)
2055 {
2056 struct ena_com_io_sq *io_sq;
2057 struct ena_com_io_cq *io_cq;
2058 int ret;
2059
2060 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
2061 netdev_err(ena_dev->net_device, "Qid (%d) is bigger than max num of queues (%d)\n",
2062 ctx->qid, ENA_TOTAL_NUM_QUEUES);
2063 return -EINVAL;
2064 }
2065
2066 io_sq = &ena_dev->io_sq_queues[ctx->qid];
2067 io_cq = &ena_dev->io_cq_queues[ctx->qid];
2068
2069 memset(io_sq, 0x0, sizeof(*io_sq));
2070 memset(io_cq, 0x0, sizeof(*io_cq));
2071
2072 /* Init CQ */
2073 io_cq->q_depth = ctx->queue_size;
2074 io_cq->direction = ctx->direction;
2075 io_cq->qid = ctx->qid;
2076
2077 io_cq->msix_vector = ctx->msix_vector;
2078
2079 io_sq->q_depth = ctx->queue_size;
2080 io_sq->direction = ctx->direction;
2081 io_sq->qid = ctx->qid;
2082
2083 io_sq->mem_queue_type = ctx->mem_queue_type;
2084
2085 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
2086 /* header length is limited to 8 bits */
2087 io_sq->tx_max_header_size = min_t(u32, ena_dev->tx_max_header_size, SZ_256);
2088
2089 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
2090 if (ret)
2091 goto error;
2092 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
2093 if (ret)
2094 goto error;
2095
2096 ret = ena_com_create_io_cq(ena_dev, io_cq);
2097 if (ret)
2098 goto error;
2099
2100 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
2101 if (ret)
2102 goto destroy_io_cq;
2103
2104 return 0;
2105
2106 destroy_io_cq:
2107 ena_com_destroy_io_cq(ena_dev, io_cq);
2108 error:
2109 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
2110 return ret;
2111 }
2112
ena_com_destroy_io_queue(struct ena_com_dev * ena_dev,u16 qid)2113 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
2114 {
2115 struct ena_com_io_sq *io_sq;
2116 struct ena_com_io_cq *io_cq;
2117
2118 if (qid >= ENA_TOTAL_NUM_QUEUES) {
2119 netdev_err(ena_dev->net_device, "Qid (%d) is bigger than max num of queues (%d)\n",
2120 qid, ENA_TOTAL_NUM_QUEUES);
2121 return;
2122 }
2123
2124 io_sq = &ena_dev->io_sq_queues[qid];
2125 io_cq = &ena_dev->io_cq_queues[qid];
2126
2127 ena_com_destroy_io_sq(ena_dev, io_sq);
2128 ena_com_destroy_io_cq(ena_dev, io_cq);
2129
2130 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
2131 }
2132
ena_com_get_link_params(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * resp)2133 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
2134 struct ena_admin_get_feat_resp *resp)
2135 {
2136 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0);
2137 }
2138
ena_get_dev_stats(struct ena_com_dev * ena_dev,struct ena_com_stats_ctx * ctx,enum ena_admin_get_stats_type type)2139 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
2140 struct ena_com_stats_ctx *ctx,
2141 enum ena_admin_get_stats_type type)
2142 {
2143 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
2144 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
2145 struct ena_com_admin_queue *admin_queue;
2146 int ret;
2147
2148 admin_queue = &ena_dev->admin_queue;
2149
2150 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
2151 get_cmd->aq_common_descriptor.flags = 0;
2152 get_cmd->type = type;
2153
2154 ret = ena_com_execute_admin_command(admin_queue,
2155 (struct ena_admin_aq_entry *)get_cmd,
2156 sizeof(*get_cmd),
2157 (struct ena_admin_acq_entry *)get_resp,
2158 sizeof(*get_resp));
2159
2160 if (unlikely(ret))
2161 netdev_err(ena_dev->net_device, "Failed to get stats. error: %d\n", ret);
2162
2163 return ret;
2164 }
2165
ena_com_set_supported_customer_metrics(struct ena_com_dev * ena_dev)2166 static void ena_com_set_supported_customer_metrics(struct ena_com_dev *ena_dev)
2167 {
2168 struct ena_customer_metrics *customer_metrics;
2169 struct ena_com_stats_ctx ctx;
2170 int ret;
2171
2172 customer_metrics = &ena_dev->customer_metrics;
2173 if (!ena_com_get_cap(ena_dev, ENA_ADMIN_CUSTOMER_METRICS)) {
2174 customer_metrics->supported_metrics = ENA_ADMIN_CUSTOMER_METRICS_MIN_SUPPORT_MASK;
2175 return;
2176 }
2177
2178 memset(&ctx, 0x0, sizeof(ctx));
2179 ctx.get_cmd.requested_metrics = ENA_ADMIN_CUSTOMER_METRICS_SUPPORT_MASK;
2180 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_CUSTOMER_METRICS);
2181 if (likely(ret == 0))
2182 customer_metrics->supported_metrics =
2183 ctx.get_resp.u.customer_metrics.reported_metrics;
2184 else
2185 netdev_err(ena_dev->net_device,
2186 "Failed to query customer metrics support. error: %d\n", ret);
2187 }
2188
ena_com_get_dev_attr_feat(struct ena_com_dev * ena_dev,struct ena_com_dev_get_features_ctx * get_feat_ctx)2189 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
2190 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2191 {
2192 struct ena_admin_get_feat_resp get_resp;
2193 int rc;
2194
2195 rc = ena_com_get_feature(ena_dev, &get_resp,
2196 ENA_ADMIN_DEVICE_ATTRIBUTES, 0);
2197 if (rc)
2198 return rc;
2199
2200 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
2201 sizeof(get_resp.u.dev_attr));
2202
2203 ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
2204 ena_dev->capabilities = get_resp.u.dev_attr.capabilities;
2205
2206 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
2207 rc = ena_com_get_feature(ena_dev, &get_resp,
2208 ENA_ADMIN_MAX_QUEUES_EXT,
2209 ENA_FEATURE_MAX_QUEUE_EXT_VER);
2210 if (rc)
2211 return rc;
2212
2213 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER)
2214 return -EINVAL;
2215
2216 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext,
2217 sizeof(get_resp.u.max_queue_ext));
2218 ena_dev->tx_max_header_size =
2219 get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size;
2220 } else {
2221 rc = ena_com_get_feature(ena_dev, &get_resp,
2222 ENA_ADMIN_MAX_QUEUES_NUM, 0);
2223 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
2224 sizeof(get_resp.u.max_queue));
2225 ena_dev->tx_max_header_size =
2226 get_resp.u.max_queue.max_header_size;
2227
2228 if (rc)
2229 return rc;
2230 }
2231
2232 rc = ena_com_get_feature(ena_dev, &get_resp,
2233 ENA_ADMIN_AENQ_CONFIG, 0);
2234 if (rc)
2235 return rc;
2236
2237 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
2238 sizeof(get_resp.u.aenq));
2239
2240 rc = ena_com_get_feature(ena_dev, &get_resp,
2241 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
2242 if (rc)
2243 return rc;
2244
2245 memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
2246 sizeof(get_resp.u.offload));
2247
2248 /* Driver hints isn't mandatory admin command. So in case the
2249 * command isn't supported set driver hints to 0
2250 */
2251 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0);
2252
2253 if (!rc)
2254 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints, sizeof(get_resp.u.hw_hints));
2255 else if (rc == -EOPNOTSUPP)
2256 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints));
2257 else
2258 return rc;
2259
2260 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0);
2261 if (!rc)
2262 memcpy(&get_feat_ctx->llq, &get_resp.u.llq, sizeof(get_resp.u.llq));
2263 else if (rc == -EOPNOTSUPP)
2264 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
2265 else
2266 return rc;
2267
2268 ena_com_set_supported_customer_metrics(ena_dev);
2269
2270 return 0;
2271 }
2272
ena_com_admin_q_comp_intr_handler(struct ena_com_dev * ena_dev)2273 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
2274 {
2275 ena_com_handle_admin_completion(&ena_dev->admin_queue);
2276 }
2277
2278 /* ena_handle_specific_aenq_event:
2279 * return the handler that is relevant to the specific event group
2280 */
ena_com_get_specific_aenq_cb(struct ena_com_dev * ena_dev,u16 group)2281 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *ena_dev,
2282 u16 group)
2283 {
2284 struct ena_aenq_handlers *aenq_handlers = ena_dev->aenq.aenq_handlers;
2285
2286 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
2287 return aenq_handlers->handlers[group];
2288
2289 return aenq_handlers->unimplemented_handler;
2290 }
2291
2292 /* ena_aenq_intr_handler:
2293 * handles the aenq incoming events.
2294 * pop events from the queue and apply the specific handler
2295 */
ena_com_aenq_intr_handler(struct ena_com_dev * ena_dev,void * data)2296 void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data)
2297 {
2298 struct ena_admin_aenq_entry *aenq_e;
2299 struct ena_admin_aenq_common_desc *aenq_common;
2300 struct ena_com_aenq *aenq = &ena_dev->aenq;
2301 u64 timestamp;
2302 ena_aenq_handler handler_cb;
2303 u16 masked_head, processed = 0;
2304 u8 phase;
2305
2306 masked_head = aenq->head & (aenq->q_depth - 1);
2307 phase = aenq->phase;
2308 aenq_e = &aenq->entries[masked_head]; /* Get first entry */
2309 aenq_common = &aenq_e->aenq_common_desc;
2310
2311 /* Go over all the events */
2312 while ((READ_ONCE(aenq_common->flags) & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
2313 /* Make sure the phase bit (ownership) is as expected before
2314 * reading the rest of the descriptor.
2315 */
2316 dma_rmb();
2317
2318 timestamp = (u64)aenq_common->timestamp_low |
2319 ((u64)aenq_common->timestamp_high << 32);
2320
2321 netdev_dbg(ena_dev->net_device, "AENQ! Group[%x] Syndrome[%x] timestamp: [%llus]\n",
2322 aenq_common->group, aenq_common->syndrome, timestamp);
2323
2324 /* Handle specific event*/
2325 handler_cb = ena_com_get_specific_aenq_cb(ena_dev,
2326 aenq_common->group);
2327 handler_cb(data, aenq_e); /* call the actual event handler*/
2328
2329 /* Get next event entry */
2330 masked_head++;
2331 processed++;
2332
2333 if (unlikely(masked_head == aenq->q_depth)) {
2334 masked_head = 0;
2335 phase = !phase;
2336 }
2337 aenq_e = &aenq->entries[masked_head];
2338 aenq_common = &aenq_e->aenq_common_desc;
2339 }
2340
2341 aenq->head += processed;
2342 aenq->phase = phase;
2343
2344 /* Don't update aenq doorbell if there weren't any processed events */
2345 if (!processed)
2346 return;
2347
2348 /* write the aenq doorbell after all AENQ descriptors were read */
2349 mb();
2350 writel_relaxed((u32)aenq->head, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
2351 }
2352
ena_com_dev_reset(struct ena_com_dev * ena_dev,enum ena_regs_reset_reason_types reset_reason)2353 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
2354 enum ena_regs_reset_reason_types reset_reason)
2355 {
2356 u32 stat, timeout, cap, reset_val;
2357 int rc;
2358
2359 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
2360 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
2361
2362 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) || (cap == ENA_MMIO_READ_TIMEOUT))) {
2363 netdev_err(ena_dev->net_device, "Reg read32 timeout occurred\n");
2364 return -ETIME;
2365 }
2366
2367 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
2368 netdev_err(ena_dev->net_device, "Device isn't ready, can't reset device\n");
2369 return -EINVAL;
2370 }
2371
2372 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
2373 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
2374 if (timeout == 0) {
2375 netdev_err(ena_dev->net_device, "Invalid timeout value\n");
2376 return -EINVAL;
2377 }
2378
2379 /* start reset */
2380 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
2381 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
2382 ENA_REGS_DEV_CTL_RESET_REASON_MASK;
2383 writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2384
2385 /* Write again the MMIO read request address */
2386 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
2387
2388 rc = wait_for_reset_state(ena_dev, timeout,
2389 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
2390 if (rc != 0) {
2391 netdev_err(ena_dev->net_device, "Reset indication didn't turn on\n");
2392 return rc;
2393 }
2394
2395 /* reset done */
2396 writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2397 rc = wait_for_reset_state(ena_dev, timeout, 0);
2398 if (rc != 0) {
2399 netdev_err(ena_dev->net_device, "Reset indication didn't turn off\n");
2400 return rc;
2401 }
2402
2403 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
2404 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
2405 if (timeout)
2406 /* the resolution of timeout reg is 100ms */
2407 ena_dev->admin_queue.completion_timeout = timeout * 100000;
2408 else
2409 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2410
2411 return 0;
2412 }
2413
ena_com_get_eni_stats(struct ena_com_dev * ena_dev,struct ena_admin_eni_stats * stats)2414 int ena_com_get_eni_stats(struct ena_com_dev *ena_dev,
2415 struct ena_admin_eni_stats *stats)
2416 {
2417 struct ena_com_stats_ctx ctx;
2418 int ret;
2419
2420 if (!ena_com_get_cap(ena_dev, ENA_ADMIN_ENI_STATS)) {
2421 netdev_err(ena_dev->net_device, "Capability %d isn't supported\n",
2422 ENA_ADMIN_ENI_STATS);
2423 return -EOPNOTSUPP;
2424 }
2425
2426 memset(&ctx, 0x0, sizeof(ctx));
2427 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENI);
2428 if (likely(ret == 0))
2429 memcpy(stats, &ctx.get_resp.u.eni_stats,
2430 sizeof(ctx.get_resp.u.eni_stats));
2431
2432 return ret;
2433 }
2434
ena_com_get_ena_srd_info(struct ena_com_dev * ena_dev,struct ena_admin_ena_srd_info * info)2435 int ena_com_get_ena_srd_info(struct ena_com_dev *ena_dev,
2436 struct ena_admin_ena_srd_info *info)
2437 {
2438 struct ena_com_stats_ctx ctx;
2439 int ret;
2440
2441 if (!ena_com_get_cap(ena_dev, ENA_ADMIN_ENA_SRD_INFO)) {
2442 netdev_err(ena_dev->net_device, "Capability %d isn't supported\n",
2443 ENA_ADMIN_ENA_SRD_INFO);
2444 return -EOPNOTSUPP;
2445 }
2446
2447 memset(&ctx, 0x0, sizeof(ctx));
2448 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENA_SRD);
2449 if (likely(ret == 0))
2450 memcpy(info, &ctx.get_resp.u.ena_srd_info,
2451 sizeof(ctx.get_resp.u.ena_srd_info));
2452
2453 return ret;
2454 }
2455
ena_com_get_customer_metrics(struct ena_com_dev * ena_dev,char * buffer,u32 len)2456 int ena_com_get_customer_metrics(struct ena_com_dev *ena_dev, char *buffer, u32 len)
2457 {
2458 struct ena_admin_aq_get_stats_cmd *get_cmd;
2459 struct ena_com_stats_ctx ctx;
2460 int ret;
2461
2462 if (unlikely(len > ena_dev->customer_metrics.buffer_len)) {
2463 netdev_err(ena_dev->net_device,
2464 "Invalid buffer size %u. The given buffer is too big.\n", len);
2465 return -EINVAL;
2466 }
2467
2468 if (!ena_com_get_cap(ena_dev, ENA_ADMIN_CUSTOMER_METRICS)) {
2469 netdev_err(ena_dev->net_device, "Capability %d not supported.\n",
2470 ENA_ADMIN_CUSTOMER_METRICS);
2471 return -EOPNOTSUPP;
2472 }
2473
2474 if (!ena_dev->customer_metrics.supported_metrics) {
2475 netdev_err(ena_dev->net_device, "No supported customer metrics.\n");
2476 return -EOPNOTSUPP;
2477 }
2478
2479 get_cmd = &ctx.get_cmd;
2480 memset(&ctx, 0x0, sizeof(ctx));
2481 ret = ena_com_mem_addr_set(ena_dev,
2482 &get_cmd->u.control_buffer.address,
2483 ena_dev->customer_metrics.buffer_dma_addr);
2484 if (unlikely(ret)) {
2485 netdev_err(ena_dev->net_device, "Memory address set failed.\n");
2486 return ret;
2487 }
2488
2489 get_cmd->u.control_buffer.length = ena_dev->customer_metrics.buffer_len;
2490 get_cmd->requested_metrics = ena_dev->customer_metrics.supported_metrics;
2491 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_CUSTOMER_METRICS);
2492 if (likely(ret == 0))
2493 memcpy(buffer, ena_dev->customer_metrics.buffer_virt_addr, len);
2494 else
2495 netdev_err(ena_dev->net_device, "Failed to get customer metrics. error: %d\n", ret);
2496
2497 return ret;
2498 }
2499
ena_com_set_dev_mtu(struct ena_com_dev * ena_dev,u32 mtu)2500 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, u32 mtu)
2501 {
2502 struct ena_com_admin_queue *admin_queue;
2503 struct ena_admin_set_feat_cmd cmd;
2504 struct ena_admin_set_feat_resp resp;
2505 int ret;
2506
2507 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2508 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", ENA_ADMIN_MTU);
2509 return -EOPNOTSUPP;
2510 }
2511
2512 memset(&cmd, 0x0, sizeof(cmd));
2513 admin_queue = &ena_dev->admin_queue;
2514
2515 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2516 cmd.aq_common_descriptor.flags = 0;
2517 cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2518 cmd.u.mtu.mtu = mtu;
2519
2520 ret = ena_com_execute_admin_command(admin_queue,
2521 (struct ena_admin_aq_entry *)&cmd,
2522 sizeof(cmd),
2523 (struct ena_admin_acq_entry *)&resp,
2524 sizeof(resp));
2525
2526 if (unlikely(ret))
2527 netdev_err(ena_dev->net_device, "Failed to set mtu %d. error: %d\n", mtu, ret);
2528
2529 return ret;
2530 }
2531
ena_com_set_hash_function(struct ena_com_dev * ena_dev)2532 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2533 {
2534 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2535 struct ena_rss *rss = &ena_dev->rss;
2536 struct ena_admin_set_feat_cmd cmd;
2537 struct ena_admin_set_feat_resp resp;
2538 struct ena_admin_get_feat_resp get_resp;
2539 int ret;
2540
2541 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_FUNCTION)) {
2542 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
2543 ENA_ADMIN_RSS_HASH_FUNCTION);
2544 return -EOPNOTSUPP;
2545 }
2546
2547 /* Validate hash function is supported */
2548 ret = ena_com_get_feature(ena_dev, &get_resp,
2549 ENA_ADMIN_RSS_HASH_FUNCTION, 0);
2550 if (unlikely(ret))
2551 return ret;
2552
2553 if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) {
2554 netdev_err(ena_dev->net_device, "Func hash %d isn't supported by device, abort\n",
2555 rss->hash_func);
2556 return -EOPNOTSUPP;
2557 }
2558
2559 memset(&cmd, 0x0, sizeof(cmd));
2560
2561 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2562 cmd.aq_common_descriptor.flags =
2563 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2564 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2565 cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2566 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2567
2568 ret = ena_com_mem_addr_set(ena_dev,
2569 &cmd.control_buffer.address,
2570 rss->hash_key_dma_addr);
2571 if (unlikely(ret)) {
2572 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2573 return ret;
2574 }
2575
2576 cmd.control_buffer.length = sizeof(*rss->hash_key);
2577
2578 ret = ena_com_execute_admin_command(admin_queue,
2579 (struct ena_admin_aq_entry *)&cmd,
2580 sizeof(cmd),
2581 (struct ena_admin_acq_entry *)&resp,
2582 sizeof(resp));
2583 if (unlikely(ret)) {
2584 netdev_err(ena_dev->net_device, "Failed to set hash function %d. error: %d\n",
2585 rss->hash_func, ret);
2586 return -EINVAL;
2587 }
2588
2589 return 0;
2590 }
2591
ena_com_fill_hash_function(struct ena_com_dev * ena_dev,enum ena_admin_hash_functions func,const u8 * key,u16 key_len,u32 init_val)2592 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2593 enum ena_admin_hash_functions func,
2594 const u8 *key, u16 key_len, u32 init_val)
2595 {
2596 struct ena_admin_feature_rss_flow_hash_control *hash_key;
2597 struct ena_admin_get_feat_resp get_resp;
2598 enum ena_admin_hash_functions old_func;
2599 struct ena_rss *rss = &ena_dev->rss;
2600 int rc;
2601
2602 hash_key = rss->hash_key;
2603
2604 /* Make sure size is a mult of DWs */
2605 if (unlikely(key_len & 0x3))
2606 return -EINVAL;
2607
2608 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2609 ENA_ADMIN_RSS_HASH_FUNCTION,
2610 rss->hash_key_dma_addr,
2611 sizeof(*rss->hash_key), 0);
2612 if (unlikely(rc))
2613 return rc;
2614
2615 if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) {
2616 netdev_err(ena_dev->net_device, "Flow hash function %d isn't supported\n", func);
2617 return -EOPNOTSUPP;
2618 }
2619
2620 if ((func == ENA_ADMIN_TOEPLITZ) && key) {
2621 if (key_len != sizeof(hash_key->key)) {
2622 netdev_err(ena_dev->net_device,
2623 "key len (%u) doesn't equal the supported size (%zu)\n", key_len,
2624 sizeof(hash_key->key));
2625 return -EINVAL;
2626 }
2627 memcpy(hash_key->key, key, key_len);
2628 hash_key->key_parts = key_len / sizeof(hash_key->key[0]);
2629 }
2630
2631 rss->hash_init_val = init_val;
2632 old_func = rss->hash_func;
2633 rss->hash_func = func;
2634 rc = ena_com_set_hash_function(ena_dev);
2635
2636 /* Restore the old function */
2637 if (unlikely(rc))
2638 rss->hash_func = old_func;
2639
2640 return rc;
2641 }
2642
ena_com_get_hash_function(struct ena_com_dev * ena_dev,enum ena_admin_hash_functions * func)2643 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2644 enum ena_admin_hash_functions *func)
2645 {
2646 struct ena_rss *rss = &ena_dev->rss;
2647 struct ena_admin_get_feat_resp get_resp;
2648 int rc;
2649
2650 if (unlikely(!func))
2651 return -EINVAL;
2652
2653 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2654 ENA_ADMIN_RSS_HASH_FUNCTION,
2655 rss->hash_key_dma_addr,
2656 sizeof(*rss->hash_key), 0);
2657 if (unlikely(rc))
2658 return rc;
2659
2660 /* ffs() returns 1 in case the lsb is set */
2661 rss->hash_func = ffs(get_resp.u.flow_hash_func.selected_func);
2662 if (rss->hash_func)
2663 rss->hash_func--;
2664
2665 *func = rss->hash_func;
2666
2667 return 0;
2668 }
2669
ena_com_get_hash_key(struct ena_com_dev * ena_dev,u8 * key)2670 int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key)
2671 {
2672 struct ena_admin_feature_rss_flow_hash_control *hash_key =
2673 ena_dev->rss.hash_key;
2674
2675 if (key)
2676 memcpy(key, hash_key->key,
2677 (size_t)(hash_key->key_parts) * sizeof(hash_key->key[0]));
2678
2679 return 0;
2680 }
2681
ena_com_get_hash_ctrl(struct ena_com_dev * ena_dev,enum ena_admin_flow_hash_proto proto,u16 * fields)2682 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2683 enum ena_admin_flow_hash_proto proto,
2684 u16 *fields)
2685 {
2686 struct ena_rss *rss = &ena_dev->rss;
2687 struct ena_admin_get_feat_resp get_resp;
2688 int rc;
2689
2690 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2691 ENA_ADMIN_RSS_HASH_INPUT,
2692 rss->hash_ctrl_dma_addr,
2693 sizeof(*rss->hash_ctrl), 0);
2694 if (unlikely(rc))
2695 return rc;
2696
2697 if (fields)
2698 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2699
2700 return 0;
2701 }
2702
ena_com_set_hash_ctrl(struct ena_com_dev * ena_dev)2703 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2704 {
2705 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2706 struct ena_rss *rss = &ena_dev->rss;
2707 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2708 struct ena_admin_set_feat_cmd cmd;
2709 struct ena_admin_set_feat_resp resp;
2710 int ret;
2711
2712 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_INPUT)) {
2713 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
2714 ENA_ADMIN_RSS_HASH_INPUT);
2715 return -EOPNOTSUPP;
2716 }
2717
2718 memset(&cmd, 0x0, sizeof(cmd));
2719
2720 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2721 cmd.aq_common_descriptor.flags =
2722 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2723 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2724 cmd.u.flow_hash_input.enabled_input_sort =
2725 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2726 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2727
2728 ret = ena_com_mem_addr_set(ena_dev,
2729 &cmd.control_buffer.address,
2730 rss->hash_ctrl_dma_addr);
2731 if (unlikely(ret)) {
2732 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2733 return ret;
2734 }
2735 cmd.control_buffer.length = sizeof(*hash_ctrl);
2736
2737 ret = ena_com_execute_admin_command(admin_queue,
2738 (struct ena_admin_aq_entry *)&cmd,
2739 sizeof(cmd),
2740 (struct ena_admin_acq_entry *)&resp,
2741 sizeof(resp));
2742 if (unlikely(ret))
2743 netdev_err(ena_dev->net_device, "Failed to set hash input. error: %d\n", ret);
2744
2745 return ret;
2746 }
2747
ena_com_set_default_hash_ctrl(struct ena_com_dev * ena_dev)2748 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2749 {
2750 struct ena_rss *rss = &ena_dev->rss;
2751 struct ena_admin_feature_rss_hash_control *hash_ctrl =
2752 rss->hash_ctrl;
2753 u16 available_fields = 0;
2754 int rc, i;
2755
2756 /* Get the supported hash input */
2757 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2758 if (unlikely(rc))
2759 return rc;
2760
2761 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2762 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2763 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2764
2765 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2766 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2767 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2768
2769 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2770 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2771 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2772
2773 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2774 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2775 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2776
2777 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2778 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2779
2780 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2781 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2782
2783 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2784 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2785
2786 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2787 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2788
2789 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2790 available_fields = hash_ctrl->selected_fields[i].fields &
2791 hash_ctrl->supported_fields[i].fields;
2792 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2793 netdev_err(ena_dev->net_device,
2794 "Hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2795 i, hash_ctrl->supported_fields[i].fields,
2796 hash_ctrl->selected_fields[i].fields);
2797 return -EOPNOTSUPP;
2798 }
2799 }
2800
2801 rc = ena_com_set_hash_ctrl(ena_dev);
2802
2803 /* In case of failure, restore the old hash ctrl */
2804 if (unlikely(rc))
2805 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2806
2807 return rc;
2808 }
2809
ena_com_fill_hash_ctrl(struct ena_com_dev * ena_dev,enum ena_admin_flow_hash_proto proto,u16 hash_fields)2810 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2811 enum ena_admin_flow_hash_proto proto,
2812 u16 hash_fields)
2813 {
2814 struct ena_rss *rss = &ena_dev->rss;
2815 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2816 u16 supported_fields;
2817 int rc;
2818
2819 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2820 netdev_err(ena_dev->net_device, "Invalid proto num (%u)\n", proto);
2821 return -EINVAL;
2822 }
2823
2824 /* Get the ctrl table */
2825 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2826 if (unlikely(rc))
2827 return rc;
2828
2829 /* Make sure all the fields are supported */
2830 supported_fields = hash_ctrl->supported_fields[proto].fields;
2831 if ((hash_fields & supported_fields) != hash_fields) {
2832 netdev_err(ena_dev->net_device,
2833 "Proto %d doesn't support the required fields %x. supports only: %x\n",
2834 proto, hash_fields, supported_fields);
2835 }
2836
2837 hash_ctrl->selected_fields[proto].fields = hash_fields;
2838
2839 rc = ena_com_set_hash_ctrl(ena_dev);
2840
2841 /* In case of failure, restore the old hash ctrl */
2842 if (unlikely(rc))
2843 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2844
2845 return 0;
2846 }
2847
ena_com_indirect_table_fill_entry(struct ena_com_dev * ena_dev,u16 entry_idx,u16 entry_value)2848 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2849 u16 entry_idx, u16 entry_value)
2850 {
2851 struct ena_rss *rss = &ena_dev->rss;
2852
2853 if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2854 return -EINVAL;
2855
2856 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2857 return -EINVAL;
2858
2859 rss->host_rss_ind_tbl[entry_idx] = entry_value;
2860
2861 return 0;
2862 }
2863
ena_com_indirect_table_set(struct ena_com_dev * ena_dev)2864 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2865 {
2866 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2867 struct ena_rss *rss = &ena_dev->rss;
2868 struct ena_admin_set_feat_cmd cmd;
2869 struct ena_admin_set_feat_resp resp;
2870 int ret;
2871
2872 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG)) {
2873 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
2874 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG);
2875 return -EOPNOTSUPP;
2876 }
2877
2878 ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2879 if (ret) {
2880 netdev_err(ena_dev->net_device,
2881 "Failed to convert host indirection table to device table\n");
2882 return ret;
2883 }
2884
2885 memset(&cmd, 0x0, sizeof(cmd));
2886
2887 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2888 cmd.aq_common_descriptor.flags =
2889 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2890 cmd.feat_common.feature_id = ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG;
2891 cmd.u.ind_table.size = rss->tbl_log_size;
2892 cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2893
2894 ret = ena_com_mem_addr_set(ena_dev,
2895 &cmd.control_buffer.address,
2896 rss->rss_ind_tbl_dma_addr);
2897 if (unlikely(ret)) {
2898 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2899 return ret;
2900 }
2901
2902 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2903 sizeof(struct ena_admin_rss_ind_table_entry);
2904
2905 ret = ena_com_execute_admin_command(admin_queue,
2906 (struct ena_admin_aq_entry *)&cmd,
2907 sizeof(cmd),
2908 (struct ena_admin_acq_entry *)&resp,
2909 sizeof(resp));
2910
2911 if (unlikely(ret))
2912 netdev_err(ena_dev->net_device, "Failed to set indirect table. error: %d\n", ret);
2913
2914 return ret;
2915 }
2916
ena_com_indirect_table_get(struct ena_com_dev * ena_dev,u32 * ind_tbl)2917 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2918 {
2919 struct ena_rss *rss = &ena_dev->rss;
2920 struct ena_admin_get_feat_resp get_resp;
2921 u32 tbl_size;
2922 int i, rc;
2923
2924 tbl_size = (1ULL << rss->tbl_log_size) *
2925 sizeof(struct ena_admin_rss_ind_table_entry);
2926
2927 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2928 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG,
2929 rss->rss_ind_tbl_dma_addr,
2930 tbl_size, 0);
2931 if (unlikely(rc))
2932 return rc;
2933
2934 if (!ind_tbl)
2935 return 0;
2936
2937 for (i = 0; i < (1 << rss->tbl_log_size); i++)
2938 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2939
2940 return 0;
2941 }
2942
ena_com_rss_init(struct ena_com_dev * ena_dev,u16 indr_tbl_log_size)2943 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2944 {
2945 int rc;
2946
2947 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2948
2949 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2950 if (unlikely(rc))
2951 goto err_indr_tbl;
2952
2953 /* The following function might return unsupported in case the
2954 * device doesn't support setting the key / hash function. We can safely
2955 * ignore this error and have indirection table support only.
2956 */
2957 rc = ena_com_hash_key_allocate(ena_dev);
2958 if (likely(!rc))
2959 ena_com_hash_key_fill_default_key(ena_dev);
2960 else if (rc != -EOPNOTSUPP)
2961 goto err_hash_key;
2962
2963 rc = ena_com_hash_ctrl_init(ena_dev);
2964 if (unlikely(rc))
2965 goto err_hash_ctrl;
2966
2967 return 0;
2968
2969 err_hash_ctrl:
2970 ena_com_hash_key_destroy(ena_dev);
2971 err_hash_key:
2972 ena_com_indirect_table_destroy(ena_dev);
2973 err_indr_tbl:
2974
2975 return rc;
2976 }
2977
ena_com_rss_destroy(struct ena_com_dev * ena_dev)2978 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2979 {
2980 ena_com_indirect_table_destroy(ena_dev);
2981 ena_com_hash_key_destroy(ena_dev);
2982 ena_com_hash_ctrl_destroy(ena_dev);
2983
2984 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2985 }
2986
ena_com_allocate_host_info(struct ena_com_dev * ena_dev)2987 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2988 {
2989 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2990
2991 host_attr->host_info = dma_alloc_coherent(ena_dev->dmadev, SZ_4K,
2992 &host_attr->host_info_dma_addr, GFP_KERNEL);
2993 if (unlikely(!host_attr->host_info))
2994 return -ENOMEM;
2995
2996 host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR <<
2997 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
2998 (ENA_COMMON_SPEC_VERSION_MINOR));
2999
3000 return 0;
3001 }
3002
ena_com_allocate_debug_area(struct ena_com_dev * ena_dev,u32 debug_area_size)3003 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
3004 u32 debug_area_size)
3005 {
3006 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
3007
3008 host_attr->debug_area_virt_addr =
3009 dma_alloc_coherent(ena_dev->dmadev, debug_area_size,
3010 &host_attr->debug_area_dma_addr, GFP_KERNEL);
3011 if (unlikely(!host_attr->debug_area_virt_addr)) {
3012 host_attr->debug_area_size = 0;
3013 return -ENOMEM;
3014 }
3015
3016 host_attr->debug_area_size = debug_area_size;
3017
3018 return 0;
3019 }
3020
ena_com_allocate_customer_metrics_buffer(struct ena_com_dev * ena_dev)3021 int ena_com_allocate_customer_metrics_buffer(struct ena_com_dev *ena_dev)
3022 {
3023 struct ena_customer_metrics *customer_metrics = &ena_dev->customer_metrics;
3024
3025 customer_metrics->buffer_len = ENA_CUSTOMER_METRICS_BUFFER_SIZE;
3026 customer_metrics->buffer_virt_addr = NULL;
3027
3028 customer_metrics->buffer_virt_addr =
3029 dma_alloc_coherent(ena_dev->dmadev, customer_metrics->buffer_len,
3030 &customer_metrics->buffer_dma_addr, GFP_KERNEL);
3031 if (!customer_metrics->buffer_virt_addr) {
3032 customer_metrics->buffer_len = 0;
3033 return -ENOMEM;
3034 }
3035
3036 return 0;
3037 }
3038
ena_com_delete_host_info(struct ena_com_dev * ena_dev)3039 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
3040 {
3041 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
3042
3043 if (host_attr->host_info) {
3044 dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info,
3045 host_attr->host_info_dma_addr);
3046 host_attr->host_info = NULL;
3047 }
3048 }
3049
ena_com_delete_debug_area(struct ena_com_dev * ena_dev)3050 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
3051 {
3052 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
3053
3054 if (host_attr->debug_area_virt_addr) {
3055 dma_free_coherent(ena_dev->dmadev, host_attr->debug_area_size,
3056 host_attr->debug_area_virt_addr, host_attr->debug_area_dma_addr);
3057 host_attr->debug_area_virt_addr = NULL;
3058 }
3059 }
3060
ena_com_delete_customer_metrics_buffer(struct ena_com_dev * ena_dev)3061 void ena_com_delete_customer_metrics_buffer(struct ena_com_dev *ena_dev)
3062 {
3063 struct ena_customer_metrics *customer_metrics = &ena_dev->customer_metrics;
3064
3065 if (customer_metrics->buffer_virt_addr) {
3066 dma_free_coherent(ena_dev->dmadev, customer_metrics->buffer_len,
3067 customer_metrics->buffer_virt_addr,
3068 customer_metrics->buffer_dma_addr);
3069 customer_metrics->buffer_virt_addr = NULL;
3070 customer_metrics->buffer_len = 0;
3071 }
3072 }
3073
ena_com_set_host_attributes(struct ena_com_dev * ena_dev)3074 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
3075 {
3076 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
3077 struct ena_com_admin_queue *admin_queue;
3078 struct ena_admin_set_feat_cmd cmd;
3079 struct ena_admin_set_feat_resp resp;
3080
3081 int ret;
3082
3083 /* Host attribute config is called before ena_com_get_dev_attr_feat
3084 * so ena_com can't check if the feature is supported.
3085 */
3086
3087 memset(&cmd, 0x0, sizeof(cmd));
3088 admin_queue = &ena_dev->admin_queue;
3089
3090 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
3091 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
3092
3093 ret = ena_com_mem_addr_set(ena_dev,
3094 &cmd.u.host_attr.debug_ba,
3095 host_attr->debug_area_dma_addr);
3096 if (unlikely(ret)) {
3097 netdev_err(ena_dev->net_device, "Memory address set failed\n");
3098 return ret;
3099 }
3100
3101 ret = ena_com_mem_addr_set(ena_dev,
3102 &cmd.u.host_attr.os_info_ba,
3103 host_attr->host_info_dma_addr);
3104 if (unlikely(ret)) {
3105 netdev_err(ena_dev->net_device, "Memory address set failed\n");
3106 return ret;
3107 }
3108
3109 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
3110
3111 ret = ena_com_execute_admin_command(admin_queue,
3112 (struct ena_admin_aq_entry *)&cmd,
3113 sizeof(cmd),
3114 (struct ena_admin_acq_entry *)&resp,
3115 sizeof(resp));
3116
3117 if (unlikely(ret))
3118 netdev_err(ena_dev->net_device, "Failed to set host attributes: %d\n", ret);
3119
3120 return ret;
3121 }
3122
3123 /* Interrupt moderation */
ena_com_interrupt_moderation_supported(struct ena_com_dev * ena_dev)3124 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
3125 {
3126 return ena_com_check_supported_feature_id(ena_dev,
3127 ENA_ADMIN_INTERRUPT_MODERATION);
3128 }
3129
ena_com_update_nonadaptive_moderation_interval(struct ena_com_dev * ena_dev,u32 coalesce_usecs,u32 intr_delay_resolution,u32 * intr_moder_interval)3130 static int ena_com_update_nonadaptive_moderation_interval(struct ena_com_dev *ena_dev,
3131 u32 coalesce_usecs,
3132 u32 intr_delay_resolution,
3133 u32 *intr_moder_interval)
3134 {
3135 if (!intr_delay_resolution) {
3136 netdev_err(ena_dev->net_device, "Illegal interrupt delay granularity value\n");
3137 return -EFAULT;
3138 }
3139
3140 *intr_moder_interval = coalesce_usecs / intr_delay_resolution;
3141
3142 return 0;
3143 }
3144
ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev * ena_dev,u32 tx_coalesce_usecs)3145 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
3146 u32 tx_coalesce_usecs)
3147 {
3148 return ena_com_update_nonadaptive_moderation_interval(ena_dev,
3149 tx_coalesce_usecs,
3150 ena_dev->intr_delay_resolution,
3151 &ena_dev->intr_moder_tx_interval);
3152 }
3153
ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev * ena_dev,u32 rx_coalesce_usecs)3154 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
3155 u32 rx_coalesce_usecs)
3156 {
3157 return ena_com_update_nonadaptive_moderation_interval(ena_dev,
3158 rx_coalesce_usecs,
3159 ena_dev->intr_delay_resolution,
3160 &ena_dev->intr_moder_rx_interval);
3161 }
3162
ena_com_init_interrupt_moderation(struct ena_com_dev * ena_dev)3163 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
3164 {
3165 struct ena_admin_get_feat_resp get_resp;
3166 u16 delay_resolution;
3167 int rc;
3168
3169 rc = ena_com_get_feature(ena_dev, &get_resp,
3170 ENA_ADMIN_INTERRUPT_MODERATION, 0);
3171
3172 if (rc) {
3173 if (rc == -EOPNOTSUPP) {
3174 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
3175 ENA_ADMIN_INTERRUPT_MODERATION);
3176 rc = 0;
3177 } else {
3178 netdev_err(ena_dev->net_device,
3179 "Failed to get interrupt moderation admin cmd. rc: %d\n", rc);
3180 }
3181
3182 /* no moderation supported, disable adaptive support */
3183 ena_com_disable_adaptive_moderation(ena_dev);
3184 return rc;
3185 }
3186
3187 /* if moderation is supported by device we set adaptive moderation */
3188 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
3189 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
3190
3191 /* Disable adaptive moderation by default - can be enabled later */
3192 ena_com_disable_adaptive_moderation(ena_dev);
3193
3194 return 0;
3195 }
3196
ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev * ena_dev)3197 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
3198 {
3199 return ena_dev->intr_moder_tx_interval;
3200 }
3201
ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev * ena_dev)3202 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
3203 {
3204 return ena_dev->intr_moder_rx_interval;
3205 }
3206
ena_com_config_dev_mode(struct ena_com_dev * ena_dev,struct ena_admin_feature_llq_desc * llq_features,struct ena_llq_configurations * llq_default_cfg)3207 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
3208 struct ena_admin_feature_llq_desc *llq_features,
3209 struct ena_llq_configurations *llq_default_cfg)
3210 {
3211 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
3212 int rc;
3213
3214 if (!llq_features->max_llq_num) {
3215 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
3216 return 0;
3217 }
3218
3219 rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg);
3220 if (rc)
3221 return rc;
3222
3223 ena_dev->tx_max_header_size = llq_info->desc_list_entry_size -
3224 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc));
3225
3226 if (unlikely(ena_dev->tx_max_header_size == 0)) {
3227 netdev_err(ena_dev->net_device, "The size of the LLQ entry is smaller than needed\n");
3228 return -EINVAL;
3229 }
3230
3231 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
3232
3233 return 0;
3234 }
3235