1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #ifndef __MT7996_H 7 #define __MT7996_H 8 9 #include <linux/interrupt.h> 10 #include <linux/ktime.h> 11 #include "../mt76_connac.h" 12 #include "regs.h" 13 14 #define MT7996_MAX_RADIOS 3 15 #define MT7996_MAX_INTERFACES 19 /* per-band */ 16 #define MT7996_MAX_WMM_SETS 4 17 #define MT7996_WTBL_BMC_SIZE (is_mt7996(&dev->mt76) ? 64 : 32) 18 #define MT7996_WTBL_RESERVED (mt7996_wtbl_size(dev) - 1) 19 #define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \ 20 mt7996_max_interface_num(dev)) 21 22 #define MT7996_WATCHDOG_TIME (HZ / 10) 23 #define MT7996_RESET_TIMEOUT (30 * HZ) 24 25 #define MT7996_TX_RING_SIZE 2048 26 #define MT7996_TX_MCU_RING_SIZE 256 27 #define MT7996_TX_FWDL_RING_SIZE 128 28 29 #define MT7996_RX_RING_SIZE 1536 30 #define MT7996_RX_MCU_RING_SIZE 512 31 #define MT7996_RX_MCU_RING_SIZE_WA 1024 32 #define MT7996_NPU_TX_RING_SIZE 1024 33 #define MT7996_NPU_RX_RING_SIZE 1024 34 #define MT7996_NPU_TXD_SIZE 3 35 36 /* scatter-gather of mcu event is not supported in connac3 */ 37 #define MT7996_RX_MCU_BUF_SIZE (2048 + \ 38 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 39 40 #define MT7996_DEVICE_ID 0x7990 41 #define MT7996_DEVICE_ID_2 0x7991 42 #define MT7992_DEVICE_ID 0x7992 43 #define MT7992_DEVICE_ID_2 0x799a 44 #define MT7990_DEVICE_ID 0x7993 45 #define MT7990_DEVICE_ID_2 0x799b 46 47 #define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin" 48 #define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin" 49 #define MT7996_FIRMWARE_DSP "mediatek/mt7996/mt7996_dsp.bin" 50 #define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin" 51 52 #define MT7996_FIRMWARE_WA_233 "mediatek/mt7996/mt7996_wa_233.bin" 53 #define MT7996_FIRMWARE_WM_233 "mediatek/mt7996/mt7996_wm_233.bin" 54 #define MT7996_FIRMWARE_DSP_233 MT7996_FIRMWARE_DSP 55 #define MT7996_ROM_PATCH_233 "mediatek/mt7996/mt7996_rom_patch_233.bin" 56 57 #define MT7992_FIRMWARE_WA "mediatek/mt7996/mt7992_wa.bin" 58 #define MT7992_FIRMWARE_WM "mediatek/mt7996/mt7992_wm.bin" 59 #define MT7992_FIRMWARE_DSP "mediatek/mt7996/mt7992_dsp.bin" 60 #define MT7992_ROM_PATCH "mediatek/mt7996/mt7992_rom_patch.bin" 61 62 #define MT7992_FIRMWARE_WA_23 "mediatek/mt7996/mt7992_wa_23.bin" 63 #define MT7992_FIRMWARE_WM_23 "mediatek/mt7996/mt7992_wm_23.bin" 64 #define MT7992_FIRMWARE_DSP_23 "mediatek/mt7996/mt7992_dsp_23.bin" 65 #define MT7992_ROM_PATCH_23 "mediatek/mt7996/mt7992_rom_patch_23.bin" 66 67 #define MT7992_FIRMWARE_WA_24 "mediatek/mt7996/mt7992_wa_24.bin" 68 #define MT7992_FIRMWARE_WM_24 "mediatek/mt7996/mt7992_wm_24.bin" 69 #define MT7992_FIRMWARE_DSP_24 "mediatek/mt7996/mt7992_dsp_24.bin" 70 #define MT7992_ROM_PATCH_24 "mediatek/mt7996/mt7992_rom_patch_24.bin" 71 72 #define MT7990_FIRMWARE_WA "" 73 #define MT7990_FIRMWARE_WM "mediatek/mt7996/mt7990_wm.bin" 74 #define MT7990_FIRMWARE_DSP "" 75 #define MT7990_ROM_PATCH "mediatek/mt7996/mt7990_rom_patch.bin" 76 77 #define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin" 78 #define MT7996_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7996_eeprom_2i5i6i.bin" 79 #define MT7996_EEPROM_DEFAULT_233 "mediatek/mt7996/mt7996_eeprom_233.bin" 80 #define MT7996_EEPROM_DEFAULT_233_INT "mediatek/mt7996/mt7996_eeprom_233_2i5i6i.bin" 81 82 #define MT7992_EEPROM_DEFAULT "mediatek/mt7996/mt7992_eeprom.bin" 83 #define MT7992_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7992_eeprom_2i5i.bin" 84 #define MT7992_EEPROM_DEFAULT_MIX "mediatek/mt7996/mt7992_eeprom_2i5e.bin" 85 #define MT7992_EEPROM_DEFAULT_23 "mediatek/mt7996/mt7992_eeprom_23.bin" 86 #define MT7992_EEPROM_DEFAULT_23_INT "mediatek/mt7996/mt7992_eeprom_23_2i5i.bin" 87 #define MT7992_EEPROM_DEFAULT_24 "mediatek/mt7996/mt7992_eeprom_24_2i5i.bin" 88 89 #define MT7990_EEPROM_DEFAULT "mediatek/mt7996/mt7990_eeprom.bin" 90 #define MT7990_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7990_eeprom_2i5i.bin" 91 92 #define MT7996_EEPROM_SIZE 7680 93 #define MT7996_EEPROM_BLOCK_SIZE 16 94 #define MT7996_EXT_EEPROM_BLOCK_SIZE 1024 95 #define MT7996_TOKEN_SIZE 16384 96 #define MT7996_HW_TOKEN_SIZE 8192 97 98 #define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */ 99 #define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */ 100 #define MT7996_IBF_MAX_NC 2 101 #define MT7996_IBF_TIMEOUT 0x18 102 #define MT7996_IBF_TIMEOUT_LEGACY 0x48 103 104 #define MT7992_CFEND_RATE_DEFAULT 0x4b /* OFDM 6M */ 105 #define MT7992_IBF_TIMEOUT 0xff 106 107 #define MT7996_SKU_RATE_NUM 417 108 #define MT7996_SKU_PATH_NUM 494 109 110 #define MT7996_MAX_TWT_AGRT 16 111 #define MT7996_MAX_STA_TWT_AGRT 8 112 #define MT7996_MIN_TWT_DUR 64 113 #define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3) 114 115 /* NOTE: used to map mt76_rates. idx may change if firmware expands table */ 116 #define MT7996_BASIC_RATES_TBL 31 117 #define MT7996_BEACON_RATES_TBL 25 118 119 #define MT7996_THERMAL_THROTTLE_MAX 100 120 #define MT7996_CDEV_THROTTLE_MAX 99 121 #define MT7996_CRIT_TEMP_IDX 0 122 #define MT7996_MAX_TEMP_IDX 1 123 #define MT7996_CRIT_TEMP 110 124 #define MT7996_MAX_TEMP 120 125 126 #define MT7996_MAX_HIF_RXD_IN_PG 5 127 #define MT7996_RRO_MSDU_PG_HASH_SIZE 127 128 #define MT7996_RRO_MAX_SESSION 1024 129 #define MT7996_RRO_WINDOW_MAX_LEN 1024 130 #define MT7996_RRO_ADDR_ELEM_LEN 128 131 #define MT7996_RRO_BA_BITMAP_LEN 2 132 #define MT7996_RRO_BA_BITMAP_CR_SIZE ((MT7996_RRO_MAX_SESSION * 128) / \ 133 MT7996_RRO_BA_BITMAP_LEN) 134 #define MT7996_RRO_BA_BITMAP_SESSION_SIZE (MT7996_RRO_MAX_SESSION / \ 135 MT7996_RRO_ADDR_ELEM_LEN) 136 #define MT7996_RRO_WINDOW_MAX_SIZE (MT7996_RRO_WINDOW_MAX_LEN * \ 137 MT7996_RRO_BA_BITMAP_SESSION_SIZE) 138 139 #define MT7996_RX_BUF_SIZE (1800 + \ 140 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 141 #define MT7996_RX_MSDU_PAGE_SIZE (128 + \ 142 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 143 144 /* RRO 3.1 */ 145 #define MT7996_RRO_MSDU_PG_CR_CNT 8 146 #define MT7996_RRO_MSDU_PG_SIZE_PER_CR 0x10000 147 148 struct mt7996_vif; 149 struct mt7996_sta; 150 struct mt7996_dfs_pulse; 151 struct mt7996_dfs_pattern; 152 153 enum mt7996_ram_type { 154 MT7996_RAM_TYPE_WM, 155 MT7996_RAM_TYPE_WA, 156 MT7996_RAM_TYPE_DSP, 157 }; 158 159 enum mt7996_var_type { 160 MT7996_VAR_TYPE_444, 161 MT7996_VAR_TYPE_233, 162 }; 163 164 enum mt7992_var_type { 165 MT7992_VAR_TYPE_44, 166 MT7992_VAR_TYPE_23, 167 MT7992_VAR_TYPE_24, 168 }; 169 170 enum mt7990_var_type { 171 MT7990_VAR_TYPE_23, 172 }; 173 174 enum mt7996_fem_type { 175 MT7996_FEM_EXT, 176 MT7996_FEM_INT, 177 MT7996_FEM_MIX, 178 }; 179 180 enum mt7996_eeprom_mode { 181 EEPROM_MODE_DEFAULT_BIN, 182 EEPROM_MODE_EFUSE, 183 EEPROM_MODE_FLASH, 184 EEPROM_MODE_EXT, 185 }; 186 187 #define MT7996_EFUSE_BASE_OFFS_ADIE0 0x400 188 #define MT7996_EFUSE_BASE_OFFS_ADIE1 0x1e00 189 #define MT7996_EFUSE_BASE_OFFS_ADIE2 0x1200 190 #define MT7992_EFUSE_BASE_OFFS_ADIE1 0x1200 191 192 enum mt7996_txq_id { 193 MT7996_TXQ_FWDL = 16, 194 MT7996_TXQ_MCU_WM, 195 MT7996_TXQ_BAND0, 196 MT7996_TXQ_BAND1, 197 MT7996_TXQ_MCU_WA, 198 MT7996_TXQ_BAND2, 199 }; 200 201 enum mt7996_rxq_id { 202 MT7996_RXQ_MCU_WM = 0, 203 MT7996_RXQ_MCU_WA, 204 MT7996_RXQ_MCU_WA_MAIN = 2, 205 MT7996_RXQ_MCU_WA_EXT = 3, /* for mt7992 */ 206 MT7996_RXQ_MCU_WA_TRI = 3, 207 MT7996_RXQ_BAND0 = 4, 208 MT7996_RXQ_BAND1 = 5, /* for mt7992 */ 209 MT7996_RXQ_BAND2 = 5, 210 MT7996_RXQ_RRO_BAND0 = 8, 211 MT7996_RXQ_RRO_BAND1 = 9, 212 MT7996_RXQ_RRO_BAND2 = 6, 213 MT7996_RXQ_MSDU_PG_BAND0 = 10, 214 MT7996_RXQ_MSDU_PG_BAND1 = 11, 215 MT7996_RXQ_MSDU_PG_BAND2 = 12, 216 MT7996_RXQ_TXFREE0 = 9, 217 MT7996_RXQ_TXFREE1 = 9, 218 MT7996_RXQ_TXFREE2 = 7, 219 MT7996_RXQ_RRO_IND = 0, 220 MT7996_RXQ_RRO_RXDMAD_C = 0, 221 MT7990_RXQ_TXFREE0 = 6, 222 MT7990_RXQ_TXFREE1 = 7, 223 }; 224 225 struct mt7996_twt_flow { 226 struct list_head list; 227 u64 start_tsf; 228 u64 tsf; 229 u32 duration; 230 u16 wcid; 231 __le16 mantissa; 232 u8 exp; 233 u8 table_id; 234 u8 id; 235 u8 protection:1; 236 u8 flowtype:1; 237 u8 trigger:1; 238 u8 sched:1; 239 }; 240 241 DECLARE_EWMA(avg_signal, 10, 8) 242 243 struct mt7996_sta_link { 244 struct mt76_wcid wcid; /* must be first */ 245 246 struct mt7996_sta *sta; 247 bool connected; 248 249 struct list_head rc_list; 250 u32 airtime_ac[8]; 251 252 int ack_signal; 253 struct ewma_avg_signal avg_ack_signal; 254 255 unsigned long changed; 256 257 struct mt76_connac_sta_key_conf bip; 258 259 struct { 260 u8 flowid_mask; 261 struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT]; 262 } twt; 263 264 struct rcu_head rcu_head; 265 }; 266 267 struct mt7996_sta_ba { 268 u16 ssn; 269 u16 buf_size; 270 bool amsdu; 271 }; 272 273 struct mt7996_sta { 274 struct mt7996_sta_link deflink; /* must be first */ 275 struct mt7996_sta_link __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS]; 276 u8 deflink_id; 277 u8 seclink_id; 278 u8 conn_state; 279 280 unsigned long wcid_flags; 281 282 u16 ba_tx_mask; 283 u16 ba_rx_mask; 284 struct mt7996_sta_ba ba_tx[IEEE80211_NUM_TIDS]; 285 struct mt7996_sta_ba ba_rx[IEEE80211_NUM_TIDS]; 286 287 struct mt7996_vif *vif; 288 }; 289 290 struct mt7996_vif_link { 291 struct mt76_vif_link mt76; /* must be first */ 292 293 struct mt7996_sta_link msta_link; 294 struct cfg80211_bitrate_mask bitrate_mask; 295 296 u8 mld_idx; 297 u8 bmc_bssid[ETH_ALEN]; 298 }; 299 300 struct mt7996_vif_link_info { 301 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS]; 302 }; 303 304 struct mt7996_vif { 305 struct mt7996_vif_link deflink; /* must be first */ 306 struct mt76_vif_data mt76; 307 308 struct mt7996_vif_link_info link_info[IEEE80211_MLD_MAX_NUM_LINKS]; 309 310 u8 mld_group_idx; 311 u8 mld_remap_idx; 312 }; 313 314 /* crash-dump */ 315 struct mt7996_crash_data { 316 guid_t guid; 317 struct timespec64 timestamp; 318 319 u8 *memdump_buf; 320 size_t memdump_buf_len; 321 }; 322 323 struct mt7996_hif { 324 struct list_head list; 325 326 struct device *dev; 327 void __iomem *regs; 328 int irq; 329 330 enum pci_bus_speed speed; 331 enum pcie_link_width width; 332 }; 333 334 #define WED_RRO_ADDR_SIGNATURE_MASK GENMASK(31, 24) 335 #define WED_RRO_ADDR_COUNT_MASK GENMASK(14, 4) 336 #define WED_RRO_ADDR_HEAD_HIGH_MASK GENMASK(3, 0) 337 struct mt7996_wed_rro_addr { 338 __le32 head_low; 339 __le32 data; 340 }; 341 342 struct mt7996_wed_rro_session_id { 343 struct list_head list; 344 u16 id; 345 }; 346 347 struct mt7996_msdu_page { 348 struct list_head list; 349 350 struct mt76_queue *q; 351 dma_addr_t dma_addr; 352 void *buf; 353 }; 354 355 /* data1 */ 356 #define RRO_HIF_DATA1_LS_MASK BIT(30) 357 #define RRO_HIF_DATA1_SDL_MASK GENMASK(29, 16) 358 /* data4 */ 359 #define RRO_HIF_DATA4_RX_TOKEN_ID_MASK GENMASK(15, 0) 360 struct mt7996_rro_hif { 361 __le32 data0; 362 __le32 data1; 363 __le32 data2; 364 __le32 data3; 365 __le32 data4; 366 __le32 data5; 367 }; 368 369 #define MSDU_PAGE_INFO_OWNER_MASK BIT(31) 370 #define MSDU_PAGE_INFO_PG_HIGH_MASK GENMASK(3, 0) 371 struct mt7996_msdu_page_info { 372 struct mt7996_rro_hif rxd[MT7996_MAX_HIF_RXD_IN_PG]; 373 __le32 pg_low; 374 __le32 data; 375 }; 376 377 #define MT7996_MAX_RRO_RRS_RING 4 378 struct mt7996_rro_queue_regs_emi { 379 struct { 380 __le16 idx; 381 __le16 rsv; 382 } ring[MT7996_MAX_RRO_RRS_RING]; 383 }; 384 385 struct mt7996_phy { 386 struct mt76_phy *mt76; 387 struct mt7996_dev *dev; 388 389 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 390 391 struct thermal_cooling_device *cdev; 392 u8 cdev_state; 393 u8 throttle_state; 394 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */ 395 396 u32 rxfilter; 397 u64 omac_mask; 398 399 u16 noise; 400 401 s16 coverage_class; 402 u8 slottime; 403 404 u16 beacon_rate; 405 406 u32 rx_ampdu_ts; 407 u32 ampdu_ref; 408 int txpower; 409 410 struct mt76_mib_stats mib; 411 struct mt76_channel_state state_ts; 412 413 u16 orig_chainmask; 414 u16 orig_antenna_mask; 415 416 bool has_aux_rx; 417 bool counter_reset; 418 bool rdd_tx_paused; 419 }; 420 421 struct mt7996_dev { 422 union { /* must be first */ 423 struct mt76_dev mt76; 424 struct mt76_phy mphy; 425 }; 426 427 struct mt7996_phy *radio_phy[MT7996_MAX_RADIOS]; 428 struct wiphy_radio radios[MT7996_MAX_RADIOS]; 429 struct wiphy_radio_freq_range radio_freqs[MT7996_MAX_RADIOS]; 430 struct mac_address radio_addrs[MT7996_MAX_RADIOS]; 431 432 struct mt7996_hif *hif2; 433 struct mt7996_reg_desc reg; 434 u8 q_id[MT7996_MAX_QUEUE]; 435 u32 q_int_mask[MT7996_MAX_QUEUE]; 436 u32 q_wfdma_mask; 437 438 u64 mld_idx_mask; 439 u64 mld_remap_idx_mask; 440 441 const struct mt76_bus_ops *bus_ops; 442 struct mt7996_phy phy; 443 444 /* monitor rx chain configured channel */ 445 struct cfg80211_chan_def rdd2_chandef; 446 struct mt7996_phy *rdd2_phy; 447 448 u16 chainmask; 449 u8 chainshift[__MT_MAX_BAND]; 450 u32 hif_idx; 451 452 struct work_struct init_work; 453 struct work_struct rc_work; 454 struct work_struct dump_work; 455 struct work_struct reset_work; 456 wait_queue_head_t reset_wait; 457 struct { 458 u32 state; 459 u32 wa_reset_count; 460 u32 wm_reset_count; 461 bool hw_full_reset:1; 462 bool hw_init_done:1; 463 bool restart:1; 464 } recovery; 465 466 /* protects coredump data */ 467 struct mutex dump_mutex; 468 #ifdef CONFIG_DEV_COREDUMP 469 struct { 470 struct mt7996_crash_data *crash_data; 471 } coredump; 472 #endif 473 474 struct list_head sta_rc_list; 475 struct list_head twt_list; 476 477 u32 hw_pattern; 478 479 u8 eeprom_mode; 480 bool has_eht:1; 481 482 struct { 483 struct { 484 void *ptr; 485 dma_addr_t phy_addr; 486 } ba_bitmap[MT7996_RRO_BA_BITMAP_LEN]; 487 struct { 488 void *ptr; 489 dma_addr_t phy_addr; 490 } addr_elem[MT7996_RRO_ADDR_ELEM_LEN]; 491 struct { 492 void *ptr; 493 dma_addr_t phy_addr; 494 } session; 495 struct { 496 void *ptr; 497 dma_addr_t phy_addr; 498 } msdu_pg[MT7996_RRO_MSDU_PG_CR_CNT]; 499 struct { 500 struct mt7996_rro_queue_regs_emi *ptr; 501 dma_addr_t phy_addr; 502 } emi_rings_cpu; 503 struct { 504 struct mt7996_rro_queue_regs_emi *ptr; 505 dma_addr_t phy_addr; 506 } emi_rings_dma; 507 508 struct work_struct work; 509 struct list_head poll_list; 510 spinlock_t lock; 511 512 struct list_head page_cache; 513 struct list_head page_map[MT7996_RRO_MSDU_PG_HASH_SIZE]; 514 } wed_rro; 515 516 dma_addr_t npu_txd_addr[2 * MT7996_NPU_TXD_SIZE]; 517 518 bool ibf; 519 u8 fw_debug_wm; 520 u8 fw_debug_wa; 521 u8 fw_debug_bin; 522 u16 fw_debug_seq; 523 524 struct dentry *debugfs_dir; 525 struct rchan *relay_fwlog; 526 527 struct { 528 u16 table_mask; 529 u8 n_agrt; 530 } twt; 531 532 spinlock_t reg_lock; 533 534 u8 wtbl_size_group; 535 struct { 536 u8 type:4; 537 u8 fem:4; 538 } var; 539 }; 540 541 enum { 542 WFDMA0 = 0x0, 543 WFDMA1, 544 WFDMA_EXT, 545 __MT_WFDMA_MAX, 546 }; 547 548 enum rdd_idx { 549 MT_RDD_IDX_BAND2, /* RDD idx for band idx 2 */ 550 MT_RDD_IDX_BAND1, /* RDD idx for band idx 1 */ 551 MT_RDD_IDX_BACKGROUND, /* RDD idx for background chain */ 552 }; 553 554 enum mt7996_rdd_cmd { 555 RDD_STOP, 556 RDD_START, 557 RDD_DET_MODE, 558 RDD_RADAR_EMULATE, 559 RDD_START_TXQ = 20, 560 RDD_CAC_START = 50, 561 RDD_CAC_END, 562 RDD_NORMAL_START, 563 RDD_DISABLE_DFS_CAL, 564 RDD_PULSE_DBG, 565 RDD_READ_PULSE, 566 RDD_RESUME_BF, 567 RDD_IRQ_OFF, 568 }; 569 570 static inline int 571 mt7996_get_rdd_idx(struct mt7996_phy *phy, bool is_background) 572 { 573 if (!phy->mt76->cap.has_5ghz) 574 return -1; 575 576 if (is_background) 577 return MT_RDD_IDX_BACKGROUND; 578 579 if (phy->mt76->band_idx == MT_BAND2) 580 return MT_RDD_IDX_BAND2; 581 582 return MT_RDD_IDX_BAND1; 583 } 584 585 static inline struct mt7996_dev * 586 mt7996_hw_dev(struct ieee80211_hw *hw) 587 { 588 struct mt76_phy *phy = hw->priv; 589 590 return container_of(phy->dev, struct mt7996_dev, mt76); 591 } 592 593 static inline struct mt7996_phy * 594 __mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band) 595 { 596 struct mt76_phy *phy = dev->mt76.phys[band]; 597 598 if (!phy) 599 return NULL; 600 601 return phy->priv; 602 } 603 604 static inline struct mt7996_phy * 605 mt7996_phy2(struct mt7996_dev *dev) 606 { 607 return __mt7996_phy(dev, MT_BAND1); 608 } 609 610 static inline struct mt7996_phy * 611 mt7996_phy3(struct mt7996_dev *dev) 612 { 613 return __mt7996_phy(dev, MT_BAND2); 614 } 615 616 static inline bool 617 mt7996_band_valid(struct mt7996_dev *dev, u8 band) 618 { 619 if (!is_mt7996(&dev->mt76)) 620 return band <= MT_BAND1; 621 622 return band <= MT_BAND2; 623 } 624 625 static inline struct mt7996_phy * 626 mt7996_band_phy(struct mt7996_dev *dev, enum nl80211_band band) 627 { 628 struct mt76_phy *mphy; 629 630 mphy = dev->mt76.band_phys[band]; 631 if (!mphy) 632 return NULL; 633 634 return mphy->priv; 635 } 636 637 static inline struct mt7996_vif_link * 638 mt7996_vif_link(struct mt7996_dev *dev, struct ieee80211_vif *vif, int link_id) 639 { 640 return (struct mt7996_vif_link *)mt76_vif_link(&dev->mt76, vif, link_id); 641 } 642 643 static inline struct mt7996_phy * 644 mt7996_vif_link_phy(struct mt7996_vif_link *link) 645 { 646 struct mt76_phy *mphy = mt76_vif_link_phy(&link->mt76); 647 648 if (!mphy) 649 return NULL; 650 651 return mphy->priv; 652 } 653 654 static inline struct mt7996_vif_link * 655 mt7996_vif_conf_link(struct mt7996_dev *dev, struct ieee80211_vif *vif, 656 struct ieee80211_bss_conf *link_conf) 657 { 658 return (struct mt7996_vif_link *)mt76_vif_conf_link(&dev->mt76, vif, 659 link_conf); 660 } 661 662 static inline struct mt76_vif_link * 663 mt7996_offchannel_link(struct mt76_wcid *wcid) 664 { 665 struct mt7996_sta_link *msta_link; 666 struct mt7996_vif_link *link; 667 668 msta_link = container_of(wcid, struct mt7996_sta_link, wcid); 669 link = container_of(msta_link, struct mt7996_vif_link, msta_link); 670 671 return &link->mt76; 672 } 673 674 static inline struct mt7996_sta_link * 675 mt7996_sta_link(struct mt7996_sta *msta, u8 link_id) 676 { 677 if (link_id >= IEEE80211_MLD_MAX_NUM_LINKS) 678 return NULL; 679 680 return rcu_dereference(msta->link[link_id]); 681 } 682 683 static inline struct mt7996_sta_link * 684 mt7996_sta_link_protected(struct mt7996_dev *dev, struct mt7996_sta *msta, 685 u8 link_id) 686 { 687 if (link_id >= IEEE80211_MLD_MAX_NUM_LINKS) 688 return NULL; 689 690 return mt76_dereference(msta->link[link_id], &dev->mt76); 691 } 692 693 #define mt7996_for_each_phy(dev, phy) \ 694 for (int __i = 0; __i < ARRAY_SIZE((dev)->radio_phy); __i++) \ 695 if (((phy) = (dev)->radio_phy[__i]) != NULL) 696 697 extern const struct ieee80211_ops mt7996_ops; 698 extern struct pci_driver mt7996_pci_driver; 699 extern struct pci_driver mt7996_hif_driver; 700 701 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, 702 void __iomem *mem_base, u32 device_id); 703 void mt7996_rro_hw_init(struct mt7996_dev *dev); 704 void mt7996_wfsys_reset(struct mt7996_dev *dev); 705 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance); 706 u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif_link *link); 707 int mt7996_register_device(struct mt7996_dev *dev); 708 void mt7996_unregister_device(struct mt7996_dev *dev); 709 int mt7996_vif_link_add(struct mt76_phy *mphy, struct ieee80211_vif *vif, 710 struct ieee80211_bss_conf *link_conf, 711 struct mt76_vif_link *mlink); 712 void mt7996_vif_link_remove(struct mt76_phy *mphy, struct ieee80211_vif *vif, 713 struct ieee80211_bss_conf *link_conf, 714 struct mt76_vif_link *mlink); 715 int mt7996_eeprom_init(struct mt7996_dev *dev); 716 int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy); 717 int mt7996_eeprom_get_target_power(struct mt7996_dev *dev, 718 struct ieee80211_channel *chan); 719 s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band); 720 bool mt7996_eeprom_has_background_radar(struct mt7996_dev *dev); 721 int mt7996_dma_init(struct mt7996_dev *dev); 722 void mt7996_dma_reset(struct mt7996_dev *dev, bool force); 723 void mt7996_dma_prefetch(struct mt7996_dev *dev); 724 void mt7996_dma_cleanup(struct mt7996_dev *dev); 725 void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset); 726 int mt7996_init_tx_queues(struct mt7996_phy *phy, int idx, 727 int n_desc, int ring_base, struct mtk_wed_device *wed); 728 void mt7996_init_txpower(struct mt7996_phy *phy); 729 int mt7996_txbf_init(struct mt7996_dev *dev); 730 void mt7996_reset(struct mt7996_dev *dev); 731 int mt7996_run(struct mt7996_phy *phy); 732 int mt7996_mcu_init(struct mt7996_dev *dev); 733 int mt7996_mcu_init_firmware(struct mt7996_dev *dev); 734 int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev, 735 struct mt7996_vif_link *link, 736 struct mt7996_twt_flow *flow, 737 int cmd); 738 int mt7996_mcu_add_dev_info(struct mt7996_phy *phy, struct ieee80211_vif *vif, 739 struct ieee80211_bss_conf *link_conf, 740 struct mt76_vif_link *mlink, bool enable); 741 int mt7996_mcu_add_bss_info(struct mt7996_phy *phy, struct ieee80211_vif *vif, 742 struct ieee80211_bss_conf *link_conf, 743 struct mt76_vif_link *mlink, 744 struct mt7996_sta_link *msta_link, int enable); 745 int mt7996_mcu_update_bss_rfch(struct mt7996_phy *phy, 746 struct mt7996_vif_link *link); 747 int mt7996_mcu_add_sta(struct mt7996_dev *dev, 748 struct ieee80211_bss_conf *link_conf, 749 struct ieee80211_link_sta *link_sta, 750 struct mt7996_vif_link *link, 751 struct mt7996_sta_link *msta_link, 752 int conn_state, bool newly); 753 int mt7996_mcu_teardown_mld_sta(struct mt7996_dev *dev, 754 struct mt7996_vif_link *link, 755 struct mt7996_sta_link *msta_link); 756 int mt7996_mcu_update_mld_sta(struct mt7996_dev *dev, 757 struct ieee80211_vif *vif, 758 struct ieee80211_sta *sta, 759 struct mt7996_vif_link *link, 760 struct mt7996_sta_link *msta_link); 761 void mt7996_mcu_update_sta_rec_bw(void *data, struct ieee80211_sta *sta); 762 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev, 763 struct ieee80211_ampdu_params *params, 764 struct ieee80211_vif *vif, unsigned long links, 765 bool enable); 766 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev, 767 struct ieee80211_ampdu_params *params, 768 struct ieee80211_vif *vif, unsigned long links, 769 bool enable); 770 int mt7996_mcu_update_bss_color(struct mt7996_dev *dev, 771 struct mt76_vif_link *mlink, 772 struct cfg80211_he_bss_color *he_bss_color); 773 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 774 struct ieee80211_bss_conf *link_conf, bool enabled); 775 int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev, 776 struct ieee80211_bss_conf *link_conf, 777 struct mt7996_vif_link *link, u32 changed); 778 int mt7996_mcu_add_obss_spr(struct mt7996_phy *phy, 779 struct mt7996_vif_link *link, 780 struct ieee80211_he_obss_pd *he_obss_pd); 781 int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct mt7996_sta *msta, 782 struct ieee80211_vif *vif, u8 link_id, 783 bool changed); 784 int mt7996_set_channel(struct mt76_phy *mphy); 785 int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag); 786 int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif, 787 struct ieee80211_bss_conf *link_conf); 788 int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev, 789 void *data, u16 version); 790 int mt7996_mcu_set_fixed_field(struct mt7996_dev *dev, struct mt7996_sta *msta, 791 void *data, u8 link_id, u32 field); 792 int mt7996_mcu_set_eeprom(struct mt7996_dev *dev); 793 int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset, u8 *buf, u32 buf_len, 794 enum mt7996_eeprom_mode mode); 795 int mt7996_mcu_get_efuse_free_block(struct mt7996_dev *dev, u8 *block_num); 796 int mt7996_mcu_get_chip_config(struct mt7996_dev *dev, u32 *cap); 797 int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band); 798 int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action); 799 int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val); 800 int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev, 801 const struct mt7996_dfs_pulse *pulse); 802 int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index, 803 const struct mt7996_dfs_pattern *pattern); 804 int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable); 805 int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val); 806 int mt7996_mcu_set_protection(struct mt7996_phy *phy, struct mt7996_vif_link *link, 807 u8 ht_mode, bool use_cts_prot); 808 int mt7996_mcu_set_timing(struct mt7996_phy *phy, struct ieee80211_vif *vif, 809 struct ieee80211_bss_conf *link_conf); 810 int mt7996_mcu_set_bssid_mapping_addr(struct mt76_dev *dev, u8 band_idx); 811 int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch); 812 int mt7996_mcu_get_temperature(struct mt7996_phy *phy); 813 int mt7996_mcu_set_thermal_throttling(struct mt7996_phy *phy, u8 state); 814 int mt7996_mcu_set_thermal_protect(struct mt7996_phy *phy, bool enable); 815 int mt7996_mcu_set_txpower_sku(struct mt7996_phy *phy); 816 int mt7996_mcu_set_tx_power_ctrl(struct mt7996_phy *phy, u8 power_ctrl_id, u8 data); 817 int mt7996_mcu_rdd_resume_tx(struct mt7996_phy *phy); 818 int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 rdd_idx, u8 val); 819 int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy, 820 struct cfg80211_chan_def *chandef); 821 int mt7996_mcu_set_fixed_rate_table(struct mt7996_phy *phy, u8 table_idx, 822 u16 rate_idx, bool beacon); 823 int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set); 824 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans); 825 int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u16 val); 826 int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3); 827 int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl); 828 int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level); 829 int mt7996_mcu_trigger_assert(struct mt7996_dev *dev); 830 void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb); 831 void mt7996_mcu_exit(struct mt7996_dev *dev); 832 int mt7996_mcu_get_all_sta_info(struct mt7996_phy *phy, u16 tag); 833 int mt7996_mcu_wed_rro_reset_sessions(struct mt7996_dev *dev, u16 id); 834 int mt7996_mcu_set_sniffer_mode(struct mt7996_phy *phy, bool enabled); 835 int mt7996_mcu_set_dup_wtbl(struct mt7996_dev *dev); 836 int mt7996_mcu_mld_reconf_stop_link(struct mt7996_dev *dev, 837 struct ieee80211_vif *vif, 838 u16 removed_links); 839 int mt7996_mcu_mld_link_oper(struct mt7996_dev *dev, 840 struct ieee80211_bss_conf *link_conf, 841 struct mt7996_vif_link *link, bool add); 842 843 static inline bool mt7996_has_hwrro(struct mt7996_dev *dev) 844 { 845 return dev->mt76.hwrro_mode != MT76_HWRRO_OFF; 846 } 847 848 static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev) 849 { 850 return min(MT7996_MAX_INTERFACES * (1 + mt7996_band_valid(dev, MT_BAND1) + 851 mt7996_band_valid(dev, MT_BAND2)), 852 MT7996_WTBL_BMC_SIZE); 853 } 854 855 static inline u16 mt7996_wtbl_size(struct mt7996_dev *dev) 856 { 857 return (dev->wtbl_size_group << 8) + MT7996_WTBL_BMC_SIZE; 858 } 859 860 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg, 861 u32 clear, u32 set); 862 863 static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask) 864 { 865 if (dev->hif2) 866 mt7996_dual_hif_set_irq_mask(dev, false, 0, mask); 867 else 868 mt76_set_irq_mask(&dev->mt76, 0, 0, mask); 869 870 tasklet_schedule(&dev->mt76.irq_tasklet); 871 } 872 873 static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask) 874 { 875 if (dev->hif2) 876 mt7996_dual_hif_set_irq_mask(dev, true, mask, 0); 877 else 878 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); 879 } 880 881 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset, 882 size_t len); 883 884 static inline u16 mt7996_rx_chainmask(struct mt7996_phy *phy) 885 { 886 int max_nss = hweight16(phy->orig_antenna_mask); 887 int cur_nss = hweight8(phy->mt76->antenna_mask); 888 u16 tx_chainmask = phy->mt76->chainmask; 889 890 if (cur_nss != max_nss) 891 return tx_chainmask; 892 893 return tx_chainmask | (BIT(fls(tx_chainmask)) * phy->has_aux_rx); 894 } 895 896 static inline bool mt7996_has_wa(struct mt7996_dev *dev) 897 { 898 return !is_mt7990(&dev->mt76); 899 } 900 901 static inline bool mt7996_has_ext_eeprom(struct mt7996_dev *dev) 902 { 903 return !is_mt7996(&dev->mt76); 904 } 905 906 void mt7996_mac_init(struct mt7996_dev *dev); 907 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw); 908 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask); 909 void mt7996_mac_reset_counters(struct mt7996_phy *phy); 910 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy); 911 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band); 912 struct mt76_wcid *mt7996_get_tx_wcid(struct mt76_wcid *wcid); 913 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi, 914 struct sk_buff *skb, struct mt76_wcid *wcid, 915 struct ieee80211_key_conf *key, int pid, 916 enum mt76_txq_id qid, u32 changed, 917 unsigned int link_id); 918 void mt7996_mac_update_beacons(struct mt7996_phy *phy); 919 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy); 920 void mt7996_mac_work(struct work_struct *work); 921 void mt7996_mac_reset_work(struct work_struct *work); 922 void mt7996_mac_dump_work(struct work_struct *work); 923 void mt7996_mac_sta_rc_work(struct work_struct *work); 924 void mt7996_mac_update_stats(struct mt7996_phy *phy); 925 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev, 926 struct mt7996_vif_link *link, 927 struct mt7996_sta_link *msta_link, 928 u8 flowid); 929 void mt7996_mac_sta_remove_link(struct mt7996_dev *dev, 930 struct ieee80211_sta *sta, 931 unsigned int link_id, bool flush); 932 u16 mt7996_mac_sta_links(struct mt7996_dev *dev, struct ieee80211_vif *vif, 933 struct ieee80211_sta *sta); 934 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw, 935 struct ieee80211_sta *sta, 936 struct ieee80211_twt_setup *twt); 937 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 938 enum mt76_txq_id qid, struct mt76_wcid *wcid, 939 struct ieee80211_sta *sta, 940 struct mt76_tx_info *tx_info); 941 void mt7996_tx_token_put(struct mt7996_dev *dev); 942 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 943 struct sk_buff *skb, u32 *info); 944 void mt7996_rro_msdu_page_map_free(struct mt7996_dev *dev); 945 int mt7996_rro_msdu_page_add(struct mt76_dev *mdev, struct mt76_queue *q, 946 dma_addr_t dma_addr, void *data); 947 void mt7996_rro_rx_process(struct mt76_dev *mdev, void *data); 948 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len); 949 void mt7996_stats_work(struct work_struct *work); 950 int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force); 951 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy); 952 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy); 953 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy); 954 void mt7996_update_channel(struct mt76_phy *mphy); 955 int mt7996_init_debugfs(struct mt7996_dev *dev); 956 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len); 957 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len); 958 int mt7996_mcu_add_key(struct mt76_dev *dev, struct mt7996_vif_link *link, 959 struct ieee80211_key_conf *key, int mcu_cmd, 960 struct mt76_wcid *wcid, enum set_key_cmd cmd); 961 int mt7996_mcu_bcn_prot_enable(struct mt7996_dev *dev, 962 struct mt7996_vif_link *link, 963 struct mt7996_sta_link *msta_link, 964 struct ieee80211_key_conf *key); 965 int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev, 966 struct ieee80211_vif *vif, 967 struct mt7996_vif_link *link, 968 struct mt7996_sta_link *msta_link); 969 int mt7996_mcu_ps_leave(struct mt7996_dev *dev, struct mt7996_vif_link *link, 970 struct mt7996_sta_link *msta_link); 971 int mt7996_mcu_cp_support(struct mt7996_dev *dev, u8 mode); 972 int mt7996_mcu_set_emlsr_mode(struct mt7996_dev *dev, 973 struct ieee80211_vif *vif, 974 struct ieee80211_sta *sta, 975 struct ieee80211_eml_params *eml_params); 976 #ifdef CONFIG_MAC80211_DEBUGFS 977 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 978 struct ieee80211_sta *sta, struct dentry *dir); 979 void mt7996_link_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 980 struct ieee80211_link_sta *link_sta, 981 struct dentry *dir); 982 #endif 983 int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr, 984 bool hif2, int *irq); 985 u32 mt7996_wed_init_buf(void *ptr, dma_addr_t phys, int token_id); 986 987 int mt7996_dma_rro_init(struct mt7996_dev *dev); 988 void mt7996_dma_rro_start(struct mt7996_dev *dev); 989 990 #ifdef CONFIG_MT7996_NPU 991 int __mt7996_npu_hw_init(struct mt7996_dev *dev); 992 int mt7996_npu_hw_init(struct mt7996_dev *dev); 993 int mt7996_npu_hw_stop(struct mt7996_dev *dev); 994 int mt7996_npu_rx_queues_init(struct mt7996_dev *dev); 995 #else 996 static inline int __mt7996_npu_hw_init(struct mt7996_dev *dev) 997 { 998 return 0; 999 } 1000 1001 static inline int mt7996_npu_hw_init(struct mt7996_dev *dev) 1002 { 1003 return 0; 1004 } 1005 1006 static inline int mt7996_npu_hw_stop(struct mt7996_dev *dev) 1007 { 1008 return 0; 1009 } 1010 1011 static inline int mt7996_npu_rx_queues_init(struct mt7996_dev *dev) 1012 { 1013 return 0; 1014 } 1015 #endif /* CONFIG_MT7996_NPU */ 1016 1017 #endif 1018