1 /* 2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "df_v4_15.h" 41 #include "nbio_v6_1.h" 42 #include "nbio_v7_0.h" 43 #include "nbio_v7_4.h" 44 #include "nbio_v7_9.h" 45 #include "nbio_v7_11.h" 46 #include "hdp_v4_0.h" 47 #include "vega10_ih.h" 48 #include "vega20_ih.h" 49 #include "sdma_v4_0.h" 50 #include "sdma_v4_4_2.h" 51 #include "uvd_v7_0.h" 52 #include "vce_v4_0.h" 53 #include "vcn_v1_0.h" 54 #include "vcn_v2_5.h" 55 #include "jpeg_v2_5.h" 56 #include "smuio_v9_0.h" 57 #include "gmc_v10_0.h" 58 #include "gmc_v11_0.h" 59 #include "gmc_v12_0.h" 60 #include "gfxhub_v2_0.h" 61 #include "mmhub_v2_0.h" 62 #include "nbio_v2_3.h" 63 #include "nbio_v4_3.h" 64 #include "nbio_v7_2.h" 65 #include "nbio_v7_7.h" 66 #include "nbif_v6_3_1.h" 67 #include "nbio_v6_3_2.h" 68 #include "hdp_v5_0.h" 69 #include "hdp_v5_2.h" 70 #include "hdp_v6_0.h" 71 #include "hdp_v7_0.h" 72 #include "nv.h" 73 #include "soc21.h" 74 #include "soc24.h" 75 #include "soc_v1_0.h" 76 #include "navi10_ih.h" 77 #include "ih_v6_0.h" 78 #include "ih_v6_1.h" 79 #include "ih_v7_0.h" 80 #include "gfx_v10_0.h" 81 #include "gfx_v11_0.h" 82 #include "gfx_v12_0.h" 83 #include "gfx_v12_1.h" 84 #include "sdma_v5_0.h" 85 #include "sdma_v5_2.h" 86 #include "sdma_v6_0.h" 87 #include "sdma_v7_0.h" 88 #include "sdma_v7_1.h" 89 #include "lsdma_v6_0.h" 90 #include "lsdma_v7_0.h" 91 #include "lsdma_v7_1.h" 92 #include "vcn_v2_0.h" 93 #include "jpeg_v2_0.h" 94 #include "vcn_v3_0.h" 95 #include "jpeg_v3_0.h" 96 #include "vcn_v4_0.h" 97 #include "jpeg_v4_0.h" 98 #include "vcn_v4_0_3.h" 99 #include "jpeg_v4_0_3.h" 100 #include "vcn_v4_0_5.h" 101 #include "jpeg_v4_0_5.h" 102 #include "amdgpu_vkms.h" 103 #include "mes_v11_0.h" 104 #include "mes_v12_0.h" 105 #include "mes_v12_1.h" 106 #include "smuio_v11_0.h" 107 #include "smuio_v11_0_6.h" 108 #include "smuio_v13_0.h" 109 #include "smuio_v13_0_3.h" 110 #include "smuio_v13_0_6.h" 111 #include "smuio_v14_0_2.h" 112 #include "smuio_v15_0_0.h" 113 #include "smuio_v15_0_8.h" 114 #include "vcn_v5_0_0.h" 115 #include "vcn_v5_0_1.h" 116 #include "vcn_v5_0_2.h" 117 #include "jpeg_v5_0_0.h" 118 #include "jpeg_v5_0_1.h" 119 #include "jpeg_v5_0_2.h" 120 #include "jpeg_v5_3_0.h" 121 122 #include "amdgpu_ras_mgr.h" 123 124 #include "amdgpu_vpe.h" 125 #if defined(CONFIG_DRM_AMD_ISP) 126 #include "amdgpu_isp.h" 127 #endif 128 129 MODULE_FIRMWARE("amdgpu/ip_discovery.bin"); 130 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin"); 131 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin"); 132 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin"); 133 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin"); 134 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin"); 135 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin"); 136 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin"); 137 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); 138 139 /* Note: These registers are consistent across all the SOCs */ 140 #define mmIP_DISCOVERY_VERSION 0x16A00 141 #define mmRCC_CONFIG_MEMSIZE 0xde3 142 #define mmMP0_SMN_C2PMSG_33 0x16061 143 #define mmMM_INDEX 0x0 144 #define mmMM_INDEX_HI 0x6 145 #define mmMM_DATA 0x1 146 147 #define mmDRIVER_SCRATCH_0 0x94 148 #define mmDRIVER_SCRATCH_1 0x95 149 #define mmDRIVER_SCRATCH_2 0x96 150 151 static const char *hw_id_names[HW_ID_MAX] = { 152 [MP1_HWID] = "MP1", 153 [MP2_HWID] = "MP2", 154 [THM_HWID] = "THM", 155 [SMUIO_HWID] = "SMUIO", 156 [FUSE_HWID] = "FUSE", 157 [CLKA_HWID] = "CLKA", 158 [PWR_HWID] = "PWR", 159 [GC_HWID] = "GC", 160 [UVD_HWID] = "UVD", 161 [AUDIO_AZ_HWID] = "AUDIO_AZ", 162 [ACP_HWID] = "ACP", 163 [DCI_HWID] = "DCI", 164 [DMU_HWID] = "DMU", 165 [DCO_HWID] = "DCO", 166 [DIO_HWID] = "DIO", 167 [XDMA_HWID] = "XDMA", 168 [DCEAZ_HWID] = "DCEAZ", 169 [DAZ_HWID] = "DAZ", 170 [SDPMUX_HWID] = "SDPMUX", 171 [NTB_HWID] = "NTB", 172 [IOHC_HWID] = "IOHC", 173 [L2IMU_HWID] = "L2IMU", 174 [VCE_HWID] = "VCE", 175 [MMHUB_HWID] = "MMHUB", 176 [ATHUB_HWID] = "ATHUB", 177 [DBGU_NBIO_HWID] = "DBGU_NBIO", 178 [DFX_HWID] = "DFX", 179 [DBGU0_HWID] = "DBGU0", 180 [DBGU1_HWID] = "DBGU1", 181 [OSSSYS_HWID] = "OSSSYS", 182 [HDP_HWID] = "HDP", 183 [SDMA0_HWID] = "SDMA0", 184 [SDMA1_HWID] = "SDMA1", 185 [SDMA2_HWID] = "SDMA2", 186 [SDMA3_HWID] = "SDMA3", 187 [LSDMA_HWID] = "LSDMA", 188 [ISP_HWID] = "ISP", 189 [DBGU_IO_HWID] = "DBGU_IO", 190 [DF_HWID] = "DF", 191 [CLKB_HWID] = "CLKB", 192 [FCH_HWID] = "FCH", 193 [DFX_DAP_HWID] = "DFX_DAP", 194 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 195 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 196 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 197 [L1IMU3_HWID] = "L1IMU3", 198 [L1IMU4_HWID] = "L1IMU4", 199 [L1IMU5_HWID] = "L1IMU5", 200 [L1IMU6_HWID] = "L1IMU6", 201 [L1IMU7_HWID] = "L1IMU7", 202 [L1IMU8_HWID] = "L1IMU8", 203 [L1IMU9_HWID] = "L1IMU9", 204 [L1IMU10_HWID] = "L1IMU10", 205 [L1IMU11_HWID] = "L1IMU11", 206 [L1IMU12_HWID] = "L1IMU12", 207 [L1IMU13_HWID] = "L1IMU13", 208 [L1IMU14_HWID] = "L1IMU14", 209 [L1IMU15_HWID] = "L1IMU15", 210 [WAFLC_HWID] = "WAFLC", 211 [FCH_USB_PD_HWID] = "FCH_USB_PD", 212 [PCIE_HWID] = "PCIE", 213 [PCS_HWID] = "PCS", 214 [DDCL_HWID] = "DDCL", 215 [SST_HWID] = "SST", 216 [IOAGR_HWID] = "IOAGR", 217 [NBIF_HWID] = "NBIF", 218 [IOAPIC_HWID] = "IOAPIC", 219 [SYSTEMHUB_HWID] = "SYSTEMHUB", 220 [NTBCCP_HWID] = "NTBCCP", 221 [UMC_HWID] = "UMC", 222 [SATA_HWID] = "SATA", 223 [USB_HWID] = "USB", 224 [CCXSEC_HWID] = "CCXSEC", 225 [XGMI_HWID] = "XGMI", 226 [XGBE_HWID] = "XGBE", 227 [MP0_HWID] = "MP0", 228 [VPE_HWID] = "VPE", 229 [ATU_HWID] = "ATU", 230 [AIGC_HWID] = "AIGC", 231 }; 232 233 static int hw_id_map[MAX_HWIP] = { 234 [GC_HWIP] = GC_HWID, 235 [HDP_HWIP] = HDP_HWID, 236 [SDMA0_HWIP] = SDMA0_HWID, 237 [SDMA1_HWIP] = SDMA1_HWID, 238 [SDMA2_HWIP] = SDMA2_HWID, 239 [SDMA3_HWIP] = SDMA3_HWID, 240 [LSDMA_HWIP] = LSDMA_HWID, 241 [MMHUB_HWIP] = MMHUB_HWID, 242 [ATHUB_HWIP] = ATHUB_HWID, 243 [NBIO_HWIP] = NBIF_HWID, 244 [MP0_HWIP] = MP0_HWID, 245 [MP1_HWIP] = MP1_HWID, 246 [UVD_HWIP] = UVD_HWID, 247 [VCE_HWIP] = VCE_HWID, 248 [DF_HWIP] = DF_HWID, 249 [DCE_HWIP] = DMU_HWID, 250 [OSSSYS_HWIP] = OSSSYS_HWID, 251 [SMUIO_HWIP] = SMUIO_HWID, 252 [PWR_HWIP] = PWR_HWID, 253 [NBIF_HWIP] = NBIF_HWID, 254 [THM_HWIP] = THM_HWID, 255 [CLK_HWIP] = CLKA_HWID, 256 [UMC_HWIP] = UMC_HWID, 257 [XGMI_HWIP] = XGMI_HWID, 258 [DCI_HWIP] = DCI_HWID, 259 [PCIE_HWIP] = PCIE_HWID, 260 [VPE_HWIP] = VPE_HWID, 261 [ISP_HWIP] = ISP_HWID, 262 [ATU_HWIP] = ATU_HWID, 263 }; 264 265 static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev, 266 bool *is_tmr_in_sysmem) 267 { 268 u64 vram_size, tmr_offset, tmr_size; 269 u32 msg, tmr_offset_lo, tmr_offset_hi; 270 int i, ret; 271 272 if (!amdgpu_sriov_vf(adev)) { 273 /* It can take up to two second for IFWI init to complete on some dGPUs, 274 * but generally it should be in the 60-100ms range. Normally this starts 275 * as soon as the device gets power so by the time the OS loads this has long 276 * completed. However, when a card is hotplugged via e.g., USB4, we need to 277 * wait for this to complete. Once the C2PMSG is updated, we can 278 * continue. 279 */ 280 281 for (i = 0; i < 2000; i++) { 282 msg = RREG32(mmMP0_SMN_C2PMSG_33); 283 if (msg & 0x80000000) 284 break; 285 msleep(1); 286 } 287 } 288 289 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); 290 if (vram_size == U32_MAX) 291 return -ENXIO; 292 else if (!vram_size) 293 *is_tmr_in_sysmem = true; 294 else 295 *is_tmr_in_sysmem = false; 296 297 /* init the default tmr size and offset */ 298 adev->discovery.size = DISCOVERY_TMR_SIZE; 299 if (vram_size) 300 adev->discovery.offset = (vram_size << 20) - DISCOVERY_TMR_OFFSET; 301 302 if (amdgpu_sriov_vf(adev)) { 303 if (adev->virt.is_dynamic_crit_regn_enabled) { 304 adev->discovery.offset = 305 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset; 306 adev->discovery.size = 307 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10; 308 if (!adev->discovery.size) 309 return -EINVAL; 310 } else { 311 goto out; 312 } 313 } else { 314 tmr_size = RREG32(mmDRIVER_SCRATCH_2); 315 if (tmr_size) { 316 /* It's preferred to transition to PSP mailbox reg interface 317 * for both bare-metal and passthrough if available */ 318 adev->discovery.size = (u32)tmr_size; 319 tmr_offset_lo = RREG32(mmDRIVER_SCRATCH_0); 320 tmr_offset_hi = RREG32(mmDRIVER_SCRATCH_1); 321 adev->discovery.offset = ((u64)le32_to_cpu(tmr_offset_hi) << 32 | 322 le32_to_cpu(tmr_offset_lo)); 323 } else if (!vram_size) { 324 /* fall back to apci approach to query tmr offset if vram_size is 0 */ 325 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 326 if (ret) 327 return ret; 328 adev->discovery.size = DISCOVERY_TMR_SIZE; 329 adev->discovery.offset = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 330 } 331 } 332 out: 333 adev->discovery.bin = kzalloc(adev->discovery.size, GFP_KERNEL); 334 if (!adev->discovery.bin) 335 return -ENOMEM; 336 adev->discovery.debugfs_blob.data = adev->discovery.bin; 337 adev->discovery.debugfs_blob.size = adev->discovery.size; 338 339 return 0; 340 } 341 342 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 343 { 344 void *discv_regn; 345 346 /* This region is read-only and reserved from system use */ 347 discv_regn = memremap(adev->discovery.offset, adev->discovery.size, MEMREMAP_WC); 348 if (discv_regn) { 349 memcpy(binary, discv_regn, adev->discovery.size); 350 memunmap(discv_regn); 351 return 0; 352 } 353 354 return -ENOENT; 355 } 356 357 #define IP_DISCOVERY_V2 2 358 #define IP_DISCOVERY_V4 4 359 360 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 361 uint8_t *binary, 362 bool is_tmr_in_sysmem) 363 { 364 int ret = 0; 365 366 if (!is_tmr_in_sysmem) { 367 if (amdgpu_sriov_vf(adev) && 368 amdgpu_sriov_xgmi_connected_to_cpu(adev)) { 369 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 370 } else { 371 amdgpu_device_vram_access(adev, adev->discovery.offset, 372 (uint32_t *)binary, 373 adev->discovery.size, false); 374 adev->discovery.reserve_tmr = true; 375 } 376 } else { 377 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 378 } 379 380 return ret; 381 } 382 383 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, 384 uint8_t *binary, 385 const char *fw_name) 386 { 387 const struct firmware *fw; 388 int r; 389 390 r = firmware_request_nowarn(&fw, fw_name, adev->dev); 391 if (r) { 392 if (amdgpu_discovery == 2) 393 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name); 394 else 395 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name); 396 return r; 397 } 398 399 if (fw->size > adev->discovery.size) { 400 dev_err(adev->dev, 401 "ip discovery firmware \"%s\" too large (%zu > %u)\n", 402 fw_name, fw->size, adev->discovery.size); 403 release_firmware(fw); 404 return -EINVAL; 405 } 406 407 /* Ensure the firmware is at least large enough to contain the 408 * binary header fields. 409 */ 410 if (fw->size < offsetof(struct binary_header, binary_size) + 411 sizeof(((struct binary_header *)0)->binary_size)) { 412 dev_err(adev->dev, 413 "ip discovery firmware \"%s\" too small (%zu)\n", 414 fw_name, fw->size); 415 release_firmware(fw); 416 return -EINVAL; 417 } 418 419 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 420 release_firmware(fw); 421 422 return 0; 423 } 424 425 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 426 { 427 uint16_t checksum = 0; 428 int i; 429 430 for (i = 0; i < size; i++) 431 checksum += data[i]; 432 433 return checksum; 434 } 435 436 static inline bool amdgpu_discovery_verify_checksum(struct amdgpu_device *adev, 437 uint8_t *data, uint32_t size, 438 uint16_t expected) 439 { 440 uint16_t calculated; 441 442 calculated = amdgpu_discovery_calculate_checksum(data, size); 443 444 if (calculated != expected) { 445 dev_err(adev->dev, "Discovery checksum failed: calc 0x%04x != exp 0x%04x, size %u.\n", 446 calculated, expected, size); 447 return false; 448 } 449 450 return true; 451 } 452 453 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 454 { 455 struct binary_header *bhdr; 456 bhdr = (struct binary_header *)binary; 457 458 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 459 } 460 461 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 462 { 463 /* 464 * So far, apply this quirk only on those Navy Flounder boards which 465 * have a bad harvest table of VCN config. 466 */ 467 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 468 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 469 switch (adev->pdev->revision) { 470 case 0xC1: 471 case 0xC2: 472 case 0xC3: 473 case 0xC5: 474 case 0xC7: 475 case 0xCF: 476 case 0xDF: 477 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 478 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 479 break; 480 default: 481 break; 482 } 483 } 484 } 485 486 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 487 struct table_info *info) 488 { 489 uint8_t *discovery_bin = adev->discovery.bin; 490 uint16_t checksum; 491 uint16_t offset; 492 493 offset = le16_to_cpu(info->offset); 494 checksum = le16_to_cpu(info->checksum); 495 496 struct nps_info_header *nhdr = 497 (struct nps_info_header *)(discovery_bin + offset); 498 499 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 500 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 501 return -EINVAL; 502 } 503 504 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 505 le32_to_cpu(nhdr->size_bytes), 506 checksum)) { 507 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 508 return -EINVAL; 509 } 510 511 return 0; 512 } 513 514 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) 515 { 516 if (amdgpu_discovery == 2) { 517 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */ 518 adev->discovery.reserve_tmr = true; 519 return "amdgpu/ip_discovery.bin"; 520 } 521 522 switch (adev->asic_type) { 523 case CHIP_VEGA10: 524 return "amdgpu/vega10_ip_discovery.bin"; 525 case CHIP_VEGA12: 526 return "amdgpu/vega12_ip_discovery.bin"; 527 case CHIP_RAVEN: 528 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 529 return "amdgpu/raven2_ip_discovery.bin"; 530 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 531 return "amdgpu/picasso_ip_discovery.bin"; 532 else 533 return "amdgpu/raven_ip_discovery.bin"; 534 case CHIP_VEGA20: 535 return "amdgpu/vega20_ip_discovery.bin"; 536 case CHIP_ARCTURUS: 537 return "amdgpu/arcturus_ip_discovery.bin"; 538 case CHIP_ALDEBARAN: 539 return "amdgpu/aldebaran_ip_discovery.bin"; 540 default: 541 return NULL; 542 } 543 } 544 545 static int amdgpu_discovery_get_table_info(struct amdgpu_device *adev, 546 struct table_info **info, 547 uint16_t table_id) 548 { 549 struct binary_header *bhdr = 550 (struct binary_header *)adev->discovery.bin; 551 struct binary_header_v2 *bhdrv2; 552 553 switch (bhdr->version_major) { 554 case 2: 555 bhdrv2 = (struct binary_header_v2 *)adev->discovery.bin; 556 *info = &bhdrv2->table_list[table_id]; 557 break; 558 case 1: 559 case 0: 560 *info = &bhdr->table_list[table_id]; 561 break; 562 default: 563 dev_err(adev->dev, "Invalid ip discovery table version %d\n",bhdr->version_major); 564 return -EINVAL; 565 } 566 567 return 0; 568 } 569 570 static int amdgpu_discovery_table_check(struct amdgpu_device *adev, 571 uint8_t *discovery_bin, 572 uint16_t table_id) 573 { 574 int r, act_val, exp_val, table_size; 575 uint16_t offset, checksum; 576 struct table_info *info; 577 bool check_table = true; 578 char *table_name; 579 580 r = amdgpu_discovery_get_table_info(adev, &info, table_id); 581 if (r) 582 return r; 583 offset = le16_to_cpu(info->offset); 584 checksum = le16_to_cpu(info->checksum); 585 586 switch (table_id) { 587 case IP_DISCOVERY: { 588 struct ip_discovery_header *ihdr = 589 (struct ip_discovery_header *)(discovery_bin + offset); 590 act_val = le32_to_cpu(ihdr->signature); 591 exp_val = DISCOVERY_TABLE_SIGNATURE; 592 table_size = le16_to_cpu(ihdr->size); 593 table_name = "data table"; 594 break; 595 } 596 case GC: { 597 struct gpu_info_header *ghdr = 598 (struct gpu_info_header *)(discovery_bin + offset); 599 act_val = le32_to_cpu(ghdr->table_id); 600 exp_val = GC_TABLE_ID; 601 table_size = le16_to_cpu(ghdr->size); 602 table_name = "gc table"; 603 break; 604 } 605 case HARVEST_INFO: { 606 struct harvest_info_header *hhdr = 607 (struct harvest_info_header *)(discovery_bin + offset); 608 act_val = le32_to_cpu(hhdr->signature); 609 exp_val = HARVEST_TABLE_SIGNATURE; 610 table_size = sizeof(struct harvest_table); 611 table_name = "harvest table"; 612 break; 613 } 614 case VCN_INFO: { 615 struct vcn_info_header *vhdr = 616 (struct vcn_info_header *)(discovery_bin + offset); 617 act_val = le32_to_cpu(vhdr->table_id); 618 exp_val = VCN_INFO_TABLE_ID; 619 table_size = le32_to_cpu(vhdr->size_bytes); 620 table_name = "vcn table"; 621 break; 622 } 623 case MALL_INFO: { 624 struct mall_info_header *mhdr = 625 (struct mall_info_header *)(discovery_bin + offset); 626 act_val = le32_to_cpu(mhdr->table_id); 627 exp_val = MALL_INFO_TABLE_ID; 628 table_size = le32_to_cpu(mhdr->size_bytes); 629 table_name = "mall table"; 630 check_table = false; 631 break; 632 } 633 default: 634 dev_err(adev->dev, "invalid ip discovery table id %d specified\n", table_id); 635 check_table = false; 636 break; 637 } 638 639 if (check_table && offset) { 640 if (act_val != exp_val) { 641 dev_err(adev->dev, "invalid ip discovery %s signature\n", table_name); 642 return -EINVAL; 643 } 644 645 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 646 table_size, checksum)) { 647 dev_err(adev->dev, "invalid ip discovery %s checksum\n", table_name); 648 return -EINVAL; 649 } 650 } 651 652 return 0; 653 } 654 655 static int amdgpu_discovery_init(struct amdgpu_device *adev) 656 { 657 struct binary_header *bhdr; 658 uint8_t *discovery_bin; 659 const char *fw_name; 660 uint16_t offset; 661 uint16_t size; 662 uint16_t checksum; 663 uint16_t table_id; 664 bool is_tmr_in_sysmem; 665 int r; 666 667 r = amdgpu_discovery_get_tmr_info(adev, &is_tmr_in_sysmem); 668 if (r) 669 return r; 670 671 discovery_bin = adev->discovery.bin; 672 /* Read from file if it is the preferred option */ 673 fw_name = amdgpu_discovery_get_fw_name(adev); 674 if (fw_name != NULL) { 675 drm_dbg(&adev->ddev, "use ip discovery information from file"); 676 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin, 677 fw_name); 678 if (r) 679 goto out; 680 } else { 681 drm_dbg(&adev->ddev, "use ip discovery information from memory"); 682 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin, 683 is_tmr_in_sysmem); 684 if (r) 685 goto out; 686 } 687 688 /* check the ip discovery binary signature */ 689 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) { 690 dev_err(adev->dev, 691 "get invalid ip discovery binary signature\n"); 692 r = -EINVAL; 693 goto out; 694 } 695 696 bhdr = (struct binary_header *)discovery_bin; 697 698 offset = offsetof(struct binary_header, binary_checksum) + 699 sizeof(bhdr->binary_checksum); 700 size = le16_to_cpu(bhdr->binary_size) - offset; 701 checksum = le16_to_cpu(bhdr->binary_checksum); 702 703 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, size, 704 checksum)) { 705 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 706 r = -EINVAL; 707 goto out; 708 } 709 710 for (table_id = 0; table_id <= MALL_INFO; table_id++) { 711 r = amdgpu_discovery_table_check(adev, discovery_bin, table_id); 712 if (r) 713 goto out; 714 } 715 716 return 0; 717 718 out: 719 kfree(adev->discovery.bin); 720 adev->discovery.bin = NULL; 721 if ((amdgpu_discovery != 2) && 722 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 723 amdgpu_ras_query_boot_status(adev, 4); 724 return r; 725 } 726 727 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 728 729 void amdgpu_discovery_fini(struct amdgpu_device *adev) 730 { 731 amdgpu_discovery_sysfs_fini(adev); 732 kfree(adev->discovery.bin); 733 adev->discovery.bin = NULL; 734 } 735 736 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, 737 uint8_t instance, uint16_t hw_id) 738 { 739 if (instance >= HWIP_MAX_INSTANCE) { 740 dev_err(adev->dev, 741 "Unexpected instance_number (%d) from ip discovery blob\n", 742 instance); 743 return -EINVAL; 744 } 745 if (hw_id >= HW_ID_MAX) { 746 dev_err(adev->dev, 747 "Unexpected hw_id (%d) from ip discovery blob\n", 748 hw_id); 749 return -EINVAL; 750 } 751 752 return 0; 753 } 754 755 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 756 uint32_t *vcn_harvest_count) 757 { 758 uint8_t *discovery_bin = adev->discovery.bin; 759 struct binary_header *bhdr; 760 struct ip_discovery_header *ihdr; 761 struct die_header *dhdr; 762 struct ip *ip; 763 uint16_t die_offset, ip_offset, num_dies, num_ips; 764 uint16_t hw_id; 765 uint8_t inst; 766 int i, j; 767 768 bhdr = (struct binary_header *)discovery_bin; 769 ihdr = (struct ip_discovery_header 770 *)(discovery_bin + 771 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 772 num_dies = le16_to_cpu(ihdr->num_dies); 773 774 /* scan harvest bit of all IP data structures */ 775 for (i = 0; i < num_dies; i++) { 776 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 777 dhdr = (struct die_header *)(discovery_bin + die_offset); 778 num_ips = le16_to_cpu(dhdr->num_ips); 779 ip_offset = die_offset + sizeof(*dhdr); 780 781 for (j = 0; j < num_ips; j++) { 782 ip = (struct ip *)(discovery_bin + ip_offset); 783 inst = ip->number_instance; 784 hw_id = le16_to_cpu(ip->hw_id); 785 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 786 goto next_ip; 787 788 if (ip->harvest == 1) { 789 switch (hw_id) { 790 case VCN_HWID: 791 (*vcn_harvest_count)++; 792 if (inst == 0) { 793 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 794 adev->vcn.inst_mask &= 795 ~AMDGPU_VCN_HARVEST_VCN0; 796 adev->jpeg.inst_mask &= 797 ~AMDGPU_VCN_HARVEST_VCN0; 798 } else { 799 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 800 adev->vcn.inst_mask &= 801 ~AMDGPU_VCN_HARVEST_VCN1; 802 adev->jpeg.inst_mask &= 803 ~AMDGPU_VCN_HARVEST_VCN1; 804 } 805 break; 806 case DMU_HWID: 807 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 808 break; 809 default: 810 break; 811 } 812 } 813 next_ip: 814 ip_offset += struct_size(ip, base_address, 815 ip->num_base_address); 816 } 817 } 818 } 819 820 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 821 uint32_t *vcn_harvest_count, 822 uint32_t *umc_harvest_count) 823 { 824 uint8_t *discovery_bin = adev->discovery.bin; 825 struct table_info *info; 826 struct harvest_table *harvest_info; 827 u16 offset; 828 int i; 829 u64 umc_harvest_config = 0; 830 831 if (amdgpu_discovery_get_table_info(adev, &info, HARVEST_INFO)) 832 return; 833 offset = le16_to_cpu(info->offset); 834 835 if (!offset) { 836 dev_err(adev->dev, "invalid harvest table offset\n"); 837 return; 838 } 839 840 harvest_info = (struct harvest_table *)(discovery_bin + offset); 841 842 for (i = 0; i < 32; i++) { 843 u16 hw_id = le16_to_cpu(harvest_info->list[i].hw_id); 844 u8 inst = harvest_info->list[i].number_instance; 845 846 if (hw_id == 0) 847 break; 848 849 if (inst >= 32) { 850 dev_warn(adev->dev, 851 "bogus harvest instance %u for hw_id %u\n", 852 inst, hw_id); 853 continue; 854 } 855 856 switch (hw_id) { 857 case VCN_HWID: 858 (*vcn_harvest_count)++; 859 adev->vcn.harvest_config |= BIT(inst); 860 adev->jpeg.harvest_config |= BIT(inst); 861 862 adev->vcn.inst_mask &= ~BIT(inst); 863 adev->jpeg.inst_mask &= ~BIT(inst); 864 break; 865 case DMU_HWID: 866 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 867 break; 868 case UMC_HWID: 869 umc_harvest_config |= BIT_ULL(inst); 870 (*umc_harvest_count)++; 871 break; 872 case GC_HWID: 873 adev->gfx.xcc_mask &= ~BIT(inst); 874 break; 875 case SDMA0_HWID: 876 adev->sdma.sdma_mask &= ~BIT(inst); 877 break; 878 #if defined(CONFIG_DRM_AMD_ISP) 879 case ISP_HWID: 880 adev->isp.harvest_config |= ~BIT(inst); 881 break; 882 #endif 883 default: 884 break; 885 } 886 } 887 888 adev->umc.active_mask = ((1ULL << adev->umc.node_inst_num) - 1ULL) & 889 ~umc_harvest_config; 890 } 891 892 /* ================================================== */ 893 894 struct ip_hw_instance { 895 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 896 897 int hw_id; 898 u8 num_instance; 899 u8 major, minor, revision; 900 u8 harvest; 901 902 int num_base_addresses; 903 u32 base_addr[] __counted_by(num_base_addresses); 904 }; 905 906 struct ip_hw_id { 907 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 908 int hw_id; 909 }; 910 911 struct ip_die_entry { 912 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 913 u16 num_ips; 914 }; 915 916 /* -------------------------------------------------- */ 917 918 struct ip_hw_instance_attr { 919 struct attribute attr; 920 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 921 }; 922 923 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 924 { 925 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 926 } 927 928 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 929 { 930 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 931 } 932 933 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 934 { 935 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 936 } 937 938 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 939 { 940 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 941 } 942 943 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 944 { 945 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 946 } 947 948 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 949 { 950 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 951 } 952 953 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 954 { 955 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 956 } 957 958 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 959 { 960 ssize_t at; 961 int ii; 962 963 for (at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 964 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 965 */ 966 if (at + 12 > PAGE_SIZE) 967 break; 968 at += sysfs_emit_at(buf, at, "0x%08X\n", 969 ip_hw_instance->base_addr[ii]); 970 } 971 972 return at; 973 } 974 975 static struct ip_hw_instance_attr ip_hw_attr[] = { 976 __ATTR_RO(hw_id), 977 __ATTR_RO(num_instance), 978 __ATTR_RO(major), 979 __ATTR_RO(minor), 980 __ATTR_RO(revision), 981 __ATTR_RO(harvest), 982 __ATTR_RO(num_base_addresses), 983 __ATTR_RO(base_addr), 984 }; 985 986 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 987 ATTRIBUTE_GROUPS(ip_hw_instance); 988 989 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 990 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 991 992 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 993 struct attribute *attr, 994 char *buf) 995 { 996 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 997 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 998 999 if (!ip_hw_attr->show) 1000 return -EIO; 1001 1002 return ip_hw_attr->show(ip_hw_instance, buf); 1003 } 1004 1005 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 1006 .show = ip_hw_instance_attr_show, 1007 }; 1008 1009 static void ip_hw_instance_release(struct kobject *kobj) 1010 { 1011 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 1012 1013 kfree(ip_hw_instance); 1014 } 1015 1016 static const struct kobj_type ip_hw_instance_ktype = { 1017 .release = ip_hw_instance_release, 1018 .sysfs_ops = &ip_hw_instance_sysfs_ops, 1019 .default_groups = ip_hw_instance_groups, 1020 }; 1021 1022 /* -------------------------------------------------- */ 1023 1024 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 1025 1026 static void ip_hw_id_release(struct kobject *kobj) 1027 { 1028 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 1029 1030 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 1031 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 1032 kfree(ip_hw_id); 1033 } 1034 1035 static const struct kobj_type ip_hw_id_ktype = { 1036 .release = ip_hw_id_release, 1037 .sysfs_ops = &kobj_sysfs_ops, 1038 }; 1039 1040 /* -------------------------------------------------- */ 1041 1042 static void die_kobj_release(struct kobject *kobj); 1043 static void ip_disc_release(struct kobject *kobj); 1044 1045 struct ip_die_entry_attribute { 1046 struct attribute attr; 1047 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 1048 }; 1049 1050 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 1051 1052 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 1053 { 1054 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 1055 } 1056 1057 /* If there are more ip_die_entry attrs, other than the number of IPs, 1058 * we can make this intro an array of attrs, and then initialize 1059 * ip_die_entry_attrs in a loop. 1060 */ 1061 static struct ip_die_entry_attribute num_ips_attr = 1062 __ATTR_RO(num_ips); 1063 1064 static struct attribute *ip_die_entry_attrs[] = { 1065 &num_ips_attr.attr, 1066 NULL, 1067 }; 1068 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 1069 1070 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 1071 1072 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 1073 struct attribute *attr, 1074 char *buf) 1075 { 1076 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 1077 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1078 1079 if (!ip_die_entry_attr->show) 1080 return -EIO; 1081 1082 return ip_die_entry_attr->show(ip_die_entry, buf); 1083 } 1084 1085 static void ip_die_entry_release(struct kobject *kobj) 1086 { 1087 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1088 1089 if (!list_empty(&ip_die_entry->ip_kset.list)) 1090 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 1091 kfree(ip_die_entry); 1092 } 1093 1094 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 1095 .show = ip_die_entry_attr_show, 1096 }; 1097 1098 static const struct kobj_type ip_die_entry_ktype = { 1099 .release = ip_die_entry_release, 1100 .sysfs_ops = &ip_die_entry_sysfs_ops, 1101 .default_groups = ip_die_entry_groups, 1102 }; 1103 1104 static const struct kobj_type die_kobj_ktype = { 1105 .release = die_kobj_release, 1106 .sysfs_ops = &kobj_sysfs_ops, 1107 }; 1108 1109 static const struct kobj_type ip_discovery_ktype = { 1110 .release = ip_disc_release, 1111 .sysfs_ops = &kobj_sysfs_ops, 1112 }; 1113 1114 struct ip_discovery_top { 1115 struct kobject kobj; /* ip_discovery/ */ 1116 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 1117 struct amdgpu_device *adev; 1118 }; 1119 1120 static void die_kobj_release(struct kobject *kobj) 1121 { 1122 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 1123 struct ip_discovery_top, 1124 die_kset); 1125 if (!list_empty(&ip_top->die_kset.list)) 1126 DRM_ERROR("ip_top->die_kset is not empty"); 1127 } 1128 1129 static void ip_disc_release(struct kobject *kobj) 1130 { 1131 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 1132 kobj); 1133 struct amdgpu_device *adev = ip_top->adev; 1134 1135 kfree(ip_top); 1136 adev->discovery.ip_top = NULL; 1137 } 1138 1139 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 1140 uint16_t hw_id, uint8_t inst) 1141 { 1142 uint8_t harvest = 0; 1143 1144 /* Until a uniform way is figured, get mask based on hwid */ 1145 switch (hw_id) { 1146 case VCN_HWID: 1147 /* VCN vs UVD+VCE */ 1148 if (!amdgpu_ip_version(adev, VCE_HWIP, 0)) 1149 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1150 break; 1151 case DMU_HWID: 1152 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 1153 harvest = 0x1; 1154 break; 1155 case UMC_HWID: 1156 /* TODO: It needs another parsing; for now, ignore.*/ 1157 break; 1158 case GC_HWID: 1159 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1160 break; 1161 case SDMA0_HWID: 1162 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 1163 break; 1164 default: 1165 break; 1166 } 1167 1168 return harvest; 1169 } 1170 1171 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1172 struct ip_die_entry *ip_die_entry, 1173 const size_t _ip_offset, const int num_ips, 1174 bool reg_base_64) 1175 { 1176 uint8_t *discovery_bin = adev->discovery.bin; 1177 int ii, jj, kk, res; 1178 uint16_t hw_id; 1179 uint8_t inst; 1180 1181 DRM_DEBUG("num_ips:%d", num_ips); 1182 1183 /* Find all IPs of a given HW ID, and add their instance to 1184 * #die/#hw_id/#instance/<attributes> 1185 */ 1186 for (ii = 0; ii < HW_ID_MAX; ii++) { 1187 struct ip_hw_id *ip_hw_id = NULL; 1188 size_t ip_offset = _ip_offset; 1189 1190 for (jj = 0; jj < num_ips; jj++) { 1191 struct ip_v4 *ip; 1192 struct ip_hw_instance *ip_hw_instance; 1193 1194 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1195 inst = ip->instance_number; 1196 hw_id = le16_to_cpu(ip->hw_id); 1197 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) || 1198 hw_id != ii) 1199 goto next_ip; 1200 1201 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1202 1203 /* We have a hw_id match; register the hw 1204 * block if not yet registered. 1205 */ 1206 if (!ip_hw_id) { 1207 ip_hw_id = kzalloc_obj(*ip_hw_id); 1208 if (!ip_hw_id) 1209 return -ENOMEM; 1210 ip_hw_id->hw_id = ii; 1211 1212 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1213 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1214 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1215 res = kset_register(&ip_hw_id->hw_id_kset); 1216 if (res) { 1217 DRM_ERROR("Couldn't register ip_hw_id kset"); 1218 kfree(ip_hw_id); 1219 return res; 1220 } 1221 if (hw_id_names[ii]) { 1222 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1223 &ip_hw_id->hw_id_kset.kobj, 1224 hw_id_names[ii]); 1225 if (res) { 1226 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1227 hw_id_names[ii], 1228 kobject_name(&ip_die_entry->ip_kset.kobj)); 1229 } 1230 } 1231 } 1232 1233 /* Now register its instance. 1234 */ 1235 ip_hw_instance = kzalloc_flex(*ip_hw_instance, 1236 base_addr, 1237 ip->num_base_address); 1238 if (!ip_hw_instance) { 1239 DRM_ERROR("no memory for ip_hw_instance"); 1240 return -ENOMEM; 1241 } 1242 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1243 ip_hw_instance->num_instance = ip->instance_number; 1244 ip_hw_instance->major = ip->major; 1245 ip_hw_instance->minor = ip->minor; 1246 ip_hw_instance->revision = ip->revision; 1247 ip_hw_instance->harvest = 1248 amdgpu_discovery_get_harvest_info( 1249 adev, ip_hw_instance->hw_id, 1250 ip_hw_instance->num_instance); 1251 ip_hw_instance->num_base_addresses = ip->num_base_address; 1252 1253 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) 1254 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1255 1256 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1257 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1258 res = kobject_add(&ip_hw_instance->kobj, NULL, 1259 "%d", ip_hw_instance->num_instance); 1260 next_ip: 1261 if (reg_base_64) 1262 ip_offset += struct_size(ip, base_address_64, 1263 ip->num_base_address); 1264 else 1265 ip_offset += struct_size(ip, base_address, 1266 ip->num_base_address); 1267 } 1268 } 1269 1270 return 0; 1271 } 1272 1273 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1274 { 1275 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1276 uint8_t *discovery_bin = adev->discovery.bin; 1277 struct table_info *info; 1278 struct ip_discovery_header *ihdr; 1279 struct die_header *dhdr; 1280 struct kset *die_kset = &ip_top->die_kset; 1281 u16 num_dies, die_offset, num_ips; 1282 size_t ip_offset; 1283 int ii, res; 1284 1285 res = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); 1286 if (res) 1287 return res; 1288 ihdr = (struct ip_discovery_header 1289 *)(discovery_bin + 1290 le16_to_cpu(info->offset)); 1291 num_dies = le16_to_cpu(ihdr->num_dies); 1292 1293 DRM_DEBUG("number of dies: %d\n", num_dies); 1294 1295 for (ii = 0; ii < num_dies; ii++) { 1296 struct ip_die_entry *ip_die_entry; 1297 1298 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1299 dhdr = (struct die_header *)(discovery_bin + die_offset); 1300 num_ips = le16_to_cpu(dhdr->num_ips); 1301 ip_offset = die_offset + sizeof(*dhdr); 1302 1303 /* Add the die to the kset. 1304 * 1305 * dhdr->die_id == ii, which was checked in 1306 * amdgpu_discovery_reg_base_init(). 1307 */ 1308 1309 ip_die_entry = kzalloc_obj(*ip_die_entry); 1310 if (!ip_die_entry) 1311 return -ENOMEM; 1312 1313 ip_die_entry->num_ips = num_ips; 1314 1315 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1316 ip_die_entry->ip_kset.kobj.kset = die_kset; 1317 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1318 res = kset_register(&ip_die_entry->ip_kset); 1319 if (res) { 1320 DRM_ERROR("Couldn't register ip_die_entry kset"); 1321 kfree(ip_die_entry); 1322 return res; 1323 } 1324 1325 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1326 } 1327 1328 return 0; 1329 } 1330 1331 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1332 { 1333 uint8_t *discovery_bin = adev->discovery.bin; 1334 struct ip_discovery_top *ip_top; 1335 struct kset *die_kset; 1336 int res, ii; 1337 1338 if (!discovery_bin) 1339 return -EINVAL; 1340 1341 ip_top = kzalloc_obj(*ip_top); 1342 if (!ip_top) 1343 return -ENOMEM; 1344 1345 ip_top->adev = adev; 1346 adev->discovery.ip_top = ip_top; 1347 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype, 1348 &adev->dev->kobj, "ip_discovery"); 1349 if (res) { 1350 DRM_ERROR("Couldn't init and add ip_discovery/"); 1351 goto Err; 1352 } 1353 1354 die_kset = &ip_top->die_kset; 1355 kobject_set_name(&die_kset->kobj, "%s", "die"); 1356 die_kset->kobj.parent = &ip_top->kobj; 1357 die_kset->kobj.ktype = &die_kobj_ktype; 1358 res = kset_register(&ip_top->die_kset); 1359 if (res) { 1360 DRM_ERROR("Couldn't register die_kset"); 1361 goto Err; 1362 } 1363 1364 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1365 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1366 ip_hw_instance_attrs[ii] = NULL; 1367 1368 res = amdgpu_discovery_sysfs_recurse(adev); 1369 1370 return res; 1371 Err: 1372 kobject_put(&ip_top->kobj); 1373 return res; 1374 } 1375 1376 /* -------------------------------------------------- */ 1377 1378 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1379 1380 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1381 { 1382 struct list_head *el, *tmp; 1383 struct kset *hw_id_kset; 1384 1385 hw_id_kset = &ip_hw_id->hw_id_kset; 1386 spin_lock(&hw_id_kset->list_lock); 1387 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1388 list_del_init(el); 1389 spin_unlock(&hw_id_kset->list_lock); 1390 /* kobject is embedded in ip_hw_instance */ 1391 kobject_put(list_to_kobj(el)); 1392 spin_lock(&hw_id_kset->list_lock); 1393 } 1394 spin_unlock(&hw_id_kset->list_lock); 1395 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1396 } 1397 1398 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1399 { 1400 struct list_head *el, *tmp; 1401 struct kset *ip_kset; 1402 1403 ip_kset = &ip_die_entry->ip_kset; 1404 spin_lock(&ip_kset->list_lock); 1405 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1406 list_del_init(el); 1407 spin_unlock(&ip_kset->list_lock); 1408 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1409 spin_lock(&ip_kset->list_lock); 1410 } 1411 spin_unlock(&ip_kset->list_lock); 1412 kobject_put(&ip_die_entry->ip_kset.kobj); 1413 } 1414 1415 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1416 { 1417 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1418 struct list_head *el, *tmp; 1419 struct kset *die_kset; 1420 1421 if (!ip_top) 1422 return; 1423 1424 die_kset = &ip_top->die_kset; 1425 spin_lock(&die_kset->list_lock); 1426 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1427 list_del_init(el); 1428 spin_unlock(&die_kset->list_lock); 1429 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1430 spin_lock(&die_kset->list_lock); 1431 } 1432 spin_unlock(&die_kset->list_lock); 1433 kobject_put(&ip_top->die_kset.kobj); 1434 kobject_put(&ip_top->kobj); 1435 } 1436 1437 /* devcoredump support */ 1438 void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p) 1439 { 1440 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1441 struct ip_die_entry *ip_die_entry; 1442 struct list_head *el_die, *el_hw_id, *el_hw_inst; 1443 struct ip_hw_id *hw_id; 1444 struct kset *die_kset; 1445 struct ip_hw_instance *ip_inst; 1446 int i = 0, j; 1447 1448 if (!ip_top) 1449 return; 1450 1451 die_kset = &ip_top->die_kset; 1452 1453 drm_printf(p, "\nHW IP Discovery\n"); 1454 1455 spin_lock(&die_kset->list_lock); 1456 list_for_each(el_die, &die_kset->list) { 1457 drm_printf(p, "die %d\n", i++); 1458 ip_die_entry = to_ip_die_entry(list_to_kobj(el_die)); 1459 1460 list_for_each(el_hw_id, &ip_die_entry->ip_kset.list) { 1461 hw_id = to_ip_hw_id(list_to_kobj(el_hw_id)); 1462 drm_printf(p, "hw_id %d %s\n", hw_id->hw_id, hw_id_names[hw_id->hw_id]); 1463 1464 list_for_each(el_hw_inst, &hw_id->hw_id_kset.list) { 1465 ip_inst = to_ip_hw_instance(list_to_kobj(el_hw_inst)); 1466 drm_printf(p, "\tinstance %d\n", ip_inst->num_instance); 1467 drm_printf(p, "\tmajor %d\n", ip_inst->major); 1468 drm_printf(p, "\tminor %d\n", ip_inst->minor); 1469 drm_printf(p, "\trevision %d\n", ip_inst->revision); 1470 drm_printf(p, "\tharvest 0x%01X\n", ip_inst->harvest); 1471 drm_printf(p, "\tnum_base_addresses %d\n", 1472 ip_inst->num_base_addresses); 1473 for (j = 0; j < ip_inst->num_base_addresses; j++) 1474 drm_printf(p, "\tbase_addr[%d] 0x%08X\n", 1475 j, ip_inst->base_addr[j]); 1476 } 1477 } 1478 } 1479 spin_unlock(&die_kset->list_lock); 1480 } 1481 1482 1483 /* ================================================== */ 1484 1485 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1486 { 1487 uint8_t num_base_address, subrev, variant; 1488 struct table_info *info; 1489 struct ip_discovery_header *ihdr; 1490 struct die_header *dhdr; 1491 uint8_t *discovery_bin; 1492 struct ip_v4 *ip; 1493 uint16_t die_offset; 1494 uint16_t ip_offset; 1495 uint16_t num_dies; 1496 uint32_t wafl_ver; 1497 uint16_t num_ips; 1498 uint16_t hw_id; 1499 uint8_t inst; 1500 int hw_ip; 1501 int i, j, k; 1502 int r; 1503 1504 r = amdgpu_discovery_init(adev); 1505 if (r) 1506 return r; 1507 discovery_bin = adev->discovery.bin; 1508 wafl_ver = 0; 1509 adev->gfx.xcc_mask = 0; 1510 adev->sdma.sdma_mask = 0; 1511 adev->vcn.inst_mask = 0; 1512 adev->jpeg.inst_mask = 0; 1513 r = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); 1514 if (r) 1515 return r; 1516 ihdr = (struct ip_discovery_header 1517 *)(discovery_bin + 1518 le16_to_cpu(info->offset)); 1519 num_dies = le16_to_cpu(ihdr->num_dies); 1520 1521 DRM_DEBUG("number of dies: %d\n", num_dies); 1522 1523 for (i = 0; i < num_dies; i++) { 1524 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1525 dhdr = (struct die_header *)(discovery_bin + die_offset); 1526 num_ips = le16_to_cpu(dhdr->num_ips); 1527 ip_offset = die_offset + sizeof(*dhdr); 1528 1529 if (le16_to_cpu(dhdr->die_id) != i) { 1530 DRM_ERROR("invalid die id %d, expected %d\n", 1531 le16_to_cpu(dhdr->die_id), i); 1532 return -EINVAL; 1533 } 1534 1535 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1536 le16_to_cpu(dhdr->die_id), num_ips); 1537 1538 for (j = 0; j < num_ips; j++) { 1539 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1540 1541 inst = ip->instance_number; 1542 hw_id = le16_to_cpu(ip->hw_id); 1543 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 1544 goto next_ip; 1545 1546 num_base_address = ip->num_base_address; 1547 1548 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1549 hw_id_names[le16_to_cpu(ip->hw_id)], 1550 le16_to_cpu(ip->hw_id), 1551 ip->instance_number, 1552 ip->major, ip->minor, 1553 ip->revision); 1554 1555 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1556 /* Bit [5:0]: original revision value 1557 * Bit [7:6]: en/decode capability: 1558 * 0b00 : VCN function normally 1559 * 0b10 : encode is disabled 1560 * 0b01 : decode is disabled 1561 */ 1562 if (adev->vcn.num_vcn_inst < 1563 AMDGPU_MAX_VCN_INSTANCES) { 1564 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = 1565 ip->revision & 0xc0; 1566 adev->vcn.num_vcn_inst++; 1567 adev->vcn.inst_mask |= 1568 (1U << ip->instance_number); 1569 adev->jpeg.inst_mask |= 1570 (1U << ip->instance_number); 1571 } else { 1572 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1573 adev->vcn.num_vcn_inst + 1, 1574 AMDGPU_MAX_VCN_INSTANCES); 1575 } 1576 ip->revision &= ~0xc0; 1577 } 1578 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1579 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1580 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1581 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1582 if (adev->sdma.num_instances < 1583 AMDGPU_MAX_SDMA_INSTANCES) { 1584 adev->sdma.num_instances++; 1585 adev->sdma.sdma_mask |= 1586 (1U << ip->instance_number); 1587 } else { 1588 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1589 adev->sdma.num_instances + 1, 1590 AMDGPU_MAX_SDMA_INSTANCES); 1591 } 1592 } 1593 1594 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1595 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1596 adev->vpe.num_instances++; 1597 else 1598 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1599 adev->vpe.num_instances + 1, 1600 AMDGPU_MAX_VPE_INSTANCES); 1601 } 1602 1603 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1604 adev->gmc.num_umc++; 1605 adev->umc.node_inst_num++; 1606 } 1607 1608 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1609 adev->gfx.xcc_mask |= 1610 (1U << ip->instance_number); 1611 1612 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID) 1613 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor, 1614 ip->revision, 0, 0); 1615 1616 for (k = 0; k < num_base_address; k++) { 1617 /* 1618 * convert the endianness of base addresses in place, 1619 * so that we don't need to convert them when accessing adev->reg_offset. 1620 */ 1621 if (ihdr->base_addr_64_bit) 1622 /* Truncate the 64bit base address from ip discovery 1623 * and only store lower 32bit ip base in reg_offset[]. 1624 * Bits > 32 follows ASIC specific format, thus just 1625 * discard them and handle it within specific ASIC. 1626 * By this way reg_offset[] and related helpers can 1627 * stay unchanged. 1628 * The base address is in dwords, thus clear the 1629 * highest 2 bits to store. 1630 */ 1631 ip->base_address[k] = 1632 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1633 else 1634 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1635 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1636 } 1637 1638 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1639 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1640 hw_id_map[hw_ip] != 0) { 1641 DRM_DEBUG("set register base offset for %s\n", 1642 hw_id_names[le16_to_cpu(ip->hw_id)]); 1643 adev->reg_offset[hw_ip][ip->instance_number] = 1644 ip->base_address; 1645 /* Instance support is somewhat inconsistent. 1646 * SDMA is a good example. Sienna cichlid has 4 total 1647 * SDMA instances, each enumerated separately (HWIDs 1648 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1649 * but they are enumerated as multiple instances of the 1650 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1651 * example. On most chips there are multiple instances 1652 * with the same HWID. 1653 */ 1654 1655 if (ihdr->version < 3) { 1656 subrev = 0; 1657 variant = 0; 1658 } else { 1659 subrev = ip->sub_revision; 1660 variant = ip->variant; 1661 } 1662 1663 adev->ip_versions[hw_ip] 1664 [ip->instance_number] = 1665 IP_VERSION_FULL(ip->major, 1666 ip->minor, 1667 ip->revision, 1668 variant, 1669 subrev); 1670 } 1671 } 1672 1673 next_ip: 1674 if (ihdr->base_addr_64_bit) 1675 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1676 else 1677 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1678 } 1679 } 1680 1681 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0]) 1682 adev->ip_versions[XGMI_HWIP][0] = wafl_ver; 1683 1684 return 0; 1685 } 1686 1687 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1688 { 1689 uint8_t *discovery_bin = adev->discovery.bin; 1690 struct ip_discovery_header *ihdr; 1691 struct table_info *info; 1692 int vcn_harvest_count = 0; 1693 int umc_harvest_count = 0; 1694 uint16_t ihdr_ver; 1695 1696 if (amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY)) 1697 return; 1698 ihdr = (struct ip_discovery_header *)(discovery_bin + 1699 le16_to_cpu(info->offset)); 1700 ihdr_ver = le16_to_cpu(ihdr->version); 1701 /* 1702 * Harvest table does not fit Navi1x and legacy GPUs, 1703 * so read harvest bit per IP data structure to set 1704 * harvest configuration. 1705 */ 1706 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1707 ihdr_ver <= 2) { 1708 if ((adev->pdev->device == 0x731E && 1709 (adev->pdev->revision == 0xC6 || 1710 adev->pdev->revision == 0xC7)) || 1711 (adev->pdev->device == 0x7340 && 1712 adev->pdev->revision == 0xC9) || 1713 (adev->pdev->device == 0x7360 && 1714 adev->pdev->revision == 0xC7)) 1715 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1716 &vcn_harvest_count); 1717 } else { 1718 amdgpu_discovery_read_from_harvest_table(adev, 1719 &vcn_harvest_count, 1720 &umc_harvest_count); 1721 } 1722 1723 amdgpu_discovery_harvest_config_quirk(adev); 1724 1725 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1726 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1727 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1728 } 1729 1730 if (umc_harvest_count < adev->gmc.num_umc) { 1731 adev->gmc.num_umc -= umc_harvest_count; 1732 } 1733 } 1734 1735 union gc_info { 1736 struct gc_info_v1_0 v1; 1737 struct gc_info_v1_1 v1_1; 1738 struct gc_info_v1_2 v1_2; 1739 struct gc_info_v1_3 v1_3; 1740 struct gc_info_v2_0 v2; 1741 struct gc_info_v2_1 v2_1; 1742 }; 1743 1744 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1745 { 1746 uint8_t *discovery_bin = adev->discovery.bin; 1747 struct table_info *info; 1748 union gc_info *gc_info; 1749 u16 offset; 1750 1751 if (!discovery_bin) { 1752 DRM_ERROR("ip discovery uninitialized\n"); 1753 return -EINVAL; 1754 } 1755 1756 if (amdgpu_discovery_get_table_info(adev, &info, GC)) 1757 return -EINVAL; 1758 offset = le16_to_cpu(info->offset); 1759 1760 if (!offset) 1761 return 0; 1762 1763 gc_info = (union gc_info *)(discovery_bin + offset); 1764 1765 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1766 case 1: 1767 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1768 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1769 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1770 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1771 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1772 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1773 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1774 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1775 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1776 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1777 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1778 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1779 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1780 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1781 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1782 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1783 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1784 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1785 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1786 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1787 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1788 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1789 } 1790 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1791 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1792 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1793 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1794 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1795 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1796 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1797 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1798 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1799 } 1800 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { 1801 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); 1802 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); 1803 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); 1804 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); 1805 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); 1806 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); 1807 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); 1808 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); 1809 } 1810 break; 1811 case 2: 1812 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1813 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1814 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1815 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1816 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1817 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1818 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1819 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1820 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1821 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1822 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1823 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1824 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1825 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1826 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1827 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1828 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1829 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1830 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1831 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1832 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1833 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1834 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1835 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1836 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1837 } 1838 break; 1839 default: 1840 dev_err(adev->dev, 1841 "Unhandled GC info table %d.%d\n", 1842 le16_to_cpu(gc_info->v1.header.version_major), 1843 le16_to_cpu(gc_info->v1.header.version_minor)); 1844 return -EINVAL; 1845 } 1846 return 0; 1847 } 1848 1849 union mall_info { 1850 struct mall_info_v1_0 v1; 1851 struct mall_info_v2_0 v2; 1852 }; 1853 1854 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1855 { 1856 uint8_t *discovery_bin = adev->discovery.bin; 1857 struct table_info *info; 1858 union mall_info *mall_info; 1859 u32 u, mall_size_per_umc, m_s_present, half_use; 1860 u64 mall_size; 1861 u16 offset; 1862 1863 if (!discovery_bin) { 1864 DRM_ERROR("ip discovery uninitialized\n"); 1865 return -EINVAL; 1866 } 1867 1868 if (amdgpu_discovery_get_table_info(adev, &info, MALL_INFO)) 1869 return -EINVAL; 1870 offset = le16_to_cpu(info->offset); 1871 1872 if (!offset) 1873 return 0; 1874 1875 mall_info = (union mall_info *)(discovery_bin + offset); 1876 1877 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1878 case 1: 1879 mall_size = 0; 1880 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1881 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1882 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1883 for (u = 0; u < adev->gmc.num_umc; u++) { 1884 if (m_s_present & (1 << u)) 1885 mall_size += mall_size_per_umc * 2; 1886 else if (half_use & (1 << u)) 1887 mall_size += mall_size_per_umc / 2; 1888 else 1889 mall_size += mall_size_per_umc; 1890 } 1891 adev->gmc.mall_size = mall_size; 1892 adev->gmc.m_half_use = half_use; 1893 break; 1894 case 2: 1895 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1896 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; 1897 break; 1898 default: 1899 dev_err(adev->dev, 1900 "Unhandled MALL info table %d.%d\n", 1901 le16_to_cpu(mall_info->v1.header.version_major), 1902 le16_to_cpu(mall_info->v1.header.version_minor)); 1903 return -EINVAL; 1904 } 1905 return 0; 1906 } 1907 1908 union vcn_info { 1909 struct vcn_info_v1_0 v1; 1910 }; 1911 1912 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1913 { 1914 uint8_t *discovery_bin = adev->discovery.bin; 1915 struct table_info *info; 1916 union vcn_info *vcn_info; 1917 u16 offset; 1918 int v; 1919 1920 if (!discovery_bin) { 1921 DRM_ERROR("ip discovery uninitialized\n"); 1922 return -EINVAL; 1923 } 1924 1925 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1926 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1927 * but that may change in the future with new GPUs so keep this 1928 * check for defensive purposes. 1929 */ 1930 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1931 dev_err(adev->dev, "invalid vcn instances\n"); 1932 return -EINVAL; 1933 } 1934 1935 if (amdgpu_discovery_get_table_info(adev, &info, VCN_INFO)) 1936 return -EINVAL; 1937 offset = le16_to_cpu(info->offset); 1938 1939 if (!offset) 1940 return 0; 1941 1942 vcn_info = (union vcn_info *)(discovery_bin + offset); 1943 1944 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1945 case 1: 1946 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1947 * so this won't overflow. 1948 */ 1949 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1950 adev->vcn.inst[v].vcn_codec_disable_mask = 1951 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1952 } 1953 break; 1954 default: 1955 dev_err(adev->dev, 1956 "Unhandled VCN info table %d.%d\n", 1957 le16_to_cpu(vcn_info->v1.header.version_major), 1958 le16_to_cpu(vcn_info->v1.header.version_minor)); 1959 return -EINVAL; 1960 } 1961 return 0; 1962 } 1963 1964 union nps_info { 1965 struct nps_info_v1_0 v1; 1966 }; 1967 1968 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, 1969 union nps_info *nps_data) 1970 { 1971 uint64_t vram_size, pos, offset; 1972 struct nps_info_header *nhdr; 1973 struct binary_header bhdr; 1974 struct binary_header_v2 bhdrv2; 1975 uint16_t checksum; 1976 1977 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 1978 pos = vram_size - DISCOVERY_TMR_OFFSET; 1979 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); 1980 1981 switch (bhdr.version_major) { 1982 case 2: 1983 amdgpu_device_vram_access(adev, pos, &bhdrv2, sizeof(bhdrv2), false); 1984 offset = le16_to_cpu(bhdrv2.table_list[NPS_INFO].offset); 1985 checksum = le16_to_cpu(bhdrv2.table_list[NPS_INFO].checksum); 1986 break; 1987 case 1: 1988 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); 1989 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); 1990 break; 1991 default: 1992 return -EINVAL; 1993 } 1994 1995 amdgpu_device_vram_access(adev, (pos + offset), nps_data, 1996 sizeof(*nps_data), false); 1997 1998 nhdr = (struct nps_info_header *)(nps_data); 1999 if (!amdgpu_discovery_verify_checksum(adev, (uint8_t *)nps_data, 2000 le32_to_cpu(nhdr->size_bytes), 2001 checksum)) { 2002 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); 2003 return -EINVAL; 2004 } 2005 2006 return 0; 2007 } 2008 2009 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 2010 uint32_t *nps_type, 2011 struct amdgpu_gmc_memrange *ranges, 2012 int *range_cnt, bool refresh) 2013 { 2014 uint8_t *discovery_bin = adev->discovery.bin; 2015 struct table_info *info; 2016 union nps_info *nps_info; 2017 union nps_info nps_data; 2018 u16 offset; 2019 int i, r; 2020 2021 if (!nps_type || !range_cnt || !ranges) 2022 return -EINVAL; 2023 2024 if (refresh) { 2025 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); 2026 if (r) 2027 return r; 2028 nps_info = &nps_data; 2029 } else { 2030 if (!discovery_bin) { 2031 dev_err(adev->dev, 2032 "fetch mem range failed, ip discovery uninitialized\n"); 2033 return -EINVAL; 2034 } 2035 2036 if (amdgpu_discovery_get_table_info(adev, &info, NPS_INFO)) 2037 return -EINVAL; 2038 offset = le16_to_cpu(info->offset); 2039 2040 if (!offset) 2041 return -ENOENT; 2042 2043 /* If verification fails, return as if NPS table doesn't exist */ 2044 if (amdgpu_discovery_verify_npsinfo(adev, info)) 2045 return -ENOENT; 2046 2047 nps_info = (union nps_info *)(discovery_bin + offset); 2048 } 2049 2050 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 2051 case 1: 2052 *nps_type = nps_info->v1.nps_type; 2053 if (*range_cnt < nps_info->v1.count) { 2054 dev_dbg(adev->dev, 2055 "not enough space for nps ranges: %d < %d\n", 2056 *range_cnt, nps_info->v1.count); 2057 return -ENOSPC; 2058 } 2059 *range_cnt = nps_info->v1.count; 2060 for (i = 0; i < *range_cnt; i++) { 2061 ranges[i].base_address = 2062 nps_info->v1.instance_info[i].base_address; 2063 ranges[i].limit_address = 2064 nps_info->v1.instance_info[i].limit_address; 2065 ranges[i].nid_mask = -1; 2066 ranges[i].flags = 0; 2067 } 2068 break; 2069 default: 2070 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 2071 le16_to_cpu(nps_info->v1.header.version_major), 2072 le16_to_cpu(nps_info->v1.header.version_minor)); 2073 return -EINVAL; 2074 } 2075 2076 return 0; 2077 } 2078 2079 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 2080 { 2081 /* what IP to use for this? */ 2082 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2083 case IP_VERSION(9, 0, 1): 2084 case IP_VERSION(9, 1, 0): 2085 case IP_VERSION(9, 2, 1): 2086 case IP_VERSION(9, 2, 2): 2087 case IP_VERSION(9, 3, 0): 2088 case IP_VERSION(9, 4, 0): 2089 case IP_VERSION(9, 4, 1): 2090 case IP_VERSION(9, 4, 2): 2091 case IP_VERSION(9, 4, 3): 2092 case IP_VERSION(9, 4, 4): 2093 case IP_VERSION(9, 5, 0): 2094 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 2095 break; 2096 case IP_VERSION(10, 1, 10): 2097 case IP_VERSION(10, 1, 1): 2098 case IP_VERSION(10, 1, 2): 2099 case IP_VERSION(10, 1, 3): 2100 case IP_VERSION(10, 1, 4): 2101 case IP_VERSION(10, 3, 0): 2102 case IP_VERSION(10, 3, 1): 2103 case IP_VERSION(10, 3, 2): 2104 case IP_VERSION(10, 3, 3): 2105 case IP_VERSION(10, 3, 4): 2106 case IP_VERSION(10, 3, 5): 2107 case IP_VERSION(10, 3, 6): 2108 case IP_VERSION(10, 3, 7): 2109 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 2110 break; 2111 case IP_VERSION(11, 0, 0): 2112 case IP_VERSION(11, 0, 1): 2113 case IP_VERSION(11, 0, 2): 2114 case IP_VERSION(11, 0, 3): 2115 case IP_VERSION(11, 0, 4): 2116 case IP_VERSION(11, 5, 0): 2117 case IP_VERSION(11, 5, 1): 2118 case IP_VERSION(11, 5, 2): 2119 case IP_VERSION(11, 5, 3): 2120 case IP_VERSION(11, 5, 4): 2121 case IP_VERSION(11, 5, 6): 2122 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 2123 break; 2124 case IP_VERSION(12, 0, 0): 2125 case IP_VERSION(12, 0, 1): 2126 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 2127 break; 2128 case IP_VERSION(12, 1, 0): 2129 amdgpu_device_ip_block_add(adev, &soc_v1_0_common_ip_block); 2130 break; 2131 default: 2132 dev_err(adev->dev, 2133 "Failed to add common ip block(GC_HWIP:0x%x)\n", 2134 amdgpu_ip_version(adev, GC_HWIP, 0)); 2135 return -EINVAL; 2136 } 2137 return 0; 2138 } 2139 2140 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 2141 { 2142 /* use GC or MMHUB IP version */ 2143 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2144 case IP_VERSION(9, 0, 1): 2145 case IP_VERSION(9, 1, 0): 2146 case IP_VERSION(9, 2, 1): 2147 case IP_VERSION(9, 2, 2): 2148 case IP_VERSION(9, 3, 0): 2149 case IP_VERSION(9, 4, 0): 2150 case IP_VERSION(9, 4, 1): 2151 case IP_VERSION(9, 4, 2): 2152 case IP_VERSION(9, 4, 3): 2153 case IP_VERSION(9, 4, 4): 2154 case IP_VERSION(9, 5, 0): 2155 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 2156 break; 2157 case IP_VERSION(10, 1, 10): 2158 case IP_VERSION(10, 1, 1): 2159 case IP_VERSION(10, 1, 2): 2160 case IP_VERSION(10, 1, 3): 2161 case IP_VERSION(10, 1, 4): 2162 case IP_VERSION(10, 3, 0): 2163 case IP_VERSION(10, 3, 1): 2164 case IP_VERSION(10, 3, 2): 2165 case IP_VERSION(10, 3, 3): 2166 case IP_VERSION(10, 3, 4): 2167 case IP_VERSION(10, 3, 5): 2168 case IP_VERSION(10, 3, 6): 2169 case IP_VERSION(10, 3, 7): 2170 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 2171 break; 2172 case IP_VERSION(11, 0, 0): 2173 case IP_VERSION(11, 0, 1): 2174 case IP_VERSION(11, 0, 2): 2175 case IP_VERSION(11, 0, 3): 2176 case IP_VERSION(11, 0, 4): 2177 case IP_VERSION(11, 5, 0): 2178 case IP_VERSION(11, 5, 1): 2179 case IP_VERSION(11, 5, 2): 2180 case IP_VERSION(11, 5, 3): 2181 case IP_VERSION(11, 5, 4): 2182 case IP_VERSION(11, 5, 6): 2183 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 2184 break; 2185 case IP_VERSION(12, 0, 0): 2186 case IP_VERSION(12, 0, 1): 2187 case IP_VERSION(12, 1, 0): 2188 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 2189 break; 2190 default: 2191 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 2192 amdgpu_ip_version(adev, GC_HWIP, 0)); 2193 return -EINVAL; 2194 } 2195 return 0; 2196 } 2197 2198 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 2199 { 2200 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 2201 case IP_VERSION(4, 0, 0): 2202 case IP_VERSION(4, 0, 1): 2203 case IP_VERSION(4, 1, 0): 2204 case IP_VERSION(4, 1, 1): 2205 case IP_VERSION(4, 3, 0): 2206 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 2207 break; 2208 case IP_VERSION(4, 2, 0): 2209 case IP_VERSION(4, 2, 1): 2210 case IP_VERSION(4, 4, 0): 2211 case IP_VERSION(4, 4, 2): 2212 case IP_VERSION(4, 4, 5): 2213 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 2214 break; 2215 case IP_VERSION(5, 0, 0): 2216 case IP_VERSION(5, 0, 1): 2217 case IP_VERSION(5, 0, 2): 2218 case IP_VERSION(5, 0, 3): 2219 case IP_VERSION(5, 2, 0): 2220 case IP_VERSION(5, 2, 1): 2221 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 2222 break; 2223 case IP_VERSION(6, 0, 0): 2224 case IP_VERSION(6, 0, 1): 2225 case IP_VERSION(6, 0, 2): 2226 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 2227 break; 2228 case IP_VERSION(6, 1, 0): 2229 case IP_VERSION(6, 1, 1): 2230 case IP_VERSION(6, 4, 0): 2231 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 2232 break; 2233 case IP_VERSION(7, 0, 0): 2234 case IP_VERSION(7, 1, 0): 2235 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 2236 break; 2237 default: 2238 dev_err(adev->dev, 2239 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 2240 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 2241 return -EINVAL; 2242 } 2243 return 0; 2244 } 2245 2246 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 2247 { 2248 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2249 case IP_VERSION(9, 0, 0): 2250 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 2251 break; 2252 case IP_VERSION(10, 0, 0): 2253 case IP_VERSION(10, 0, 1): 2254 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 2255 break; 2256 case IP_VERSION(11, 0, 0): 2257 case IP_VERSION(11, 0, 2): 2258 case IP_VERSION(11, 0, 4): 2259 case IP_VERSION(11, 0, 5): 2260 case IP_VERSION(11, 0, 9): 2261 case IP_VERSION(11, 0, 7): 2262 case IP_VERSION(11, 0, 11): 2263 case IP_VERSION(11, 0, 12): 2264 case IP_VERSION(11, 0, 13): 2265 case IP_VERSION(11, 5, 0): 2266 case IP_VERSION(11, 5, 2): 2267 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 2268 break; 2269 case IP_VERSION(11, 0, 8): 2270 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 2271 break; 2272 case IP_VERSION(11, 0, 3): 2273 case IP_VERSION(12, 0, 1): 2274 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 2275 break; 2276 case IP_VERSION(13, 0, 0): 2277 case IP_VERSION(13, 0, 1): 2278 case IP_VERSION(13, 0, 2): 2279 case IP_VERSION(13, 0, 3): 2280 case IP_VERSION(13, 0, 5): 2281 case IP_VERSION(13, 0, 6): 2282 case IP_VERSION(13, 0, 7): 2283 case IP_VERSION(13, 0, 8): 2284 case IP_VERSION(13, 0, 10): 2285 case IP_VERSION(13, 0, 11): 2286 case IP_VERSION(13, 0, 12): 2287 case IP_VERSION(13, 0, 14): 2288 case IP_VERSION(13, 0, 15): 2289 case IP_VERSION(14, 0, 0): 2290 case IP_VERSION(14, 0, 1): 2291 case IP_VERSION(14, 0, 4): 2292 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 2293 break; 2294 case IP_VERSION(13, 0, 4): 2295 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 2296 break; 2297 case IP_VERSION(14, 0, 2): 2298 case IP_VERSION(14, 0, 3): 2299 case IP_VERSION(14, 0, 5): 2300 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 2301 break; 2302 case IP_VERSION(15, 0, 0): 2303 amdgpu_device_ip_block_add(adev, &psp_v15_0_ip_block); 2304 break; 2305 case IP_VERSION(15, 0, 8): 2306 amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block); 2307 break; 2308 default: 2309 dev_err(adev->dev, 2310 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 2311 amdgpu_ip_version(adev, MP0_HWIP, 0)); 2312 return -EINVAL; 2313 } 2314 return 0; 2315 } 2316 2317 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 2318 { 2319 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2320 case IP_VERSION(9, 0, 0): 2321 case IP_VERSION(10, 0, 0): 2322 case IP_VERSION(10, 0, 1): 2323 case IP_VERSION(11, 0, 2): 2324 if (adev->asic_type == CHIP_ARCTURUS) 2325 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2326 else 2327 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2328 break; 2329 case IP_VERSION(11, 0, 0): 2330 case IP_VERSION(11, 0, 5): 2331 case IP_VERSION(11, 0, 9): 2332 case IP_VERSION(11, 0, 7): 2333 case IP_VERSION(11, 0, 11): 2334 case IP_VERSION(11, 0, 12): 2335 case IP_VERSION(11, 0, 13): 2336 case IP_VERSION(11, 5, 0): 2337 case IP_VERSION(11, 5, 2): 2338 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2339 break; 2340 case IP_VERSION(11, 0, 8): 2341 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 2342 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2343 break; 2344 case IP_VERSION(12, 0, 0): 2345 case IP_VERSION(12, 0, 1): 2346 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 2347 break; 2348 case IP_VERSION(13, 0, 0): 2349 case IP_VERSION(13, 0, 1): 2350 case IP_VERSION(13, 0, 2): 2351 case IP_VERSION(13, 0, 3): 2352 case IP_VERSION(13, 0, 4): 2353 case IP_VERSION(13, 0, 5): 2354 case IP_VERSION(13, 0, 6): 2355 case IP_VERSION(13, 0, 7): 2356 case IP_VERSION(13, 0, 8): 2357 case IP_VERSION(13, 0, 10): 2358 case IP_VERSION(13, 0, 11): 2359 case IP_VERSION(13, 0, 14): 2360 case IP_VERSION(13, 0, 12): 2361 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2362 break; 2363 case IP_VERSION(14, 0, 0): 2364 case IP_VERSION(14, 0, 1): 2365 case IP_VERSION(14, 0, 2): 2366 case IP_VERSION(14, 0, 3): 2367 case IP_VERSION(14, 0, 4): 2368 case IP_VERSION(14, 0, 5): 2369 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2370 break; 2371 case IP_VERSION(15, 0, 0): 2372 case IP_VERSION(15, 0, 5): 2373 case IP_VERSION(15, 0, 8): 2374 amdgpu_device_ip_block_add(adev, &smu_v15_0_ip_block); 2375 break; 2376 default: 2377 dev_err(adev->dev, 2378 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2379 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2380 return -EINVAL; 2381 } 2382 return 0; 2383 } 2384 2385 #if defined(CONFIG_DRM_AMD_DC) 2386 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2387 { 2388 amdgpu_device_set_sriov_virtual_display(adev); 2389 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2390 } 2391 #endif 2392 2393 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2394 { 2395 if (adev->enable_virtual_display) { 2396 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2397 return 0; 2398 } 2399 2400 if (!amdgpu_device_has_dc_support(adev)) 2401 return 0; 2402 2403 #if defined(CONFIG_DRM_AMD_DC) 2404 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2405 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2406 case IP_VERSION(1, 0, 0): 2407 case IP_VERSION(1, 0, 1): 2408 case IP_VERSION(2, 0, 2): 2409 case IP_VERSION(2, 0, 0): 2410 case IP_VERSION(2, 0, 3): 2411 case IP_VERSION(2, 1, 0): 2412 case IP_VERSION(3, 0, 0): 2413 case IP_VERSION(3, 0, 2): 2414 case IP_VERSION(3, 0, 3): 2415 case IP_VERSION(3, 0, 1): 2416 case IP_VERSION(3, 1, 2): 2417 case IP_VERSION(3, 1, 3): 2418 case IP_VERSION(3, 1, 4): 2419 case IP_VERSION(3, 1, 5): 2420 case IP_VERSION(3, 1, 6): 2421 case IP_VERSION(3, 2, 0): 2422 case IP_VERSION(3, 2, 1): 2423 case IP_VERSION(3, 5, 0): 2424 case IP_VERSION(3, 5, 1): 2425 case IP_VERSION(3, 6, 0): 2426 case IP_VERSION(4, 1, 0): 2427 case IP_VERSION(4, 2, 0): 2428 case IP_VERSION(4, 2, 1): 2429 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2430 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2431 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2432 2433 if (amdgpu_sriov_vf(adev)) 2434 amdgpu_discovery_set_sriov_display(adev); 2435 else 2436 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2437 break; 2438 default: 2439 dev_err(adev->dev, 2440 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 2441 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2442 return -EINVAL; 2443 } 2444 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2445 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2446 case IP_VERSION(12, 0, 0): 2447 case IP_VERSION(12, 0, 1): 2448 case IP_VERSION(12, 1, 0): 2449 if (amdgpu_sriov_vf(adev)) 2450 amdgpu_discovery_set_sriov_display(adev); 2451 else 2452 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2453 break; 2454 default: 2455 dev_err(adev->dev, 2456 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 2457 amdgpu_ip_version(adev, DCI_HWIP, 0)); 2458 return -EINVAL; 2459 } 2460 } 2461 #endif 2462 return 0; 2463 } 2464 2465 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 2466 { 2467 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2468 case IP_VERSION(9, 0, 1): 2469 case IP_VERSION(9, 1, 0): 2470 case IP_VERSION(9, 2, 1): 2471 case IP_VERSION(9, 2, 2): 2472 case IP_VERSION(9, 3, 0): 2473 case IP_VERSION(9, 4, 0): 2474 case IP_VERSION(9, 4, 1): 2475 case IP_VERSION(9, 4, 2): 2476 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2477 break; 2478 case IP_VERSION(9, 4, 3): 2479 case IP_VERSION(9, 4, 4): 2480 case IP_VERSION(9, 5, 0): 2481 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2482 break; 2483 case IP_VERSION(10, 1, 10): 2484 case IP_VERSION(10, 1, 2): 2485 case IP_VERSION(10, 1, 1): 2486 case IP_VERSION(10, 1, 3): 2487 case IP_VERSION(10, 1, 4): 2488 case IP_VERSION(10, 3, 0): 2489 case IP_VERSION(10, 3, 2): 2490 case IP_VERSION(10, 3, 1): 2491 case IP_VERSION(10, 3, 4): 2492 case IP_VERSION(10, 3, 5): 2493 case IP_VERSION(10, 3, 6): 2494 case IP_VERSION(10, 3, 3): 2495 case IP_VERSION(10, 3, 7): 2496 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2497 break; 2498 case IP_VERSION(11, 0, 0): 2499 case IP_VERSION(11, 0, 1): 2500 case IP_VERSION(11, 0, 2): 2501 case IP_VERSION(11, 0, 3): 2502 case IP_VERSION(11, 0, 4): 2503 case IP_VERSION(11, 5, 0): 2504 case IP_VERSION(11, 5, 1): 2505 case IP_VERSION(11, 5, 2): 2506 case IP_VERSION(11, 5, 3): 2507 case IP_VERSION(11, 5, 4): 2508 case IP_VERSION(11, 5, 6): 2509 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2510 break; 2511 case IP_VERSION(12, 0, 0): 2512 case IP_VERSION(12, 0, 1): 2513 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 2514 break; 2515 case IP_VERSION(12, 1, 0): 2516 amdgpu_device_ip_block_add(adev, &gfx_v12_1_ip_block); 2517 break; 2518 default: 2519 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2520 amdgpu_ip_version(adev, GC_HWIP, 0)); 2521 return -EINVAL; 2522 } 2523 return 0; 2524 } 2525 2526 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2527 { 2528 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2529 case IP_VERSION(4, 0, 0): 2530 case IP_VERSION(4, 0, 1): 2531 case IP_VERSION(4, 1, 0): 2532 case IP_VERSION(4, 1, 1): 2533 case IP_VERSION(4, 1, 2): 2534 case IP_VERSION(4, 2, 0): 2535 case IP_VERSION(4, 2, 2): 2536 case IP_VERSION(4, 4, 0): 2537 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2538 break; 2539 case IP_VERSION(4, 4, 2): 2540 case IP_VERSION(4, 4, 5): 2541 case IP_VERSION(4, 4, 4): 2542 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2543 break; 2544 case IP_VERSION(5, 0, 0): 2545 case IP_VERSION(5, 0, 1): 2546 case IP_VERSION(5, 0, 2): 2547 case IP_VERSION(5, 0, 5): 2548 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2549 break; 2550 case IP_VERSION(5, 2, 0): 2551 case IP_VERSION(5, 2, 2): 2552 case IP_VERSION(5, 2, 4): 2553 case IP_VERSION(5, 2, 5): 2554 case IP_VERSION(5, 2, 6): 2555 case IP_VERSION(5, 2, 3): 2556 case IP_VERSION(5, 2, 1): 2557 case IP_VERSION(5, 2, 7): 2558 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2559 break; 2560 case IP_VERSION(6, 0, 0): 2561 case IP_VERSION(6, 0, 1): 2562 case IP_VERSION(6, 0, 2): 2563 case IP_VERSION(6, 0, 3): 2564 case IP_VERSION(6, 1, 0): 2565 case IP_VERSION(6, 1, 1): 2566 case IP_VERSION(6, 1, 2): 2567 case IP_VERSION(6, 1, 3): 2568 case IP_VERSION(6, 1, 4): 2569 case IP_VERSION(6, 4, 0): 2570 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2571 break; 2572 case IP_VERSION(7, 0, 0): 2573 case IP_VERSION(7, 0, 1): 2574 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 2575 break; 2576 case IP_VERSION(7, 1, 0): 2577 amdgpu_device_ip_block_add(adev, &sdma_v7_1_ip_block); 2578 break; 2579 default: 2580 dev_err(adev->dev, 2581 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2582 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2583 return -EINVAL; 2584 } 2585 2586 return 0; 2587 } 2588 2589 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev) 2590 { 2591 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2592 case IP_VERSION(13, 0, 6): 2593 case IP_VERSION(13, 0, 12): 2594 case IP_VERSION(13, 0, 14): 2595 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block); 2596 break; 2597 default: 2598 break; 2599 } 2600 return 0; 2601 } 2602 2603 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2604 { 2605 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2606 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2607 case IP_VERSION(7, 0, 0): 2608 case IP_VERSION(7, 2, 0): 2609 /* UVD is not supported on vega20 SR-IOV */ 2610 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2611 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2612 break; 2613 default: 2614 dev_err(adev->dev, 2615 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2616 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2617 return -EINVAL; 2618 } 2619 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2620 case IP_VERSION(4, 0, 0): 2621 case IP_VERSION(4, 1, 0): 2622 /* VCE is not supported on vega20 SR-IOV */ 2623 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2624 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2625 break; 2626 default: 2627 dev_err(adev->dev, 2628 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2629 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2630 return -EINVAL; 2631 } 2632 } else { 2633 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2634 case IP_VERSION(1, 0, 0): 2635 case IP_VERSION(1, 0, 1): 2636 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2637 break; 2638 case IP_VERSION(2, 0, 0): 2639 case IP_VERSION(2, 0, 2): 2640 case IP_VERSION(2, 2, 0): 2641 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2642 if (!amdgpu_sriov_vf(adev)) 2643 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2644 break; 2645 case IP_VERSION(2, 0, 3): 2646 break; 2647 case IP_VERSION(2, 5, 0): 2648 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2649 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2650 break; 2651 case IP_VERSION(2, 6, 0): 2652 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2653 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2654 break; 2655 case IP_VERSION(3, 0, 0): 2656 case IP_VERSION(3, 0, 16): 2657 case IP_VERSION(3, 1, 1): 2658 case IP_VERSION(3, 1, 2): 2659 case IP_VERSION(3, 0, 2): 2660 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2661 if (!amdgpu_sriov_vf(adev)) 2662 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2663 break; 2664 case IP_VERSION(3, 0, 33): 2665 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2666 break; 2667 case IP_VERSION(4, 0, 0): 2668 case IP_VERSION(4, 0, 2): 2669 case IP_VERSION(4, 0, 4): 2670 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2671 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2672 break; 2673 case IP_VERSION(4, 0, 3): 2674 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2675 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2676 break; 2677 case IP_VERSION(4, 0, 5): 2678 case IP_VERSION(4, 0, 6): 2679 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2680 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2681 break; 2682 case IP_VERSION(5, 0, 0): 2683 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2684 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2685 break; 2686 case IP_VERSION(5, 3, 0): 2687 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2688 amdgpu_device_ip_block_add(adev, &jpeg_v5_3_0_ip_block); 2689 break; 2690 case IP_VERSION(5, 0, 1): 2691 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); 2692 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); 2693 break; 2694 case IP_VERSION(5, 0, 2): 2695 amdgpu_device_ip_block_add(adev, &vcn_v5_0_2_ip_block); 2696 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_2_ip_block); 2697 break; 2698 default: 2699 dev_err(adev->dev, 2700 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2701 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2702 return -EINVAL; 2703 } 2704 } 2705 return 0; 2706 } 2707 2708 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2709 { 2710 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2711 case IP_VERSION(11, 0, 0): 2712 case IP_VERSION(11, 0, 1): 2713 case IP_VERSION(11, 0, 2): 2714 case IP_VERSION(11, 0, 3): 2715 case IP_VERSION(11, 0, 4): 2716 case IP_VERSION(11, 5, 0): 2717 case IP_VERSION(11, 5, 1): 2718 case IP_VERSION(11, 5, 2): 2719 case IP_VERSION(11, 5, 3): 2720 case IP_VERSION(11, 5, 4): 2721 case IP_VERSION(11, 5, 6): 2722 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2723 adev->enable_mes = true; 2724 adev->enable_mes_kiq = true; 2725 break; 2726 case IP_VERSION(12, 0, 0): 2727 case IP_VERSION(12, 0, 1): 2728 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 2729 adev->enable_mes = true; 2730 adev->enable_mes_kiq = true; 2731 if (amdgpu_uni_mes) 2732 adev->enable_uni_mes = true; 2733 break; 2734 case IP_VERSION(12, 1, 0): 2735 amdgpu_device_ip_block_add(adev, &mes_v12_1_ip_block); 2736 adev->enable_mes = true; 2737 adev->enable_mes_kiq = true; 2738 if (amdgpu_uni_mes) 2739 adev->enable_uni_mes = true; 2740 break; 2741 default: 2742 break; 2743 } 2744 return 0; 2745 } 2746 2747 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2748 { 2749 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2750 case IP_VERSION(9, 4, 3): 2751 case IP_VERSION(9, 4, 4): 2752 case IP_VERSION(9, 5, 0): 2753 aqua_vanjaram_init_soc_config(adev); 2754 break; 2755 case IP_VERSION(12, 1, 0): 2756 soc_v1_0_init_soc_config(adev); 2757 break; 2758 default: 2759 break; 2760 } 2761 } 2762 2763 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2764 { 2765 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2766 case IP_VERSION(6, 1, 0): 2767 case IP_VERSION(6, 1, 1): 2768 case IP_VERSION(6, 1, 3): 2769 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2770 break; 2771 case IP_VERSION(2, 0, 0): 2772 case IP_VERSION(2, 2, 0): 2773 amdgpu_device_ip_block_add(adev, &vpe_v2_0_ip_block); 2774 break; 2775 default: 2776 break; 2777 } 2778 2779 return 0; 2780 } 2781 2782 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2783 { 2784 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2785 case IP_VERSION(4, 0, 5): 2786 case IP_VERSION(4, 0, 6): 2787 if (amdgpu_umsch_mm & 0x1) { 2788 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2789 adev->enable_umsch_mm = true; 2790 } 2791 break; 2792 default: 2793 break; 2794 } 2795 2796 return 0; 2797 } 2798 2799 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev) 2800 { 2801 #if defined(CONFIG_DRM_AMD_ISP) 2802 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { 2803 case IP_VERSION(4, 1, 0): 2804 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block); 2805 break; 2806 case IP_VERSION(4, 1, 1): 2807 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block); 2808 break; 2809 default: 2810 break; 2811 } 2812 #endif 2813 2814 return 0; 2815 } 2816 2817 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2818 { 2819 int r; 2820 2821 switch (adev->asic_type) { 2822 case CHIP_VEGA10: 2823 /* This is not fatal. We only need the discovery 2824 * binary for sysfs. We don't need it for a 2825 * functional system. 2826 */ 2827 amdgpu_discovery_init(adev); 2828 vega10_reg_base_init(adev); 2829 adev->sdma.num_instances = 2; 2830 adev->sdma.sdma_mask = 3; 2831 adev->gmc.num_umc = 4; 2832 adev->gfx.xcc_mask = 1; 2833 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2834 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2835 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2836 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2837 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2838 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2839 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2840 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2841 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2842 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2843 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2844 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2845 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2846 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2847 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2848 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2849 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2850 break; 2851 case CHIP_VEGA12: 2852 /* This is not fatal. We only need the discovery 2853 * binary for sysfs. We don't need it for a 2854 * functional system. 2855 */ 2856 amdgpu_discovery_init(adev); 2857 vega10_reg_base_init(adev); 2858 adev->sdma.num_instances = 2; 2859 adev->sdma.sdma_mask = 3; 2860 adev->gmc.num_umc = 4; 2861 adev->gfx.xcc_mask = 1; 2862 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2863 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2864 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2865 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2866 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2867 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2868 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2869 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2870 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2871 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2872 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2873 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2874 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2875 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2876 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2877 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2878 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2879 break; 2880 case CHIP_RAVEN: 2881 /* This is not fatal. We only need the discovery 2882 * binary for sysfs. We don't need it for a 2883 * functional system. 2884 */ 2885 amdgpu_discovery_init(adev); 2886 vega10_reg_base_init(adev); 2887 adev->sdma.num_instances = 1; 2888 adev->sdma.sdma_mask = 1; 2889 adev->vcn.num_vcn_inst = 1; 2890 adev->gmc.num_umc = 2; 2891 adev->gfx.xcc_mask = 1; 2892 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2893 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2894 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2895 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2896 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2897 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2898 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2899 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2900 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2901 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2902 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2903 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2904 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2905 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2906 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2907 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2908 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2909 } else { 2910 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2911 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2912 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2913 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2914 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2915 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2916 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2917 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2918 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2919 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2920 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2921 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2922 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2923 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2924 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2925 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2926 } 2927 break; 2928 case CHIP_VEGA20: 2929 /* This is not fatal. We only need the discovery 2930 * binary for sysfs. We don't need it for a 2931 * functional system. 2932 */ 2933 amdgpu_discovery_init(adev); 2934 vega20_reg_base_init(adev); 2935 adev->sdma.num_instances = 2; 2936 adev->sdma.sdma_mask = 3; 2937 adev->gmc.num_umc = 8; 2938 adev->gfx.xcc_mask = 1; 2939 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2940 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2941 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2942 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2943 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2944 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2945 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2946 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2947 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2948 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2949 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2950 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2951 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2952 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2953 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2954 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2955 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2956 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2957 break; 2958 case CHIP_ARCTURUS: 2959 /* This is not fatal. We only need the discovery 2960 * binary for sysfs. We don't need it for a 2961 * functional system. 2962 */ 2963 amdgpu_discovery_init(adev); 2964 arct_reg_base_init(adev); 2965 adev->sdma.num_instances = 8; 2966 adev->sdma.sdma_mask = 0xff; 2967 adev->vcn.num_vcn_inst = 2; 2968 adev->gmc.num_umc = 8; 2969 adev->gfx.xcc_mask = 1; 2970 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2971 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2972 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2973 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2974 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2975 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2976 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2977 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2978 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2979 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2980 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2981 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2982 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2983 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2984 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2985 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2986 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2987 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2988 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2989 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2990 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2991 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2992 break; 2993 case CHIP_ALDEBARAN: 2994 /* This is not fatal. We only need the discovery 2995 * binary for sysfs. We don't need it for a 2996 * functional system. 2997 */ 2998 amdgpu_discovery_init(adev); 2999 aldebaran_reg_base_init(adev); 3000 adev->sdma.num_instances = 5; 3001 adev->sdma.sdma_mask = 0x1f; 3002 adev->vcn.num_vcn_inst = 2; 3003 adev->gmc.num_umc = 4; 3004 adev->gfx.xcc_mask = 1; 3005 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 3006 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 3007 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 3008 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 3009 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 3010 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 3011 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 3012 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 3013 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 3014 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 3015 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 3016 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 3017 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 3018 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 3019 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 3020 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 3021 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 3022 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 3023 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 3024 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 3025 break; 3026 case CHIP_CYAN_SKILLFISH: 3027 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 3028 r = amdgpu_discovery_reg_base_init(adev); 3029 if (r) 3030 return -EINVAL; 3031 3032 amdgpu_discovery_harvest_ip(adev); 3033 amdgpu_discovery_get_gfx_info(adev); 3034 amdgpu_discovery_get_mall_info(adev); 3035 amdgpu_discovery_get_vcn_info(adev); 3036 } else { 3037 cyan_skillfish_reg_base_init(adev); 3038 adev->sdma.num_instances = 2; 3039 adev->sdma.sdma_mask = 3; 3040 adev->gfx.xcc_mask = 1; 3041 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); 3042 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); 3043 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1); 3044 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1); 3045 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1); 3046 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1); 3047 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0); 3048 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1); 3049 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1); 3050 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8); 3051 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8); 3052 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1); 3053 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8); 3054 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3); 3055 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3); 3056 } 3057 break; 3058 default: 3059 r = amdgpu_discovery_reg_base_init(adev); 3060 if (r) { 3061 drm_err(&adev->ddev, "discovery failed: %d\n", r); 3062 return r; 3063 } 3064 3065 amdgpu_discovery_harvest_ip(adev); 3066 amdgpu_discovery_get_gfx_info(adev); 3067 amdgpu_discovery_get_mall_info(adev); 3068 amdgpu_discovery_get_vcn_info(adev); 3069 break; 3070 } 3071 3072 amdgpu_discovery_init_soc_config(adev); 3073 amdgpu_discovery_sysfs_init(adev); 3074 3075 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3076 case IP_VERSION(9, 0, 1): 3077 case IP_VERSION(9, 2, 1): 3078 case IP_VERSION(9, 4, 0): 3079 case IP_VERSION(9, 4, 1): 3080 case IP_VERSION(9, 4, 2): 3081 case IP_VERSION(9, 4, 3): 3082 case IP_VERSION(9, 4, 4): 3083 case IP_VERSION(9, 5, 0): 3084 adev->family = AMDGPU_FAMILY_AI; 3085 break; 3086 case IP_VERSION(9, 1, 0): 3087 case IP_VERSION(9, 2, 2): 3088 case IP_VERSION(9, 3, 0): 3089 adev->family = AMDGPU_FAMILY_RV; 3090 break; 3091 case IP_VERSION(10, 1, 10): 3092 case IP_VERSION(10, 1, 1): 3093 case IP_VERSION(10, 1, 2): 3094 case IP_VERSION(10, 1, 3): 3095 case IP_VERSION(10, 1, 4): 3096 case IP_VERSION(10, 3, 0): 3097 case IP_VERSION(10, 3, 2): 3098 case IP_VERSION(10, 3, 4): 3099 case IP_VERSION(10, 3, 5): 3100 adev->family = AMDGPU_FAMILY_NV; 3101 break; 3102 case IP_VERSION(10, 3, 1): 3103 adev->family = AMDGPU_FAMILY_VGH; 3104 adev->apu_flags |= AMD_APU_IS_VANGOGH; 3105 break; 3106 case IP_VERSION(10, 3, 3): 3107 adev->family = AMDGPU_FAMILY_YC; 3108 break; 3109 case IP_VERSION(10, 3, 6): 3110 adev->family = AMDGPU_FAMILY_GC_10_3_6; 3111 break; 3112 case IP_VERSION(10, 3, 7): 3113 adev->family = AMDGPU_FAMILY_GC_10_3_7; 3114 break; 3115 case IP_VERSION(11, 0, 0): 3116 case IP_VERSION(11, 0, 2): 3117 case IP_VERSION(11, 0, 3): 3118 adev->family = AMDGPU_FAMILY_GC_11_0_0; 3119 break; 3120 case IP_VERSION(11, 0, 1): 3121 case IP_VERSION(11, 0, 4): 3122 adev->family = AMDGPU_FAMILY_GC_11_0_1; 3123 break; 3124 case IP_VERSION(11, 5, 0): 3125 case IP_VERSION(11, 5, 1): 3126 case IP_VERSION(11, 5, 2): 3127 case IP_VERSION(11, 5, 3): 3128 case IP_VERSION(11, 5, 4): 3129 case IP_VERSION(11, 5, 6): 3130 adev->family = AMDGPU_FAMILY_GC_11_5_0; 3131 break; 3132 case IP_VERSION(12, 0, 0): 3133 case IP_VERSION(12, 0, 1): 3134 case IP_VERSION(12, 1, 0): 3135 adev->family = AMDGPU_FAMILY_GC_12_0_0; 3136 break; 3137 default: 3138 return -EINVAL; 3139 } 3140 3141 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3142 case IP_VERSION(9, 1, 0): 3143 case IP_VERSION(9, 2, 2): 3144 case IP_VERSION(9, 3, 0): 3145 case IP_VERSION(10, 1, 3): 3146 case IP_VERSION(10, 1, 4): 3147 case IP_VERSION(10, 3, 1): 3148 case IP_VERSION(10, 3, 3): 3149 case IP_VERSION(10, 3, 6): 3150 case IP_VERSION(10, 3, 7): 3151 case IP_VERSION(11, 0, 1): 3152 case IP_VERSION(11, 0, 4): 3153 case IP_VERSION(11, 5, 0): 3154 case IP_VERSION(11, 5, 1): 3155 case IP_VERSION(11, 5, 2): 3156 case IP_VERSION(11, 5, 3): 3157 case IP_VERSION(11, 5, 4): 3158 case IP_VERSION(11, 5, 6): 3159 adev->flags |= AMD_IS_APU; 3160 break; 3161 default: 3162 break; 3163 } 3164 3165 /* set NBIO version */ 3166 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 3167 case IP_VERSION(6, 1, 0): 3168 case IP_VERSION(6, 2, 0): 3169 adev->nbio.funcs = &nbio_v6_1_funcs; 3170 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 3171 break; 3172 case IP_VERSION(7, 0, 0): 3173 case IP_VERSION(7, 0, 1): 3174 case IP_VERSION(2, 5, 0): 3175 adev->nbio.funcs = &nbio_v7_0_funcs; 3176 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 3177 break; 3178 case IP_VERSION(7, 4, 0): 3179 case IP_VERSION(7, 4, 1): 3180 case IP_VERSION(7, 4, 4): 3181 adev->nbio.funcs = &nbio_v7_4_funcs; 3182 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 3183 break; 3184 case IP_VERSION(7, 9, 0): 3185 case IP_VERSION(7, 9, 1): 3186 adev->nbio.funcs = &nbio_v7_9_funcs; 3187 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 3188 break; 3189 case IP_VERSION(7, 11, 0): 3190 case IP_VERSION(7, 11, 1): 3191 case IP_VERSION(7, 11, 2): 3192 case IP_VERSION(7, 11, 3): 3193 adev->nbio.funcs = &nbio_v7_11_funcs; 3194 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 3195 break; 3196 case IP_VERSION(7, 2, 0): 3197 case IP_VERSION(7, 2, 1): 3198 case IP_VERSION(7, 3, 0): 3199 case IP_VERSION(7, 5, 0): 3200 case IP_VERSION(7, 5, 1): 3201 adev->nbio.funcs = &nbio_v7_2_funcs; 3202 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 3203 break; 3204 case IP_VERSION(2, 1, 1): 3205 case IP_VERSION(2, 3, 0): 3206 case IP_VERSION(2, 3, 1): 3207 case IP_VERSION(2, 3, 2): 3208 case IP_VERSION(3, 3, 0): 3209 case IP_VERSION(3, 3, 1): 3210 case IP_VERSION(3, 3, 2): 3211 case IP_VERSION(3, 3, 3): 3212 adev->nbio.funcs = &nbio_v2_3_funcs; 3213 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 3214 break; 3215 case IP_VERSION(4, 3, 0): 3216 case IP_VERSION(4, 3, 1): 3217 if (amdgpu_sriov_vf(adev)) 3218 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 3219 else 3220 adev->nbio.funcs = &nbio_v4_3_funcs; 3221 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 3222 break; 3223 case IP_VERSION(7, 7, 0): 3224 case IP_VERSION(7, 7, 1): 3225 adev->nbio.funcs = &nbio_v7_7_funcs; 3226 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 3227 break; 3228 case IP_VERSION(6, 3, 1): 3229 case IP_VERSION(7, 11, 4): 3230 case IP_VERSION(7, 11, 5): 3231 adev->nbio.funcs = &nbif_v6_3_1_funcs; 3232 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 3233 break; 3234 case IP_VERSION(6, 3, 2): 3235 adev->nbio.funcs = &nbio_v6_3_2_funcs; 3236 break; 3237 default: 3238 break; 3239 } 3240 3241 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 3242 case IP_VERSION(4, 0, 0): 3243 case IP_VERSION(4, 0, 1): 3244 case IP_VERSION(4, 1, 0): 3245 case IP_VERSION(4, 1, 1): 3246 case IP_VERSION(4, 1, 2): 3247 case IP_VERSION(4, 2, 0): 3248 case IP_VERSION(4, 2, 1): 3249 case IP_VERSION(4, 4, 0): 3250 case IP_VERSION(4, 4, 2): 3251 case IP_VERSION(4, 4, 5): 3252 adev->hdp.funcs = &hdp_v4_0_funcs; 3253 break; 3254 case IP_VERSION(5, 0, 0): 3255 case IP_VERSION(5, 0, 1): 3256 case IP_VERSION(5, 0, 2): 3257 case IP_VERSION(5, 0, 3): 3258 case IP_VERSION(5, 0, 4): 3259 case IP_VERSION(5, 2, 0): 3260 adev->hdp.funcs = &hdp_v5_0_funcs; 3261 break; 3262 case IP_VERSION(5, 2, 1): 3263 adev->hdp.funcs = &hdp_v5_2_funcs; 3264 break; 3265 case IP_VERSION(6, 0, 0): 3266 case IP_VERSION(6, 0, 1): 3267 case IP_VERSION(6, 1, 0): 3268 case IP_VERSION(6, 1, 1): 3269 case IP_VERSION(6, 4, 0): 3270 adev->hdp.funcs = &hdp_v6_0_funcs; 3271 break; 3272 case IP_VERSION(7, 0, 0): 3273 adev->hdp.funcs = &hdp_v7_0_funcs; 3274 break; 3275 default: 3276 break; 3277 } 3278 3279 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 3280 case IP_VERSION(3, 6, 0): 3281 case IP_VERSION(3, 6, 1): 3282 case IP_VERSION(3, 6, 2): 3283 adev->df.funcs = &df_v3_6_funcs; 3284 break; 3285 case IP_VERSION(2, 1, 0): 3286 case IP_VERSION(2, 1, 1): 3287 case IP_VERSION(2, 5, 0): 3288 case IP_VERSION(3, 5, 1): 3289 case IP_VERSION(3, 5, 2): 3290 adev->df.funcs = &df_v1_7_funcs; 3291 break; 3292 case IP_VERSION(4, 3, 0): 3293 adev->df.funcs = &df_v4_3_funcs; 3294 break; 3295 case IP_VERSION(4, 6, 2): 3296 adev->df.funcs = &df_v4_6_2_funcs; 3297 break; 3298 case IP_VERSION(4, 15, 0): 3299 case IP_VERSION(4, 15, 1): 3300 adev->df.funcs = &df_v4_15_funcs; 3301 break; 3302 default: 3303 break; 3304 } 3305 3306 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 3307 case IP_VERSION(9, 0, 0): 3308 case IP_VERSION(9, 0, 1): 3309 case IP_VERSION(10, 0, 0): 3310 case IP_VERSION(10, 0, 1): 3311 case IP_VERSION(10, 0, 2): 3312 adev->smuio.funcs = &smuio_v9_0_funcs; 3313 break; 3314 case IP_VERSION(11, 0, 0): 3315 case IP_VERSION(11, 0, 2): 3316 case IP_VERSION(11, 0, 3): 3317 case IP_VERSION(11, 0, 4): 3318 case IP_VERSION(11, 0, 7): 3319 case IP_VERSION(11, 0, 8): 3320 adev->smuio.funcs = &smuio_v11_0_funcs; 3321 break; 3322 case IP_VERSION(11, 0, 6): 3323 case IP_VERSION(11, 0, 10): 3324 case IP_VERSION(11, 0, 11): 3325 case IP_VERSION(11, 5, 0): 3326 case IP_VERSION(11, 5, 2): 3327 case IP_VERSION(13, 0, 1): 3328 case IP_VERSION(13, 0, 9): 3329 case IP_VERSION(13, 0, 10): 3330 adev->smuio.funcs = &smuio_v11_0_6_funcs; 3331 break; 3332 case IP_VERSION(13, 0, 2): 3333 adev->smuio.funcs = &smuio_v13_0_funcs; 3334 break; 3335 case IP_VERSION(13, 0, 3): 3336 case IP_VERSION(13, 0, 11): 3337 adev->smuio.funcs = &smuio_v13_0_3_funcs; 3338 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 3339 adev->flags |= AMD_IS_APU; 3340 } 3341 break; 3342 case IP_VERSION(13, 0, 6): 3343 case IP_VERSION(13, 0, 8): 3344 case IP_VERSION(14, 0, 0): 3345 case IP_VERSION(14, 0, 1): 3346 adev->smuio.funcs = &smuio_v13_0_6_funcs; 3347 break; 3348 case IP_VERSION(14, 0, 2): 3349 adev->smuio.funcs = &smuio_v14_0_2_funcs; 3350 break; 3351 case IP_VERSION(15, 0, 0): 3352 case IP_VERSION(15, 0, 5): 3353 adev->smuio.funcs = &smuio_v15_0_0_funcs; 3354 break; 3355 case IP_VERSION(15, 0, 8): 3356 adev->smuio.funcs = &smuio_v15_0_8_funcs; 3357 break; 3358 default: 3359 break; 3360 } 3361 3362 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 3363 case IP_VERSION(6, 0, 0): 3364 case IP_VERSION(6, 0, 1): 3365 case IP_VERSION(6, 0, 2): 3366 case IP_VERSION(6, 0, 3): 3367 adev->lsdma.funcs = &lsdma_v6_0_funcs; 3368 break; 3369 case IP_VERSION(7, 0, 0): 3370 case IP_VERSION(7, 0, 1): 3371 adev->lsdma.funcs = &lsdma_v7_0_funcs; 3372 break; 3373 case IP_VERSION(7, 1, 0): 3374 adev->lsdma.funcs = &lsdma_v7_1_funcs; 3375 break; 3376 default: 3377 break; 3378 } 3379 3380 r = amdgpu_discovery_set_common_ip_blocks(adev); 3381 if (r) 3382 return r; 3383 3384 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 3385 if (r) 3386 return r; 3387 3388 /* For SR-IOV, PSP needs to be initialized before IH */ 3389 if (amdgpu_sriov_vf(adev)) { 3390 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3391 if (r) 3392 return r; 3393 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3394 if (r) 3395 return r; 3396 } else { 3397 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3398 if (r) 3399 return r; 3400 3401 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3402 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3403 if (r) 3404 return r; 3405 } 3406 } 3407 3408 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3409 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3410 if (r) 3411 return r; 3412 } 3413 3414 r = amdgpu_discovery_set_display_ip_blocks(adev); 3415 if (r) 3416 return r; 3417 3418 r = amdgpu_discovery_set_gc_ip_blocks(adev); 3419 if (r) 3420 return r; 3421 3422 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 3423 if (r) 3424 return r; 3425 3426 r = amdgpu_discovery_set_ras_ip_blocks(adev); 3427 if (r) 3428 return r; 3429 3430 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 3431 !amdgpu_sriov_vf(adev) && 3432 amdgpu_dpm == 1) || 3433 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && 3434 amdgpu_dpm == 1)) { 3435 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3436 if (r) 3437 return r; 3438 } 3439 3440 r = amdgpu_discovery_set_mm_ip_blocks(adev); 3441 if (r) 3442 return r; 3443 3444 r = amdgpu_discovery_set_mes_ip_blocks(adev); 3445 if (r) 3446 return r; 3447 3448 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 3449 if (r) 3450 return r; 3451 3452 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 3453 if (r) 3454 return r; 3455 3456 r = amdgpu_discovery_set_isp_ip_blocks(adev); 3457 if (r) 3458 return r; 3459 return 0; 3460 } 3461 3462 int amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device *adev, 3463 uint16_t *major, uint16_t *minor) 3464 { 3465 uint8_t *discovery_bin = adev->discovery.bin; 3466 struct table_info *info; 3467 union gc_info *gc_info; 3468 u16 offset; 3469 3470 if (!discovery_bin) 3471 return -EINVAL; 3472 if (amdgpu_discovery_get_table_info(adev, &info, GC)) 3473 return -EINVAL; 3474 3475 offset = le16_to_cpu(info->offset); 3476 if (!offset) 3477 return -EINVAL; 3478 3479 gc_info = (union gc_info *)(discovery_bin + offset); 3480 3481 if (major) 3482 *major = le16_to_cpu(gc_info->v1.header.version_major); 3483 if (minor) 3484 *minor = le16_to_cpu(gc_info->v1.header.version_minor); 3485 return 0; 3486 } 3487