1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SC16IS7xx tty serial driver - common code 4 * 5 * Copyright (C) 2014 GridPoint 6 * Author: Jon Ringle <jringle@gridpoint.com> 7 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> 8 */ 9 10 #undef DEFAULT_SYMBOL_NAMESPACE 11 #define DEFAULT_SYMBOL_NAMESPACE "SERIAL_NXP_SC16IS7XX" 12 13 #include <linux/bits.h> 14 #include <linux/cleanup.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/device.h> 18 #include <linux/export.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/gpio/driver.h> 21 #include <linux/idr.h> 22 #include <linux/kthread.h> 23 #include <linux/module.h> 24 #include <linux/property.h> 25 #include <linux/regmap.h> 26 #include <linux/sched.h> 27 #include <linux/serial_core.h> 28 #include <linux/serial.h> 29 #include <linux/string.h> 30 #include <linux/tty.h> 31 #include <linux/tty_flip.h> 32 #include <linux/uaccess.h> 33 #include <linux/units.h> 34 35 #include "sc16is7xx.h" 36 37 #define SC16IS7XX_MAX_DEVS 8 38 39 /* SC16IS7XX register definitions */ 40 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ 41 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ 42 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ 43 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ 44 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ 45 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */ 46 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ 47 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */ 48 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ 49 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 50 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 51 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 52 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction - only on 75x/76x */ 53 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State - only on 75x/76x */ 54 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable - only on 75x/76x */ 55 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control - only on 75x/76x */ 56 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 57 58 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ 59 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ 60 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ 61 62 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ 63 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ 64 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ 65 66 /* Enhanced Register set: Only if (LCR == 0xBF) */ 67 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ 68 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ 69 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ 70 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ 71 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 72 73 /* IER register bits */ 74 #define SC16IS7XX_IER_RDI_BIT BIT(0) /* Enable RX data interrupt */ 75 #define SC16IS7XX_IER_THRI_BIT BIT(1) /* Enable TX holding register interrupt */ 76 #define SC16IS7XX_IER_RLSI_BIT BIT(2) /* Enable RX line status interrupt */ 77 #define SC16IS7XX_IER_MSI_BIT BIT(3) /* Enable Modem status interrupt */ 78 79 /* IER register bits - write only if (EFR[4] == 1) */ 80 #define SC16IS7XX_IER_SLEEP_BIT BIT(4) /* Enable Sleep mode */ 81 #define SC16IS7XX_IER_XOFFI_BIT BIT(5) /* Enable Xoff interrupt */ 82 #define SC16IS7XX_IER_RTSI_BIT BIT(6) /* Enable nRTS interrupt */ 83 #define SC16IS7XX_IER_CTSI_BIT BIT(7) /* Enable nCTS interrupt */ 84 85 /* FCR register bits */ 86 #define SC16IS7XX_FCR_FIFO_BIT BIT(0) /* Enable FIFO */ 87 #define SC16IS7XX_FCR_RXRESET_BIT BIT(1) /* Reset RX FIFO */ 88 #define SC16IS7XX_FCR_TXRESET_BIT BIT(2) /* Reset TX FIFO */ 89 #define SC16IS7XX_FCR_RXLVLL_BIT BIT(6) /* RX Trigger level LSB */ 90 #define SC16IS7XX_FCR_RXLVLH_BIT BIT(7) /* RX Trigger level MSB */ 91 92 /* FCR register bits - write only if (EFR[4] == 1) */ 93 #define SC16IS7XX_FCR_TXLVLL_BIT BIT(4) /* TX Trigger level LSB */ 94 #define SC16IS7XX_FCR_TXLVLH_BIT BIT(5) /* TX Trigger level MSB */ 95 96 /* IIR register bits */ 97 #define SC16IS7XX_IIR_NO_INT_BIT 0x01 /* No interrupts pending */ 98 #define SC16IS7XX_IIR_ID_MASK GENMASK(5, 1) /* Mask for the interrupt ID */ 99 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 100 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 101 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 102 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 103 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 104 * - only on 75x/76x 105 */ 106 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 107 * - only on 75x/76x 108 */ 109 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 110 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state from active 111 * (LOW) to inactive (HIGH) 112 */ 113 /* LCR register bits */ 114 #define SC16IS7XX_LCR_LENGTH0_BIT BIT(0) /* Word length bit 0 */ 115 #define SC16IS7XX_LCR_LENGTH1_BIT BIT(1) /* Word length bit 1 116 * 117 * Word length bits table: 118 * 00 -> 5 bit words 119 * 01 -> 6 bit words 120 * 10 -> 7 bit words 121 * 11 -> 8 bit words 122 */ 123 #define SC16IS7XX_LCR_STOPLEN_BIT BIT(2) /* STOP length bit 124 * 125 * STOP length bit table: 126 * 0 -> 1 stop bit 127 * 1 -> 1-1.5 stop bits if word length is 5, 128 * 2 stop bits otherwise 129 */ 130 #define SC16IS7XX_LCR_PARITY_BIT BIT(3) /* Parity bit enable */ 131 #define SC16IS7XX_LCR_EVENPARITY_BIT BIT(4) /* Even parity bit enable */ 132 #define SC16IS7XX_LCR_FORCEPARITY_BIT BIT(5) /* 9-bit multidrop parity */ 133 #define SC16IS7XX_LCR_TXBREAK_BIT BIT(6) /* TX break enable */ 134 #define SC16IS7XX_LCR_DLAB_BIT BIT(7) /* Divisor Latch enable */ 135 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 136 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 137 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 138 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 139 #define SC16IS7XX_LCR_REG_SET_SPECIAL SC16IS7XX_LCR_DLAB_BIT /* Special reg set */ 140 #define SC16IS7XX_LCR_REG_SET_ENHANCED 0xBF /* Enhanced reg set */ 141 142 /* MCR register bits */ 143 #define SC16IS7XX_MCR_DTR_BIT BIT(0) /* DTR complement - only on 75x/76x */ 144 #define SC16IS7XX_MCR_RTS_BIT BIT(1) /* RTS complement */ 145 #define SC16IS7XX_MCR_TCRTLR_BIT BIT(2) /* TCR/TLR registers enable */ 146 #define SC16IS7XX_MCR_LOOP_BIT BIT(4) /* Enable loopback test mode */ 147 #define SC16IS7XX_MCR_XONANY_BIT BIT(5) /* Enable Xon Any 148 * - write enabled if (EFR[4] == 1) 149 */ 150 #define SC16IS7XX_MCR_IRDA_BIT BIT(6) /* Enable IrDA mode 151 * - write enabled if (EFR[4] == 1) 152 */ 153 #define SC16IS7XX_MCR_CLKSEL_BIT BIT(7) /* Divide clock by 4 154 * - write enabled if (EFR[4] == 1) 155 */ 156 157 /* LSR register bits */ 158 #define SC16IS7XX_LSR_DR_BIT BIT(0) /* Receiver data ready */ 159 #define SC16IS7XX_LSR_OE_BIT BIT(1) /* Overrun Error */ 160 #define SC16IS7XX_LSR_PE_BIT BIT(2) /* Parity Error */ 161 #define SC16IS7XX_LSR_FE_BIT BIT(3) /* Frame Error */ 162 #define SC16IS7XX_LSR_BI_BIT BIT(4) /* Break Interrupt */ 163 #define SC16IS7XX_LSR_BRK_ERROR_MASK \ 164 (SC16IS7XX_LSR_OE_BIT | \ 165 SC16IS7XX_LSR_PE_BIT | \ 166 SC16IS7XX_LSR_FE_BIT | \ 167 SC16IS7XX_LSR_BI_BIT) 168 169 #define SC16IS7XX_LSR_THRE_BIT BIT(5) /* TX holding register empty */ 170 #define SC16IS7XX_LSR_TEMT_BIT BIT(6) /* Transmitter empty */ 171 #define SC16IS7XX_LSR_FIFOE_BIT BIT(7) /* Fifo Error */ 172 173 /* MSR register bits */ 174 #define SC16IS7XX_MSR_DCTS_BIT BIT(0) /* Delta CTS Clear To Send */ 175 #define SC16IS7XX_MSR_DDSR_BIT BIT(1) /* Delta DSR Data Set Ready or (IO4) 176 * - only on 75x/76x 177 */ 178 #define SC16IS7XX_MSR_DRI_BIT BIT(2) /* Delta RI Ring Indicator or (IO7) 179 * - only on 75x/76x 180 */ 181 #define SC16IS7XX_MSR_DCD_BIT BIT(3) /* Delta CD Carrier Detect or (IO6) 182 * - only on 75x/76x 183 */ 184 #define SC16IS7XX_MSR_CTS_BIT BIT(4) /* CTS */ 185 #define SC16IS7XX_MSR_DSR_BIT BIT(5) /* DSR (IO4) - only on 75x/76x */ 186 #define SC16IS7XX_MSR_RI_BIT BIT(6) /* RI (IO7) - only on 75x/76x */ 187 #define SC16IS7XX_MSR_CD_BIT BIT(7) /* CD (IO6) - only on 75x/76x */ 188 189 /* 190 * TCR register bits 191 * TCR trigger levels are available from 0 to 60 characters with a granularity 192 * of four. 193 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is 194 * no built-in hardware check to make sure this condition is met. Also, the TCR 195 * must be programmed with this condition before auto RTS or software flow 196 * control is enabled to avoid spurious operation of the device. 197 */ 198 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) 199 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) 200 201 /* 202 * TLR register bits 203 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the 204 * FIFO Control Register (FCR) are used for the transmit and receive FIFO 205 * trigger levels. Trigger levels from 4 characters to 60 characters are 206 * available with a granularity of four. 207 * 208 * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the 209 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 210 * the trigger level defined in FCR is discarded. This applies to both transmit 211 * FIFO and receive FIFO trigger level setting. 212 * 213 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the 214 * default state, that is, '00'. 215 */ 216 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 217 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 218 219 #define SC16IS7XX_TX_TRIGGER_LEVEL 32 220 221 /* IOControl register bits (Only 75x/76x) */ 222 #define SC16IS7XX_IOCONTROL_LATCH_BIT BIT(0) /* Enable input latching */ 223 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT BIT(1) /* Enable GPIO[7:4] as modem A pins */ 224 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT BIT(2) /* Enable GPIO[3:0] as modem B pins */ 225 #define SC16IS7XX_IOCONTROL_SRESET_BIT BIT(3) /* Software Reset */ 226 227 /* EFCR register bits */ 228 #define SC16IS7XX_EFCR_9BIT_MODE_BIT BIT(0) /* Enable 9-bit or Multidrop mode (RS485) */ 229 #define SC16IS7XX_EFCR_RXDISABLE_BIT BIT(1) /* Disable receiver */ 230 #define SC16IS7XX_EFCR_TXDISABLE_BIT BIT(2) /* Disable transmitter */ 231 #define SC16IS7XX_EFCR_AUTO_RS485_BIT BIT(4) /* Auto RS485 RTS direction */ 232 #define SC16IS7XX_EFCR_RTS_INVERT_BIT BIT(5) /* RTS output inversion */ 233 #define SC16IS7XX_EFCR_IRDA_MODE_BIT BIT(7) /* IrDA mode 234 * 0 = rate up to 115.2 kbit/s - Only 75x/76x 235 * 1 = rate up to 1.152 Mbit/s - Only 76x 236 */ 237 238 /* EFR register bits */ 239 #define SC16IS7XX_EFR_AUTORTS_BIT BIT(6) /* Auto RTS flow ctrl enable */ 240 #define SC16IS7XX_EFR_AUTOCTS_BIT BIT(7) /* Auto CTS flow ctrl enable */ 241 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT BIT(5) /* Enable Xoff2 detection */ 242 #define SC16IS7XX_EFR_ENABLE_BIT BIT(4) /* Enable enhanced functions and writing to 243 * IER[7:4], FCR[5:4], MCR[7:5] 244 */ 245 #define SC16IS7XX_EFR_SWFLOW3_BIT BIT(3) 246 #define SC16IS7XX_EFR_SWFLOW2_BIT BIT(2) 247 /* 248 * SWFLOW bits 3 & 2 table: 249 * 00 -> no transmitter flow control 250 * 01 -> transmitter generates XON2 and XOFF2 251 * 10 -> transmitter generates XON1 and XOFF1 252 * 11 -> transmitter generates XON1, XON2, 253 * XOFF1 and XOFF2 254 */ 255 #define SC16IS7XX_EFR_SWFLOW1_BIT BIT(1) 256 #define SC16IS7XX_EFR_SWFLOW0_BIT BIT(0) 257 /* 258 * SWFLOW bits 1 & 0 table: 259 * 00 -> no received flow control 260 * 01 -> receiver compares XON2 and XOFF2 261 * 10 -> receiver compares XON1 and XOFF1 262 * 11 -> receiver compares XON1, XON2, 263 * XOFF1 and XOFF2 264 */ 265 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \ 266 SC16IS7XX_EFR_AUTOCTS_BIT | \ 267 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \ 268 SC16IS7XX_EFR_SWFLOW3_BIT | \ 269 SC16IS7XX_EFR_SWFLOW2_BIT | \ 270 SC16IS7XX_EFR_SWFLOW1_BIT | \ 271 SC16IS7XX_EFR_SWFLOW0_BIT) 272 273 274 /* Misc definitions */ 275 #define SC16IS7XX_FIFO_SIZE (64) 276 #define SC16IS7XX_GPIOS_PER_BANK 4 277 278 #define SC16IS7XX_POLL_PERIOD_MS 10 279 #define SC16IS7XX_RECONF_MD BIT(0) 280 #define SC16IS7XX_RECONF_IER BIT(1) 281 #define SC16IS7XX_RECONF_RS485 BIT(2) 282 283 struct sc16is7xx_one_config { 284 unsigned int flags; 285 u8 ier_mask; 286 u8 ier_val; 287 }; 288 289 struct sc16is7xx_one { 290 struct uart_port port; 291 struct regmap *regmap; 292 struct mutex lock; /* For registers sharing same address space. */ 293 struct kthread_work tx_work; 294 struct kthread_work reg_work; 295 struct kthread_delayed_work ms_work; 296 struct sc16is7xx_one_config config; 297 unsigned char buf[SC16IS7XX_FIFO_SIZE]; /* Rx buffer. */ 298 unsigned int old_mctrl; 299 u8 old_lcr; /* Value before EFR access. */ 300 bool irda_mode; 301 }; 302 303 struct sc16is7xx_port { 304 const struct sc16is7xx_devtype *devtype; 305 struct clk *clk; 306 #ifdef CONFIG_GPIOLIB 307 struct gpio_chip gpio; 308 unsigned long gpio_valid_mask; 309 #endif 310 u8 mctrl_mask; 311 struct kthread_worker kworker; 312 struct task_struct *kworker_task; 313 struct kthread_delayed_work poll_work; 314 bool polling; 315 struct sc16is7xx_one p[]; 316 }; 317 318 static DEFINE_IDA(sc16is7xx_lines); 319 320 static struct uart_driver sc16is7xx_uart = { 321 .owner = THIS_MODULE, 322 .driver_name = KBUILD_MODNAME, 323 .dev_name = "ttySC", 324 .nr = SC16IS7XX_MAX_DEVS, 325 }; 326 327 #define to_sc16is7xx_one(p) container_of((p), struct sc16is7xx_one, port) 328 329 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) 330 { 331 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 332 unsigned int val = 0; 333 334 regmap_read(one->regmap, reg, &val); 335 336 return val; 337 } 338 339 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) 340 { 341 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 342 343 regmap_write(one->regmap, reg, val); 344 } 345 346 static void sc16is7xx_fifo_read(struct uart_port *port, u8 *rxbuf, unsigned int rxlen) 347 { 348 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 349 350 regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, rxbuf, rxlen); 351 } 352 353 static void sc16is7xx_fifo_write(struct uart_port *port, u8 *txbuf, u8 to_send) 354 { 355 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 356 357 /* 358 * Don't send zero-length data, at least on SPI it confuses the chip 359 * delivering wrong TXLVL data. 360 */ 361 if (unlikely(!to_send)) 362 return; 363 364 regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, txbuf, to_send); 365 } 366 367 static void sc16is7xx_port_update(struct uart_port *port, u8 reg, 368 u8 mask, u8 val) 369 { 370 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 371 372 regmap_update_bits(one->regmap, reg, mask, val); 373 } 374 375 static void sc16is7xx_power(struct uart_port *port, int on) 376 { 377 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 378 SC16IS7XX_IER_SLEEP_BIT, 379 on ? 0 : SC16IS7XX_IER_SLEEP_BIT); 380 } 381 382 /* 383 * In an amazing feat of design, the enhanced register set shares the 384 * addresses 0x02 and 0x04-0x07 with the general register set. 385 * The special register set also shares the addresses 0x00-0x01 with the 386 * general register set. 387 * 388 * Access to the enhanced or special register set is enabled by writing a magic 389 * value to the Line Control Register (LCR). When enhanced register set access 390 * is enabled, for example, any interrupt firing during this time will see the 391 * EFR where it expects the IIR to be, leading to 392 * "Unexpected interrupt" messages. 393 * 394 * Prevent this possibility by claiming a mutex when access to the enhanced 395 * or special register set is enabled, and claiming the same mutex from within 396 * the interrupt handler. This is similar to disabling the interrupt, but that 397 * doesn't work because the bulk of the interrupt processing is run as a 398 * workqueue job in thread context. 399 */ 400 static void sc16is7xx_regs_lock(struct uart_port *port, u8 register_set) 401 { 402 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 403 404 mutex_lock(&one->lock); 405 406 /* Backup content of LCR. */ 407 one->old_lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 408 409 /* Enable access to the desired register set */ 410 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, register_set); 411 412 /* Disable cache updates when writing to non-general registers */ 413 regcache_cache_bypass(one->regmap, true); 414 } 415 416 static void sc16is7xx_regs_unlock(struct uart_port *port) 417 { 418 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 419 420 /* Re-enable cache updates when writing to general registers */ 421 regcache_cache_bypass(one->regmap, false); 422 423 /* Restore original content of LCR */ 424 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, one->old_lcr); 425 426 mutex_unlock(&one->lock); 427 } 428 429 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) 430 { 431 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 432 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 433 434 lockdep_assert_held_once(&port->lock); 435 436 one->config.flags |= SC16IS7XX_RECONF_IER; 437 one->config.ier_mask |= bit; 438 one->config.ier_val &= ~bit; 439 kthread_queue_work(&s->kworker, &one->reg_work); 440 } 441 442 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit) 443 { 444 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 445 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 446 447 lockdep_assert_held_once(&port->lock); 448 449 one->config.flags |= SC16IS7XX_RECONF_IER; 450 one->config.ier_mask |= bit; 451 one->config.ier_val |= bit; 452 kthread_queue_work(&s->kworker, &one->reg_work); 453 } 454 455 static void sc16is7xx_stop_tx(struct uart_port *port) 456 { 457 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); 458 } 459 460 static void sc16is7xx_stop_rx(struct uart_port *port) 461 { 462 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 463 } 464 465 const struct sc16is7xx_devtype sc16is74x_devtype = { 466 .name = "SC16IS74X", 467 .nr_gpio = 0, 468 .nr_uart = 1, 469 }; 470 EXPORT_SYMBOL_GPL(sc16is74x_devtype); 471 472 const struct sc16is7xx_devtype sc16is750_devtype = { 473 .name = "SC16IS750", 474 .nr_gpio = 8, 475 .nr_uart = 1, 476 }; 477 EXPORT_SYMBOL_GPL(sc16is750_devtype); 478 479 const struct sc16is7xx_devtype sc16is752_devtype = { 480 .name = "SC16IS752", 481 .nr_gpio = 8, 482 .nr_uart = 2, 483 }; 484 EXPORT_SYMBOL_GPL(sc16is752_devtype); 485 486 const struct sc16is7xx_devtype sc16is760_devtype = { 487 .name = "SC16IS760", 488 .nr_gpio = 8, 489 .nr_uart = 1, 490 }; 491 EXPORT_SYMBOL_GPL(sc16is760_devtype); 492 493 const struct sc16is7xx_devtype sc16is762_devtype = { 494 .name = "SC16IS762", 495 .nr_gpio = 8, 496 .nr_uart = 2, 497 }; 498 EXPORT_SYMBOL_GPL(sc16is762_devtype); 499 500 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) 501 { 502 switch (reg) { 503 case SC16IS7XX_RHR_REG: /* Shared address space with THR & DLL */ 504 case SC16IS7XX_IIR_REG: /* Shared address space with FCR & EFR */ 505 case SC16IS7XX_LSR_REG: /* Shared address space with XON2 */ 506 case SC16IS7XX_MSR_REG: /* Shared address space with TCR & XOFF1 */ 507 case SC16IS7XX_SPR_REG: /* Shared address space with TLR & XOFF2 */ 508 case SC16IS7XX_TXLVL_REG: 509 case SC16IS7XX_RXLVL_REG: 510 case SC16IS7XX_IOSTATE_REG: 511 case SC16IS7XX_IOCONTROL_REG: 512 return true; 513 default: 514 return false; 515 } 516 } 517 518 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) 519 { 520 switch (reg) { 521 case SC16IS7XX_RHR_REG: 522 return true; 523 default: 524 return false; 525 } 526 } 527 528 static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg) 529 { 530 return reg == SC16IS7XX_RHR_REG; 531 } 532 533 /* 534 * Configure programmable baud rate generator (divisor) according to the 535 * desired baud rate. 536 * 537 * From the datasheet, the divisor is computed according to: 538 * 539 * XTAL1 input frequency 540 * ----------------------- 541 * prescaler 542 * divisor = --------------------------- 543 * baud-rate x sampling-rate 544 */ 545 static int sc16is7xx_set_baud(struct uart_port *port, int baud) 546 { 547 unsigned int prescaler = 1; 548 unsigned long clk = port->uartclk, div = clk / 16 / baud; 549 550 if (div >= BIT(16)) { 551 prescaler = 4; 552 div /= prescaler; 553 } 554 555 /* If bit MCR_CLKSEL is set, the divide by 4 prescaler is activated. */ 556 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 557 SC16IS7XX_MCR_CLKSEL_BIT, 558 prescaler == 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT); 559 560 /* Access special register set (DLL/DLH) */ 561 sc16is7xx_regs_lock(port, SC16IS7XX_LCR_REG_SET_SPECIAL); 562 563 /* Write the new divisor */ 564 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 565 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 566 567 /* Restore access to general register set */ 568 sc16is7xx_regs_unlock(port); 569 570 return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div); 571 } 572 573 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, 574 unsigned int iir) 575 { 576 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 577 unsigned int lsr = 0, bytes_read, i; 578 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC); 579 u8 ch, flag; 580 581 if (unlikely(rxlen >= sizeof(one->buf))) { 582 dev_warn_ratelimited(port->dev, 583 "ttySC%i: Possible RX FIFO overrun: %d\n", 584 port->line, rxlen); 585 port->icount.buf_overrun++; 586 /* Ensure sanity of RX level */ 587 rxlen = sizeof(one->buf); 588 } 589 590 while (rxlen) { 591 /* Only read lsr if there are possible errors in FIFO */ 592 if (read_lsr) { 593 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 594 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) 595 read_lsr = false; /* No errors left in FIFO */ 596 } else 597 lsr = 0; 598 599 if (read_lsr) { 600 one->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); 601 bytes_read = 1; 602 } else { 603 sc16is7xx_fifo_read(port, one->buf, rxlen); 604 bytes_read = rxlen; 605 } 606 607 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; 608 609 port->icount.rx++; 610 flag = TTY_NORMAL; 611 612 if (unlikely(lsr)) { 613 if (lsr & SC16IS7XX_LSR_BI_BIT) { 614 port->icount.brk++; 615 if (uart_handle_break(port)) 616 continue; 617 } else if (lsr & SC16IS7XX_LSR_PE_BIT) 618 port->icount.parity++; 619 else if (lsr & SC16IS7XX_LSR_FE_BIT) 620 port->icount.frame++; 621 else if (lsr & SC16IS7XX_LSR_OE_BIT) 622 port->icount.overrun++; 623 624 lsr &= port->read_status_mask; 625 if (lsr & SC16IS7XX_LSR_BI_BIT) 626 flag = TTY_BREAK; 627 else if (lsr & SC16IS7XX_LSR_PE_BIT) 628 flag = TTY_PARITY; 629 else if (lsr & SC16IS7XX_LSR_FE_BIT) 630 flag = TTY_FRAME; 631 else if (lsr & SC16IS7XX_LSR_OE_BIT) 632 flag = TTY_OVERRUN; 633 } 634 635 for (i = 0; i < bytes_read; ++i) { 636 ch = one->buf[i]; 637 if (uart_handle_sysrq_char(port, ch)) 638 continue; 639 640 if (lsr & port->ignore_status_mask) 641 continue; 642 643 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, 644 flag); 645 } 646 rxlen -= bytes_read; 647 } 648 649 tty_flip_buffer_push(&port->state->port); 650 } 651 652 static unsigned int sc16is7xx_txlvl(struct uart_port *port) 653 { 654 unsigned int txlvl; 655 656 txlvl = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 657 if (txlvl > SC16IS7XX_FIFO_SIZE) { 658 dev_err_ratelimited(port->dev, 659 "chip reports %u free bytes in TX FIFO, but it only has %u\n", 660 txlvl, SC16IS7XX_FIFO_SIZE); 661 return 0; 662 } 663 664 return txlvl; 665 } 666 667 static void sc16is7xx_handle_tx(struct uart_port *port) 668 { 669 struct tty_port *tport = &port->state->port; 670 unsigned long flags; 671 unsigned int txlen; 672 673 if (unlikely(port->x_char)) { 674 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); 675 port->icount.tx++; 676 port->x_char = 0; 677 return; 678 } 679 680 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) { 681 uart_port_lock_irqsave(port, &flags); 682 sc16is7xx_stop_tx(port); 683 uart_port_unlock_irqrestore(port, flags); 684 return; 685 } 686 687 /* Limit to space available in TX FIFO */ 688 txlen = sc16is7xx_txlvl(port); 689 690 /* Handle circular buffer wrap-around by sending multiple segments */ 691 while (txlen > 0 && !kfifo_is_empty(&tport->xmit_fifo)) { 692 unsigned char *tail; 693 unsigned int to_send; 694 695 to_send = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, txlen); 696 if (!to_send) 697 break; 698 699 sc16is7xx_fifo_write(port, tail, to_send); 700 uart_xmit_advance(port, to_send); 701 702 if (kfifo_is_empty(&tport->xmit_fifo)) 703 break; 704 705 /* Refill below the trigger to enable the next THRI crossing. */ 706 txlen = sc16is7xx_txlvl(port); 707 if (txlen < SC16IS7XX_TX_TRIGGER_LEVEL) 708 break; 709 } 710 711 uart_port_lock_irqsave(port, &flags); 712 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 713 uart_write_wakeup(port); 714 715 if (kfifo_is_empty(&tport->xmit_fifo)) 716 sc16is7xx_stop_tx(port); 717 else 718 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT); 719 uart_port_unlock_irqrestore(port, flags); 720 } 721 722 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port) 723 { 724 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG); 725 unsigned int mctrl = 0; 726 727 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0; 728 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0; 729 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0; 730 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0; 731 return mctrl; 732 } 733 734 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one) 735 { 736 struct uart_port *port = &one->port; 737 unsigned long flags; 738 unsigned int status, changed; 739 740 /* Lock required as MSR address is shared with TCR and XOFF1. */ 741 lockdep_assert_held_once(&one->lock); 742 743 status = sc16is7xx_get_hwmctrl(port); 744 changed = status ^ one->old_mctrl; 745 746 if (changed == 0) 747 return; 748 749 one->old_mctrl = status; 750 751 uart_port_lock_irqsave(port, &flags); 752 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG)) 753 port->icount.rng++; 754 if (changed & TIOCM_DSR) 755 port->icount.dsr++; 756 if (changed & TIOCM_CAR) 757 uart_handle_dcd_change(port, status & TIOCM_CAR); 758 if (changed & TIOCM_CTS) 759 uart_handle_cts_change(port, status & TIOCM_CTS); 760 761 wake_up_interruptible(&port->state->port.delta_msr_wait); 762 uart_port_unlock_irqrestore(port, flags); 763 } 764 765 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) 766 { 767 unsigned int iir, rxlen; 768 struct uart_port *port = &s->p[portno].port; 769 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 770 771 guard(mutex)(&one->lock); 772 773 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); 774 if (iir & SC16IS7XX_IIR_NO_INT_BIT) 775 return false; 776 777 iir &= SC16IS7XX_IIR_ID_MASK; 778 779 switch (iir) { 780 case SC16IS7XX_IIR_RDI_SRC: 781 case SC16IS7XX_IIR_RLSE_SRC: 782 case SC16IS7XX_IIR_RTOI_SRC: 783 case SC16IS7XX_IIR_XOFFI_SRC: 784 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); 785 786 /* 787 * There is a silicon bug that makes the chip report a 788 * time-out interrupt but no data in the FIFO. This is 789 * described in errata section 18.1.4. 790 * 791 * When this happens, read one byte from the FIFO to 792 * clear the interrupt. 793 */ 794 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen) 795 rxlen = 1; 796 797 if (rxlen) 798 sc16is7xx_handle_rx(port, rxlen, iir); 799 break; 800 /* CTSRTS interrupt comes only when CTS goes inactive */ 801 case SC16IS7XX_IIR_CTSRTS_SRC: 802 case SC16IS7XX_IIR_MSI_SRC: 803 sc16is7xx_update_mlines(one); 804 break; 805 case SC16IS7XX_IIR_THRI_SRC: 806 sc16is7xx_handle_tx(port); 807 break; 808 default: 809 dev_err_ratelimited(port->dev, 810 "ttySC%i: Unexpected interrupt: %x", 811 port->line, iir); 812 break; 813 } 814 815 return true; 816 } 817 818 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) 819 { 820 struct sc16is7xx_port *s = dev_id; 821 bool keep_polling; 822 823 do { 824 int i; 825 826 keep_polling = false; 827 828 for (i = 0; i < s->devtype->nr_uart; ++i) 829 keep_polling |= sc16is7xx_port_irq(s, i); 830 } while (keep_polling); 831 832 return IRQ_HANDLED; 833 } 834 835 static void sc16is7xx_poll_proc(struct kthread_work *ws) 836 { 837 struct sc16is7xx_port *s = container_of(ws, struct sc16is7xx_port, poll_work.work); 838 839 /* Reuse standard IRQ handler. Interrupt ID is unused in this context. */ 840 sc16is7xx_irq(0, s); 841 842 /* Setup delay based on SC16IS7XX_POLL_PERIOD_MS */ 843 kthread_queue_delayed_work(&s->kworker, &s->poll_work, 844 msecs_to_jiffies(SC16IS7XX_POLL_PERIOD_MS)); 845 } 846 847 static void sc16is7xx_tx_proc(struct kthread_work *ws) 848 { 849 struct sc16is7xx_one *one = container_of(ws, struct sc16is7xx_one, tx_work); 850 struct uart_port *port = &one->port; 851 852 if ((port->rs485.flags & SER_RS485_ENABLED) && 853 (port->rs485.delay_rts_before_send > 0)) 854 msleep(port->rs485.delay_rts_before_send); 855 856 guard(mutex)(&one->lock); 857 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 858 SC16IS7XX_IER_THRI_BIT, 859 SC16IS7XX_IER_THRI_BIT); 860 sc16is7xx_handle_tx(port); 861 } 862 863 static void sc16is7xx_reconf_rs485(struct uart_port *port) 864 { 865 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | 866 SC16IS7XX_EFCR_RTS_INVERT_BIT; 867 u32 efcr = 0; 868 struct serial_rs485 *rs485 = &port->rs485; 869 unsigned long irqflags; 870 871 uart_port_lock_irqsave(port, &irqflags); 872 if (rs485->flags & SER_RS485_ENABLED) { 873 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; 874 875 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 876 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; 877 } 878 uart_port_unlock_irqrestore(port, irqflags); 879 880 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); 881 } 882 883 static void sc16is7xx_reg_proc(struct kthread_work *ws) 884 { 885 struct sc16is7xx_one *one = container_of(ws, struct sc16is7xx_one, reg_work); 886 struct sc16is7xx_one_config config; 887 unsigned long irqflags; 888 889 uart_port_lock_irqsave(&one->port, &irqflags); 890 config = one->config; 891 memset(&one->config, 0, sizeof(one->config)); 892 uart_port_unlock_irqrestore(&one->port, irqflags); 893 894 if (config.flags & SC16IS7XX_RECONF_MD) { 895 u8 mcr = 0; 896 897 /* Device ignores RTS setting when hardware flow is enabled */ 898 if (one->port.mctrl & TIOCM_RTS) 899 mcr |= SC16IS7XX_MCR_RTS_BIT; 900 901 if (one->port.mctrl & TIOCM_DTR) 902 mcr |= SC16IS7XX_MCR_DTR_BIT; 903 904 if (one->port.mctrl & TIOCM_LOOP) 905 mcr |= SC16IS7XX_MCR_LOOP_BIT; 906 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 907 SC16IS7XX_MCR_RTS_BIT | 908 SC16IS7XX_MCR_DTR_BIT | 909 SC16IS7XX_MCR_LOOP_BIT, 910 mcr); 911 } 912 913 if (config.flags & SC16IS7XX_RECONF_IER) 914 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG, 915 config.ier_mask, config.ier_val); 916 917 if (config.flags & SC16IS7XX_RECONF_RS485) 918 sc16is7xx_reconf_rs485(&one->port); 919 } 920 921 static void sc16is7xx_ms_proc(struct kthread_work *ws) 922 { 923 struct sc16is7xx_one *one = container_of(ws, struct sc16is7xx_one, ms_work.work); 924 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev); 925 926 if (one->port.state) { 927 scoped_guard(mutex, &one->lock) 928 sc16is7xx_update_mlines(one); 929 930 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ); 931 } 932 } 933 934 static void sc16is7xx_enable_ms(struct uart_port *port) 935 { 936 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 937 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 938 939 lockdep_assert_held_once(&port->lock); 940 941 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0); 942 } 943 944 static void sc16is7xx_start_tx(struct uart_port *port) 945 { 946 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 947 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 948 949 kthread_queue_work(&s->kworker, &one->tx_work); 950 } 951 952 static void sc16is7xx_throttle(struct uart_port *port) 953 { 954 unsigned long flags; 955 956 /* 957 * Hardware flow control is enabled and thus the device ignores RTS 958 * value set in MCR register. Stop reading data from RX FIFO so the 959 * AutoRTS feature will de-activate RTS output. 960 */ 961 uart_port_lock_irqsave(port, &flags); 962 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 963 uart_port_unlock_irqrestore(port, flags); 964 } 965 966 static void sc16is7xx_unthrottle(struct uart_port *port) 967 { 968 unsigned long flags; 969 970 uart_port_lock_irqsave(port, &flags); 971 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT); 972 uart_port_unlock_irqrestore(port, flags); 973 } 974 975 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) 976 { 977 unsigned int lsr; 978 979 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 980 981 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0; 982 } 983 984 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) 985 { 986 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 987 988 /* Called with port lock taken so we can only return cached value */ 989 return one->old_mctrl; 990 } 991 992 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) 993 { 994 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 995 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 996 997 one->config.flags |= SC16IS7XX_RECONF_MD; 998 kthread_queue_work(&s->kworker, &one->reg_work); 999 } 1000 1001 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) 1002 { 1003 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, 1004 SC16IS7XX_LCR_TXBREAK_BIT, 1005 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); 1006 } 1007 1008 static void sc16is7xx_set_termios(struct uart_port *port, 1009 struct ktermios *termios, 1010 const struct ktermios *old) 1011 { 1012 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 1013 unsigned int lcr, flow = 0; 1014 int baud; 1015 unsigned long flags; 1016 1017 kthread_cancel_delayed_work_sync(&one->ms_work); 1018 1019 /* Mask termios capabilities we don't support */ 1020 termios->c_cflag &= ~CMSPAR; 1021 1022 /* Word size */ 1023 switch (termios->c_cflag & CSIZE) { 1024 case CS5: 1025 lcr = SC16IS7XX_LCR_WORD_LEN_5; 1026 break; 1027 case CS6: 1028 lcr = SC16IS7XX_LCR_WORD_LEN_6; 1029 break; 1030 case CS7: 1031 lcr = SC16IS7XX_LCR_WORD_LEN_7; 1032 break; 1033 case CS8: 1034 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1035 break; 1036 default: 1037 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1038 termios->c_cflag &= ~CSIZE; 1039 termios->c_cflag |= CS8; 1040 break; 1041 } 1042 1043 /* Parity */ 1044 if (termios->c_cflag & PARENB) { 1045 lcr |= SC16IS7XX_LCR_PARITY_BIT; 1046 if (!(termios->c_cflag & PARODD)) 1047 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; 1048 } 1049 1050 /* Stop bits */ 1051 if (termios->c_cflag & CSTOPB) 1052 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ 1053 1054 /* Set read status mask */ 1055 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; 1056 if (termios->c_iflag & INPCK) 1057 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | 1058 SC16IS7XX_LSR_FE_BIT; 1059 if (termios->c_iflag & (BRKINT | PARMRK)) 1060 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; 1061 1062 /* Set status ignore mask */ 1063 port->ignore_status_mask = 0; 1064 if (termios->c_iflag & IGNBRK) 1065 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; 1066 if (!(termios->c_cflag & CREAD)) 1067 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; 1068 1069 /* Configure flow control */ 1070 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1071 if (termios->c_cflag & CRTSCTS) { 1072 flow |= SC16IS7XX_EFR_AUTOCTS_BIT | 1073 SC16IS7XX_EFR_AUTORTS_BIT; 1074 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1075 } 1076 if (termios->c_iflag & IXON) 1077 flow |= SC16IS7XX_EFR_SWFLOW3_BIT; 1078 if (termios->c_iflag & IXOFF) 1079 flow |= SC16IS7XX_EFR_SWFLOW1_BIT; 1080 1081 /* Update LCR register */ 1082 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 1083 1084 /* Update EFR registers */ 1085 sc16is7xx_regs_lock(port, SC16IS7XX_LCR_REG_SET_ENHANCED); 1086 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); 1087 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); 1088 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 1089 SC16IS7XX_EFR_FLOWCTRL_BITS, flow); 1090 sc16is7xx_regs_unlock(port); 1091 1092 /* Get baud rate generator configuration */ 1093 baud = uart_get_baud_rate(port, termios, old, 1094 port->uartclk / 16 / 4 / 0xffff, 1095 port->uartclk / 16); 1096 1097 /* Setup baudrate generator */ 1098 baud = sc16is7xx_set_baud(port, baud); 1099 1100 uart_port_lock_irqsave(port, &flags); 1101 1102 /* Update timeout according to new baud rate */ 1103 uart_update_timeout(port, termios->c_cflag, baud); 1104 1105 if (UART_ENABLE_MS(port, termios->c_cflag)) 1106 sc16is7xx_enable_ms(port); 1107 1108 uart_port_unlock_irqrestore(port, flags); 1109 } 1110 1111 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios, 1112 struct serial_rs485 *rs485) 1113 { 1114 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1115 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 1116 1117 if (rs485->flags & SER_RS485_ENABLED) { 1118 /* 1119 * RTS signal is handled by HW, it's timing can't be influenced. 1120 * However, it's sometimes useful to delay TX even without RTS 1121 * control therefore we try to handle .delay_rts_before_send. 1122 */ 1123 if (rs485->delay_rts_after_send) 1124 return -EINVAL; 1125 } 1126 1127 one->config.flags |= SC16IS7XX_RECONF_RS485; 1128 kthread_queue_work(&s->kworker, &one->reg_work); 1129 1130 return 0; 1131 } 1132 1133 static int sc16is7xx_startup(struct uart_port *port) 1134 { 1135 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 1136 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1137 unsigned int val; 1138 unsigned long flags; 1139 1140 sc16is7xx_power(port, 1); 1141 1142 /* Reset FIFOs */ 1143 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 1144 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 1145 udelay(5); 1146 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, 1147 SC16IS7XX_FCR_FIFO_BIT); 1148 1149 /* Enable TCR/TLR */ 1150 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1151 SC16IS7XX_MCR_TCRTLR_BIT, 1152 SC16IS7XX_MCR_TCRTLR_BIT); 1153 1154 /* Configure flow control levels */ 1155 /* Flow control halt level 48, resume level 24 */ 1156 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, 1157 SC16IS7XX_TCR_RX_RESUME(24) | 1158 SC16IS7XX_TCR_RX_HALT(48)); 1159 1160 /* Sync hardware and software TX trigger levels */ 1161 sc16is7xx_port_write(port, SC16IS7XX_TLR_REG, 1162 SC16IS7XX_TLR_TX_TRIGGER(SC16IS7XX_TX_TRIGGER_LEVEL)); 1163 1164 /* Disable TCR/TLR access */ 1165 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, SC16IS7XX_MCR_TCRTLR_BIT, 0); 1166 1167 /* Now, initialize the UART */ 1168 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); 1169 1170 /* Enable IrDA mode if requested in DT */ 1171 /* This bit must be written with LCR[7] = 0 */ 1172 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1173 SC16IS7XX_MCR_IRDA_BIT, 1174 one->irda_mode ? SC16IS7XX_MCR_IRDA_BIT : 0); 1175 1176 /* Enable the Rx and Tx FIFO */ 1177 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1178 SC16IS7XX_EFCR_RXDISABLE_BIT | 1179 SC16IS7XX_EFCR_TXDISABLE_BIT, 1180 0); 1181 1182 /* Enable RX, CTS change and modem lines interrupts */ 1183 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT | 1184 SC16IS7XX_IER_MSI_BIT; 1185 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 1186 1187 /* Enable modem status polling */ 1188 uart_port_lock_irqsave(port, &flags); 1189 sc16is7xx_enable_ms(port); 1190 uart_port_unlock_irqrestore(port, flags); 1191 1192 if (s->polling) 1193 kthread_queue_delayed_work(&s->kworker, &s->poll_work, 1194 msecs_to_jiffies(SC16IS7XX_POLL_PERIOD_MS)); 1195 1196 return 0; 1197 } 1198 1199 static void sc16is7xx_shutdown(struct uart_port *port) 1200 { 1201 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1202 struct sc16is7xx_one *one = to_sc16is7xx_one(port); 1203 1204 kthread_cancel_delayed_work_sync(&one->ms_work); 1205 1206 /* Disable all interrupts */ 1207 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 1208 /* Disable TX/RX */ 1209 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1210 SC16IS7XX_EFCR_RXDISABLE_BIT | 1211 SC16IS7XX_EFCR_TXDISABLE_BIT, 1212 SC16IS7XX_EFCR_RXDISABLE_BIT | 1213 SC16IS7XX_EFCR_TXDISABLE_BIT); 1214 1215 sc16is7xx_power(port, 0); 1216 1217 if (s->polling) 1218 kthread_cancel_delayed_work_sync(&s->poll_work); 1219 1220 kthread_flush_worker(&s->kworker); 1221 } 1222 1223 static const char *sc16is7xx_type(struct uart_port *port) 1224 { 1225 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1226 1227 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; 1228 } 1229 1230 static int sc16is7xx_request_port(struct uart_port *port) 1231 { 1232 /* Do nothing */ 1233 return 0; 1234 } 1235 1236 static void sc16is7xx_config_port(struct uart_port *port, int flags) 1237 { 1238 if (flags & UART_CONFIG_TYPE) 1239 port->type = PORT_SC16IS7XX; 1240 } 1241 1242 static int sc16is7xx_verify_port(struct uart_port *port, 1243 struct serial_struct *s) 1244 { 1245 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) 1246 return -EINVAL; 1247 if (s->irq != port->irq) 1248 return -EINVAL; 1249 1250 return 0; 1251 } 1252 1253 static void sc16is7xx_pm(struct uart_port *port, unsigned int state, 1254 unsigned int oldstate) 1255 { 1256 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); 1257 } 1258 1259 static void sc16is7xx_null_void(struct uart_port *port) 1260 { 1261 /* Do nothing */ 1262 } 1263 1264 static const struct uart_ops sc16is7xx_ops = { 1265 .tx_empty = sc16is7xx_tx_empty, 1266 .set_mctrl = sc16is7xx_set_mctrl, 1267 .get_mctrl = sc16is7xx_get_mctrl, 1268 .stop_tx = sc16is7xx_stop_tx, 1269 .start_tx = sc16is7xx_start_tx, 1270 .throttle = sc16is7xx_throttle, 1271 .unthrottle = sc16is7xx_unthrottle, 1272 .stop_rx = sc16is7xx_stop_rx, 1273 .enable_ms = sc16is7xx_enable_ms, 1274 .break_ctl = sc16is7xx_break_ctl, 1275 .startup = sc16is7xx_startup, 1276 .shutdown = sc16is7xx_shutdown, 1277 .set_termios = sc16is7xx_set_termios, 1278 .type = sc16is7xx_type, 1279 .request_port = sc16is7xx_request_port, 1280 .release_port = sc16is7xx_null_void, 1281 .config_port = sc16is7xx_config_port, 1282 .verify_port = sc16is7xx_verify_port, 1283 .pm = sc16is7xx_pm, 1284 }; 1285 1286 #ifdef CONFIG_GPIOLIB 1287 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) 1288 { 1289 unsigned int val; 1290 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1291 struct uart_port *port = &s->p[0].port; 1292 1293 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1294 1295 return !!(val & BIT(offset)); 1296 } 1297 1298 static int sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned int offset, 1299 int val) 1300 { 1301 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1302 struct uart_port *port = &s->p[0].port; 1303 1304 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1305 val ? BIT(offset) : 0); 1306 1307 return 0; 1308 } 1309 1310 static int sc16is7xx_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1311 { 1312 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1313 struct uart_port *port = &s->p[0].port; 1314 unsigned int val; 1315 1316 val = sc16is7xx_port_read(port, SC16IS7XX_IODIR_REG); 1317 1318 return val & BIT(offset) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1319 } 1320 1321 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, 1322 unsigned offset) 1323 { 1324 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1325 struct uart_port *port = &s->p[0].port; 1326 1327 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); 1328 1329 return 0; 1330 } 1331 1332 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, 1333 unsigned offset, int val) 1334 { 1335 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1336 struct uart_port *port = &s->p[0].port; 1337 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1338 1339 if (val) 1340 state |= BIT(offset); 1341 else 1342 state &= ~BIT(offset); 1343 1344 /* 1345 * If we write IOSTATE first, and then IODIR, the output value is not 1346 * transferred to the corresponding I/O pin. 1347 * The datasheet states that each register bit will be transferred to 1348 * the corresponding I/O pin programmed as output when writing to 1349 * IOSTATE. Therefore, configure direction first with IODIR, and then 1350 * set value after with IOSTATE. 1351 */ 1352 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1353 BIT(offset)); 1354 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); 1355 1356 return 0; 1357 } 1358 1359 static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip, 1360 unsigned long *valid_mask, 1361 unsigned int ngpios) 1362 { 1363 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1364 1365 *valid_mask = s->gpio_valid_mask; 1366 1367 return 0; 1368 } 1369 1370 static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s) 1371 { 1372 struct device *dev = s->p[0].port.dev; 1373 1374 if (!s->devtype->nr_gpio) 1375 return 0; 1376 1377 switch (s->mctrl_mask) { 1378 case 0: 1379 s->gpio_valid_mask = GENMASK(7, 0); 1380 break; 1381 case SC16IS7XX_IOCONTROL_MODEM_A_BIT: 1382 s->gpio_valid_mask = GENMASK(3, 0); 1383 break; 1384 case SC16IS7XX_IOCONTROL_MODEM_B_BIT: 1385 s->gpio_valid_mask = GENMASK(7, 4); 1386 break; 1387 default: 1388 break; 1389 } 1390 1391 if (s->gpio_valid_mask == 0) 1392 return 0; 1393 1394 s->gpio.owner = THIS_MODULE; 1395 s->gpio.parent = dev; 1396 s->gpio.label = dev_name(dev); 1397 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask; 1398 s->gpio.get_direction = sc16is7xx_gpio_get_direction; 1399 s->gpio.direction_input = sc16is7xx_gpio_direction_input; 1400 s->gpio.get = sc16is7xx_gpio_get; 1401 s->gpio.direction_output = sc16is7xx_gpio_direction_output; 1402 s->gpio.set = sc16is7xx_gpio_set; 1403 s->gpio.base = -1; 1404 s->gpio.ngpio = s->devtype->nr_gpio; 1405 s->gpio.can_sleep = 1; 1406 1407 return gpiochip_add_data(&s->gpio, s); 1408 } 1409 #endif 1410 1411 static void sc16is7xx_setup_irda_ports(struct sc16is7xx_port *s) 1412 { 1413 int i; 1414 int ret; 1415 int count; 1416 u32 irda_port[SC16IS7XX_MAX_PORTS]; 1417 struct device *dev = s->p[0].port.dev; 1418 1419 count = device_property_count_u32(dev, "irda-mode-ports"); 1420 if (count < 0 || count > ARRAY_SIZE(irda_port)) 1421 return; 1422 1423 ret = device_property_read_u32_array(dev, "irda-mode-ports", 1424 irda_port, count); 1425 if (ret) 1426 return; 1427 1428 for (i = 0; i < count; i++) { 1429 if (irda_port[i] < s->devtype->nr_uart) 1430 s->p[irda_port[i]].irda_mode = true; 1431 } 1432 } 1433 1434 /* 1435 * Configure ports designated to operate as modem control lines. 1436 */ 1437 static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s, 1438 struct regmap *regmap) 1439 { 1440 int i; 1441 int ret; 1442 int count; 1443 u32 mctrl_port[SC16IS7XX_MAX_PORTS]; 1444 struct device *dev = s->p[0].port.dev; 1445 1446 count = device_property_count_u32(dev, "nxp,modem-control-line-ports"); 1447 if (count < 0 || count > ARRAY_SIZE(mctrl_port)) 1448 return 0; 1449 1450 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports", 1451 mctrl_port, count); 1452 if (ret) 1453 return ret; 1454 1455 s->mctrl_mask = 0; 1456 1457 for (i = 0; i < count; i++) { 1458 /* Use GPIO lines as modem control lines */ 1459 if (mctrl_port[i] == 0) 1460 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT; 1461 else if (mctrl_port[i] == 1) 1462 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT; 1463 } 1464 1465 if (s->mctrl_mask) 1466 regmap_update_bits( 1467 regmap, 1468 SC16IS7XX_IOCONTROL_REG, 1469 SC16IS7XX_IOCONTROL_MODEM_A_BIT | 1470 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask); 1471 1472 return 0; 1473 } 1474 1475 static const struct serial_rs485 sc16is7xx_rs485_supported = { 1476 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND, 1477 .delay_rts_before_send = 1, 1478 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */ 1479 }; 1480 1481 /* Reset device, purging any pending irq / data */ 1482 static int sc16is7xx_reset(struct device *dev, struct regmap *regmap) 1483 { 1484 struct gpio_desc *reset_gpio; 1485 1486 /* Assert reset GPIO if defined and valid. */ 1487 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1488 if (IS_ERR(reset_gpio)) 1489 return dev_err_probe(dev, PTR_ERR(reset_gpio), "Failed to get reset GPIO\n"); 1490 1491 if (reset_gpio) { 1492 /* The minimum reset pulse width is 3 us. */ 1493 fsleep(5); 1494 gpiod_set_value_cansleep(reset_gpio, 0); /* Deassert GPIO */ 1495 } else { 1496 /* Software reset */ 1497 regmap_write(regmap, SC16IS7XX_IOCONTROL_REG, 1498 SC16IS7XX_IOCONTROL_SRESET_BIT); 1499 } 1500 1501 return 0; 1502 } 1503 1504 static int sc16is7xx_setup_channel(struct sc16is7xx_one *one, int i, 1505 bool *port_registered) 1506 { 1507 struct uart_port *port = &one->port; 1508 int ret; 1509 1510 ret = ida_alloc_max(&sc16is7xx_lines, SC16IS7XX_MAX_DEVS - 1, GFP_KERNEL); 1511 if (ret < 0) 1512 return ret; 1513 1514 port->line = ret; 1515 1516 /* Initialize port data */ 1517 port->type = PORT_SC16IS7XX; 1518 port->fifosize = SC16IS7XX_FIFO_SIZE; 1519 port->flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1520 port->iotype = UPIO_BUS; 1521 port->rs485_config = sc16is7xx_config_rs485; 1522 port->rs485_supported = sc16is7xx_rs485_supported; 1523 port->ops = &sc16is7xx_ops; 1524 one->old_mctrl = 0; 1525 1526 mutex_init(&one->lock); 1527 1528 ret = uart_get_rs485_mode(port); 1529 if (ret) 1530 return ret; 1531 1532 /* Enable access to general register set */ 1533 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 0x00); 1534 1535 /* Disable all interrupts */ 1536 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 1537 /* Disable TX/RX */ 1538 sc16is7xx_port_write(port, SC16IS7XX_EFCR_REG, 1539 SC16IS7XX_EFCR_RXDISABLE_BIT | 1540 SC16IS7XX_EFCR_TXDISABLE_BIT); 1541 1542 /* Initialize kthread work structs */ 1543 kthread_init_work(&one->tx_work, sc16is7xx_tx_proc); 1544 kthread_init_work(&one->reg_work, sc16is7xx_reg_proc); 1545 kthread_init_delayed_work(&one->ms_work, sc16is7xx_ms_proc); 1546 1547 /* Register port */ 1548 ret = uart_add_one_port(&sc16is7xx_uart, port); 1549 if (ret) 1550 return ret; 1551 1552 *port_registered = true; 1553 1554 sc16is7xx_regs_lock(port, SC16IS7XX_LCR_REG_SET_ENHANCED); 1555 /* Enable write access to enhanced features */ 1556 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, 1557 SC16IS7XX_EFR_ENABLE_BIT); 1558 sc16is7xx_regs_unlock(port); 1559 1560 /* Go to suspend mode */ 1561 sc16is7xx_power(port, 0); 1562 1563 return 0; 1564 } 1565 1566 int sc16is7xx_probe(struct device *dev, const struct sc16is7xx_devtype *devtype, 1567 struct regmap *regmaps[], int irq) 1568 { 1569 unsigned long freq = 0, *pfreq = dev_get_platdata(dev); 1570 unsigned int val; 1571 u32 uartclk = 0; 1572 int i, ret; 1573 struct sc16is7xx_port *s; 1574 bool port_registered[SC16IS7XX_MAX_PORTS]; 1575 1576 for (i = 0; i < devtype->nr_uart; i++) 1577 if (IS_ERR(regmaps[i])) 1578 return PTR_ERR(regmaps[i]); 1579 1580 /* 1581 * This device does not have an identification register that would 1582 * tell us if we are really connected to the correct device. 1583 * The best we can do is to check if communication is at all possible. 1584 * 1585 * Note: regmap[0] is used in the probe function to access registers 1586 * common to all channels/ports, as it is guaranteed to be present on 1587 * all variants. 1588 */ 1589 ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val); 1590 if (ret < 0) 1591 return -EPROBE_DEFER; 1592 1593 /* Alloc port structure */ 1594 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL); 1595 if (!s) 1596 return -ENOMEM; 1597 1598 /* Always ask for fixed clock rate from a property. */ 1599 device_property_read_u32(dev, "clock-frequency", &uartclk); 1600 1601 s->polling = (irq <= 0); 1602 if (s->polling) 1603 dev_dbg(dev, 1604 "No interrupt pin definition, falling back to polling mode\n"); 1605 1606 s->clk = devm_clk_get_optional(dev, NULL); 1607 if (IS_ERR(s->clk)) 1608 return PTR_ERR(s->clk); 1609 1610 ret = clk_prepare_enable(s->clk); 1611 if (ret) 1612 return ret; 1613 1614 freq = clk_get_rate(s->clk); 1615 if (freq == 0) { 1616 if (uartclk) 1617 freq = uartclk; 1618 if (pfreq) 1619 freq = *pfreq; 1620 if (freq) 1621 dev_dbg(dev, "Clock frequency: %luHz\n", freq); 1622 else 1623 return -EINVAL; 1624 } 1625 1626 s->devtype = devtype; 1627 dev_set_drvdata(dev, s); 1628 1629 kthread_init_worker(&s->kworker); 1630 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, 1631 "sc16is7xx"); 1632 if (IS_ERR(s->kworker_task)) { 1633 ret = PTR_ERR(s->kworker_task); 1634 goto out_clk; 1635 } 1636 sched_set_fifo(s->kworker_task); 1637 1638 ret = sc16is7xx_reset(dev, regmaps[0]); 1639 if (ret) 1640 goto out_kthread; 1641 1642 /* Mark each port line and status as uninitialised. */ 1643 for (i = 0; i < devtype->nr_uart; ++i) { 1644 s->p[i].port.line = SC16IS7XX_MAX_DEVS; 1645 port_registered[i] = false; 1646 } 1647 1648 for (i = 0; i < devtype->nr_uart; ++i) { 1649 s->p[i].port.dev = dev; 1650 s->p[i].port.irq = irq; 1651 s->p[i].port.uartclk = freq; 1652 s->p[i].regmap = regmaps[i]; 1653 1654 ret = sc16is7xx_setup_channel(&s->p[i], i, &port_registered[i]); 1655 if (ret) 1656 goto out_ports; 1657 } 1658 1659 sc16is7xx_setup_irda_ports(s); 1660 1661 ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]); 1662 if (ret) 1663 goto out_ports; 1664 1665 #ifdef CONFIG_GPIOLIB 1666 ret = sc16is7xx_setup_gpio_chip(s); 1667 if (ret) 1668 goto out_ports; 1669 #endif 1670 1671 if (s->polling) { 1672 /* Initialize kernel thread for polling */ 1673 kthread_init_delayed_work(&s->poll_work, sc16is7xx_poll_proc); 1674 return 0; 1675 } 1676 1677 /* 1678 * Setup interrupt. We first try to acquire the IRQ line as level IRQ. 1679 * If that succeeds, we can allow sharing the interrupt as well. 1680 * In case the interrupt controller doesn't support that, we fall 1681 * back to a non-shared falling-edge trigger. 1682 */ 1683 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1684 IRQF_TRIGGER_LOW | IRQF_SHARED | 1685 IRQF_ONESHOT, 1686 dev_name(dev), s); 1687 if (!ret) 1688 return 0; 1689 1690 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1691 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1692 dev_name(dev), s); 1693 if (!ret) 1694 return 0; 1695 1696 #ifdef CONFIG_GPIOLIB 1697 if (s->gpio_valid_mask) 1698 gpiochip_remove(&s->gpio); 1699 #endif 1700 1701 out_ports: 1702 for (i = 0; i < devtype->nr_uart; i++) { 1703 if (s->p[i].port.line < SC16IS7XX_MAX_DEVS) 1704 ida_free(&sc16is7xx_lines, s->p[i].port.line); 1705 if (port_registered[i]) 1706 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1707 } 1708 1709 out_kthread: 1710 kthread_stop(s->kworker_task); 1711 1712 out_clk: 1713 clk_disable_unprepare(s->clk); 1714 1715 return ret; 1716 } 1717 EXPORT_SYMBOL_GPL(sc16is7xx_probe); 1718 1719 void sc16is7xx_remove(struct device *dev) 1720 { 1721 struct sc16is7xx_port *s = dev_get_drvdata(dev); 1722 int i; 1723 1724 #ifdef CONFIG_GPIOLIB 1725 if (s->gpio_valid_mask) 1726 gpiochip_remove(&s->gpio); 1727 #endif 1728 1729 for (i = 0; i < s->devtype->nr_uart; i++) { 1730 kthread_cancel_delayed_work_sync(&s->p[i].ms_work); 1731 ida_free(&sc16is7xx_lines, s->p[i].port.line); 1732 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1733 sc16is7xx_power(&s->p[i].port, 0); 1734 } 1735 1736 if (s->polling) 1737 kthread_cancel_delayed_work_sync(&s->poll_work); 1738 1739 kthread_flush_worker(&s->kworker); 1740 kthread_stop(s->kworker_task); 1741 1742 clk_disable_unprepare(s->clk); 1743 } 1744 EXPORT_SYMBOL_GPL(sc16is7xx_remove); 1745 1746 const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { 1747 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, }, 1748 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, }, 1749 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, }, 1750 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, }, 1751 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, }, 1752 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, }, 1753 { } 1754 }; 1755 EXPORT_SYMBOL_GPL(sc16is7xx_dt_ids); 1756 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); 1757 1758 const struct regmap_config sc16is7xx_regcfg = { 1759 .reg_bits = 5, 1760 .pad_bits = 3, 1761 .val_bits = 8, 1762 .cache_type = REGCACHE_MAPLE, 1763 .volatile_reg = sc16is7xx_regmap_volatile, 1764 .precious_reg = sc16is7xx_regmap_precious, 1765 .writeable_noinc_reg = sc16is7xx_regmap_noinc, 1766 .readable_noinc_reg = sc16is7xx_regmap_noinc, 1767 .max_raw_read = SC16IS7XX_FIFO_SIZE, 1768 .max_raw_write = SC16IS7XX_FIFO_SIZE, 1769 .max_register = SC16IS7XX_EFCR_REG, 1770 }; 1771 EXPORT_SYMBOL_GPL(sc16is7xx_regcfg); 1772 1773 const char *sc16is7xx_regmap_name(u8 port_id) 1774 { 1775 switch (port_id) { 1776 case 0: return "port0"; 1777 case 1: return "port1"; 1778 default: 1779 WARN_ON(true); 1780 return NULL; 1781 } 1782 } 1783 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_name); 1784 1785 unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id) 1786 { 1787 /* CH1,CH0 are at bits 2:1. */ 1788 return port_id << 1; 1789 } 1790 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_port_mask); 1791 1792 static int __init sc16is7xx_init(void) 1793 { 1794 return uart_register_driver(&sc16is7xx_uart); 1795 } 1796 module_init(sc16is7xx_init); 1797 1798 static void __exit sc16is7xx_exit(void) 1799 { 1800 uart_unregister_driver(&sc16is7xx_uart); 1801 } 1802 module_exit(sc16is7xx_exit); 1803 1804 MODULE_LICENSE("GPL"); 1805 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1806 MODULE_DESCRIPTION(KBUILD_MODNAME " tty serial core driver"); 1807