1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2 /* 3 * Copyright 2018-2026 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 6 #include <linux/crc16.h> 7 #include <linux/log2.h> 8 9 #include "efa_com.h" 10 #include "efa_regs_defs.h" 11 12 #define ADMIN_CMD_TIMEOUT_US 30000000 /* usecs */ 13 14 #define EFA_REG_READ_TIMEOUT_US 50000 /* usecs */ 15 #define EFA_MMIO_READ_INVALID 0xffffffff 16 17 #define EFA_POLL_INTERVAL_MS 100 /* msecs */ 18 19 #define EFA_ASYNC_QUEUE_DEPTH 16 20 #define EFA_ADMIN_QUEUE_DEPTH 32 21 22 #define EFA_CTRL_MAJOR 0 23 #define EFA_CTRL_MINOR 0 24 #define EFA_CTRL_SUB_MINOR 1 25 26 #define EFA_CRC16_INIT_VAL 0xffff 27 28 #define EFA_CRC_MIN_ADMIN_API_VERSION_MAJOR 0 29 #define EFA_CRC_MIN_ADMIN_API_VERSION_MINOR 2 30 31 #define EFA_MIN_ADMIN_API_VERSION_MAJOR 0 32 #define EFA_MIN_ADMIN_API_VERSION_MINOR 1 33 34 enum efa_cmd_status { 35 EFA_CMD_UNUSED, 36 EFA_CMD_ALLOCATED, 37 EFA_CMD_SUBMITTED, 38 EFA_CMD_COMPLETED, 39 }; 40 41 struct efa_comp_ctx { 42 struct completion wait_event; 43 struct efa_admin_acq_entry *user_cqe; 44 u32 comp_size; 45 enum efa_cmd_status status; 46 u16 cmd_id; 47 u8 cmd_opcode; 48 }; 49 50 static const char *efa_com_cmd_str(u8 cmd) 51 { 52 #define EFA_CMD_STR_CASE(_cmd) case EFA_ADMIN_##_cmd: return #_cmd 53 54 switch (cmd) { 55 EFA_CMD_STR_CASE(CREATE_QP); 56 EFA_CMD_STR_CASE(MODIFY_QP); 57 EFA_CMD_STR_CASE(QUERY_QP); 58 EFA_CMD_STR_CASE(DESTROY_QP); 59 EFA_CMD_STR_CASE(CREATE_AH); 60 EFA_CMD_STR_CASE(DESTROY_AH); 61 EFA_CMD_STR_CASE(REG_MR); 62 EFA_CMD_STR_CASE(DEREG_MR); 63 EFA_CMD_STR_CASE(CREATE_CQ); 64 EFA_CMD_STR_CASE(DESTROY_CQ); 65 EFA_CMD_STR_CASE(GET_FEATURE); 66 EFA_CMD_STR_CASE(SET_FEATURE); 67 EFA_CMD_STR_CASE(GET_STATS); 68 EFA_CMD_STR_CASE(ALLOC_PD); 69 EFA_CMD_STR_CASE(DEALLOC_PD); 70 EFA_CMD_STR_CASE(ALLOC_UAR); 71 EFA_CMD_STR_CASE(DEALLOC_UAR); 72 EFA_CMD_STR_CASE(CREATE_EQ); 73 EFA_CMD_STR_CASE(DESTROY_EQ); 74 default: return "unknown command opcode"; 75 } 76 #undef EFA_CMD_STR_CASE 77 } 78 79 void efa_com_set_dma_addr(dma_addr_t addr, u32 *addr_high, u32 *addr_low) 80 { 81 *addr_low = lower_32_bits(addr); 82 *addr_high = upper_32_bits(addr); 83 } 84 85 static u32 efa_com_reg_read32(struct efa_com_dev *edev, u16 offset) 86 { 87 struct efa_com_mmio_read *mmio_read = &edev->mmio_read; 88 struct efa_admin_mmio_req_read_less_resp *read_resp; 89 unsigned long exp_time; 90 u32 mmio_read_reg = 0; 91 u32 err; 92 93 read_resp = mmio_read->read_resp; 94 95 spin_lock(&mmio_read->lock); 96 mmio_read->seq_num++; 97 98 /* trash DMA req_id to identify when hardware is done */ 99 read_resp->req_id = mmio_read->seq_num + 0x9aL; 100 EFA_SET(&mmio_read_reg, EFA_REGS_MMIO_REG_READ_REG_OFF, offset); 101 EFA_SET(&mmio_read_reg, EFA_REGS_MMIO_REG_READ_REQ_ID, 102 mmio_read->seq_num); 103 104 writel(mmio_read_reg, edev->reg_bar + EFA_REGS_MMIO_REG_READ_OFF); 105 106 exp_time = jiffies + usecs_to_jiffies(mmio_read->mmio_read_timeout); 107 do { 108 if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num) 109 break; 110 udelay(1); 111 } while (time_is_after_jiffies(exp_time)); 112 113 if (read_resp->req_id != mmio_read->seq_num) { 114 ibdev_err_ratelimited( 115 edev->efa_dev, 116 "Reading register timed out. expected: req id[%u] offset[%#x] actual: req id[%u] offset[%#x]\n", 117 mmio_read->seq_num, offset, read_resp->req_id, 118 read_resp->reg_off); 119 err = EFA_MMIO_READ_INVALID; 120 goto out; 121 } 122 123 if (read_resp->reg_off != offset) { 124 ibdev_err_ratelimited( 125 edev->efa_dev, 126 "Reading register failed: wrong offset provided\n"); 127 err = EFA_MMIO_READ_INVALID; 128 goto out; 129 } 130 131 err = read_resp->reg_val; 132 out: 133 spin_unlock(&mmio_read->lock); 134 return err; 135 } 136 137 static int efa_com_admin_init_sq(struct efa_com_dev *edev) 138 { 139 struct efa_com_admin_queue *aq = &edev->aq; 140 struct efa_com_admin_sq *sq = &aq->sq; 141 u16 size = aq->depth * sizeof(*sq->entries); 142 u32 aq_caps = 0; 143 u32 addr_high; 144 u32 addr_low; 145 146 sq->entries = 147 dma_alloc_coherent(aq->dmadev, size, &sq->dma_addr, GFP_KERNEL); 148 if (!sq->entries) 149 return -ENOMEM; 150 151 spin_lock_init(&sq->lock); 152 153 sq->cc = 0; 154 sq->pc = 0; 155 sq->phase = 1; 156 157 sq->db_addr = (u32 __iomem *)(edev->reg_bar + EFA_REGS_AQ_PROD_DB_OFF); 158 159 addr_high = upper_32_bits(sq->dma_addr); 160 addr_low = lower_32_bits(sq->dma_addr); 161 162 writel(addr_low, edev->reg_bar + EFA_REGS_AQ_BASE_LO_OFF); 163 writel(addr_high, edev->reg_bar + EFA_REGS_AQ_BASE_HI_OFF); 164 165 EFA_SET(&aq_caps, EFA_REGS_AQ_CAPS_AQ_DEPTH, aq->depth); 166 EFA_SET(&aq_caps, EFA_REGS_AQ_CAPS_AQ_ENTRY_SIZE, 167 sizeof(struct efa_admin_aq_entry)); 168 169 writel(aq_caps, edev->reg_bar + EFA_REGS_AQ_CAPS_OFF); 170 171 return 0; 172 } 173 174 static int efa_com_admin_init_cq(struct efa_com_dev *edev) 175 { 176 struct efa_com_admin_queue *aq = &edev->aq; 177 struct efa_com_admin_cq *cq = &aq->cq; 178 u16 size = aq->depth * sizeof(*cq->entries); 179 u32 acq_caps = 0, crc_min_ver = 0; 180 u32 addr_high, addr_low; 181 182 cq->entries = 183 dma_alloc_coherent(aq->dmadev, size, &cq->dma_addr, GFP_KERNEL); 184 if (!cq->entries) 185 return -ENOMEM; 186 187 spin_lock_init(&cq->lock); 188 189 EFA_SET(&crc_min_ver, EFA_REGS_VERSION_MAJOR_VERSION, EFA_CRC_MIN_ADMIN_API_VERSION_MAJOR); 190 EFA_SET(&crc_min_ver, EFA_REGS_VERSION_MINOR_VERSION, EFA_CRC_MIN_ADMIN_API_VERSION_MINOR); 191 if (edev->dev_api_ver >= crc_min_ver) 192 cq->validate_checksum = true; 193 194 cq->cc = 0; 195 cq->phase = 1; 196 197 addr_high = upper_32_bits(cq->dma_addr); 198 addr_low = lower_32_bits(cq->dma_addr); 199 200 writel(addr_low, edev->reg_bar + EFA_REGS_ACQ_BASE_LO_OFF); 201 writel(addr_high, edev->reg_bar + EFA_REGS_ACQ_BASE_HI_OFF); 202 203 EFA_SET(&acq_caps, EFA_REGS_ACQ_CAPS_ACQ_DEPTH, aq->depth); 204 EFA_SET(&acq_caps, EFA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE, 205 sizeof(struct efa_admin_acq_entry)); 206 EFA_SET(&acq_caps, EFA_REGS_ACQ_CAPS_ACQ_MSIX_VECTOR, 207 aq->msix_vector_idx); 208 209 writel(acq_caps, edev->reg_bar + EFA_REGS_ACQ_CAPS_OFF); 210 211 return 0; 212 } 213 214 static int efa_com_admin_init_aenq(struct efa_com_dev *edev, 215 struct efa_aenq_handlers *aenq_handlers) 216 { 217 struct efa_com_aenq *aenq = &edev->aenq; 218 u32 addr_low, addr_high; 219 u32 aenq_caps = 0; 220 u16 size; 221 222 if (!aenq_handlers) { 223 ibdev_err(edev->efa_dev, "aenq handlers pointer is NULL\n"); 224 return -EINVAL; 225 } 226 227 size = EFA_ASYNC_QUEUE_DEPTH * sizeof(*aenq->entries); 228 aenq->entries = dma_alloc_coherent(edev->dmadev, size, &aenq->dma_addr, 229 GFP_KERNEL); 230 if (!aenq->entries) 231 return -ENOMEM; 232 233 aenq->aenq_handlers = aenq_handlers; 234 aenq->depth = EFA_ASYNC_QUEUE_DEPTH; 235 aenq->cc = 0; 236 aenq->phase = 1; 237 238 addr_low = lower_32_bits(aenq->dma_addr); 239 addr_high = upper_32_bits(aenq->dma_addr); 240 241 writel(addr_low, edev->reg_bar + EFA_REGS_AENQ_BASE_LO_OFF); 242 writel(addr_high, edev->reg_bar + EFA_REGS_AENQ_BASE_HI_OFF); 243 244 EFA_SET(&aenq_caps, EFA_REGS_AENQ_CAPS_AENQ_DEPTH, aenq->depth); 245 EFA_SET(&aenq_caps, EFA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE, 246 sizeof(struct efa_admin_aenq_entry)); 247 EFA_SET(&aenq_caps, EFA_REGS_AENQ_CAPS_AENQ_MSIX_VECTOR, 248 aenq->msix_vector_idx); 249 writel(aenq_caps, edev->reg_bar + EFA_REGS_AENQ_CAPS_OFF); 250 251 /* 252 * Init cons_db to mark that all entries in the queue 253 * are initially available 254 */ 255 writel(edev->aenq.cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF); 256 257 return 0; 258 } 259 260 static u16 efa_com_alloc_ctx_id(struct efa_com_admin_queue *aq) 261 { 262 u16 ctx_id; 263 264 spin_lock(&aq->comp_ctx_lock); 265 ctx_id = aq->comp_ctx_pool[aq->comp_ctx_pool_next]; 266 aq->comp_ctx_pool_next++; 267 spin_unlock(&aq->comp_ctx_lock); 268 269 return ctx_id; 270 } 271 272 static void efa_com_dealloc_ctx_id(struct efa_com_admin_queue *aq, 273 u16 ctx_id) 274 { 275 spin_lock(&aq->comp_ctx_lock); 276 aq->comp_ctx_pool_next--; 277 aq->comp_ctx_pool[aq->comp_ctx_pool_next] = ctx_id; 278 spin_unlock(&aq->comp_ctx_lock); 279 } 280 281 static struct efa_comp_ctx *efa_com_alloc_comp_ctx(struct efa_com_admin_queue *aq) 282 { 283 struct efa_comp_ctx *comp_ctx; 284 u16 ctx_id; 285 286 ctx_id = efa_com_alloc_ctx_id(aq); 287 288 comp_ctx = &aq->comp_ctx[ctx_id]; 289 if (comp_ctx->status != EFA_CMD_UNUSED) { 290 efa_com_dealloc_ctx_id(aq, ctx_id); 291 ibdev_err_ratelimited(aq->efa_dev, 292 "Completion context[%u] is used[%u]\n", 293 ctx_id, comp_ctx->status); 294 return NULL; 295 } 296 297 comp_ctx->status = EFA_CMD_ALLOCATED; 298 ibdev_dbg(aq->efa_dev, "Take completion context[%u]\n", ctx_id); 299 return comp_ctx; 300 } 301 302 static inline u16 efa_com_get_comp_ctx_id(struct efa_com_admin_queue *aq, 303 struct efa_comp_ctx *comp_ctx) 304 { 305 return comp_ctx - aq->comp_ctx; 306 } 307 308 static inline void efa_com_dealloc_comp_ctx(struct efa_com_admin_queue *aq, 309 struct efa_comp_ctx *comp_ctx) 310 { 311 u16 ctx_id = efa_com_get_comp_ctx_id(aq, comp_ctx); 312 313 ibdev_dbg(aq->efa_dev, "Put completion context[%u]\n", ctx_id); 314 comp_ctx->status = EFA_CMD_UNUSED; 315 efa_com_dealloc_ctx_id(aq, ctx_id); 316 } 317 318 static inline struct efa_comp_ctx *efa_com_get_comp_ctx_by_cmd_id(struct efa_com_admin_queue *aq, 319 u16 cmd_id) 320 { 321 u16 ctx_id = cmd_id & (aq->depth - 1); 322 323 return &aq->comp_ctx[ctx_id]; 324 } 325 326 static void __efa_com_submit_admin_cmd(struct efa_com_admin_queue *aq, 327 struct efa_comp_ctx *comp_ctx, 328 struct efa_admin_aq_entry *cmd, 329 size_t cmd_size_in_bytes, 330 struct efa_admin_acq_entry *comp, 331 size_t comp_size_in_bytes) 332 { 333 struct efa_admin_aq_entry *aqe; 334 u16 queue_size_mask; 335 u16 cmd_id; 336 u16 ctx_id; 337 u16 pi; 338 339 queue_size_mask = aq->depth - 1; 340 pi = aq->sq.pc & queue_size_mask; 341 ctx_id = efa_com_get_comp_ctx_id(aq, comp_ctx); 342 343 /* cmd_id LSBs are the ctx_id and MSBs are entropy bits from pc */ 344 cmd_id = ctx_id & queue_size_mask; 345 cmd_id |= aq->sq.pc << ilog2(aq->depth); 346 cmd_id &= EFA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 347 348 cmd->aq_common_descriptor.command_id = cmd_id; 349 EFA_SET(&cmd->aq_common_descriptor.flags, 350 EFA_ADMIN_AQ_COMMON_DESC_PHASE, aq->sq.phase); 351 352 comp_ctx->status = EFA_CMD_SUBMITTED; 353 comp_ctx->comp_size = comp_size_in_bytes; 354 comp_ctx->user_cqe = comp; 355 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode; 356 comp_ctx->cmd_id = cmd_id; 357 358 reinit_completion(&comp_ctx->wait_event); 359 360 aqe = &aq->sq.entries[pi]; 361 memset(aqe, 0, sizeof(*aqe)); 362 memcpy(aqe, cmd, cmd_size_in_bytes); 363 364 aq->sq.pc++; 365 atomic64_inc(&aq->stats.submitted_cmd); 366 367 if ((aq->sq.pc & queue_size_mask) == 0) 368 aq->sq.phase = !aq->sq.phase; 369 370 /* barrier not needed in case of writel */ 371 writel(aq->sq.pc, aq->sq.db_addr); 372 } 373 374 static inline int efa_com_init_comp_ctxt(struct efa_com_admin_queue *aq) 375 { 376 size_t pool_size = aq->depth * sizeof(*aq->comp_ctx_pool); 377 size_t size = aq->depth * sizeof(struct efa_comp_ctx); 378 struct efa_comp_ctx *comp_ctx; 379 u16 i; 380 381 aq->comp_ctx = devm_kzalloc(aq->dmadev, size, GFP_KERNEL); 382 aq->comp_ctx_pool = devm_kzalloc(aq->dmadev, pool_size, GFP_KERNEL); 383 if (!aq->comp_ctx || !aq->comp_ctx_pool) { 384 devm_kfree(aq->dmadev, aq->comp_ctx_pool); 385 devm_kfree(aq->dmadev, aq->comp_ctx); 386 return -ENOMEM; 387 } 388 389 for (i = 0; i < aq->depth; i++) { 390 comp_ctx = &aq->comp_ctx[i]; 391 comp_ctx->status = EFA_CMD_UNUSED; 392 init_completion(&comp_ctx->wait_event); 393 394 aq->comp_ctx_pool[i] = i; 395 } 396 397 spin_lock_init(&aq->comp_ctx_lock); 398 399 aq->comp_ctx_pool_next = 0; 400 401 return 0; 402 } 403 404 static int efa_com_submit_admin_cmd(struct efa_com_admin_queue *aq, 405 struct efa_comp_ctx *comp_ctx, 406 struct efa_admin_aq_entry *cmd, 407 size_t cmd_size_in_bytes, 408 struct efa_admin_acq_entry *comp, 409 size_t comp_size_in_bytes) 410 { 411 spin_lock(&aq->sq.lock); 412 if (!test_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state)) { 413 ibdev_err_ratelimited(aq->efa_dev, "Admin queue is closed\n"); 414 spin_unlock(&aq->sq.lock); 415 return -ENODEV; 416 } 417 418 __efa_com_submit_admin_cmd(aq, comp_ctx, cmd, cmd_size_in_bytes, comp, 419 comp_size_in_bytes); 420 spin_unlock(&aq->sq.lock); 421 422 return 0; 423 } 424 425 static bool efa_com_cqe_checksum_valid(struct efa_com_admin_queue *aq, 426 struct efa_admin_acq_entry *cqe) 427 { 428 u16 cqe_checksum = cqe->acq_common_descriptor.checksum; 429 u16 calc_checksum; 430 431 cqe->acq_common_descriptor.checksum = 0; 432 433 calc_checksum = crc16(EFA_CRC16_INIT_VAL, (u8 *)cqe, sizeof(*cqe)) ^ EFA_CRC16_INIT_VAL; 434 if (calc_checksum != cqe_checksum) { 435 ibdev_err(aq->efa_dev, 436 "Received completion with invalid checksum, cqe[%u], calc[%u], sq producer[%d], sq consumer[%d], cq consumer[%d]\n", 437 cqe_checksum, calc_checksum, aq->sq.pc, aq->sq.cc, 438 aq->cq.cc); 439 return false; 440 } 441 442 return true; 443 } 444 445 static int efa_com_handle_single_admin_completion(struct efa_com_admin_queue *aq, 446 struct efa_admin_acq_entry *cqe) 447 { 448 struct efa_comp_ctx *comp_ctx; 449 u16 cmd_id; 450 451 if (aq->cq.validate_checksum && !efa_com_cqe_checksum_valid(aq, cqe)) 452 return -EINVAL; 453 454 cmd_id = EFA_GET(&cqe->acq_common_descriptor.command, 455 EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID); 456 457 comp_ctx = efa_com_get_comp_ctx_by_cmd_id(aq, cmd_id); 458 if (comp_ctx->status != EFA_CMD_SUBMITTED || comp_ctx->cmd_id != cmd_id) { 459 ibdev_err(aq->efa_dev, 460 "Received completion with unexpected command id[%x], status[%d] sq producer[%d], sq consumer[%d], cq consumer[%d]\n", 461 cmd_id, comp_ctx->status, aq->sq.pc, aq->sq.cc, 462 aq->cq.cc); 463 return -EINVAL; 464 } 465 466 comp_ctx->status = EFA_CMD_COMPLETED; 467 memcpy(comp_ctx->user_cqe, cqe, comp_ctx->comp_size); 468 469 if (!test_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state)) 470 complete(&comp_ctx->wait_event); 471 472 return 0; 473 } 474 475 static void efa_com_handle_admin_completion(struct efa_com_admin_queue *aq) 476 { 477 struct efa_admin_acq_entry *cqe; 478 u16 queue_size_mask; 479 u16 comp_cmds = 0; 480 u8 phase; 481 int err; 482 u16 ci; 483 484 queue_size_mask = aq->depth - 1; 485 486 ci = aq->cq.cc & queue_size_mask; 487 phase = aq->cq.phase; 488 489 cqe = &aq->cq.entries[ci]; 490 491 /* Go over all the completions */ 492 while ((READ_ONCE(cqe->acq_common_descriptor.flags) & 493 EFA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) { 494 /* 495 * Do not read the rest of the completion entry before the 496 * phase bit was validated 497 */ 498 dma_rmb(); 499 err = efa_com_handle_single_admin_completion(aq, cqe); 500 if (!err) 501 comp_cmds++; 502 503 aq->cq.cc++; 504 ci++; 505 if (ci == aq->depth) { 506 ci = 0; 507 phase = !phase; 508 } 509 510 cqe = &aq->cq.entries[ci]; 511 } 512 513 aq->cq.phase = phase; 514 aq->sq.cc += comp_cmds; 515 atomic64_add(comp_cmds, &aq->stats.completed_cmd); 516 } 517 518 static int efa_com_comp_status_to_errno(u8 comp_status) 519 { 520 switch (comp_status) { 521 case EFA_ADMIN_SUCCESS: 522 return 0; 523 case EFA_ADMIN_RESOURCE_ALLOCATION_FAILURE: 524 return -ENOMEM; 525 case EFA_ADMIN_UNSUPPORTED_OPCODE: 526 return -EOPNOTSUPP; 527 case EFA_ADMIN_BAD_OPCODE: 528 case EFA_ADMIN_MALFORMED_REQUEST: 529 case EFA_ADMIN_ILLEGAL_PARAMETER: 530 case EFA_ADMIN_UNKNOWN_ERROR: 531 return -EINVAL; 532 default: 533 return -EINVAL; 534 } 535 } 536 537 static int efa_com_wait_and_process_admin_cq_polling(struct efa_comp_ctx *comp_ctx, 538 struct efa_com_admin_queue *aq) 539 { 540 unsigned long timeout; 541 unsigned long flags; 542 543 timeout = jiffies + usecs_to_jiffies(aq->completion_timeout); 544 545 while (1) { 546 spin_lock_irqsave(&aq->cq.lock, flags); 547 efa_com_handle_admin_completion(aq); 548 spin_unlock_irqrestore(&aq->cq.lock, flags); 549 550 if (comp_ctx->status != EFA_CMD_SUBMITTED) 551 break; 552 553 if (time_is_before_jiffies(timeout)) { 554 ibdev_err_ratelimited( 555 aq->efa_dev, 556 "Wait for completion (polling) timeout\n"); 557 /* EFA didn't have any completion */ 558 atomic64_inc(&aq->stats.no_completion); 559 560 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); 561 return -ETIME; 562 } 563 564 msleep(aq->poll_interval); 565 } 566 567 return efa_com_comp_status_to_errno( 568 comp_ctx->user_cqe->acq_common_descriptor.status); 569 } 570 571 static int efa_com_wait_and_process_admin_cq_interrupts(struct efa_comp_ctx *comp_ctx, 572 struct efa_com_admin_queue *aq) 573 { 574 unsigned long flags; 575 576 wait_for_completion_timeout(&comp_ctx->wait_event, 577 usecs_to_jiffies(aq->completion_timeout)); 578 579 /* 580 * In case the command wasn't completed find out the root cause. 581 * There might be 2 kinds of errors 582 * 1) No completion (timeout reached) 583 * 2) There is completion but the device didn't get any msi-x interrupt. 584 */ 585 if (comp_ctx->status == EFA_CMD_SUBMITTED) { 586 spin_lock_irqsave(&aq->cq.lock, flags); 587 efa_com_handle_admin_completion(aq); 588 spin_unlock_irqrestore(&aq->cq.lock, flags); 589 590 atomic64_inc(&aq->stats.no_completion); 591 592 if (comp_ctx->status == EFA_CMD_COMPLETED) 593 ibdev_err_ratelimited( 594 aq->efa_dev, 595 "The device sent a completion but the driver didn't receive any MSI-X interrupt for admin cmd %s(%d) status %d (id: %d, sq producer: %d, sq consumer: %d, cq consumer: %d)\n", 596 efa_com_cmd_str(comp_ctx->cmd_opcode), 597 comp_ctx->cmd_opcode, comp_ctx->status, 598 comp_ctx->cmd_id, aq->sq.pc, aq->sq.cc, 599 aq->cq.cc); 600 else 601 ibdev_err_ratelimited( 602 aq->efa_dev, 603 "The device didn't send any completion for admin cmd %s(%d) status %d (id: %d, sq producer: %d, sq consumer: %d, cq consumer: %d)\n", 604 efa_com_cmd_str(comp_ctx->cmd_opcode), 605 comp_ctx->cmd_opcode, comp_ctx->status, 606 comp_ctx->cmd_id, aq->sq.pc, aq->sq.cc, 607 aq->cq.cc); 608 609 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); 610 return -ETIME; 611 } 612 613 return efa_com_comp_status_to_errno( 614 comp_ctx->user_cqe->acq_common_descriptor.status); 615 } 616 617 /* 618 * There are two types to wait for completion. 619 * Polling mode - wait until the completion is available. 620 * Async mode - wait on wait queue until the completion is ready 621 * (or the timeout expired). 622 * It is expected that the IRQ called efa_com_handle_admin_completion 623 * to mark the completions. 624 */ 625 static int efa_com_wait_and_process_admin_cq(struct efa_comp_ctx *comp_ctx, 626 struct efa_com_admin_queue *aq) 627 { 628 if (test_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state)) 629 return efa_com_wait_and_process_admin_cq_polling(comp_ctx, aq); 630 631 return efa_com_wait_and_process_admin_cq_interrupts(comp_ctx, aq); 632 } 633 634 /** 635 * efa_com_cmd_exec - Execute admin command 636 * @aq: admin queue. 637 * @cmd: the admin command to execute. 638 * @cmd_size: the command size. 639 * @comp: command completion return entry. 640 * @comp_size: command completion size. 641 * Submit an admin command and then wait until the device will return a 642 * completion. 643 * The completion will be copied into comp. 644 * 645 * @return - 0 on success, negative value on failure. 646 */ 647 int efa_com_cmd_exec(struct efa_com_admin_queue *aq, 648 struct efa_admin_aq_entry *cmd, 649 size_t cmd_size, 650 struct efa_admin_acq_entry *comp, 651 size_t comp_size) 652 { 653 struct efa_comp_ctx *comp_ctx; 654 int err; 655 656 might_sleep(); 657 658 /* In case of queue FULL */ 659 down(&aq->avail_cmds); 660 661 ibdev_dbg(aq->efa_dev, "%s (opcode %d)\n", 662 efa_com_cmd_str(cmd->aq_common_descriptor.opcode), 663 cmd->aq_common_descriptor.opcode); 664 665 comp_ctx = efa_com_alloc_comp_ctx(aq); 666 if (!comp_ctx) { 667 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); 668 up(&aq->avail_cmds); 669 return -EINVAL; 670 } 671 672 err = efa_com_submit_admin_cmd(aq, comp_ctx, cmd, cmd_size, comp, comp_size); 673 if (err) { 674 ibdev_err_ratelimited( 675 aq->efa_dev, 676 "Failed to submit command %s (opcode %u) err %d\n", 677 efa_com_cmd_str(cmd->aq_common_descriptor.opcode), 678 cmd->aq_common_descriptor.opcode, err); 679 680 efa_com_dealloc_comp_ctx(aq, comp_ctx); 681 up(&aq->avail_cmds); 682 atomic64_inc(&aq->stats.cmd_err); 683 return err; 684 } 685 686 err = efa_com_wait_and_process_admin_cq(comp_ctx, aq); 687 if (err) { 688 ibdev_err_ratelimited( 689 aq->efa_dev, 690 "Failed to process command %s (opcode %u) err %d\n", 691 efa_com_cmd_str(cmd->aq_common_descriptor.opcode), 692 cmd->aq_common_descriptor.opcode, err); 693 atomic64_inc(&aq->stats.cmd_err); 694 } 695 696 efa_com_dealloc_comp_ctx(aq, comp_ctx); 697 up(&aq->avail_cmds); 698 699 return err; 700 } 701 702 /** 703 * efa_com_admin_destroy - Destroy the admin and the async events queues. 704 * @edev: EFA communication layer struct 705 */ 706 void efa_com_admin_destroy(struct efa_com_dev *edev) 707 { 708 struct efa_com_admin_queue *aq = &edev->aq; 709 struct efa_com_aenq *aenq = &edev->aenq; 710 struct efa_com_admin_cq *cq = &aq->cq; 711 struct efa_com_admin_sq *sq = &aq->sq; 712 u16 size; 713 714 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); 715 716 devm_kfree(edev->dmadev, aq->comp_ctx_pool); 717 devm_kfree(edev->dmadev, aq->comp_ctx); 718 719 size = aq->depth * sizeof(*sq->entries); 720 dma_free_coherent(edev->dmadev, size, sq->entries, sq->dma_addr); 721 722 size = aq->depth * sizeof(*cq->entries); 723 dma_free_coherent(edev->dmadev, size, cq->entries, cq->dma_addr); 724 725 size = aenq->depth * sizeof(*aenq->entries); 726 dma_free_coherent(edev->dmadev, size, aenq->entries, aenq->dma_addr); 727 } 728 729 /** 730 * efa_com_set_admin_polling_mode - Set the admin completion queue polling mode 731 * @edev: EFA communication layer struct 732 * @polling: Enable/Disable polling mode 733 * 734 * Set the admin completion mode. 735 */ 736 void efa_com_set_admin_polling_mode(struct efa_com_dev *edev, bool polling) 737 { 738 u32 mask_value = 0; 739 740 if (polling) 741 EFA_SET(&mask_value, EFA_REGS_INTR_MASK_EN, 1); 742 743 writel(mask_value, edev->reg_bar + EFA_REGS_INTR_MASK_OFF); 744 if (polling) 745 set_bit(EFA_AQ_STATE_POLLING_BIT, &edev->aq.state); 746 else 747 clear_bit(EFA_AQ_STATE_POLLING_BIT, &edev->aq.state); 748 } 749 750 static void efa_com_stats_init(struct efa_com_dev *edev) 751 { 752 atomic64_t *s = (atomic64_t *)&edev->aq.stats; 753 int i; 754 755 for (i = 0; i < sizeof(edev->aq.stats) / sizeof(*s); i++, s++) 756 atomic64_set(s, 0); 757 } 758 759 /** 760 * efa_com_admin_init - Init the admin and the async queues 761 * @edev: EFA communication layer struct 762 * @aenq_handlers: Those handlers to be called upon event. 763 * 764 * Initialize the admin submission and completion queues. 765 * Initialize the asynchronous events notification queues. 766 * 767 * @return - 0 on success, negative value on failure. 768 */ 769 int efa_com_admin_init(struct efa_com_dev *edev, 770 struct efa_aenq_handlers *aenq_handlers) 771 { 772 struct efa_com_admin_queue *aq = &edev->aq; 773 u32 timeout; 774 u32 dev_sts; 775 u32 cap; 776 int err; 777 778 dev_sts = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF); 779 if (!EFA_GET(&dev_sts, EFA_REGS_DEV_STS_READY)) { 780 ibdev_err(edev->efa_dev, 781 "Device isn't ready, abort com init %#x\n", dev_sts); 782 return -ENODEV; 783 } 784 785 aq->depth = EFA_ADMIN_QUEUE_DEPTH; 786 787 aq->dmadev = edev->dmadev; 788 aq->efa_dev = edev->efa_dev; 789 set_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state); 790 791 sema_init(&aq->avail_cmds, aq->depth); 792 793 efa_com_stats_init(edev); 794 795 err = efa_com_init_comp_ctxt(aq); 796 if (err) 797 return err; 798 799 err = efa_com_admin_init_sq(edev); 800 if (err) 801 goto err_destroy_comp_ctxt; 802 803 err = efa_com_admin_init_cq(edev); 804 if (err) 805 goto err_destroy_sq; 806 807 efa_com_set_admin_polling_mode(edev, false); 808 809 err = efa_com_admin_init_aenq(edev, aenq_handlers); 810 if (err) 811 goto err_destroy_cq; 812 813 cap = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF); 814 timeout = EFA_GET(&cap, EFA_REGS_CAPS_ADMIN_CMD_TO); 815 if (timeout) 816 /* the resolution of timeout reg is 100ms */ 817 aq->completion_timeout = timeout * 100000; 818 else 819 aq->completion_timeout = ADMIN_CMD_TIMEOUT_US; 820 821 aq->poll_interval = EFA_POLL_INTERVAL_MS; 822 823 set_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); 824 825 return 0; 826 827 err_destroy_cq: 828 dma_free_coherent(edev->dmadev, aq->depth * sizeof(*aq->cq.entries), 829 aq->cq.entries, aq->cq.dma_addr); 830 err_destroy_sq: 831 dma_free_coherent(edev->dmadev, aq->depth * sizeof(*aq->sq.entries), 832 aq->sq.entries, aq->sq.dma_addr); 833 err_destroy_comp_ctxt: 834 devm_kfree(edev->dmadev, aq->comp_ctx); 835 836 return err; 837 } 838 839 /** 840 * efa_com_admin_q_comp_intr_handler - admin queue interrupt handler 841 * @edev: EFA communication layer struct 842 * 843 * This method goes over the admin completion queue and wakes up 844 * all the pending threads that wait on the commands wait event. 845 * 846 * Note: Should be called after MSI-X interrupt. 847 */ 848 void efa_com_admin_q_comp_intr_handler(struct efa_com_dev *edev) 849 { 850 unsigned long flags; 851 852 spin_lock_irqsave(&edev->aq.cq.lock, flags); 853 efa_com_handle_admin_completion(&edev->aq); 854 spin_unlock_irqrestore(&edev->aq.cq.lock, flags); 855 } 856 857 /* 858 * efa_handle_specific_aenq_event: 859 * return the handler that is relevant to the specific event group 860 */ 861 static efa_aenq_handler efa_com_get_specific_aenq_cb(struct efa_com_dev *edev, 862 u16 group) 863 { 864 struct efa_aenq_handlers *aenq_handlers = edev->aenq.aenq_handlers; 865 866 if (group < EFA_MAX_HANDLERS && aenq_handlers->handlers[group]) 867 return aenq_handlers->handlers[group]; 868 869 return aenq_handlers->unimplemented_handler; 870 } 871 872 /** 873 * efa_com_aenq_intr_handler - AENQ interrupt handler 874 * @edev: EFA communication layer struct 875 * @data: Data of interrupt handler. 876 * 877 * Go over the async event notification queue and call the proper aenq handler. 878 */ 879 void efa_com_aenq_intr_handler(struct efa_com_dev *edev, void *data) 880 { 881 struct efa_admin_aenq_common_desc *aenq_common; 882 struct efa_com_aenq *aenq = &edev->aenq; 883 struct efa_admin_aenq_entry *aenq_e; 884 efa_aenq_handler handler_cb; 885 u32 processed = 0; 886 u8 phase; 887 u32 ci; 888 889 ci = aenq->cc & (aenq->depth - 1); 890 phase = aenq->phase; 891 aenq_e = &aenq->entries[ci]; /* Get first entry */ 892 aenq_common = &aenq_e->aenq_common_desc; 893 894 /* Go over all the events */ 895 while ((READ_ONCE(aenq_common->flags) & 896 EFA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) { 897 /* 898 * Do not read the rest of the completion entry before the 899 * phase bit was validated 900 */ 901 dma_rmb(); 902 903 /* Handle specific event*/ 904 handler_cb = efa_com_get_specific_aenq_cb(edev, 905 aenq_common->group); 906 handler_cb(data, aenq_e); /* call the actual event handler*/ 907 908 /* Get next event entry */ 909 ci++; 910 processed++; 911 912 if (ci == aenq->depth) { 913 ci = 0; 914 phase = !phase; 915 } 916 aenq_e = &aenq->entries[ci]; 917 aenq_common = &aenq_e->aenq_common_desc; 918 } 919 920 aenq->cc += processed; 921 aenq->phase = phase; 922 923 /* Don't update aenq doorbell if there weren't any processed events */ 924 if (!processed) 925 return; 926 927 /* barrier not needed in case of writel */ 928 writel(aenq->cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF); 929 } 930 931 static void efa_com_mmio_reg_read_resp_addr_init(struct efa_com_dev *edev) 932 { 933 struct efa_com_mmio_read *mmio_read = &edev->mmio_read; 934 u32 addr_high; 935 u32 addr_low; 936 937 /* dma_addr_bits is unknown at this point */ 938 addr_high = (mmio_read->read_resp_dma_addr >> 32) & GENMASK(31, 0); 939 addr_low = mmio_read->read_resp_dma_addr & GENMASK(31, 0); 940 941 writel(addr_high, edev->reg_bar + EFA_REGS_MMIO_RESP_HI_OFF); 942 writel(addr_low, edev->reg_bar + EFA_REGS_MMIO_RESP_LO_OFF); 943 } 944 945 int efa_com_mmio_reg_read_init(struct efa_com_dev *edev) 946 { 947 struct efa_com_mmio_read *mmio_read = &edev->mmio_read; 948 949 spin_lock_init(&mmio_read->lock); 950 mmio_read->read_resp = 951 dma_alloc_coherent(edev->dmadev, sizeof(*mmio_read->read_resp), 952 &mmio_read->read_resp_dma_addr, GFP_KERNEL); 953 if (!mmio_read->read_resp) 954 return -ENOMEM; 955 956 efa_com_mmio_reg_read_resp_addr_init(edev); 957 958 mmio_read->read_resp->req_id = 0; 959 mmio_read->seq_num = 0; 960 mmio_read->mmio_read_timeout = EFA_REG_READ_TIMEOUT_US; 961 962 return 0; 963 } 964 965 void efa_com_mmio_reg_read_destroy(struct efa_com_dev *edev) 966 { 967 struct efa_com_mmio_read *mmio_read = &edev->mmio_read; 968 969 dma_free_coherent(edev->dmadev, sizeof(*mmio_read->read_resp), 970 mmio_read->read_resp, mmio_read->read_resp_dma_addr); 971 } 972 973 int efa_com_validate_version(struct efa_com_dev *edev) 974 { 975 u32 min_ctrl_ver = 0; 976 u32 ctrl_ver_masked; 977 u32 min_ver = 0; 978 u32 ctrl_ver; 979 u32 ver; 980 981 /* 982 * Make sure the EFA version and the controller version are at least 983 * as the driver expects 984 */ 985 ver = efa_com_reg_read32(edev, EFA_REGS_VERSION_OFF); 986 ctrl_ver = efa_com_reg_read32(edev, 987 EFA_REGS_CONTROLLER_VERSION_OFF); 988 989 ibdev_dbg(edev->efa_dev, "efa device version: %d.%d\n", 990 EFA_GET(&ver, EFA_REGS_VERSION_MAJOR_VERSION), 991 EFA_GET(&ver, EFA_REGS_VERSION_MINOR_VERSION)); 992 993 EFA_SET(&min_ver, EFA_REGS_VERSION_MAJOR_VERSION, EFA_MIN_ADMIN_API_VERSION_MAJOR); 994 EFA_SET(&min_ver, EFA_REGS_VERSION_MINOR_VERSION, EFA_MIN_ADMIN_API_VERSION_MINOR); 995 if (ver < min_ver) { 996 ibdev_err(edev->efa_dev, 997 "EFA version is lower than the minimal version the driver supports\n"); 998 return -EOPNOTSUPP; 999 } 1000 1001 edev->dev_api_ver = ver; 1002 1003 ibdev_dbg( 1004 edev->efa_dev, 1005 "efa controller version: %d.%d.%d implementation version %d\n", 1006 EFA_GET(&ctrl_ver, EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION), 1007 EFA_GET(&ctrl_ver, EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION), 1008 EFA_GET(&ctrl_ver, 1009 EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION), 1010 EFA_GET(&ctrl_ver, EFA_REGS_CONTROLLER_VERSION_IMPL_ID)); 1011 1012 ctrl_ver_masked = 1013 EFA_GET(&ctrl_ver, EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION) | 1014 EFA_GET(&ctrl_ver, EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION) | 1015 EFA_GET(&ctrl_ver, 1016 EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION); 1017 1018 EFA_SET(&min_ctrl_ver, EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION, 1019 EFA_CTRL_MAJOR); 1020 EFA_SET(&min_ctrl_ver, EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION, 1021 EFA_CTRL_MINOR); 1022 EFA_SET(&min_ctrl_ver, EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION, 1023 EFA_CTRL_SUB_MINOR); 1024 /* Validate the ctrl version without the implementation ID */ 1025 if (ctrl_ver_masked < min_ctrl_ver) { 1026 ibdev_err(edev->efa_dev, 1027 "EFA ctrl version is lower than the minimal ctrl version the driver supports\n"); 1028 return -EOPNOTSUPP; 1029 } 1030 1031 return 0; 1032 } 1033 1034 /** 1035 * efa_com_get_dma_width - Retrieve physical dma address width the device 1036 * supports. 1037 * @edev: EFA communication layer struct 1038 * 1039 * Retrieve the maximum physical address bits the device can handle. 1040 * 1041 * @return: > 0 on Success and negative value otherwise. 1042 */ 1043 int efa_com_get_dma_width(struct efa_com_dev *edev) 1044 { 1045 u32 caps = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF); 1046 int width; 1047 1048 width = EFA_GET(&caps, EFA_REGS_CAPS_DMA_ADDR_WIDTH); 1049 1050 ibdev_dbg(edev->efa_dev, "DMA width: %d\n", width); 1051 1052 if (width < 32 || width > 64) { 1053 ibdev_err(edev->efa_dev, "DMA width illegal value: %d\n", width); 1054 return -EINVAL; 1055 } 1056 1057 edev->dma_addr_bits = width; 1058 1059 return width; 1060 } 1061 1062 static int wait_for_reset_state(struct efa_com_dev *edev, u32 timeout, int on) 1063 { 1064 u32 val, i; 1065 1066 for (i = 0; i < timeout; i++) { 1067 val = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF); 1068 1069 if (EFA_GET(&val, EFA_REGS_DEV_STS_RESET_IN_PROGRESS) == on) 1070 return 0; 1071 1072 ibdev_dbg(edev->efa_dev, "Reset indication val %d\n", val); 1073 msleep(EFA_POLL_INTERVAL_MS); 1074 } 1075 1076 return -ETIME; 1077 } 1078 1079 /** 1080 * efa_com_dev_reset - Perform device FLR to the device. 1081 * @edev: EFA communication layer struct 1082 * @reset_reason: Specify what is the trigger for the reset in case of an error. 1083 * 1084 * @return - 0 on success, negative value on failure. 1085 */ 1086 int efa_com_dev_reset(struct efa_com_dev *edev, 1087 enum efa_regs_reset_reason_types reset_reason) 1088 { 1089 u32 stat, timeout, cap; 1090 u32 reset_val = 0; 1091 int err; 1092 1093 stat = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF); 1094 cap = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF); 1095 1096 if (!EFA_GET(&stat, EFA_REGS_DEV_STS_READY)) { 1097 ibdev_err(edev->efa_dev, 1098 "Device isn't ready, can't reset device\n"); 1099 return -EINVAL; 1100 } 1101 1102 timeout = EFA_GET(&cap, EFA_REGS_CAPS_RESET_TIMEOUT); 1103 if (!timeout) { 1104 ibdev_err(edev->efa_dev, "Invalid timeout value\n"); 1105 return -EINVAL; 1106 } 1107 1108 /* start reset */ 1109 EFA_SET(&reset_val, EFA_REGS_DEV_CTL_DEV_RESET, 1); 1110 EFA_SET(&reset_val, EFA_REGS_DEV_CTL_RESET_REASON, reset_reason); 1111 writel(reset_val, edev->reg_bar + EFA_REGS_DEV_CTL_OFF); 1112 1113 /* reset clears the mmio readless address, restore it */ 1114 efa_com_mmio_reg_read_resp_addr_init(edev); 1115 1116 err = wait_for_reset_state(edev, timeout, 1); 1117 if (err) { 1118 ibdev_err(edev->efa_dev, "Reset indication didn't turn on\n"); 1119 return err; 1120 } 1121 1122 /* reset done */ 1123 writel(0, edev->reg_bar + EFA_REGS_DEV_CTL_OFF); 1124 err = wait_for_reset_state(edev, timeout, 0); 1125 if (err) { 1126 ibdev_err(edev->efa_dev, "Reset indication didn't turn off\n"); 1127 return err; 1128 } 1129 1130 timeout = EFA_GET(&cap, EFA_REGS_CAPS_ADMIN_CMD_TO); 1131 if (timeout) 1132 /* the resolution of timeout reg is 100ms */ 1133 edev->aq.completion_timeout = timeout * 100000; 1134 else 1135 edev->aq.completion_timeout = ADMIN_CMD_TIMEOUT_US; 1136 1137 return 0; 1138 } 1139 1140 static int efa_com_create_eq(struct efa_com_dev *edev, 1141 struct efa_com_create_eq_params *params, 1142 struct efa_com_create_eq_result *result) 1143 { 1144 struct efa_com_admin_queue *aq = &edev->aq; 1145 struct efa_admin_create_eq_resp resp = {}; 1146 struct efa_admin_create_eq_cmd cmd = {}; 1147 int err; 1148 1149 cmd.aq_common_descriptor.opcode = EFA_ADMIN_CREATE_EQ; 1150 EFA_SET(&cmd.caps, EFA_ADMIN_CREATE_EQ_CMD_ENTRY_SIZE_WORDS, 1151 params->entry_size_in_bytes / 4); 1152 cmd.depth = params->depth; 1153 cmd.event_bitmask = params->event_bitmask; 1154 cmd.msix_vec = params->msix_vec; 1155 1156 efa_com_set_dma_addr(params->dma_addr, &cmd.ba.mem_addr_high, 1157 &cmd.ba.mem_addr_low); 1158 1159 err = efa_com_cmd_exec(aq, 1160 (struct efa_admin_aq_entry *)&cmd, 1161 sizeof(cmd), 1162 (struct efa_admin_acq_entry *)&resp, 1163 sizeof(resp)); 1164 if (err) { 1165 ibdev_err_ratelimited(edev->efa_dev, 1166 "Failed to create eq[%d]\n", err); 1167 return err; 1168 } 1169 1170 result->eqn = resp.eqn; 1171 1172 return 0; 1173 } 1174 1175 static void efa_com_destroy_eq(struct efa_com_dev *edev, 1176 struct efa_com_destroy_eq_params *params) 1177 { 1178 struct efa_com_admin_queue *aq = &edev->aq; 1179 struct efa_admin_destroy_eq_resp resp = {}; 1180 struct efa_admin_destroy_eq_cmd cmd = {}; 1181 int err; 1182 1183 cmd.aq_common_descriptor.opcode = EFA_ADMIN_DESTROY_EQ; 1184 cmd.eqn = params->eqn; 1185 1186 err = efa_com_cmd_exec(aq, 1187 (struct efa_admin_aq_entry *)&cmd, 1188 sizeof(cmd), 1189 (struct efa_admin_acq_entry *)&resp, 1190 sizeof(resp)); 1191 if (err) 1192 ibdev_err_ratelimited(edev->efa_dev, 1193 "Failed to destroy EQ-%u [%d]\n", cmd.eqn, 1194 err); 1195 } 1196 1197 static void efa_com_arm_eq(struct efa_com_dev *edev, struct efa_com_eq *eeq) 1198 { 1199 u32 val = 0; 1200 1201 EFA_SET(&val, EFA_REGS_EQ_DB_EQN, eeq->eqn); 1202 EFA_SET(&val, EFA_REGS_EQ_DB_ARM, 1); 1203 1204 writel(val, edev->reg_bar + EFA_REGS_EQ_DB_OFF); 1205 } 1206 1207 void efa_com_eq_comp_intr_handler(struct efa_com_dev *edev, 1208 struct efa_com_eq *eeq) 1209 { 1210 struct efa_admin_eqe *eqe; 1211 u32 processed = 0; 1212 u8 phase; 1213 u32 ci; 1214 1215 ci = eeq->cc & (eeq->depth - 1); 1216 phase = eeq->phase; 1217 eqe = &eeq->eqes[ci]; 1218 1219 /* Go over all the events */ 1220 while ((READ_ONCE(eqe->common) & EFA_ADMIN_EQE_PHASE_MASK) == phase) { 1221 /* 1222 * Do not read the rest of the completion entry before the 1223 * phase bit was validated 1224 */ 1225 dma_rmb(); 1226 1227 eeq->cb(eeq, eqe); 1228 1229 /* Get next event entry */ 1230 ci++; 1231 processed++; 1232 1233 if (ci == eeq->depth) { 1234 ci = 0; 1235 phase = !phase; 1236 } 1237 1238 eqe = &eeq->eqes[ci]; 1239 } 1240 1241 eeq->cc += processed; 1242 eeq->phase = phase; 1243 efa_com_arm_eq(eeq->edev, eeq); 1244 } 1245 1246 void efa_com_eq_destroy(struct efa_com_dev *edev, struct efa_com_eq *eeq) 1247 { 1248 struct efa_com_destroy_eq_params params = { 1249 .eqn = eeq->eqn, 1250 }; 1251 1252 efa_com_destroy_eq(edev, ¶ms); 1253 dma_free_coherent(edev->dmadev, eeq->depth * sizeof(*eeq->eqes), 1254 eeq->eqes, eeq->dma_addr); 1255 } 1256 1257 int efa_com_eq_init(struct efa_com_dev *edev, struct efa_com_eq *eeq, 1258 efa_eqe_handler cb, u16 depth, u8 msix_vec) 1259 { 1260 struct efa_com_create_eq_params params = {}; 1261 struct efa_com_create_eq_result result = {}; 1262 int err; 1263 1264 params.depth = depth; 1265 params.entry_size_in_bytes = sizeof(*eeq->eqes); 1266 EFA_SET(¶ms.event_bitmask, 1267 EFA_ADMIN_CREATE_EQ_CMD_COMPLETION_EVENTS, 1); 1268 params.msix_vec = msix_vec; 1269 1270 eeq->eqes = dma_alloc_coherent(edev->dmadev, 1271 params.depth * sizeof(*eeq->eqes), 1272 ¶ms.dma_addr, GFP_KERNEL); 1273 if (!eeq->eqes) 1274 return -ENOMEM; 1275 1276 err = efa_com_create_eq(edev, ¶ms, &result); 1277 if (err) 1278 goto err_free_coherent; 1279 1280 eeq->eqn = result.eqn; 1281 eeq->edev = edev; 1282 eeq->dma_addr = params.dma_addr; 1283 eeq->phase = 1; 1284 eeq->depth = params.depth; 1285 eeq->cb = cb; 1286 efa_com_arm_eq(edev, eeq); 1287 1288 return 0; 1289 1290 err_free_coherent: 1291 dma_free_coherent(edev->dmadev, params.depth * sizeof(*eeq->eqes), 1292 eeq->eqes, params.dma_addr); 1293 return err; 1294 } 1295