1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
4 */
5 /*
6 * QCOM BAM DMA engine driver
7 *
8 * QCOM BAM DMA blocks are distributed amongst a number of the on-chip
9 * peripherals on the MSM 8x74. The configuration of the channels are dependent
10 * on the way they are hard wired to that specific peripheral. The peripheral
11 * device tree entries specify the configuration of each channel.
12 *
13 * The DMA controller requires the use of external memory for storage of the
14 * hardware descriptors for each channel. The descriptor FIFO is accessed as a
15 * circular buffer and operations are managed according to the offset within the
16 * FIFO. After pipe/channel reset, all of the pipe registers and internal state
17 * are back to defaults.
18 *
19 * During DMA operations, we write descriptors to the FIFO, being careful to
20 * handle wrapping and then write the last FIFO offset to that channel's
21 * P_EVNT_REG register to kick off the transaction. The P_SW_OFSTS register
22 * indicates the current FIFO offset that is being processed, so there is some
23 * indication of where the hardware is currently working.
24 */
25
26 #include <linux/circ_buf.h>
27 #include <linux/cleanup.h>
28 #include <linux/clk.h>
29 #include <linux/device.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/init.h>
33 #include <linux/interrupt.h>
34 #include <linux/io.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/of_address.h>
38 #include <linux/of_dma.h>
39 #include <linux/of_irq.h>
40 #include <linux/of.h>
41 #include <linux/platform_device.h>
42 #include <linux/pm_runtime.h>
43 #include <linux/scatterlist.h>
44 #include <linux/slab.h>
45
46 #include "../dmaengine.h"
47 #include "../virt-dma.h"
48
49 struct bam_desc_hw {
50 __le32 addr; /* Buffer physical address */
51 __le16 size; /* Buffer size in bytes */
52 __le16 flags;
53 };
54
55 #define BAM_DMA_AUTOSUSPEND_DELAY 100
56
57 #define DESC_FLAG_INT BIT(15)
58 #define DESC_FLAG_EOT BIT(14)
59 #define DESC_FLAG_EOB BIT(13)
60 #define DESC_FLAG_NWD BIT(12)
61 #define DESC_FLAG_CMD BIT(11)
62
63 struct bam_async_desc {
64 struct virt_dma_desc vd;
65
66 u32 num_desc;
67 u32 xfer_len;
68
69 /* transaction flags, EOT|EOB|NWD */
70 u16 flags;
71
72 struct bam_desc_hw *curr_desc;
73
74 /* list node for the desc in the bam_chan list of descriptors */
75 struct list_head desc_node;
76 enum dma_transfer_direction dir;
77 size_t length;
78 struct bam_desc_hw desc[] __counted_by(num_desc);
79 };
80
81 enum bam_reg {
82 BAM_CTRL,
83 BAM_REVISION,
84 BAM_NUM_PIPES,
85 BAM_DESC_CNT_TRSHLD,
86 BAM_IRQ_SRCS,
87 BAM_IRQ_SRCS_MSK,
88 BAM_IRQ_SRCS_UNMASKED,
89 BAM_IRQ_STTS,
90 BAM_IRQ_CLR,
91 BAM_IRQ_EN,
92 BAM_CNFG_BITS,
93 BAM_IRQ_SRCS_EE,
94 BAM_IRQ_SRCS_MSK_EE,
95 BAM_P_CTRL,
96 BAM_P_RST,
97 BAM_P_HALT,
98 BAM_P_IRQ_STTS,
99 BAM_P_IRQ_CLR,
100 BAM_P_IRQ_EN,
101 BAM_P_EVNT_DEST_ADDR,
102 BAM_P_EVNT_REG,
103 BAM_P_SW_OFSTS,
104 BAM_P_DATA_FIFO_ADDR,
105 BAM_P_DESC_FIFO_ADDR,
106 BAM_P_EVNT_GEN_TRSHLD,
107 BAM_P_FIFO_SIZES,
108 };
109
110 struct reg_offset_data {
111 u32 base_offset;
112 unsigned int pipe_mult, evnt_mult, ee_mult;
113 };
114
115 static const struct reg_offset_data bam_v1_3_reg_info[] = {
116 [BAM_CTRL] = { 0x0F80, 0x00, 0x00, 0x00 },
117 [BAM_REVISION] = { 0x0F84, 0x00, 0x00, 0x00 },
118 [BAM_NUM_PIPES] = { 0x0FBC, 0x00, 0x00, 0x00 },
119 [BAM_DESC_CNT_TRSHLD] = { 0x0F88, 0x00, 0x00, 0x00 },
120 [BAM_IRQ_SRCS] = { 0x0F8C, 0x00, 0x00, 0x00 },
121 [BAM_IRQ_SRCS_MSK] = { 0x0F90, 0x00, 0x00, 0x00 },
122 [BAM_IRQ_SRCS_UNMASKED] = { 0x0FB0, 0x00, 0x00, 0x00 },
123 [BAM_IRQ_STTS] = { 0x0F94, 0x00, 0x00, 0x00 },
124 [BAM_IRQ_CLR] = { 0x0F98, 0x00, 0x00, 0x00 },
125 [BAM_IRQ_EN] = { 0x0F9C, 0x00, 0x00, 0x00 },
126 [BAM_CNFG_BITS] = { 0x0FFC, 0x00, 0x00, 0x00 },
127 [BAM_IRQ_SRCS_EE] = { 0x1800, 0x00, 0x00, 0x80 },
128 [BAM_IRQ_SRCS_MSK_EE] = { 0x1804, 0x00, 0x00, 0x80 },
129 [BAM_P_CTRL] = { 0x0000, 0x80, 0x00, 0x00 },
130 [BAM_P_RST] = { 0x0004, 0x80, 0x00, 0x00 },
131 [BAM_P_HALT] = { 0x0008, 0x80, 0x00, 0x00 },
132 [BAM_P_IRQ_STTS] = { 0x0010, 0x80, 0x00, 0x00 },
133 [BAM_P_IRQ_CLR] = { 0x0014, 0x80, 0x00, 0x00 },
134 [BAM_P_IRQ_EN] = { 0x0018, 0x80, 0x00, 0x00 },
135 [BAM_P_EVNT_DEST_ADDR] = { 0x102C, 0x00, 0x40, 0x00 },
136 [BAM_P_EVNT_REG] = { 0x1018, 0x00, 0x40, 0x00 },
137 [BAM_P_SW_OFSTS] = { 0x1000, 0x00, 0x40, 0x00 },
138 [BAM_P_DATA_FIFO_ADDR] = { 0x1024, 0x00, 0x40, 0x00 },
139 [BAM_P_DESC_FIFO_ADDR] = { 0x101C, 0x00, 0x40, 0x00 },
140 [BAM_P_EVNT_GEN_TRSHLD] = { 0x1028, 0x00, 0x40, 0x00 },
141 [BAM_P_FIFO_SIZES] = { 0x1020, 0x00, 0x40, 0x00 },
142 };
143
144 static const struct reg_offset_data bam_v1_4_reg_info[] = {
145 [BAM_CTRL] = { 0x0000, 0x00, 0x00, 0x00 },
146 [BAM_REVISION] = { 0x0004, 0x00, 0x00, 0x00 },
147 [BAM_NUM_PIPES] = { 0x003C, 0x00, 0x00, 0x00 },
148 [BAM_DESC_CNT_TRSHLD] = { 0x0008, 0x00, 0x00, 0x00 },
149 [BAM_IRQ_SRCS] = { 0x000C, 0x00, 0x00, 0x00 },
150 [BAM_IRQ_SRCS_MSK] = { 0x0010, 0x00, 0x00, 0x00 },
151 [BAM_IRQ_SRCS_UNMASKED] = { 0x0030, 0x00, 0x00, 0x00 },
152 [BAM_IRQ_STTS] = { 0x0014, 0x00, 0x00, 0x00 },
153 [BAM_IRQ_CLR] = { 0x0018, 0x00, 0x00, 0x00 },
154 [BAM_IRQ_EN] = { 0x001C, 0x00, 0x00, 0x00 },
155 [BAM_CNFG_BITS] = { 0x007C, 0x00, 0x00, 0x00 },
156 [BAM_IRQ_SRCS_EE] = { 0x0800, 0x00, 0x00, 0x80 },
157 [BAM_IRQ_SRCS_MSK_EE] = { 0x0804, 0x00, 0x00, 0x80 },
158 [BAM_P_CTRL] = { 0x1000, 0x1000, 0x00, 0x00 },
159 [BAM_P_RST] = { 0x1004, 0x1000, 0x00, 0x00 },
160 [BAM_P_HALT] = { 0x1008, 0x1000, 0x00, 0x00 },
161 [BAM_P_IRQ_STTS] = { 0x1010, 0x1000, 0x00, 0x00 },
162 [BAM_P_IRQ_CLR] = { 0x1014, 0x1000, 0x00, 0x00 },
163 [BAM_P_IRQ_EN] = { 0x1018, 0x1000, 0x00, 0x00 },
164 [BAM_P_EVNT_DEST_ADDR] = { 0x182C, 0x00, 0x1000, 0x00 },
165 [BAM_P_EVNT_REG] = { 0x1818, 0x00, 0x1000, 0x00 },
166 [BAM_P_SW_OFSTS] = { 0x1800, 0x00, 0x1000, 0x00 },
167 [BAM_P_DATA_FIFO_ADDR] = { 0x1824, 0x00, 0x1000, 0x00 },
168 [BAM_P_DESC_FIFO_ADDR] = { 0x181C, 0x00, 0x1000, 0x00 },
169 [BAM_P_EVNT_GEN_TRSHLD] = { 0x1828, 0x00, 0x1000, 0x00 },
170 [BAM_P_FIFO_SIZES] = { 0x1820, 0x00, 0x1000, 0x00 },
171 };
172
173 static const struct reg_offset_data bam_v1_7_reg_info[] = {
174 [BAM_CTRL] = { 0x00000, 0x00, 0x00, 0x00 },
175 [BAM_REVISION] = { 0x01000, 0x00, 0x00, 0x00 },
176 [BAM_NUM_PIPES] = { 0x01008, 0x00, 0x00, 0x00 },
177 [BAM_DESC_CNT_TRSHLD] = { 0x00008, 0x00, 0x00, 0x00 },
178 [BAM_IRQ_SRCS] = { 0x03010, 0x00, 0x00, 0x00 },
179 [BAM_IRQ_SRCS_MSK] = { 0x03014, 0x00, 0x00, 0x00 },
180 [BAM_IRQ_SRCS_UNMASKED] = { 0x03018, 0x00, 0x00, 0x00 },
181 [BAM_IRQ_STTS] = { 0x00014, 0x00, 0x00, 0x00 },
182 [BAM_IRQ_CLR] = { 0x00018, 0x00, 0x00, 0x00 },
183 [BAM_IRQ_EN] = { 0x0001C, 0x00, 0x00, 0x00 },
184 [BAM_CNFG_BITS] = { 0x0007C, 0x00, 0x00, 0x00 },
185 [BAM_IRQ_SRCS_EE] = { 0x03000, 0x00, 0x00, 0x1000 },
186 [BAM_IRQ_SRCS_MSK_EE] = { 0x03004, 0x00, 0x00, 0x1000 },
187 [BAM_P_CTRL] = { 0x13000, 0x1000, 0x00, 0x00 },
188 [BAM_P_RST] = { 0x13004, 0x1000, 0x00, 0x00 },
189 [BAM_P_HALT] = { 0x13008, 0x1000, 0x00, 0x00 },
190 [BAM_P_IRQ_STTS] = { 0x13010, 0x1000, 0x00, 0x00 },
191 [BAM_P_IRQ_CLR] = { 0x13014, 0x1000, 0x00, 0x00 },
192 [BAM_P_IRQ_EN] = { 0x13018, 0x1000, 0x00, 0x00 },
193 [BAM_P_EVNT_DEST_ADDR] = { 0x1382C, 0x00, 0x1000, 0x00 },
194 [BAM_P_EVNT_REG] = { 0x13818, 0x00, 0x1000, 0x00 },
195 [BAM_P_SW_OFSTS] = { 0x13800, 0x00, 0x1000, 0x00 },
196 [BAM_P_DATA_FIFO_ADDR] = { 0x13824, 0x00, 0x1000, 0x00 },
197 [BAM_P_DESC_FIFO_ADDR] = { 0x1381C, 0x00, 0x1000, 0x00 },
198 [BAM_P_EVNT_GEN_TRSHLD] = { 0x13828, 0x00, 0x1000, 0x00 },
199 [BAM_P_FIFO_SIZES] = { 0x13820, 0x00, 0x1000, 0x00 },
200 };
201
202 /* BAM CTRL */
203 #define BAM_SW_RST BIT(0)
204 #define BAM_EN BIT(1)
205 #define BAM_EN_ACCUM BIT(4)
206 #define BAM_TESTBUS_SEL_SHIFT 5
207 #define BAM_TESTBUS_SEL_MASK 0x3F
208 #define BAM_DESC_CACHE_SEL_SHIFT 13
209 #define BAM_DESC_CACHE_SEL_MASK 0x3
210 #define BAM_CACHED_DESC_STORE BIT(15)
211 #define IBC_DISABLE BIT(16)
212
213 /* BAM REVISION */
214 #define REVISION_SHIFT 0
215 #define REVISION_MASK 0xFF
216 #define NUM_EES_SHIFT 8
217 #define NUM_EES_MASK 0xF
218 #define CE_BUFFER_SIZE BIT(13)
219 #define AXI_ACTIVE BIT(14)
220 #define USE_VMIDMT BIT(15)
221 #define SECURED BIT(16)
222 #define BAM_HAS_NO_BYPASS BIT(17)
223 #define HIGH_FREQUENCY_BAM BIT(18)
224 #define INACTIV_TMRS_EXST BIT(19)
225 #define NUM_INACTIV_TMRS BIT(20)
226 #define DESC_CACHE_DEPTH_SHIFT 21
227 #define DESC_CACHE_DEPTH_1 (0 << DESC_CACHE_DEPTH_SHIFT)
228 #define DESC_CACHE_DEPTH_2 (1 << DESC_CACHE_DEPTH_SHIFT)
229 #define DESC_CACHE_DEPTH_3 (2 << DESC_CACHE_DEPTH_SHIFT)
230 #define DESC_CACHE_DEPTH_4 (3 << DESC_CACHE_DEPTH_SHIFT)
231 #define CMD_DESC_EN BIT(23)
232 #define INACTIV_TMR_BASE_SHIFT 24
233 #define INACTIV_TMR_BASE_MASK 0xFF
234
235 /* BAM NUM PIPES */
236 #define BAM_NUM_PIPES_SHIFT 0
237 #define BAM_NUM_PIPES_MASK 0xFF
238 #define PERIPH_NON_PIPE_GRP_SHIFT 16
239 #define PERIPH_NON_PIP_GRP_MASK 0xFF
240 #define BAM_NON_PIPE_GRP_SHIFT 24
241 #define BAM_NON_PIPE_GRP_MASK 0xFF
242
243 /* BAM CNFG BITS */
244 #define BAM_PIPE_CNFG BIT(2)
245 #define BAM_FULL_PIPE BIT(11)
246 #define BAM_NO_EXT_P_RST BIT(12)
247 #define BAM_IBC_DISABLE BIT(13)
248 #define BAM_SB_CLK_REQ BIT(14)
249 #define BAM_PSM_CSW_REQ BIT(15)
250 #define BAM_PSM_P_RES BIT(16)
251 #define BAM_AU_P_RES BIT(17)
252 #define BAM_SI_P_RES BIT(18)
253 #define BAM_WB_P_RES BIT(19)
254 #define BAM_WB_BLK_CSW BIT(20)
255 #define BAM_WB_CSW_ACK_IDL BIT(21)
256 #define BAM_WB_RETR_SVPNT BIT(22)
257 #define BAM_WB_DSC_AVL_P_RST BIT(23)
258 #define BAM_REG_P_EN BIT(24)
259 #define BAM_PSM_P_HD_DATA BIT(25)
260 #define BAM_AU_ACCUMED BIT(26)
261 #define BAM_CMD_ENABLE BIT(27)
262
263 #define BAM_CNFG_BITS_DEFAULT (BAM_PIPE_CNFG | \
264 BAM_NO_EXT_P_RST | \
265 BAM_IBC_DISABLE | \
266 BAM_SB_CLK_REQ | \
267 BAM_PSM_CSW_REQ | \
268 BAM_PSM_P_RES | \
269 BAM_AU_P_RES | \
270 BAM_SI_P_RES | \
271 BAM_WB_P_RES | \
272 BAM_WB_BLK_CSW | \
273 BAM_WB_CSW_ACK_IDL | \
274 BAM_WB_RETR_SVPNT | \
275 BAM_WB_DSC_AVL_P_RST | \
276 BAM_REG_P_EN | \
277 BAM_PSM_P_HD_DATA | \
278 BAM_AU_ACCUMED | \
279 BAM_CMD_ENABLE)
280
281 /* PIPE CTRL */
282 #define P_EN BIT(1)
283 #define P_DIRECTION BIT(3)
284 #define P_SYS_STRM BIT(4)
285 #define P_SYS_MODE BIT(5)
286 #define P_AUTO_EOB BIT(6)
287 #define P_AUTO_EOB_SEL_SHIFT 7
288 #define P_AUTO_EOB_SEL_512 (0 << P_AUTO_EOB_SEL_SHIFT)
289 #define P_AUTO_EOB_SEL_256 (1 << P_AUTO_EOB_SEL_SHIFT)
290 #define P_AUTO_EOB_SEL_128 (2 << P_AUTO_EOB_SEL_SHIFT)
291 #define P_AUTO_EOB_SEL_64 (3 << P_AUTO_EOB_SEL_SHIFT)
292 #define P_PREFETCH_LIMIT_SHIFT 9
293 #define P_PREFETCH_LIMIT_32 (0 << P_PREFETCH_LIMIT_SHIFT)
294 #define P_PREFETCH_LIMIT_16 (1 << P_PREFETCH_LIMIT_SHIFT)
295 #define P_PREFETCH_LIMIT_4 (2 << P_PREFETCH_LIMIT_SHIFT)
296 #define P_WRITE_NWD BIT(11)
297 #define P_LOCK_GROUP_SHIFT 16
298 #define P_LOCK_GROUP_MASK 0x1F
299
300 /* BAM_DESC_CNT_TRSHLD */
301 #define CNT_TRSHLD 0xffff
302 #define DEFAULT_CNT_THRSHLD 0x4
303
304 /* BAM_IRQ_SRCS */
305 #define BAM_IRQ BIT(31)
306 #define P_IRQ 0x7fffffff
307
308 /* BAM_IRQ_SRCS_MSK */
309 #define BAM_IRQ_MSK BAM_IRQ
310 #define P_IRQ_MSK P_IRQ
311
312 /* BAM_IRQ_STTS */
313 #define BAM_TIMER_IRQ BIT(4)
314 #define BAM_EMPTY_IRQ BIT(3)
315 #define BAM_ERROR_IRQ BIT(2)
316 #define BAM_HRESP_ERR_IRQ BIT(1)
317
318 /* BAM_IRQ_CLR */
319 #define BAM_TIMER_CLR BIT(4)
320 #define BAM_EMPTY_CLR BIT(3)
321 #define BAM_ERROR_CLR BIT(2)
322 #define BAM_HRESP_ERR_CLR BIT(1)
323
324 /* BAM_IRQ_EN */
325 #define BAM_TIMER_EN BIT(4)
326 #define BAM_EMPTY_EN BIT(3)
327 #define BAM_ERROR_EN BIT(2)
328 #define BAM_HRESP_ERR_EN BIT(1)
329
330 /* BAM_P_IRQ_EN */
331 #define P_PRCSD_DESC_EN BIT(0)
332 #define P_TIMER_EN BIT(1)
333 #define P_WAKE_EN BIT(2)
334 #define P_OUT_OF_DESC_EN BIT(3)
335 #define P_ERR_EN BIT(4)
336 #define P_TRNSFR_END_EN BIT(5)
337 #define P_DEFAULT_IRQS_EN (P_PRCSD_DESC_EN | P_ERR_EN | P_TRNSFR_END_EN)
338
339 /* BAM_P_SW_OFSTS */
340 #define P_SW_OFSTS_MASK 0xffff
341
342 #define BAM_DESC_FIFO_SIZE SZ_32K
343 #define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1)
344 #define BAM_FIFO_SIZE (SZ_32K - 8)
345 #define IS_BUSY(chan) (CIRC_SPACE(bchan->tail, bchan->head,\
346 MAX_DESCRIPTORS + 1) == 0)
347
348 struct bam_chan {
349 struct virt_dma_chan vc;
350
351 struct bam_device *bdev;
352
353 /* configuration from device tree */
354 u32 id;
355
356 /* runtime configuration */
357 struct dma_slave_config slave;
358
359 /* fifo storage */
360 struct bam_desc_hw *fifo_virt;
361 dma_addr_t fifo_phys;
362
363 /* fifo markers */
364 unsigned short head; /* start of active descriptor entries */
365 unsigned short tail; /* end of active descriptor entries */
366
367 unsigned int initialized; /* is the channel hw initialized? */
368 unsigned int paused; /* is the channel paused? */
369 unsigned int reconfigure; /* new slave config? */
370 /* list of descriptors currently processed */
371 struct list_head desc_list;
372
373 struct list_head node;
374 };
375
to_bam_chan(struct dma_chan * common)376 static inline struct bam_chan *to_bam_chan(struct dma_chan *common)
377 {
378 return container_of(common, struct bam_chan, vc.chan);
379 }
380
381 struct bam_device {
382 void __iomem *regs;
383 struct device *dev;
384 struct dma_device common;
385 struct bam_chan *channels;
386 u32 num_channels;
387 u32 num_ees;
388
389 /* execution environment ID, from DT */
390 u32 ee;
391 bool controlled_remotely;
392 bool powered_remotely;
393 u32 active_channels;
394
395 const struct reg_offset_data *layout;
396
397 struct clk *bamclk;
398 int irq;
399
400 /* dma start transaction tasklet */
401 struct tasklet_struct task;
402 };
403
404 /**
405 * bam_addr - returns BAM register address
406 * @bdev: bam device
407 * @pipe: pipe instance (ignored when register doesn't have multiple instances)
408 * @reg: register enum
409 */
bam_addr(struct bam_device * bdev,u32 pipe,enum bam_reg reg)410 static inline void __iomem *bam_addr(struct bam_device *bdev, u32 pipe,
411 enum bam_reg reg)
412 {
413 const struct reg_offset_data r = bdev->layout[reg];
414
415 return bdev->regs + r.base_offset +
416 r.pipe_mult * pipe +
417 r.evnt_mult * pipe +
418 r.ee_mult * bdev->ee;
419 }
420
421 /**
422 * bam_reset() - reset and initialize BAM registers
423 * @bdev: bam device
424 */
bam_reset(struct bam_device * bdev)425 static void bam_reset(struct bam_device *bdev)
426 {
427 u32 val;
428
429 /* s/w reset bam */
430 /* after reset all pipes are disabled and idle */
431 val = readl_relaxed(bam_addr(bdev, 0, BAM_CTRL));
432 val |= BAM_SW_RST;
433 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
434 val &= ~BAM_SW_RST;
435 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
436
437 /* make sure previous stores are visible before enabling BAM */
438 wmb();
439
440 /* enable bam */
441 val |= BAM_EN;
442 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
443
444 /* set descriptor threshold, start with 4 bytes */
445 writel_relaxed(DEFAULT_CNT_THRSHLD,
446 bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
447
448 /* Enable default set of h/w workarounds, ie all except BAM_FULL_PIPE */
449 writel_relaxed(BAM_CNFG_BITS_DEFAULT, bam_addr(bdev, 0, BAM_CNFG_BITS));
450
451 /* enable irqs for errors */
452 writel_relaxed(BAM_ERROR_EN | BAM_HRESP_ERR_EN,
453 bam_addr(bdev, 0, BAM_IRQ_EN));
454
455 /* unmask global bam interrupt */
456 writel_relaxed(BAM_IRQ_MSK, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
457 }
458
459 /**
460 * bam_reset_channel - Reset individual BAM DMA channel
461 * @bchan: bam channel
462 *
463 * This function resets a specific BAM channel
464 */
bam_reset_channel(struct bam_chan * bchan)465 static void bam_reset_channel(struct bam_chan *bchan)
466 {
467 struct bam_device *bdev = bchan->bdev;
468
469 lockdep_assert_held(&bchan->vc.lock);
470
471 /* reset channel */
472 writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_RST));
473 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_RST));
474
475 /* don't allow cpu to reorder BAM register accesses done after this */
476 wmb();
477
478 /* make sure hw is initialized when channel is used the first time */
479 bchan->initialized = 0;
480 }
481
482 /**
483 * bam_chan_init_hw - Initialize channel hardware
484 * @bchan: bam channel
485 * @dir: DMA transfer direction
486 *
487 * This function resets and initializes the BAM channel
488 */
bam_chan_init_hw(struct bam_chan * bchan,enum dma_transfer_direction dir)489 static void bam_chan_init_hw(struct bam_chan *bchan,
490 enum dma_transfer_direction dir)
491 {
492 struct bam_device *bdev = bchan->bdev;
493 u32 val;
494
495 /* Reset the channel to clear internal state of the FIFO */
496 bam_reset_channel(bchan);
497
498 /*
499 * write out 8 byte aligned address. We have enough space for this
500 * because we allocated 1 more descriptor (8 bytes) than we can use
501 */
502 writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)),
503 bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR));
504 writel_relaxed(BAM_FIFO_SIZE,
505 bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES));
506
507 /* enable the per pipe interrupts, enable EOT, ERR, and INT irqs */
508 writel_relaxed(P_DEFAULT_IRQS_EN,
509 bam_addr(bdev, bchan->id, BAM_P_IRQ_EN));
510
511 /* unmask the specific pipe and EE combo */
512 val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
513 val |= BIT(bchan->id);
514 writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
515
516 /* don't allow cpu to reorder the channel enable done below */
517 wmb();
518
519 /* set fixed direction and mode, then enable channel */
520 val = P_EN | P_SYS_MODE;
521 if (dir == DMA_DEV_TO_MEM)
522 val |= P_DIRECTION;
523
524 writel_relaxed(val, bam_addr(bdev, bchan->id, BAM_P_CTRL));
525
526 bchan->initialized = 1;
527
528 /* init FIFO pointers */
529 bchan->head = 0;
530 bchan->tail = 0;
531 }
532
533 /**
534 * bam_alloc_chan - Allocate channel resources for DMA channel.
535 * @chan: specified channel
536 *
537 * This function allocates the FIFO descriptor memory
538 */
bam_alloc_chan(struct dma_chan * chan)539 static int bam_alloc_chan(struct dma_chan *chan)
540 {
541 struct bam_chan *bchan = to_bam_chan(chan);
542 struct bam_device *bdev = bchan->bdev;
543
544 if (bchan->fifo_virt)
545 return 0;
546
547 /* allocate FIFO descriptor space, but only if necessary */
548 bchan->fifo_virt = dma_alloc_wc(bdev->dev, BAM_DESC_FIFO_SIZE,
549 &bchan->fifo_phys, GFP_KERNEL);
550
551 if (!bchan->fifo_virt) {
552 dev_err(bdev->dev, "Failed to allocate desc fifo\n");
553 return -ENOMEM;
554 }
555
556 if (bdev->active_channels++ == 0 && bdev->powered_remotely)
557 bam_reset(bdev);
558
559 return 0;
560 }
561
562 /**
563 * bam_free_chan - Frees dma resources associated with specific channel
564 * @chan: specified channel
565 *
566 * Free the allocated fifo descriptor memory and channel resources
567 *
568 */
bam_free_chan(struct dma_chan * chan)569 static void bam_free_chan(struct dma_chan *chan)
570 {
571 struct bam_chan *bchan = to_bam_chan(chan);
572 struct bam_device *bdev = bchan->bdev;
573 u32 val;
574 int ret;
575
576 ret = pm_runtime_get_sync(bdev->dev);
577 if (ret < 0)
578 return;
579
580 vchan_free_chan_resources(to_virt_chan(chan));
581
582 if (!list_empty(&bchan->desc_list)) {
583 dev_err(bchan->bdev->dev, "Cannot free busy channel\n");
584 goto err;
585 }
586
587 scoped_guard(spinlock_irqsave, &bchan->vc.lock)
588 bam_reset_channel(bchan);
589
590 dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE, bchan->fifo_virt,
591 bchan->fifo_phys);
592 bchan->fifo_virt = NULL;
593
594 /* mask irq for pipe/channel */
595 val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
596 val &= ~BIT(bchan->id);
597 writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
598
599 /* disable irq */
600 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_IRQ_EN));
601
602 if (--bdev->active_channels == 0 && bdev->powered_remotely) {
603 /* s/w reset bam */
604 val = readl_relaxed(bam_addr(bdev, 0, BAM_CTRL));
605 val |= BAM_SW_RST;
606 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
607 }
608
609 err:
610 pm_runtime_mark_last_busy(bdev->dev);
611 pm_runtime_put_autosuspend(bdev->dev);
612 }
613
614 /**
615 * bam_slave_config - set slave configuration for channel
616 * @chan: dma channel
617 * @cfg: slave configuration
618 *
619 * Sets slave configuration for channel
620 *
621 */
bam_slave_config(struct dma_chan * chan,struct dma_slave_config * cfg)622 static int bam_slave_config(struct dma_chan *chan,
623 struct dma_slave_config *cfg)
624 {
625 struct bam_chan *bchan = to_bam_chan(chan);
626
627 guard(spinlock_irqsave)(&bchan->vc.lock);
628
629 memcpy(&bchan->slave, cfg, sizeof(*cfg));
630 bchan->reconfigure = 1;
631
632 return 0;
633 }
634
635 /**
636 * bam_prep_slave_sg - Prep slave sg transaction
637 *
638 * @chan: dma channel
639 * @sgl: scatter gather list
640 * @sg_len: length of sg
641 * @direction: DMA transfer direction
642 * @flags: DMA flags
643 * @context: transfer context (unused)
644 */
bam_prep_slave_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,enum dma_transfer_direction direction,unsigned long flags,void * context)645 static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan,
646 struct scatterlist *sgl, unsigned int sg_len,
647 enum dma_transfer_direction direction, unsigned long flags,
648 void *context)
649 {
650 struct bam_chan *bchan = to_bam_chan(chan);
651 struct bam_device *bdev = bchan->bdev;
652 struct bam_async_desc *async_desc;
653 struct scatterlist *sg;
654 u32 i;
655 struct bam_desc_hw *desc;
656 unsigned int num_alloc;
657
658 if (!is_slave_direction(direction)) {
659 dev_err(bdev->dev, "invalid dma direction\n");
660 return NULL;
661 }
662
663 /* allocate enough room to accommodate the number of entries */
664 num_alloc = sg_nents_for_dma(sgl, sg_len, BAM_FIFO_SIZE);
665 async_desc = kzalloc_flex(*async_desc, desc, num_alloc, GFP_NOWAIT);
666 if (!async_desc)
667 return NULL;
668
669 if (flags & DMA_PREP_FENCE)
670 async_desc->flags |= DESC_FLAG_NWD;
671
672 if (flags & DMA_PREP_INTERRUPT)
673 async_desc->flags |= DESC_FLAG_EOT;
674
675 async_desc->num_desc = num_alloc;
676 async_desc->curr_desc = async_desc->desc;
677 async_desc->dir = direction;
678
679 /* fill in temporary descriptors */
680 desc = async_desc->desc;
681 for_each_sg(sgl, sg, sg_len, i) {
682 unsigned int remainder = sg_dma_len(sg);
683 unsigned int curr_offset = 0;
684
685 do {
686 if (flags & DMA_PREP_CMD)
687 desc->flags |= cpu_to_le16(DESC_FLAG_CMD);
688
689 desc->addr = cpu_to_le32(sg_dma_address(sg) +
690 curr_offset);
691
692 if (remainder > BAM_FIFO_SIZE) {
693 desc->size = cpu_to_le16(BAM_FIFO_SIZE);
694 remainder -= BAM_FIFO_SIZE;
695 curr_offset += BAM_FIFO_SIZE;
696 } else {
697 desc->size = cpu_to_le16(remainder);
698 remainder = 0;
699 }
700
701 async_desc->length += le16_to_cpu(desc->size);
702 desc++;
703 } while (remainder > 0);
704 }
705
706 return vchan_tx_prep(&bchan->vc, &async_desc->vd, flags);
707 }
708
709 /**
710 * bam_dma_terminate_all - terminate all transactions on a channel
711 * @chan: bam dma channel
712 *
713 * Dequeues and frees all transactions
714 * No callbacks are done
715 *
716 */
bam_dma_terminate_all(struct dma_chan * chan)717 static int bam_dma_terminate_all(struct dma_chan *chan)
718 {
719 struct bam_chan *bchan = to_bam_chan(chan);
720 struct bam_async_desc *async_desc, *tmp;
721 LIST_HEAD(head);
722
723 /* remove all transactions, including active transaction */
724 scoped_guard(spinlock_irqsave, &bchan->vc.lock) {
725 /*
726 * If we have transactions queued, then some might be committed to the
727 * hardware in the desc fifo. The only way to reset the desc fifo is
728 * to do a hardware reset (either by pipe or the entire block).
729 * bam_chan_init_hw() will trigger a pipe reset, and also reinit the
730 * pipe. If the pipe is left disabled (default state after pipe reset)
731 * and is accessed by a connected hardware engine, a fatal error in
732 * the BAM will occur. There is a small window where this could happen
733 * with bam_chan_init_hw(), but it is assumed that the caller has
734 * stopped activity on any attached hardware engine. Make sure to do
735 * this first so that the BAM hardware doesn't cause memory corruption
736 * by accessing freed resources.
737 */
738 if (!list_empty(&bchan->desc_list)) {
739 async_desc = list_first_entry(&bchan->desc_list,
740 struct bam_async_desc, desc_node);
741 bam_chan_init_hw(bchan, async_desc->dir);
742 }
743
744 list_for_each_entry_safe(async_desc, tmp,
745 &bchan->desc_list, desc_node) {
746 list_add(&async_desc->vd.node, &bchan->vc.desc_issued);
747 list_del(&async_desc->desc_node);
748 }
749
750 vchan_get_all_descriptors(&bchan->vc, &head);
751 }
752
753 vchan_dma_desc_free_list(&bchan->vc, &head);
754
755 return 0;
756 }
757
758 /**
759 * bam_pause - Pause DMA channel
760 * @chan: dma channel
761 *
762 */
bam_pause(struct dma_chan * chan)763 static int bam_pause(struct dma_chan *chan)
764 {
765 struct bam_chan *bchan = to_bam_chan(chan);
766 struct bam_device *bdev = bchan->bdev;
767 int ret;
768
769 ret = pm_runtime_get_sync(bdev->dev);
770 if (ret < 0)
771 return ret;
772
773 scoped_guard(spinlock_irqsave, &bchan->vc.lock) {
774 writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_HALT));
775 bchan->paused = 1;
776 }
777 pm_runtime_mark_last_busy(bdev->dev);
778 pm_runtime_put_autosuspend(bdev->dev);
779
780 return 0;
781 }
782
783 /**
784 * bam_resume - Resume DMA channel operations
785 * @chan: dma channel
786 *
787 */
bam_resume(struct dma_chan * chan)788 static int bam_resume(struct dma_chan *chan)
789 {
790 struct bam_chan *bchan = to_bam_chan(chan);
791 struct bam_device *bdev = bchan->bdev;
792 int ret;
793
794 ret = pm_runtime_get_sync(bdev->dev);
795 if (ret < 0)
796 return ret;
797
798 scoped_guard(spinlock_irqsave, &bchan->vc.lock) {
799 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_HALT));
800 bchan->paused = 0;
801 }
802 pm_runtime_mark_last_busy(bdev->dev);
803 pm_runtime_put_autosuspend(bdev->dev);
804
805 return 0;
806 }
807
808 /**
809 * process_channel_irqs - processes the channel interrupts
810 * @bdev: bam controller
811 *
812 * This function processes the channel interrupts
813 *
814 */
process_channel_irqs(struct bam_device * bdev)815 static u32 process_channel_irqs(struct bam_device *bdev)
816 {
817 u32 i, srcs, pipe_stts, offset, avail;
818 struct bam_async_desc *async_desc, *tmp;
819
820 srcs = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_EE));
821
822 /* return early if no pipe/channel interrupts are present */
823 if (!(srcs & P_IRQ))
824 return srcs;
825
826 for (i = 0; i < bdev->num_channels; i++) {
827 struct bam_chan *bchan = &bdev->channels[i];
828
829 if (!(srcs & BIT(i)))
830 continue;
831
832 /* clear pipe irq */
833 pipe_stts = readl_relaxed(bam_addr(bdev, i, BAM_P_IRQ_STTS));
834
835 writel_relaxed(pipe_stts, bam_addr(bdev, i, BAM_P_IRQ_CLR));
836
837 guard(spinlock_irqsave)(&bchan->vc.lock);
838
839 offset = readl_relaxed(bam_addr(bdev, i, BAM_P_SW_OFSTS)) &
840 P_SW_OFSTS_MASK;
841 offset /= sizeof(struct bam_desc_hw);
842
843 /* Number of bytes available to read */
844 avail = CIRC_CNT(offset, bchan->head, MAX_DESCRIPTORS + 1);
845
846 if (offset < bchan->head)
847 avail--;
848
849 list_for_each_entry_safe(async_desc, tmp,
850 &bchan->desc_list, desc_node) {
851 /* Not enough data to read */
852 if (avail < async_desc->xfer_len)
853 break;
854
855 /* manage FIFO */
856 bchan->head += async_desc->xfer_len;
857 bchan->head %= MAX_DESCRIPTORS;
858
859 async_desc->num_desc -= async_desc->xfer_len;
860 async_desc->curr_desc += async_desc->xfer_len;
861 avail -= async_desc->xfer_len;
862
863 /*
864 * if complete, process cookie. Otherwise
865 * push back to front of desc_issued so that
866 * it gets restarted by the tasklet
867 */
868 if (!async_desc->num_desc) {
869 vchan_cookie_complete(&async_desc->vd);
870 } else {
871 list_add(&async_desc->vd.node,
872 &bchan->vc.desc_issued);
873 }
874 list_del(&async_desc->desc_node);
875 }
876 }
877
878 return srcs;
879 }
880
881 /**
882 * bam_dma_irq - irq handler for bam controller
883 * @irq: IRQ of interrupt
884 * @data: callback data
885 *
886 * IRQ handler for the bam controller
887 */
bam_dma_irq(int irq,void * data)888 static irqreturn_t bam_dma_irq(int irq, void *data)
889 {
890 struct bam_device *bdev = data;
891 u32 clr_mask = 0, srcs = 0;
892 int ret;
893
894 srcs |= process_channel_irqs(bdev);
895
896 /* kick off tasklet to start next dma transfer */
897 if (srcs & P_IRQ)
898 tasklet_schedule(&bdev->task);
899
900 ret = pm_runtime_get_sync(bdev->dev);
901 if (ret < 0)
902 return IRQ_NONE;
903
904 if (srcs & BAM_IRQ) {
905 clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS));
906
907 /*
908 * don't allow reorder of the various accesses to the BAM
909 * registers
910 */
911 mb();
912
913 writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR));
914 }
915
916 pm_runtime_mark_last_busy(bdev->dev);
917 pm_runtime_put_autosuspend(bdev->dev);
918
919 return IRQ_HANDLED;
920 }
921
922 /**
923 * bam_tx_status - returns status of transaction
924 * @chan: dma channel
925 * @cookie: transaction cookie
926 * @txstate: DMA transaction state
927 *
928 * Return status of dma transaction
929 */
bam_tx_status(struct dma_chan * chan,dma_cookie_t cookie,struct dma_tx_state * txstate)930 static enum dma_status bam_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
931 struct dma_tx_state *txstate)
932 {
933 struct bam_chan *bchan = to_bam_chan(chan);
934 struct bam_async_desc *async_desc;
935 struct virt_dma_desc *vd;
936 int ret;
937 size_t residue = 0;
938 unsigned int i;
939
940 ret = dma_cookie_status(chan, cookie, txstate);
941 if (ret == DMA_COMPLETE)
942 return ret;
943
944 if (!txstate)
945 return bchan->paused ? DMA_PAUSED : ret;
946
947 scoped_guard(spinlock_irqsave, &bchan->vc.lock) {
948 vd = vchan_find_desc(&bchan->vc, cookie);
949 if (vd) {
950 residue = container_of(vd, struct bam_async_desc, vd)->length;
951 } else {
952 list_for_each_entry(async_desc, &bchan->desc_list, desc_node) {
953 if (async_desc->vd.tx.cookie != cookie)
954 continue;
955
956 for (i = 0; i < async_desc->num_desc; i++)
957 residue += le16_to_cpu(
958 async_desc->curr_desc[i].size);
959 }
960 }
961 }
962
963 dma_set_residue(txstate, residue);
964
965 if (ret == DMA_IN_PROGRESS && bchan->paused)
966 ret = DMA_PAUSED;
967
968 return ret;
969 }
970
971 /**
972 * bam_apply_new_config
973 * @bchan: bam dma channel
974 * @dir: DMA direction
975 */
bam_apply_new_config(struct bam_chan * bchan,enum dma_transfer_direction dir)976 static void bam_apply_new_config(struct bam_chan *bchan,
977 enum dma_transfer_direction dir)
978 {
979 struct bam_device *bdev = bchan->bdev;
980 u32 maxburst;
981
982 if (!bdev->controlled_remotely) {
983 if (dir == DMA_DEV_TO_MEM)
984 maxburst = bchan->slave.src_maxburst;
985 else
986 maxburst = bchan->slave.dst_maxburst;
987
988 writel_relaxed(maxburst,
989 bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
990 }
991
992 bchan->reconfigure = 0;
993 }
994
995 /**
996 * bam_start_dma - start next transaction
997 * @bchan: bam dma channel
998 */
bam_start_dma(struct bam_chan * bchan)999 static void bam_start_dma(struct bam_chan *bchan)
1000 {
1001 struct virt_dma_desc *vd = vchan_next_desc(&bchan->vc);
1002 struct bam_device *bdev = bchan->bdev;
1003 struct bam_async_desc *async_desc = NULL;
1004 struct bam_desc_hw *desc;
1005 struct bam_desc_hw *fifo = PTR_ALIGN(bchan->fifo_virt,
1006 sizeof(struct bam_desc_hw));
1007 int ret;
1008 unsigned int avail;
1009 struct dmaengine_desc_callback cb;
1010
1011 lockdep_assert_held(&bchan->vc.lock);
1012
1013 if (!vd)
1014 return;
1015
1016 ret = pm_runtime_get_sync(bdev->dev);
1017 if (ret < 0)
1018 return;
1019
1020 while (vd && !IS_BUSY(bchan)) {
1021 list_del(&vd->node);
1022
1023 async_desc = container_of(vd, struct bam_async_desc, vd);
1024
1025 /* on first use, initialize the channel hardware */
1026 if (!bchan->initialized)
1027 bam_chan_init_hw(bchan, async_desc->dir);
1028
1029 /* apply new slave config changes, if necessary */
1030 if (bchan->reconfigure)
1031 bam_apply_new_config(bchan, async_desc->dir);
1032
1033 desc = async_desc->curr_desc;
1034 avail = CIRC_SPACE(bchan->tail, bchan->head,
1035 MAX_DESCRIPTORS + 1);
1036
1037 if (async_desc->num_desc > avail)
1038 async_desc->xfer_len = avail;
1039 else
1040 async_desc->xfer_len = async_desc->num_desc;
1041
1042 /* set any special flags on the last descriptor */
1043 if (async_desc->num_desc == async_desc->xfer_len)
1044 desc[async_desc->xfer_len - 1].flags |=
1045 cpu_to_le16(async_desc->flags);
1046
1047 vd = vchan_next_desc(&bchan->vc);
1048
1049 dmaengine_desc_get_callback(&async_desc->vd.tx, &cb);
1050
1051 /*
1052 * An interrupt is generated at this desc, if
1053 * - FIFO is FULL.
1054 * - No more descriptors to add.
1055 * - If a callback completion was requested for this DESC,
1056 * In this case, BAM will deliver the completion callback
1057 * for this desc and continue processing the next desc.
1058 */
1059 if (((avail <= async_desc->xfer_len) || !vd ||
1060 dmaengine_desc_callback_valid(&cb)) &&
1061 !(async_desc->flags & DESC_FLAG_EOT))
1062 desc[async_desc->xfer_len - 1].flags |=
1063 cpu_to_le16(DESC_FLAG_INT);
1064
1065 if (bchan->tail + async_desc->xfer_len > MAX_DESCRIPTORS) {
1066 u32 partial = MAX_DESCRIPTORS - bchan->tail;
1067
1068 memcpy(&fifo[bchan->tail], desc,
1069 partial * sizeof(struct bam_desc_hw));
1070 memcpy(fifo, &desc[partial],
1071 (async_desc->xfer_len - partial) *
1072 sizeof(struct bam_desc_hw));
1073 } else {
1074 memcpy(&fifo[bchan->tail], desc,
1075 async_desc->xfer_len *
1076 sizeof(struct bam_desc_hw));
1077 }
1078
1079 bchan->tail += async_desc->xfer_len;
1080 bchan->tail %= MAX_DESCRIPTORS;
1081 list_add_tail(&async_desc->desc_node, &bchan->desc_list);
1082 }
1083
1084 /* ensure descriptor writes and dma start not reordered */
1085 wmb();
1086 writel_relaxed(bchan->tail * sizeof(struct bam_desc_hw),
1087 bam_addr(bdev, bchan->id, BAM_P_EVNT_REG));
1088
1089 pm_runtime_mark_last_busy(bdev->dev);
1090 pm_runtime_put_autosuspend(bdev->dev);
1091 }
1092
1093 /**
1094 * dma_tasklet - DMA IRQ tasklet
1095 * @t: tasklet argument (bam controller structure)
1096 *
1097 * Sets up next DMA operation and then processes all completed transactions
1098 */
dma_tasklet(struct tasklet_struct * t)1099 static void dma_tasklet(struct tasklet_struct *t)
1100 {
1101 struct bam_device *bdev = from_tasklet(bdev, t, task);
1102 struct bam_chan *bchan;
1103 unsigned int i;
1104
1105 /* go through the channels and kick off transactions */
1106 for (i = 0; i < bdev->num_channels; i++) {
1107 bchan = &bdev->channels[i];
1108
1109 guard(spinlock_irqsave)(&bchan->vc.lock);
1110
1111 if (!list_empty(&bchan->vc.desc_issued) && !IS_BUSY(bchan))
1112 bam_start_dma(bchan);
1113 }
1114
1115 }
1116
1117 /**
1118 * bam_issue_pending - starts pending transactions
1119 * @chan: dma channel
1120 *
1121 * Calls tasklet directly which in turn starts any pending transactions
1122 */
bam_issue_pending(struct dma_chan * chan)1123 static void bam_issue_pending(struct dma_chan *chan)
1124 {
1125 struct bam_chan *bchan = to_bam_chan(chan);
1126
1127 guard(spinlock_irqsave)(&bchan->vc.lock);
1128
1129 /* if work pending and idle, start a transaction */
1130 if (vchan_issue_pending(&bchan->vc) && !IS_BUSY(bchan))
1131 bam_start_dma(bchan);
1132 }
1133
1134 /**
1135 * bam_dma_free_desc - free descriptor memory
1136 * @vd: virtual descriptor
1137 *
1138 */
bam_dma_free_desc(struct virt_dma_desc * vd)1139 static void bam_dma_free_desc(struct virt_dma_desc *vd)
1140 {
1141 struct bam_async_desc *async_desc = container_of(vd,
1142 struct bam_async_desc, vd);
1143
1144 kfree(async_desc);
1145 }
1146
bam_dma_xlate(struct of_phandle_args * dma_spec,struct of_dma * of)1147 static struct dma_chan *bam_dma_xlate(struct of_phandle_args *dma_spec,
1148 struct of_dma *of)
1149 {
1150 struct bam_device *bdev = container_of(of->of_dma_data,
1151 struct bam_device, common);
1152 unsigned int request;
1153
1154 if (dma_spec->args_count != 1)
1155 return NULL;
1156
1157 request = dma_spec->args[0];
1158 if (request >= bdev->num_channels)
1159 return NULL;
1160
1161 return dma_get_slave_channel(&(bdev->channels[request].vc.chan));
1162 }
1163
1164 /**
1165 * bam_init
1166 * @bdev: bam device
1167 *
1168 * Initialization helper for global bam registers
1169 */
bam_init(struct bam_device * bdev)1170 static int bam_init(struct bam_device *bdev)
1171 {
1172 u32 val;
1173
1174 /* read revision and configuration information */
1175 if (!bdev->num_ees) {
1176 val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION));
1177 bdev->num_ees = (val >> NUM_EES_SHIFT) & NUM_EES_MASK;
1178 }
1179
1180 /* check that configured EE is within range */
1181 if (bdev->ee >= bdev->num_ees)
1182 return -EINVAL;
1183
1184 if (!bdev->num_channels) {
1185 val = readl_relaxed(bam_addr(bdev, 0, BAM_NUM_PIPES));
1186 bdev->num_channels = val & BAM_NUM_PIPES_MASK;
1187 }
1188
1189 /* Reset BAM now if fully controlled locally */
1190 if (!bdev->controlled_remotely && !bdev->powered_remotely)
1191 bam_reset(bdev);
1192
1193 return 0;
1194 }
1195
bam_channel_init(struct bam_device * bdev,struct bam_chan * bchan,u32 index)1196 static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan,
1197 u32 index)
1198 {
1199 bchan->id = index;
1200 bchan->bdev = bdev;
1201
1202 vchan_init(&bchan->vc, &bdev->common);
1203 bchan->vc.desc_free = bam_dma_free_desc;
1204 INIT_LIST_HEAD(&bchan->desc_list);
1205 }
1206
1207 static const struct of_device_id bam_of_match[] = {
1208 { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info },
1209 { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info },
1210 { .compatible = "qcom,bam-v1.7.0", .data = &bam_v1_7_reg_info },
1211 {}
1212 };
1213
1214 MODULE_DEVICE_TABLE(of, bam_of_match);
1215
bam_dma_probe(struct platform_device * pdev)1216 static int bam_dma_probe(struct platform_device *pdev)
1217 {
1218 struct bam_device *bdev;
1219 const struct of_device_id *match;
1220 int ret, i;
1221
1222 bdev = devm_kzalloc(&pdev->dev, sizeof(*bdev), GFP_KERNEL);
1223 if (!bdev)
1224 return -ENOMEM;
1225
1226 bdev->dev = &pdev->dev;
1227
1228 match = of_match_node(bam_of_match, pdev->dev.of_node);
1229 if (!match) {
1230 dev_err(&pdev->dev, "Unsupported BAM module\n");
1231 return -ENODEV;
1232 }
1233
1234 bdev->layout = match->data;
1235
1236 bdev->regs = devm_platform_ioremap_resource(pdev, 0);
1237 if (IS_ERR(bdev->regs))
1238 return PTR_ERR(bdev->regs);
1239
1240 bdev->irq = platform_get_irq(pdev, 0);
1241 if (bdev->irq < 0)
1242 return bdev->irq;
1243
1244 ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &bdev->ee);
1245 if (ret) {
1246 dev_err(bdev->dev, "Execution environment unspecified\n");
1247 return ret;
1248 }
1249
1250 bdev->controlled_remotely = of_property_read_bool(pdev->dev.of_node,
1251 "qcom,controlled-remotely");
1252 bdev->powered_remotely = of_property_read_bool(pdev->dev.of_node,
1253 "qcom,powered-remotely");
1254
1255 if (bdev->controlled_remotely || bdev->powered_remotely)
1256 bdev->bamclk = devm_clk_get_optional(bdev->dev, "bam_clk");
1257 else
1258 bdev->bamclk = devm_clk_get(bdev->dev, "bam_clk");
1259
1260 if (IS_ERR(bdev->bamclk))
1261 return PTR_ERR(bdev->bamclk);
1262
1263 if (!bdev->bamclk) {
1264 ret = of_property_read_u32(pdev->dev.of_node, "num-channels",
1265 &bdev->num_channels);
1266 if (ret) {
1267 dev_err(bdev->dev, "num-channels unspecified in dt\n");
1268 return ret;
1269 }
1270
1271 ret = of_property_read_u32(pdev->dev.of_node, "qcom,num-ees",
1272 &bdev->num_ees);
1273 if (ret) {
1274 dev_err(bdev->dev, "num-ees unspecified in dt\n");
1275 return ret;
1276 }
1277 }
1278
1279 ret = clk_prepare_enable(bdev->bamclk);
1280 if (ret) {
1281 dev_err(bdev->dev, "failed to prepare/enable clock\n");
1282 return ret;
1283 }
1284
1285 ret = bam_init(bdev);
1286 if (ret)
1287 goto err_disable_clk;
1288
1289 tasklet_setup(&bdev->task, dma_tasklet);
1290
1291 bdev->channels = devm_kcalloc(bdev->dev, bdev->num_channels,
1292 sizeof(*bdev->channels), GFP_KERNEL);
1293
1294 if (!bdev->channels) {
1295 ret = -ENOMEM;
1296 goto err_tasklet_kill;
1297 }
1298
1299 /* allocate and initialize channels */
1300 INIT_LIST_HEAD(&bdev->common.channels);
1301
1302 for (i = 0; i < bdev->num_channels; i++)
1303 bam_channel_init(bdev, &bdev->channels[i], i);
1304
1305 ret = devm_request_irq(bdev->dev, bdev->irq, bam_dma_irq,
1306 IRQF_TRIGGER_HIGH, "bam_dma", bdev);
1307 if (ret)
1308 goto err_bam_channel_exit;
1309
1310 /* set max dma segment size */
1311 bdev->common.dev = bdev->dev;
1312 dma_set_max_seg_size(bdev->common.dev, BAM_FIFO_SIZE);
1313
1314 platform_set_drvdata(pdev, bdev);
1315
1316 /* set capabilities */
1317 dma_cap_zero(bdev->common.cap_mask);
1318 dma_cap_set(DMA_SLAVE, bdev->common.cap_mask);
1319
1320 /* initialize dmaengine apis */
1321 bdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1322 bdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
1323 bdev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
1324 bdev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
1325 bdev->common.device_alloc_chan_resources = bam_alloc_chan;
1326 bdev->common.device_free_chan_resources = bam_free_chan;
1327 bdev->common.device_prep_slave_sg = bam_prep_slave_sg;
1328 bdev->common.device_config = bam_slave_config;
1329 bdev->common.device_pause = bam_pause;
1330 bdev->common.device_resume = bam_resume;
1331 bdev->common.device_terminate_all = bam_dma_terminate_all;
1332 bdev->common.device_issue_pending = bam_issue_pending;
1333 bdev->common.device_tx_status = bam_tx_status;
1334 bdev->common.dev = bdev->dev;
1335
1336 ret = dma_async_device_register(&bdev->common);
1337 if (ret) {
1338 dev_err(bdev->dev, "failed to register dma async device\n");
1339 goto err_bam_channel_exit;
1340 }
1341
1342 ret = of_dma_controller_register(pdev->dev.of_node, bam_dma_xlate,
1343 &bdev->common);
1344 if (ret)
1345 goto err_unregister_dma;
1346
1347 pm_runtime_irq_safe(&pdev->dev);
1348 pm_runtime_set_autosuspend_delay(&pdev->dev, BAM_DMA_AUTOSUSPEND_DELAY);
1349 pm_runtime_use_autosuspend(&pdev->dev);
1350 pm_runtime_mark_last_busy(&pdev->dev);
1351 pm_runtime_set_active(&pdev->dev);
1352 pm_runtime_enable(&pdev->dev);
1353
1354 return 0;
1355
1356 err_unregister_dma:
1357 dma_async_device_unregister(&bdev->common);
1358 err_bam_channel_exit:
1359 for (i = 0; i < bdev->num_channels; i++)
1360 tasklet_kill(&bdev->channels[i].vc.task);
1361 err_tasklet_kill:
1362 tasklet_kill(&bdev->task);
1363 err_disable_clk:
1364 clk_disable_unprepare(bdev->bamclk);
1365
1366 return ret;
1367 }
1368
bam_dma_remove(struct platform_device * pdev)1369 static void bam_dma_remove(struct platform_device *pdev)
1370 {
1371 struct bam_device *bdev = platform_get_drvdata(pdev);
1372 u32 i;
1373
1374 pm_runtime_force_suspend(&pdev->dev);
1375
1376 of_dma_controller_free(pdev->dev.of_node);
1377 dma_async_device_unregister(&bdev->common);
1378
1379 /* mask all interrupts for this execution environment */
1380 writel_relaxed(0, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
1381
1382 devm_free_irq(bdev->dev, bdev->irq, bdev);
1383
1384 for (i = 0; i < bdev->num_channels; i++) {
1385 bam_dma_terminate_all(&bdev->channels[i].vc.chan);
1386 tasklet_kill(&bdev->channels[i].vc.task);
1387
1388 if (!bdev->channels[i].fifo_virt)
1389 continue;
1390
1391 dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE,
1392 bdev->channels[i].fifo_virt,
1393 bdev->channels[i].fifo_phys);
1394 }
1395
1396 tasklet_kill(&bdev->task);
1397
1398 clk_disable_unprepare(bdev->bamclk);
1399 }
1400
bam_dma_runtime_suspend(struct device * dev)1401 static int __maybe_unused bam_dma_runtime_suspend(struct device *dev)
1402 {
1403 struct bam_device *bdev = dev_get_drvdata(dev);
1404
1405 clk_disable(bdev->bamclk);
1406
1407 return 0;
1408 }
1409
bam_dma_runtime_resume(struct device * dev)1410 static int __maybe_unused bam_dma_runtime_resume(struct device *dev)
1411 {
1412 struct bam_device *bdev = dev_get_drvdata(dev);
1413 int ret;
1414
1415 ret = clk_enable(bdev->bamclk);
1416 if (ret < 0) {
1417 dev_err(dev, "clk_enable failed: %d\n", ret);
1418 return ret;
1419 }
1420
1421 return 0;
1422 }
1423
bam_dma_suspend(struct device * dev)1424 static int __maybe_unused bam_dma_suspend(struct device *dev)
1425 {
1426 struct bam_device *bdev = dev_get_drvdata(dev);
1427
1428 pm_runtime_force_suspend(dev);
1429 clk_unprepare(bdev->bamclk);
1430
1431 return 0;
1432 }
1433
bam_dma_resume(struct device * dev)1434 static int __maybe_unused bam_dma_resume(struct device *dev)
1435 {
1436 struct bam_device *bdev = dev_get_drvdata(dev);
1437 int ret;
1438
1439 ret = clk_prepare(bdev->bamclk);
1440 if (ret)
1441 return ret;
1442
1443 pm_runtime_force_resume(dev);
1444
1445 return 0;
1446 }
1447
1448 static const struct dev_pm_ops bam_dma_pm_ops = {
1449 SET_LATE_SYSTEM_SLEEP_PM_OPS(bam_dma_suspend, bam_dma_resume)
1450 SET_RUNTIME_PM_OPS(bam_dma_runtime_suspend, bam_dma_runtime_resume,
1451 NULL)
1452 };
1453
1454 static struct platform_driver bam_dma_driver = {
1455 .probe = bam_dma_probe,
1456 .remove = bam_dma_remove,
1457 .driver = {
1458 .name = "bam-dma-engine",
1459 .pm = &bam_dma_pm_ops,
1460 .of_match_table = bam_of_match,
1461 },
1462 };
1463
1464 module_platform_driver(bam_dma_driver);
1465
1466 MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
1467 MODULE_DESCRIPTION("QCOM BAM DMA engine driver");
1468 MODULE_LICENSE("GPL v2");
1469