1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 /* FILE POLICY AND INTENDED USAGE:
27 * This file implements dp specific link capability retrieval sequence. It is
28 * responsible for retrieving, parsing, overriding, deciding capability obtained
29 * from dp link. Link capability consists of encoders, DPRXs, cables, retimers,
30 * usb and all other possible backend capabilities. Other components should
31 * include this header file in order to access link capability. Accessing link
32 * capability by dereferencing dc_link outside dp_link_capability is not a
33 * recommended method as it makes the component dependent on the underlying data
34 * structure used to represent link capability instead of function interfaces.
35 */
36
37 #include "link_dp_capability.h"
38 #include "link_ddc.h"
39 #include "link_dpcd.h"
40 #include "link_dp_dpia.h"
41 #include "link_dp_phy.h"
42 #include "link_edp_panel_control.h"
43 #include "link_dp_irq_handler.h"
44 #include "link/accessories/link_dp_trace.h"
45 #include "link/link_detection.h"
46 #include "link/link_validation.h"
47 #include "link_dp_training.h"
48 #include "atomfirmware.h"
49 #include "resource.h"
50 #include "link_enc_cfg.h"
51 #include "dc_dmub_srv.h"
52 #include "gpio_service_interface.h"
53
54 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
55
56 #define DC_LOGGER \
57 link->ctx->logger
58
59 #ifndef MAX
60 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
61 #endif
62 #ifndef MIN
63 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
64 #endif
65
66 struct dp_lt_fallback_entry {
67 enum dc_lane_count lane_count;
68 enum dc_link_rate link_rate;
69 };
70
71 static const struct dp_lt_fallback_entry dp_lt_fallbacks[] = {
72 /* This link training fallback array is ordered by
73 * link bandwidth from highest to lowest.
74 * DP specs makes it a normative policy to always
75 * choose the next highest link bandwidth during
76 * link training fallback.
77 */
78 {LANE_COUNT_FOUR, LINK_RATE_UHBR20},
79 {LANE_COUNT_FOUR, LINK_RATE_UHBR13_5},
80 {LANE_COUNT_TWO, LINK_RATE_UHBR20},
81 {LANE_COUNT_FOUR, LINK_RATE_UHBR10},
82 {LANE_COUNT_TWO, LINK_RATE_UHBR13_5},
83 {LANE_COUNT_FOUR, LINK_RATE_HIGH3},
84 {LANE_COUNT_ONE, LINK_RATE_UHBR20},
85 {LANE_COUNT_TWO, LINK_RATE_UHBR10},
86 {LANE_COUNT_FOUR, LINK_RATE_HIGH2},
87 {LANE_COUNT_ONE, LINK_RATE_UHBR13_5},
88 {LANE_COUNT_TWO, LINK_RATE_HIGH3},
89 {LANE_COUNT_ONE, LINK_RATE_UHBR10},
90 {LANE_COUNT_TWO, LINK_RATE_HIGH2},
91 {LANE_COUNT_FOUR, LINK_RATE_HIGH},
92 {LANE_COUNT_ONE, LINK_RATE_HIGH3},
93 {LANE_COUNT_FOUR, LINK_RATE_LOW},
94 {LANE_COUNT_ONE, LINK_RATE_HIGH2},
95 {LANE_COUNT_TWO, LINK_RATE_HIGH},
96 {LANE_COUNT_TWO, LINK_RATE_LOW},
97 {LANE_COUNT_ONE, LINK_RATE_HIGH},
98 {LANE_COUNT_ONE, LINK_RATE_LOW},
99 };
100
101 static const struct dc_link_settings fail_safe_link_settings = {
102 .lane_count = LANE_COUNT_ONE,
103 .link_rate = LINK_RATE_LOW,
104 .link_spread = LINK_SPREAD_DISABLED,
105 };
106
is_dp_active_dongle(const struct dc_link * link)107 bool is_dp_active_dongle(const struct dc_link *link)
108 {
109 return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
110 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
111 }
112
is_dp_branch_device(const struct dc_link * link)113 bool is_dp_branch_device(const struct dc_link *link)
114 {
115 return link->dpcd_caps.is_branch_dev;
116 }
117
translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)118 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
119 {
120 switch (bpc) {
121 case DOWN_STREAM_MAX_8BPC:
122 return 8;
123 case DOWN_STREAM_MAX_10BPC:
124 return 10;
125 case DOWN_STREAM_MAX_12BPC:
126 return 12;
127 case DOWN_STREAM_MAX_16BPC:
128 return 16;
129 default:
130 break;
131 }
132
133 return -1;
134 }
135
dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)136 uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)
137 {
138 switch (lttpr_repeater_count) {
139 case 0x80: // 1 lttpr repeater
140 return 1;
141 case 0x40: // 2 lttpr repeaters
142 return 2;
143 case 0x20: // 3 lttpr repeaters
144 return 3;
145 case 0x10: // 4 lttpr repeaters
146 return 4;
147 case 0x08: // 5 lttpr repeaters
148 return 5;
149 case 0x04: // 6 lttpr repeaters
150 return 6;
151 case 0x02: // 7 lttpr repeaters
152 return 7;
153 case 0x01: // 8 lttpr repeaters
154 return 8;
155 default:
156 break;
157 }
158 return 0; // invalid value
159 }
160
link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)161 uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)
162 {
163 switch (bw) {
164 case 0b001:
165 return 9000000;
166 case 0b010:
167 return 18000000;
168 case 0b011:
169 return 24000000;
170 case 0b100:
171 return 32000000;
172 case 0b101:
173 return 40000000;
174 case 0b110:
175 return 48000000;
176 }
177
178 return 0;
179 }
180
linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)181 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
182 {
183 enum dc_link_rate link_rate;
184 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
185 switch (link_rate_in_khz) {
186 case 1620000:
187 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane
188 break;
189 case 2160000:
190 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane
191 break;
192 case 2430000:
193 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane
194 break;
195 case 2700000:
196 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane
197 break;
198 case 3240000:
199 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2)- 3.24 Gbps/Lane
200 break;
201 case 4320000:
202 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane
203 break;
204 case 5400000:
205 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2)- 5.40 Gbps/Lane
206 break;
207 case 6750000:
208 link_rate = LINK_RATE_RATE_8; // Rate_8 - 6.75 Gbps/Lane
209 break;
210 case 8100000:
211 link_rate = LINK_RATE_HIGH3; // Rate_9 (HBR3)- 8.10 Gbps/Lane
212 break;
213 case 10000000:
214 link_rate = LINK_RATE_UHBR10; // UHBR10 - 10.0 Gbps/Lane
215 break;
216 case 13500000:
217 link_rate = LINK_RATE_UHBR13_5; // UHBR13.5 - 13.5 Gbps/Lane
218 break;
219 case 20000000:
220 link_rate = LINK_RATE_UHBR20; // UHBR20 - 20.0 Gbps/Lane
221 break;
222
223 default:
224 link_rate = LINK_RATE_UNKNOWN;
225 break;
226 }
227 return link_rate;
228 }
229
intersect_cable_id(union dp_cable_id * a,union dp_cable_id * b)230 static union dp_cable_id intersect_cable_id(
231 union dp_cable_id *a, union dp_cable_id *b)
232 {
233 union dp_cable_id out;
234
235 out.bits.UHBR10_20_CAPABILITY = MIN(a->bits.UHBR10_20_CAPABILITY,
236 b->bits.UHBR10_20_CAPABILITY);
237 out.bits.UHBR13_5_CAPABILITY = MIN(a->bits.UHBR13_5_CAPABILITY,
238 b->bits.UHBR13_5_CAPABILITY);
239 out.bits.CABLE_TYPE = MAX(a->bits.CABLE_TYPE, b->bits.CABLE_TYPE);
240
241 return out;
242 }
243
244 /*
245 * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw.
246 */
intersect_frl_link_bw_support(const uint32_t max_supported_frl_bw_in_kbps,const union hdmi_encoded_link_bw hdmi_encoded_link_bw)247 static uint32_t intersect_frl_link_bw_support(
248 const uint32_t max_supported_frl_bw_in_kbps,
249 const union hdmi_encoded_link_bw hdmi_encoded_link_bw)
250 {
251 uint32_t supported_bw_in_kbps = max_supported_frl_bw_in_kbps;
252
253 // HDMI_ENCODED_LINK_BW bits are only valid if HDMI Link Configuration bit is 1 (FRL mode)
254 if (hdmi_encoded_link_bw.bits.FRL_MODE) {
255 if (hdmi_encoded_link_bw.bits.BW_48Gbps)
256 supported_bw_in_kbps = 48000000;
257 else if (hdmi_encoded_link_bw.bits.BW_40Gbps)
258 supported_bw_in_kbps = 40000000;
259 else if (hdmi_encoded_link_bw.bits.BW_32Gbps)
260 supported_bw_in_kbps = 32000000;
261 else if (hdmi_encoded_link_bw.bits.BW_24Gbps)
262 supported_bw_in_kbps = 24000000;
263 else if (hdmi_encoded_link_bw.bits.BW_18Gbps)
264 supported_bw_in_kbps = 18000000;
265 else if (hdmi_encoded_link_bw.bits.BW_9Gbps)
266 supported_bw_in_kbps = 9000000;
267 }
268
269 return supported_bw_in_kbps;
270 }
271
get_clock_source_id(struct dc_link * link)272 static enum clock_source_id get_clock_source_id(struct dc_link *link)
273 {
274 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
275 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
276
277 if (dp_cs != NULL) {
278 dp_cs_id = dp_cs->id;
279 } else {
280 /*
281 * dp clock source is not initialized for some reason.
282 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
283 */
284 ASSERT(dp_cs);
285 }
286
287 return dp_cs_id;
288 }
289
dp_wa_power_up_0010FA(struct dc_link * link,uint8_t * dpcd_data,int length)290 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
291 int length)
292 {
293 int retry = 0;
294
295 if (!link->dpcd_caps.dpcd_rev.raw) {
296 do {
297 dpcd_write_rx_power_ctrl(link, true);
298 core_link_read_dpcd(link, DP_DPCD_REV,
299 dpcd_data, length);
300 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
301 DP_DPCD_REV -
302 DP_DPCD_REV];
303 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
304 }
305
306 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
307 switch (link->dpcd_caps.branch_dev_id) {
308 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
309 * all internal circuits including AUX communication preventing
310 * reading DPCD table and EDID (spec violation).
311 * Encoder will skip DP RX power down on disable_output to
312 * keep receiver powered all the time.*/
313 case DP_BRANCH_DEVICE_ID_0010FA:
314 case DP_BRANCH_DEVICE_ID_0080E1:
315 case DP_BRANCH_DEVICE_ID_00E04C:
316 link->wa_flags.dp_keep_receiver_powered = true;
317 break;
318
319 /* TODO: May need work around for other dongles. */
320 default:
321 link->wa_flags.dp_keep_receiver_powered = false;
322 break;
323 }
324 } else
325 link->wa_flags.dp_keep_receiver_powered = false;
326 }
327
dp_is_fec_supported(const struct dc_link * link)328 bool dp_is_fec_supported(const struct dc_link *link)
329 {
330 /* TODO - use asic cap instead of link_enc->features
331 * we no longer know which link enc to use for this link before commit
332 */
333 struct link_encoder *link_enc = NULL;
334
335 link_enc = link_enc_cfg_get_link_enc(link);
336 ASSERT(link_enc);
337
338 return (dc_is_dp_signal(link->connector_signal) && link_enc &&
339 link_enc->features.fec_supported &&
340 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE);
341 }
342
dp_should_enable_fec(const struct dc_link * link)343 bool dp_should_enable_fec(const struct dc_link *link)
344 {
345 bool force_disable = false;
346
347 if (link->fec_state == dc_link_fec_enabled)
348 force_disable = false;
349 else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
350 link->local_sink &&
351 link->local_sink->edid_caps.panel_patch.disable_fec)
352 force_disable = true;
353 else if (link->connector_signal == SIGNAL_TYPE_EDP
354 && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
355 dsc_support.DSC_SUPPORT == false
356 || link->panel_config.dsc.disable_dsc_edp
357 || !link->dc->caps.edp_dsc_support))
358 force_disable = true;
359
360 return !force_disable && dp_is_fec_supported(link);
361 }
362
dp_is_128b_132b_signal(struct pipe_ctx * pipe_ctx)363 bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx)
364 {
365 /* If this assert is hit then we have a link encoder dynamic management issue */
366 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
367 return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
368 pipe_ctx->link_res.hpo_dp_link_enc &&
369 dc_is_dp_signal(pipe_ctx->stream->signal));
370 }
371
dp_is_lttpr_present(struct dc_link * link)372 bool dp_is_lttpr_present(struct dc_link *link)
373 {
374 /* Some sink devices report invalid LTTPR revision, so don't validate against that cap */
375 return (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
376 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
377 link->dpcd_caps.lttpr_caps.max_lane_count <= 4);
378 }
379
380 /* in DP compliance test, DPR-120 may have
381 * a random value in its MAX_LINK_BW dpcd field.
382 * We map it to the maximum supported link rate that
383 * is smaller than MAX_LINK_BW in this case.
384 */
get_link_rate_from_max_link_bw(uint8_t max_link_bw)385 static enum dc_link_rate get_link_rate_from_max_link_bw(
386 uint8_t max_link_bw)
387 {
388 enum dc_link_rate link_rate;
389
390 if (max_link_bw >= LINK_RATE_HIGH3) {
391 link_rate = LINK_RATE_HIGH3;
392 } else if (max_link_bw < LINK_RATE_HIGH3
393 && max_link_bw >= LINK_RATE_HIGH2) {
394 link_rate = LINK_RATE_HIGH2;
395 } else if (max_link_bw < LINK_RATE_HIGH2
396 && max_link_bw >= LINK_RATE_HIGH) {
397 link_rate = LINK_RATE_HIGH;
398 } else if (max_link_bw < LINK_RATE_HIGH
399 && max_link_bw >= LINK_RATE_LOW) {
400 link_rate = LINK_RATE_LOW;
401 } else {
402 link_rate = LINK_RATE_UNKNOWN;
403 }
404
405 return link_rate;
406 }
407
get_lttpr_max_link_rate(struct dc_link * link)408 static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link)
409 {
410
411 enum dc_link_rate lttpr_max_link_rate = LINK_RATE_UNKNOWN;
412
413 switch (link->dpcd_caps.lttpr_caps.max_link_rate) {
414 case LINK_RATE_LOW:
415 case LINK_RATE_HIGH:
416 case LINK_RATE_HIGH2:
417 case LINK_RATE_HIGH3:
418 lttpr_max_link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
419 break;
420 }
421
422 if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR20)
423 lttpr_max_link_rate = LINK_RATE_UHBR20;
424 else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)
425 lttpr_max_link_rate = LINK_RATE_UHBR13_5;
426 else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR10)
427 lttpr_max_link_rate = LINK_RATE_UHBR10;
428
429 return lttpr_max_link_rate;
430 }
431
get_cable_max_link_rate(struct dc_link * link)432 static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link)
433 {
434 enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN;
435
436 if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR20) {
437 cable_max_link_rate = LINK_RATE_UHBR20;
438 } else if (link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY) {
439 cable_max_link_rate = LINK_RATE_UHBR13_5;
440 } else if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR10) {
441 // allow DP40 cables to do UHBR13.5 for passive or unknown cable type
442 if (link->dpcd_caps.cable_id.bits.CABLE_TYPE < 2) {
443 cable_max_link_rate = LINK_RATE_UHBR13_5;
444 } else {
445 cable_max_link_rate = LINK_RATE_UHBR10;
446 }
447 }
448
449 return cable_max_link_rate;
450 }
451
reached_minimum_lane_count(enum dc_lane_count lane_count)452 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
453 {
454 return lane_count <= LANE_COUNT_ONE;
455 }
456
reached_minimum_link_rate(enum dc_link_rate link_rate)457 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
458 {
459 return link_rate <= LINK_RATE_LOW;
460 }
461
reduce_lane_count(enum dc_lane_count lane_count)462 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
463 {
464 switch (lane_count) {
465 case LANE_COUNT_FOUR:
466 return LANE_COUNT_TWO;
467 case LANE_COUNT_TWO:
468 return LANE_COUNT_ONE;
469 case LANE_COUNT_ONE:
470 return LANE_COUNT_UNKNOWN;
471 default:
472 return LANE_COUNT_UNKNOWN;
473 }
474 }
475
reduce_link_rate(const struct dc_link * link,enum dc_link_rate link_rate)476 static enum dc_link_rate reduce_link_rate(const struct dc_link *link, enum dc_link_rate link_rate)
477 {
478 // NEEDSWORK: provide some details about why this function never returns some of the
479 // obscure link rates such as 4.32 Gbps or 3.24 Gbps and if such behavior is intended.
480 //
481
482 switch (link_rate) {
483 case LINK_RATE_UHBR20:
484 return LINK_RATE_UHBR13_5;
485 case LINK_RATE_UHBR13_5:
486 return LINK_RATE_UHBR10;
487 case LINK_RATE_UHBR10:
488 return LINK_RATE_HIGH3;
489 case LINK_RATE_HIGH3:
490 if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->debug.support_eDP1_5)
491 return LINK_RATE_RATE_8;
492 return LINK_RATE_HIGH2;
493 case LINK_RATE_RATE_8:
494 return LINK_RATE_HIGH2;
495 case LINK_RATE_HIGH2:
496 return LINK_RATE_HIGH;
497 case LINK_RATE_RATE_6:
498 case LINK_RATE_RBR2:
499 return LINK_RATE_HIGH;
500 case LINK_RATE_HIGH:
501 return LINK_RATE_LOW;
502 case LINK_RATE_RATE_3:
503 case LINK_RATE_RATE_2:
504 return LINK_RATE_LOW;
505 case LINK_RATE_LOW:
506 default:
507 return LINK_RATE_UNKNOWN;
508 }
509 }
510
increase_lane_count(enum dc_lane_count lane_count)511 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
512 {
513 switch (lane_count) {
514 case LANE_COUNT_ONE:
515 return LANE_COUNT_TWO;
516 case LANE_COUNT_TWO:
517 return LANE_COUNT_FOUR;
518 default:
519 return LANE_COUNT_UNKNOWN;
520 }
521 }
522
increase_link_rate(struct dc_link * link,enum dc_link_rate link_rate)523 static enum dc_link_rate increase_link_rate(struct dc_link *link,
524 enum dc_link_rate link_rate)
525 {
526 switch (link_rate) {
527 case LINK_RATE_LOW:
528 return LINK_RATE_HIGH;
529 case LINK_RATE_HIGH:
530 return LINK_RATE_HIGH2;
531 case LINK_RATE_HIGH2:
532 return LINK_RATE_HIGH3;
533 case LINK_RATE_HIGH3:
534 return LINK_RATE_UHBR10;
535 case LINK_RATE_UHBR10:
536 /* upto DP2.x specs UHBR13.5 is the only link rate that could be
537 * not supported by DPRX when higher link rate is supported.
538 * so we treat it as a special case for code simplicity. When we
539 * have new specs with more link rates like this, we should
540 * consider a more generic solution to handle discrete link
541 * rate capabilities.
542 */
543 return link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 ?
544 LINK_RATE_UHBR13_5 : LINK_RATE_UHBR20;
545 case LINK_RATE_UHBR13_5:
546 return LINK_RATE_UHBR20;
547 default:
548 return LINK_RATE_UNKNOWN;
549 }
550 }
551
increase_edp_link_rate(struct dc_link * link,struct dc_link_settings * current_link_setting)552 static void increase_edp_link_rate(struct dc_link *link,
553 struct dc_link_settings *current_link_setting)
554 {
555 if (current_link_setting->use_link_rate_set) {
556 if (current_link_setting->link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
557 current_link_setting->link_rate_set++;
558 current_link_setting->link_rate =
559 link->dpcd_caps.edp_supported_link_rates[current_link_setting->link_rate_set];
560 } else {
561 current_link_setting->use_link_rate_set = false;
562 current_link_setting->link_rate = LINK_RATE_UHBR10;
563 }
564 } else {
565 current_link_setting->link_rate = increase_link_rate(link, current_link_setting->link_rate);
566 }
567 }
568
decide_fallback_link_setting_max_bw_policy(struct dc_link * link,const struct dc_link_settings * max,struct dc_link_settings * cur,enum link_training_result training_result)569 static bool decide_fallback_link_setting_max_bw_policy(
570 struct dc_link *link,
571 const struct dc_link_settings *max,
572 struct dc_link_settings *cur,
573 enum link_training_result training_result)
574 {
575 uint32_t cur_idx = 0, next_idx;
576 bool found = false;
577
578 if (training_result == LINK_TRAINING_ABORT)
579 return false;
580
581 while (cur_idx < ARRAY_SIZE(dp_lt_fallbacks))
582 /* find current index */
583 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count &&
584 dp_lt_fallbacks[cur_idx].link_rate == cur->link_rate)
585 break;
586 else
587 cur_idx++;
588
589 next_idx = cur_idx + 1;
590
591 while (next_idx < ARRAY_SIZE(dp_lt_fallbacks))
592 /* find next index */
593 if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count ||
594 dp_lt_fallbacks[next_idx].link_rate > max->link_rate)
595 next_idx++;
596 else if (dp_lt_fallbacks[next_idx].link_rate == LINK_RATE_UHBR13_5 &&
597 link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 == 0)
598 /* upto DP2.x specs UHBR13.5 is the only link rate that
599 * could be not supported by DPRX when higher link rate
600 * is supported. so we treat it as a special case for
601 * code simplicity. When we have new specs with more
602 * link rates like this, we should consider a more
603 * generic solution to handle discrete link rate
604 * capabilities.
605 */
606 next_idx++;
607 else
608 break;
609
610 if (next_idx < ARRAY_SIZE(dp_lt_fallbacks)) {
611 cur->lane_count = dp_lt_fallbacks[next_idx].lane_count;
612 cur->link_rate = dp_lt_fallbacks[next_idx].link_rate;
613 found = true;
614 }
615
616 return found;
617 }
618
619 /*
620 * function: set link rate and lane count fallback based
621 * on current link setting and last link training result
622 * return value:
623 * true - link setting could be set
624 * false - has reached minimum setting
625 * and no further fallback could be done
626 */
decide_fallback_link_setting(struct dc_link * link,struct dc_link_settings * max,struct dc_link_settings * cur,enum link_training_result training_result)627 bool decide_fallback_link_setting(
628 struct dc_link *link,
629 struct dc_link_settings *max,
630 struct dc_link_settings *cur,
631 enum link_training_result training_result)
632 {
633 if (link_dp_get_encoding_format(max) == DP_128b_132b_ENCODING ||
634 link->dc->debug.force_dp2_lt_fallback_method)
635 return decide_fallback_link_setting_max_bw_policy(link, max,
636 cur, training_result);
637
638 switch (training_result) {
639 case LINK_TRAINING_CR_FAIL_LANE0:
640 case LINK_TRAINING_CR_FAIL_LANE1:
641 case LINK_TRAINING_CR_FAIL_LANE23:
642 case LINK_TRAINING_LQA_FAIL:
643 {
644 if (!reached_minimum_link_rate(cur->link_rate)) {
645 cur->link_rate = reduce_link_rate(link, cur->link_rate);
646 } else if (!reached_minimum_lane_count(cur->lane_count)) {
647 cur->link_rate = max->link_rate;
648 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
649 return false;
650 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
651 cur->lane_count = LANE_COUNT_ONE;
652 else if (training_result == LINK_TRAINING_CR_FAIL_LANE23)
653 cur->lane_count = LANE_COUNT_TWO;
654 else
655 cur->lane_count = reduce_lane_count(cur->lane_count);
656 } else {
657 return false;
658 }
659 break;
660 }
661 case LINK_TRAINING_EQ_FAIL_EQ:
662 case LINK_TRAINING_EQ_FAIL_CR_PARTIAL:
663 {
664 if (!reached_minimum_lane_count(cur->lane_count)) {
665 cur->lane_count = reduce_lane_count(cur->lane_count);
666 } else if (!reached_minimum_link_rate(cur->link_rate)) {
667 cur->link_rate = reduce_link_rate(link, cur->link_rate);
668 /* Reduce max link rate to avoid potential infinite loop.
669 * Needed so that any subsequent CR_FAIL fallback can't
670 * re-set the link rate higher than the link rate from
671 * the latest EQ_FAIL fallback.
672 */
673 max->link_rate = cur->link_rate;
674 cur->lane_count = max->lane_count;
675 } else {
676 return false;
677 }
678 break;
679 }
680 case LINK_TRAINING_EQ_FAIL_CR:
681 {
682 if (!reached_minimum_link_rate(cur->link_rate)) {
683 cur->link_rate = reduce_link_rate(link, cur->link_rate);
684 /* Reduce max link rate to avoid potential infinite loop.
685 * Needed so that any subsequent CR_FAIL fallback can't
686 * re-set the link rate higher than the link rate from
687 * the latest EQ_FAIL fallback.
688 */
689 max->link_rate = cur->link_rate;
690 cur->lane_count = max->lane_count;
691 } else {
692 return false;
693 }
694 break;
695 }
696 default:
697 return false;
698 }
699 return true;
700 }
decide_dp_link_settings(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw)701 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
702 {
703 struct dc_link_settings initial_link_setting = {
704 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
705 struct dc_link_settings current_link_setting =
706 initial_link_setting;
707 uint32_t link_bw;
708
709 if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap))
710 return false;
711
712 /* search for the minimum link setting that:
713 * 1. is supported according to the link training result
714 * 2. could support the b/w requested by the timing
715 */
716 while (current_link_setting.link_rate <=
717 link->verified_link_cap.link_rate) {
718 link_bw = dp_link_bandwidth_kbps(
719 link,
720 ¤t_link_setting);
721 if (req_bw <= link_bw) {
722 *link_setting = current_link_setting;
723 return true;
724 }
725
726 if (current_link_setting.lane_count <
727 link->verified_link_cap.lane_count) {
728 current_link_setting.lane_count =
729 increase_lane_count(
730 current_link_setting.lane_count);
731 } else {
732 current_link_setting.link_rate =
733 increase_link_rate(link,
734 current_link_setting.link_rate);
735 current_link_setting.lane_count =
736 initial_link_setting.lane_count;
737 }
738 }
739
740 return false;
741 }
742
edp_decide_link_settings(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw)743 bool edp_decide_link_settings(struct dc_link *link,
744 struct dc_link_settings *link_setting, uint32_t req_bw)
745 {
746 struct dc_link_settings initial_link_setting;
747 struct dc_link_settings current_link_setting;
748 uint32_t link_bw;
749
750 /*
751 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
752 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
753 */
754 if (!edp_is_ilr_optimization_enabled(link)) {
755 *link_setting = link->verified_link_cap;
756 return true;
757 }
758
759 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
760 initial_link_setting.lane_count = LANE_COUNT_ONE;
761 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
762 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
763 initial_link_setting.use_link_rate_set = true;
764 initial_link_setting.link_rate_set = 0;
765 current_link_setting = initial_link_setting;
766
767 /* search for the minimum link setting that:
768 * 1. is supported according to the link training result
769 * 2. could support the b/w requested by the timing
770 */
771 while (current_link_setting.link_rate <=
772 link->verified_link_cap.link_rate) {
773 link_bw = dp_link_bandwidth_kbps(
774 link,
775 ¤t_link_setting);
776 if (req_bw <= link_bw) {
777 *link_setting = current_link_setting;
778 return true;
779 }
780
781 if (current_link_setting.lane_count <
782 link->verified_link_cap.lane_count) {
783 current_link_setting.lane_count =
784 increase_lane_count(
785 current_link_setting.lane_count);
786 } else {
787 increase_edp_link_rate(link, ¤t_link_setting);
788 }
789 }
790 return false;
791 }
792
decide_edp_link_settings_with_dsc(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw,enum dc_link_rate max_link_rate)793 bool decide_edp_link_settings_with_dsc(struct dc_link *link,
794 struct dc_link_settings *link_setting,
795 uint32_t req_bw,
796 enum dc_link_rate max_link_rate)
797 {
798 struct dc_link_settings initial_link_setting;
799 struct dc_link_settings current_link_setting;
800 uint32_t link_bw;
801
802 unsigned int policy = 0;
803
804 policy = link->panel_config.dsc.force_dsc_edp_policy;
805 if (max_link_rate == LINK_RATE_UNKNOWN)
806 max_link_rate = link->verified_link_cap.link_rate;
807 /*
808 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
809 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
810 */
811 if (!edp_is_ilr_optimization_enabled(link)) {
812 /* for DSC enabled case, we search for minimum lane count */
813 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
814 initial_link_setting.lane_count = LANE_COUNT_ONE;
815 initial_link_setting.link_rate = LINK_RATE_LOW;
816 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
817 initial_link_setting.use_link_rate_set = false;
818 initial_link_setting.link_rate_set = 0;
819 current_link_setting = initial_link_setting;
820 if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap))
821 return false;
822
823 /* search for the minimum link setting that:
824 * 1. is supported according to the link training result
825 * 2. could support the b/w requested by the timing
826 */
827 while (current_link_setting.link_rate <=
828 max_link_rate) {
829 link_bw = dp_link_bandwidth_kbps(
830 link,
831 ¤t_link_setting);
832 if (req_bw <= link_bw) {
833 *link_setting = current_link_setting;
834 return true;
835 }
836 if (policy) {
837 /* minimize lane */
838 if (current_link_setting.link_rate < max_link_rate) {
839 increase_edp_link_rate(link, ¤t_link_setting);
840 } else {
841 if (current_link_setting.lane_count <
842 link->verified_link_cap.lane_count) {
843 current_link_setting.lane_count =
844 increase_lane_count(
845 current_link_setting.lane_count);
846 current_link_setting.link_rate = initial_link_setting.link_rate;
847 } else
848 break;
849 }
850 } else {
851 /* minimize link rate */
852 if (current_link_setting.lane_count <
853 link->verified_link_cap.lane_count) {
854 current_link_setting.lane_count =
855 increase_lane_count(
856 current_link_setting.lane_count);
857 } else {
858 increase_edp_link_rate(link, ¤t_link_setting);
859 current_link_setting.lane_count =
860 initial_link_setting.lane_count;
861 }
862 }
863 }
864 return false;
865 }
866
867 /* if optimize edp link is supported */
868 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
869 initial_link_setting.lane_count = LANE_COUNT_ONE;
870 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
871 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
872 initial_link_setting.use_link_rate_set = true;
873 initial_link_setting.link_rate_set = 0;
874 current_link_setting = initial_link_setting;
875
876 /* search for the minimum link setting that:
877 * 1. is supported according to the link training result
878 * 2. could support the b/w requested by the timing
879 */
880 while (current_link_setting.link_rate <=
881 max_link_rate) {
882 link_bw = dp_link_bandwidth_kbps(
883 link,
884 ¤t_link_setting);
885 if (req_bw <= link_bw) {
886 *link_setting = current_link_setting;
887 return true;
888 }
889 if (policy) {
890 /* minimize lane */
891 if (current_link_setting.link_rate < max_link_rate) {
892 increase_edp_link_rate(link, ¤t_link_setting);
893 } else {
894 if (current_link_setting.lane_count < link->verified_link_cap.lane_count) {
895 current_link_setting.lane_count =
896 increase_lane_count(
897 current_link_setting.lane_count);
898 current_link_setting.link_rate_set = initial_link_setting.link_rate_set;
899 current_link_setting.use_link_rate_set = initial_link_setting.use_link_rate_set;
900 current_link_setting.link_rate =
901 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
902 } else
903 break;
904 }
905 } else {
906 /* minimize link rate */
907 if (current_link_setting.lane_count <
908 link->verified_link_cap.lane_count) {
909 current_link_setting.lane_count =
910 increase_lane_count(
911 current_link_setting.lane_count);
912 } else {
913 increase_edp_link_rate(link, ¤t_link_setting);
914 if (current_link_setting.link_rate == LINK_RATE_UNKNOWN)
915 break;
916 }
917 }
918 }
919 return false;
920 }
921
decide_mst_link_settings(const struct dc_link * link,struct dc_link_settings * link_setting)922 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
923 {
924 *link_setting = link->verified_link_cap;
925 return true;
926 }
927
link_decide_link_settings(struct dc_stream_state * stream,struct dc_link_settings * link_setting)928 bool link_decide_link_settings(struct dc_stream_state *stream,
929 struct dc_link_settings *link_setting)
930 {
931 struct dc_link *link = stream->link;
932 uint32_t req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, dc_link_get_highest_encoding_format(link));
933
934 memset(link_setting, 0, sizeof(*link_setting));
935
936 if (dc_is_dp_signal(stream->signal) &&
937 link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
938 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) {
939 /* if preferred is specified through AMDDP, use it, if it's enough
940 * to drive the mode
941 */
942 *link_setting = link->preferred_link_setting;
943 } else if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
944 /* MST doesn't perform link training for now
945 * TODO: add MST specific link training routine
946 */
947 decide_mst_link_settings(link, link_setting);
948 } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
949 /* enable edp link optimization for DSC eDP case */
950 if (stream->timing.flags.DSC) {
951 enum dc_link_rate max_link_rate = LINK_RATE_UNKNOWN;
952
953 if (link->panel_config.dsc.force_dsc_edp_policy) {
954 /* calculate link max link rate cap*/
955 struct dc_link_settings tmp_link_setting;
956 struct dc_crtc_timing tmp_timing = stream->timing;
957 uint32_t orig_req_bw;
958
959 tmp_link_setting.link_rate = LINK_RATE_UNKNOWN;
960 tmp_timing.flags.DSC = 0;
961 orig_req_bw = dc_bandwidth_in_kbps_from_timing(&tmp_timing,
962 dc_link_get_highest_encoding_format(link));
963 edp_decide_link_settings(link, &tmp_link_setting, orig_req_bw);
964 max_link_rate = tmp_link_setting.link_rate;
965 }
966 decide_edp_link_settings_with_dsc(link, link_setting, req_bw, max_link_rate);
967 } else {
968 edp_decide_link_settings(link, link_setting, req_bw);
969 }
970 } else if (stream->signal == SIGNAL_TYPE_VIRTUAL) {
971 link_setting->lane_count = LANE_COUNT_FOUR;
972 link_setting->link_rate = LINK_RATE_HIGH3;
973 } else {
974 decide_dp_link_settings(link, link_setting, req_bw);
975 }
976
977 return link_setting->lane_count != LANE_COUNT_UNKNOWN &&
978 link_setting->link_rate != LINK_RATE_UNKNOWN;
979 }
980
link_dp_get_encoding_format(const struct dc_link_settings * link_settings)981 enum dp_link_encoding link_dp_get_encoding_format(const struct dc_link_settings *link_settings)
982 {
983 if ((link_settings->link_rate >= LINK_RATE_LOW) &&
984 (link_settings->link_rate <= LINK_RATE_HIGH3))
985 return DP_8b_10b_ENCODING;
986 else if ((link_settings->link_rate >= LINK_RATE_UHBR10) &&
987 (link_settings->link_rate <= LINK_RATE_UHBR20))
988 return DP_128b_132b_ENCODING;
989 return DP_UNKNOWN_ENCODING;
990 }
991
mst_decide_link_encoding_format(const struct dc_link * link)992 enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link)
993 {
994 struct dc_link_settings link_settings = {0};
995
996 if (!dc_is_dp_signal(link->connector_signal))
997 return DP_UNKNOWN_ENCODING;
998
999 if (link->preferred_link_setting.lane_count !=
1000 LANE_COUNT_UNKNOWN &&
1001 link->preferred_link_setting.link_rate !=
1002 LINK_RATE_UNKNOWN) {
1003 link_settings = link->preferred_link_setting;
1004 } else {
1005 decide_mst_link_settings(link, &link_settings);
1006 }
1007
1008 return link_dp_get_encoding_format(&link_settings);
1009 }
1010
read_dp_device_vendor_id(struct dc_link * link)1011 static void read_dp_device_vendor_id(struct dc_link *link)
1012 {
1013 struct dp_device_vendor_id dp_id = {0};
1014
1015 /* read IEEE branch device id */
1016 core_link_read_dpcd(
1017 link,
1018 DP_BRANCH_OUI,
1019 (uint8_t *)&dp_id,
1020 sizeof(dp_id));
1021
1022 link->dpcd_caps.branch_dev_id =
1023 (dp_id.ieee_oui[0] << 16) +
1024 (dp_id.ieee_oui[1] << 8) +
1025 dp_id.ieee_oui[2];
1026
1027 memmove(
1028 link->dpcd_caps.branch_dev_name,
1029 dp_id.ieee_device_id,
1030 sizeof(dp_id.ieee_device_id));
1031 }
1032
wake_up_aux_channel(struct dc_link * link)1033 static enum dc_status wake_up_aux_channel(struct dc_link *link)
1034 {
1035 enum dc_status status = DC_ERROR_UNEXPECTED;
1036 uint32_t aux_channel_retry_cnt = 0;
1037 uint8_t dpcd_power_state = '\0';
1038
1039 while (status != DC_OK && aux_channel_retry_cnt < 10) {
1040 status = core_link_read_dpcd(link, DP_SET_POWER,
1041 &dpcd_power_state, sizeof(dpcd_power_state));
1042
1043 /* Delay 1 ms if AUX CH is in power down state. Based on spec
1044 * section 2.3.1.2, if AUX CH may be powered down due to
1045 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
1046 * signal and may need up to 1 ms before being able to reply.
1047 */
1048 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) {
1049 fsleep(1000);
1050 aux_channel_retry_cnt++;
1051 }
1052 }
1053
1054 if (status != DC_OK) {
1055 dpcd_power_state = DP_SET_POWER_D0;
1056 status = core_link_write_dpcd(
1057 link,
1058 DP_SET_POWER,
1059 &dpcd_power_state,
1060 sizeof(dpcd_power_state));
1061
1062 dpcd_power_state = DP_SET_POWER_D3;
1063 status = core_link_write_dpcd(
1064 link,
1065 DP_SET_POWER,
1066 &dpcd_power_state,
1067 sizeof(dpcd_power_state));
1068 DC_LOG_DC("%s: Failed to power up sink\n", __func__);
1069 return DC_ERROR_UNEXPECTED;
1070 }
1071
1072 return DC_OK;
1073 }
1074
get_active_converter_info(uint8_t data,struct dc_link * link)1075 static void get_active_converter_info(
1076 uint8_t data, struct dc_link *link)
1077 {
1078 union dp_downstream_port_present ds_port = { .byte = data };
1079 memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
1080
1081 /* decode converter info*/
1082 if (!ds_port.fields.PORT_PRESENT) {
1083 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1084 set_dongle_type(link->ddc,
1085 link->dpcd_caps.dongle_type);
1086 link->dpcd_caps.is_branch_dev = false;
1087 return;
1088 }
1089
1090 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
1091 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
1092
1093 switch (ds_port.fields.PORT_TYPE) {
1094 case DOWNSTREAM_VGA:
1095 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
1096 break;
1097 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
1098 /* At this point we don't know is it DVI or HDMI or DP++,
1099 * assume DVI.*/
1100 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
1101 break;
1102 default:
1103 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1104 break;
1105 }
1106
1107 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
1108 uint8_t det_caps[16] = {0}; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
1109 union dwnstream_port_caps_byte0 *port_caps =
1110 (union dwnstream_port_caps_byte0 *)det_caps;
1111 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
1112 det_caps, sizeof(det_caps)) == DC_OK) {
1113
1114 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
1115 /*Handle DP case as DONGLE_NONE*/
1116 case DOWN_STREAM_DETAILED_DP:
1117 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1118 break;
1119 case DOWN_STREAM_DETAILED_VGA:
1120 link->dpcd_caps.dongle_type =
1121 DISPLAY_DONGLE_DP_VGA_CONVERTER;
1122 break;
1123 case DOWN_STREAM_DETAILED_DVI:
1124 link->dpcd_caps.dongle_type =
1125 DISPLAY_DONGLE_DP_DVI_CONVERTER;
1126 break;
1127 case DOWN_STREAM_DETAILED_HDMI:
1128 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
1129 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
1130 link->dpcd_caps.dongle_type =
1131 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
1132
1133 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
1134 if (ds_port.fields.DETAILED_CAPS) {
1135
1136 union dwnstream_port_caps_byte3_hdmi
1137 hdmi_caps = {.raw = det_caps[3] };
1138 union dwnstream_port_caps_byte2
1139 hdmi_color_caps = {.raw = det_caps[2] };
1140 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
1141 det_caps[1] * 2500;
1142
1143 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
1144 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
1145 /*YCBCR capability only for HDMI case*/
1146 if (port_caps->bits.DWN_STRM_PORTX_TYPE
1147 == DOWN_STREAM_DETAILED_HDMI) {
1148 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
1149 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
1150 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
1151 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
1152 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
1153 hdmi_caps.bits.YCrCr422_CONVERSION;
1154 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
1155 hdmi_caps.bits.YCrCr420_CONVERSION;
1156 }
1157
1158 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
1159 translate_dpcd_max_bpc(
1160 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
1161
1162 if (link->dc->caps.dp_hdmi21_pcon_support) {
1163 union hdmi_encoded_link_bw hdmi_encoded_link_bw;
1164
1165 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps =
1166 link_bw_kbps_from_raw_frl_link_rate_data(
1167 hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT);
1168
1169 // Intersect reported max link bw support with the supported link rate post FRL link training
1170 if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS,
1171 &hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) {
1172 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support(
1173 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps,
1174 hdmi_encoded_link_bw);
1175 DC_LOG_DC("%s: pcon frl link bw = %u\n", __func__,
1176 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps);
1177 }
1178
1179 if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0)
1180 link->dpcd_caps.dongle_caps.extendedCapValid = true;
1181 }
1182
1183 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
1184 link->dpcd_caps.dongle_caps.extendedCapValid = true;
1185 }
1186
1187 break;
1188 }
1189 }
1190 }
1191
1192 set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
1193
1194 {
1195 struct dp_sink_hw_fw_revision dp_hw_fw_revision = {0};
1196
1197 core_link_read_dpcd(
1198 link,
1199 DP_BRANCH_REVISION_START,
1200 (uint8_t *)&dp_hw_fw_revision,
1201 sizeof(dp_hw_fw_revision));
1202
1203 link->dpcd_caps.branch_hw_revision =
1204 dp_hw_fw_revision.ieee_hw_rev;
1205
1206 memmove(
1207 link->dpcd_caps.branch_fw_revision,
1208 dp_hw_fw_revision.ieee_fw_rev,
1209 sizeof(dp_hw_fw_revision.ieee_fw_rev));
1210 }
1211
1212 core_link_read_dpcd(
1213 link,
1214 DP_BRANCH_VENDOR_SPECIFIC_START,
1215 (uint8_t *)link->dpcd_caps.branch_vendor_specific_data,
1216 sizeof(link->dpcd_caps.branch_vendor_specific_data));
1217
1218 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
1219 link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {
1220 union dp_dfp_cap_ext dfp_cap_ext;
1221 memset(&dfp_cap_ext, '\0', sizeof (dfp_cap_ext));
1222 core_link_read_dpcd(
1223 link,
1224 DP_DFP_CAPABILITY_EXTENSION_SUPPORT,
1225 dfp_cap_ext.raw,
1226 sizeof(dfp_cap_ext.raw));
1227 link->dpcd_caps.dongle_caps.dfp_cap_ext.supported = dfp_cap_ext.fields.supported;
1228 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps =
1229 dfp_cap_ext.fields.max_pixel_rate_in_mps[0] +
1230 (dfp_cap_ext.fields.max_pixel_rate_in_mps[1] << 8);
1231 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width =
1232 dfp_cap_ext.fields.max_video_h_active_width[0] +
1233 (dfp_cap_ext.fields.max_video_h_active_width[1] << 8);
1234 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height =
1235 dfp_cap_ext.fields.max_video_v_active_height[0] +
1236 (dfp_cap_ext.fields.max_video_v_active_height[1] << 8);
1237 link->dpcd_caps.dongle_caps.dfp_cap_ext.encoding_format_caps =
1238 dfp_cap_ext.fields.encoding_format_caps;
1239 link->dpcd_caps.dongle_caps.dfp_cap_ext.rgb_color_depth_caps =
1240 dfp_cap_ext.fields.rgb_color_depth_caps;
1241 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr444_color_depth_caps =
1242 dfp_cap_ext.fields.ycbcr444_color_depth_caps;
1243 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr422_color_depth_caps =
1244 dfp_cap_ext.fields.ycbcr422_color_depth_caps;
1245 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr420_color_depth_caps =
1246 dfp_cap_ext.fields.ycbcr420_color_depth_caps;
1247 DC_LOG_DP2("DFP capability extension is read at link %d", link->link_index);
1248 DC_LOG_DP2("\tdfp_cap_ext.supported = %s", link->dpcd_caps.dongle_caps.dfp_cap_ext.supported ? "true" : "false");
1249 DC_LOG_DP2("\tdfp_cap_ext.max_pixel_rate_in_mps = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps);
1250 DC_LOG_DP2("\tdfp_cap_ext.max_video_h_active_width = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width);
1251 DC_LOG_DP2("\tdfp_cap_ext.max_video_v_active_height = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height);
1252 }
1253 }
1254
apply_usbc_combo_phy_reset_wa(struct dc_link * link,struct dc_link_settings * link_settings)1255 static void apply_usbc_combo_phy_reset_wa(struct dc_link *link,
1256 struct dc_link_settings *link_settings)
1257 {
1258 /* Temporary Renoir-specific workaround PHY will sometimes be in bad
1259 * state on hotplugging display from certain USB-C dongle, so add extra
1260 * cycle of enabling and disabling the PHY before first link training.
1261 */
1262 struct link_resource link_res = {0};
1263 enum clock_source_id dp_cs_id = get_clock_source_id(link);
1264
1265 dp_enable_link_phy(link, &link_res, link->connector_signal,
1266 dp_cs_id, link_settings);
1267 dp_disable_link_phy(link, &link_res, link->connector_signal);
1268 }
1269
dp_overwrite_extended_receiver_cap(struct dc_link * link)1270 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
1271 {
1272 uint8_t dpcd_data[16] = {0};
1273 uint32_t read_dpcd_retry_cnt = 3;
1274 enum dc_status status = DC_ERROR_UNEXPECTED;
1275 union dp_downstream_port_present ds_port = { 0 };
1276 union down_stream_port_count down_strm_port_count;
1277 union edp_configuration_cap edp_config_cap;
1278
1279 int i;
1280
1281 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1282 status = core_link_read_dpcd(
1283 link,
1284 DP_DPCD_REV,
1285 dpcd_data,
1286 sizeof(dpcd_data));
1287 if (status == DC_OK)
1288 break;
1289 }
1290
1291 link->dpcd_caps.dpcd_rev.raw =
1292 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
1293
1294 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
1295 return false;
1296
1297 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
1298 DP_DPCD_REV];
1299
1300 get_active_converter_info(ds_port.byte, link);
1301
1302 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
1303 DP_DPCD_REV];
1304
1305 link->dpcd_caps.allow_invalid_MSA_timing_param =
1306 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
1307
1308 link->dpcd_caps.max_ln_count.raw = dpcd_data[
1309 DP_MAX_LANE_COUNT - DP_DPCD_REV];
1310
1311 link->dpcd_caps.max_down_spread.raw = dpcd_data[
1312 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
1313
1314 link->reported_link_cap.lane_count =
1315 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
1316 link->reported_link_cap.link_rate = dpcd_data[
1317 DP_MAX_LINK_RATE - DP_DPCD_REV];
1318 link->reported_link_cap.link_spread =
1319 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
1320 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
1321
1322 edp_config_cap.raw = dpcd_data[
1323 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
1324 link->dpcd_caps.panel_mode_edp =
1325 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
1326 link->dpcd_caps.dpcd_display_control_capable =
1327 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
1328
1329 return true;
1330 }
1331
dpcd_set_source_specific_data(struct dc_link * link)1332 void dpcd_set_source_specific_data(struct dc_link *link)
1333 {
1334 if (!link->dc->vendor_signature.is_valid) {
1335 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
1336 struct dpcd_amd_signature amd_signature = {0};
1337 struct dpcd_amd_device_id amd_device_id = {0};
1338
1339 amd_device_id.device_id_byte1 =
1340 (uint8_t)(link->ctx->asic_id.chip_id);
1341 amd_device_id.device_id_byte2 =
1342 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
1343 amd_device_id.dce_version =
1344 (uint8_t)(link->ctx->dce_version);
1345 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
1346 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
1347
1348 core_link_read_dpcd(link, DP_SOURCE_OUI,
1349 (uint8_t *)(&amd_signature),
1350 sizeof(amd_signature));
1351
1352 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
1353 (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
1354 (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
1355
1356 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
1357 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
1358 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
1359
1360 core_link_write_dpcd(link, DP_SOURCE_OUI,
1361 (uint8_t *)(&amd_signature),
1362 sizeof(amd_signature));
1363 }
1364
1365 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
1366 (uint8_t *)(&amd_device_id),
1367 sizeof(amd_device_id));
1368
1369 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
1370 link->dc->caps.min_horizontal_blanking_period != 0) {
1371
1372 uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
1373
1374 result_write_min_hblank = core_link_write_dpcd(link,
1375 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
1376 sizeof(hblank_size));
1377 }
1378 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
1379 WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
1380 "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
1381 result_write_min_hblank,
1382 link->link_index,
1383 link->ctx->dce_version,
1384 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
1385 link->dc->caps.min_horizontal_blanking_period,
1386 link->dpcd_caps.branch_dev_id,
1387 link->dpcd_caps.branch_dev_name[0],
1388 link->dpcd_caps.branch_dev_name[1],
1389 link->dpcd_caps.branch_dev_name[2],
1390 link->dpcd_caps.branch_dev_name[3],
1391 link->dpcd_caps.branch_dev_name[4],
1392 link->dpcd_caps.branch_dev_name[5]);
1393 } else {
1394 core_link_write_dpcd(link, DP_SOURCE_OUI,
1395 link->dc->vendor_signature.data.raw,
1396 sizeof(link->dc->vendor_signature.data.raw));
1397 }
1398 }
1399
dpcd_write_cable_id_to_dprx(struct dc_link * link)1400 void dpcd_write_cable_id_to_dprx(struct dc_link *link)
1401 {
1402 if (!link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED ||
1403 link->dpcd_caps.cable_id.raw == 0 ||
1404 link->dprx_states.cable_id_written)
1405 return;
1406
1407 core_link_write_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX,
1408 &link->dpcd_caps.cable_id.raw,
1409 sizeof(link->dpcd_caps.cable_id.raw));
1410
1411 link->dprx_states.cable_id_written = 1;
1412 }
1413
get_usbc_cable_id(struct dc_link * link,union dp_cable_id * cable_id)1414 static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id)
1415 {
1416 union dmub_rb_cmd cmd;
1417
1418 if (!link->ctx->dmub_srv ||
1419 link->ep_type != DISPLAY_ENDPOINT_PHY ||
1420 link->link_enc->features.flags.bits.DP_IS_USB_C == 0)
1421 return false;
1422
1423 memset(&cmd, 0, sizeof(cmd));
1424 cmd.cable_id.header.type = DMUB_CMD_GET_USBC_CABLE_ID;
1425 cmd.cable_id.header.payload_bytes = sizeof(cmd.cable_id.data);
1426 cmd.cable_id.data.input.phy_inst = resource_transmitter_to_phy_idx(
1427 link->dc, link->link_enc->transmitter);
1428 if (dc_wake_and_execute_dmub_cmd(link->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
1429 cmd.cable_id.header.ret_status == 1) {
1430 cable_id->raw = cmd.cable_id.data.output_raw;
1431 DC_LOG_DC("usbc_cable_id = %d.\n", cable_id->raw);
1432 }
1433 return cmd.cable_id.header.ret_status == 1;
1434 }
1435
retrieve_cable_id(struct dc_link * link)1436 static void retrieve_cable_id(struct dc_link *link)
1437 {
1438 union dp_cable_id usbc_cable_id = {0};
1439
1440 link->dpcd_caps.cable_id.raw = 0;
1441 core_link_read_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX,
1442 &link->dpcd_caps.cable_id.raw, sizeof(uint8_t));
1443
1444 if (get_usbc_cable_id(link, &usbc_cable_id))
1445 link->dpcd_caps.cable_id = intersect_cable_id(
1446 &link->dpcd_caps.cable_id, &usbc_cable_id);
1447 }
1448
read_is_mst_supported(struct dc_link * link)1449 bool read_is_mst_supported(struct dc_link *link)
1450 {
1451 bool mst = false;
1452 enum dc_status st = DC_OK;
1453 union dpcd_rev rev;
1454 union mstm_cap cap;
1455
1456 if (link->preferred_training_settings.mst_enable &&
1457 *link->preferred_training_settings.mst_enable == false) {
1458 return false;
1459 }
1460
1461 rev.raw = 0;
1462 cap.raw = 0;
1463
1464 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
1465 sizeof(rev));
1466
1467 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
1468
1469 st = core_link_read_dpcd(link, DP_MSTM_CAP,
1470 &cap.raw, sizeof(cap));
1471 if (st == DC_OK && cap.bits.MST_CAP == 1)
1472 mst = true;
1473 }
1474 return mst;
1475
1476 }
1477
1478 /* Read additional sink caps defined in source specific DPCD area
1479 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
1480 * TODO: Add FS caps and read from DP_SOURCE_SINK_FS_CAP as well
1481 */
dpcd_read_sink_ext_caps(struct dc_link * link)1482 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
1483 {
1484 uint8_t dpcd_data = 0;
1485 uint8_t edp_general_cap2 = 0;
1486
1487 if (!link)
1488 return false;
1489
1490 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
1491 return false;
1492
1493 link->dpcd_sink_ext_caps.raw = dpcd_data;
1494
1495 if (core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2, &edp_general_cap2, 1) != DC_OK)
1496 return false;
1497
1498 link->dpcd_caps.panel_luminance_control = (edp_general_cap2 & DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE) != 0;
1499
1500 return true;
1501 }
1502
dp_retrieve_lttpr_cap(struct dc_link * link)1503 enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)
1504 {
1505 uint8_t lttpr_dpcd_data[8] = {0};
1506 enum dc_status status;
1507 bool is_lttpr_present;
1508
1509 /* Logic to determine LTTPR support*/
1510 bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
1511
1512 if (!vbios_lttpr_interop || !link->dc->caps.extended_aux_timeout_support)
1513 return DC_NOT_SUPPORTED;
1514
1515 /* By reading LTTPR capability, RX assumes that we will enable
1516 * LTTPR extended aux timeout if LTTPR is present.
1517 */
1518 status = core_link_read_dpcd(
1519 link,
1520 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
1521 lttpr_dpcd_data,
1522 sizeof(lttpr_dpcd_data));
1523
1524 link->dpcd_caps.lttpr_caps.revision.raw =
1525 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
1526 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1527
1528 link->dpcd_caps.lttpr_caps.max_link_rate =
1529 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
1530 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1531
1532 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
1533 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
1534 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1535
1536 link->dpcd_caps.lttpr_caps.max_lane_count =
1537 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
1538 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1539
1540 link->dpcd_caps.lttpr_caps.mode =
1541 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
1542 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1543
1544 link->dpcd_caps.lttpr_caps.max_ext_timeout =
1545 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
1546 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1547 link->dpcd_caps.lttpr_caps.main_link_channel_coding.raw =
1548 lttpr_dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
1549 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1550
1551 link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
1552 lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
1553 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1554
1555 /* If this chip cap is set, at least one retimer must exist in the chain
1556 * Override count to 1 if we receive a known bad count (0 or an invalid value) */
1557 if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
1558 (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == 0)) {
1559 /* If you see this message consistently, either the host platform has FIXED_VS flag
1560 * incorrectly configured or the sink device is returning an invalid count.
1561 */
1562 DC_LOG_ERROR("lttpr_caps phy_repeater_cnt is 0x%x, forcing it to 0x80.",
1563 link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1564 link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 0x80;
1565 DC_LOG_DC("lttpr_caps forced phy_repeater_cnt = %d\n", link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1566 }
1567
1568 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
1569 is_lttpr_present = dp_is_lttpr_present(link);
1570
1571 if (is_lttpr_present)
1572 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
1573
1574 DC_LOG_DC("is_lttpr_present = %d\n", is_lttpr_present);
1575 return status;
1576 }
1577
retrieve_link_cap(struct dc_link * link)1578 static bool retrieve_link_cap(struct dc_link *link)
1579 {
1580 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
1581 * which means size 16 will be good for both of those DPCD register block reads
1582 */
1583 uint8_t dpcd_data[16];
1584 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
1585 */
1586 uint8_t dpcd_dprx_data = '\0';
1587
1588 struct dp_device_vendor_id sink_id;
1589 union down_stream_port_count down_strm_port_count;
1590 union edp_configuration_cap edp_config_cap;
1591 union dp_downstream_port_present ds_port = { 0 };
1592 enum dc_status status = DC_ERROR_UNEXPECTED;
1593 uint32_t read_dpcd_retry_cnt = 3;
1594 int i;
1595 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
1596 const uint32_t post_oui_delay = 30; // 30ms
1597 bool is_fec_supported = false;
1598 bool is_dsc_basic_supported = false;
1599 bool is_dsc_passthrough_supported = false;
1600
1601 memset(dpcd_data, '\0', sizeof(dpcd_data));
1602 memset(&down_strm_port_count,
1603 '\0', sizeof(union down_stream_port_count));
1604 memset(&edp_config_cap, '\0',
1605 sizeof(union edp_configuration_cap));
1606
1607 /* if extended timeout is supported in hardware,
1608 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
1609 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
1610 */
1611 try_to_configure_aux_timeout(link->ddc,
1612 LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
1613
1614 status = dp_retrieve_lttpr_cap(link);
1615
1616 if (status != DC_OK) {
1617 status = wake_up_aux_channel(link);
1618 if (status == DC_OK)
1619 dp_retrieve_lttpr_cap(link);
1620 else
1621 return false;
1622 }
1623
1624 if (dp_is_lttpr_present(link)) {
1625 configure_lttpr_mode_transparent(link);
1626
1627 // Echo TOTAL_LTTPR_CNT back downstream
1628 core_link_write_dpcd(
1629 link,
1630 DP_TOTAL_LTTPR_CNT,
1631 &link->dpcd_caps.lttpr_caps.phy_repeater_cnt,
1632 sizeof(link->dpcd_caps.lttpr_caps.phy_repeater_cnt));
1633 }
1634
1635 /* Read DP tunneling information. */
1636 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
1637 status = dpcd_get_tunneling_device_data(link);
1638 if (status != DC_OK)
1639 dm_error("%s: Read tunneling device data failed.\n", __func__);
1640 }
1641
1642 dpcd_set_source_specific_data(link);
1643 /* Sink may need to configure internals based on vendor, so allow some
1644 * time before proceeding with possibly vendor specific transactions
1645 */
1646 msleep(post_oui_delay);
1647
1648 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1649 status = core_link_read_dpcd(
1650 link,
1651 DP_DPCD_REV,
1652 dpcd_data,
1653 sizeof(dpcd_data));
1654 if (status == DC_OK)
1655 break;
1656 }
1657
1658
1659 if (status != DC_OK) {
1660 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
1661 return false;
1662 }
1663
1664 if (!dp_is_lttpr_present(link))
1665 try_to_configure_aux_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
1666
1667
1668 {
1669 union training_aux_rd_interval aux_rd_interval;
1670
1671 aux_rd_interval.raw =
1672 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
1673
1674 link->dpcd_caps.ext_receiver_cap_field_present =
1675 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
1676
1677 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
1678 uint8_t ext_cap_data[16];
1679
1680 memset(ext_cap_data, '\0', sizeof(ext_cap_data));
1681 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1682 status = core_link_read_dpcd(
1683 link,
1684 DP_DP13_DPCD_REV,
1685 ext_cap_data,
1686 sizeof(ext_cap_data));
1687 if (status == DC_OK) {
1688 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
1689 break;
1690 }
1691 }
1692 if (status != DC_OK)
1693 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
1694 }
1695 }
1696
1697 link->dpcd_caps.dpcd_rev.raw =
1698 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
1699
1700 if (link->dpcd_caps.ext_receiver_cap_field_present) {
1701 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1702 status = core_link_read_dpcd(
1703 link,
1704 DP_DPRX_FEATURE_ENUMERATION_LIST,
1705 &dpcd_dprx_data,
1706 sizeof(dpcd_dprx_data));
1707 if (status == DC_OK)
1708 break;
1709 }
1710
1711 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
1712
1713 if (status != DC_OK)
1714 dm_error("%s: Read DPRX caps data failed.\n", __func__);
1715
1716 /* AdaptiveSyncCapability */
1717 dpcd_dprx_data = 0;
1718 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1719 status = core_link_read_dpcd(
1720 link, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
1721 &dpcd_dprx_data, sizeof(dpcd_dprx_data));
1722 if (status == DC_OK)
1723 break;
1724 }
1725
1726 link->dpcd_caps.adaptive_sync_caps.dp_adap_sync_caps.raw = dpcd_dprx_data;
1727
1728 if (status != DC_OK)
1729 dm_error("%s: Read DPRX caps data failed. Addr:%#x\n",
1730 __func__, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1);
1731 }
1732
1733 else {
1734 link->dpcd_caps.dprx_feature.raw = 0;
1735 }
1736
1737
1738 /* Error condition checking...
1739 * It is impossible for Sink to report Max Lane Count = 0.
1740 * It is possible for Sink to report Max Link Rate = 0, if it is
1741 * an eDP device that is reporting specialized link rates in the
1742 * SUPPORTED_LINK_RATE table.
1743 */
1744 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
1745 return false;
1746
1747 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
1748 DP_DPCD_REV];
1749
1750 read_dp_device_vendor_id(link);
1751
1752 /* TODO - decouple raw mst capability from policy decision */
1753 link->dpcd_caps.is_mst_capable = read_is_mst_supported(link);
1754 DC_LOG_DC("%s: MST_Support: %s\n", __func__, str_yes_no(link->dpcd_caps.is_mst_capable));
1755
1756 get_active_converter_info(ds_port.byte, link);
1757
1758 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
1759
1760 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
1761 DP_DPCD_REV];
1762
1763 link->dpcd_caps.allow_invalid_MSA_timing_param =
1764 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
1765
1766 link->dpcd_caps.max_ln_count.raw = dpcd_data[
1767 DP_MAX_LANE_COUNT - DP_DPCD_REV];
1768
1769 link->dpcd_caps.max_down_spread.raw = dpcd_data[
1770 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
1771
1772 link->reported_link_cap.lane_count =
1773 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
1774 link->reported_link_cap.link_rate = get_link_rate_from_max_link_bw(
1775 dpcd_data[DP_MAX_LINK_RATE - DP_DPCD_REV]);
1776 link->reported_link_cap.link_spread =
1777 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
1778 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
1779
1780 edp_config_cap.raw = dpcd_data[
1781 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
1782 link->dpcd_caps.panel_mode_edp =
1783 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
1784 link->dpcd_caps.dpcd_display_control_capable =
1785 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
1786 link->dpcd_caps.channel_coding_cap.raw =
1787 dpcd_data[DP_MAIN_LINK_CHANNEL_CODING - DP_DPCD_REV];
1788 link->test_pattern_enabled = false;
1789 link->compliance_test_state.raw = 0;
1790
1791 /* read sink count */
1792 core_link_read_dpcd(link,
1793 DP_SINK_COUNT,
1794 &link->dpcd_caps.sink_count.raw,
1795 sizeof(link->dpcd_caps.sink_count.raw));
1796
1797 /* read sink ieee oui */
1798 core_link_read_dpcd(link,
1799 DP_SINK_OUI,
1800 (uint8_t *)(&sink_id),
1801 sizeof(sink_id));
1802
1803 link->dpcd_caps.sink_dev_id =
1804 (sink_id.ieee_oui[0] << 16) +
1805 (sink_id.ieee_oui[1] << 8) +
1806 (sink_id.ieee_oui[2]);
1807
1808 memmove(
1809 link->dpcd_caps.sink_dev_id_str,
1810 sink_id.ieee_device_id,
1811 sizeof(sink_id.ieee_device_id));
1812
1813 core_link_read_dpcd(
1814 link,
1815 DP_SINK_HW_REVISION_START,
1816 (uint8_t *)&dp_hw_fw_revision,
1817 sizeof(dp_hw_fw_revision));
1818
1819 link->dpcd_caps.sink_hw_revision =
1820 dp_hw_fw_revision.ieee_hw_rev;
1821
1822 memmove(
1823 link->dpcd_caps.sink_fw_revision,
1824 dp_hw_fw_revision.ieee_fw_rev,
1825 sizeof(dp_hw_fw_revision.ieee_fw_rev));
1826
1827 /* Quirk for Retina panels: wrong DP_MAX_LINK_RATE */
1828 {
1829 uint8_t str_mbp_2018[] = { 101, 68, 21, 103, 98, 97 };
1830 uint8_t fwrev_mbp_2018[] = { 7, 4 };
1831 uint8_t fwrev_mbp_2018_vega[] = { 8, 4 };
1832
1833 /* We also check for the firmware revision as 16,1 models have an
1834 * identical device id and are incorrectly quirked otherwise.
1835 */
1836 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
1837 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2018,
1838 sizeof(str_mbp_2018)) &&
1839 (!memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018,
1840 sizeof(fwrev_mbp_2018)) ||
1841 !memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018_vega,
1842 sizeof(fwrev_mbp_2018_vega)))) {
1843 link->reported_link_cap.link_rate = LINK_RATE_RBR2;
1844 }
1845 }
1846
1847 memset(&link->dpcd_caps.dsc_caps, '\0',
1848 sizeof(link->dpcd_caps.dsc_caps));
1849 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
1850 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
1851 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
1852 status = core_link_read_dpcd(
1853 link,
1854 DP_FEC_CAPABILITY,
1855 &link->dpcd_caps.fec_cap.raw,
1856 sizeof(link->dpcd_caps.fec_cap.raw));
1857 if (status != DC_OK)
1858 DC_LOG_ERROR("%s:%d: core_link_read_dpcd (DP_FEC_CAPABILITY) failed\n", __func__, __LINE__);
1859
1860 status = core_link_read_dpcd(
1861 link,
1862 DP_DSC_SUPPORT,
1863 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
1864 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
1865 if (status == DC_OK) {
1866 is_fec_supported = link->dpcd_caps.fec_cap.bits.FEC_CAPABLE;
1867 is_dsc_basic_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT;
1868 is_dsc_passthrough_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT;
1869 DC_LOG_DC("%s: FEC_Sink_Support: %s\n", __func__,
1870 str_yes_no(is_fec_supported));
1871 DC_LOG_DC("%s: DSC_Basic_Sink_Support: %s\n", __func__,
1872 str_yes_no(is_dsc_basic_supported));
1873 DC_LOG_DC("%s: DSC_Passthrough_Sink_Support: %s\n", __func__,
1874 str_yes_no(is_dsc_passthrough_supported));
1875 }
1876 if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {
1877 status = core_link_read_dpcd(
1878 link,
1879 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
1880 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
1881 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
1882 if (status != DC_OK)
1883 DC_LOG_ERROR("%s:%d: core_link_read_dpcd (DP_DSC_BRANCH_OVERALL_THROUGHPUT_0) failed\n", __func__, __LINE__);
1884
1885 DC_LOG_DSC("DSC branch decoder capability is read at link %d", link->link_index);
1886 DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_0 = 0x%02x",
1887 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_0);
1888 DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_1 = 0x%02x",
1889 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_1);
1890 DC_LOG_DSC("\tBRANCH_MAX_LINE_WIDTH 0x%02x",
1891 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_MAX_LINE_WIDTH);
1892 }
1893
1894 /* Apply work around to disable FEC and DSC for USB4 tunneling in TBT3 compatibility mode
1895 * only if required.
1896 */
1897 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
1898 link->dc->debug.dpia_debug.bits.enable_force_tbt3_work_around &&
1899 link->dpcd_caps.is_branch_dev &&
1900 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
1901 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 &&
1902 (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE ||
1903 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT)) {
1904 /* A TBT3 device is expected to report no support for FEC or DSC to a USB4 DPIA.
1905 * Clear FEC and DSC capabilities as a work around if that is not the case.
1906 */
1907 link->wa_flags.dpia_forced_tbt3_mode = true;
1908 memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps));
1909 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
1910 DC_LOG_DSC("Clear DSC SUPPORT for USB4 link(%d) in TBT3 compatibility mode", link->link_index);
1911 } else
1912 link->wa_flags.dpia_forced_tbt3_mode = false;
1913 }
1914
1915 if (!dpcd_read_sink_ext_caps(link))
1916 link->dpcd_sink_ext_caps.raw = 0;
1917
1918 if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
1919 DC_LOG_DP2("128b/132b encoding is supported at link %d", link->link_index);
1920
1921 core_link_read_dpcd(link,
1922 DP_128B132B_SUPPORTED_LINK_RATES,
1923 &link->dpcd_caps.dp_128b_132b_supported_link_rates.raw,
1924 sizeof(link->dpcd_caps.dp_128b_132b_supported_link_rates.raw));
1925 if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR20)
1926 link->reported_link_cap.link_rate = LINK_RATE_UHBR20;
1927 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5)
1928 link->reported_link_cap.link_rate = LINK_RATE_UHBR13_5;
1929 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR10)
1930 link->reported_link_cap.link_rate = LINK_RATE_UHBR10;
1931 else
1932 dm_error("%s: Invalid RX 128b_132b_supported_link_rates\n", __func__);
1933 DC_LOG_DP2("128b/132b supported link rates is read at link %d", link->link_index);
1934 DC_LOG_DP2("\tmax 128b/132b link rate support is %d.%d GHz",
1935 link->reported_link_cap.link_rate / 100,
1936 link->reported_link_cap.link_rate % 100);
1937
1938 core_link_read_dpcd(link,
1939 DP_SINK_VIDEO_FALLBACK_FORMATS,
1940 &link->dpcd_caps.fallback_formats.raw,
1941 sizeof(link->dpcd_caps.fallback_formats.raw));
1942 DC_LOG_DP2("sink video fallback format is read at link %d", link->link_index);
1943 if (link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support)
1944 DC_LOG_DP2("\t1920x1080@60Hz 24bpp fallback format supported");
1945 if (link->dpcd_caps.fallback_formats.bits.dp_1280x720_60Hz_24bpp_support)
1946 DC_LOG_DP2("\t1280x720@60Hz 24bpp fallback format supported");
1947 if (link->dpcd_caps.fallback_formats.bits.dp_1024x768_60Hz_24bpp_support)
1948 DC_LOG_DP2("\t1024x768@60Hz 24bpp fallback format supported");
1949 if (link->dpcd_caps.fallback_formats.raw == 0) {
1950 DC_LOG_DP2("\tno supported fallback formats, assume 1920x1080@60Hz 24bpp is supported");
1951 link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support = 1;
1952 }
1953
1954 core_link_read_dpcd(link,
1955 DP_FEC_CAPABILITY_1,
1956 &link->dpcd_caps.fec_cap1.raw,
1957 sizeof(link->dpcd_caps.fec_cap1.raw));
1958 DC_LOG_DP2("FEC CAPABILITY 1 is read at link %d", link->link_index);
1959 if (link->dpcd_caps.fec_cap1.bits.AGGREGATED_ERROR_COUNTERS_CAPABLE)
1960 DC_LOG_DP2("\tFEC aggregated error counters are supported");
1961 }
1962
1963 core_link_read_dpcd(link,
1964 DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP,
1965 link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw,
1966 sizeof(link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw));
1967
1968 retrieve_cable_id(link);
1969 dpcd_write_cable_id_to_dprx(link);
1970
1971 /* Connectivity log: detection */
1972 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
1973
1974 return true;
1975 }
1976
detect_dp_sink_caps(struct dc_link * link)1977 bool detect_dp_sink_caps(struct dc_link *link)
1978 {
1979 return retrieve_link_cap(link);
1980 }
1981
detect_edp_sink_caps(struct dc_link * link)1982 void detect_edp_sink_caps(struct dc_link *link)
1983 {
1984 uint8_t supported_link_rates[16];
1985 uint32_t entry;
1986 uint32_t link_rate_in_khz;
1987 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
1988 uint8_t backlight_adj_cap = 0;
1989 uint8_t general_edp_cap = 0;
1990
1991 retrieve_link_cap(link);
1992 link->dpcd_caps.edp_supported_link_rates_count = 0;
1993 memset(supported_link_rates, 0, sizeof(supported_link_rates));
1994
1995 /*
1996 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
1997 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
1998 */
1999 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13) {
2000 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
2001 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
2002 supported_link_rates, sizeof(supported_link_rates));
2003
2004 for (entry = 0; entry < 16; entry += 2) {
2005 // DPCD register reports per-lane link rate = 16-bit link rate capability
2006 // value X 200 kHz. Need multiplier to find link rate in kHz.
2007 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
2008 supported_link_rates[entry]) * 200;
2009
2010 DC_LOG_DC("%s: eDP v1.4 supported sink rates: [%d] %d kHz\n", __func__,
2011 entry / 2, link_rate_in_khz);
2012
2013 if (link_rate_in_khz != 0) {
2014 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
2015 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
2016 link->dpcd_caps.edp_supported_link_rates_count++;
2017 }
2018 }
2019 }
2020
2021 core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
2022 &backlight_adj_cap, sizeof(backlight_adj_cap));
2023
2024 link->dpcd_caps.dynamic_backlight_capable_edp =
2025 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
2026
2027 core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_1,
2028 &general_edp_cap, sizeof(general_edp_cap));
2029
2030 link->dpcd_caps.set_power_state_capable_edp =
2031 (general_edp_cap & DP_EDP_SET_POWER_CAP) ? true:false;
2032
2033 set_default_brightness_aux(link);
2034
2035 core_link_read_dpcd(link, DP_EDP_DPCD_REV,
2036 &link->dpcd_caps.edp_rev,
2037 sizeof(link->dpcd_caps.edp_rev));
2038 /*
2039 * PSR is only valid for eDP v1.3 or higher.
2040 */
2041 if (link->dpcd_caps.edp_rev >= DP_EDP_13) {
2042 core_link_read_dpcd(link, DP_PSR_SUPPORT,
2043 &link->dpcd_caps.psr_info.psr_version,
2044 sizeof(link->dpcd_caps.psr_info.psr_version));
2045 if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8)
2046 core_link_read_dpcd(link, DP_FORCE_PSRSU_CAPABILITY,
2047 &link->dpcd_caps.psr_info.force_psrsu_cap,
2048 sizeof(link->dpcd_caps.psr_info.force_psrsu_cap));
2049 core_link_read_dpcd(link, DP_PSR_CAPS,
2050 &link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
2051 sizeof(link->dpcd_caps.psr_info.psr_dpcd_caps.raw));
2052 if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) {
2053 core_link_read_dpcd(link, DP_PSR2_SU_Y_GRANULARITY,
2054 &link->dpcd_caps.psr_info.psr2_su_y_granularity_cap,
2055 sizeof(link->dpcd_caps.psr_info.psr2_su_y_granularity_cap));
2056 }
2057 }
2058
2059 /*
2060 * ALPM is only valid for eDP v1.4 or higher.
2061 */
2062 if (link->dpcd_caps.dpcd_rev.raw >= DP_EDP_14)
2063 core_link_read_dpcd(link, DP_RECEIVER_ALPM_CAP,
2064 &link->dpcd_caps.alpm_caps.raw,
2065 sizeof(link->dpcd_caps.alpm_caps.raw));
2066
2067 /*
2068 * Read REPLAY info
2069 */
2070 core_link_read_dpcd(link, DP_SINK_PR_PIXEL_DEVIATION_PER_LINE,
2071 &link->dpcd_caps.pr_info.pixel_deviation_per_line,
2072 sizeof(link->dpcd_caps.pr_info.pixel_deviation_per_line));
2073 core_link_read_dpcd(link, DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE,
2074 &link->dpcd_caps.pr_info.max_deviation_line,
2075 sizeof(link->dpcd_caps.pr_info.max_deviation_line));
2076
2077 /*
2078 * OLED Emission Rate info
2079 */
2080 if (link->dpcd_sink_ext_caps.bits.emission_output)
2081 core_link_read_dpcd(link, DP_SINK_EMISSION_RATE,
2082 (uint8_t *)&link->dpcd_caps.edp_oled_emission_rate,
2083 sizeof(link->dpcd_caps.edp_oled_emission_rate));
2084 }
2085
dp_get_max_link_enc_cap(const struct dc_link * link,struct dc_link_settings * max_link_enc_cap)2086 bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
2087 {
2088 struct link_encoder *link_enc = NULL;
2089
2090 if (!max_link_enc_cap) {
2091 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
2092 return false;
2093 }
2094
2095 link_enc = link_enc_cfg_get_link_enc(link);
2096 ASSERT(link_enc);
2097
2098 if (link_enc && link_enc->funcs->get_max_link_cap) {
2099 link_enc->funcs->get_max_link_cap(link_enc, max_link_enc_cap);
2100 return true;
2101 }
2102
2103 DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
2104 max_link_enc_cap->lane_count = 1;
2105 max_link_enc_cap->link_rate = 6;
2106 return false;
2107 }
2108
dp_get_verified_link_cap(const struct dc_link * link)2109 const struct dc_link_settings *dp_get_verified_link_cap(
2110 const struct dc_link *link)
2111 {
2112 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
2113 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
2114 return &link->preferred_link_setting;
2115 return &link->verified_link_cap;
2116 }
2117
dp_get_max_link_cap(struct dc_link * link)2118 struct dc_link_settings dp_get_max_link_cap(struct dc_link *link)
2119 {
2120 struct dc_link_settings max_link_cap = {0};
2121 enum dc_link_rate lttpr_max_link_rate;
2122 enum dc_link_rate cable_max_link_rate;
2123 struct link_encoder *link_enc = NULL;
2124 bool is_uhbr13_5_supported = true;
2125
2126 link_enc = link_enc_cfg_get_link_enc(link);
2127 ASSERT(link_enc);
2128
2129 /* get max link encoder capability */
2130 if (link_enc)
2131 link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap);
2132
2133 /* Lower link settings based on sink's link cap */
2134 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
2135 max_link_cap.lane_count =
2136 link->reported_link_cap.lane_count;
2137 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
2138 max_link_cap.link_rate =
2139 link->reported_link_cap.link_rate;
2140 if (link->reported_link_cap.link_spread <
2141 max_link_cap.link_spread)
2142 max_link_cap.link_spread =
2143 link->reported_link_cap.link_spread;
2144
2145 if (!link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5)
2146 is_uhbr13_5_supported = false;
2147
2148 /* Lower link settings based on cable attributes
2149 * Cable ID is a DP2 feature to identify max certified link rate that
2150 * a cable can carry. The cable identification method requires both
2151 * cable and display hardware support. Since the specs comes late, it is
2152 * anticipated that the first round of DP2 cables and displays may not
2153 * be fully compatible to reliably return cable ID data. Therefore the
2154 * decision of our cable id policy is that if the cable can return non
2155 * zero cable id data, we will take cable's link rate capability into
2156 * account. However if we get zero data, the cable link rate capability
2157 * is considered inconclusive. In this case, we will not take cable's
2158 * capability into account to avoid of over limiting hardware capability
2159 * from users. The max overall link rate capability is still determined
2160 * after actual dp pre-training. Cable id is considered as an auxiliary
2161 * method of determining max link bandwidth capability.
2162 */
2163 cable_max_link_rate = get_cable_max_link_rate(link);
2164
2165 if (!link->dc->debug.ignore_cable_id &&
2166 cable_max_link_rate != LINK_RATE_UNKNOWN) {
2167 if (cable_max_link_rate < max_link_cap.link_rate)
2168 max_link_cap.link_rate = cable_max_link_rate;
2169
2170 if (!link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY &&
2171 link->dpcd_caps.cable_id.bits.CABLE_TYPE >= 2)
2172 is_uhbr13_5_supported = false;
2173 }
2174
2175 /* account for lttpr repeaters cap
2176 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2177 */
2178 if (dp_is_lttpr_present(link)) {
2179
2180 /* Some LTTPR devices do not report valid DPCD revisions, if so, do not take it's link cap into consideration. */
2181 if (link->dpcd_caps.lttpr_caps.revision.raw >= DPCD_REV_14) {
2182 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2183 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2184 lttpr_max_link_rate = get_lttpr_max_link_rate(link);
2185
2186 if (lttpr_max_link_rate < max_link_cap.link_rate)
2187 max_link_cap.link_rate = lttpr_max_link_rate;
2188
2189 if (!link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)
2190 is_uhbr13_5_supported = false;
2191 }
2192
2193 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n",
2194 __func__,
2195 max_link_cap.lane_count,
2196 max_link_cap.link_rate);
2197 }
2198
2199 if (max_link_cap.link_rate == LINK_RATE_UHBR13_5 &&
2200 !is_uhbr13_5_supported)
2201 max_link_cap.link_rate = LINK_RATE_UHBR10;
2202
2203 if (link_dp_get_encoding_format(&max_link_cap) == DP_128b_132b_ENCODING &&
2204 link->dc->debug.disable_uhbr)
2205 max_link_cap.link_rate = LINK_RATE_HIGH3;
2206
2207 return max_link_cap;
2208 }
2209
dp_verify_link_cap(struct dc_link * link,struct dc_link_settings * known_limit_link_setting,int * fail_count)2210 static bool dp_verify_link_cap(
2211 struct dc_link *link,
2212 struct dc_link_settings *known_limit_link_setting,
2213 int *fail_count)
2214 {
2215 struct dc_link_settings cur_link_settings = {0};
2216 struct dc_link_settings max_link_settings = *known_limit_link_setting;
2217 bool success = false;
2218 bool skip_video_pattern;
2219 enum clock_source_id dp_cs_id = get_clock_source_id(link);
2220 enum link_training_result status = LINK_TRAINING_SUCCESS;
2221 union hpd_irq_data irq_data;
2222 struct link_resource link_res;
2223
2224 memset(&irq_data, 0, sizeof(irq_data));
2225 cur_link_settings = max_link_settings;
2226
2227 /* Grant extended timeout request */
2228 if (dp_is_lttpr_present(link) && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
2229 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2230
2231 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2232 }
2233
2234 do {
2235 if (!get_temp_dp_link_res(link, &link_res, &cur_link_settings))
2236 continue;
2237
2238 skip_video_pattern = cur_link_settings.link_rate != LINK_RATE_LOW;
2239 dp_enable_link_phy(
2240 link,
2241 &link_res,
2242 link->connector_signal,
2243 dp_cs_id,
2244 &cur_link_settings);
2245
2246 status = dp_perform_link_training(
2247 link,
2248 &link_res,
2249 &cur_link_settings,
2250 skip_video_pattern);
2251
2252 if (status == LINK_TRAINING_SUCCESS) {
2253 success = true;
2254 fsleep(1000);
2255 if (dp_read_hpd_rx_irq_data(link, &irq_data) == DC_OK &&
2256 dp_parse_link_loss_status(
2257 link,
2258 &irq_data))
2259 (*fail_count)++;
2260 } else if (status == LINK_TRAINING_LINK_LOSS) {
2261 success = true;
2262 (*fail_count)++;
2263 } else {
2264 (*fail_count)++;
2265 }
2266 dp_trace_lt_total_count_increment(link, true);
2267 dp_trace_lt_result_update(link, status, true);
2268 dp_disable_link_phy(link, &link_res, link->connector_signal);
2269 } while (!success && decide_fallback_link_setting(link,
2270 &max_link_settings, &cur_link_settings, status));
2271
2272 link->verified_link_cap = success ?
2273 cur_link_settings : fail_safe_link_settings;
2274 return success;
2275 }
2276
dp_verify_link_cap_with_retries(struct dc_link * link,struct dc_link_settings * known_limit_link_setting,int attempts)2277 bool dp_verify_link_cap_with_retries(
2278 struct dc_link *link,
2279 struct dc_link_settings *known_limit_link_setting,
2280 int attempts)
2281 {
2282 int i = 0;
2283 bool success = false;
2284 int fail_count = 0;
2285 struct dc_link_settings last_verified_link_cap = fail_safe_link_settings;
2286
2287 dp_trace_detect_lt_init(link);
2288
2289 if (link->link_enc && link->link_enc->features.flags.bits.DP_IS_USB_C &&
2290 link->dc->debug.usbc_combo_phy_reset_wa)
2291 apply_usbc_combo_phy_reset_wa(link, known_limit_link_setting);
2292
2293 dp_trace_set_lt_start_timestamp(link, false);
2294 for (i = 0; i < attempts; i++) {
2295 enum dc_connection_type type = dc_connection_none;
2296
2297 memset(&link->verified_link_cap, 0,
2298 sizeof(struct dc_link_settings));
2299 if (link->link_enc && (!link_detect_connection_type(link, &type) || type == dc_connection_none)) {
2300 link->verified_link_cap = fail_safe_link_settings;
2301 break;
2302 } else if (dp_verify_link_cap(link, known_limit_link_setting, &fail_count)) {
2303 last_verified_link_cap = link->verified_link_cap;
2304 if (fail_count == 0) {
2305 success = true;
2306 break;
2307 }
2308 } else {
2309 link->verified_link_cap = last_verified_link_cap;
2310 }
2311 fsleep(10 * 1000);
2312 }
2313
2314 dp_trace_lt_fail_count_update(link, fail_count, true);
2315 dp_trace_set_lt_end_timestamp(link, true);
2316
2317 return success;
2318 }
2319
2320 /*
2321 * Check if there is a native DP or passive DP-HDMI dongle connected
2322 */
dp_is_sink_present(struct dc_link * link)2323 bool dp_is_sink_present(struct dc_link *link)
2324 {
2325 enum gpio_result gpio_result;
2326 uint32_t clock_pin = 0;
2327 uint8_t retry = 0;
2328 struct ddc *ddc;
2329
2330 enum connector_id connector_id =
2331 dal_graphics_object_id_get_connector_id(link->link_id);
2332
2333 bool present =
2334 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
2335 (connector_id == CONNECTOR_ID_EDP) ||
2336 (connector_id == CONNECTOR_ID_USBC));
2337
2338 ddc = get_ddc_pin(link->ddc);
2339
2340 if (!ddc) {
2341 BREAK_TO_DEBUGGER();
2342 return present;
2343 }
2344
2345 /* Open GPIO and set it to I2C mode */
2346 /* Note: this GpioMode_Input will be converted
2347 * to GpioConfigType_I2cAuxDualMode in GPIO component,
2348 * which indicates we need additional delay
2349 */
2350
2351 if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
2352 GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
2353 dal_ddc_close(ddc);
2354
2355 return present;
2356 }
2357
2358 /*
2359 * Read GPIO: DP sink is present if both clock and data pins are zero
2360 *
2361 * [W/A] plug-unplug DP cable, sometimes customer board has
2362 * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
2363 * then monitor can't br light up. Add retry 3 times
2364 * But in real passive dongle, it need additional 3ms to detect
2365 */
2366 do {
2367 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
2368 ASSERT(gpio_result == GPIO_RESULT_OK);
2369 if (clock_pin)
2370 fsleep(1000);
2371 else
2372 break;
2373 } while (retry++ < 3);
2374
2375 present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
2376
2377 dal_ddc_close(ddc);
2378
2379 return present;
2380 }
2381