1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v13_0.h"
35 #include "smu13_driver_if_v13_0_0.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "smu_v13_0_0_ppt.h"
39 #include "smu_v13_0_0_pptable.h"
40 #include "smu_v13_0_0_ppsmc.h"
41 #include "nbio/nbio_4_3_0_offset.h"
42 #include "nbio/nbio_4_3_0_sh_mask.h"
43 #include "mp/mp_13_0_0_offset.h"
44 #include "mp/mp_13_0_0_sh_mask.h"
45
46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
47 #include "smu_cmn.h"
48 #include "amdgpu_ras.h"
49
50 /*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61
62 #define FEATURE_MASK(feature) (1ULL << feature)
63 #define SMC_DPM_FEATURE ( \
64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
70
71 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
72
73 #define mmMP1_SMN_C2PMSG_66 0x0282
74 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
75
76 #define mmMP1_SMN_C2PMSG_82 0x0292
77 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
78
79 #define mmMP1_SMN_C2PMSG_90 0x029a
80 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
81
82 #define mmMP1_SMN_C2PMSG_75 0x028b
83 #define mmMP1_SMN_C2PMSG_75_BASE_IDX 0
84
85 #define mmMP1_SMN_C2PMSG_53 0x0275
86 #define mmMP1_SMN_C2PMSG_53_BASE_IDX 0
87
88 #define mmMP1_SMN_C2PMSG_54 0x0276
89 #define mmMP1_SMN_C2PMSG_54_BASE_IDX 0
90
91 #define DEBUGSMC_MSG_Mode1Reset 2
92
93 /*
94 * SMU_v13_0_10 supports ECCTABLE since version 80.34.0,
95 * use this to check ECCTABLE feature whether support
96 */
97 #define SUPPORT_ECCTABLE_SMU_13_0_10_VERSION 0x00502200
98
99 #define PP_OD_FEATURE_GFXCLK_FMIN 0
100 #define PP_OD_FEATURE_GFXCLK_FMAX 1
101 #define PP_OD_FEATURE_UCLK_FMIN 2
102 #define PP_OD_FEATURE_UCLK_FMAX 3
103 #define PP_OD_FEATURE_GFX_VF_CURVE 4
104 #define PP_OD_FEATURE_FAN_CURVE_TEMP 5
105 #define PP_OD_FEATURE_FAN_CURVE_PWM 6
106 #define PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT 7
107 #define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET 8
108 #define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE 9
109 #define PP_OD_FEATURE_FAN_MINIMUM_PWM 10
110 #define PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE 11
111 #define PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP 12
112
113 #define LINK_SPEED_MAX 3
114
115 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = {
116 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
117 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
118 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
119 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
120 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
121 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
122 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
123 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
124 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
125 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
126 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
127 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
128 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
129 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 0),
130 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
131 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
132 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
133 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
134 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
135 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
136 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
137 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
138 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
139 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
140 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
141 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
142 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
143 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0),
144 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
145 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
146 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
147 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
148 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
149 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
150 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
151 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
152 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 0),
153 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
154 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
155 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
156 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
157 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
158 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
159 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
160 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
161 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
162 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
163 MSG_MAP(Mode2Reset, PPSMC_MSG_Mode2Reset, 0),
164 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
165 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
166 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
167 MSG_MAP(SetNumBadMemoryPagesRetired, PPSMC_MSG_SetNumBadMemoryPagesRetired, 0),
168 MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel,
169 PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 0),
170 MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0),
171 MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0),
172 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
173 MSG_MAP(DALNotPresent, PPSMC_MSG_DALNotPresent, 0),
174 MSG_MAP(EnableUCLKShadow, PPSMC_MSG_EnableUCLKShadow, 0),
175 };
176
177 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
178 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
179 CLK_MAP(SCLK, PPCLK_GFXCLK),
180 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
181 CLK_MAP(FCLK, PPCLK_FCLK),
182 CLK_MAP(UCLK, PPCLK_UCLK),
183 CLK_MAP(MCLK, PPCLK_UCLK),
184 CLK_MAP(VCLK, PPCLK_VCLK_0),
185 CLK_MAP(VCLK1, PPCLK_VCLK_1),
186 CLK_MAP(DCLK, PPCLK_DCLK_0),
187 CLK_MAP(DCLK1, PPCLK_DCLK_1),
188 CLK_MAP(DCEFCLK, PPCLK_DCFCLK),
189 };
190
191 static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] = {
192 FEA_MAP(FW_DATA_READ),
193 FEA_MAP(DPM_GFXCLK),
194 FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
195 FEA_MAP(DPM_UCLK),
196 FEA_MAP(DPM_FCLK),
197 FEA_MAP(DPM_SOCCLK),
198 FEA_MAP(DPM_MP0CLK),
199 FEA_MAP(DPM_LINK),
200 FEA_MAP(DPM_DCN),
201 FEA_MAP(VMEMP_SCALING),
202 FEA_MAP(VDDIO_MEM_SCALING),
203 FEA_MAP(DS_GFXCLK),
204 FEA_MAP(DS_SOCCLK),
205 FEA_MAP(DS_FCLK),
206 FEA_MAP(DS_LCLK),
207 FEA_MAP(DS_DCFCLK),
208 FEA_MAP(DS_UCLK),
209 FEA_MAP(GFX_ULV),
210 FEA_MAP(FW_DSTATE),
211 FEA_MAP(GFXOFF),
212 FEA_MAP(BACO),
213 FEA_MAP(MM_DPM),
214 FEA_MAP(SOC_MPCLK_DS),
215 FEA_MAP(BACO_MPCLK_DS),
216 FEA_MAP(THROTTLERS),
217 FEA_MAP(SMARTSHIFT),
218 FEA_MAP(GTHR),
219 FEA_MAP(ACDC),
220 FEA_MAP(VR0HOT),
221 FEA_MAP(FW_CTF),
222 FEA_MAP(FAN_CONTROL),
223 FEA_MAP(GFX_DCS),
224 FEA_MAP(GFX_READ_MARGIN),
225 FEA_MAP(LED_DISPLAY),
226 FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
227 FEA_MAP(OUT_OF_BAND_MONITOR),
228 FEA_MAP(OPTIMIZED_VMIN),
229 FEA_MAP(GFX_IMU),
230 FEA_MAP(BOOT_TIME_CAL),
231 FEA_MAP(GFX_PCC_DFLL),
232 FEA_MAP(SOC_CG),
233 FEA_MAP(DF_CSTATE),
234 FEA_MAP(GFX_EDC),
235 FEA_MAP(BOOT_POWER_OPT),
236 FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
237 FEA_MAP(DS_VCN),
238 FEA_MAP(BACO_CG),
239 FEA_MAP(MEM_TEMP_READ),
240 FEA_MAP(ATHUB_MMHUB_PG),
241 FEA_MAP(SOC_PCC),
242 [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
243 [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
244 [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
245 };
246
247 static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
248 TAB_MAP(PPTABLE),
249 TAB_MAP(WATERMARKS),
250 TAB_MAP(AVFS_PSM_DEBUG),
251 TAB_MAP(PMSTATUSLOG),
252 TAB_MAP(SMU_METRICS),
253 TAB_MAP(DRIVER_SMU_CONFIG),
254 TAB_MAP(ACTIVITY_MONITOR_COEFF),
255 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
256 TAB_MAP(I2C_COMMANDS),
257 TAB_MAP(ECCINFO),
258 TAB_MAP(OVERDRIVE),
259 TAB_MAP(WIFIBAND),
260 };
261
262 static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
263 PWR_MAP(AC),
264 PWR_MAP(DC),
265 };
266
267 static struct cmn2asic_mapping smu_v13_0_0_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
268 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
269 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
270 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
271 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
272 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
273 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
274 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
275 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT),
276 };
277
278 static const uint8_t smu_v13_0_0_throttler_map[] = {
279 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
280 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
281 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
282 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
283 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
284 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
285 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
286 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
287 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
288 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
289 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
290 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
291 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
292 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
293 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
294 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT),
295 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
296 };
297
298 static int
smu_v13_0_0_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)299 smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
300 uint32_t *feature_mask, uint32_t num)
301 {
302 struct amdgpu_device *adev = smu->adev;
303
304 if (num > 2)
305 return -EINVAL;
306
307 memset(feature_mask, 0xff, sizeof(uint32_t) * num);
308
309 if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) {
310 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
311 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT);
312 }
313
314 if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) ||
315 !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
316 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
317
318 if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK))
319 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
320
321 /* PMFW 78.58 contains a critical fix for gfxoff feature */
322 if ((smu->smc_fw_version < 0x004e3a00) ||
323 !(adev->pm.pp_feature & PP_GFXOFF_MASK))
324 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT);
325
326 if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
327 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
328 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
329 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
330 }
331
332 if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK))
333 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
334
335 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
336 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT);
337 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT);
338 }
339
340 if (!(adev->pm.pp_feature & PP_ULV_MASK))
341 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT);
342
343 return 0;
344 }
345
smu_v13_0_0_check_powerplay_table(struct smu_context * smu)346 static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu)
347 {
348 struct smu_table_context *table_context = &smu->smu_table;
349 struct smu_13_0_0_powerplay_table *powerplay_table =
350 table_context->power_play_table;
351 struct smu_baco_context *smu_baco = &smu->smu_baco;
352 PPTable_t *pptable = smu->smu_table.driver_pptable;
353 const OverDriveLimits_t * const overdrive_upperlimits =
354 &pptable->SkuTable.OverDriveLimitsBasicMax;
355 const OverDriveLimits_t * const overdrive_lowerlimits =
356 &pptable->SkuTable.OverDriveLimitsMin;
357
358 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC)
359 smu->dc_controlled_by_gpio = true;
360
361 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO) {
362 smu_baco->platform_support = true;
363
364 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO)
365 smu_baco->maco_support = true;
366 }
367
368 if (!overdrive_lowerlimits->FeatureCtrlMask ||
369 !overdrive_upperlimits->FeatureCtrlMask)
370 smu->od_enabled = false;
371
372 table_context->thermal_controller_type =
373 powerplay_table->thermal_controller_type;
374
375 /*
376 * Instead of having its own buffer space and get overdrive_table copied,
377 * smu->od_settings just points to the actual overdrive_table
378 */
379 smu->od_settings = &powerplay_table->overdrive_table;
380
381 smu->adev->pm.no_fan =
382 !(pptable->SkuTable.FeaturesToRun[0] & (1 << FEATURE_FAN_CONTROL_BIT));
383
384 return 0;
385 }
386
smu_v13_0_0_store_powerplay_table(struct smu_context * smu)387 static int smu_v13_0_0_store_powerplay_table(struct smu_context *smu)
388 {
389 struct smu_table_context *table_context = &smu->smu_table;
390 struct smu_13_0_0_powerplay_table *powerplay_table =
391 table_context->power_play_table;
392
393 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
394 sizeof(PPTable_t));
395
396 return 0;
397 }
398
399 #ifndef atom_smc_dpm_info_table_13_0_0
400 struct atom_smc_dpm_info_table_13_0_0 {
401 struct atom_common_table_header table_header;
402 BoardTable_t BoardTable;
403 };
404 #endif
405
smu_v13_0_0_append_powerplay_table(struct smu_context * smu)406 static int smu_v13_0_0_append_powerplay_table(struct smu_context *smu)
407 {
408 struct smu_table_context *table_context = &smu->smu_table;
409 PPTable_t *smc_pptable = table_context->driver_pptable;
410 struct atom_smc_dpm_info_table_13_0_0 *smc_dpm_table;
411 BoardTable_t *BoardTable = &smc_pptable->BoardTable;
412 int index, ret;
413
414 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
415 smc_dpm_info);
416
417 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
418 (uint8_t **)&smc_dpm_table);
419 if (ret)
420 return ret;
421
422 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
423
424 return 0;
425 }
426
smu_v13_0_0_get_pptable_from_pmfw(struct smu_context * smu,void ** table,uint32_t * size)427 static int smu_v13_0_0_get_pptable_from_pmfw(struct smu_context *smu,
428 void **table,
429 uint32_t *size)
430 {
431 struct smu_table_context *smu_table = &smu->smu_table;
432 void *combo_pptable = smu_table->combo_pptable;
433 int ret = 0;
434
435 ret = smu_cmn_get_combo_pptable(smu);
436 if (ret)
437 return ret;
438
439 *table = combo_pptable;
440 *size = sizeof(struct smu_13_0_0_powerplay_table);
441
442 return 0;
443 }
444
smu_v13_0_0_setup_pptable(struct smu_context * smu)445 static int smu_v13_0_0_setup_pptable(struct smu_context *smu)
446 {
447 struct smu_table_context *smu_table = &smu->smu_table;
448 struct amdgpu_device *adev = smu->adev;
449 int ret = 0;
450
451 if (amdgpu_sriov_vf(smu->adev))
452 return 0;
453
454 ret = smu_v13_0_0_get_pptable_from_pmfw(smu,
455 &smu_table->power_play_table,
456 &smu_table->power_play_table_size);
457 if (ret)
458 return ret;
459
460 ret = smu_v13_0_0_store_powerplay_table(smu);
461 if (ret)
462 return ret;
463
464 /*
465 * With SCPM enabled, the operation below will be handled
466 * by PSP. Driver involvment is unnecessary and useless.
467 */
468 if (!adev->scpm_enabled) {
469 ret = smu_v13_0_0_append_powerplay_table(smu);
470 if (ret)
471 return ret;
472 }
473
474 ret = smu_v13_0_0_check_powerplay_table(smu);
475 if (ret)
476 return ret;
477
478 return ret;
479 }
480
smu_v13_0_0_tables_init(struct smu_context * smu)481 static int smu_v13_0_0_tables_init(struct smu_context *smu)
482 {
483 struct smu_table_context *smu_table = &smu->smu_table;
484 struct smu_table *tables = smu_table->tables;
485
486 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
487 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
488 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
489 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
490 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
491 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
492 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
493 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
494 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTableExternal_t),
495 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
496 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
497 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
498 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
499 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
500 AMDGPU_GEM_DOMAIN_VRAM);
501 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
502 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
503 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
504 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
505 SMU_TABLE_INIT(tables, SMU_TABLE_WIFIBAND,
506 sizeof(WifiBandEntryTable_t), PAGE_SIZE,
507 AMDGPU_GEM_DOMAIN_VRAM);
508
509 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
510 if (!smu_table->metrics_table)
511 goto err0_out;
512 smu_table->metrics_time = 0;
513
514 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
515 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
516 if (!smu_table->gpu_metrics_table)
517 goto err1_out;
518
519 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
520 if (!smu_table->watermarks_table)
521 goto err2_out;
522
523 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
524 if (!smu_table->ecc_table)
525 goto err3_out;
526
527 return 0;
528
529 err3_out:
530 kfree(smu_table->watermarks_table);
531 err2_out:
532 kfree(smu_table->gpu_metrics_table);
533 err1_out:
534 kfree(smu_table->metrics_table);
535 err0_out:
536 return -ENOMEM;
537 }
538
smu_v13_0_0_allocate_dpm_context(struct smu_context * smu)539 static int smu_v13_0_0_allocate_dpm_context(struct smu_context *smu)
540 {
541 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
542
543 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
544 GFP_KERNEL);
545 if (!smu_dpm->dpm_context)
546 return -ENOMEM;
547
548 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
549
550 return 0;
551 }
552
smu_v13_0_0_init_smc_tables(struct smu_context * smu)553 static int smu_v13_0_0_init_smc_tables(struct smu_context *smu)
554 {
555 int ret = 0;
556
557 ret = smu_v13_0_0_tables_init(smu);
558 if (ret)
559 return ret;
560
561 ret = smu_v13_0_0_allocate_dpm_context(smu);
562 if (ret)
563 return ret;
564
565 return smu_v13_0_init_smc_tables(smu);
566 }
567
smu_v13_0_0_set_default_dpm_table(struct smu_context * smu)568 static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu)
569 {
570 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
571 struct smu_table_context *table_context = &smu->smu_table;
572 PPTable_t *pptable = table_context->driver_pptable;
573 SkuTable_t *skutable = &pptable->SkuTable;
574 struct smu_13_0_dpm_table *dpm_table;
575 int ret = 0;
576
577 /* socclk dpm table setup */
578 dpm_table = &dpm_context->dpm_tables.soc_table;
579 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
580 ret = smu_v13_0_set_single_dpm_table(smu,
581 SMU_SOCCLK,
582 dpm_table);
583 if (ret)
584 return ret;
585 } else {
586 dpm_table->count = 1;
587 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
588 dpm_table->dpm_levels[0].enabled = true;
589 dpm_table->min = dpm_table->dpm_levels[0].value;
590 dpm_table->max = dpm_table->dpm_levels[0].value;
591 }
592
593 /* gfxclk dpm table setup */
594 dpm_table = &dpm_context->dpm_tables.gfx_table;
595 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
596 ret = smu_v13_0_set_single_dpm_table(smu,
597 SMU_GFXCLK,
598 dpm_table);
599 if (ret)
600 return ret;
601
602 /*
603 * Update the reported maximum shader clock to the value
604 * which can be guarded to be achieved on all cards. This
605 * is aligned with Window setting. And considering that value
606 * might be not the peak frequency the card can achieve, it
607 * is normal some real-time clock frequency can overtake this
608 * labelled maximum clock frequency(for example in pp_dpm_sclk
609 * sysfs output).
610 */
611 if (skutable->DriverReportedClocks.GameClockAc &&
612 (dpm_table->dpm_levels[dpm_table->count - 1].value >
613 skutable->DriverReportedClocks.GameClockAc)) {
614 dpm_table->dpm_levels[dpm_table->count - 1].value =
615 skutable->DriverReportedClocks.GameClockAc;
616 dpm_table->max = skutable->DriverReportedClocks.GameClockAc;
617 }
618 } else {
619 dpm_table->count = 1;
620 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
621 dpm_table->dpm_levels[0].enabled = true;
622 dpm_table->min = dpm_table->dpm_levels[0].value;
623 dpm_table->max = dpm_table->dpm_levels[0].value;
624 }
625
626 /* uclk dpm table setup */
627 dpm_table = &dpm_context->dpm_tables.uclk_table;
628 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
629 ret = smu_v13_0_set_single_dpm_table(smu,
630 SMU_UCLK,
631 dpm_table);
632 if (ret)
633 return ret;
634 } else {
635 dpm_table->count = 1;
636 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
637 dpm_table->dpm_levels[0].enabled = true;
638 dpm_table->min = dpm_table->dpm_levels[0].value;
639 dpm_table->max = dpm_table->dpm_levels[0].value;
640 }
641
642 /* fclk dpm table setup */
643 dpm_table = &dpm_context->dpm_tables.fclk_table;
644 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
645 ret = smu_v13_0_set_single_dpm_table(smu,
646 SMU_FCLK,
647 dpm_table);
648 if (ret)
649 return ret;
650 } else {
651 dpm_table->count = 1;
652 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
653 dpm_table->dpm_levels[0].enabled = true;
654 dpm_table->min = dpm_table->dpm_levels[0].value;
655 dpm_table->max = dpm_table->dpm_levels[0].value;
656 }
657
658 /* vclk dpm table setup */
659 dpm_table = &dpm_context->dpm_tables.vclk_table;
660 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
661 ret = smu_v13_0_set_single_dpm_table(smu,
662 SMU_VCLK,
663 dpm_table);
664 if (ret)
665 return ret;
666 } else {
667 dpm_table->count = 1;
668 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
669 dpm_table->dpm_levels[0].enabled = true;
670 dpm_table->min = dpm_table->dpm_levels[0].value;
671 dpm_table->max = dpm_table->dpm_levels[0].value;
672 }
673
674 /* dclk dpm table setup */
675 dpm_table = &dpm_context->dpm_tables.dclk_table;
676 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
677 ret = smu_v13_0_set_single_dpm_table(smu,
678 SMU_DCLK,
679 dpm_table);
680 if (ret)
681 return ret;
682 } else {
683 dpm_table->count = 1;
684 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
685 dpm_table->dpm_levels[0].enabled = true;
686 dpm_table->min = dpm_table->dpm_levels[0].value;
687 dpm_table->max = dpm_table->dpm_levels[0].value;
688 }
689
690 /* dcefclk dpm table setup */
691 dpm_table = &dpm_context->dpm_tables.dcef_table;
692 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {
693 ret = smu_v13_0_set_single_dpm_table(smu,
694 SMU_DCEFCLK,
695 dpm_table);
696 if (ret)
697 return ret;
698 } else {
699 dpm_table->count = 1;
700 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
701 dpm_table->dpm_levels[0].enabled = true;
702 dpm_table->min = dpm_table->dpm_levels[0].value;
703 dpm_table->max = dpm_table->dpm_levels[0].value;
704 }
705
706 return 0;
707 }
708
smu_v13_0_0_is_dpm_running(struct smu_context * smu)709 static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu)
710 {
711 int ret = 0;
712 uint64_t feature_enabled;
713
714 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
715 if (ret)
716 return false;
717
718 return !!(feature_enabled & SMC_DPM_FEATURE);
719 }
720
smu_v13_0_0_system_features_control(struct smu_context * smu,bool en)721 static int smu_v13_0_0_system_features_control(struct smu_context *smu,
722 bool en)
723 {
724 return smu_v13_0_system_features_control(smu, en);
725 }
726
smu_v13_0_get_throttler_status(SmuMetrics_t * metrics)727 static uint32_t smu_v13_0_get_throttler_status(SmuMetrics_t *metrics)
728 {
729 uint32_t throttler_status = 0;
730 int i;
731
732 for (i = 0; i < THROTTLER_COUNT; i++)
733 throttler_status |=
734 (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
735
736 return throttler_status;
737 }
738
739 #define SMU_13_0_0_BUSY_THRESHOLD 15
smu_v13_0_0_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)740 static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu,
741 MetricsMember_t member,
742 uint32_t *value)
743 {
744 struct smu_table_context *smu_table = &smu->smu_table;
745 SmuMetrics_t *metrics =
746 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
747 int ret = 0;
748
749 ret = smu_cmn_get_metrics_table(smu,
750 NULL,
751 false);
752 if (ret)
753 return ret;
754
755 switch (member) {
756 case METRICS_CURR_GFXCLK:
757 *value = metrics->CurrClock[PPCLK_GFXCLK];
758 break;
759 case METRICS_CURR_SOCCLK:
760 *value = metrics->CurrClock[PPCLK_SOCCLK];
761 break;
762 case METRICS_CURR_UCLK:
763 *value = metrics->CurrClock[PPCLK_UCLK];
764 break;
765 case METRICS_CURR_VCLK:
766 *value = metrics->CurrClock[PPCLK_VCLK_0];
767 break;
768 case METRICS_CURR_VCLK1:
769 *value = metrics->CurrClock[PPCLK_VCLK_1];
770 break;
771 case METRICS_CURR_DCLK:
772 *value = metrics->CurrClock[PPCLK_DCLK_0];
773 break;
774 case METRICS_CURR_DCLK1:
775 *value = metrics->CurrClock[PPCLK_DCLK_1];
776 break;
777 case METRICS_CURR_FCLK:
778 *value = metrics->CurrClock[PPCLK_FCLK];
779 break;
780 case METRICS_CURR_DCEFCLK:
781 *value = metrics->CurrClock[PPCLK_DCFCLK];
782 break;
783 case METRICS_AVERAGE_GFXCLK:
784 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
785 *value = metrics->AverageGfxclkFrequencyPostDs;
786 else
787 *value = metrics->AverageGfxclkFrequencyPreDs;
788 break;
789 case METRICS_AVERAGE_FCLK:
790 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
791 *value = metrics->AverageFclkFrequencyPostDs;
792 else
793 *value = metrics->AverageFclkFrequencyPreDs;
794 break;
795 case METRICS_AVERAGE_UCLK:
796 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
797 *value = metrics->AverageMemclkFrequencyPostDs;
798 else
799 *value = metrics->AverageMemclkFrequencyPreDs;
800 break;
801 case METRICS_AVERAGE_VCLK:
802 *value = metrics->AverageVclk0Frequency;
803 break;
804 case METRICS_AVERAGE_DCLK:
805 *value = metrics->AverageDclk0Frequency;
806 break;
807 case METRICS_AVERAGE_VCLK1:
808 *value = metrics->AverageVclk1Frequency;
809 break;
810 case METRICS_AVERAGE_DCLK1:
811 *value = metrics->AverageDclk1Frequency;
812 break;
813 case METRICS_AVERAGE_GFXACTIVITY:
814 *value = metrics->AverageGfxActivity;
815 break;
816 case METRICS_AVERAGE_MEMACTIVITY:
817 *value = metrics->AverageUclkActivity;
818 break;
819 case METRICS_AVERAGE_VCNACTIVITY:
820 *value = max(metrics->Vcn0ActivityPercentage,
821 metrics->Vcn1ActivityPercentage);
822 break;
823 case METRICS_AVERAGE_SOCKETPOWER:
824 *value = metrics->AverageSocketPower << 8;
825 break;
826 case METRICS_TEMPERATURE_EDGE:
827 *value = metrics->AvgTemperature[TEMP_EDGE] *
828 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
829 break;
830 case METRICS_TEMPERATURE_HOTSPOT:
831 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
832 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
833 break;
834 case METRICS_TEMPERATURE_MEM:
835 *value = metrics->AvgTemperature[TEMP_MEM] *
836 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
837 break;
838 case METRICS_TEMPERATURE_VRGFX:
839 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
840 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
841 break;
842 case METRICS_TEMPERATURE_VRSOC:
843 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
844 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
845 break;
846 case METRICS_THROTTLER_STATUS:
847 *value = smu_v13_0_get_throttler_status(metrics);
848 break;
849 case METRICS_CURR_FANSPEED:
850 *value = metrics->AvgFanRpm;
851 break;
852 case METRICS_CURR_FANPWM:
853 *value = metrics->AvgFanPwm;
854 break;
855 case METRICS_VOLTAGE_VDDGFX:
856 *value = metrics->AvgVoltage[SVI_PLANE_GFX];
857 break;
858 case METRICS_PCIE_RATE:
859 *value = metrics->PcieRate;
860 break;
861 case METRICS_PCIE_WIDTH:
862 *value = metrics->PcieWidth;
863 break;
864 default:
865 *value = UINT_MAX;
866 break;
867 }
868
869 return ret;
870 }
871
smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)872 static int smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
873 enum smu_clk_type clk_type,
874 uint32_t *min,
875 uint32_t *max)
876 {
877 struct smu_13_0_dpm_context *dpm_context =
878 smu->smu_dpm.dpm_context;
879 struct smu_13_0_dpm_table *dpm_table;
880
881 switch (clk_type) {
882 case SMU_MCLK:
883 case SMU_UCLK:
884 /* uclk dpm table */
885 dpm_table = &dpm_context->dpm_tables.uclk_table;
886 break;
887 case SMU_GFXCLK:
888 case SMU_SCLK:
889 /* gfxclk dpm table */
890 dpm_table = &dpm_context->dpm_tables.gfx_table;
891 break;
892 case SMU_SOCCLK:
893 /* socclk dpm table */
894 dpm_table = &dpm_context->dpm_tables.soc_table;
895 break;
896 case SMU_FCLK:
897 /* fclk dpm table */
898 dpm_table = &dpm_context->dpm_tables.fclk_table;
899 break;
900 case SMU_VCLK:
901 case SMU_VCLK1:
902 /* vclk dpm table */
903 dpm_table = &dpm_context->dpm_tables.vclk_table;
904 break;
905 case SMU_DCLK:
906 case SMU_DCLK1:
907 /* dclk dpm table */
908 dpm_table = &dpm_context->dpm_tables.dclk_table;
909 break;
910 default:
911 dev_err(smu->adev->dev, "Unsupported clock type!\n");
912 return -EINVAL;
913 }
914
915 if (min)
916 *min = dpm_table->min;
917 if (max)
918 *max = dpm_table->max;
919
920 return 0;
921 }
922
smu_v13_0_0_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)923 static int smu_v13_0_0_read_sensor(struct smu_context *smu,
924 enum amd_pp_sensors sensor,
925 void *data,
926 uint32_t *size)
927 {
928 struct smu_table_context *table_context = &smu->smu_table;
929 PPTable_t *smc_pptable = table_context->driver_pptable;
930 int ret = 0;
931
932 switch (sensor) {
933 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
934 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm;
935 *size = 4;
936 break;
937 case AMDGPU_PP_SENSOR_MEM_LOAD:
938 ret = smu_v13_0_0_get_smu_metrics_data(smu,
939 METRICS_AVERAGE_MEMACTIVITY,
940 (uint32_t *)data);
941 *size = 4;
942 break;
943 case AMDGPU_PP_SENSOR_GPU_LOAD:
944 ret = smu_v13_0_0_get_smu_metrics_data(smu,
945 METRICS_AVERAGE_GFXACTIVITY,
946 (uint32_t *)data);
947 *size = 4;
948 break;
949 case AMDGPU_PP_SENSOR_VCN_LOAD:
950 ret = smu_v13_0_0_get_smu_metrics_data(smu,
951 METRICS_AVERAGE_VCNACTIVITY,
952 (uint32_t *)data);
953 *size = 4;
954 break;
955 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
956 ret = smu_v13_0_0_get_smu_metrics_data(smu,
957 METRICS_AVERAGE_SOCKETPOWER,
958 (uint32_t *)data);
959 *size = 4;
960 break;
961 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
962 ret = smu_v13_0_0_get_smu_metrics_data(smu,
963 METRICS_TEMPERATURE_HOTSPOT,
964 (uint32_t *)data);
965 *size = 4;
966 break;
967 case AMDGPU_PP_SENSOR_EDGE_TEMP:
968 ret = smu_v13_0_0_get_smu_metrics_data(smu,
969 METRICS_TEMPERATURE_EDGE,
970 (uint32_t *)data);
971 *size = 4;
972 break;
973 case AMDGPU_PP_SENSOR_MEM_TEMP:
974 ret = smu_v13_0_0_get_smu_metrics_data(smu,
975 METRICS_TEMPERATURE_MEM,
976 (uint32_t *)data);
977 *size = 4;
978 break;
979 case AMDGPU_PP_SENSOR_GFX_MCLK:
980 ret = smu_v13_0_0_get_smu_metrics_data(smu,
981 METRICS_CURR_UCLK,
982 (uint32_t *)data);
983 *(uint32_t *)data *= 100;
984 *size = 4;
985 break;
986 case AMDGPU_PP_SENSOR_GFX_SCLK:
987 ret = smu_v13_0_0_get_smu_metrics_data(smu,
988 METRICS_AVERAGE_GFXCLK,
989 (uint32_t *)data);
990 *(uint32_t *)data *= 100;
991 *size = 4;
992 break;
993 case AMDGPU_PP_SENSOR_VDDGFX:
994 ret = smu_v13_0_0_get_smu_metrics_data(smu,
995 METRICS_VOLTAGE_VDDGFX,
996 (uint32_t *)data);
997 *size = 4;
998 break;
999 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1000 default:
1001 ret = -EOPNOTSUPP;
1002 break;
1003 }
1004
1005 return ret;
1006 }
1007
smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1008 static int smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu,
1009 enum smu_clk_type clk_type,
1010 uint32_t *value)
1011 {
1012 MetricsMember_t member_type;
1013 int clk_id = 0;
1014
1015 clk_id = smu_cmn_to_asic_specific_index(smu,
1016 CMN2ASIC_MAPPING_CLK,
1017 clk_type);
1018 if (clk_id < 0)
1019 return -EINVAL;
1020
1021 switch (clk_id) {
1022 case PPCLK_GFXCLK:
1023 member_type = METRICS_AVERAGE_GFXCLK;
1024 break;
1025 case PPCLK_UCLK:
1026 member_type = METRICS_CURR_UCLK;
1027 break;
1028 case PPCLK_FCLK:
1029 member_type = METRICS_CURR_FCLK;
1030 break;
1031 case PPCLK_SOCCLK:
1032 member_type = METRICS_CURR_SOCCLK;
1033 break;
1034 case PPCLK_VCLK_0:
1035 member_type = METRICS_AVERAGE_VCLK;
1036 break;
1037 case PPCLK_DCLK_0:
1038 member_type = METRICS_AVERAGE_DCLK;
1039 break;
1040 case PPCLK_VCLK_1:
1041 member_type = METRICS_AVERAGE_VCLK1;
1042 break;
1043 case PPCLK_DCLK_1:
1044 member_type = METRICS_AVERAGE_DCLK1;
1045 break;
1046 case PPCLK_DCFCLK:
1047 member_type = METRICS_CURR_DCEFCLK;
1048 break;
1049 default:
1050 return -EINVAL;
1051 }
1052
1053 return smu_v13_0_0_get_smu_metrics_data(smu,
1054 member_type,
1055 value);
1056 }
1057
smu_v13_0_0_is_od_feature_supported(struct smu_context * smu,int od_feature_bit)1058 static bool smu_v13_0_0_is_od_feature_supported(struct smu_context *smu,
1059 int od_feature_bit)
1060 {
1061 PPTable_t *pptable = smu->smu_table.driver_pptable;
1062 const OverDriveLimits_t * const overdrive_upperlimits =
1063 &pptable->SkuTable.OverDriveLimitsBasicMax;
1064
1065 return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit);
1066 }
1067
smu_v13_0_0_get_od_setting_limits(struct smu_context * smu,int od_feature_bit,int32_t * min,int32_t * max)1068 static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu,
1069 int od_feature_bit,
1070 int32_t *min,
1071 int32_t *max)
1072 {
1073 PPTable_t *pptable = smu->smu_table.driver_pptable;
1074 const OverDriveLimits_t * const overdrive_upperlimits =
1075 &pptable->SkuTable.OverDriveLimitsBasicMax;
1076 const OverDriveLimits_t * const overdrive_lowerlimits =
1077 &pptable->SkuTable.OverDriveLimitsMin;
1078 int32_t od_min_setting, od_max_setting;
1079
1080 switch (od_feature_bit) {
1081 case PP_OD_FEATURE_GFXCLK_FMIN:
1082 od_min_setting = overdrive_lowerlimits->GfxclkFmin;
1083 od_max_setting = overdrive_upperlimits->GfxclkFmin;
1084 break;
1085 case PP_OD_FEATURE_GFXCLK_FMAX:
1086 od_min_setting = overdrive_lowerlimits->GfxclkFmax;
1087 od_max_setting = overdrive_upperlimits->GfxclkFmax;
1088 break;
1089 case PP_OD_FEATURE_UCLK_FMIN:
1090 od_min_setting = overdrive_lowerlimits->UclkFmin;
1091 od_max_setting = overdrive_upperlimits->UclkFmin;
1092 break;
1093 case PP_OD_FEATURE_UCLK_FMAX:
1094 od_min_setting = overdrive_lowerlimits->UclkFmax;
1095 od_max_setting = overdrive_upperlimits->UclkFmax;
1096 break;
1097 case PP_OD_FEATURE_GFX_VF_CURVE:
1098 od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary;
1099 od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary;
1100 break;
1101 case PP_OD_FEATURE_FAN_CURVE_TEMP:
1102 od_min_setting = overdrive_lowerlimits->FanLinearTempPoints;
1103 od_max_setting = overdrive_upperlimits->FanLinearTempPoints;
1104 break;
1105 case PP_OD_FEATURE_FAN_CURVE_PWM:
1106 od_min_setting = overdrive_lowerlimits->FanLinearPwmPoints;
1107 od_max_setting = overdrive_upperlimits->FanLinearPwmPoints;
1108 break;
1109 case PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT:
1110 od_min_setting = overdrive_lowerlimits->AcousticLimitRpmThreshold;
1111 od_max_setting = overdrive_upperlimits->AcousticLimitRpmThreshold;
1112 break;
1113 case PP_OD_FEATURE_FAN_ACOUSTIC_TARGET:
1114 od_min_setting = overdrive_lowerlimits->AcousticTargetRpmThreshold;
1115 od_max_setting = overdrive_upperlimits->AcousticTargetRpmThreshold;
1116 break;
1117 case PP_OD_FEATURE_FAN_TARGET_TEMPERATURE:
1118 od_min_setting = overdrive_lowerlimits->FanTargetTemperature;
1119 od_max_setting = overdrive_upperlimits->FanTargetTemperature;
1120 break;
1121 case PP_OD_FEATURE_FAN_MINIMUM_PWM:
1122 od_min_setting = overdrive_lowerlimits->FanMinimumPwm;
1123 od_max_setting = overdrive_upperlimits->FanMinimumPwm;
1124 break;
1125 case PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE:
1126 od_min_setting = overdrive_lowerlimits->FanZeroRpmEnable;
1127 od_max_setting = overdrive_upperlimits->FanZeroRpmEnable;
1128 break;
1129 case PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP:
1130 od_min_setting = overdrive_lowerlimits->FanZeroRpmStopTemp;
1131 od_max_setting = overdrive_upperlimits->FanZeroRpmStopTemp;
1132 break;
1133 default:
1134 od_min_setting = od_max_setting = INT_MAX;
1135 break;
1136 }
1137
1138 if (min)
1139 *min = od_min_setting;
1140 if (max)
1141 *max = od_max_setting;
1142 }
1143
smu_v13_0_0_dump_od_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1144 static void smu_v13_0_0_dump_od_table(struct smu_context *smu,
1145 OverDriveTableExternal_t *od_table)
1146 {
1147 struct amdgpu_device *adev = smu->adev;
1148
1149 dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin,
1150 od_table->OverDriveTable.GfxclkFmax);
1151 dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin,
1152 od_table->OverDriveTable.UclkFmax);
1153 }
1154
smu_v13_0_0_get_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1155 static int smu_v13_0_0_get_overdrive_table(struct smu_context *smu,
1156 OverDriveTableExternal_t *od_table)
1157 {
1158 int ret = 0;
1159
1160 ret = smu_cmn_update_table(smu,
1161 SMU_TABLE_OVERDRIVE,
1162 0,
1163 (void *)od_table,
1164 false);
1165 if (ret)
1166 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1167
1168 return ret;
1169 }
1170
smu_v13_0_0_upload_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1171 static int smu_v13_0_0_upload_overdrive_table(struct smu_context *smu,
1172 OverDriveTableExternal_t *od_table)
1173 {
1174 int ret = 0;
1175
1176 ret = smu_cmn_update_table(smu,
1177 SMU_TABLE_OVERDRIVE,
1178 0,
1179 (void *)od_table,
1180 true);
1181 if (ret)
1182 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
1183
1184 return ret;
1185 }
1186
smu_v13_0_0_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)1187 static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
1188 enum smu_clk_type clk_type,
1189 char *buf)
1190 {
1191 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1192 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1193 OverDriveTableExternal_t *od_table =
1194 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
1195 struct smu_13_0_dpm_table *single_dpm_table;
1196 struct smu_13_0_pcie_table *pcie_table;
1197 uint32_t gen_speed, lane_width;
1198 int i, curr_freq, size = 0, start_offset = 0;
1199 int32_t min_value, max_value;
1200 int ret = 0;
1201
1202 smu_cmn_get_sysfs_buf(&buf, &size);
1203 start_offset = size;
1204
1205 if (amdgpu_ras_intr_triggered()) {
1206 size += sysfs_emit_at(buf, size, "unavailable\n");
1207 return size - start_offset;
1208 }
1209
1210 switch (clk_type) {
1211 case SMU_SCLK:
1212 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1213 break;
1214 case SMU_MCLK:
1215 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1216 break;
1217 case SMU_SOCCLK:
1218 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1219 break;
1220 case SMU_FCLK:
1221 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1222 break;
1223 case SMU_VCLK:
1224 case SMU_VCLK1:
1225 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1226 break;
1227 case SMU_DCLK:
1228 case SMU_DCLK1:
1229 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1230 break;
1231 case SMU_DCEFCLK:
1232 single_dpm_table = &(dpm_context->dpm_tables.dcef_table);
1233 break;
1234 default:
1235 break;
1236 }
1237
1238 switch (clk_type) {
1239 case SMU_SCLK:
1240 case SMU_MCLK:
1241 case SMU_SOCCLK:
1242 case SMU_FCLK:
1243 case SMU_VCLK:
1244 case SMU_VCLK1:
1245 case SMU_DCLK:
1246 case SMU_DCLK1:
1247 case SMU_DCEFCLK:
1248 ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
1249 if (ret) {
1250 dev_err(smu->adev->dev, "Failed to get current clock freq!");
1251 return ret;
1252 }
1253
1254 if (single_dpm_table->is_fine_grained) {
1255 /*
1256 * For fine grained dpms, there are only two dpm levels:
1257 * - level 0 -> min clock freq
1258 * - level 1 -> max clock freq
1259 * And the current clock frequency can be any value between them.
1260 * So, if the current clock frequency is not at level 0 or level 1,
1261 * we will fake it as three dpm levels:
1262 * - level 0 -> min clock freq
1263 * - level 1 -> current actual clock freq
1264 * - level 2 -> max clock freq
1265 */
1266 if ((single_dpm_table->dpm_levels[0].value != curr_freq) &&
1267 (single_dpm_table->dpm_levels[1].value != curr_freq)) {
1268 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1269 single_dpm_table->dpm_levels[0].value);
1270 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1271 curr_freq);
1272 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1273 single_dpm_table->dpm_levels[1].value);
1274 } else {
1275 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1276 single_dpm_table->dpm_levels[0].value,
1277 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
1278 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1279 single_dpm_table->dpm_levels[1].value,
1280 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
1281 }
1282 } else {
1283 for (i = 0; i < single_dpm_table->count; i++)
1284 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
1285 i, single_dpm_table->dpm_levels[i].value,
1286 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : "");
1287 }
1288 break;
1289 case SMU_PCIE:
1290 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1291 METRICS_PCIE_RATE,
1292 &gen_speed);
1293 if (ret)
1294 return ret;
1295
1296 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1297 METRICS_PCIE_WIDTH,
1298 &lane_width);
1299 if (ret)
1300 return ret;
1301
1302 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1303 for (i = 0; i < pcie_table->num_of_link_levels; i++)
1304 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1305 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :
1306 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :
1307 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :
1308 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",
1309 (pcie_table->pcie_lane[i] == 1) ? "x1" :
1310 (pcie_table->pcie_lane[i] == 2) ? "x2" :
1311 (pcie_table->pcie_lane[i] == 3) ? "x4" :
1312 (pcie_table->pcie_lane[i] == 4) ? "x8" :
1313 (pcie_table->pcie_lane[i] == 5) ? "x12" :
1314 (pcie_table->pcie_lane[i] == 6) ? "x16" : "",
1315 pcie_table->clk_freq[i],
1316 (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
1317 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
1318 "*" : "");
1319 break;
1320
1321 case SMU_OD_SCLK:
1322 if (!smu_v13_0_0_is_od_feature_supported(smu,
1323 PP_OD_FEATURE_GFXCLK_BIT))
1324 break;
1325
1326 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1327 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1328 od_table->OverDriveTable.GfxclkFmin,
1329 od_table->OverDriveTable.GfxclkFmax);
1330 break;
1331
1332 case SMU_OD_MCLK:
1333 if (!smu_v13_0_0_is_od_feature_supported(smu,
1334 PP_OD_FEATURE_UCLK_BIT))
1335 break;
1336
1337 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1338 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n",
1339 od_table->OverDriveTable.UclkFmin,
1340 od_table->OverDriveTable.UclkFmax);
1341 break;
1342
1343 case SMU_OD_VDDGFX_OFFSET:
1344 if (!smu_v13_0_0_is_od_feature_supported(smu,
1345 PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1346 break;
1347
1348 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1349 size += sysfs_emit_at(buf, size, "%dmV\n",
1350 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[0]);
1351 break;
1352
1353 case SMU_OD_FAN_CURVE:
1354 if (!smu_v13_0_0_is_od_feature_supported(smu,
1355 PP_OD_FEATURE_FAN_CURVE_BIT))
1356 break;
1357
1358 size += sysfs_emit_at(buf, size, "OD_FAN_CURVE:\n");
1359 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++)
1360 size += sysfs_emit_at(buf, size, "%d: %dC %d%%\n",
1361 i,
1362 (int)od_table->OverDriveTable.FanLinearTempPoints[i],
1363 (int)od_table->OverDriveTable.FanLinearPwmPoints[i]);
1364
1365 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1366 smu_v13_0_0_get_od_setting_limits(smu,
1367 PP_OD_FEATURE_FAN_CURVE_TEMP,
1368 &min_value,
1369 &max_value);
1370 size += sysfs_emit_at(buf, size, "FAN_CURVE(hotspot temp): %uC %uC\n",
1371 min_value, max_value);
1372
1373 smu_v13_0_0_get_od_setting_limits(smu,
1374 PP_OD_FEATURE_FAN_CURVE_PWM,
1375 &min_value,
1376 &max_value);
1377 size += sysfs_emit_at(buf, size, "FAN_CURVE(fan speed): %u%% %u%%\n",
1378 min_value, max_value);
1379
1380 break;
1381
1382 case SMU_OD_ACOUSTIC_LIMIT:
1383 if (!smu_v13_0_0_is_od_feature_supported(smu,
1384 PP_OD_FEATURE_FAN_CURVE_BIT))
1385 break;
1386
1387 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_LIMIT:\n");
1388 size += sysfs_emit_at(buf, size, "%d\n",
1389 (int)od_table->OverDriveTable.AcousticLimitRpmThreshold);
1390
1391 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1392 smu_v13_0_0_get_od_setting_limits(smu,
1393 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1394 &min_value,
1395 &max_value);
1396 size += sysfs_emit_at(buf, size, "ACOUSTIC_LIMIT: %u %u\n",
1397 min_value, max_value);
1398 break;
1399
1400 case SMU_OD_ACOUSTIC_TARGET:
1401 if (!smu_v13_0_0_is_od_feature_supported(smu,
1402 PP_OD_FEATURE_FAN_CURVE_BIT))
1403 break;
1404
1405 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_TARGET:\n");
1406 size += sysfs_emit_at(buf, size, "%d\n",
1407 (int)od_table->OverDriveTable.AcousticTargetRpmThreshold);
1408
1409 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1410 smu_v13_0_0_get_od_setting_limits(smu,
1411 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1412 &min_value,
1413 &max_value);
1414 size += sysfs_emit_at(buf, size, "ACOUSTIC_TARGET: %u %u\n",
1415 min_value, max_value);
1416 break;
1417
1418 case SMU_OD_FAN_TARGET_TEMPERATURE:
1419 if (!smu_v13_0_0_is_od_feature_supported(smu,
1420 PP_OD_FEATURE_FAN_CURVE_BIT))
1421 break;
1422
1423 size += sysfs_emit_at(buf, size, "FAN_TARGET_TEMPERATURE:\n");
1424 size += sysfs_emit_at(buf, size, "%d\n",
1425 (int)od_table->OverDriveTable.FanTargetTemperature);
1426
1427 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1428 smu_v13_0_0_get_od_setting_limits(smu,
1429 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1430 &min_value,
1431 &max_value);
1432 size += sysfs_emit_at(buf, size, "TARGET_TEMPERATURE: %u %u\n",
1433 min_value, max_value);
1434 break;
1435
1436 case SMU_OD_FAN_MINIMUM_PWM:
1437 if (!smu_v13_0_0_is_od_feature_supported(smu,
1438 PP_OD_FEATURE_FAN_CURVE_BIT))
1439 break;
1440
1441 size += sysfs_emit_at(buf, size, "FAN_MINIMUM_PWM:\n");
1442 size += sysfs_emit_at(buf, size, "%d\n",
1443 (int)od_table->OverDriveTable.FanMinimumPwm);
1444
1445 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1446 smu_v13_0_0_get_od_setting_limits(smu,
1447 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1448 &min_value,
1449 &max_value);
1450 size += sysfs_emit_at(buf, size, "MINIMUM_PWM: %u %u\n",
1451 min_value, max_value);
1452 break;
1453
1454 case SMU_OD_FAN_ZERO_RPM_ENABLE:
1455 if (!smu_v13_0_0_is_od_feature_supported(smu,
1456 PP_OD_FEATURE_ZERO_FAN_BIT))
1457 break;
1458
1459 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_ENABLE:\n");
1460 size += sysfs_emit_at(buf, size, "%d\n",
1461 (int)od_table->OverDriveTable.FanZeroRpmEnable);
1462
1463 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1464 smu_v13_0_0_get_od_setting_limits(smu,
1465 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1466 &min_value,
1467 &max_value);
1468 size += sysfs_emit_at(buf, size, "ZERO_RPM_ENABLE: %u %u\n",
1469 min_value, max_value);
1470 break;
1471
1472 case SMU_OD_FAN_ZERO_RPM_STOP_TEMP:
1473 if (!smu_v13_0_0_is_od_feature_supported(smu,
1474 PP_OD_FEATURE_ZERO_FAN_BIT))
1475 break;
1476
1477 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_STOP_TEMPERATURE:\n");
1478 size += sysfs_emit_at(buf, size, "%d\n",
1479 (int)od_table->OverDriveTable.FanZeroRpmStopTemp);
1480
1481 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1482 smu_v13_0_0_get_od_setting_limits(smu,
1483 PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP,
1484 &min_value,
1485 &max_value);
1486 size += sysfs_emit_at(buf, size, "ZERO_RPM_STOP_TEMPERATURE: %u %u\n",
1487 min_value, max_value);
1488 break;
1489
1490 case SMU_OD_RANGE:
1491 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&
1492 !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&
1493 !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1494 break;
1495
1496 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1497
1498 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1499 smu_v13_0_0_get_od_setting_limits(smu,
1500 PP_OD_FEATURE_GFXCLK_FMIN,
1501 &min_value,
1502 NULL);
1503 smu_v13_0_0_get_od_setting_limits(smu,
1504 PP_OD_FEATURE_GFXCLK_FMAX,
1505 NULL,
1506 &max_value);
1507 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1508 min_value, max_value);
1509 }
1510
1511 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1512 smu_v13_0_0_get_od_setting_limits(smu,
1513 PP_OD_FEATURE_UCLK_FMIN,
1514 &min_value,
1515 NULL);
1516 smu_v13_0_0_get_od_setting_limits(smu,
1517 PP_OD_FEATURE_UCLK_FMAX,
1518 NULL,
1519 &max_value);
1520 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1521 min_value, max_value);
1522 }
1523
1524 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1525 smu_v13_0_0_get_od_setting_limits(smu,
1526 PP_OD_FEATURE_GFX_VF_CURVE,
1527 &min_value,
1528 &max_value);
1529 size += sysfs_emit_at(buf, size, "VDDGFX_OFFSET: %7dmv %10dmv\n",
1530 min_value, max_value);
1531 }
1532 break;
1533
1534 default:
1535 break;
1536 }
1537
1538 return size - start_offset;
1539 }
1540
1541
smu_v13_0_0_od_restore_table_single(struct smu_context * smu,long input)1542 static int smu_v13_0_0_od_restore_table_single(struct smu_context *smu, long input)
1543 {
1544 struct smu_table_context *table_context = &smu->smu_table;
1545 OverDriveTableExternal_t *boot_overdrive_table =
1546 (OverDriveTableExternal_t *)table_context->boot_overdrive_table;
1547 OverDriveTableExternal_t *od_table =
1548 (OverDriveTableExternal_t *)table_context->overdrive_table;
1549 struct amdgpu_device *adev = smu->adev;
1550 int i;
1551
1552 switch (input) {
1553 case PP_OD_EDIT_FAN_CURVE:
1554 for (i = 0; i < NUM_OD_FAN_MAX_POINTS; i++) {
1555 od_table->OverDriveTable.FanLinearTempPoints[i] =
1556 boot_overdrive_table->OverDriveTable.FanLinearTempPoints[i];
1557 od_table->OverDriveTable.FanLinearPwmPoints[i] =
1558 boot_overdrive_table->OverDriveTable.FanLinearPwmPoints[i];
1559 }
1560 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1561 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1562 break;
1563 case PP_OD_EDIT_ACOUSTIC_LIMIT:
1564 od_table->OverDriveTable.AcousticLimitRpmThreshold =
1565 boot_overdrive_table->OverDriveTable.AcousticLimitRpmThreshold;
1566 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1567 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1568 break;
1569 case PP_OD_EDIT_ACOUSTIC_TARGET:
1570 od_table->OverDriveTable.AcousticTargetRpmThreshold =
1571 boot_overdrive_table->OverDriveTable.AcousticTargetRpmThreshold;
1572 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1573 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1574 break;
1575 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1576 od_table->OverDriveTable.FanTargetTemperature =
1577 boot_overdrive_table->OverDriveTable.FanTargetTemperature;
1578 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1579 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1580 break;
1581 case PP_OD_EDIT_FAN_MINIMUM_PWM:
1582 od_table->OverDriveTable.FanMinimumPwm =
1583 boot_overdrive_table->OverDriveTable.FanMinimumPwm;
1584 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1585 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1586 break;
1587 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
1588 od_table->OverDriveTable.FanZeroRpmEnable =
1589 boot_overdrive_table->OverDriveTable.FanZeroRpmEnable;
1590 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1591 break;
1592 case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP:
1593 od_table->OverDriveTable.FanZeroRpmStopTemp =
1594 boot_overdrive_table->OverDriveTable.FanZeroRpmStopTemp;
1595 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1596 break;
1597 default:
1598 dev_info(adev->dev, "Invalid table index: %ld\n", input);
1599 return -EINVAL;
1600 }
1601
1602 return 0;
1603 }
1604
smu_v13_0_0_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1605 static int smu_v13_0_0_od_edit_dpm_table(struct smu_context *smu,
1606 enum PP_OD_DPM_TABLE_COMMAND type,
1607 long input[],
1608 uint32_t size)
1609 {
1610 struct smu_table_context *table_context = &smu->smu_table;
1611 OverDriveTableExternal_t *od_table =
1612 (OverDriveTableExternal_t *)table_context->overdrive_table;
1613 struct amdgpu_device *adev = smu->adev;
1614 uint32_t offset_of_voltageoffset;
1615 int32_t minimum, maximum;
1616 uint32_t feature_ctrlmask;
1617 int i, ret = 0;
1618
1619 switch (type) {
1620 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1621 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1622 dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n");
1623 return -ENOTSUPP;
1624 }
1625
1626 for (i = 0; i < size; i += 2) {
1627 if (i + 2 > size) {
1628 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1629 return -EINVAL;
1630 }
1631
1632 switch (input[i]) {
1633 case 0:
1634 smu_v13_0_0_get_od_setting_limits(smu,
1635 PP_OD_FEATURE_GFXCLK_FMIN,
1636 &minimum,
1637 &maximum);
1638 if (input[i + 1] < minimum ||
1639 input[i + 1] > maximum) {
1640 dev_info(adev->dev, "GfxclkFmin (%ld) must be within [%u, %u]!\n",
1641 input[i + 1], minimum, maximum);
1642 return -EINVAL;
1643 }
1644
1645 od_table->OverDriveTable.GfxclkFmin = input[i + 1];
1646 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1647 break;
1648
1649 case 1:
1650 smu_v13_0_0_get_od_setting_limits(smu,
1651 PP_OD_FEATURE_GFXCLK_FMAX,
1652 &minimum,
1653 &maximum);
1654 if (input[i + 1] < minimum ||
1655 input[i + 1] > maximum) {
1656 dev_info(adev->dev, "GfxclkFmax (%ld) must be within [%u, %u]!\n",
1657 input[i + 1], minimum, maximum);
1658 return -EINVAL;
1659 }
1660
1661 od_table->OverDriveTable.GfxclkFmax = input[i + 1];
1662 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1663 break;
1664
1665 default:
1666 dev_info(adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
1667 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1668 return -EINVAL;
1669 }
1670 }
1671
1672 if (od_table->OverDriveTable.GfxclkFmin > od_table->OverDriveTable.GfxclkFmax) {
1673 dev_err(adev->dev,
1674 "Invalid setting: GfxclkFmin(%u) is bigger than GfxclkFmax(%u)\n",
1675 (uint32_t)od_table->OverDriveTable.GfxclkFmin,
1676 (uint32_t)od_table->OverDriveTable.GfxclkFmax);
1677 return -EINVAL;
1678 }
1679 break;
1680
1681 case PP_OD_EDIT_MCLK_VDDC_TABLE:
1682 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1683 dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n");
1684 return -ENOTSUPP;
1685 }
1686
1687 for (i = 0; i < size; i += 2) {
1688 if (i + 2 > size) {
1689 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1690 return -EINVAL;
1691 }
1692
1693 switch (input[i]) {
1694 case 0:
1695 smu_v13_0_0_get_od_setting_limits(smu,
1696 PP_OD_FEATURE_UCLK_FMIN,
1697 &minimum,
1698 &maximum);
1699 if (input[i + 1] < minimum ||
1700 input[i + 1] > maximum) {
1701 dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n",
1702 input[i + 1], minimum, maximum);
1703 return -EINVAL;
1704 }
1705
1706 od_table->OverDriveTable.UclkFmin = input[i + 1];
1707 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1708 break;
1709
1710 case 1:
1711 smu_v13_0_0_get_od_setting_limits(smu,
1712 PP_OD_FEATURE_UCLK_FMAX,
1713 &minimum,
1714 &maximum);
1715 if (input[i + 1] < minimum ||
1716 input[i + 1] > maximum) {
1717 dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n",
1718 input[i + 1], minimum, maximum);
1719 return -EINVAL;
1720 }
1721
1722 od_table->OverDriveTable.UclkFmax = input[i + 1];
1723 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1724 break;
1725
1726 default:
1727 dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
1728 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1729 return -EINVAL;
1730 }
1731 }
1732
1733 if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) {
1734 dev_err(adev->dev,
1735 "Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n",
1736 (uint32_t)od_table->OverDriveTable.UclkFmin,
1737 (uint32_t)od_table->OverDriveTable.UclkFmax);
1738 return -EINVAL;
1739 }
1740 break;
1741
1742 case PP_OD_EDIT_VDDGFX_OFFSET:
1743 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1744 dev_warn(adev->dev, "Gfx offset setting not supported!\n");
1745 return -ENOTSUPP;
1746 }
1747
1748 smu_v13_0_0_get_od_setting_limits(smu,
1749 PP_OD_FEATURE_GFX_VF_CURVE,
1750 &minimum,
1751 &maximum);
1752 if (input[0] < minimum ||
1753 input[0] > maximum) {
1754 dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n",
1755 input[0], minimum, maximum);
1756 return -EINVAL;
1757 }
1758
1759 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
1760 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = input[0];
1761 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
1762 break;
1763
1764 case PP_OD_EDIT_FAN_CURVE:
1765 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1766 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1767 return -ENOTSUPP;
1768 }
1769
1770 if (input[0] >= NUM_OD_FAN_MAX_POINTS - 1 ||
1771 input[0] < 0)
1772 return -EINVAL;
1773
1774 smu_v13_0_0_get_od_setting_limits(smu,
1775 PP_OD_FEATURE_FAN_CURVE_TEMP,
1776 &minimum,
1777 &maximum);
1778 if (input[1] < minimum ||
1779 input[1] > maximum) {
1780 dev_info(adev->dev, "Fan curve temp setting(%ld) must be within [%d, %d]!\n",
1781 input[1], minimum, maximum);
1782 return -EINVAL;
1783 }
1784
1785 smu_v13_0_0_get_od_setting_limits(smu,
1786 PP_OD_FEATURE_FAN_CURVE_PWM,
1787 &minimum,
1788 &maximum);
1789 if (input[2] < minimum ||
1790 input[2] > maximum) {
1791 dev_info(adev->dev, "Fan curve pwm setting(%ld) must be within [%d, %d]!\n",
1792 input[2], minimum, maximum);
1793 return -EINVAL;
1794 }
1795
1796 od_table->OverDriveTable.FanLinearTempPoints[input[0]] = input[1];
1797 od_table->OverDriveTable.FanLinearPwmPoints[input[0]] = input[2];
1798 od_table->OverDriveTable.FanMode = FAN_MODE_MANUAL_LINEAR;
1799 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1800 break;
1801
1802 case PP_OD_EDIT_ACOUSTIC_LIMIT:
1803 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1804 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1805 return -ENOTSUPP;
1806 }
1807
1808 smu_v13_0_0_get_od_setting_limits(smu,
1809 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1810 &minimum,
1811 &maximum);
1812 if (input[0] < minimum ||
1813 input[0] > maximum) {
1814 dev_info(adev->dev, "acoustic limit threshold setting(%ld) must be within [%d, %d]!\n",
1815 input[0], minimum, maximum);
1816 return -EINVAL;
1817 }
1818
1819 od_table->OverDriveTable.AcousticLimitRpmThreshold = input[0];
1820 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1821 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1822 break;
1823
1824 case PP_OD_EDIT_ACOUSTIC_TARGET:
1825 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1826 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1827 return -ENOTSUPP;
1828 }
1829
1830 smu_v13_0_0_get_od_setting_limits(smu,
1831 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1832 &minimum,
1833 &maximum);
1834 if (input[0] < minimum ||
1835 input[0] > maximum) {
1836 dev_info(adev->dev, "acoustic target threshold setting(%ld) must be within [%d, %d]!\n",
1837 input[0], minimum, maximum);
1838 return -EINVAL;
1839 }
1840
1841 od_table->OverDriveTable.AcousticTargetRpmThreshold = input[0];
1842 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1843 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1844 break;
1845
1846 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1847 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1848 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1849 return -ENOTSUPP;
1850 }
1851
1852 smu_v13_0_0_get_od_setting_limits(smu,
1853 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1854 &minimum,
1855 &maximum);
1856 if (input[0] < minimum ||
1857 input[0] > maximum) {
1858 dev_info(adev->dev, "fan target temperature setting(%ld) must be within [%d, %d]!\n",
1859 input[0], minimum, maximum);
1860 return -EINVAL;
1861 }
1862
1863 od_table->OverDriveTable.FanTargetTemperature = input[0];
1864 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1865 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1866 break;
1867
1868 case PP_OD_EDIT_FAN_MINIMUM_PWM:
1869 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1870 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1871 return -ENOTSUPP;
1872 }
1873
1874 smu_v13_0_0_get_od_setting_limits(smu,
1875 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1876 &minimum,
1877 &maximum);
1878 if (input[0] < minimum ||
1879 input[0] > maximum) {
1880 dev_info(adev->dev, "fan minimum pwm setting(%ld) must be within [%d, %d]!\n",
1881 input[0], minimum, maximum);
1882 return -EINVAL;
1883 }
1884
1885 od_table->OverDriveTable.FanMinimumPwm = input[0];
1886 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1887 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1888 break;
1889
1890 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
1891 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
1892 dev_warn(adev->dev, "Zero RPM setting not supported!\n");
1893 return -ENOTSUPP;
1894 }
1895
1896 smu_v13_0_0_get_od_setting_limits(smu,
1897 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1898 &minimum,
1899 &maximum);
1900 if (input[0] < minimum ||
1901 input[0] > maximum) {
1902 dev_info(adev->dev, "zero RPM enable setting(%ld) must be within [%d, %d]!\n",
1903 input[0], minimum, maximum);
1904 return -EINVAL;
1905 }
1906
1907 od_table->OverDriveTable.FanZeroRpmEnable = input[0];
1908 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1909 break;
1910
1911 case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP:
1912 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
1913 dev_warn(adev->dev, "Zero RPM setting not supported!\n");
1914 return -ENOTSUPP;
1915 }
1916
1917 smu_v13_0_0_get_od_setting_limits(smu,
1918 PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP,
1919 &minimum,
1920 &maximum);
1921 if (input[0] < minimum ||
1922 input[0] > maximum) {
1923 dev_info(adev->dev, "zero RPM stop temperature setting(%ld) must be within [%d, %d]!\n",
1924 input[0], minimum, maximum);
1925 return -EINVAL;
1926 }
1927
1928 od_table->OverDriveTable.FanZeroRpmStopTemp = input[0];
1929 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1930 break;
1931
1932 case PP_OD_RESTORE_DEFAULT_TABLE:
1933 if (size == 1) {
1934 ret = smu_v13_0_0_od_restore_table_single(smu, input[0]);
1935 if (ret)
1936 return ret;
1937 } else {
1938 feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask;
1939 memcpy(od_table,
1940 table_context->boot_overdrive_table,
1941 sizeof(OverDriveTableExternal_t));
1942 od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask;
1943 }
1944 fallthrough;
1945 case PP_OD_COMMIT_DPM_TABLE:
1946 /*
1947 * The member below instructs PMFW the settings focused in
1948 * this single operation.
1949 * `uint32_t FeatureCtrlMask;`
1950 * It does not contain actual informations about user's custom
1951 * settings. Thus we do not cache it.
1952 */
1953 offset_of_voltageoffset = offsetof(OverDriveTable_t, VoltageOffsetPerZoneBoundary);
1954 if (memcmp((u8 *)od_table + offset_of_voltageoffset,
1955 table_context->user_overdrive_table + offset_of_voltageoffset,
1956 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset)) {
1957 smu_v13_0_0_dump_od_table(smu, od_table);
1958
1959 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
1960 if (ret) {
1961 dev_err(adev->dev, "Failed to upload overdrive table!\n");
1962 return ret;
1963 }
1964
1965 od_table->OverDriveTable.FeatureCtrlMask = 0;
1966 memcpy(table_context->user_overdrive_table + offset_of_voltageoffset,
1967 (u8 *)od_table + offset_of_voltageoffset,
1968 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset);
1969
1970 if (!memcmp(table_context->user_overdrive_table,
1971 table_context->boot_overdrive_table,
1972 sizeof(OverDriveTableExternal_t)))
1973 smu->user_dpm_profile.user_od = false;
1974 else
1975 smu->user_dpm_profile.user_od = true;
1976 }
1977 break;
1978
1979 default:
1980 return -ENOSYS;
1981 }
1982
1983 return ret;
1984 }
1985
smu_v13_0_0_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1986 static int smu_v13_0_0_force_clk_levels(struct smu_context *smu,
1987 enum smu_clk_type clk_type,
1988 uint32_t mask)
1989 {
1990 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1991 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1992 struct smu_13_0_dpm_table *single_dpm_table;
1993 uint32_t soft_min_level, soft_max_level;
1994 uint32_t min_freq, max_freq;
1995 int ret = 0;
1996
1997 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1998 soft_max_level = mask ? (fls(mask) - 1) : 0;
1999
2000 switch (clk_type) {
2001 case SMU_GFXCLK:
2002 case SMU_SCLK:
2003 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
2004 break;
2005 case SMU_MCLK:
2006 case SMU_UCLK:
2007 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
2008 break;
2009 case SMU_SOCCLK:
2010 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
2011 break;
2012 case SMU_FCLK:
2013 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
2014 break;
2015 case SMU_VCLK:
2016 case SMU_VCLK1:
2017 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
2018 break;
2019 case SMU_DCLK:
2020 case SMU_DCLK1:
2021 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
2022 break;
2023 default:
2024 break;
2025 }
2026
2027 switch (clk_type) {
2028 case SMU_GFXCLK:
2029 case SMU_SCLK:
2030 case SMU_MCLK:
2031 case SMU_UCLK:
2032 case SMU_SOCCLK:
2033 case SMU_FCLK:
2034 case SMU_VCLK:
2035 case SMU_VCLK1:
2036 case SMU_DCLK:
2037 case SMU_DCLK1:
2038 if (single_dpm_table->is_fine_grained) {
2039 /* There is only 2 levels for fine grained DPM */
2040 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
2041 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
2042 } else {
2043 if ((soft_max_level >= single_dpm_table->count) ||
2044 (soft_min_level >= single_dpm_table->count))
2045 return -EINVAL;
2046 }
2047
2048 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
2049 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
2050
2051 ret = smu_v13_0_set_soft_freq_limited_range(smu,
2052 clk_type,
2053 min_freq,
2054 max_freq,
2055 false);
2056 break;
2057 case SMU_DCEFCLK:
2058 case SMU_PCIE:
2059 default:
2060 break;
2061 }
2062
2063 return ret;
2064 }
2065
2066 static const struct smu_temperature_range smu13_thermal_policy[] = {
2067 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
2068 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
2069 };
2070
smu_v13_0_0_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2071 static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu,
2072 struct smu_temperature_range *range)
2073 {
2074 struct smu_table_context *table_context = &smu->smu_table;
2075 struct smu_13_0_0_powerplay_table *powerplay_table =
2076 table_context->power_play_table;
2077 PPTable_t *pptable = smu->smu_table.driver_pptable;
2078
2079 if (amdgpu_sriov_vf(smu->adev))
2080 return 0;
2081
2082 if (!range)
2083 return -EINVAL;
2084
2085 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
2086
2087 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] *
2088 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2089 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
2090 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2091 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] *
2092 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2093 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
2094 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2095 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] *
2096 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2097 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
2098 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2099 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2100 range->software_shutdown_temp_offset = pptable->SkuTable.FanAbnormalTempLimitOffset;
2101
2102 return 0;
2103 }
2104
smu_v13_0_0_get_gpu_metrics(struct smu_context * smu,void ** table)2105 static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu,
2106 void **table)
2107 {
2108 struct smu_table_context *smu_table = &smu->smu_table;
2109 struct gpu_metrics_v1_3 *gpu_metrics =
2110 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2111 SmuMetricsExternal_t metrics_ext;
2112 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
2113 int ret = 0;
2114
2115 ret = smu_cmn_get_metrics_table(smu,
2116 &metrics_ext,
2117 true);
2118 if (ret)
2119 return ret;
2120
2121 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2122
2123 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
2124 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
2125 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
2126 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
2127 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
2128 gpu_metrics->temperature_vrmem = max(metrics->AvgTemperature[TEMP_VR_MEM0],
2129 metrics->AvgTemperature[TEMP_VR_MEM1]);
2130
2131 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
2132 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
2133 gpu_metrics->average_mm_activity = max(metrics->Vcn0ActivityPercentage,
2134 metrics->Vcn1ActivityPercentage);
2135
2136 gpu_metrics->average_socket_power = metrics->AverageSocketPower;
2137 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
2138
2139 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
2140 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
2141 else
2142 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
2143
2144 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
2145 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
2146 else
2147 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
2148
2149 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
2150 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
2151 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
2152 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
2153
2154 gpu_metrics->current_gfxclk = gpu_metrics->average_gfxclk_frequency;
2155 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
2156 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
2157 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
2158 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
2159 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
2160 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
2161
2162 gpu_metrics->throttle_status =
2163 smu_v13_0_get_throttler_status(metrics);
2164 gpu_metrics->indep_throttle_status =
2165 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
2166 smu_v13_0_0_throttler_map);
2167
2168 gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
2169
2170 gpu_metrics->pcie_link_width = metrics->PcieWidth;
2171 if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
2172 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
2173 else
2174 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate);
2175
2176 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2177
2178 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX];
2179 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC];
2180 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP];
2181
2182 *table = (void *)gpu_metrics;
2183
2184 return sizeof(struct gpu_metrics_v1_3);
2185 }
2186
smu_v13_0_0_set_supported_od_feature_mask(struct smu_context * smu)2187 static void smu_v13_0_0_set_supported_od_feature_mask(struct smu_context *smu)
2188 {
2189 struct amdgpu_device *adev = smu->adev;
2190
2191 if (smu_v13_0_0_is_od_feature_supported(smu,
2192 PP_OD_FEATURE_FAN_CURVE_BIT))
2193 adev->pm.od_feature_mask |= OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE |
2194 OD_OPS_SUPPORT_FAN_CURVE_SET |
2195 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE |
2196 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET |
2197 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE |
2198 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET |
2199 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE |
2200 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET |
2201 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE |
2202 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET |
2203 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE |
2204 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET |
2205 OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE |
2206 OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET;
2207 }
2208
smu_v13_0_0_set_default_od_settings(struct smu_context * smu)2209 static int smu_v13_0_0_set_default_od_settings(struct smu_context *smu)
2210 {
2211 OverDriveTableExternal_t *od_table =
2212 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
2213 OverDriveTableExternal_t *boot_od_table =
2214 (OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table;
2215 OverDriveTableExternal_t *user_od_table =
2216 (OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table;
2217 OverDriveTableExternal_t user_od_table_bak;
2218 int ret = 0;
2219 int i;
2220
2221 ret = smu_v13_0_0_get_overdrive_table(smu, boot_od_table);
2222 if (ret)
2223 return ret;
2224
2225 smu_v13_0_0_dump_od_table(smu, boot_od_table);
2226
2227 memcpy(od_table,
2228 boot_od_table,
2229 sizeof(OverDriveTableExternal_t));
2230
2231 /*
2232 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2233 * but we have to preserve user defined values in "user_od_table".
2234 */
2235 if (!smu->adev->in_suspend) {
2236 memcpy(user_od_table,
2237 boot_od_table,
2238 sizeof(OverDriveTableExternal_t));
2239 smu->user_dpm_profile.user_od = false;
2240 } else if (smu->user_dpm_profile.user_od) {
2241 memcpy(&user_od_table_bak,
2242 user_od_table,
2243 sizeof(OverDriveTableExternal_t));
2244 memcpy(user_od_table,
2245 boot_od_table,
2246 sizeof(OverDriveTableExternal_t));
2247 user_od_table->OverDriveTable.GfxclkFmin =
2248 user_od_table_bak.OverDriveTable.GfxclkFmin;
2249 user_od_table->OverDriveTable.GfxclkFmax =
2250 user_od_table_bak.OverDriveTable.GfxclkFmax;
2251 user_od_table->OverDriveTable.UclkFmin =
2252 user_od_table_bak.OverDriveTable.UclkFmin;
2253 user_od_table->OverDriveTable.UclkFmax =
2254 user_od_table_bak.OverDriveTable.UclkFmax;
2255 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
2256 user_od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] =
2257 user_od_table_bak.OverDriveTable.VoltageOffsetPerZoneBoundary[i];
2258 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++) {
2259 user_od_table->OverDriveTable.FanLinearTempPoints[i] =
2260 user_od_table_bak.OverDriveTable.FanLinearTempPoints[i];
2261 user_od_table->OverDriveTable.FanLinearPwmPoints[i] =
2262 user_od_table_bak.OverDriveTable.FanLinearPwmPoints[i];
2263 }
2264 user_od_table->OverDriveTable.AcousticLimitRpmThreshold =
2265 user_od_table_bak.OverDriveTable.AcousticLimitRpmThreshold;
2266 user_od_table->OverDriveTable.AcousticTargetRpmThreshold =
2267 user_od_table_bak.OverDriveTable.AcousticTargetRpmThreshold;
2268 user_od_table->OverDriveTable.FanTargetTemperature =
2269 user_od_table_bak.OverDriveTable.FanTargetTemperature;
2270 user_od_table->OverDriveTable.FanMinimumPwm =
2271 user_od_table_bak.OverDriveTable.FanMinimumPwm;
2272 user_od_table->OverDriveTable.FanZeroRpmEnable =
2273 user_od_table_bak.OverDriveTable.FanZeroRpmEnable;
2274 user_od_table->OverDriveTable.FanZeroRpmStopTemp =
2275 user_od_table_bak.OverDriveTable.FanZeroRpmStopTemp;
2276 }
2277
2278 smu_v13_0_0_set_supported_od_feature_mask(smu);
2279
2280 return 0;
2281 }
2282
smu_v13_0_0_restore_user_od_settings(struct smu_context * smu)2283 static int smu_v13_0_0_restore_user_od_settings(struct smu_context *smu)
2284 {
2285 struct smu_table_context *table_context = &smu->smu_table;
2286 OverDriveTableExternal_t *od_table = table_context->overdrive_table;
2287 OverDriveTableExternal_t *user_od_table = table_context->user_overdrive_table;
2288 int res;
2289
2290 user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) |
2291 BIT(PP_OD_FEATURE_UCLK_BIT) |
2292 BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) |
2293 BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2294 res = smu_v13_0_0_upload_overdrive_table(smu, user_od_table);
2295 user_od_table->OverDriveTable.FeatureCtrlMask = 0;
2296 if (res == 0)
2297 memcpy(od_table, user_od_table, sizeof(OverDriveTableExternal_t));
2298
2299 return res;
2300 }
2301
smu_v13_0_0_populate_umd_state_clk(struct smu_context * smu)2302 static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu)
2303 {
2304 struct smu_13_0_dpm_context *dpm_context =
2305 smu->smu_dpm.dpm_context;
2306 struct smu_13_0_dpm_table *gfx_table =
2307 &dpm_context->dpm_tables.gfx_table;
2308 struct smu_13_0_dpm_table *mem_table =
2309 &dpm_context->dpm_tables.uclk_table;
2310 struct smu_13_0_dpm_table *soc_table =
2311 &dpm_context->dpm_tables.soc_table;
2312 struct smu_13_0_dpm_table *vclk_table =
2313 &dpm_context->dpm_tables.vclk_table;
2314 struct smu_13_0_dpm_table *dclk_table =
2315 &dpm_context->dpm_tables.dclk_table;
2316 struct smu_13_0_dpm_table *fclk_table =
2317 &dpm_context->dpm_tables.fclk_table;
2318 struct smu_umd_pstate_table *pstate_table =
2319 &smu->pstate_table;
2320 struct smu_table_context *table_context = &smu->smu_table;
2321 PPTable_t *pptable = table_context->driver_pptable;
2322 DriverReportedClocks_t driver_clocks =
2323 pptable->SkuTable.DriverReportedClocks;
2324
2325 pstate_table->gfxclk_pstate.min = gfx_table->min;
2326 if (driver_clocks.GameClockAc &&
2327 (driver_clocks.GameClockAc < gfx_table->max))
2328 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc;
2329 else
2330 pstate_table->gfxclk_pstate.peak = gfx_table->max;
2331
2332 pstate_table->uclk_pstate.min = mem_table->min;
2333 pstate_table->uclk_pstate.peak = mem_table->max;
2334
2335 pstate_table->socclk_pstate.min = soc_table->min;
2336 pstate_table->socclk_pstate.peak = soc_table->max;
2337
2338 pstate_table->vclk_pstate.min = vclk_table->min;
2339 pstate_table->vclk_pstate.peak = vclk_table->max;
2340
2341 pstate_table->dclk_pstate.min = dclk_table->min;
2342 pstate_table->dclk_pstate.peak = dclk_table->max;
2343
2344 pstate_table->fclk_pstate.min = fclk_table->min;
2345 pstate_table->fclk_pstate.peak = fclk_table->max;
2346
2347 if (driver_clocks.BaseClockAc &&
2348 driver_clocks.BaseClockAc < gfx_table->max)
2349 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc;
2350 else
2351 pstate_table->gfxclk_pstate.standard = gfx_table->max;
2352 pstate_table->uclk_pstate.standard = mem_table->max;
2353 pstate_table->socclk_pstate.standard = soc_table->min;
2354 pstate_table->vclk_pstate.standard = vclk_table->min;
2355 pstate_table->dclk_pstate.standard = dclk_table->min;
2356 pstate_table->fclk_pstate.standard = fclk_table->min;
2357
2358 return 0;
2359 }
2360
smu_v13_0_0_get_unique_id(struct smu_context * smu)2361 static void smu_v13_0_0_get_unique_id(struct smu_context *smu)
2362 {
2363 struct smu_table_context *smu_table = &smu->smu_table;
2364 SmuMetrics_t *metrics =
2365 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
2366 struct amdgpu_device *adev = smu->adev;
2367 uint32_t upper32 = 0, lower32 = 0;
2368 int ret;
2369
2370 ret = smu_cmn_get_metrics_table(smu, NULL, false);
2371 if (ret)
2372 goto out;
2373
2374 upper32 = metrics->PublicSerialNumberUpper;
2375 lower32 = metrics->PublicSerialNumberLower;
2376
2377 out:
2378 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
2379 }
2380
smu_v13_0_0_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)2381 static int smu_v13_0_0_get_fan_speed_pwm(struct smu_context *smu,
2382 uint32_t *speed)
2383 {
2384 int ret;
2385
2386 if (!speed)
2387 return -EINVAL;
2388
2389 ret = smu_v13_0_0_get_smu_metrics_data(smu,
2390 METRICS_CURR_FANPWM,
2391 speed);
2392 if (ret) {
2393 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!");
2394 return ret;
2395 }
2396
2397 /* Convert the PMFW output which is in percent to pwm(255) based */
2398 *speed = min(*speed * 255 / 100, (uint32_t)255);
2399
2400 return 0;
2401 }
2402
smu_v13_0_0_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)2403 static int smu_v13_0_0_get_fan_speed_rpm(struct smu_context *smu,
2404 uint32_t *speed)
2405 {
2406 if (!speed)
2407 return -EINVAL;
2408
2409 return smu_v13_0_0_get_smu_metrics_data(smu,
2410 METRICS_CURR_FANSPEED,
2411 speed);
2412 }
2413
smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context * smu)2414 static int smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context *smu)
2415 {
2416 struct smu_table_context *table_context = &smu->smu_table;
2417 PPTable_t *pptable = table_context->driver_pptable;
2418 SkuTable_t *skutable = &pptable->SkuTable;
2419
2420 /*
2421 * Skip the MGpuFanBoost setting for those ASICs
2422 * which do not support it
2423 */
2424 if (skutable->MGpuAcousticLimitRpmThreshold == 0)
2425 return 0;
2426
2427 return smu_cmn_send_smc_msg_with_param(smu,
2428 SMU_MSG_SetMGpuFanBoostLimitRpm,
2429 0,
2430 NULL);
2431 }
2432
smu_v13_0_0_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)2433 static int smu_v13_0_0_get_power_limit(struct smu_context *smu,
2434 uint32_t *current_power_limit,
2435 uint32_t *default_power_limit,
2436 uint32_t *max_power_limit,
2437 uint32_t *min_power_limit)
2438 {
2439 struct smu_table_context *table_context = &smu->smu_table;
2440 struct smu_13_0_0_powerplay_table *powerplay_table =
2441 (struct smu_13_0_0_powerplay_table *)table_context->power_play_table;
2442 PPTable_t *pptable = table_context->driver_pptable;
2443 SkuTable_t *skutable = &pptable->SkuTable;
2444 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
2445 uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
2446
2447 if (smu_v13_0_get_current_power_limit(smu, &power_limit))
2448 power_limit = smu->adev->pm.ac_power ?
2449 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
2450 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
2451
2452 if (current_power_limit)
2453 *current_power_limit = power_limit;
2454 if (default_power_limit)
2455 *default_power_limit = power_limit;
2456
2457 if (powerplay_table) {
2458 if (smu->od_enabled &&
2459 smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
2460 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
2461 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
2462 } else if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
2463 od_percent_upper = 0;
2464 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
2465 }
2466 }
2467
2468 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
2469 od_percent_upper, od_percent_lower, power_limit);
2470
2471 if (max_power_limit) {
2472 *max_power_limit = msg_limit * (100 + od_percent_upper);
2473 *max_power_limit /= 100;
2474 }
2475
2476 if (min_power_limit) {
2477 *min_power_limit = power_limit * (100 - od_percent_lower);
2478 *min_power_limit /= 100;
2479 }
2480
2481 return 0;
2482 }
2483
smu_v13_0_0_get_power_profile_mode(struct smu_context * smu,char * buf)2484 static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu,
2485 char *buf)
2486 {
2487 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
2488 DpmActivityMonitorCoeffInt_t *activity_monitor =
2489 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
2490 static const char *title[] = {
2491 "PROFILE_INDEX(NAME)",
2492 "CLOCK_TYPE(NAME)",
2493 "FPS",
2494 "MinActiveFreqType",
2495 "MinActiveFreq",
2496 "BoosterFreqType",
2497 "BoosterFreq",
2498 "PD_Data_limit_c",
2499 "PD_Data_error_coeff",
2500 "PD_Data_error_rate_coeff"};
2501 int16_t workload_type = 0;
2502 uint32_t i, size = 0;
2503 int result = 0;
2504
2505 if (!buf)
2506 return -EINVAL;
2507
2508 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n",
2509 title[0], title[1], title[2], title[3], title[4], title[5],
2510 title[6], title[7], title[8], title[9]);
2511
2512 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
2513 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
2514 workload_type = smu_cmn_to_asic_specific_index(smu,
2515 CMN2ASIC_MAPPING_WORKLOAD,
2516 i);
2517 if (workload_type == -ENOTSUPP)
2518 continue;
2519 else if (workload_type < 0)
2520 return -EINVAL;
2521
2522 result = smu_cmn_update_table(smu,
2523 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
2524 workload_type,
2525 (void *)(&activity_monitor_external),
2526 false);
2527 if (result) {
2528 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2529 return result;
2530 }
2531
2532 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
2533 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
2534
2535 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
2536 " ",
2537 0,
2538 "GFXCLK",
2539 activity_monitor->Gfx_FPS,
2540 activity_monitor->Gfx_MinActiveFreqType,
2541 activity_monitor->Gfx_MinActiveFreq,
2542 activity_monitor->Gfx_BoosterFreqType,
2543 activity_monitor->Gfx_BoosterFreq,
2544 activity_monitor->Gfx_PD_Data_limit_c,
2545 activity_monitor->Gfx_PD_Data_error_coeff,
2546 activity_monitor->Gfx_PD_Data_error_rate_coeff);
2547
2548 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
2549 " ",
2550 1,
2551 "FCLK",
2552 activity_monitor->Fclk_FPS,
2553 activity_monitor->Fclk_MinActiveFreqType,
2554 activity_monitor->Fclk_MinActiveFreq,
2555 activity_monitor->Fclk_BoosterFreqType,
2556 activity_monitor->Fclk_BoosterFreq,
2557 activity_monitor->Fclk_PD_Data_limit_c,
2558 activity_monitor->Fclk_PD_Data_error_coeff,
2559 activity_monitor->Fclk_PD_Data_error_rate_coeff);
2560 }
2561
2562 return size;
2563 }
2564
2565 #define SMU_13_0_0_CUSTOM_PARAMS_COUNT 9
2566 #define SMU_13_0_0_CUSTOM_PARAMS_CLOCK_COUNT 2
2567 #define SMU_13_0_0_CUSTOM_PARAMS_SIZE (SMU_13_0_0_CUSTOM_PARAMS_CLOCK_COUNT * SMU_13_0_0_CUSTOM_PARAMS_COUNT * sizeof(long))
2568
smu_v13_0_0_set_power_profile_mode_coeff(struct smu_context * smu,long * input)2569 static int smu_v13_0_0_set_power_profile_mode_coeff(struct smu_context *smu,
2570 long *input)
2571 {
2572 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
2573 DpmActivityMonitorCoeffInt_t *activity_monitor =
2574 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
2575 int ret, idx;
2576
2577 ret = smu_cmn_update_table(smu,
2578 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
2579 WORKLOAD_PPLIB_CUSTOM_BIT,
2580 (void *)(&activity_monitor_external),
2581 false);
2582 if (ret) {
2583 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2584 return ret;
2585 }
2586
2587 idx = 0 * SMU_13_0_0_CUSTOM_PARAMS_COUNT;
2588 if (input[idx]) {
2589 /* Gfxclk */
2590 activity_monitor->Gfx_FPS = input[idx + 1];
2591 activity_monitor->Gfx_MinActiveFreqType = input[idx + 2];
2592 activity_monitor->Gfx_MinActiveFreq = input[idx + 3];
2593 activity_monitor->Gfx_BoosterFreqType = input[idx + 4];
2594 activity_monitor->Gfx_BoosterFreq = input[idx + 5];
2595 activity_monitor->Gfx_PD_Data_limit_c = input[idx + 6];
2596 activity_monitor->Gfx_PD_Data_error_coeff = input[idx + 7];
2597 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[idx + 8];
2598 }
2599 idx = 1 * SMU_13_0_0_CUSTOM_PARAMS_COUNT;
2600 if (input[idx]) {
2601 /* Fclk */
2602 activity_monitor->Fclk_FPS = input[idx + 1];
2603 activity_monitor->Fclk_MinActiveFreqType = input[idx + 2];
2604 activity_monitor->Fclk_MinActiveFreq = input[idx + 3];
2605 activity_monitor->Fclk_BoosterFreqType = input[idx + 4];
2606 activity_monitor->Fclk_BoosterFreq = input[idx + 5];
2607 activity_monitor->Fclk_PD_Data_limit_c = input[idx + 6];
2608 activity_monitor->Fclk_PD_Data_error_coeff = input[idx + 7];
2609 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[idx + 8];
2610 }
2611
2612 ret = smu_cmn_update_table(smu,
2613 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
2614 WORKLOAD_PPLIB_CUSTOM_BIT,
2615 (void *)(&activity_monitor_external),
2616 true);
2617 if (ret) {
2618 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
2619 return ret;
2620 }
2621
2622 return ret;
2623 }
2624
smu_v13_0_0_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)2625 static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
2626 u32 workload_mask,
2627 long *custom_params,
2628 u32 custom_params_max_idx)
2629 {
2630 u32 backend_workload_mask = 0;
2631 int workload_type, ret, idx = -1, i;
2632
2633 smu_cmn_get_backend_workload_mask(smu, workload_mask,
2634 &backend_workload_mask);
2635
2636 /* Add optimizations for SMU13.0.0/10. Reuse the power saving profile */
2637 if ((workload_mask & (1 << PP_SMC_POWER_PROFILE_COMPUTE)) &&
2638 ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) &&
2639 ((smu->adev->pm.fw_version == 0x004e6601) ||
2640 (smu->adev->pm.fw_version >= 0x004e7300))) ||
2641 (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) &&
2642 smu->adev->pm.fw_version >= 0x00504500))) {
2643 workload_type = smu_cmn_to_asic_specific_index(smu,
2644 CMN2ASIC_MAPPING_WORKLOAD,
2645 PP_SMC_POWER_PROFILE_POWERSAVING);
2646 if (workload_type >= 0)
2647 backend_workload_mask |= 1 << workload_type;
2648 }
2649
2650 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) {
2651 if (!smu->custom_profile_params) {
2652 smu->custom_profile_params =
2653 kzalloc(SMU_13_0_0_CUSTOM_PARAMS_SIZE, GFP_KERNEL);
2654 if (!smu->custom_profile_params)
2655 return -ENOMEM;
2656 }
2657 if (custom_params && custom_params_max_idx) {
2658 if (custom_params_max_idx != SMU_13_0_0_CUSTOM_PARAMS_COUNT)
2659 return -EINVAL;
2660 if (custom_params[0] >= SMU_13_0_0_CUSTOM_PARAMS_CLOCK_COUNT)
2661 return -EINVAL;
2662 idx = custom_params[0] * SMU_13_0_0_CUSTOM_PARAMS_COUNT;
2663 smu->custom_profile_params[idx] = 1;
2664 for (i = 1; i < custom_params_max_idx; i++)
2665 smu->custom_profile_params[idx + i] = custom_params[i];
2666 }
2667 ret = smu_v13_0_0_set_power_profile_mode_coeff(smu,
2668 smu->custom_profile_params);
2669 if (ret) {
2670 if (idx != -1)
2671 smu->custom_profile_params[idx] = 0;
2672 return ret;
2673 }
2674 } else if (smu->custom_profile_params) {
2675 memset(smu->custom_profile_params, 0, SMU_13_0_0_CUSTOM_PARAMS_SIZE);
2676 }
2677
2678 ret = smu_cmn_send_smc_msg_with_param(smu,
2679 SMU_MSG_SetWorkloadMask,
2680 backend_workload_mask,
2681 NULL);
2682 if (ret) {
2683 dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n",
2684 workload_mask);
2685 if (idx != -1)
2686 smu->custom_profile_params[idx] = 0;
2687 return ret;
2688 }
2689
2690 return ret;
2691 }
2692
smu_v13_0_0_is_mode1_reset_supported(struct smu_context * smu)2693 static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu)
2694 {
2695 struct amdgpu_device *adev = smu->adev;
2696 u32 smu_version;
2697 int ret;
2698
2699 /* SRIOV does not support SMU mode1 reset */
2700 if (amdgpu_sriov_vf(adev))
2701 return false;
2702
2703 /* PMFW support is available since 78.41 */
2704 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2705 if (ret)
2706 return false;
2707
2708 if (smu_version < 0x004e2900)
2709 return false;
2710
2711 return true;
2712 }
2713
smu_v13_0_0_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)2714 static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap,
2715 struct i2c_msg *msg, int num_msgs)
2716 {
2717 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2718 struct amdgpu_device *adev = smu_i2c->adev;
2719 struct smu_context *smu = adev->powerplay.pp_handle;
2720 struct smu_table_context *smu_table = &smu->smu_table;
2721 struct smu_table *table = &smu_table->driver_table;
2722 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2723 int i, j, r, c;
2724 u16 dir;
2725
2726 if (!adev->pm.dpm_enabled)
2727 return -EBUSY;
2728
2729 req = kzalloc(sizeof(*req), GFP_KERNEL);
2730 if (!req)
2731 return -ENOMEM;
2732
2733 req->I2CcontrollerPort = smu_i2c->port;
2734 req->I2CSpeed = I2C_SPEED_FAST_400K;
2735 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2736 dir = msg[0].flags & I2C_M_RD;
2737
2738 for (c = i = 0; i < num_msgs; i++) {
2739 for (j = 0; j < msg[i].len; j++, c++) {
2740 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2741
2742 if (!(msg[i].flags & I2C_M_RD)) {
2743 /* write */
2744 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
2745 cmd->ReadWriteData = msg[i].buf[j];
2746 }
2747
2748 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2749 /* The direction changes.
2750 */
2751 dir = msg[i].flags & I2C_M_RD;
2752 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2753 }
2754
2755 req->NumCmds++;
2756
2757 /*
2758 * Insert STOP if we are at the last byte of either last
2759 * message for the transaction or the client explicitly
2760 * requires a STOP at this particular message.
2761 */
2762 if ((j == msg[i].len - 1) &&
2763 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2764 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2765 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2766 }
2767 }
2768 }
2769 mutex_lock(&adev->pm.mutex);
2770 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2771 if (r)
2772 goto fail;
2773
2774 for (c = i = 0; i < num_msgs; i++) {
2775 if (!(msg[i].flags & I2C_M_RD)) {
2776 c += msg[i].len;
2777 continue;
2778 }
2779 for (j = 0; j < msg[i].len; j++, c++) {
2780 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2781
2782 msg[i].buf[j] = cmd->ReadWriteData;
2783 }
2784 }
2785 r = num_msgs;
2786 fail:
2787 mutex_unlock(&adev->pm.mutex);
2788 kfree(req);
2789 return r;
2790 }
2791
smu_v13_0_0_i2c_func(struct i2c_adapter * adap)2792 static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap)
2793 {
2794 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2795 }
2796
2797 static const struct i2c_algorithm smu_v13_0_0_i2c_algo = {
2798 .master_xfer = smu_v13_0_0_i2c_xfer,
2799 .functionality = smu_v13_0_0_i2c_func,
2800 };
2801
2802 static const struct i2c_adapter_quirks smu_v13_0_0_i2c_control_quirks = {
2803 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2804 .max_read_len = MAX_SW_I2C_COMMANDS,
2805 .max_write_len = MAX_SW_I2C_COMMANDS,
2806 .max_comb_1st_msg_len = 2,
2807 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2808 };
2809
smu_v13_0_0_i2c_control_init(struct smu_context * smu)2810 static int smu_v13_0_0_i2c_control_init(struct smu_context *smu)
2811 {
2812 struct amdgpu_device *adev = smu->adev;
2813 int res, i;
2814
2815 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2816 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2817 struct i2c_adapter *control = &smu_i2c->adapter;
2818
2819 smu_i2c->adev = adev;
2820 smu_i2c->port = i;
2821 mutex_init(&smu_i2c->mutex);
2822 control->owner = THIS_MODULE;
2823 control->dev.parent = &adev->pdev->dev;
2824 control->algo = &smu_v13_0_0_i2c_algo;
2825 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2826 control->quirks = &smu_v13_0_0_i2c_control_quirks;
2827 i2c_set_adapdata(control, smu_i2c);
2828
2829 res = devm_i2c_add_adapter(adev->dev, control);
2830 if (res) {
2831 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2832 return res;
2833 }
2834 }
2835
2836 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
2837 /* XXX ideally this would be something in a vbios data table */
2838 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
2839 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2840
2841 return 0;
2842 }
2843
smu_v13_0_0_i2c_control_fini(struct smu_context * smu)2844 static void smu_v13_0_0_i2c_control_fini(struct smu_context *smu)
2845 {
2846 struct amdgpu_device *adev = smu->adev;
2847
2848 adev->pm.ras_eeprom_i2c_bus = NULL;
2849 adev->pm.fru_eeprom_i2c_bus = NULL;
2850 }
2851
smu_v13_0_0_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)2852 static int smu_v13_0_0_set_mp1_state(struct smu_context *smu,
2853 enum pp_mp1_state mp1_state)
2854 {
2855 int ret;
2856
2857 switch (mp1_state) {
2858 case PP_MP1_STATE_UNLOAD:
2859 ret = smu_cmn_send_smc_msg_with_param(smu,
2860 SMU_MSG_PrepareMp1ForUnload,
2861 0x55, NULL);
2862
2863 if (!ret && smu->smu_baco.state == SMU_BACO_STATE_EXIT)
2864 ret = smu_v13_0_disable_pmfw_state(smu);
2865
2866 break;
2867 default:
2868 /* Ignore others */
2869 ret = 0;
2870 }
2871
2872 return ret;
2873 }
2874
smu_v13_0_0_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)2875 static int smu_v13_0_0_set_df_cstate(struct smu_context *smu,
2876 enum pp_df_cstate state)
2877 {
2878 return smu_cmn_send_smc_msg_with_param(smu,
2879 SMU_MSG_DFCstateControl,
2880 state,
2881 NULL);
2882 }
2883
smu_v13_0_0_set_mode1_reset_param(struct smu_context * smu,uint32_t supported_version,uint32_t * param)2884 static void smu_v13_0_0_set_mode1_reset_param(struct smu_context *smu,
2885 uint32_t supported_version,
2886 uint32_t *param)
2887 {
2888 struct amdgpu_device *adev = smu->adev;
2889
2890 if ((smu->smc_fw_version >= supported_version) &&
2891 amdgpu_ras_get_fed_status(adev))
2892 /* Set RAS fatal error reset flag */
2893 *param = 1 << 16;
2894 else
2895 *param = 0;
2896 }
2897
smu_v13_0_0_mode1_reset(struct smu_context * smu)2898 static int smu_v13_0_0_mode1_reset(struct smu_context *smu)
2899 {
2900 int ret;
2901 uint32_t param;
2902 struct amdgpu_device *adev = smu->adev;
2903
2904 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2905 case IP_VERSION(13, 0, 0):
2906 /* SMU 13_0_0 PMFW supports RAS fatal error reset from 78.77 */
2907 smu_v13_0_0_set_mode1_reset_param(smu, 0x004e4d00, ¶m);
2908
2909 ret = smu_cmn_send_smc_msg_with_param(smu,
2910 SMU_MSG_Mode1Reset, param, NULL);
2911 break;
2912
2913 case IP_VERSION(13, 0, 10):
2914 /* SMU 13_0_10 PMFW supports RAS fatal error reset from 80.28 */
2915 smu_v13_0_0_set_mode1_reset_param(smu, 0x00501c00, ¶m);
2916
2917 ret = smu_cmn_send_debug_smc_msg_with_param(smu,
2918 DEBUGSMC_MSG_Mode1Reset, param);
2919 break;
2920
2921 default:
2922 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2923 break;
2924 }
2925
2926 if (!ret) {
2927 /* disable mmio access while doing mode 1 reset*/
2928 smu->adev->no_hw_access = true;
2929 /* ensure no_hw_access is globally visible before any MMIO */
2930 smp_mb();
2931 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2932 }
2933
2934 return ret;
2935 }
2936
smu_v13_0_0_mode2_reset(struct smu_context * smu)2937 static int smu_v13_0_0_mode2_reset(struct smu_context *smu)
2938 {
2939 int ret;
2940 struct amdgpu_device *adev = smu->adev;
2941
2942 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10))
2943 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode2Reset, NULL);
2944 else
2945 return -EOPNOTSUPP;
2946
2947 return ret;
2948 }
2949
smu_v13_0_0_enable_gfx_features(struct smu_context * smu)2950 static int smu_v13_0_0_enable_gfx_features(struct smu_context *smu)
2951 {
2952 struct amdgpu_device *adev = smu->adev;
2953
2954 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10))
2955 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableAllSmuFeatures,
2956 FEATURE_PWR_GFX, NULL);
2957 else
2958 return -EOPNOTSUPP;
2959 }
2960
smu_v13_0_0_set_smu_mailbox_registers(struct smu_context * smu)2961 static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu)
2962 {
2963 struct amdgpu_device *adev = smu->adev;
2964
2965 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2966 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2967 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2968
2969 smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53);
2970 smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75);
2971 smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);
2972 }
2973
smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context * smu,uint32_t size)2974 static int smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context *smu,
2975 uint32_t size)
2976 {
2977 int ret = 0;
2978
2979 /* message SMU to update the bad page number on SMUBUS */
2980 ret = smu_cmn_send_smc_msg_with_param(smu,
2981 SMU_MSG_SetNumBadMemoryPagesRetired,
2982 size, NULL);
2983 if (ret)
2984 dev_err(smu->adev->dev,
2985 "[%s] failed to message SMU to update bad memory pages number\n",
2986 __func__);
2987
2988 return ret;
2989 }
2990
smu_v13_0_0_send_bad_mem_channel_flag(struct smu_context * smu,uint32_t size)2991 static int smu_v13_0_0_send_bad_mem_channel_flag(struct smu_context *smu,
2992 uint32_t size)
2993 {
2994 int ret = 0;
2995
2996 /* message SMU to update the bad channel info on SMUBUS */
2997 ret = smu_cmn_send_smc_msg_with_param(smu,
2998 SMU_MSG_SetBadMemoryPagesRetiredFlagsPerChannel,
2999 size, NULL);
3000 if (ret)
3001 dev_err(smu->adev->dev,
3002 "[%s] failed to message SMU to update bad memory pages channel info\n",
3003 __func__);
3004
3005 return ret;
3006 }
3007
smu_v13_0_0_check_ecc_table_support(struct smu_context * smu)3008 static int smu_v13_0_0_check_ecc_table_support(struct smu_context *smu)
3009 {
3010 struct amdgpu_device *adev = smu->adev;
3011 int ret = 0;
3012
3013 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10)) &&
3014 (smu->smc_fw_version >= SUPPORT_ECCTABLE_SMU_13_0_10_VERSION))
3015 return ret;
3016 else
3017 return -EOPNOTSUPP;
3018 }
3019
smu_v13_0_0_get_ecc_info(struct smu_context * smu,void * table)3020 static ssize_t smu_v13_0_0_get_ecc_info(struct smu_context *smu,
3021 void *table)
3022 {
3023 struct smu_table_context *smu_table = &smu->smu_table;
3024 struct amdgpu_device *adev = smu->adev;
3025 EccInfoTable_t *ecc_table = NULL;
3026 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
3027 int i, ret = 0;
3028 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
3029
3030 ret = smu_v13_0_0_check_ecc_table_support(smu);
3031 if (ret)
3032 return ret;
3033
3034 ret = smu_cmn_update_table(smu,
3035 SMU_TABLE_ECCINFO,
3036 0,
3037 smu_table->ecc_table,
3038 false);
3039 if (ret) {
3040 dev_info(adev->dev, "Failed to export SMU ecc table!\n");
3041 return ret;
3042 }
3043
3044 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
3045
3046 for (i = 0; i < ARRAY_SIZE(ecc_table->EccInfo); i++) {
3047 ecc_info_per_channel = &(eccinfo->ecc[i]);
3048 ecc_info_per_channel->ce_count_lo_chip =
3049 ecc_table->EccInfo[i].ce_count_lo_chip;
3050 ecc_info_per_channel->ce_count_hi_chip =
3051 ecc_table->EccInfo[i].ce_count_hi_chip;
3052 ecc_info_per_channel->mca_umc_status =
3053 ecc_table->EccInfo[i].mca_umc_status;
3054 ecc_info_per_channel->mca_umc_addr =
3055 ecc_table->EccInfo[i].mca_umc_addr;
3056 }
3057
3058 return ret;
3059 }
3060
smu_v13_0_0_wbrf_support_check(struct smu_context * smu)3061 static bool smu_v13_0_0_wbrf_support_check(struct smu_context *smu)
3062 {
3063 struct amdgpu_device *adev = smu->adev;
3064
3065 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
3066 case IP_VERSION(13, 0, 0):
3067 return smu->smc_fw_version >= 0x004e6300;
3068 case IP_VERSION(13, 0, 10):
3069 return smu->smc_fw_version >= 0x00503300;
3070 default:
3071 return false;
3072 }
3073 }
3074
smu_v13_0_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)3075 static int smu_v13_0_0_set_power_limit(struct smu_context *smu,
3076 enum smu_ppt_limit_type limit_type,
3077 uint32_t limit)
3078 {
3079 PPTable_t *pptable = smu->smu_table.driver_pptable;
3080 SkuTable_t *skutable = &pptable->SkuTable;
3081 uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
3082 struct smu_table_context *table_context = &smu->smu_table;
3083 OverDriveTableExternal_t *od_table =
3084 (OverDriveTableExternal_t *)table_context->overdrive_table;
3085 int ret = 0;
3086
3087 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
3088 return -EINVAL;
3089
3090 if (limit <= msg_limit) {
3091 if (smu->current_power_limit > msg_limit) {
3092 od_table->OverDriveTable.Ppt = 0;
3093 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
3094
3095 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
3096 if (ret) {
3097 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
3098 return ret;
3099 }
3100 }
3101 return smu_v13_0_set_power_limit(smu, limit_type, limit);
3102 } else if (smu->od_enabled) {
3103 ret = smu_v13_0_set_power_limit(smu, limit_type, msg_limit);
3104 if (ret)
3105 return ret;
3106
3107 od_table->OverDriveTable.Ppt = (limit * 100) / msg_limit - 100;
3108 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
3109
3110 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
3111 if (ret) {
3112 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
3113 return ret;
3114 }
3115
3116 smu->current_power_limit = limit;
3117 } else {
3118 return -EINVAL;
3119 }
3120
3121 return 0;
3122 }
3123
smu_v13_0_0_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)3124 static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu,
3125 uint8_t pcie_gen_cap,
3126 uint8_t pcie_width_cap)
3127 {
3128 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
3129 struct smu_13_0_pcie_table *pcie_table =
3130 &dpm_context->dpm_tables.pcie_table;
3131 int num_of_levels;
3132 uint32_t smu_pcie_arg;
3133 uint32_t link_level;
3134 struct smu_table_context *table_context = &smu->smu_table;
3135 PPTable_t *pptable = table_context->driver_pptable;
3136 SkuTable_t *skutable = &pptable->SkuTable;
3137 int ret = 0;
3138 int i;
3139
3140 pcie_table->num_of_link_levels = 0;
3141
3142 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
3143 if (!skutable->PcieGenSpeed[link_level] &&
3144 !skutable->PcieLaneCount[link_level] &&
3145 !skutable->LclkFreq[link_level])
3146 continue;
3147
3148 pcie_table->pcie_gen[pcie_table->num_of_link_levels] =
3149 skutable->PcieGenSpeed[link_level];
3150 pcie_table->pcie_lane[pcie_table->num_of_link_levels] =
3151 skutable->PcieLaneCount[link_level];
3152 pcie_table->clk_freq[pcie_table->num_of_link_levels] =
3153 skutable->LclkFreq[link_level];
3154 pcie_table->num_of_link_levels++;
3155 }
3156
3157 num_of_levels = pcie_table->num_of_link_levels;
3158 if (!num_of_levels)
3159 return 0;
3160
3161 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
3162 if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
3163 pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
3164
3165 if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
3166 pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
3167
3168 /* Force all levels to use the same settings */
3169 for (i = 0; i < num_of_levels; i++) {
3170 pcie_table->pcie_gen[i] = pcie_gen_cap;
3171 pcie_table->pcie_lane[i] = pcie_width_cap;
3172 smu_pcie_arg = i << 16;
3173 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
3174 smu_pcie_arg |= pcie_table->pcie_lane[i];
3175
3176 ret = smu_cmn_send_smc_msg_with_param(smu,
3177 SMU_MSG_OverridePcieParameters,
3178 smu_pcie_arg,
3179 NULL);
3180 if (ret)
3181 break;
3182 }
3183 } else {
3184 for (i = 0; i < num_of_levels; i++) {
3185 if (pcie_table->pcie_gen[i] > pcie_gen_cap ||
3186 pcie_table->pcie_lane[i] > pcie_width_cap) {
3187 pcie_table->pcie_gen[i] = pcie_table->pcie_gen[i] > pcie_gen_cap ?
3188 pcie_gen_cap : pcie_table->pcie_gen[i];
3189 pcie_table->pcie_lane[i] = pcie_table->pcie_lane[i] > pcie_width_cap ?
3190 pcie_width_cap : pcie_table->pcie_lane[i];
3191 smu_pcie_arg = i << 16;
3192 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
3193 smu_pcie_arg |= pcie_table->pcie_lane[i];
3194
3195 ret = smu_cmn_send_smc_msg_with_param(smu,
3196 SMU_MSG_OverridePcieParameters,
3197 smu_pcie_arg,
3198 NULL);
3199 if (ret)
3200 break;
3201 }
3202 }
3203 }
3204
3205 return ret;
3206 }
3207
3208 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
3209 .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
3210 .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
3211 .i2c_init = smu_v13_0_0_i2c_control_init,
3212 .i2c_fini = smu_v13_0_0_i2c_control_fini,
3213 .is_dpm_running = smu_v13_0_0_is_dpm_running,
3214 .init_microcode = smu_v13_0_init_microcode,
3215 .load_microcode = smu_v13_0_load_microcode,
3216 .fini_microcode = smu_v13_0_fini_microcode,
3217 .init_smc_tables = smu_v13_0_0_init_smc_tables,
3218 .fini_smc_tables = smu_v13_0_fini_smc_tables,
3219 .init_power = smu_v13_0_init_power,
3220 .fini_power = smu_v13_0_fini_power,
3221 .check_fw_status = smu_v13_0_check_fw_status,
3222 .setup_pptable = smu_v13_0_0_setup_pptable,
3223 .check_fw_version = smu_v13_0_check_fw_version,
3224 .write_pptable = smu_cmn_write_pptable,
3225 .set_driver_table_location = smu_v13_0_set_driver_table_location,
3226 .system_features_control = smu_v13_0_0_system_features_control,
3227 .set_allowed_mask = smu_v13_0_set_allowed_mask,
3228 .get_enabled_mask = smu_cmn_get_enabled_mask,
3229 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
3230 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
3231 .get_dpm_ultimate_freq = smu_v13_0_0_get_dpm_ultimate_freq,
3232 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
3233 .read_sensor = smu_v13_0_0_read_sensor,
3234 .feature_is_enabled = smu_cmn_feature_is_enabled,
3235 .print_clk_levels = smu_v13_0_0_print_clk_levels,
3236 .force_clk_levels = smu_v13_0_0_force_clk_levels,
3237 .update_pcie_parameters = smu_v13_0_0_update_pcie_parameters,
3238 .get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range,
3239 .register_irq_handler = smu_v13_0_register_irq_handler,
3240 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
3241 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
3242 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
3243 .get_gpu_metrics = smu_v13_0_0_get_gpu_metrics,
3244 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
3245 .set_default_od_settings = smu_v13_0_0_set_default_od_settings,
3246 .restore_user_od_settings = smu_v13_0_0_restore_user_od_settings,
3247 .od_edit_dpm_table = smu_v13_0_0_od_edit_dpm_table,
3248 .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
3249 .populate_umd_state_clk = smu_v13_0_0_populate_umd_state_clk,
3250 .set_performance_level = smu_v13_0_set_performance_level,
3251 .gfx_off_control = smu_v13_0_gfx_off_control,
3252 .get_unique_id = smu_v13_0_0_get_unique_id,
3253 .get_fan_speed_pwm = smu_v13_0_0_get_fan_speed_pwm,
3254 .get_fan_speed_rpm = smu_v13_0_0_get_fan_speed_rpm,
3255 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
3256 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm,
3257 .get_fan_control_mode = smu_v13_0_get_fan_control_mode,
3258 .set_fan_control_mode = smu_v13_0_set_fan_control_mode,
3259 .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost,
3260 .get_power_limit = smu_v13_0_0_get_power_limit,
3261 .set_power_limit = smu_v13_0_0_set_power_limit,
3262 .set_power_source = smu_v13_0_set_power_source,
3263 .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
3264 .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
3265 .run_btc = smu_v13_0_run_btc,
3266 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3267 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3268 .set_tool_table_location = smu_v13_0_set_tool_table_location,
3269 .deep_sleep_control = smu_v13_0_deep_sleep_control,
3270 .gfx_ulv_control = smu_v13_0_gfx_ulv_control,
3271 .get_bamaco_support = smu_v13_0_get_bamaco_support,
3272 .baco_enter = smu_v13_0_baco_enter,
3273 .baco_exit = smu_v13_0_baco_exit,
3274 .mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported,
3275 .mode1_reset = smu_v13_0_0_mode1_reset,
3276 .mode2_reset = smu_v13_0_0_mode2_reset,
3277 .enable_gfx_features = smu_v13_0_0_enable_gfx_features,
3278 .set_mp1_state = smu_v13_0_0_set_mp1_state,
3279 .set_df_cstate = smu_v13_0_0_set_df_cstate,
3280 .send_hbm_bad_pages_num = smu_v13_0_0_smu_send_bad_mem_page_num,
3281 .send_hbm_bad_channel_flag = smu_v13_0_0_send_bad_mem_channel_flag,
3282 .gpo_control = smu_v13_0_gpo_control,
3283 .get_ecc_info = smu_v13_0_0_get_ecc_info,
3284 .notify_display_change = smu_v13_0_notify_display_change,
3285 .is_asic_wbrf_supported = smu_v13_0_0_wbrf_support_check,
3286 .enable_uclk_shadow = smu_v13_0_enable_uclk_shadow,
3287 .set_wbrf_exclusion_ranges = smu_v13_0_set_wbrf_exclusion_ranges,
3288 .interrupt_work = smu_v13_0_interrupt_work,
3289 };
3290
smu_v13_0_0_set_ppt_funcs(struct smu_context * smu)3291 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
3292 {
3293 smu->ppt_funcs = &smu_v13_0_0_ppt_funcs;
3294 smu->message_map = smu_v13_0_0_message_map;
3295 smu->clock_map = smu_v13_0_0_clk_map;
3296 smu->feature_map = smu_v13_0_0_feature_mask_map;
3297 smu->table_map = smu_v13_0_0_table_map;
3298 smu->pwr_src_map = smu_v13_0_0_pwr_src_map;
3299 smu->workload_map = smu_v13_0_0_workload_map;
3300 smu->smc_driver_if_version = SMU13_0_0_DRIVER_IF_VERSION;
3301 smu_v13_0_0_set_smu_mailbox_registers(smu);
3302
3303 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
3304 IP_VERSION(13, 0, 10) &&
3305 !amdgpu_device_has_display_hardware(smu->adev))
3306 smu->adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3307 }
3308