1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 8 #ifndef __QCOM_CLK_ALPHA_PLL_H__ 9 #define __QCOM_CLK_ALPHA_PLL_H__ 10 11 #include <linux/clk-provider.h> 12 #include "clk-regmap.h" 13 14 /* Alpha PLL types */ 15 enum { 16 CLK_ALPHA_PLL_TYPE_DEFAULT, 17 CLK_ALPHA_PLL_TYPE_HUAYRA, 18 CLK_ALPHA_PLL_TYPE_HUAYRA_APSS, 19 CLK_ALPHA_PLL_TYPE_HUAYRA_2290, 20 CLK_ALPHA_PLL_TYPE_BRAMMO, 21 CLK_ALPHA_PLL_TYPE_FABIA, 22 CLK_ALPHA_PLL_TYPE_TRION, 23 CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, 24 CLK_ALPHA_PLL_TYPE_AGERA, 25 CLK_ALPHA_PLL_TYPE_ZONDA, 26 CLK_ALPHA_PLL_TYPE_REGERA = CLK_ALPHA_PLL_TYPE_ZONDA, 27 CLK_ALPHA_PLL_TYPE_ZONDA_OLE, 28 CLK_ALPHA_PLL_TYPE_LUCID_EVO, 29 CLK_ALPHA_PLL_TYPE_LUCID_OLE, 30 CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, 31 CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, 32 CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, 33 CLK_ALPHA_PLL_TYPE_STROMER, 34 CLK_ALPHA_PLL_TYPE_STROMER_PLUS, 35 CLK_ALPHA_PLL_TYPE_MAX, 36 }; 37 38 enum { 39 PLL_OFF_L_VAL, 40 PLL_OFF_CAL_L_VAL, 41 PLL_OFF_ALPHA_VAL, 42 PLL_OFF_ALPHA_VAL_U, 43 PLL_OFF_USER_CTL, 44 PLL_OFF_USER_CTL_U, 45 PLL_OFF_USER_CTL_U1, 46 PLL_OFF_CONFIG_CTL, 47 PLL_OFF_CONFIG_CTL_U, 48 PLL_OFF_CONFIG_CTL_U1, 49 PLL_OFF_CONFIG_CTL_U2, 50 PLL_OFF_TEST_CTL, 51 PLL_OFF_TEST_CTL_U, 52 PLL_OFF_TEST_CTL_U1, 53 PLL_OFF_TEST_CTL_U2, 54 PLL_OFF_STATE, 55 PLL_OFF_STATUS, 56 PLL_OFF_OPMODE, 57 PLL_OFF_FRAC, 58 PLL_OFF_CAL_VAL, 59 PLL_OFF_MAX_REGS 60 }; 61 62 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; 63 64 struct pll_vco { 65 unsigned long min_freq; 66 unsigned long max_freq; 67 u32 val; 68 }; 69 70 #define VCO(a, b, c) { \ 71 .val = a,\ 72 .min_freq = b,\ 73 .max_freq = c,\ 74 } 75 76 /** 77 * struct clk_alpha_pll - phase locked loop (PLL) 78 * @offset: base address of registers 79 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 80 * @vco_table: array of VCO settings 81 * @num_vco: number of VCO settings in @vco_table 82 * @flags: bitmask to indicate features supported by the hardware 83 * @clkr: regmap clock handle 84 */ 85 struct clk_alpha_pll { 86 u32 offset; 87 const u8 *regs; 88 89 const struct pll_vco *vco_table; 90 size_t num_vco; 91 #define SUPPORTS_OFFLINE_REQ BIT(0) 92 #define SUPPORTS_FSM_MODE BIT(2) 93 #define SUPPORTS_DYNAMIC_UPDATE BIT(3) 94 #define SUPPORTS_FSM_LEGACY_MODE BIT(4) 95 u8 flags; 96 97 struct clk_regmap clkr; 98 }; 99 100 /** 101 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider 102 * @offset: base address of registers 103 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 104 * @width: width of post-divider 105 * @post_div_shift: shift to differentiate between odd & even post-divider 106 * @post_div_table: table with PLL odd and even post-divider settings 107 * @num_post_div: Number of PLL post-divider settings 108 * 109 * @clkr: regmap clock handle 110 */ 111 struct clk_alpha_pll_postdiv { 112 u32 offset; 113 u8 width; 114 const u8 *regs; 115 116 struct clk_regmap clkr; 117 int post_div_shift; 118 const struct clk_div_table *post_div_table; 119 size_t num_post_div; 120 }; 121 122 struct alpha_pll_config { 123 u32 l; 124 u32 alpha; 125 u32 alpha_hi; 126 u32 config_ctl_val; 127 u32 config_ctl_hi_val; 128 u32 config_ctl_hi1_val; 129 u32 config_ctl_hi2_val; 130 u32 user_ctl_val; 131 u32 user_ctl_hi_val; 132 u32 user_ctl_hi1_val; 133 u32 test_ctl_val; 134 u32 test_ctl_mask; 135 u32 test_ctl_hi_val; 136 u32 test_ctl_hi_mask; 137 u32 test_ctl_hi1_val; 138 u32 test_ctl_hi2_val; 139 u32 main_output_mask; 140 u32 aux_output_mask; 141 u32 aux2_output_mask; 142 u32 early_output_mask; 143 u32 alpha_en_mask; 144 u32 alpha_mode_mask; 145 u32 pre_div_val; 146 u32 pre_div_mask; 147 u32 post_div_val; 148 u32 post_div_mask; 149 u32 vco_val; 150 u32 vco_mask; 151 u32 status_val; 152 u32 status_mask; 153 u32 lock_det; 154 }; 155 156 extern const struct clk_ops clk_alpha_pll_ops; 157 extern const struct clk_ops clk_alpha_pll_fixed_ops; 158 extern const struct clk_ops clk_alpha_pll_hwfsm_ops; 159 extern const struct clk_ops clk_alpha_pll_postdiv_ops; 160 extern const struct clk_ops clk_alpha_pll_huayra_ops; 161 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; 162 extern const struct clk_ops clk_alpha_pll_stromer_ops; 163 extern const struct clk_ops clk_alpha_pll_stromer_plus_ops; 164 165 extern const struct clk_ops clk_alpha_pll_fabia_ops; 166 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; 167 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops; 168 169 extern const struct clk_ops clk_alpha_pll_trion_ops; 170 extern const struct clk_ops clk_alpha_pll_fixed_trion_ops; 171 extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops; 172 173 extern const struct clk_ops clk_alpha_pll_lucid_ops; 174 #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops 175 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops; 176 extern const struct clk_ops clk_alpha_pll_agera_ops; 177 178 extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops; 179 extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops; 180 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; 181 182 extern const struct clk_ops clk_alpha_pll_zonda_ops; 183 #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops 184 #define clk_alpha_pll_zonda_ole_ops clk_alpha_pll_zonda_ops 185 186 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; 187 extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops; 188 #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops 189 extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; 190 #define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops 191 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; 192 #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops 193 194 extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; 195 #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops 196 197 extern const struct clk_ops clk_alpha_pll_regera_ops; 198 199 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 200 const struct alpha_pll_config *config); 201 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 202 const struct alpha_pll_config *config); 203 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 204 const struct alpha_pll_config *config); 205 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 206 const struct alpha_pll_config *config); 207 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 208 const struct alpha_pll_config *config); 209 #define clk_lucid_pll_configure(pll, regmap, config) \ 210 clk_trion_pll_configure(pll, regmap, config) 211 212 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 213 const struct alpha_pll_config *config); 214 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 215 const struct alpha_pll_config *config); 216 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 217 const struct alpha_pll_config *config); 218 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 219 const struct alpha_pll_config *config); 220 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 221 const struct alpha_pll_config *config); 222 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 223 const struct alpha_pll_config *config); 224 void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 225 const struct alpha_pll_config *config); 226 227 #endif 228