1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6 #include <linux/module.h>
7 #include <linux/types.h>
8 #include <linux/init.h>
9 #include <linux/pci.h>
10 #include <linux/vmalloc.h>
11 #include <linux/pagemap.h>
12 #include <linux/delay.h>
13 #include <linux/netdevice.h>
14 #include <linux/interrupt.h>
15 #include <linux/tcp.h>
16 #include <linux/ipv6.h>
17 #include <linux/slab.h>
18 #include <net/checksum.h>
19 #include <net/ip6_checksum.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/cpu.h>
23 #include <linux/smp.h>
24 #include <linux/pm_qos.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/prefetch.h>
27 #include <linux/suspend.h>
28 #include <linux/dmi.h>
29
30 #include "e1000.h"
31 #define CREATE_TRACE_POINTS
32 #include "e1000e_trace.h"
33
34 char e1000e_driver_name[] = "e1000e";
35
36 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
37 static int debug = -1;
38 module_param(debug, int, 0);
39 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
40
41 static const struct e1000_info *e1000_info_tbl[] = {
42 [board_82571] = &e1000_82571_info,
43 [board_82572] = &e1000_82572_info,
44 [board_82573] = &e1000_82573_info,
45 [board_82574] = &e1000_82574_info,
46 [board_82583] = &e1000_82583_info,
47 [board_80003es2lan] = &e1000_es2_info,
48 [board_ich8lan] = &e1000_ich8_info,
49 [board_ich9lan] = &e1000_ich9_info,
50 [board_ich10lan] = &e1000_ich10_info,
51 [board_pchlan] = &e1000_pch_info,
52 [board_pch2lan] = &e1000_pch2_info,
53 [board_pch_lpt] = &e1000_pch_lpt_info,
54 [board_pch_spt] = &e1000_pch_spt_info,
55 [board_pch_cnp] = &e1000_pch_cnp_info,
56 [board_pch_tgp] = &e1000_pch_tgp_info,
57 [board_pch_adp] = &e1000_pch_adp_info,
58 [board_pch_mtp] = &e1000_pch_mtp_info,
59 [board_pch_ptp] = &e1000_pch_ptp_info,
60 };
61
62 static const struct dmi_system_id disable_k1_list[] = {
63 {
64 .ident = "Dell Pro 16 Plus PB16250",
65 .matches = {
66 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
67 DMI_MATCH(DMI_PRODUCT_NAME, "Dell Pro 16 Plus PB16250"),
68 },
69 },
70 {}
71 };
72
73 struct e1000_reg_info {
74 u32 ofs;
75 char *name;
76 };
77
78 static const struct e1000_reg_info e1000_reg_info_tbl[] = {
79 /* General Registers */
80 {E1000_CTRL, "CTRL"},
81 {E1000_STATUS, "STATUS"},
82 {E1000_CTRL_EXT, "CTRL_EXT"},
83
84 /* Interrupt Registers */
85 {E1000_ICR, "ICR"},
86
87 /* Rx Registers */
88 {E1000_RCTL, "RCTL"},
89 {E1000_RDLEN(0), "RDLEN"},
90 {E1000_RDH(0), "RDH"},
91 {E1000_RDT(0), "RDT"},
92 {E1000_RDTR, "RDTR"},
93 {E1000_RXDCTL(0), "RXDCTL"},
94 {E1000_ERT, "ERT"},
95 {E1000_RDBAL(0), "RDBAL"},
96 {E1000_RDBAH(0), "RDBAH"},
97 {E1000_RDFH, "RDFH"},
98 {E1000_RDFT, "RDFT"},
99 {E1000_RDFHS, "RDFHS"},
100 {E1000_RDFTS, "RDFTS"},
101 {E1000_RDFPC, "RDFPC"},
102
103 /* Tx Registers */
104 {E1000_TCTL, "TCTL"},
105 {E1000_TDBAL(0), "TDBAL"},
106 {E1000_TDBAH(0), "TDBAH"},
107 {E1000_TDLEN(0), "TDLEN"},
108 {E1000_TDH(0), "TDH"},
109 {E1000_TDT(0), "TDT"},
110 {E1000_TIDV, "TIDV"},
111 {E1000_TXDCTL(0), "TXDCTL"},
112 {E1000_TADV, "TADV"},
113 {E1000_TARC(0), "TARC"},
114 {E1000_TDFH, "TDFH"},
115 {E1000_TDFT, "TDFT"},
116 {E1000_TDFHS, "TDFHS"},
117 {E1000_TDFTS, "TDFTS"},
118 {E1000_TDFPC, "TDFPC"},
119
120 /* List Terminator */
121 {0, NULL}
122 };
123
124 /**
125 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
126 * @hw: pointer to the HW structure
127 *
128 * When updating the MAC CSR registers, the Manageability Engine (ME) could
129 * be accessing the registers at the same time. Normally, this is handled in
130 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
131 * accesses later than it should which could result in the register to have
132 * an incorrect value. Workaround this by checking the FWSM register which
133 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
134 * and try again a number of times.
135 **/
__ew32_prepare(struct e1000_hw * hw)136 static void __ew32_prepare(struct e1000_hw *hw)
137 {
138 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
139
140 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
141 udelay(50);
142 }
143
__ew32(struct e1000_hw * hw,unsigned long reg,u32 val)144 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
145 {
146 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
147 __ew32_prepare(hw);
148
149 writel(val, hw->hw_addr + reg);
150 }
151
152 /**
153 * e1000_regdump - register printout routine
154 * @hw: pointer to the HW structure
155 * @reginfo: pointer to the register info table
156 **/
e1000_regdump(struct e1000_hw * hw,struct e1000_reg_info * reginfo)157 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
158 {
159 int n = 0;
160 char rname[16];
161 u32 regs[8];
162
163 switch (reginfo->ofs) {
164 case E1000_RXDCTL(0):
165 for (n = 0; n < 2; n++)
166 regs[n] = __er32(hw, E1000_RXDCTL(n));
167 break;
168 case E1000_TXDCTL(0):
169 for (n = 0; n < 2; n++)
170 regs[n] = __er32(hw, E1000_TXDCTL(n));
171 break;
172 case E1000_TARC(0):
173 for (n = 0; n < 2; n++)
174 regs[n] = __er32(hw, E1000_TARC(n));
175 break;
176 default:
177 pr_info("%-15s %08x\n",
178 reginfo->name, __er32(hw, reginfo->ofs));
179 return;
180 }
181
182 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
183 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
184 }
185
e1000e_dump_ps_pages(struct e1000_adapter * adapter,struct e1000_buffer * bi)186 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
187 struct e1000_buffer *bi)
188 {
189 int i;
190 struct e1000_ps_page *ps_page;
191
192 for (i = 0; i < adapter->rx_ps_pages; i++) {
193 ps_page = &bi->ps_pages[i];
194
195 if (ps_page->page) {
196 pr_info("packet dump for ps_page %d:\n", i);
197 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
198 16, 1, page_address(ps_page->page),
199 PAGE_SIZE, true);
200 }
201 }
202 }
203
204 /**
205 * e1000e_dump - Print registers, Tx-ring and Rx-ring
206 * @adapter: board private structure
207 **/
e1000e_dump(struct e1000_adapter * adapter)208 static void e1000e_dump(struct e1000_adapter *adapter)
209 {
210 struct net_device *netdev = adapter->netdev;
211 struct e1000_hw *hw = &adapter->hw;
212 struct e1000_reg_info *reginfo;
213 struct e1000_ring *tx_ring = adapter->tx_ring;
214 struct e1000_tx_desc *tx_desc;
215 struct my_u0 {
216 __le64 a;
217 __le64 b;
218 } *u0;
219 struct e1000_buffer *buffer_info;
220 struct e1000_ring *rx_ring = adapter->rx_ring;
221 union e1000_rx_desc_packet_split *rx_desc_ps;
222 union e1000_rx_desc_extended *rx_desc;
223 struct my_u1 {
224 __le64 a;
225 __le64 b;
226 __le64 c;
227 __le64 d;
228 } *u1;
229 u32 staterr;
230 int i = 0;
231
232 if (!netif_msg_hw(adapter))
233 return;
234
235 /* Print netdevice Info */
236 if (netdev) {
237 dev_info(&adapter->pdev->dev, "Net device Info\n");
238 pr_info("Device Name state trans_start\n");
239 pr_info("%-15s %016lX %016lX\n", netdev->name,
240 netdev->state, dev_trans_start(netdev));
241 }
242
243 /* Print Registers */
244 dev_info(&adapter->pdev->dev, "Register Dump\n");
245 pr_info(" Register Name Value\n");
246 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
247 reginfo->name; reginfo++) {
248 e1000_regdump(hw, reginfo);
249 }
250
251 /* Print Tx Ring Summary */
252 if (!netdev || !netif_running(netdev))
253 return;
254
255 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
256 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
257 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
258 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
259 0, tx_ring->next_to_use, tx_ring->next_to_clean,
260 (unsigned long long)buffer_info->dma,
261 buffer_info->length,
262 buffer_info->next_to_watch,
263 (unsigned long long)buffer_info->time_stamp);
264
265 /* Print Tx Ring */
266 if (!netif_msg_tx_done(adapter))
267 goto rx_ring_summary;
268
269 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
270
271 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
272 *
273 * Legacy Transmit Descriptor
274 * +--------------------------------------------------------------+
275 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
276 * +--------------------------------------------------------------+
277 * 8 | Special | CSS | Status | CMD | CSO | Length |
278 * +--------------------------------------------------------------+
279 * 63 48 47 36 35 32 31 24 23 16 15 0
280 *
281 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
282 * 63 48 47 40 39 32 31 16 15 8 7 0
283 * +----------------------------------------------------------------+
284 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
285 * +----------------------------------------------------------------+
286 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
287 * +----------------------------------------------------------------+
288 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
289 *
290 * Extended Data Descriptor (DTYP=0x1)
291 * +----------------------------------------------------------------+
292 * 0 | Buffer Address [63:0] |
293 * +----------------------------------------------------------------+
294 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
295 * +----------------------------------------------------------------+
296 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
297 */
298 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
299 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
300 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
301 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
302 const char *next_desc;
303 tx_desc = E1000_TX_DESC(*tx_ring, i);
304 buffer_info = &tx_ring->buffer_info[i];
305 u0 = (struct my_u0 *)tx_desc;
306 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
307 next_desc = " NTC/U";
308 else if (i == tx_ring->next_to_use)
309 next_desc = " NTU";
310 else if (i == tx_ring->next_to_clean)
311 next_desc = " NTC";
312 else
313 next_desc = "";
314 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
315 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
316 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
317 i,
318 (unsigned long long)le64_to_cpu(u0->a),
319 (unsigned long long)le64_to_cpu(u0->b),
320 (unsigned long long)buffer_info->dma,
321 buffer_info->length, buffer_info->next_to_watch,
322 (unsigned long long)buffer_info->time_stamp,
323 buffer_info->skb, next_desc);
324
325 if (netif_msg_pktdata(adapter) && buffer_info->skb)
326 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
327 16, 1, buffer_info->skb->data,
328 buffer_info->skb->len, true);
329 }
330
331 /* Print Rx Ring Summary */
332 rx_ring_summary:
333 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
334 pr_info("Queue [NTU] [NTC]\n");
335 pr_info(" %5d %5X %5X\n",
336 0, rx_ring->next_to_use, rx_ring->next_to_clean);
337
338 /* Print Rx Ring */
339 if (!netif_msg_rx_status(adapter))
340 return;
341
342 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
343 switch (adapter->rx_ps_pages) {
344 case 1:
345 case 2:
346 case 3:
347 /* [Extended] Packet Split Receive Descriptor Format
348 *
349 * +-----------------------------------------------------+
350 * 0 | Buffer Address 0 [63:0] |
351 * +-----------------------------------------------------+
352 * 8 | Buffer Address 1 [63:0] |
353 * +-----------------------------------------------------+
354 * 16 | Buffer Address 2 [63:0] |
355 * +-----------------------------------------------------+
356 * 24 | Buffer Address 3 [63:0] |
357 * +-----------------------------------------------------+
358 */
359 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
360 /* [Extended] Receive Descriptor (Write-Back) Format
361 *
362 * 63 48 47 32 31 13 12 8 7 4 3 0
363 * +------------------------------------------------------+
364 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
365 * | Checksum | Ident | | Queue | | Type |
366 * +------------------------------------------------------+
367 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
368 * +------------------------------------------------------+
369 * 63 48 47 32 31 20 19 0
370 */
371 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
372 for (i = 0; i < rx_ring->count; i++) {
373 const char *next_desc;
374 buffer_info = &rx_ring->buffer_info[i];
375 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
376 u1 = (struct my_u1 *)rx_desc_ps;
377 staterr =
378 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
379
380 if (i == rx_ring->next_to_use)
381 next_desc = " NTU";
382 else if (i == rx_ring->next_to_clean)
383 next_desc = " NTC";
384 else
385 next_desc = "";
386
387 if (staterr & E1000_RXD_STAT_DD) {
388 /* Descriptor Done */
389 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
390 "RWB", i,
391 (unsigned long long)le64_to_cpu(u1->a),
392 (unsigned long long)le64_to_cpu(u1->b),
393 (unsigned long long)le64_to_cpu(u1->c),
394 (unsigned long long)le64_to_cpu(u1->d),
395 buffer_info->skb, next_desc);
396 } else {
397 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
398 "R ", i,
399 (unsigned long long)le64_to_cpu(u1->a),
400 (unsigned long long)le64_to_cpu(u1->b),
401 (unsigned long long)le64_to_cpu(u1->c),
402 (unsigned long long)le64_to_cpu(u1->d),
403 (unsigned long long)buffer_info->dma,
404 buffer_info->skb, next_desc);
405
406 if (netif_msg_pktdata(adapter))
407 e1000e_dump_ps_pages(adapter,
408 buffer_info);
409 }
410 }
411 break;
412 default:
413 case 0:
414 /* Extended Receive Descriptor (Read) Format
415 *
416 * +-----------------------------------------------------+
417 * 0 | Buffer Address [63:0] |
418 * +-----------------------------------------------------+
419 * 8 | Reserved |
420 * +-----------------------------------------------------+
421 */
422 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
423 /* Extended Receive Descriptor (Write-Back) Format
424 *
425 * 63 48 47 32 31 24 23 4 3 0
426 * +------------------------------------------------------+
427 * | RSS Hash | | | |
428 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
429 * | Packet | IP | | | Type |
430 * | Checksum | Ident | | | |
431 * +------------------------------------------------------+
432 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
433 * +------------------------------------------------------+
434 * 63 48 47 32 31 20 19 0
435 */
436 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
437
438 for (i = 0; i < rx_ring->count; i++) {
439 const char *next_desc;
440
441 buffer_info = &rx_ring->buffer_info[i];
442 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
443 u1 = (struct my_u1 *)rx_desc;
444 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
445
446 if (i == rx_ring->next_to_use)
447 next_desc = " NTU";
448 else if (i == rx_ring->next_to_clean)
449 next_desc = " NTC";
450 else
451 next_desc = "";
452
453 if (staterr & E1000_RXD_STAT_DD) {
454 /* Descriptor Done */
455 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
456 "RWB", i,
457 (unsigned long long)le64_to_cpu(u1->a),
458 (unsigned long long)le64_to_cpu(u1->b),
459 buffer_info->skb, next_desc);
460 } else {
461 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
462 "R ", i,
463 (unsigned long long)le64_to_cpu(u1->a),
464 (unsigned long long)le64_to_cpu(u1->b),
465 (unsigned long long)buffer_info->dma,
466 buffer_info->skb, next_desc);
467
468 if (netif_msg_pktdata(adapter) &&
469 buffer_info->skb)
470 print_hex_dump(KERN_INFO, "",
471 DUMP_PREFIX_ADDRESS, 16,
472 1,
473 buffer_info->skb->data,
474 adapter->rx_buffer_len,
475 true);
476 }
477 }
478 }
479 }
480
481 /**
482 * e1000_desc_unused - calculate if we have unused descriptors
483 * @ring: pointer to ring struct to perform calculation on
484 **/
e1000_desc_unused(struct e1000_ring * ring)485 static int e1000_desc_unused(struct e1000_ring *ring)
486 {
487 if (ring->next_to_clean > ring->next_to_use)
488 return ring->next_to_clean - ring->next_to_use - 1;
489
490 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
491 }
492
493 /**
494 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
495 * @adapter: board private structure
496 * @hwtstamps: time stamp structure to update
497 * @systim: unsigned 64bit system time value.
498 *
499 * Convert the system time value stored in the RX/TXSTMP registers into a
500 * hwtstamp which can be used by the upper level time stamping functions.
501 *
502 * The 'systim_lock' spinlock is used to protect the consistency of the
503 * system time value. This is needed because reading the 64 bit time
504 * value involves reading two 32 bit registers. The first read latches the
505 * value.
506 **/
e1000e_systim_to_hwtstamp(struct e1000_adapter * adapter,struct skb_shared_hwtstamps * hwtstamps,u64 systim)507 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
508 struct skb_shared_hwtstamps *hwtstamps,
509 u64 systim)
510 {
511 u64 ns;
512 unsigned long flags;
513
514 spin_lock_irqsave(&adapter->systim_lock, flags);
515 ns = timecounter_cyc2time(&adapter->tc, systim);
516 spin_unlock_irqrestore(&adapter->systim_lock, flags);
517
518 memset(hwtstamps, 0, sizeof(*hwtstamps));
519 hwtstamps->hwtstamp = ns_to_ktime(ns);
520 }
521
522 /**
523 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
524 * @adapter: board private structure
525 * @status: descriptor extended error and status field
526 * @skb: particular skb to include time stamp
527 *
528 * If the time stamp is valid, convert it into the timecounter ns value
529 * and store that result into the shhwtstamps structure which is passed
530 * up the network stack.
531 **/
e1000e_rx_hwtstamp(struct e1000_adapter * adapter,u32 status,struct sk_buff * skb)532 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
533 struct sk_buff *skb)
534 {
535 struct e1000_hw *hw = &adapter->hw;
536 u64 rxstmp;
537
538 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
539 !(status & E1000_RXDEXT_STATERR_TST) ||
540 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
541 return;
542
543 /* The Rx time stamp registers contain the time stamp. No other
544 * received packet will be time stamped until the Rx time stamp
545 * registers are read. Because only one packet can be time stamped
546 * at a time, the register values must belong to this packet and
547 * therefore none of the other additional attributes need to be
548 * compared.
549 */
550 rxstmp = (u64)er32(RXSTMPL);
551 rxstmp |= (u64)er32(RXSTMPH) << 32;
552 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
553
554 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
555 }
556
557 /**
558 * e1000_receive_skb - helper function to handle Rx indications
559 * @adapter: board private structure
560 * @netdev: pointer to netdev struct
561 * @staterr: descriptor extended error and status field as written by hardware
562 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
563 * @skb: pointer to sk_buff to be indicated to stack
564 **/
e1000_receive_skb(struct e1000_adapter * adapter,struct net_device * netdev,struct sk_buff * skb,u32 staterr,__le16 vlan)565 static void e1000_receive_skb(struct e1000_adapter *adapter,
566 struct net_device *netdev, struct sk_buff *skb,
567 u32 staterr, __le16 vlan)
568 {
569 u16 tag = le16_to_cpu(vlan);
570
571 e1000e_rx_hwtstamp(adapter, staterr, skb);
572
573 skb->protocol = eth_type_trans(skb, netdev);
574
575 if (staterr & E1000_RXD_STAT_VP)
576 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
577
578 napi_gro_receive(&adapter->napi, skb);
579 }
580
581 /**
582 * e1000_rx_checksum - Receive Checksum Offload
583 * @adapter: board private structure
584 * @status_err: receive descriptor status and error fields
585 * @skb: socket buffer with received data
586 **/
e1000_rx_checksum(struct e1000_adapter * adapter,u32 status_err,struct sk_buff * skb)587 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
588 struct sk_buff *skb)
589 {
590 u16 status = (u16)status_err;
591 u8 errors = (u8)(status_err >> 24);
592
593 skb_checksum_none_assert(skb);
594
595 /* Rx checksum disabled */
596 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
597 return;
598
599 /* Ignore Checksum bit is set */
600 if (status & E1000_RXD_STAT_IXSM)
601 return;
602
603 /* TCP/UDP checksum error bit or IP checksum error bit is set */
604 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
605 /* let the stack verify checksum errors */
606 adapter->hw_csum_err++;
607 return;
608 }
609
610 /* TCP/UDP Checksum has not been calculated */
611 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
612 return;
613
614 /* It must be a TCP or UDP packet with a valid checksum */
615 skb->ip_summed = CHECKSUM_UNNECESSARY;
616 adapter->hw_csum_good++;
617 }
618
e1000e_update_rdt_wa(struct e1000_ring * rx_ring,unsigned int i)619 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
620 {
621 struct e1000_adapter *adapter = rx_ring->adapter;
622 struct e1000_hw *hw = &adapter->hw;
623
624 __ew32_prepare(hw);
625 writel(i, rx_ring->tail);
626
627 if (unlikely(i != readl(rx_ring->tail))) {
628 u32 rctl = er32(RCTL);
629
630 ew32(RCTL, rctl & ~E1000_RCTL_EN);
631 e_err("ME firmware caused invalid RDT - resetting\n");
632 schedule_work(&adapter->reset_task);
633 }
634 }
635
e1000e_update_tdt_wa(struct e1000_ring * tx_ring,unsigned int i)636 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
637 {
638 struct e1000_adapter *adapter = tx_ring->adapter;
639 struct e1000_hw *hw = &adapter->hw;
640
641 __ew32_prepare(hw);
642 writel(i, tx_ring->tail);
643
644 if (unlikely(i != readl(tx_ring->tail))) {
645 u32 tctl = er32(TCTL);
646
647 ew32(TCTL, tctl & ~E1000_TCTL_EN);
648 e_err("ME firmware caused invalid TDT - resetting\n");
649 schedule_work(&adapter->reset_task);
650 }
651 }
652
653 /**
654 * e1000_alloc_rx_buffers - Replace used receive buffers
655 * @rx_ring: Rx descriptor ring
656 * @cleaned_count: number to reallocate
657 * @gfp: flags for allocation
658 **/
e1000_alloc_rx_buffers(struct e1000_ring * rx_ring,int cleaned_count,gfp_t gfp)659 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
660 int cleaned_count, gfp_t gfp)
661 {
662 struct e1000_adapter *adapter = rx_ring->adapter;
663 struct net_device *netdev = adapter->netdev;
664 struct pci_dev *pdev = adapter->pdev;
665 union e1000_rx_desc_extended *rx_desc;
666 struct e1000_buffer *buffer_info;
667 struct sk_buff *skb;
668 unsigned int i;
669 unsigned int bufsz = adapter->rx_buffer_len;
670
671 i = rx_ring->next_to_use;
672 buffer_info = &rx_ring->buffer_info[i];
673
674 while (cleaned_count--) {
675 skb = buffer_info->skb;
676 if (skb) {
677 skb_trim(skb, 0);
678 goto map_skb;
679 }
680
681 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
682 if (!skb) {
683 /* Better luck next round */
684 adapter->alloc_rx_buff_failed++;
685 break;
686 }
687
688 buffer_info->skb = skb;
689 map_skb:
690 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
691 adapter->rx_buffer_len,
692 DMA_FROM_DEVICE);
693 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
694 dev_err(&pdev->dev, "Rx DMA map failed\n");
695 adapter->rx_dma_failed++;
696 break;
697 }
698
699 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
700 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
701
702 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
703 /* Force memory writes to complete before letting h/w
704 * know there are new descriptors to fetch. (Only
705 * applicable for weak-ordered memory model archs,
706 * such as IA-64).
707 */
708 wmb();
709 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
710 e1000e_update_rdt_wa(rx_ring, i);
711 else
712 writel(i, rx_ring->tail);
713 }
714 i++;
715 if (i == rx_ring->count)
716 i = 0;
717 buffer_info = &rx_ring->buffer_info[i];
718 }
719
720 rx_ring->next_to_use = i;
721 }
722
723 /**
724 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
725 * @rx_ring: Rx descriptor ring
726 * @cleaned_count: number to reallocate
727 * @gfp: flags for allocation
728 **/
e1000_alloc_rx_buffers_ps(struct e1000_ring * rx_ring,int cleaned_count,gfp_t gfp)729 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
730 int cleaned_count, gfp_t gfp)
731 {
732 struct e1000_adapter *adapter = rx_ring->adapter;
733 struct net_device *netdev = adapter->netdev;
734 struct pci_dev *pdev = adapter->pdev;
735 union e1000_rx_desc_packet_split *rx_desc;
736 struct e1000_buffer *buffer_info;
737 struct e1000_ps_page *ps_page;
738 struct sk_buff *skb;
739 unsigned int i, j;
740
741 i = rx_ring->next_to_use;
742 buffer_info = &rx_ring->buffer_info[i];
743
744 while (cleaned_count--) {
745 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
746
747 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
748 ps_page = &buffer_info->ps_pages[j];
749 if (j >= adapter->rx_ps_pages) {
750 /* all unused desc entries get hw null ptr */
751 rx_desc->read.buffer_addr[j + 1] =
752 ~cpu_to_le64(0);
753 continue;
754 }
755 if (!ps_page->page) {
756 ps_page->page = alloc_page(gfp);
757 if (!ps_page->page) {
758 adapter->alloc_rx_buff_failed++;
759 goto no_buffers;
760 }
761 ps_page->dma = dma_map_page(&pdev->dev,
762 ps_page->page,
763 0, PAGE_SIZE,
764 DMA_FROM_DEVICE);
765 if (dma_mapping_error(&pdev->dev,
766 ps_page->dma)) {
767 dev_err(&adapter->pdev->dev,
768 "Rx DMA page map failed\n");
769 adapter->rx_dma_failed++;
770 goto no_buffers;
771 }
772 }
773 /* Refresh the desc even if buffer_addrs
774 * didn't change because each write-back
775 * erases this info.
776 */
777 rx_desc->read.buffer_addr[j + 1] =
778 cpu_to_le64(ps_page->dma);
779 }
780
781 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
782 gfp);
783
784 if (!skb) {
785 adapter->alloc_rx_buff_failed++;
786 break;
787 }
788
789 buffer_info->skb = skb;
790 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
791 adapter->rx_ps_bsize0,
792 DMA_FROM_DEVICE);
793 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
794 dev_err(&pdev->dev, "Rx DMA map failed\n");
795 adapter->rx_dma_failed++;
796 /* cleanup skb */
797 dev_kfree_skb_any(skb);
798 buffer_info->skb = NULL;
799 break;
800 }
801
802 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
803
804 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
805 /* Force memory writes to complete before letting h/w
806 * know there are new descriptors to fetch. (Only
807 * applicable for weak-ordered memory model archs,
808 * such as IA-64).
809 */
810 wmb();
811 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
812 e1000e_update_rdt_wa(rx_ring, i << 1);
813 else
814 writel(i << 1, rx_ring->tail);
815 }
816
817 i++;
818 if (i == rx_ring->count)
819 i = 0;
820 buffer_info = &rx_ring->buffer_info[i];
821 }
822
823 no_buffers:
824 rx_ring->next_to_use = i;
825 }
826
827 /**
828 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
829 * @rx_ring: Rx descriptor ring
830 * @cleaned_count: number of buffers to allocate this pass
831 * @gfp: flags for allocation
832 **/
833
e1000_alloc_jumbo_rx_buffers(struct e1000_ring * rx_ring,int cleaned_count,gfp_t gfp)834 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
835 int cleaned_count, gfp_t gfp)
836 {
837 struct e1000_adapter *adapter = rx_ring->adapter;
838 struct net_device *netdev = adapter->netdev;
839 struct pci_dev *pdev = adapter->pdev;
840 union e1000_rx_desc_extended *rx_desc;
841 struct e1000_buffer *buffer_info;
842 struct sk_buff *skb;
843 unsigned int i;
844 unsigned int bufsz = 256 - 16; /* for skb_reserve */
845
846 i = rx_ring->next_to_use;
847 buffer_info = &rx_ring->buffer_info[i];
848
849 while (cleaned_count--) {
850 skb = buffer_info->skb;
851 if (skb) {
852 skb_trim(skb, 0);
853 goto check_page;
854 }
855
856 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
857 if (unlikely(!skb)) {
858 /* Better luck next round */
859 adapter->alloc_rx_buff_failed++;
860 break;
861 }
862
863 buffer_info->skb = skb;
864 check_page:
865 /* allocate a new page if necessary */
866 if (!buffer_info->page) {
867 buffer_info->page = alloc_page(gfp);
868 if (unlikely(!buffer_info->page)) {
869 adapter->alloc_rx_buff_failed++;
870 break;
871 }
872 }
873
874 if (!buffer_info->dma) {
875 buffer_info->dma = dma_map_page(&pdev->dev,
876 buffer_info->page, 0,
877 PAGE_SIZE,
878 DMA_FROM_DEVICE);
879 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
880 adapter->alloc_rx_buff_failed++;
881 break;
882 }
883 }
884
885 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
886 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
887
888 if (unlikely(++i == rx_ring->count))
889 i = 0;
890 buffer_info = &rx_ring->buffer_info[i];
891 }
892
893 if (likely(rx_ring->next_to_use != i)) {
894 rx_ring->next_to_use = i;
895 if (unlikely(i-- == 0))
896 i = (rx_ring->count - 1);
897
898 /* Force memory writes to complete before letting h/w
899 * know there are new descriptors to fetch. (Only
900 * applicable for weak-ordered memory model archs,
901 * such as IA-64).
902 */
903 wmb();
904 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
905 e1000e_update_rdt_wa(rx_ring, i);
906 else
907 writel(i, rx_ring->tail);
908 }
909 }
910
e1000_rx_hash(struct net_device * netdev,__le32 rss,struct sk_buff * skb)911 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
912 struct sk_buff *skb)
913 {
914 if (netdev->features & NETIF_F_RXHASH)
915 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
916 }
917
918 /**
919 * e1000_clean_rx_irq - Send received data up the network stack
920 * @rx_ring: Rx descriptor ring
921 * @work_done: output parameter for indicating completed work
922 * @work_to_do: how many packets we can clean
923 *
924 * the return value indicates whether actual cleaning was done, there
925 * is no guarantee that everything was cleaned
926 **/
e1000_clean_rx_irq(struct e1000_ring * rx_ring,int * work_done,int work_to_do)927 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
928 int work_to_do)
929 {
930 struct e1000_adapter *adapter = rx_ring->adapter;
931 struct net_device *netdev = adapter->netdev;
932 struct pci_dev *pdev = adapter->pdev;
933 struct e1000_hw *hw = &adapter->hw;
934 union e1000_rx_desc_extended *rx_desc, *next_rxd;
935 struct e1000_buffer *buffer_info, *next_buffer;
936 u32 length, staterr;
937 unsigned int i;
938 int cleaned_count = 0;
939 bool cleaned = false;
940 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
941
942 i = rx_ring->next_to_clean;
943 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
944 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
945 buffer_info = &rx_ring->buffer_info[i];
946
947 while (staterr & E1000_RXD_STAT_DD) {
948 struct sk_buff *skb;
949
950 if (*work_done >= work_to_do)
951 break;
952 (*work_done)++;
953 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
954
955 skb = buffer_info->skb;
956 buffer_info->skb = NULL;
957
958 prefetch(skb->data - NET_IP_ALIGN);
959
960 i++;
961 if (i == rx_ring->count)
962 i = 0;
963 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
964 prefetch(next_rxd);
965
966 next_buffer = &rx_ring->buffer_info[i];
967
968 cleaned = true;
969 cleaned_count++;
970 dma_unmap_single(&pdev->dev, buffer_info->dma,
971 adapter->rx_buffer_len, DMA_FROM_DEVICE);
972 buffer_info->dma = 0;
973
974 length = le16_to_cpu(rx_desc->wb.upper.length);
975
976 /* !EOP means multiple descriptors were used to store a single
977 * packet, if that's the case we need to toss it. In fact, we
978 * need to toss every packet with the EOP bit clear and the
979 * next frame that _does_ have the EOP bit set, as it is by
980 * definition only a frame fragment
981 */
982 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
983 adapter->flags2 |= FLAG2_IS_DISCARDING;
984
985 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
986 /* All receives must fit into a single buffer */
987 e_dbg("Receive packet consumed multiple buffers\n");
988 /* recycle */
989 buffer_info->skb = skb;
990 if (staterr & E1000_RXD_STAT_EOP)
991 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
992 goto next_desc;
993 }
994
995 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
996 !(netdev->features & NETIF_F_RXALL))) {
997 /* recycle */
998 buffer_info->skb = skb;
999 goto next_desc;
1000 }
1001
1002 /* adjust length to remove Ethernet CRC */
1003 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1004 /* If configured to store CRC, don't subtract FCS,
1005 * but keep the FCS bytes out of the total_rx_bytes
1006 * counter
1007 */
1008 if (netdev->features & NETIF_F_RXFCS)
1009 total_rx_bytes -= 4;
1010 else
1011 length -= 4;
1012 }
1013
1014 total_rx_bytes += length;
1015 total_rx_packets++;
1016
1017 /* code added for copybreak, this should improve
1018 * performance for small packets with large amounts
1019 * of reassembly being done in the stack
1020 */
1021 if (length < copybreak) {
1022 struct sk_buff *new_skb =
1023 napi_alloc_skb(&adapter->napi, length);
1024 if (new_skb) {
1025 skb_copy_to_linear_data_offset(new_skb,
1026 -NET_IP_ALIGN,
1027 (skb->data -
1028 NET_IP_ALIGN),
1029 (length +
1030 NET_IP_ALIGN));
1031 /* save the skb in buffer_info as good */
1032 buffer_info->skb = skb;
1033 skb = new_skb;
1034 }
1035 /* else just continue with the old one */
1036 }
1037 /* end copybreak code */
1038 skb_put(skb, length);
1039
1040 /* Receive Checksum Offload */
1041 e1000_rx_checksum(adapter, staterr, skb);
1042
1043 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1044
1045 e1000_receive_skb(adapter, netdev, skb, staterr,
1046 rx_desc->wb.upper.vlan);
1047
1048 next_desc:
1049 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1050
1051 /* return some buffers to hardware, one at a time is too slow */
1052 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1053 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1054 GFP_ATOMIC);
1055 cleaned_count = 0;
1056 }
1057
1058 /* use prefetched values */
1059 rx_desc = next_rxd;
1060 buffer_info = next_buffer;
1061
1062 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1063 }
1064 rx_ring->next_to_clean = i;
1065
1066 cleaned_count = e1000_desc_unused(rx_ring);
1067 if (cleaned_count)
1068 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1069
1070 adapter->total_rx_bytes += total_rx_bytes;
1071 adapter->total_rx_packets += total_rx_packets;
1072 return cleaned;
1073 }
1074
e1000_put_txbuf(struct e1000_ring * tx_ring,struct e1000_buffer * buffer_info,bool drop)1075 static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1076 struct e1000_buffer *buffer_info,
1077 bool drop)
1078 {
1079 struct e1000_adapter *adapter = tx_ring->adapter;
1080
1081 if (buffer_info->dma) {
1082 if (buffer_info->mapped_as_page)
1083 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1084 buffer_info->length, DMA_TO_DEVICE);
1085 else
1086 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1087 buffer_info->length, DMA_TO_DEVICE);
1088 buffer_info->dma = 0;
1089 }
1090 if (buffer_info->skb) {
1091 if (drop)
1092 dev_kfree_skb_any(buffer_info->skb);
1093 else
1094 dev_consume_skb_any(buffer_info->skb);
1095 buffer_info->skb = NULL;
1096 }
1097 buffer_info->time_stamp = 0;
1098 }
1099
e1000_print_hw_hang(struct work_struct * work)1100 static void e1000_print_hw_hang(struct work_struct *work)
1101 {
1102 struct e1000_adapter *adapter = container_of(work,
1103 struct e1000_adapter,
1104 print_hang_task);
1105 struct net_device *netdev = adapter->netdev;
1106 struct e1000_ring *tx_ring = adapter->tx_ring;
1107 unsigned int i = tx_ring->next_to_clean;
1108 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1109 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1110 struct e1000_hw *hw = &adapter->hw;
1111 u16 phy_status, phy_1000t_status, phy_ext_status;
1112 u16 pci_status;
1113
1114 if (test_bit(__E1000_DOWN, &adapter->state))
1115 return;
1116
1117 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
1118 /* May be block on write-back, flush and detect again
1119 * flush pending descriptor writebacks to memory
1120 */
1121 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1122 /* execute the writes immediately */
1123 e1e_flush();
1124 /* Due to rare timing issues, write to TIDV again to ensure
1125 * the write is successful
1126 */
1127 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1128 /* execute the writes immediately */
1129 e1e_flush();
1130 adapter->tx_hang_recheck = true;
1131 return;
1132 }
1133 adapter->tx_hang_recheck = false;
1134
1135 if (er32(TDH(0)) == er32(TDT(0))) {
1136 e_dbg("false hang detected, ignoring\n");
1137 return;
1138 }
1139
1140 /* Real hang detected */
1141 netif_stop_queue(netdev);
1142
1143 e1e_rphy(hw, MII_BMSR, &phy_status);
1144 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1145 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
1146
1147 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1148
1149 /* detected Hardware unit hang */
1150 e_err("Detected Hardware Unit Hang:\n"
1151 " TDH <%x>\n"
1152 " TDT <%x>\n"
1153 " next_to_use <%x>\n"
1154 " next_to_clean <%x>\n"
1155 "buffer_info[next_to_clean]:\n"
1156 " time_stamp <%lx>\n"
1157 " next_to_watch <%x>\n"
1158 " jiffies <%lx>\n"
1159 " next_to_watch.status <%x>\n"
1160 "MAC Status <%x>\n"
1161 "PHY Status <%x>\n"
1162 "PHY 1000BASE-T Status <%x>\n"
1163 "PHY Extended Status <%x>\n"
1164 "PCI Status <%x>\n",
1165 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1166 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1167 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1168 phy_status, phy_1000t_status, phy_ext_status, pci_status);
1169
1170 e1000e_dump(adapter);
1171
1172 /* Suggest workaround for known h/w issue */
1173 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1174 e_err("Try turning off Tx pause (flow control) via ethtool\n");
1175 }
1176
1177 /**
1178 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1179 * @work: pointer to work struct
1180 *
1181 * This work function polls the TSYNCTXCTL valid bit to determine when a
1182 * timestamp has been taken for the current stored skb. The timestamp must
1183 * be for this skb because only one such packet is allowed in the queue.
1184 */
e1000e_tx_hwtstamp_work(struct work_struct * work)1185 static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1186 {
1187 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1188 tx_hwtstamp_work);
1189 struct e1000_hw *hw = &adapter->hw;
1190
1191 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1192 struct sk_buff *skb = adapter->tx_hwtstamp_skb;
1193 struct skb_shared_hwtstamps shhwtstamps;
1194 u64 txstmp;
1195
1196 txstmp = er32(TXSTMPL);
1197 txstmp |= (u64)er32(TXSTMPH) << 32;
1198
1199 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1200
1201 /* Clear the global tx_hwtstamp_skb pointer and force writes
1202 * prior to notifying the stack of a Tx timestamp.
1203 */
1204 adapter->tx_hwtstamp_skb = NULL;
1205 wmb(); /* force write prior to skb_tstamp_tx */
1206
1207 skb_tstamp_tx(skb, &shhwtstamps);
1208 dev_consume_skb_any(skb);
1209 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1210 + adapter->tx_timeout_factor * HZ)) {
1211 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1212 adapter->tx_hwtstamp_skb = NULL;
1213 adapter->tx_hwtstamp_timeouts++;
1214 e_warn("clearing Tx timestamp hang\n");
1215 } else {
1216 /* reschedule to check later */
1217 schedule_work(&adapter->tx_hwtstamp_work);
1218 }
1219 }
1220
1221 /**
1222 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1223 * @tx_ring: Tx descriptor ring
1224 *
1225 * the return value indicates whether actual cleaning was done, there
1226 * is no guarantee that everything was cleaned
1227 **/
e1000_clean_tx_irq(struct e1000_ring * tx_ring)1228 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1229 {
1230 struct e1000_adapter *adapter = tx_ring->adapter;
1231 struct net_device *netdev = adapter->netdev;
1232 struct e1000_hw *hw = &adapter->hw;
1233 struct e1000_tx_desc *tx_desc, *eop_desc;
1234 struct e1000_buffer *buffer_info;
1235 unsigned int i, eop;
1236 unsigned int count = 0;
1237 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1238 unsigned int bytes_compl = 0, pkts_compl = 0;
1239
1240 i = tx_ring->next_to_clean;
1241 eop = tx_ring->buffer_info[i].next_to_watch;
1242 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1243
1244 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1245 (count < tx_ring->count)) {
1246 bool cleaned = false;
1247
1248 dma_rmb(); /* read buffer_info after eop_desc */
1249 for (; !cleaned; count++) {
1250 tx_desc = E1000_TX_DESC(*tx_ring, i);
1251 buffer_info = &tx_ring->buffer_info[i];
1252 cleaned = (i == eop);
1253
1254 if (cleaned) {
1255 total_tx_packets += buffer_info->segs;
1256 total_tx_bytes += buffer_info->bytecount;
1257 if (buffer_info->skb) {
1258 bytes_compl += buffer_info->skb->len;
1259 pkts_compl++;
1260 }
1261 }
1262
1263 e1000_put_txbuf(tx_ring, buffer_info, false);
1264 tx_desc->upper.data = 0;
1265
1266 i++;
1267 if (i == tx_ring->count)
1268 i = 0;
1269 }
1270
1271 if (i == tx_ring->next_to_use)
1272 break;
1273 eop = tx_ring->buffer_info[i].next_to_watch;
1274 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1275 }
1276
1277 tx_ring->next_to_clean = i;
1278
1279 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1280
1281 #define TX_WAKE_THRESHOLD 32
1282 if (count && netif_carrier_ok(netdev) &&
1283 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
1284 /* Make sure that anybody stopping the queue after this
1285 * sees the new next_to_clean.
1286 */
1287 smp_mb();
1288
1289 if (netif_queue_stopped(netdev) &&
1290 !(test_bit(__E1000_DOWN, &adapter->state))) {
1291 netif_wake_queue(netdev);
1292 ++adapter->restart_queue;
1293 }
1294 }
1295
1296 if (adapter->detect_tx_hung) {
1297 /* Detect a transmit hang in hardware, this serializes the
1298 * check with the clearing of time_stamp and movement of i
1299 */
1300 adapter->detect_tx_hung = false;
1301 if (tx_ring->buffer_info[i].time_stamp &&
1302 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1303 + (adapter->tx_timeout_factor * HZ)) &&
1304 !(er32(STATUS) & E1000_STATUS_TXOFF))
1305 schedule_work(&adapter->print_hang_task);
1306 else
1307 adapter->tx_hang_recheck = false;
1308 }
1309 adapter->total_tx_bytes += total_tx_bytes;
1310 adapter->total_tx_packets += total_tx_packets;
1311 return count < tx_ring->count;
1312 }
1313
1314 /**
1315 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1316 * @rx_ring: Rx descriptor ring
1317 * @work_done: output parameter for indicating completed work
1318 * @work_to_do: how many packets we can clean
1319 *
1320 * the return value indicates whether actual cleaning was done, there
1321 * is no guarantee that everything was cleaned
1322 **/
e1000_clean_rx_irq_ps(struct e1000_ring * rx_ring,int * work_done,int work_to_do)1323 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1324 int work_to_do)
1325 {
1326 struct e1000_adapter *adapter = rx_ring->adapter;
1327 struct e1000_hw *hw = &adapter->hw;
1328 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1329 struct net_device *netdev = adapter->netdev;
1330 struct pci_dev *pdev = adapter->pdev;
1331 struct e1000_buffer *buffer_info, *next_buffer;
1332 struct e1000_ps_page *ps_page;
1333 struct sk_buff *skb;
1334 unsigned int i, j;
1335 u32 length, staterr;
1336 int cleaned_count = 0;
1337 bool cleaned = false;
1338 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1339
1340 i = rx_ring->next_to_clean;
1341 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1342 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1343 buffer_info = &rx_ring->buffer_info[i];
1344
1345 while (staterr & E1000_RXD_STAT_DD) {
1346 if (*work_done >= work_to_do)
1347 break;
1348 (*work_done)++;
1349 skb = buffer_info->skb;
1350 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1351
1352 /* in the packet split case this is header only */
1353 prefetch(skb->data - NET_IP_ALIGN);
1354
1355 i++;
1356 if (i == rx_ring->count)
1357 i = 0;
1358 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1359 prefetch(next_rxd);
1360
1361 next_buffer = &rx_ring->buffer_info[i];
1362
1363 cleaned = true;
1364 cleaned_count++;
1365 dma_unmap_single(&pdev->dev, buffer_info->dma,
1366 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1367 buffer_info->dma = 0;
1368
1369 /* see !EOP comment in other Rx routine */
1370 if (!(staterr & E1000_RXD_STAT_EOP))
1371 adapter->flags2 |= FLAG2_IS_DISCARDING;
1372
1373 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1374 e_dbg("Packet Split buffers didn't pick up the full packet\n");
1375 dev_kfree_skb_irq(skb);
1376 if (staterr & E1000_RXD_STAT_EOP)
1377 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1378 goto next_desc;
1379 }
1380
1381 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1382 !(netdev->features & NETIF_F_RXALL))) {
1383 dev_kfree_skb_irq(skb);
1384 goto next_desc;
1385 }
1386
1387 length = le16_to_cpu(rx_desc->wb.middle.length0);
1388
1389 if (!length) {
1390 e_dbg("Last part of the packet spanning multiple descriptors\n");
1391 dev_kfree_skb_irq(skb);
1392 goto next_desc;
1393 }
1394
1395 /* Good Receive */
1396 skb_put(skb, length);
1397
1398 {
1399 /* this looks ugly, but it seems compiler issues make
1400 * it more efficient than reusing j
1401 */
1402 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1403
1404 /* page alloc/put takes too long and effects small
1405 * packet throughput, so unsplit small packets and
1406 * save the alloc/put
1407 */
1408 if (l1 && (l1 <= copybreak) &&
1409 ((length + l1) <= adapter->rx_ps_bsize0)) {
1410 ps_page = &buffer_info->ps_pages[0];
1411
1412 dma_sync_single_for_cpu(&pdev->dev,
1413 ps_page->dma,
1414 PAGE_SIZE,
1415 DMA_FROM_DEVICE);
1416 memcpy(skb_tail_pointer(skb),
1417 page_address(ps_page->page), l1);
1418 dma_sync_single_for_device(&pdev->dev,
1419 ps_page->dma,
1420 PAGE_SIZE,
1421 DMA_FROM_DEVICE);
1422
1423 /* remove the CRC */
1424 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1425 if (!(netdev->features & NETIF_F_RXFCS))
1426 l1 -= 4;
1427 }
1428
1429 skb_put(skb, l1);
1430 goto copydone;
1431 } /* if */
1432 }
1433
1434 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1435 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1436 if (!length)
1437 break;
1438
1439 ps_page = &buffer_info->ps_pages[j];
1440 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1441 DMA_FROM_DEVICE);
1442 ps_page->dma = 0;
1443 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1444 ps_page->page = NULL;
1445 skb->len += length;
1446 skb->data_len += length;
1447 skb->truesize += PAGE_SIZE;
1448 }
1449
1450 /* strip the ethernet crc, problem is we're using pages now so
1451 * this whole operation can get a little cpu intensive
1452 */
1453 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1454 if (!(netdev->features & NETIF_F_RXFCS))
1455 pskb_trim(skb, skb->len - 4);
1456 }
1457
1458 copydone:
1459 total_rx_bytes += skb->len;
1460 total_rx_packets++;
1461
1462 e1000_rx_checksum(adapter, staterr, skb);
1463
1464 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1465
1466 if (rx_desc->wb.upper.header_status &
1467 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1468 adapter->rx_hdr_split++;
1469
1470 e1000_receive_skb(adapter, netdev, skb, staterr,
1471 rx_desc->wb.middle.vlan);
1472
1473 next_desc:
1474 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1475 buffer_info->skb = NULL;
1476
1477 /* return some buffers to hardware, one at a time is too slow */
1478 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1479 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1480 GFP_ATOMIC);
1481 cleaned_count = 0;
1482 }
1483
1484 /* use prefetched values */
1485 rx_desc = next_rxd;
1486 buffer_info = next_buffer;
1487
1488 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1489 }
1490 rx_ring->next_to_clean = i;
1491
1492 cleaned_count = e1000_desc_unused(rx_ring);
1493 if (cleaned_count)
1494 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1495
1496 adapter->total_rx_bytes += total_rx_bytes;
1497 adapter->total_rx_packets += total_rx_packets;
1498 return cleaned;
1499 }
1500
e1000_consume_page(struct e1000_buffer * bi,struct sk_buff * skb,u16 length)1501 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1502 u16 length)
1503 {
1504 bi->page = NULL;
1505 skb->len += length;
1506 skb->data_len += length;
1507 skb->truesize += PAGE_SIZE;
1508 }
1509
1510 /**
1511 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1512 * @rx_ring: Rx descriptor ring
1513 * @work_done: output parameter for indicating completed work
1514 * @work_to_do: how many packets we can clean
1515 *
1516 * the return value indicates whether actual cleaning was done, there
1517 * is no guarantee that everything was cleaned
1518 **/
e1000_clean_jumbo_rx_irq(struct e1000_ring * rx_ring,int * work_done,int work_to_do)1519 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1520 int work_to_do)
1521 {
1522 struct e1000_adapter *adapter = rx_ring->adapter;
1523 struct net_device *netdev = adapter->netdev;
1524 struct pci_dev *pdev = adapter->pdev;
1525 union e1000_rx_desc_extended *rx_desc, *next_rxd;
1526 struct e1000_buffer *buffer_info, *next_buffer;
1527 u32 length, staterr;
1528 unsigned int i;
1529 int cleaned_count = 0;
1530 bool cleaned = false;
1531 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1532 struct skb_shared_info *shinfo;
1533
1534 i = rx_ring->next_to_clean;
1535 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1536 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1537 buffer_info = &rx_ring->buffer_info[i];
1538
1539 while (staterr & E1000_RXD_STAT_DD) {
1540 struct sk_buff *skb;
1541
1542 if (*work_done >= work_to_do)
1543 break;
1544 (*work_done)++;
1545 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1546
1547 skb = buffer_info->skb;
1548 buffer_info->skb = NULL;
1549
1550 ++i;
1551 if (i == rx_ring->count)
1552 i = 0;
1553 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1554 prefetch(next_rxd);
1555
1556 next_buffer = &rx_ring->buffer_info[i];
1557
1558 cleaned = true;
1559 cleaned_count++;
1560 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1561 DMA_FROM_DEVICE);
1562 buffer_info->dma = 0;
1563
1564 length = le16_to_cpu(rx_desc->wb.upper.length);
1565
1566 /* errors is only valid for DD + EOP descriptors */
1567 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1568 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1569 !(netdev->features & NETIF_F_RXALL)))) {
1570 /* recycle both page and skb */
1571 buffer_info->skb = skb;
1572 /* an error means any chain goes out the window too */
1573 if (rx_ring->rx_skb_top)
1574 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1575 rx_ring->rx_skb_top = NULL;
1576 goto next_desc;
1577 }
1578 #define rxtop (rx_ring->rx_skb_top)
1579 if (!(staterr & E1000_RXD_STAT_EOP)) {
1580 /* this descriptor is only the beginning (or middle) */
1581 if (!rxtop) {
1582 /* this is the beginning of a chain */
1583 rxtop = skb;
1584 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1585 0, length);
1586 } else {
1587 /* this is the middle of a chain */
1588 shinfo = skb_shinfo(rxtop);
1589 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1590 buffer_info->page, 0,
1591 length);
1592 /* re-use the skb, only consumed the page */
1593 buffer_info->skb = skb;
1594 }
1595 e1000_consume_page(buffer_info, rxtop, length);
1596 goto next_desc;
1597 } else {
1598 if (rxtop) {
1599 /* end of the chain */
1600 shinfo = skb_shinfo(rxtop);
1601 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1602 buffer_info->page, 0,
1603 length);
1604 /* re-use the current skb, we only consumed the
1605 * page
1606 */
1607 buffer_info->skb = skb;
1608 skb = rxtop;
1609 rxtop = NULL;
1610 e1000_consume_page(buffer_info, skb, length);
1611 } else {
1612 /* no chain, got EOP, this buf is the packet
1613 * copybreak to save the put_page/alloc_page
1614 */
1615 if (length <= copybreak &&
1616 skb_tailroom(skb) >= length) {
1617 memcpy(skb_tail_pointer(skb),
1618 page_address(buffer_info->page),
1619 length);
1620 /* re-use the page, so don't erase
1621 * buffer_info->page
1622 */
1623 skb_put(skb, length);
1624 } else {
1625 skb_fill_page_desc(skb, 0,
1626 buffer_info->page, 0,
1627 length);
1628 e1000_consume_page(buffer_info, skb,
1629 length);
1630 }
1631 }
1632 }
1633
1634 /* Receive Checksum Offload */
1635 e1000_rx_checksum(adapter, staterr, skb);
1636
1637 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1638
1639 /* probably a little skewed due to removing CRC */
1640 total_rx_bytes += skb->len;
1641 total_rx_packets++;
1642
1643 /* eth type trans needs skb->data to point to something */
1644 if (!pskb_may_pull(skb, ETH_HLEN)) {
1645 e_err("pskb_may_pull failed.\n");
1646 dev_kfree_skb_irq(skb);
1647 goto next_desc;
1648 }
1649
1650 e1000_receive_skb(adapter, netdev, skb, staterr,
1651 rx_desc->wb.upper.vlan);
1652
1653 next_desc:
1654 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1655
1656 /* return some buffers to hardware, one at a time is too slow */
1657 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1658 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1659 GFP_ATOMIC);
1660 cleaned_count = 0;
1661 }
1662
1663 /* use prefetched values */
1664 rx_desc = next_rxd;
1665 buffer_info = next_buffer;
1666
1667 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1668 }
1669 rx_ring->next_to_clean = i;
1670
1671 cleaned_count = e1000_desc_unused(rx_ring);
1672 if (cleaned_count)
1673 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1674
1675 adapter->total_rx_bytes += total_rx_bytes;
1676 adapter->total_rx_packets += total_rx_packets;
1677 return cleaned;
1678 }
1679
1680 /**
1681 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1682 * @rx_ring: Rx descriptor ring
1683 **/
e1000_clean_rx_ring(struct e1000_ring * rx_ring)1684 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1685 {
1686 struct e1000_adapter *adapter = rx_ring->adapter;
1687 struct e1000_buffer *buffer_info;
1688 struct e1000_ps_page *ps_page;
1689 struct pci_dev *pdev = adapter->pdev;
1690 unsigned int i, j;
1691
1692 /* Free all the Rx ring sk_buffs */
1693 for (i = 0; i < rx_ring->count; i++) {
1694 buffer_info = &rx_ring->buffer_info[i];
1695 if (buffer_info->dma) {
1696 if (adapter->clean_rx == e1000_clean_rx_irq)
1697 dma_unmap_single(&pdev->dev, buffer_info->dma,
1698 adapter->rx_buffer_len,
1699 DMA_FROM_DEVICE);
1700 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1701 dma_unmap_page(&pdev->dev, buffer_info->dma,
1702 PAGE_SIZE, DMA_FROM_DEVICE);
1703 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1704 dma_unmap_single(&pdev->dev, buffer_info->dma,
1705 adapter->rx_ps_bsize0,
1706 DMA_FROM_DEVICE);
1707 buffer_info->dma = 0;
1708 }
1709
1710 if (buffer_info->page) {
1711 put_page(buffer_info->page);
1712 buffer_info->page = NULL;
1713 }
1714
1715 if (buffer_info->skb) {
1716 dev_kfree_skb(buffer_info->skb);
1717 buffer_info->skb = NULL;
1718 }
1719
1720 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1721 ps_page = &buffer_info->ps_pages[j];
1722 if (!ps_page->page)
1723 break;
1724 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1725 DMA_FROM_DEVICE);
1726 ps_page->dma = 0;
1727 put_page(ps_page->page);
1728 ps_page->page = NULL;
1729 }
1730 }
1731
1732 /* there also may be some cached data from a chained receive */
1733 if (rx_ring->rx_skb_top) {
1734 dev_kfree_skb(rx_ring->rx_skb_top);
1735 rx_ring->rx_skb_top = NULL;
1736 }
1737
1738 /* Zero out the descriptor ring */
1739 memset(rx_ring->desc, 0, rx_ring->size);
1740
1741 rx_ring->next_to_clean = 0;
1742 rx_ring->next_to_use = 0;
1743 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1744 }
1745
e1000e_downshift_workaround(struct work_struct * work)1746 static void e1000e_downshift_workaround(struct work_struct *work)
1747 {
1748 struct e1000_adapter *adapter = container_of(work,
1749 struct e1000_adapter,
1750 downshift_task);
1751
1752 if (test_bit(__E1000_DOWN, &adapter->state))
1753 return;
1754
1755 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1756 }
1757
1758 /**
1759 * e1000_intr_msi - Interrupt Handler
1760 * @irq: interrupt number
1761 * @data: pointer to a network interface device structure
1762 **/
e1000_intr_msi(int __always_unused irq,void * data)1763 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1764 {
1765 struct net_device *netdev = data;
1766 struct e1000_adapter *adapter = netdev_priv(netdev);
1767 struct e1000_hw *hw = &adapter->hw;
1768 u32 icr = er32(ICR);
1769
1770 /* read ICR disables interrupts using IAM */
1771 if (icr & E1000_ICR_LSC) {
1772 hw->mac.get_link_status = true;
1773 /* ICH8 workaround-- Call gig speed drop workaround on cable
1774 * disconnect (LSC) before accessing any PHY registers
1775 */
1776 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1777 (!(er32(STATUS) & E1000_STATUS_LU)))
1778 schedule_work(&adapter->downshift_task);
1779
1780 /* 80003ES2LAN workaround-- For packet buffer work-around on
1781 * link down event; disable receives here in the ISR and reset
1782 * adapter in watchdog
1783 */
1784 if (netif_carrier_ok(netdev) &&
1785 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1786 /* disable receives */
1787 u32 rctl = er32(RCTL);
1788
1789 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1790 adapter->flags |= FLAG_RESTART_NOW;
1791 }
1792 /* guard against interrupt when we're going down */
1793 if (!test_bit(__E1000_DOWN, &adapter->state))
1794 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1795 }
1796
1797 /* Reset on uncorrectable ECC error */
1798 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1799 u32 pbeccsts = er32(PBECCSTS);
1800
1801 adapter->corr_errors +=
1802 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1803 adapter->uncorr_errors +=
1804 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
1805
1806 /* Do the reset outside of interrupt context */
1807 schedule_work(&adapter->reset_task);
1808
1809 /* return immediately since reset is imminent */
1810 return IRQ_HANDLED;
1811 }
1812
1813 if (napi_schedule_prep(&adapter->napi)) {
1814 adapter->total_tx_bytes = 0;
1815 adapter->total_tx_packets = 0;
1816 adapter->total_rx_bytes = 0;
1817 adapter->total_rx_packets = 0;
1818 __napi_schedule_irqoff(&adapter->napi);
1819 }
1820
1821 return IRQ_HANDLED;
1822 }
1823
1824 /**
1825 * e1000_intr - Interrupt Handler
1826 * @irq: interrupt number
1827 * @data: pointer to a network interface device structure
1828 **/
e1000_intr(int __always_unused irq,void * data)1829 static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1830 {
1831 struct net_device *netdev = data;
1832 struct e1000_adapter *adapter = netdev_priv(netdev);
1833 struct e1000_hw *hw = &adapter->hw;
1834 u32 rctl, icr = er32(ICR);
1835
1836 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1837 return IRQ_NONE; /* Not our interrupt */
1838
1839 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1840 * not set, then the adapter didn't send an interrupt
1841 */
1842 if (!(icr & E1000_ICR_INT_ASSERTED))
1843 return IRQ_NONE;
1844
1845 /* Interrupt Auto-Mask...upon reading ICR,
1846 * interrupts are masked. No need for the
1847 * IMC write
1848 */
1849
1850 if (icr & E1000_ICR_LSC) {
1851 hw->mac.get_link_status = true;
1852 /* ICH8 workaround-- Call gig speed drop workaround on cable
1853 * disconnect (LSC) before accessing any PHY registers
1854 */
1855 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1856 (!(er32(STATUS) & E1000_STATUS_LU)))
1857 schedule_work(&adapter->downshift_task);
1858
1859 /* 80003ES2LAN workaround--
1860 * For packet buffer work-around on link down event;
1861 * disable receives here in the ISR and
1862 * reset adapter in watchdog
1863 */
1864 if (netif_carrier_ok(netdev) &&
1865 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1866 /* disable receives */
1867 rctl = er32(RCTL);
1868 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1869 adapter->flags |= FLAG_RESTART_NOW;
1870 }
1871 /* guard against interrupt when we're going down */
1872 if (!test_bit(__E1000_DOWN, &adapter->state))
1873 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1874 }
1875
1876 /* Reset on uncorrectable ECC error */
1877 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1878 u32 pbeccsts = er32(PBECCSTS);
1879
1880 adapter->corr_errors +=
1881 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1882 adapter->uncorr_errors +=
1883 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
1884
1885 /* Do the reset outside of interrupt context */
1886 schedule_work(&adapter->reset_task);
1887
1888 /* return immediately since reset is imminent */
1889 return IRQ_HANDLED;
1890 }
1891
1892 if (napi_schedule_prep(&adapter->napi)) {
1893 adapter->total_tx_bytes = 0;
1894 adapter->total_tx_packets = 0;
1895 adapter->total_rx_bytes = 0;
1896 adapter->total_rx_packets = 0;
1897 __napi_schedule_irqoff(&adapter->napi);
1898 }
1899
1900 return IRQ_HANDLED;
1901 }
1902
e1000_msix_other(int __always_unused irq,void * data)1903 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1904 {
1905 struct net_device *netdev = data;
1906 struct e1000_adapter *adapter = netdev_priv(netdev);
1907 struct e1000_hw *hw = &adapter->hw;
1908 u32 icr = er32(ICR);
1909
1910 if (icr & adapter->eiac_mask)
1911 ew32(ICS, (icr & adapter->eiac_mask));
1912
1913 if (icr & E1000_ICR_LSC) {
1914 hw->mac.get_link_status = true;
1915 /* guard against interrupt when we're going down */
1916 if (!test_bit(__E1000_DOWN, &adapter->state))
1917 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1918 }
1919
1920 if (!test_bit(__E1000_DOWN, &adapter->state))
1921 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
1922
1923 return IRQ_HANDLED;
1924 }
1925
e1000_intr_msix_tx(int __always_unused irq,void * data)1926 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1927 {
1928 struct net_device *netdev = data;
1929 struct e1000_adapter *adapter = netdev_priv(netdev);
1930 struct e1000_hw *hw = &adapter->hw;
1931 struct e1000_ring *tx_ring = adapter->tx_ring;
1932
1933 adapter->total_tx_bytes = 0;
1934 adapter->total_tx_packets = 0;
1935
1936 if (!e1000_clean_tx_irq(tx_ring))
1937 /* Ring was not completely cleaned, so fire another interrupt */
1938 ew32(ICS, tx_ring->ims_val);
1939
1940 if (!test_bit(__E1000_DOWN, &adapter->state))
1941 ew32(IMS, adapter->tx_ring->ims_val);
1942
1943 return IRQ_HANDLED;
1944 }
1945
e1000_intr_msix_rx(int __always_unused irq,void * data)1946 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1947 {
1948 struct net_device *netdev = data;
1949 struct e1000_adapter *adapter = netdev_priv(netdev);
1950 struct e1000_ring *rx_ring = adapter->rx_ring;
1951
1952 /* Write the ITR value calculated at the end of the
1953 * previous interrupt.
1954 */
1955 if (rx_ring->set_itr) {
1956 u32 itr = rx_ring->itr_val ?
1957 1000000000 / (rx_ring->itr_val * 256) : 0;
1958
1959 writel(itr, rx_ring->itr_register);
1960 rx_ring->set_itr = 0;
1961 }
1962
1963 if (napi_schedule_prep(&adapter->napi)) {
1964 adapter->total_rx_bytes = 0;
1965 adapter->total_rx_packets = 0;
1966 __napi_schedule_irqoff(&adapter->napi);
1967 }
1968 return IRQ_HANDLED;
1969 }
1970
1971 /**
1972 * e1000_configure_msix - Configure MSI-X hardware
1973 * @adapter: board private structure
1974 *
1975 * e1000_configure_msix sets up the hardware to properly
1976 * generate MSI-X interrupts.
1977 **/
e1000_configure_msix(struct e1000_adapter * adapter)1978 static void e1000_configure_msix(struct e1000_adapter *adapter)
1979 {
1980 struct e1000_hw *hw = &adapter->hw;
1981 struct e1000_ring *rx_ring = adapter->rx_ring;
1982 struct e1000_ring *tx_ring = adapter->tx_ring;
1983 int vector = 0;
1984 u32 ctrl_ext, ivar = 0;
1985
1986 adapter->eiac_mask = 0;
1987
1988 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1989 if (hw->mac.type == e1000_82574) {
1990 u32 rfctl = er32(RFCTL);
1991
1992 rfctl |= E1000_RFCTL_ACK_DIS;
1993 ew32(RFCTL, rfctl);
1994 }
1995
1996 /* Configure Rx vector */
1997 rx_ring->ims_val = E1000_IMS_RXQ0;
1998 adapter->eiac_mask |= rx_ring->ims_val;
1999 if (rx_ring->itr_val)
2000 writel(1000000000 / (rx_ring->itr_val * 256),
2001 rx_ring->itr_register);
2002 else
2003 writel(1, rx_ring->itr_register);
2004 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
2005
2006 /* Configure Tx vector */
2007 tx_ring->ims_val = E1000_IMS_TXQ0;
2008 vector++;
2009 if (tx_ring->itr_val)
2010 writel(1000000000 / (tx_ring->itr_val * 256),
2011 tx_ring->itr_register);
2012 else
2013 writel(1, tx_ring->itr_register);
2014 adapter->eiac_mask |= tx_ring->ims_val;
2015 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2016
2017 /* set vector for Other Causes, e.g. link changes */
2018 vector++;
2019 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2020 if (rx_ring->itr_val)
2021 writel(1000000000 / (rx_ring->itr_val * 256),
2022 hw->hw_addr + E1000_EITR_82574(vector));
2023 else
2024 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2025
2026 /* Cause Tx interrupts on every write back */
2027 ivar |= BIT(31);
2028
2029 ew32(IVAR, ivar);
2030
2031 /* enable MSI-X PBA support */
2032 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME;
2033 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME;
2034 ew32(CTRL_EXT, ctrl_ext);
2035 e1e_flush();
2036 }
2037
e1000e_reset_interrupt_capability(struct e1000_adapter * adapter)2038 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2039 {
2040 if (adapter->msix_entries) {
2041 pci_disable_msix(adapter->pdev);
2042 kfree(adapter->msix_entries);
2043 adapter->msix_entries = NULL;
2044 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2045 pci_disable_msi(adapter->pdev);
2046 adapter->flags &= ~FLAG_MSI_ENABLED;
2047 }
2048 }
2049
2050 /**
2051 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2052 * @adapter: board private structure
2053 *
2054 * Attempt to configure interrupts using the best available
2055 * capabilities of the hardware and kernel.
2056 **/
e1000e_set_interrupt_capability(struct e1000_adapter * adapter)2057 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2058 {
2059 int err;
2060 int i;
2061
2062 switch (adapter->int_mode) {
2063 case E1000E_INT_MODE_MSIX:
2064 if (adapter->flags & FLAG_HAS_MSIX) {
2065 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2066 adapter->msix_entries = kzalloc_objs(struct msix_entry,
2067 adapter->num_vectors);
2068 if (adapter->msix_entries) {
2069 struct e1000_adapter *a = adapter;
2070
2071 for (i = 0; i < adapter->num_vectors; i++)
2072 adapter->msix_entries[i].entry = i;
2073
2074 err = pci_enable_msix_range(a->pdev,
2075 a->msix_entries,
2076 a->num_vectors,
2077 a->num_vectors);
2078 if (err > 0)
2079 return;
2080 }
2081 /* MSI-X failed, so fall through and try MSI */
2082 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
2083 e1000e_reset_interrupt_capability(adapter);
2084 }
2085 adapter->int_mode = E1000E_INT_MODE_MSI;
2086 fallthrough;
2087 case E1000E_INT_MODE_MSI:
2088 if (!pci_enable_msi(adapter->pdev)) {
2089 adapter->flags |= FLAG_MSI_ENABLED;
2090 } else {
2091 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2092 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
2093 }
2094 fallthrough;
2095 case E1000E_INT_MODE_LEGACY:
2096 /* Don't do anything; this is the system default */
2097 break;
2098 }
2099
2100 /* store the number of vectors being used */
2101 adapter->num_vectors = 1;
2102 }
2103
2104 /**
2105 * e1000_request_msix - Initialize MSI-X interrupts
2106 * @adapter: board private structure
2107 *
2108 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2109 * kernel.
2110 **/
e1000_request_msix(struct e1000_adapter * adapter)2111 static int e1000_request_msix(struct e1000_adapter *adapter)
2112 {
2113 struct net_device *netdev = adapter->netdev;
2114 int err = 0, vector = 0;
2115
2116 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2117 snprintf(adapter->rx_ring->name,
2118 sizeof(adapter->rx_ring->name) - 1,
2119 "%.14s-rx-0", netdev->name);
2120 else
2121 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2122 err = request_irq(adapter->msix_entries[vector].vector,
2123 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
2124 netdev);
2125 if (err)
2126 return err;
2127 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2128 E1000_EITR_82574(vector);
2129 adapter->rx_ring->itr_val = adapter->itr;
2130 vector++;
2131
2132 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2133 snprintf(adapter->tx_ring->name,
2134 sizeof(adapter->tx_ring->name) - 1,
2135 "%.14s-tx-0", netdev->name);
2136 else
2137 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2138 err = request_irq(adapter->msix_entries[vector].vector,
2139 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
2140 netdev);
2141 if (err)
2142 return err;
2143 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2144 E1000_EITR_82574(vector);
2145 adapter->tx_ring->itr_val = adapter->itr;
2146 vector++;
2147
2148 err = request_irq(adapter->msix_entries[vector].vector,
2149 e1000_msix_other, 0, netdev->name, netdev);
2150 if (err)
2151 return err;
2152
2153 e1000_configure_msix(adapter);
2154
2155 return 0;
2156 }
2157
2158 /**
2159 * e1000_request_irq - initialize interrupts
2160 * @adapter: board private structure
2161 *
2162 * Attempts to configure interrupts using the best available
2163 * capabilities of the hardware and kernel.
2164 **/
e1000_request_irq(struct e1000_adapter * adapter)2165 static int e1000_request_irq(struct e1000_adapter *adapter)
2166 {
2167 struct net_device *netdev = adapter->netdev;
2168 int err;
2169
2170 if (adapter->msix_entries) {
2171 err = e1000_request_msix(adapter);
2172 if (!err)
2173 return err;
2174 /* fall back to MSI */
2175 e1000e_reset_interrupt_capability(adapter);
2176 adapter->int_mode = E1000E_INT_MODE_MSI;
2177 e1000e_set_interrupt_capability(adapter);
2178 }
2179 if (adapter->flags & FLAG_MSI_ENABLED) {
2180 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
2181 netdev->name, netdev);
2182 if (!err)
2183 return err;
2184
2185 /* fall back to legacy interrupt */
2186 e1000e_reset_interrupt_capability(adapter);
2187 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2188 }
2189
2190 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
2191 netdev->name, netdev);
2192 if (err)
2193 e_err("Unable to allocate interrupt, Error: %d\n", err);
2194
2195 return err;
2196 }
2197
e1000_free_irq(struct e1000_adapter * adapter)2198 static void e1000_free_irq(struct e1000_adapter *adapter)
2199 {
2200 struct net_device *netdev = adapter->netdev;
2201
2202 if (adapter->msix_entries) {
2203 int vector = 0;
2204
2205 free_irq(adapter->msix_entries[vector].vector, netdev);
2206 vector++;
2207
2208 free_irq(adapter->msix_entries[vector].vector, netdev);
2209 vector++;
2210
2211 /* Other Causes interrupt vector */
2212 free_irq(adapter->msix_entries[vector].vector, netdev);
2213 return;
2214 }
2215
2216 free_irq(adapter->pdev->irq, netdev);
2217 }
2218
2219 /**
2220 * e1000_irq_disable - Mask off interrupt generation on the NIC
2221 * @adapter: board private structure
2222 **/
e1000_irq_disable(struct e1000_adapter * adapter)2223 static void e1000_irq_disable(struct e1000_adapter *adapter)
2224 {
2225 struct e1000_hw *hw = &adapter->hw;
2226
2227 ew32(IMC, ~0);
2228 if (adapter->msix_entries)
2229 ew32(EIAC_82574, 0);
2230 e1e_flush();
2231
2232 if (adapter->msix_entries) {
2233 int i;
2234
2235 for (i = 0; i < adapter->num_vectors; i++)
2236 synchronize_irq(adapter->msix_entries[i].vector);
2237 } else {
2238 synchronize_irq(adapter->pdev->irq);
2239 }
2240 }
2241
2242 /**
2243 * e1000_irq_enable - Enable default interrupt generation settings
2244 * @adapter: board private structure
2245 **/
e1000_irq_enable(struct e1000_adapter * adapter)2246 static void e1000_irq_enable(struct e1000_adapter *adapter)
2247 {
2248 struct e1000_hw *hw = &adapter->hw;
2249
2250 if (adapter->msix_entries) {
2251 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2252 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
2253 IMS_OTHER_MASK);
2254 } else if (hw->mac.type >= e1000_pch_lpt) {
2255 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2256 } else {
2257 ew32(IMS, IMS_ENABLE_MASK);
2258 }
2259 e1e_flush();
2260 }
2261
2262 /**
2263 * e1000e_get_hw_control - get control of the h/w from f/w
2264 * @adapter: address of board private structure
2265 *
2266 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2267 * For ASF and Pass Through versions of f/w this means that
2268 * the driver is loaded. For AMT version (only with 82573)
2269 * of the f/w this means that the network i/f is open.
2270 **/
e1000e_get_hw_control(struct e1000_adapter * adapter)2271 void e1000e_get_hw_control(struct e1000_adapter *adapter)
2272 {
2273 struct e1000_hw *hw = &adapter->hw;
2274 u32 ctrl_ext;
2275 u32 swsm;
2276
2277 /* Let firmware know the driver has taken over */
2278 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2279 swsm = er32(SWSM);
2280 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2281 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2282 ctrl_ext = er32(CTRL_EXT);
2283 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2284 }
2285 }
2286
2287 /**
2288 * e1000e_release_hw_control - release control of the h/w to f/w
2289 * @adapter: address of board private structure
2290 *
2291 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2292 * For ASF and Pass Through versions of f/w this means that the
2293 * driver is no longer loaded. For AMT version (only with 82573) i
2294 * of the f/w this means that the network i/f is closed.
2295 *
2296 **/
e1000e_release_hw_control(struct e1000_adapter * adapter)2297 void e1000e_release_hw_control(struct e1000_adapter *adapter)
2298 {
2299 struct e1000_hw *hw = &adapter->hw;
2300 u32 ctrl_ext;
2301 u32 swsm;
2302
2303 /* Let firmware taken over control of h/w */
2304 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2305 swsm = er32(SWSM);
2306 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2307 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2308 ctrl_ext = er32(CTRL_EXT);
2309 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2310 }
2311 }
2312
2313 /**
2314 * e1000_alloc_ring_dma - allocate memory for a ring structure
2315 * @adapter: board private structure
2316 * @ring: ring struct for which to allocate dma
2317 **/
e1000_alloc_ring_dma(struct e1000_adapter * adapter,struct e1000_ring * ring)2318 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2319 struct e1000_ring *ring)
2320 {
2321 struct pci_dev *pdev = adapter->pdev;
2322
2323 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2324 GFP_KERNEL);
2325 if (!ring->desc)
2326 return -ENOMEM;
2327
2328 return 0;
2329 }
2330
2331 /**
2332 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2333 * @tx_ring: Tx descriptor ring
2334 *
2335 * Return 0 on success, negative on failure
2336 **/
e1000e_setup_tx_resources(struct e1000_ring * tx_ring)2337 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2338 {
2339 struct e1000_adapter *adapter = tx_ring->adapter;
2340 int err = -ENOMEM, size;
2341
2342 size = sizeof(struct e1000_buffer) * tx_ring->count;
2343 tx_ring->buffer_info = vzalloc(size);
2344 if (!tx_ring->buffer_info)
2345 goto err;
2346
2347 /* round up to nearest 4K */
2348 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2349 tx_ring->size = ALIGN(tx_ring->size, 4096);
2350
2351 err = e1000_alloc_ring_dma(adapter, tx_ring);
2352 if (err)
2353 goto err;
2354
2355 tx_ring->next_to_use = 0;
2356 tx_ring->next_to_clean = 0;
2357
2358 return 0;
2359 err:
2360 vfree(tx_ring->buffer_info);
2361 e_err("Unable to allocate memory for the transmit descriptor ring\n");
2362 return err;
2363 }
2364
2365 /**
2366 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2367 * @rx_ring: Rx descriptor ring
2368 *
2369 * Returns 0 on success, negative on failure
2370 **/
e1000e_setup_rx_resources(struct e1000_ring * rx_ring)2371 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2372 {
2373 struct e1000_adapter *adapter = rx_ring->adapter;
2374 struct e1000_buffer *buffer_info;
2375 int i, size, desc_len, err = -ENOMEM;
2376
2377 size = sizeof(struct e1000_buffer) * rx_ring->count;
2378 rx_ring->buffer_info = vzalloc(size);
2379 if (!rx_ring->buffer_info)
2380 goto err;
2381
2382 for (i = 0; i < rx_ring->count; i++) {
2383 buffer_info = &rx_ring->buffer_info[i];
2384 buffer_info->ps_pages = kzalloc_objs(struct e1000_ps_page,
2385 PS_PAGE_BUFFERS);
2386 if (!buffer_info->ps_pages)
2387 goto err_pages;
2388 }
2389
2390 desc_len = sizeof(union e1000_rx_desc_packet_split);
2391
2392 /* Round up to nearest 4K */
2393 rx_ring->size = rx_ring->count * desc_len;
2394 rx_ring->size = ALIGN(rx_ring->size, 4096);
2395
2396 err = e1000_alloc_ring_dma(adapter, rx_ring);
2397 if (err)
2398 goto err_pages;
2399
2400 rx_ring->next_to_clean = 0;
2401 rx_ring->next_to_use = 0;
2402 rx_ring->rx_skb_top = NULL;
2403
2404 return 0;
2405
2406 err_pages:
2407 for (i = 0; i < rx_ring->count; i++) {
2408 buffer_info = &rx_ring->buffer_info[i];
2409 kfree(buffer_info->ps_pages);
2410 }
2411 err:
2412 vfree(rx_ring->buffer_info);
2413 e_err("Unable to allocate memory for the receive descriptor ring\n");
2414 return err;
2415 }
2416
2417 /**
2418 * e1000_clean_tx_ring - Free Tx Buffers
2419 * @tx_ring: Tx descriptor ring
2420 **/
e1000_clean_tx_ring(struct e1000_ring * tx_ring)2421 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2422 {
2423 struct e1000_adapter *adapter = tx_ring->adapter;
2424 struct e1000_buffer *buffer_info;
2425 unsigned long size;
2426 unsigned int i;
2427
2428 for (i = 0; i < tx_ring->count; i++) {
2429 buffer_info = &tx_ring->buffer_info[i];
2430 e1000_put_txbuf(tx_ring, buffer_info, false);
2431 }
2432
2433 netdev_reset_queue(adapter->netdev);
2434 size = sizeof(struct e1000_buffer) * tx_ring->count;
2435 memset(tx_ring->buffer_info, 0, size);
2436
2437 memset(tx_ring->desc, 0, tx_ring->size);
2438
2439 tx_ring->next_to_use = 0;
2440 tx_ring->next_to_clean = 0;
2441 }
2442
2443 /**
2444 * e1000e_free_tx_resources - Free Tx Resources per Queue
2445 * @tx_ring: Tx descriptor ring
2446 *
2447 * Free all transmit software resources
2448 **/
e1000e_free_tx_resources(struct e1000_ring * tx_ring)2449 void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2450 {
2451 struct e1000_adapter *adapter = tx_ring->adapter;
2452 struct pci_dev *pdev = adapter->pdev;
2453
2454 e1000_clean_tx_ring(tx_ring);
2455
2456 vfree(tx_ring->buffer_info);
2457 tx_ring->buffer_info = NULL;
2458
2459 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2460 tx_ring->dma);
2461 tx_ring->desc = NULL;
2462 }
2463
2464 /**
2465 * e1000e_free_rx_resources - Free Rx Resources
2466 * @rx_ring: Rx descriptor ring
2467 *
2468 * Free all receive software resources
2469 **/
e1000e_free_rx_resources(struct e1000_ring * rx_ring)2470 void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2471 {
2472 struct e1000_adapter *adapter = rx_ring->adapter;
2473 struct pci_dev *pdev = adapter->pdev;
2474 int i;
2475
2476 e1000_clean_rx_ring(rx_ring);
2477
2478 for (i = 0; i < rx_ring->count; i++)
2479 kfree(rx_ring->buffer_info[i].ps_pages);
2480
2481 vfree(rx_ring->buffer_info);
2482 rx_ring->buffer_info = NULL;
2483
2484 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2485 rx_ring->dma);
2486 rx_ring->desc = NULL;
2487 }
2488
2489 /**
2490 * e1000_update_itr - update the dynamic ITR value based on statistics
2491 * @itr_setting: current adapter->itr
2492 * @packets: the number of packets during this measurement interval
2493 * @bytes: the number of bytes during this measurement interval
2494 *
2495 * Stores a new ITR value based on packets and byte
2496 * counts during the last interrupt. The advantage of per interrupt
2497 * computation is faster updates and more accurate ITR for the current
2498 * traffic pattern. Constants in this function were computed
2499 * based on theoretical maximum wire speed and thresholds were set based
2500 * on testing data as well as attempting to minimize response time
2501 * while increasing bulk throughput. This functionality is controlled
2502 * by the InterruptThrottleRate module parameter.
2503 **/
e1000_update_itr(u16 itr_setting,int packets,int bytes)2504 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2505 {
2506 unsigned int retval = itr_setting;
2507
2508 if (packets == 0)
2509 return itr_setting;
2510
2511 switch (itr_setting) {
2512 case lowest_latency:
2513 /* handle TSO and jumbo frames */
2514 if (bytes / packets > 8000)
2515 retval = bulk_latency;
2516 else if ((packets < 5) && (bytes > 512))
2517 retval = low_latency;
2518 break;
2519 case low_latency: /* 50 usec aka 20000 ints/s */
2520 if (bytes > 10000) {
2521 /* this if handles the TSO accounting */
2522 if (bytes / packets > 8000)
2523 retval = bulk_latency;
2524 else if ((packets < 10) || ((bytes / packets) > 1200))
2525 retval = bulk_latency;
2526 else if ((packets > 35))
2527 retval = lowest_latency;
2528 } else if (bytes / packets > 2000) {
2529 retval = bulk_latency;
2530 } else if (packets <= 2 && bytes < 512) {
2531 retval = lowest_latency;
2532 }
2533 break;
2534 case bulk_latency: /* 250 usec aka 4000 ints/s */
2535 if (bytes > 25000) {
2536 if (packets > 35)
2537 retval = low_latency;
2538 } else if (bytes < 6000) {
2539 retval = low_latency;
2540 }
2541 break;
2542 }
2543
2544 return retval;
2545 }
2546
e1000_set_itr(struct e1000_adapter * adapter)2547 static void e1000_set_itr(struct e1000_adapter *adapter)
2548 {
2549 u16 current_itr;
2550 u32 new_itr = adapter->itr;
2551
2552 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2553 if (adapter->link_speed != SPEED_1000) {
2554 new_itr = 4000;
2555 goto set_itr_now;
2556 }
2557
2558 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2559 new_itr = 0;
2560 goto set_itr_now;
2561 }
2562
2563 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2564 adapter->total_tx_packets,
2565 adapter->total_tx_bytes);
2566 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2567 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2568 adapter->tx_itr = low_latency;
2569
2570 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2571 adapter->total_rx_packets,
2572 adapter->total_rx_bytes);
2573 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2574 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2575 adapter->rx_itr = low_latency;
2576
2577 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2578
2579 /* counts and packets in update_itr are dependent on these numbers */
2580 switch (current_itr) {
2581 case lowest_latency:
2582 new_itr = 70000;
2583 break;
2584 case low_latency:
2585 new_itr = 20000; /* aka hwitr = ~200 */
2586 break;
2587 case bulk_latency:
2588 new_itr = 4000;
2589 break;
2590 default:
2591 break;
2592 }
2593
2594 set_itr_now:
2595 if (new_itr != adapter->itr) {
2596 /* this attempts to bias the interrupt rate towards Bulk
2597 * by adding intermediate steps when interrupt rate is
2598 * increasing
2599 */
2600 new_itr = new_itr > adapter->itr ?
2601 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
2602 adapter->itr = new_itr;
2603 adapter->rx_ring->itr_val = new_itr;
2604 if (adapter->msix_entries)
2605 adapter->rx_ring->set_itr = 1;
2606 else
2607 e1000e_write_itr(adapter, new_itr);
2608 }
2609 }
2610
2611 /**
2612 * e1000e_write_itr - write the ITR value to the appropriate registers
2613 * @adapter: address of board private structure
2614 * @itr: new ITR value to program
2615 *
2616 * e1000e_write_itr determines if the adapter is in MSI-X mode
2617 * and, if so, writes the EITR registers with the ITR value.
2618 * Otherwise, it writes the ITR value into the ITR register.
2619 **/
e1000e_write_itr(struct e1000_adapter * adapter,u32 itr)2620 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2621 {
2622 struct e1000_hw *hw = &adapter->hw;
2623 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2624
2625 if (adapter->msix_entries) {
2626 int vector;
2627
2628 for (vector = 0; vector < adapter->num_vectors; vector++)
2629 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2630 } else {
2631 ew32(ITR, new_itr);
2632 }
2633 }
2634
2635 /**
2636 * e1000_alloc_queues - Allocate memory for all rings
2637 * @adapter: board private structure to initialize
2638 **/
e1000_alloc_queues(struct e1000_adapter * adapter)2639 static int e1000_alloc_queues(struct e1000_adapter *adapter)
2640 {
2641 int size = sizeof(struct e1000_ring);
2642
2643 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2644 if (!adapter->tx_ring)
2645 goto err;
2646 adapter->tx_ring->count = adapter->tx_ring_count;
2647 adapter->tx_ring->adapter = adapter;
2648
2649 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2650 if (!adapter->rx_ring)
2651 goto err;
2652 adapter->rx_ring->count = adapter->rx_ring_count;
2653 adapter->rx_ring->adapter = adapter;
2654
2655 return 0;
2656 err:
2657 e_err("Unable to allocate memory for queues\n");
2658 kfree(adapter->rx_ring);
2659 kfree(adapter->tx_ring);
2660 return -ENOMEM;
2661 }
2662
2663 /**
2664 * e1000e_poll - NAPI Rx polling callback
2665 * @napi: struct associated with this polling callback
2666 * @budget: number of packets driver is allowed to process this poll
2667 **/
e1000e_poll(struct napi_struct * napi,int budget)2668 static int e1000e_poll(struct napi_struct *napi, int budget)
2669 {
2670 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2671 napi);
2672 struct e1000_hw *hw = &adapter->hw;
2673 struct net_device *poll_dev = adapter->netdev;
2674 int tx_cleaned = 1, work_done = 0;
2675
2676 adapter = netdev_priv(poll_dev);
2677
2678 if (!adapter->msix_entries ||
2679 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2680 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
2681
2682 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
2683
2684 if (!tx_cleaned || work_done == budget)
2685 return budget;
2686
2687 /* Exit the polling mode, but don't re-enable interrupts if stack might
2688 * poll us due to busy-polling
2689 */
2690 if (likely(napi_complete_done(napi, work_done))) {
2691 if (adapter->itr_setting & 3)
2692 e1000_set_itr(adapter);
2693 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2694 if (adapter->msix_entries)
2695 ew32(IMS, adapter->rx_ring->ims_val);
2696 else
2697 e1000_irq_enable(adapter);
2698 }
2699 }
2700
2701 return work_done;
2702 }
2703
e1000_vlan_rx_add_vid(struct net_device * netdev,__always_unused __be16 proto,u16 vid)2704 static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2705 __always_unused __be16 proto, u16 vid)
2706 {
2707 struct e1000_adapter *adapter = netdev_priv(netdev);
2708 struct e1000_hw *hw = &adapter->hw;
2709 u32 vfta, index;
2710
2711 /* don't update vlan cookie if already programmed */
2712 if ((adapter->hw.mng_cookie.status &
2713 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2714 (vid == adapter->mng_vlan_id))
2715 return 0;
2716
2717 /* add VID to filter table */
2718 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2719 index = (vid >> 5) & 0x7F;
2720 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2721 vfta |= BIT((vid & 0x1F));
2722 hw->mac.ops.write_vfta(hw, index, vfta);
2723 }
2724
2725 set_bit(vid, adapter->active_vlans);
2726
2727 return 0;
2728 }
2729
e1000_vlan_rx_kill_vid(struct net_device * netdev,__always_unused __be16 proto,u16 vid)2730 static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2731 __always_unused __be16 proto, u16 vid)
2732 {
2733 struct e1000_adapter *adapter = netdev_priv(netdev);
2734 struct e1000_hw *hw = &adapter->hw;
2735 u32 vfta, index;
2736
2737 if ((adapter->hw.mng_cookie.status &
2738 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2739 (vid == adapter->mng_vlan_id)) {
2740 /* release control to f/w */
2741 e1000e_release_hw_control(adapter);
2742 return 0;
2743 }
2744
2745 /* remove VID from filter table */
2746 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2747 index = (vid >> 5) & 0x7F;
2748 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2749 vfta &= ~BIT((vid & 0x1F));
2750 hw->mac.ops.write_vfta(hw, index, vfta);
2751 }
2752
2753 clear_bit(vid, adapter->active_vlans);
2754
2755 return 0;
2756 }
2757
2758 /**
2759 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2760 * @adapter: board private structure to initialize
2761 **/
e1000e_vlan_filter_disable(struct e1000_adapter * adapter)2762 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2763 {
2764 struct net_device *netdev = adapter->netdev;
2765 struct e1000_hw *hw = &adapter->hw;
2766 u32 rctl;
2767
2768 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2769 /* disable VLAN receive filtering */
2770 rctl = er32(RCTL);
2771 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2772 ew32(RCTL, rctl);
2773
2774 if (adapter->mng_vlan_id != E1000_MNG_VLAN_NONE) {
2775 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2776 adapter->mng_vlan_id);
2777 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2778 }
2779 }
2780 }
2781
2782 /**
2783 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2784 * @adapter: board private structure to initialize
2785 **/
e1000e_vlan_filter_enable(struct e1000_adapter * adapter)2786 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2787 {
2788 struct e1000_hw *hw = &adapter->hw;
2789 u32 rctl;
2790
2791 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2792 /* enable VLAN receive filtering */
2793 rctl = er32(RCTL);
2794 rctl |= E1000_RCTL_VFE;
2795 rctl &= ~E1000_RCTL_CFIEN;
2796 ew32(RCTL, rctl);
2797 }
2798 }
2799
2800 /**
2801 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2802 * @adapter: board private structure to initialize
2803 **/
e1000e_vlan_strip_disable(struct e1000_adapter * adapter)2804 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2805 {
2806 struct e1000_hw *hw = &adapter->hw;
2807 u32 ctrl;
2808
2809 /* disable VLAN tag insert/strip */
2810 ctrl = er32(CTRL);
2811 ctrl &= ~E1000_CTRL_VME;
2812 ew32(CTRL, ctrl);
2813 }
2814
2815 /**
2816 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2817 * @adapter: board private structure to initialize
2818 **/
e1000e_vlan_strip_enable(struct e1000_adapter * adapter)2819 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2820 {
2821 struct e1000_hw *hw = &adapter->hw;
2822 u32 ctrl;
2823
2824 /* enable VLAN tag insert/strip */
2825 ctrl = er32(CTRL);
2826 ctrl |= E1000_CTRL_VME;
2827 ew32(CTRL, ctrl);
2828 }
2829
e1000_update_mng_vlan(struct e1000_adapter * adapter)2830 static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2831 {
2832 struct net_device *netdev = adapter->netdev;
2833 u16 vid = adapter->hw.mng_cookie.vlan_id;
2834 u16 old_vid = adapter->mng_vlan_id;
2835
2836 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2837 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
2838 adapter->mng_vlan_id = vid;
2839 }
2840
2841 if (old_vid != E1000_MNG_VLAN_NONE && vid != old_vid)
2842 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
2843 }
2844
e1000_restore_vlan(struct e1000_adapter * adapter)2845 static void e1000_restore_vlan(struct e1000_adapter *adapter)
2846 {
2847 u16 vid;
2848
2849 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
2850
2851 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2852 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
2853 }
2854
e1000_init_manageability_pt(struct e1000_adapter * adapter)2855 static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2856 {
2857 struct e1000_hw *hw = &adapter->hw;
2858 u32 manc, manc2h, mdef, i, j;
2859
2860 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2861 return;
2862
2863 manc = er32(MANC);
2864
2865 /* enable receiving management packets to the host. this will probably
2866 * generate destination unreachable messages from the host OS, but
2867 * the packets will be handled on SMBUS
2868 */
2869 manc |= E1000_MANC_EN_MNG2HOST;
2870 manc2h = er32(MANC2H);
2871
2872 switch (hw->mac.type) {
2873 default:
2874 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2875 break;
2876 case e1000_82574:
2877 case e1000_82583:
2878 /* Check if IPMI pass-through decision filter already exists;
2879 * if so, enable it.
2880 */
2881 for (i = 0, j = 0; i < 8; i++) {
2882 mdef = er32(MDEF(i));
2883
2884 /* Ignore filters with anything other than IPMI ports */
2885 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2886 continue;
2887
2888 /* Enable this decision filter in MANC2H */
2889 if (mdef)
2890 manc2h |= BIT(i);
2891
2892 j |= mdef;
2893 }
2894
2895 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2896 break;
2897
2898 /* Create new decision filter in an empty filter */
2899 for (i = 0, j = 0; i < 8; i++)
2900 if (er32(MDEF(i)) == 0) {
2901 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2902 E1000_MDEF_PORT_664));
2903 manc2h |= BIT(1);
2904 j++;
2905 break;
2906 }
2907
2908 if (!j)
2909 e_warn("Unable to create IPMI pass-through filter\n");
2910 break;
2911 }
2912
2913 ew32(MANC2H, manc2h);
2914 ew32(MANC, manc);
2915 }
2916
2917 /**
2918 * e1000_configure_tx - Configure Transmit Unit after Reset
2919 * @adapter: board private structure
2920 *
2921 * Configure the Tx unit of the MAC after a reset.
2922 **/
e1000_configure_tx(struct e1000_adapter * adapter)2923 static void e1000_configure_tx(struct e1000_adapter *adapter)
2924 {
2925 struct e1000_hw *hw = &adapter->hw;
2926 struct e1000_ring *tx_ring = adapter->tx_ring;
2927 u64 tdba;
2928 u32 tdlen, tctl, tarc;
2929
2930 /* Setup the HW Tx Head and Tail descriptor pointers */
2931 tdba = tx_ring->dma;
2932 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2933 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2934 ew32(TDBAH(0), (tdba >> 32));
2935 ew32(TDLEN(0), tdlen);
2936 ew32(TDH(0), 0);
2937 ew32(TDT(0), 0);
2938 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2939 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2940
2941 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2942 e1000e_update_tdt_wa(tx_ring, 0);
2943
2944 /* Set the Tx Interrupt Delay register */
2945 ew32(TIDV, adapter->tx_int_delay);
2946 /* Tx irq moderation */
2947 ew32(TADV, adapter->tx_abs_int_delay);
2948
2949 if (adapter->flags2 & FLAG2_DMA_BURST) {
2950 u32 txdctl = er32(TXDCTL(0));
2951
2952 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2953 E1000_TXDCTL_WTHRESH);
2954 /* set up some performance related parameters to encourage the
2955 * hardware to use the bus more efficiently in bursts, depends
2956 * on the tx_int_delay to be enabled,
2957 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2958 * hthresh = 1 ==> prefetch when one or more available
2959 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2960 * BEWARE: this seems to work but should be considered first if
2961 * there are Tx hangs or other Tx related bugs
2962 */
2963 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2964 ew32(TXDCTL(0), txdctl);
2965 }
2966 /* erratum work around: set txdctl the same for both queues */
2967 ew32(TXDCTL(1), er32(TXDCTL(0)));
2968
2969 /* Program the Transmit Control Register */
2970 tctl = er32(TCTL);
2971 tctl &= ~E1000_TCTL_CT;
2972 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2973 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2974
2975 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2976 tarc = er32(TARC(0));
2977 /* set the speed mode bit, we'll clear it if we're not at
2978 * gigabit link later
2979 */
2980 #define SPEED_MODE_BIT BIT(21)
2981 tarc |= SPEED_MODE_BIT;
2982 ew32(TARC(0), tarc);
2983 }
2984
2985 /* errata: program both queues to unweighted RR */
2986 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
2987 tarc = er32(TARC(0));
2988 tarc |= 1;
2989 ew32(TARC(0), tarc);
2990 tarc = er32(TARC(1));
2991 tarc |= 1;
2992 ew32(TARC(1), tarc);
2993 }
2994
2995 /* Setup Transmit Descriptor Settings for eop descriptor */
2996 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2997
2998 /* only set IDE if we are delaying interrupts using the timers */
2999 if (adapter->tx_int_delay)
3000 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3001
3002 /* enable Report Status bit */
3003 adapter->txd_cmd |= E1000_TXD_CMD_RS;
3004
3005 ew32(TCTL, tctl);
3006
3007 hw->mac.ops.config_collision_dist(hw);
3008
3009 /* SPT and KBL Si errata workaround to avoid data corruption */
3010 if (hw->mac.type == e1000_pch_spt) {
3011 u32 reg_val;
3012
3013 reg_val = er32(IOSFPC);
3014 reg_val |= E1000_RCTL_RDMTS_HEX;
3015 ew32(IOSFPC, reg_val);
3016
3017 reg_val = er32(TARC(0));
3018 /* SPT and KBL Si errata workaround to avoid Tx hang.
3019 * Dropping the number of outstanding requests from
3020 * 3 to 2 in order to avoid a buffer overrun.
3021 */
3022 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3023 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
3024 ew32(TARC(0), reg_val);
3025 }
3026 }
3027
3028 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3029 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3030
3031 /**
3032 * e1000_setup_rctl - configure the receive control registers
3033 * @adapter: Board private structure
3034 **/
e1000_setup_rctl(struct e1000_adapter * adapter)3035 static void e1000_setup_rctl(struct e1000_adapter *adapter)
3036 {
3037 struct e1000_hw *hw = &adapter->hw;
3038 u32 rctl, rfctl;
3039 u32 pages = 0;
3040
3041 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3042 * If jumbo frames not set, program related MAC/PHY registers
3043 * to h/w defaults
3044 */
3045 if (hw->mac.type >= e1000_pch2lan) {
3046 s32 ret_val;
3047
3048 if (adapter->netdev->mtu > ETH_DATA_LEN)
3049 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3050 else
3051 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3052
3053 if (ret_val)
3054 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3055 }
3056
3057 /* Program MC offset vector base */
3058 rctl = er32(RCTL);
3059 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3060 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3061 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3062 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3063
3064 /* Do not Store bad packets */
3065 rctl &= ~E1000_RCTL_SBP;
3066
3067 /* Enable Long Packet receive */
3068 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3069 rctl &= ~E1000_RCTL_LPE;
3070 else
3071 rctl |= E1000_RCTL_LPE;
3072
3073 /* Some systems expect that the CRC is included in SMBUS traffic. The
3074 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3075 * host memory when this is enabled
3076 */
3077 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3078 rctl |= E1000_RCTL_SECRC;
3079
3080 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3081 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3082 u16 phy_data;
3083
3084 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3085 phy_data &= 0xfff8;
3086 phy_data |= BIT(2);
3087 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3088
3089 e1e_rphy(hw, 22, &phy_data);
3090 phy_data &= 0x0fff;
3091 phy_data |= BIT(14);
3092 e1e_wphy(hw, 0x10, 0x2823);
3093 e1e_wphy(hw, 0x11, 0x0003);
3094 e1e_wphy(hw, 22, phy_data);
3095 }
3096
3097 /* Setup buffer sizes */
3098 rctl &= ~E1000_RCTL_SZ_4096;
3099 rctl |= E1000_RCTL_BSEX;
3100 switch (adapter->rx_buffer_len) {
3101 case 2048:
3102 default:
3103 rctl |= E1000_RCTL_SZ_2048;
3104 rctl &= ~E1000_RCTL_BSEX;
3105 break;
3106 case 4096:
3107 rctl |= E1000_RCTL_SZ_4096;
3108 break;
3109 case 8192:
3110 rctl |= E1000_RCTL_SZ_8192;
3111 break;
3112 case 16384:
3113 rctl |= E1000_RCTL_SZ_16384;
3114 break;
3115 }
3116
3117 /* Enable Extended Status in all Receive Descriptors */
3118 rfctl = er32(RFCTL);
3119 rfctl |= E1000_RFCTL_EXTEN;
3120 ew32(RFCTL, rfctl);
3121
3122 /* 82571 and greater support packet-split where the protocol
3123 * header is placed in skb->data and the packet data is
3124 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3125 * In the case of a non-split, skb->data is linearly filled,
3126 * followed by the page buffers. Therefore, skb->data is
3127 * sized to hold the largest protocol header.
3128 *
3129 * allocations using alloc_page take too long for regular MTU
3130 * so only enable packet split for jumbo frames
3131 *
3132 * Using pages when the page size is greater than 16k wastes
3133 * a lot of memory, since we allocate 3 pages at all times
3134 * per packet.
3135 */
3136 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3137 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3138 adapter->rx_ps_pages = pages;
3139 else
3140 adapter->rx_ps_pages = 0;
3141
3142 if (adapter->rx_ps_pages) {
3143 u32 psrctl = 0;
3144
3145 /* Enable Packet split descriptors */
3146 rctl |= E1000_RCTL_DTYP_PS;
3147
3148 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
3149
3150 switch (adapter->rx_ps_pages) {
3151 case 3:
3152 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3153 fallthrough;
3154 case 2:
3155 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3156 fallthrough;
3157 case 1:
3158 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
3159 break;
3160 }
3161
3162 ew32(PSRCTL, psrctl);
3163 }
3164
3165 /* This is useful for sniffing bad packets. */
3166 if (adapter->netdev->features & NETIF_F_RXALL) {
3167 /* UPE and MPE will be handled by normal PROMISC logic
3168 * in e1000e_set_rx_mode
3169 */
3170 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3171 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3172 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3173
3174 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3175 E1000_RCTL_DPF | /* Allow filtered pause */
3176 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3177 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3178 * and that breaks VLANs.
3179 */
3180 }
3181
3182 ew32(RCTL, rctl);
3183 /* just started the receive unit, no need to restart */
3184 adapter->flags &= ~FLAG_RESTART_NOW;
3185 }
3186
3187 /**
3188 * e1000_configure_rx - Configure Receive Unit after Reset
3189 * @adapter: board private structure
3190 *
3191 * Configure the Rx unit of the MAC after a reset.
3192 **/
e1000_configure_rx(struct e1000_adapter * adapter)3193 static void e1000_configure_rx(struct e1000_adapter *adapter)
3194 {
3195 struct e1000_hw *hw = &adapter->hw;
3196 struct e1000_ring *rx_ring = adapter->rx_ring;
3197 u64 rdba;
3198 u32 rdlen, rctl, rxcsum, ctrl_ext;
3199
3200 if (adapter->rx_ps_pages) {
3201 /* this is a 32 byte descriptor */
3202 rdlen = rx_ring->count *
3203 sizeof(union e1000_rx_desc_packet_split);
3204 adapter->clean_rx = e1000_clean_rx_irq_ps;
3205 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3206 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3207 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3208 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3209 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3210 } else {
3211 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3212 adapter->clean_rx = e1000_clean_rx_irq;
3213 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3214 }
3215
3216 /* disable receives while setting up the descriptors */
3217 rctl = er32(RCTL);
3218 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3219 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3220 e1e_flush();
3221 usleep_range(10000, 11000);
3222
3223 if (adapter->flags2 & FLAG2_DMA_BURST) {
3224 /* set the writeback threshold (only takes effect if the RDTR
3225 * is set). set GRAN=1 and write back up to 0x4 worth, and
3226 * enable prefetching of 0x20 Rx descriptors
3227 * granularity = 01
3228 * wthresh = 04,
3229 * hthresh = 04,
3230 * pthresh = 0x20
3231 */
3232 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3233 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3234 }
3235
3236 /* set the Receive Delay Timer Register */
3237 ew32(RDTR, adapter->rx_int_delay);
3238
3239 /* irq moderation */
3240 ew32(RADV, adapter->rx_abs_int_delay);
3241 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3242 e1000e_write_itr(adapter, adapter->itr);
3243
3244 ctrl_ext = er32(CTRL_EXT);
3245 /* Auto-Mask interrupts upon ICR access */
3246 ctrl_ext |= E1000_CTRL_EXT_IAME;
3247 ew32(IAM, 0xffffffff);
3248 ew32(CTRL_EXT, ctrl_ext);
3249 e1e_flush();
3250
3251 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3252 * the Base and Length of the Rx Descriptor Ring
3253 */
3254 rdba = rx_ring->dma;
3255 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3256 ew32(RDBAH(0), (rdba >> 32));
3257 ew32(RDLEN(0), rdlen);
3258 ew32(RDH(0), 0);
3259 ew32(RDT(0), 0);
3260 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3261 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3262
3263 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3264 e1000e_update_rdt_wa(rx_ring, 0);
3265
3266 /* Enable Receive Checksum Offload for TCP and UDP */
3267 rxcsum = er32(RXCSUM);
3268 if (adapter->netdev->features & NETIF_F_RXCSUM)
3269 rxcsum |= E1000_RXCSUM_TUOFL;
3270 else
3271 rxcsum &= ~E1000_RXCSUM_TUOFL;
3272 ew32(RXCSUM, rxcsum);
3273
3274 /* With jumbo frames, excessive C-state transition latencies result
3275 * in dropped transactions.
3276 */
3277 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3278 u32 lat =
3279 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3280 adapter->max_frame_size) * 8 / 1000;
3281
3282 if (adapter->flags & FLAG_IS_ICH) {
3283 u32 rxdctl = er32(RXDCTL(0));
3284
3285 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8));
3286 }
3287
3288 dev_info(&adapter->pdev->dev,
3289 "Some CPU C-states have been disabled in order to enable jumbo frames\n");
3290 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat);
3291 } else {
3292 cpu_latency_qos_update_request(&adapter->pm_qos_req,
3293 PM_QOS_DEFAULT_VALUE);
3294 }
3295
3296 /* Enable Receives */
3297 ew32(RCTL, rctl);
3298 }
3299
3300 /**
3301 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3302 * @netdev: network interface device structure
3303 *
3304 * Writes multicast address list to the MTA hash table.
3305 * Returns: -ENOMEM on failure
3306 * 0 on no addresses written
3307 * X on writing X addresses to MTA
3308 */
e1000e_write_mc_addr_list(struct net_device * netdev)3309 static int e1000e_write_mc_addr_list(struct net_device *netdev)
3310 {
3311 struct e1000_adapter *adapter = netdev_priv(netdev);
3312 struct e1000_hw *hw = &adapter->hw;
3313 struct netdev_hw_addr *ha;
3314 u8 *mta_list;
3315 int i;
3316
3317 if (netdev_mc_empty(netdev)) {
3318 /* nothing to program, so clear mc list */
3319 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3320 return 0;
3321 }
3322
3323 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC);
3324 if (!mta_list)
3325 return -ENOMEM;
3326
3327 /* update_mc_addr_list expects a packed array of only addresses. */
3328 i = 0;
3329 netdev_for_each_mc_addr(ha, netdev)
3330 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3331
3332 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3333 kfree(mta_list);
3334
3335 return netdev_mc_count(netdev);
3336 }
3337
3338 /**
3339 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3340 * @netdev: network interface device structure
3341 *
3342 * Writes unicast address list to the RAR table.
3343 * Returns: -ENOMEM on failure/insufficient address space
3344 * 0 on no addresses written
3345 * X on writing X addresses to the RAR table
3346 **/
e1000e_write_uc_addr_list(struct net_device * netdev)3347 static int e1000e_write_uc_addr_list(struct net_device *netdev)
3348 {
3349 struct e1000_adapter *adapter = netdev_priv(netdev);
3350 struct e1000_hw *hw = &adapter->hw;
3351 unsigned int rar_entries;
3352 int count = 0;
3353
3354 rar_entries = hw->mac.ops.rar_get_count(hw);
3355
3356 /* save a rar entry for our hardware address */
3357 rar_entries--;
3358
3359 /* save a rar entry for the LAA workaround */
3360 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3361 rar_entries--;
3362
3363 /* return ENOMEM indicating insufficient memory for addresses */
3364 if (netdev_uc_count(netdev) > rar_entries)
3365 return -ENOMEM;
3366
3367 if (!netdev_uc_empty(netdev) && rar_entries) {
3368 struct netdev_hw_addr *ha;
3369
3370 /* write the addresses in reverse order to avoid write
3371 * combining
3372 */
3373 netdev_for_each_uc_addr(ha, netdev) {
3374 int ret_val;
3375
3376 if (!rar_entries)
3377 break;
3378 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3379 if (ret_val < 0)
3380 return -ENOMEM;
3381 count++;
3382 }
3383 }
3384
3385 /* zero out the remaining RAR entries not used above */
3386 for (; rar_entries > 0; rar_entries--) {
3387 ew32(RAH(rar_entries), 0);
3388 ew32(RAL(rar_entries), 0);
3389 }
3390 e1e_flush();
3391
3392 return count;
3393 }
3394
3395 /**
3396 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3397 * @netdev: network interface device structure
3398 *
3399 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3400 * address list or the network interface flags are updated. This routine is
3401 * responsible for configuring the hardware for proper unicast, multicast,
3402 * promiscuous mode, and all-multi behavior.
3403 **/
e1000e_set_rx_mode(struct net_device * netdev)3404 static void e1000e_set_rx_mode(struct net_device *netdev)
3405 {
3406 struct e1000_adapter *adapter = netdev_priv(netdev);
3407 struct e1000_hw *hw = &adapter->hw;
3408 u32 rctl;
3409
3410 if (pm_runtime_suspended(netdev->dev.parent))
3411 return;
3412
3413 /* Check for Promiscuous and All Multicast modes */
3414 rctl = er32(RCTL);
3415
3416 /* clear the affected bits */
3417 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3418
3419 if (netdev->flags & IFF_PROMISC) {
3420 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3421 /* Do not hardware filter VLANs in promisc mode */
3422 e1000e_vlan_filter_disable(adapter);
3423 } else {
3424 int count;
3425
3426 if (netdev->flags & IFF_ALLMULTI) {
3427 rctl |= E1000_RCTL_MPE;
3428 } else {
3429 /* Write addresses to the MTA, if the attempt fails
3430 * then we should just turn on promiscuous mode so
3431 * that we can at least receive multicast traffic
3432 */
3433 count = e1000e_write_mc_addr_list(netdev);
3434 if (count < 0)
3435 rctl |= E1000_RCTL_MPE;
3436 }
3437 e1000e_vlan_filter_enable(adapter);
3438 /* Write addresses to available RAR registers, if there is not
3439 * sufficient space to store all the addresses then enable
3440 * unicast promiscuous mode
3441 */
3442 count = e1000e_write_uc_addr_list(netdev);
3443 if (count < 0)
3444 rctl |= E1000_RCTL_UPE;
3445 }
3446
3447 ew32(RCTL, rctl);
3448
3449 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3450 e1000e_vlan_strip_enable(adapter);
3451 else
3452 e1000e_vlan_strip_disable(adapter);
3453 }
3454
e1000e_setup_rss_hash(struct e1000_adapter * adapter)3455 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3456 {
3457 struct e1000_hw *hw = &adapter->hw;
3458 u32 mrqc, rxcsum;
3459 u32 rss_key[10];
3460 int i;
3461
3462 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3463 for (i = 0; i < 10; i++)
3464 ew32(RSSRK(i), rss_key[i]);
3465
3466 /* Direct all traffic to queue 0 */
3467 for (i = 0; i < 32; i++)
3468 ew32(RETA(i), 0);
3469
3470 /* Disable raw packet checksumming so that RSS hash is placed in
3471 * descriptor on writeback.
3472 */
3473 rxcsum = er32(RXCSUM);
3474 rxcsum |= E1000_RXCSUM_PCSD;
3475
3476 ew32(RXCSUM, rxcsum);
3477
3478 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3479 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3480 E1000_MRQC_RSS_FIELD_IPV6 |
3481 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3482 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3483
3484 ew32(MRQC, mrqc);
3485 }
3486
3487 /**
3488 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3489 * @adapter: board private structure
3490 * @timinca: pointer to returned time increment attributes
3491 *
3492 * Get attributes for incrementing the System Time Register SYSTIML/H at
3493 * the default base frequency, and set the cyclecounter shift value.
3494 **/
e1000e_get_base_timinca(struct e1000_adapter * adapter,u32 * timinca)3495 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3496 {
3497 struct e1000_hw *hw = &adapter->hw;
3498 u32 incvalue, incperiod, shift;
3499
3500 /* Make sure clock is enabled on I217/I218/I219 before checking
3501 * the frequency
3502 */
3503 if ((hw->mac.type >= e1000_pch_lpt) &&
3504 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3505 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3506 u32 fextnvm7 = er32(FEXTNVM7);
3507
3508 if (!(fextnvm7 & BIT(0))) {
3509 ew32(FEXTNVM7, fextnvm7 | BIT(0));
3510 e1e_flush();
3511 }
3512 }
3513
3514 switch (hw->mac.type) {
3515 case e1000_pch2lan:
3516 /* Stable 96MHz frequency */
3517 incperiod = INCPERIOD_96MHZ;
3518 incvalue = INCVALUE_96MHZ;
3519 shift = INCVALUE_SHIFT_96MHZ;
3520 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3521 break;
3522 case e1000_pch_lpt:
3523 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3524 /* Stable 96MHz frequency */
3525 incperiod = INCPERIOD_96MHZ;
3526 incvalue = INCVALUE_96MHZ;
3527 shift = INCVALUE_SHIFT_96MHZ;
3528 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3529 } else {
3530 /* Stable 25MHz frequency */
3531 incperiod = INCPERIOD_25MHZ;
3532 incvalue = INCVALUE_25MHZ;
3533 shift = INCVALUE_SHIFT_25MHZ;
3534 adapter->cc.shift = shift;
3535 }
3536 break;
3537 case e1000_pch_spt:
3538 /* Stable 24MHz frequency */
3539 incperiod = INCPERIOD_24MHZ;
3540 incvalue = INCVALUE_24MHZ;
3541 shift = INCVALUE_SHIFT_24MHZ;
3542 adapter->cc.shift = shift;
3543 break;
3544 case e1000_pch_cnp:
3545 case e1000_pch_tgp:
3546 case e1000_pch_adp:
3547 case e1000_pch_nvp:
3548 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3549 /* Stable 24MHz frequency */
3550 incperiod = INCPERIOD_24MHZ;
3551 incvalue = INCVALUE_24MHZ;
3552 shift = INCVALUE_SHIFT_24MHZ;
3553 adapter->cc.shift = shift;
3554 } else {
3555 /* Stable 38400KHz frequency */
3556 incperiod = INCPERIOD_38400KHZ;
3557 incvalue = INCVALUE_38400KHZ;
3558 shift = INCVALUE_SHIFT_38400KHZ;
3559 adapter->cc.shift = shift;
3560 }
3561 break;
3562 case e1000_pch_mtp:
3563 case e1000_pch_lnp:
3564 case e1000_pch_ptp:
3565 /* System firmware can misreport this value, so set it to a
3566 * stable 38400KHz frequency.
3567 */
3568 incperiod = INCPERIOD_38400KHZ;
3569 incvalue = INCVALUE_38400KHZ;
3570 shift = INCVALUE_SHIFT_38400KHZ;
3571 adapter->cc.shift = shift;
3572 break;
3573 case e1000_82574:
3574 case e1000_82583:
3575 /* Stable 25MHz frequency */
3576 incperiod = INCPERIOD_25MHZ;
3577 incvalue = INCVALUE_25MHZ;
3578 shift = INCVALUE_SHIFT_25MHZ;
3579 adapter->cc.shift = shift;
3580 break;
3581 default:
3582 return -EINVAL;
3583 }
3584
3585 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3586 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3587
3588 return 0;
3589 }
3590
3591 /**
3592 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3593 * @adapter: board private structure
3594 * @config: timestamp configuration
3595 * @extack: netlink extended ACK for error report
3596 *
3597 * Outgoing time stamping can be enabled and disabled. Play nice and
3598 * disable it when requested, although it shouldn't cause any overhead
3599 * when no packet needs it. At most one packet in the queue may be
3600 * marked for time stamping, otherwise it would be impossible to tell
3601 * for sure to which packet the hardware time stamp belongs.
3602 *
3603 * Incoming time stamping has to be configured via the hardware filters.
3604 * Not all combinations are supported, in particular event type has to be
3605 * specified. Matching the kind of event packet is not supported, with the
3606 * exception of "all V2 events regardless of level 2 or 4".
3607 **/
e1000e_config_hwtstamp(struct e1000_adapter * adapter,struct kernel_hwtstamp_config * config,struct netlink_ext_ack * extack)3608 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3609 struct kernel_hwtstamp_config *config,
3610 struct netlink_ext_ack *extack)
3611 {
3612 struct e1000_hw *hw = &adapter->hw;
3613 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3614 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3615 u32 rxmtrl = 0;
3616 u16 rxudp = 0;
3617 bool is_l4 = false;
3618 bool is_l2 = false;
3619 u32 regval;
3620
3621 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
3622 NL_SET_ERR_MSG(extack, "No HW timestamp support");
3623 return -EINVAL;
3624 }
3625
3626 switch (config->tx_type) {
3627 case HWTSTAMP_TX_OFF:
3628 tsync_tx_ctl = 0;
3629 break;
3630 case HWTSTAMP_TX_ON:
3631 break;
3632 default:
3633 NL_SET_ERR_MSG(extack, "Unsupported TX HW timestamp type");
3634 return -ERANGE;
3635 }
3636
3637 switch (config->rx_filter) {
3638 case HWTSTAMP_FILTER_NONE:
3639 tsync_rx_ctl = 0;
3640 break;
3641 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3642 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3643 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3644 is_l4 = true;
3645 break;
3646 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3647 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3648 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3649 is_l4 = true;
3650 break;
3651 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3652 /* Also time stamps V2 L2 Path Delay Request/Response */
3653 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3654 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3655 is_l2 = true;
3656 break;
3657 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3658 /* Also time stamps V2 L2 Path Delay Request/Response. */
3659 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3660 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3661 is_l2 = true;
3662 break;
3663 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3664 /* Hardware cannot filter just V2 L4 Sync messages */
3665 fallthrough;
3666 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3667 /* Also time stamps V2 Path Delay Request/Response. */
3668 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3669 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3670 is_l2 = true;
3671 is_l4 = true;
3672 break;
3673 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3674 /* Hardware cannot filter just V2 L4 Delay Request messages */
3675 fallthrough;
3676 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3677 /* Also time stamps V2 Path Delay Request/Response. */
3678 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3679 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3680 is_l2 = true;
3681 is_l4 = true;
3682 break;
3683 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3684 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3685 /* Hardware cannot filter just V2 L4 or L2 Event messages */
3686 fallthrough;
3687 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3688 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3689 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3690 is_l2 = true;
3691 is_l4 = true;
3692 break;
3693 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3694 /* For V1, the hardware can only filter Sync messages or
3695 * Delay Request messages but not both so fall-through to
3696 * time stamp all packets.
3697 */
3698 fallthrough;
3699 case HWTSTAMP_FILTER_NTP_ALL:
3700 case HWTSTAMP_FILTER_ALL:
3701 is_l2 = true;
3702 is_l4 = true;
3703 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3704 config->rx_filter = HWTSTAMP_FILTER_ALL;
3705 break;
3706 default:
3707 NL_SET_ERR_MSG(extack, "Unsupported RX HW timestamp filter");
3708 return -ERANGE;
3709 }
3710
3711 adapter->hwtstamp_config = *config;
3712
3713 /* enable/disable Tx h/w time stamping */
3714 regval = er32(TSYNCTXCTL);
3715 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3716 regval |= tsync_tx_ctl;
3717 ew32(TSYNCTXCTL, regval);
3718 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3719 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3720 NL_SET_ERR_MSG(extack,
3721 "Timesync Tx Control register not set as expected");
3722 return -EAGAIN;
3723 }
3724
3725 /* enable/disable Rx h/w time stamping */
3726 regval = er32(TSYNCRXCTL);
3727 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3728 regval |= tsync_rx_ctl;
3729 ew32(TSYNCRXCTL, regval);
3730 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3731 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3732 (regval & (E1000_TSYNCRXCTL_ENABLED |
3733 E1000_TSYNCRXCTL_TYPE_MASK))) {
3734 NL_SET_ERR_MSG(extack,
3735 "Timesync Rx Control register not set as expected");
3736 return -EAGAIN;
3737 }
3738
3739 /* L2: define ethertype filter for time stamped packets */
3740 if (is_l2)
3741 rxmtrl |= ETH_P_1588;
3742
3743 /* define which PTP packets get time stamped */
3744 ew32(RXMTRL, rxmtrl);
3745
3746 /* Filter by destination port */
3747 if (is_l4) {
3748 rxudp = PTP_EV_PORT;
3749 cpu_to_be16s(&rxudp);
3750 }
3751 ew32(RXUDP, rxudp);
3752
3753 e1e_flush();
3754
3755 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3756 er32(RXSTMPH);
3757 er32(TXSTMPH);
3758
3759 return 0;
3760 }
3761
3762 /**
3763 * e1000_configure - configure the hardware for Rx and Tx
3764 * @adapter: private board structure
3765 **/
e1000_configure(struct e1000_adapter * adapter)3766 static void e1000_configure(struct e1000_adapter *adapter)
3767 {
3768 struct e1000_ring *rx_ring = adapter->rx_ring;
3769
3770 e1000e_set_rx_mode(adapter->netdev);
3771
3772 e1000_restore_vlan(adapter);
3773 e1000_init_manageability_pt(adapter);
3774
3775 e1000_configure_tx(adapter);
3776
3777 if (adapter->netdev->features & NETIF_F_RXHASH)
3778 e1000e_setup_rss_hash(adapter);
3779 e1000_setup_rctl(adapter);
3780 e1000_configure_rx(adapter);
3781 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
3782 }
3783
3784 /**
3785 * e1000e_power_up_phy - restore link in case the phy was powered down
3786 * @adapter: address of board private structure
3787 *
3788 * The phy may be powered down to save power and turn off link when the
3789 * driver is unloaded and wake on lan is not enabled (among others)
3790 * *** this routine MUST be followed by a call to e1000e_reset ***
3791 **/
e1000e_power_up_phy(struct e1000_adapter * adapter)3792 void e1000e_power_up_phy(struct e1000_adapter *adapter)
3793 {
3794 if (adapter->hw.phy.ops.power_up)
3795 adapter->hw.phy.ops.power_up(&adapter->hw);
3796
3797 adapter->hw.mac.ops.setup_link(&adapter->hw);
3798 }
3799
3800 /**
3801 * e1000_power_down_phy - Power down the PHY
3802 * @adapter: board private structure
3803 *
3804 * Power down the PHY so no link is implied when interface is down.
3805 * The PHY cannot be powered down if management or WoL is active.
3806 */
e1000_power_down_phy(struct e1000_adapter * adapter)3807 static void e1000_power_down_phy(struct e1000_adapter *adapter)
3808 {
3809 if (adapter->hw.phy.ops.power_down)
3810 adapter->hw.phy.ops.power_down(&adapter->hw);
3811 }
3812
3813 /**
3814 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3815 * @adapter: board private structure
3816 *
3817 * We want to clear all pending descriptors from the TX ring.
3818 * zeroing happens when the HW reads the regs. We assign the ring itself as
3819 * the data of the next descriptor. We don't care about the data we are about
3820 * to reset the HW.
3821 */
e1000_flush_tx_ring(struct e1000_adapter * adapter)3822 static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3823 {
3824 struct e1000_hw *hw = &adapter->hw;
3825 struct e1000_ring *tx_ring = adapter->tx_ring;
3826 struct e1000_tx_desc *tx_desc = NULL;
3827 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3828 u16 size = 512;
3829
3830 tctl = er32(TCTL);
3831 ew32(TCTL, tctl | E1000_TCTL_EN);
3832 tdt = er32(TDT(0));
3833 BUG_ON(tdt != tx_ring->next_to_use);
3834 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3835 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma);
3836
3837 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3838 tx_desc->upper.data = 0;
3839 /* flush descriptors to memory before notifying the HW */
3840 wmb();
3841 tx_ring->next_to_use++;
3842 if (tx_ring->next_to_use == tx_ring->count)
3843 tx_ring->next_to_use = 0;
3844 ew32(TDT(0), tx_ring->next_to_use);
3845 usleep_range(200, 250);
3846 }
3847
3848 /**
3849 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3850 * @adapter: board private structure
3851 *
3852 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3853 */
e1000_flush_rx_ring(struct e1000_adapter * adapter)3854 static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3855 {
3856 u32 rctl, rxdctl;
3857 struct e1000_hw *hw = &adapter->hw;
3858
3859 rctl = er32(RCTL);
3860 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3861 e1e_flush();
3862 usleep_range(100, 150);
3863
3864 rxdctl = er32(RXDCTL(0));
3865 /* zero the lower 14 bits (prefetch and host thresholds) */
3866 rxdctl &= 0xffffc000;
3867
3868 /* update thresholds: prefetch threshold to 31, host threshold to 1
3869 * and make sure the granularity is "descriptors" and not "cache lines"
3870 */
3871 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3872
3873 ew32(RXDCTL(0), rxdctl);
3874 /* momentarily enable the RX ring for the changes to take effect */
3875 ew32(RCTL, rctl | E1000_RCTL_EN);
3876 e1e_flush();
3877 usleep_range(100, 150);
3878 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3879 }
3880
3881 /**
3882 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3883 * @adapter: board private structure
3884 *
3885 * In i219, the descriptor rings must be emptied before resetting the HW
3886 * or before changing the device state to D3 during runtime (runtime PM).
3887 *
3888 * Failure to do this will cause the HW to enter a unit hang state which can
3889 * only be released by PCI reset on the device
3890 *
3891 */
3892
e1000_flush_desc_rings(struct e1000_adapter * adapter)3893 static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3894 {
3895 u16 hang_state;
3896 u32 fext_nvm11, tdlen;
3897 struct e1000_hw *hw = &adapter->hw;
3898
3899 /* First, disable MULR fix in FEXTNVM11 */
3900 fext_nvm11 = er32(FEXTNVM11);
3901 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3902 ew32(FEXTNVM11, fext_nvm11);
3903 /* do nothing if we're not in faulty state, or if the queue is empty */
3904 tdlen = er32(TDLEN(0));
3905 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3906 &hang_state);
3907 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3908 return;
3909 e1000_flush_tx_ring(adapter);
3910 /* recheck, maybe the fault is caused by the rx ring */
3911 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3912 &hang_state);
3913 if (hang_state & FLUSH_DESC_REQUIRED)
3914 e1000_flush_rx_ring(adapter);
3915 }
3916
3917 /**
3918 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3919 * @adapter: board private structure
3920 *
3921 * When the MAC is reset, all hardware bits for timesync will be reset to the
3922 * default values. This function will restore the settings last in place.
3923 * Since the clock SYSTIME registers are reset, we will simply restore the
3924 * cyclecounter to the kernel real clock time.
3925 **/
e1000e_systim_reset(struct e1000_adapter * adapter)3926 static void e1000e_systim_reset(struct e1000_adapter *adapter)
3927 {
3928 struct ptp_clock_info *info = &adapter->ptp_clock_info;
3929 struct e1000_hw *hw = &adapter->hw;
3930 struct netlink_ext_ack extack = {};
3931 unsigned long flags;
3932 u32 timinca;
3933 s32 ret_val;
3934
3935 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3936 return;
3937
3938 if (info->adjfine) {
3939 /* restore the previous ptp frequency delta */
3940 ret_val = info->adjfine(info, adapter->ptp_delta);
3941 } else {
3942 /* set the default base frequency if no adjustment possible */
3943 ret_val = e1000e_get_base_timinca(adapter, &timinca);
3944 if (!ret_val)
3945 ew32(TIMINCA, timinca);
3946 }
3947
3948 if (ret_val) {
3949 dev_warn(&adapter->pdev->dev,
3950 "Failed to restore TIMINCA clock rate delta: %d\n",
3951 ret_val);
3952 return;
3953 }
3954
3955 /* reset the systim ns time counter */
3956 spin_lock_irqsave(&adapter->systim_lock, flags);
3957 timecounter_init(&adapter->tc, &adapter->cc,
3958 ktime_get_real_ns());
3959 spin_unlock_irqrestore(&adapter->systim_lock, flags);
3960
3961 /* restore the previous hwtstamp configuration settings */
3962 ret_val = e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config,
3963 &extack);
3964 if (ret_val) {
3965 if (extack._msg)
3966 e_err("%s\n", extack._msg);
3967 }
3968 }
3969
3970 /**
3971 * e1000e_reset - bring the hardware into a known good state
3972 * @adapter: board private structure
3973 *
3974 * This function boots the hardware and enables some settings that
3975 * require a configuration cycle of the hardware - those cannot be
3976 * set/changed during runtime. After reset the device needs to be
3977 * properly configured for Rx, Tx etc.
3978 */
e1000e_reset(struct e1000_adapter * adapter)3979 void e1000e_reset(struct e1000_adapter *adapter)
3980 {
3981 struct e1000_mac_info *mac = &adapter->hw.mac;
3982 struct e1000_fc_info *fc = &adapter->hw.fc;
3983 struct e1000_hw *hw = &adapter->hw;
3984 u32 tx_space, min_tx_space, min_rx_space;
3985 u32 pba = adapter->pba;
3986 u16 hwm;
3987
3988 /* reset Packet Buffer Allocation to default */
3989 ew32(PBA, pba);
3990
3991 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
3992 /* To maintain wire speed transmits, the Tx FIFO should be
3993 * large enough to accommodate two full transmit packets,
3994 * rounded up to the next 1KB and expressed in KB. Likewise,
3995 * the Rx FIFO should be large enough to accommodate at least
3996 * one full receive packet and is similarly rounded up and
3997 * expressed in KB.
3998 */
3999 pba = er32(PBA);
4000 /* upper 16 bits has Tx packet buffer allocation size in KB */
4001 tx_space = pba >> 16;
4002 /* lower 16 bits has Rx packet buffer allocation size in KB */
4003 pba &= 0xffff;
4004 /* the Tx fifo also stores 16 bytes of information about the Tx
4005 * but don't include ethernet FCS because hardware appends it
4006 */
4007 min_tx_space = (adapter->max_frame_size +
4008 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
4009 min_tx_space = ALIGN(min_tx_space, 1024);
4010 min_tx_space >>= 10;
4011 /* software strips receive CRC, so leave room for it */
4012 min_rx_space = adapter->max_frame_size;
4013 min_rx_space = ALIGN(min_rx_space, 1024);
4014 min_rx_space >>= 10;
4015
4016 /* If current Tx allocation is less than the min Tx FIFO size,
4017 * and the min Tx FIFO size is less than the current Rx FIFO
4018 * allocation, take space away from current Rx allocation
4019 */
4020 if ((tx_space < min_tx_space) &&
4021 ((min_tx_space - tx_space) < pba)) {
4022 pba -= min_tx_space - tx_space;
4023
4024 /* if short on Rx space, Rx wins and must trump Tx
4025 * adjustment
4026 */
4027 if (pba < min_rx_space)
4028 pba = min_rx_space;
4029 }
4030
4031 ew32(PBA, pba);
4032 }
4033
4034 /* flow control settings
4035 *
4036 * The high water mark must be low enough to fit one full frame
4037 * (or the size used for early receive) above it in the Rx FIFO.
4038 * Set it to the lower of:
4039 * - 90% of the Rx FIFO size, and
4040 * - the full Rx FIFO size minus one full frame
4041 */
4042 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
4043 fc->pause_time = 0xFFFF;
4044 else
4045 fc->pause_time = E1000_FC_PAUSE_TIME;
4046 fc->send_xon = true;
4047 fc->current_mode = fc->requested_mode;
4048
4049 switch (hw->mac.type) {
4050 case e1000_ich9lan:
4051 case e1000_ich10lan:
4052 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4053 pba = 14;
4054 ew32(PBA, pba);
4055 fc->high_water = 0x2800;
4056 fc->low_water = fc->high_water - 8;
4057 break;
4058 }
4059 fallthrough;
4060 default:
4061 hwm = min(((pba << 10) * 9 / 10),
4062 ((pba << 10) - adapter->max_frame_size));
4063
4064 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
4065 fc->low_water = fc->high_water - 8;
4066 break;
4067 case e1000_pchlan:
4068 /* Workaround PCH LOM adapter hangs with certain network
4069 * loads. If hangs persist, try disabling Tx flow control.
4070 */
4071 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4072 fc->high_water = 0x3500;
4073 fc->low_water = 0x1500;
4074 } else {
4075 fc->high_water = 0x5000;
4076 fc->low_water = 0x3000;
4077 }
4078 fc->refresh_time = 0x1000;
4079 break;
4080 case e1000_pch2lan:
4081 case e1000_pch_lpt:
4082 case e1000_pch_spt:
4083 case e1000_pch_cnp:
4084 case e1000_pch_tgp:
4085 case e1000_pch_adp:
4086 case e1000_pch_mtp:
4087 case e1000_pch_lnp:
4088 case e1000_pch_ptp:
4089 case e1000_pch_nvp:
4090 fc->refresh_time = 0xFFFF;
4091 fc->pause_time = 0xFFFF;
4092
4093 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4094 fc->high_water = 0x05C20;
4095 fc->low_water = 0x05048;
4096 break;
4097 }
4098
4099 pba = 14;
4100 ew32(PBA, pba);
4101 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4102 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
4103 break;
4104 }
4105
4106 /* Alignment of Tx data is on an arbitrary byte boundary with the
4107 * maximum size per Tx descriptor limited only to the transmit
4108 * allocation of the packet buffer minus 96 bytes with an upper
4109 * limit of 24KB due to receive synchronization limitations.
4110 */
4111 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4112 24 << 10);
4113
4114 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4115 * fit in receive buffer.
4116 */
4117 if (adapter->itr_setting & 0x3) {
4118 if ((adapter->max_frame_size * 2) > (pba << 10)) {
4119 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4120 dev_info(&adapter->pdev->dev,
4121 "Interrupt Throttle Rate off\n");
4122 adapter->flags2 |= FLAG2_DISABLE_AIM;
4123 e1000e_write_itr(adapter, 0);
4124 }
4125 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4126 dev_info(&adapter->pdev->dev,
4127 "Interrupt Throttle Rate on\n");
4128 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4129 adapter->itr = 20000;
4130 e1000e_write_itr(adapter, adapter->itr);
4131 }
4132 }
4133
4134 if (hw->mac.type >= e1000_pch_spt)
4135 e1000_flush_desc_rings(adapter);
4136 /* Allow time for pending master requests to run */
4137 mac->ops.reset_hw(hw);
4138
4139 /* For parts with AMT enabled, let the firmware know
4140 * that the network interface is in control
4141 */
4142 if (adapter->flags & FLAG_HAS_AMT)
4143 e1000e_get_hw_control(adapter);
4144
4145 ew32(WUC, 0);
4146
4147 if (mac->ops.init_hw(hw))
4148 e_err("Hardware Error\n");
4149
4150 e1000_update_mng_vlan(adapter);
4151
4152 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4153 ew32(VET, ETH_P_8021Q);
4154
4155 e1000e_reset_adaptive(hw);
4156
4157 /* restore systim and hwtstamp settings */
4158 e1000e_systim_reset(adapter);
4159
4160 /* Set EEE advertisement as appropriate */
4161 if (adapter->flags2 & FLAG2_HAS_EEE) {
4162 s32 ret_val;
4163 u16 adv_addr;
4164
4165 switch (hw->phy.type) {
4166 case e1000_phy_82579:
4167 adv_addr = I82579_EEE_ADVERTISEMENT;
4168 break;
4169 case e1000_phy_i217:
4170 adv_addr = I217_EEE_ADVERTISEMENT;
4171 break;
4172 default:
4173 dev_err(&adapter->pdev->dev,
4174 "Invalid PHY type setting EEE advertisement\n");
4175 return;
4176 }
4177
4178 ret_val = hw->phy.ops.acquire(hw);
4179 if (ret_val) {
4180 dev_err(&adapter->pdev->dev,
4181 "EEE advertisement - unable to acquire PHY\n");
4182 return;
4183 }
4184
4185 e1000_write_emi_reg_locked(hw, adv_addr,
4186 hw->dev_spec.ich8lan.eee_disable ?
4187 0 : adapter->eee_advert);
4188
4189 hw->phy.ops.release(hw);
4190 }
4191
4192 if (!netif_running(adapter->netdev) &&
4193 !test_bit(__E1000_TESTING, &adapter->state))
4194 e1000_power_down_phy(adapter);
4195
4196 e1000_get_phy_info(hw);
4197
4198 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4199 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
4200 u16 phy_data = 0;
4201 /* speed up time to link by disabling smart power down, ignore
4202 * the return value of this function because there is nothing
4203 * different we would do if it failed
4204 */
4205 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4206 phy_data &= ~IGP02E1000_PM_SPD;
4207 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4208 }
4209 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) {
4210 u32 reg;
4211
4212 /* Fextnvm7 @ 0xe4[2] = 1 */
4213 reg = er32(FEXTNVM7);
4214 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4215 ew32(FEXTNVM7, reg);
4216 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4217 reg = er32(FEXTNVM9);
4218 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4219 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4220 ew32(FEXTNVM9, reg);
4221 }
4222
4223 }
4224
4225 /**
4226 * e1000e_trigger_lsc - trigger an LSC interrupt
4227 * @adapter: board private structure
4228 *
4229 * Fire a link status change interrupt to start the watchdog.
4230 **/
e1000e_trigger_lsc(struct e1000_adapter * adapter)4231 static void e1000e_trigger_lsc(struct e1000_adapter *adapter)
4232 {
4233 struct e1000_hw *hw = &adapter->hw;
4234
4235 if (adapter->msix_entries)
4236 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER);
4237 else
4238 ew32(ICS, E1000_ICS_LSC);
4239 }
4240
e1000e_up(struct e1000_adapter * adapter)4241 void e1000e_up(struct e1000_adapter *adapter)
4242 {
4243 /* hardware has been reset, we need to reload some things */
4244 e1000_configure(adapter);
4245
4246 clear_bit(__E1000_DOWN, &adapter->state);
4247
4248 if (adapter->msix_entries)
4249 e1000_configure_msix(adapter);
4250 e1000_irq_enable(adapter);
4251
4252 /* Tx queue started by watchdog timer when link is up */
4253
4254 e1000e_trigger_lsc(adapter);
4255 }
4256
e1000e_flush_descriptors(struct e1000_adapter * adapter)4257 static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4258 {
4259 struct e1000_hw *hw = &adapter->hw;
4260
4261 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4262 return;
4263
4264 /* flush pending descriptor writebacks to memory */
4265 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4266 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4267
4268 /* execute the writes immediately */
4269 e1e_flush();
4270
4271 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4272 * write is successful
4273 */
4274 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4275 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4276
4277 /* execute the writes immediately */
4278 e1e_flush();
4279 }
4280
4281 static void e1000e_update_stats(struct e1000_adapter *adapter);
4282
4283 /**
4284 * e1000e_down - quiesce the device and optionally reset the hardware
4285 * @adapter: board private structure
4286 * @reset: boolean flag to reset the hardware or not
4287 */
e1000e_down(struct e1000_adapter * adapter,bool reset)4288 void e1000e_down(struct e1000_adapter *adapter, bool reset)
4289 {
4290 struct net_device *netdev = adapter->netdev;
4291 struct e1000_hw *hw = &adapter->hw;
4292 u32 tctl, rctl;
4293
4294 /* signal that we're down so the interrupt handler does not
4295 * reschedule our watchdog timer
4296 */
4297 set_bit(__E1000_DOWN, &adapter->state);
4298
4299 netif_carrier_off(netdev);
4300
4301 /* disable receives in the hardware */
4302 rctl = er32(RCTL);
4303 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4304 ew32(RCTL, rctl & ~E1000_RCTL_EN);
4305 /* flush and sleep below */
4306
4307 netif_stop_queue(netdev);
4308
4309 /* disable transmits in the hardware */
4310 tctl = er32(TCTL);
4311 tctl &= ~E1000_TCTL_EN;
4312 ew32(TCTL, tctl);
4313
4314 /* flush both disables and wait for them to finish */
4315 e1e_flush();
4316 usleep_range(10000, 11000);
4317
4318 e1000_irq_disable(adapter);
4319
4320 napi_synchronize(&adapter->napi);
4321
4322 timer_delete_sync(&adapter->watchdog_timer);
4323 timer_delete_sync(&adapter->phy_info_timer);
4324
4325 spin_lock(&adapter->stats64_lock);
4326 e1000e_update_stats(adapter);
4327 spin_unlock(&adapter->stats64_lock);
4328
4329 e1000e_flush_descriptors(adapter);
4330
4331 adapter->link_speed = 0;
4332 adapter->link_duplex = 0;
4333
4334 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4335 if ((hw->mac.type >= e1000_pch2lan) &&
4336 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4337 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4338 e_dbg("failed to disable jumbo frame workaround mode\n");
4339
4340 if (!pci_channel_offline(adapter->pdev)) {
4341 if (reset)
4342 e1000e_reset(adapter);
4343 else if (hw->mac.type >= e1000_pch_spt)
4344 e1000_flush_desc_rings(adapter);
4345 }
4346 e1000_clean_tx_ring(adapter->tx_ring);
4347 e1000_clean_rx_ring(adapter->rx_ring);
4348 }
4349
e1000e_reinit_locked(struct e1000_adapter * adapter)4350 void e1000e_reinit_locked(struct e1000_adapter *adapter)
4351 {
4352 might_sleep();
4353 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4354 usleep_range(1000, 1100);
4355 e1000e_down(adapter, true);
4356 e1000e_up(adapter);
4357 clear_bit(__E1000_RESETTING, &adapter->state);
4358 }
4359
4360 /**
4361 * e1000e_sanitize_systim - sanitize raw cycle counter reads
4362 * @hw: pointer to the HW structure
4363 * @systim: PHC time value read, sanitized and returned
4364 * @sts: structure to hold system time before and after reading SYSTIML,
4365 * may be NULL
4366 *
4367 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4368 * check to see that the time is incrementing at a reasonable
4369 * rate and is a multiple of incvalue.
4370 **/
e1000e_sanitize_systim(struct e1000_hw * hw,u64 systim,struct ptp_system_timestamp * sts)4371 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim,
4372 struct ptp_system_timestamp *sts)
4373 {
4374 u64 time_delta, rem, temp;
4375 u64 systim_next;
4376 u32 incvalue;
4377 int i;
4378
4379 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4380 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4381 /* latch SYSTIMH on read of SYSTIML */
4382 ptp_read_system_prets(sts);
4383 systim_next = (u64)er32(SYSTIML);
4384 ptp_read_system_postts(sts);
4385 systim_next |= (u64)er32(SYSTIMH) << 32;
4386
4387 time_delta = systim_next - systim;
4388 temp = time_delta;
4389 /* VMWare users have seen incvalue of zero, don't div / 0 */
4390 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0);
4391
4392 systim = systim_next;
4393
4394 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0))
4395 break;
4396 }
4397
4398 return systim;
4399 }
4400
4401 /**
4402 * e1000e_read_systim - read SYSTIM register
4403 * @adapter: board private structure
4404 * @sts: structure which will contain system time before and after reading
4405 * SYSTIML, may be NULL
4406 **/
e1000e_read_systim(struct e1000_adapter * adapter,struct ptp_system_timestamp * sts)4407 u64 e1000e_read_systim(struct e1000_adapter *adapter,
4408 struct ptp_system_timestamp *sts)
4409 {
4410 struct e1000_hw *hw = &adapter->hw;
4411 u32 systimel, systimel_2, systimeh;
4412 u64 systim;
4413 /* SYSTIMH latching upon SYSTIML read does not work well.
4414 * This means that if SYSTIML overflows after we read it but before
4415 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4416 * will experience a huge non linear increment in the systime value
4417 * to fix that we test for overflow and if true, we re-read systime.
4418 */
4419 ptp_read_system_prets(sts);
4420 systimel = er32(SYSTIML);
4421 ptp_read_system_postts(sts);
4422 systimeh = er32(SYSTIMH);
4423 /* Is systimel is so large that overflow is possible? */
4424 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
4425 ptp_read_system_prets(sts);
4426 systimel_2 = er32(SYSTIML);
4427 ptp_read_system_postts(sts);
4428 if (systimel > systimel_2) {
4429 /* There was an overflow, read again SYSTIMH, and use
4430 * systimel_2
4431 */
4432 systimeh = er32(SYSTIMH);
4433 systimel = systimel_2;
4434 }
4435 }
4436 systim = (u64)systimel;
4437 systim |= (u64)systimeh << 32;
4438
4439 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW)
4440 systim = e1000e_sanitize_systim(hw, systim, sts);
4441
4442 return systim;
4443 }
4444
4445 /**
4446 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4447 * @cc: cyclecounter structure
4448 **/
e1000e_cyclecounter_read(struct cyclecounter * cc)4449 static u64 e1000e_cyclecounter_read(struct cyclecounter *cc)
4450 {
4451 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4452 cc);
4453
4454 return e1000e_read_systim(adapter, NULL);
4455 }
4456
4457 /**
4458 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4459 * @adapter: board private structure to initialize
4460 *
4461 * e1000_sw_init initializes the Adapter private data structure.
4462 * Fields are initialized based on PCI device information and
4463 * OS network device settings (MTU size).
4464 **/
e1000_sw_init(struct e1000_adapter * adapter)4465 static int e1000_sw_init(struct e1000_adapter *adapter)
4466 {
4467 struct net_device *netdev = adapter->netdev;
4468
4469 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
4470 adapter->rx_ps_bsize0 = 128;
4471 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4472 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4473 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4474 adapter->rx_ring_count = E1000_DEFAULT_RXD;
4475
4476 spin_lock_init(&adapter->stats64_lock);
4477
4478 e1000e_set_interrupt_capability(adapter);
4479
4480 if (e1000_alloc_queues(adapter))
4481 return -ENOMEM;
4482
4483 /* Setup hardware time stamping cyclecounter */
4484 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4485 adapter->cc.read = e1000e_cyclecounter_read;
4486 adapter->cc.mask = CYCLECOUNTER_MASK(64);
4487 adapter->cc.mult = 1;
4488 /* cc.shift set in e1000e_get_base_tininca() */
4489
4490 spin_lock_init(&adapter->systim_lock);
4491 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4492 }
4493
4494 /* Explicitly disable IRQ since the NIC can be in any state. */
4495 e1000_irq_disable(adapter);
4496
4497 set_bit(__E1000_DOWN, &adapter->state);
4498 return 0;
4499 }
4500
4501 /**
4502 * e1000_intr_msi_test - Interrupt Handler
4503 * @irq: interrupt number
4504 * @data: pointer to a network interface device structure
4505 **/
e1000_intr_msi_test(int __always_unused irq,void * data)4506 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4507 {
4508 struct net_device *netdev = data;
4509 struct e1000_adapter *adapter = netdev_priv(netdev);
4510 struct e1000_hw *hw = &adapter->hw;
4511 u32 icr = er32(ICR);
4512
4513 e_dbg("icr is %08X\n", icr);
4514 if (icr & E1000_ICR_RXSEQ) {
4515 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4516 /* Force memory writes to complete before acknowledging the
4517 * interrupt is handled.
4518 */
4519 wmb();
4520 }
4521
4522 return IRQ_HANDLED;
4523 }
4524
4525 /**
4526 * e1000_test_msi_interrupt - Returns 0 for successful test
4527 * @adapter: board private struct
4528 *
4529 * code flow taken from tg3.c
4530 **/
e1000_test_msi_interrupt(struct e1000_adapter * adapter)4531 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4532 {
4533 struct net_device *netdev = adapter->netdev;
4534 struct e1000_hw *hw = &adapter->hw;
4535 int err;
4536
4537 /* poll_enable hasn't been called yet, so don't need disable */
4538 /* clear any pending events */
4539 er32(ICR);
4540
4541 /* free the real vector and request a test handler */
4542 e1000_free_irq(adapter);
4543 e1000e_reset_interrupt_capability(adapter);
4544
4545 /* Assume that the test fails, if it succeeds then the test
4546 * MSI irq handler will unset this flag
4547 */
4548 adapter->flags |= FLAG_MSI_TEST_FAILED;
4549
4550 err = pci_enable_msi(adapter->pdev);
4551 if (err)
4552 goto msi_test_failed;
4553
4554 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
4555 netdev->name, netdev);
4556 if (err) {
4557 pci_disable_msi(adapter->pdev);
4558 goto msi_test_failed;
4559 }
4560
4561 /* Force memory writes to complete before enabling and firing an
4562 * interrupt.
4563 */
4564 wmb();
4565
4566 e1000_irq_enable(adapter);
4567
4568 /* fire an unusual interrupt on the test handler */
4569 ew32(ICS, E1000_ICS_RXSEQ);
4570 e1e_flush();
4571 msleep(100);
4572
4573 e1000_irq_disable(adapter);
4574
4575 rmb(); /* read flags after interrupt has been fired */
4576
4577 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4578 adapter->int_mode = E1000E_INT_MODE_LEGACY;
4579 e_info("MSI interrupt test failed, using legacy interrupt.\n");
4580 } else {
4581 e_dbg("MSI interrupt test succeeded!\n");
4582 }
4583
4584 free_irq(adapter->pdev->irq, netdev);
4585 pci_disable_msi(adapter->pdev);
4586
4587 msi_test_failed:
4588 e1000e_set_interrupt_capability(adapter);
4589 return e1000_request_irq(adapter);
4590 }
4591
4592 /**
4593 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4594 * @adapter: board private struct
4595 *
4596 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4597 **/
e1000_test_msi(struct e1000_adapter * adapter)4598 static int e1000_test_msi(struct e1000_adapter *adapter)
4599 {
4600 int err;
4601 u16 pci_cmd;
4602
4603 if (!(adapter->flags & FLAG_MSI_ENABLED))
4604 return 0;
4605
4606 /* disable SERR in case the MSI write causes a master abort */
4607 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4608 if (pci_cmd & PCI_COMMAND_SERR)
4609 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4610 pci_cmd & ~PCI_COMMAND_SERR);
4611
4612 err = e1000_test_msi_interrupt(adapter);
4613
4614 /* re-enable SERR */
4615 if (pci_cmd & PCI_COMMAND_SERR) {
4616 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4617 pci_cmd |= PCI_COMMAND_SERR;
4618 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4619 }
4620
4621 return err;
4622 }
4623
4624 /**
4625 * e1000e_open - Called when a network interface is made active
4626 * @netdev: network interface device structure
4627 *
4628 * Returns 0 on success, negative value on failure
4629 *
4630 * The open entry point is called when a network interface is made
4631 * active by the system (IFF_UP). At this point all resources needed
4632 * for transmit and receive operations are allocated, the interrupt
4633 * handler is registered with the OS, the watchdog timer is started,
4634 * and the stack is notified that the interface is ready.
4635 **/
e1000e_open(struct net_device * netdev)4636 int e1000e_open(struct net_device *netdev)
4637 {
4638 struct e1000_adapter *adapter = netdev_priv(netdev);
4639 struct e1000_hw *hw = &adapter->hw;
4640 struct pci_dev *pdev = adapter->pdev;
4641 int err;
4642 int irq;
4643
4644 /* disallow open during test */
4645 if (test_bit(__E1000_TESTING, &adapter->state))
4646 return -EBUSY;
4647
4648 pm_runtime_get_sync(&pdev->dev);
4649
4650 netif_carrier_off(netdev);
4651 netif_stop_queue(netdev);
4652
4653 /* allocate transmit descriptors */
4654 err = e1000e_setup_tx_resources(adapter->tx_ring);
4655 if (err)
4656 goto err_setup_tx;
4657
4658 /* allocate receive descriptors */
4659 err = e1000e_setup_rx_resources(adapter->rx_ring);
4660 if (err)
4661 goto err_setup_rx;
4662
4663 /* If AMT is enabled, let the firmware know that the network
4664 * interface is now open and reset the part to a known state.
4665 */
4666 if (adapter->flags & FLAG_HAS_AMT) {
4667 e1000e_get_hw_control(adapter);
4668 e1000e_reset(adapter);
4669 }
4670
4671 e1000e_power_up_phy(adapter);
4672
4673 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4674 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4675 e1000_update_mng_vlan(adapter);
4676
4677 /* DMA latency requirement to workaround jumbo issue */
4678 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE);
4679
4680 /* before we allocate an interrupt, we must be ready to handle it.
4681 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4682 * as soon as we call pci_request_irq, so we have to setup our
4683 * clean_rx handler before we do so.
4684 */
4685 e1000_configure(adapter);
4686
4687 err = e1000_request_irq(adapter);
4688 if (err)
4689 goto err_req_irq;
4690
4691 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4692 * ignore e1000e MSI messages, which means we need to test our MSI
4693 * interrupt now
4694 */
4695 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4696 err = e1000_test_msi(adapter);
4697 if (err) {
4698 e_err("Interrupt allocation failed\n");
4699 goto err_req_irq;
4700 }
4701 }
4702
4703 /* From here on the code is the same as e1000e_up() */
4704 clear_bit(__E1000_DOWN, &adapter->state);
4705
4706 if (adapter->int_mode == E1000E_INT_MODE_MSIX)
4707 irq = adapter->msix_entries[0].vector;
4708 else
4709 irq = adapter->pdev->irq;
4710
4711 netif_napi_set_irq(&adapter->napi, irq);
4712 napi_enable(&adapter->napi);
4713 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_RX, &adapter->napi);
4714 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_TX, &adapter->napi);
4715
4716 e1000_irq_enable(adapter);
4717
4718 adapter->tx_hang_recheck = false;
4719
4720 hw->mac.get_link_status = true;
4721 pm_runtime_put(&pdev->dev);
4722
4723 e1000e_trigger_lsc(adapter);
4724
4725 return 0;
4726
4727 err_req_irq:
4728 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
4729 e1000e_release_hw_control(adapter);
4730 e1000_power_down_phy(adapter);
4731 e1000e_free_rx_resources(adapter->rx_ring);
4732 err_setup_rx:
4733 e1000e_free_tx_resources(adapter->tx_ring);
4734 err_setup_tx:
4735 e1000e_reset(adapter);
4736 pm_runtime_put_sync(&pdev->dev);
4737
4738 return err;
4739 }
4740
4741 /**
4742 * e1000e_close - Disables a network interface
4743 * @netdev: network interface device structure
4744 *
4745 * Returns 0, this is not allowed to fail
4746 *
4747 * The close entry point is called when an interface is de-activated
4748 * by the OS. The hardware is still under the drivers control, but
4749 * needs to be disabled. A global MAC reset is issued to stop the
4750 * hardware, and all transmit and receive resources are freed.
4751 **/
e1000e_close(struct net_device * netdev)4752 int e1000e_close(struct net_device *netdev)
4753 {
4754 struct e1000_adapter *adapter = netdev_priv(netdev);
4755 struct pci_dev *pdev = adapter->pdev;
4756 int count = E1000_CHECK_RESET_COUNT;
4757
4758 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4759 usleep_range(10000, 11000);
4760
4761 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4762
4763 pm_runtime_get_sync(&pdev->dev);
4764
4765 if (netif_device_present(netdev)) {
4766 e1000e_down(adapter, true);
4767 e1000_free_irq(adapter);
4768
4769 /* Link status message must follow this format */
4770 netdev_info(netdev, "NIC Link is Down\n");
4771 }
4772
4773 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_RX, NULL);
4774 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_TX, NULL);
4775 napi_disable(&adapter->napi);
4776
4777 e1000e_free_tx_resources(adapter->tx_ring);
4778 e1000e_free_rx_resources(adapter->rx_ring);
4779
4780 /* kill manageability vlan ID if supported, but not if a vlan with
4781 * the same ID is registered on the host OS (let 8021q kill it)
4782 */
4783 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4784 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4785 adapter->mng_vlan_id);
4786
4787 /* If AMT is enabled, let the firmware know that the network
4788 * interface is now closed
4789 */
4790 if ((adapter->flags & FLAG_HAS_AMT) &&
4791 !test_bit(__E1000_TESTING, &adapter->state))
4792 e1000e_release_hw_control(adapter);
4793
4794 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
4795
4796 pm_runtime_put_sync(&pdev->dev);
4797
4798 return 0;
4799 }
4800
4801 /**
4802 * e1000_set_mac - Change the Ethernet Address of the NIC
4803 * @netdev: network interface device structure
4804 * @p: pointer to an address structure
4805 *
4806 * Returns 0 on success, negative on failure
4807 **/
e1000_set_mac(struct net_device * netdev,void * p)4808 static int e1000_set_mac(struct net_device *netdev, void *p)
4809 {
4810 struct e1000_adapter *adapter = netdev_priv(netdev);
4811 struct e1000_hw *hw = &adapter->hw;
4812 struct sockaddr *addr = p;
4813
4814 if (!is_valid_ether_addr(addr->sa_data))
4815 return -EADDRNOTAVAIL;
4816
4817 eth_hw_addr_set(netdev, addr->sa_data);
4818 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4819
4820 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4821
4822 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4823 /* activate the work around */
4824 e1000e_set_laa_state_82571(&adapter->hw, 1);
4825
4826 /* Hold a copy of the LAA in RAR[14] This is done so that
4827 * between the time RAR[0] gets clobbered and the time it
4828 * gets fixed (in e1000_watchdog), the actual LAA is in one
4829 * of the RARs and no incoming packets directed to this port
4830 * are dropped. Eventually the LAA will be in RAR[0] and
4831 * RAR[14]
4832 */
4833 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4834 adapter->hw.mac.rar_entry_count - 1);
4835 }
4836
4837 return 0;
4838 }
4839
4840 /**
4841 * e1000e_update_phy_task - work thread to update phy
4842 * @work: pointer to our work struct
4843 *
4844 * this worker thread exists because we must acquire a
4845 * semaphore to read the phy, which we could msleep while
4846 * waiting for it, and we can't msleep in a timer.
4847 **/
e1000e_update_phy_task(struct work_struct * work)4848 static void e1000e_update_phy_task(struct work_struct *work)
4849 {
4850 struct e1000_adapter *adapter = container_of(work,
4851 struct e1000_adapter,
4852 update_phy_task);
4853 struct e1000_hw *hw = &adapter->hw;
4854
4855 if (test_bit(__E1000_DOWN, &adapter->state))
4856 return;
4857
4858 e1000_get_phy_info(hw);
4859
4860 /* Enable EEE on 82579 after link up */
4861 if (hw->phy.type >= e1000_phy_82579)
4862 e1000_set_eee_pchlan(hw);
4863 }
4864
4865 /**
4866 * e1000_update_phy_info - timre call-back to update PHY info
4867 * @t: pointer to timer_list containing private info adapter
4868 *
4869 * Need to wait a few seconds after link up to get diagnostic information from
4870 * the phy
4871 **/
e1000_update_phy_info(struct timer_list * t)4872 static void e1000_update_phy_info(struct timer_list *t)
4873 {
4874 struct e1000_adapter *adapter = timer_container_of(adapter, t,
4875 phy_info_timer);
4876
4877 if (test_bit(__E1000_DOWN, &adapter->state))
4878 return;
4879
4880 schedule_work(&adapter->update_phy_task);
4881 }
4882
4883 /**
4884 * e1000e_update_phy_stats - Update the PHY statistics counters
4885 * @adapter: board private structure
4886 *
4887 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4888 **/
e1000e_update_phy_stats(struct e1000_adapter * adapter)4889 static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4890 {
4891 struct e1000_hw *hw = &adapter->hw;
4892 s32 ret_val;
4893 u16 phy_data;
4894
4895 ret_val = hw->phy.ops.acquire(hw);
4896 if (ret_val)
4897 return;
4898
4899 /* A page set is expensive so check if already on desired page.
4900 * If not, set to the page with the PHY status registers.
4901 */
4902 hw->phy.addr = 1;
4903 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4904 &phy_data);
4905 if (ret_val)
4906 goto release;
4907 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4908 ret_val = hw->phy.ops.set_page(hw,
4909 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4910 if (ret_val)
4911 goto release;
4912 }
4913
4914 /* Single Collision Count */
4915 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4916 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4917 if (!ret_val)
4918 adapter->stats.scc += phy_data;
4919
4920 /* Excessive Collision Count */
4921 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4922 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4923 if (!ret_val)
4924 adapter->stats.ecol += phy_data;
4925
4926 /* Multiple Collision Count */
4927 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4928 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4929 if (!ret_val)
4930 adapter->stats.mcc += phy_data;
4931
4932 /* Late Collision Count */
4933 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4934 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4935 if (!ret_val)
4936 adapter->stats.latecol += phy_data;
4937
4938 /* Collision Count - also used for adaptive IFS */
4939 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4940 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4941 if (!ret_val)
4942 hw->mac.collision_delta = phy_data;
4943
4944 /* Defer Count */
4945 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4946 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4947 if (!ret_val)
4948 adapter->stats.dc += phy_data;
4949
4950 /* Transmit with no CRS */
4951 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4952 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4953 if (!ret_val)
4954 adapter->stats.tncrs += phy_data;
4955
4956 release:
4957 hw->phy.ops.release(hw);
4958 }
4959
4960 /**
4961 * e1000e_update_stats - Update the board statistics counters
4962 * @adapter: board private structure
4963 **/
e1000e_update_stats(struct e1000_adapter * adapter)4964 static void e1000e_update_stats(struct e1000_adapter *adapter)
4965 {
4966 struct net_device *netdev = adapter->netdev;
4967 struct e1000_hw *hw = &adapter->hw;
4968 struct pci_dev *pdev = adapter->pdev;
4969
4970 /* Prevent stats update while adapter is being reset, or if the pci
4971 * connection is down.
4972 */
4973 if (adapter->link_speed == 0)
4974 return;
4975 if (pci_channel_offline(pdev))
4976 return;
4977
4978 adapter->stats.crcerrs += er32(CRCERRS);
4979 adapter->stats.gprc += er32(GPRC);
4980 adapter->stats.gorc += er32(GORCL);
4981 er32(GORCH); /* Clear gorc */
4982 adapter->stats.bprc += er32(BPRC);
4983 adapter->stats.mprc += er32(MPRC);
4984 adapter->stats.roc += er32(ROC);
4985
4986 adapter->stats.mpc += er32(MPC);
4987
4988 /* Half-duplex statistics */
4989 if (adapter->link_duplex == HALF_DUPLEX) {
4990 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4991 e1000e_update_phy_stats(adapter);
4992 } else {
4993 adapter->stats.scc += er32(SCC);
4994 adapter->stats.ecol += er32(ECOL);
4995 adapter->stats.mcc += er32(MCC);
4996 adapter->stats.latecol += er32(LATECOL);
4997 adapter->stats.dc += er32(DC);
4998
4999 hw->mac.collision_delta = er32(COLC);
5000
5001 if ((hw->mac.type != e1000_82574) &&
5002 (hw->mac.type != e1000_82583))
5003 adapter->stats.tncrs += er32(TNCRS);
5004 }
5005 adapter->stats.colc += hw->mac.collision_delta;
5006 }
5007
5008 adapter->stats.xonrxc += er32(XONRXC);
5009 adapter->stats.xontxc += er32(XONTXC);
5010 adapter->stats.xoffrxc += er32(XOFFRXC);
5011 adapter->stats.xofftxc += er32(XOFFTXC);
5012 adapter->stats.gptc += er32(GPTC);
5013 adapter->stats.gotc += er32(GOTCL);
5014 er32(GOTCH); /* Clear gotc */
5015 adapter->stats.rnbc += er32(RNBC);
5016 adapter->stats.ruc += er32(RUC);
5017
5018 adapter->stats.mptc += er32(MPTC);
5019 adapter->stats.bptc += er32(BPTC);
5020
5021 /* used for adaptive IFS */
5022
5023 hw->mac.tx_packet_delta = er32(TPT);
5024 adapter->stats.tpt += hw->mac.tx_packet_delta;
5025
5026 adapter->stats.algnerrc += er32(ALGNERRC);
5027 adapter->stats.rxerrc += er32(RXERRC);
5028 adapter->stats.cexterr += er32(CEXTERR);
5029 adapter->stats.tsctc += er32(TSCTC);
5030 adapter->stats.tsctfc += er32(TSCTFC);
5031
5032 /* Fill out the OS statistics structure */
5033 netdev->stats.multicast = adapter->stats.mprc;
5034 netdev->stats.collisions = adapter->stats.colc;
5035
5036 /* Rx Errors */
5037
5038 /* RLEC on some newer hardware can be incorrect so build
5039 * our own version based on RUC and ROC
5040 */
5041 netdev->stats.rx_errors = adapter->stats.rxerrc +
5042 adapter->stats.crcerrs + adapter->stats.algnerrc +
5043 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5044 netdev->stats.rx_length_errors = adapter->stats.ruc +
5045 adapter->stats.roc;
5046 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5047 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
5048 netdev->stats.rx_missed_errors = adapter->stats.mpc;
5049
5050 /* Tx Errors */
5051 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5052 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
5053 netdev->stats.tx_window_errors = adapter->stats.latecol;
5054 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
5055
5056 /* Tx Dropped needs to be maintained elsewhere */
5057
5058 /* Management Stats */
5059 adapter->stats.mgptc += er32(MGTPTC);
5060 adapter->stats.mgprc += er32(MGTPRC);
5061 adapter->stats.mgpdc += er32(MGTPDC);
5062
5063 /* Correctable ECC Errors */
5064 if (hw->mac.type >= e1000_pch_lpt) {
5065 u32 pbeccsts = er32(PBECCSTS);
5066
5067 adapter->corr_errors +=
5068 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
5069 adapter->uncorr_errors +=
5070 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
5071 }
5072 }
5073
5074 /**
5075 * e1000_phy_read_status - Update the PHY register status snapshot
5076 * @adapter: board private structure
5077 **/
e1000_phy_read_status(struct e1000_adapter * adapter)5078 static void e1000_phy_read_status(struct e1000_adapter *adapter)
5079 {
5080 struct e1000_hw *hw = &adapter->hw;
5081 struct e1000_phy_regs *phy = &adapter->phy_regs;
5082
5083 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
5084 (er32(STATUS) & E1000_STATUS_LU) &&
5085 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
5086 int ret_val;
5087
5088 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
5089 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
5090 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
5091 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
5092 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
5093 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
5094 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
5095 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
5096 if (ret_val)
5097 e_warn("Error reading PHY register\n");
5098 } else {
5099 /* Do not read PHY registers if link is not up
5100 * Set values to typical power-on defaults
5101 */
5102 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
5103 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
5104 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
5105 BMSR_ERCAP);
5106 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
5107 ADVERTISE_ALL | ADVERTISE_CSMA);
5108 phy->lpa = 0;
5109 phy->expansion = EXPANSION_ENABLENPAGE;
5110 phy->ctrl1000 = ADVERTISE_1000FULL;
5111 phy->stat1000 = 0;
5112 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
5113 }
5114 }
5115
e1000_print_link_info(struct e1000_adapter * adapter)5116 static void e1000_print_link_info(struct e1000_adapter *adapter)
5117 {
5118 struct e1000_hw *hw = &adapter->hw;
5119 u32 ctrl = er32(CTRL);
5120
5121 /* Link status message must follow this format for user tools */
5122 netdev_info(adapter->netdev,
5123 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5124 adapter->link_speed,
5125 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
5126 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
5127 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5128 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
5129 }
5130
e1000e_has_link(struct e1000_adapter * adapter)5131 static bool e1000e_has_link(struct e1000_adapter *adapter)
5132 {
5133 struct e1000_hw *hw = &adapter->hw;
5134 bool link_active = false;
5135 s32 ret_val = 0;
5136
5137 /* get_link_status is set on LSC (link status) interrupt or
5138 * Rx sequence error interrupt. get_link_status will stay
5139 * true until the check_for_link establishes link
5140 * for copper adapters ONLY
5141 */
5142 switch (hw->phy.media_type) {
5143 case e1000_media_type_copper:
5144 if (hw->mac.get_link_status) {
5145 ret_val = hw->mac.ops.check_for_link(hw);
5146 link_active = !hw->mac.get_link_status;
5147 } else {
5148 link_active = true;
5149 }
5150 break;
5151 case e1000_media_type_fiber:
5152 ret_val = hw->mac.ops.check_for_link(hw);
5153 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5154 break;
5155 case e1000_media_type_internal_serdes:
5156 ret_val = hw->mac.ops.check_for_link(hw);
5157 link_active = hw->mac.serdes_has_link;
5158 break;
5159 default:
5160 case e1000_media_type_unknown:
5161 break;
5162 }
5163
5164 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5165 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5166 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5167 e_info("Gigabit has been disabled, downgrading speed\n");
5168 }
5169
5170 return link_active;
5171 }
5172
e1000e_enable_receives(struct e1000_adapter * adapter)5173 static void e1000e_enable_receives(struct e1000_adapter *adapter)
5174 {
5175 /* make sure the receive unit is started */
5176 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5177 (adapter->flags & FLAG_RESTART_NOW)) {
5178 struct e1000_hw *hw = &adapter->hw;
5179 u32 rctl = er32(RCTL);
5180
5181 ew32(RCTL, rctl | E1000_RCTL_EN);
5182 adapter->flags &= ~FLAG_RESTART_NOW;
5183 }
5184 }
5185
e1000e_check_82574_phy_workaround(struct e1000_adapter * adapter)5186 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5187 {
5188 struct e1000_hw *hw = &adapter->hw;
5189
5190 /* With 82574 controllers, PHY needs to be checked periodically
5191 * for hung state and reset, if two calls return true
5192 */
5193 if (e1000_check_phy_82574(hw))
5194 adapter->phy_hang_count++;
5195 else
5196 adapter->phy_hang_count = 0;
5197
5198 if (adapter->phy_hang_count > 1) {
5199 adapter->phy_hang_count = 0;
5200 e_dbg("PHY appears hung - resetting\n");
5201 schedule_work(&adapter->reset_task);
5202 }
5203 }
5204
5205 /**
5206 * e1000_watchdog - Timer Call-back
5207 * @t: pointer to timer_list containing private info adapter
5208 **/
e1000_watchdog(struct timer_list * t)5209 static void e1000_watchdog(struct timer_list *t)
5210 {
5211 struct e1000_adapter *adapter = timer_container_of(adapter, t,
5212 watchdog_timer);
5213
5214 /* Do the rest outside of interrupt context */
5215 schedule_work(&adapter->watchdog_task);
5216
5217 /* TODO: make this use queue_delayed_work() */
5218 }
5219
e1000_watchdog_task(struct work_struct * work)5220 static void e1000_watchdog_task(struct work_struct *work)
5221 {
5222 struct e1000_adapter *adapter = container_of(work,
5223 struct e1000_adapter,
5224 watchdog_task);
5225 struct net_device *netdev = adapter->netdev;
5226 struct e1000_mac_info *mac = &adapter->hw.mac;
5227 struct e1000_phy_info *phy = &adapter->hw.phy;
5228 struct e1000_ring *tx_ring = adapter->tx_ring;
5229 u32 dmoff_exit_timeout = 100, tries = 0;
5230 struct e1000_hw *hw = &adapter->hw;
5231 u32 link, tctl, pcim_state;
5232
5233 if (test_bit(__E1000_DOWN, &adapter->state))
5234 return;
5235
5236 link = e1000e_has_link(adapter);
5237 if ((netif_carrier_ok(netdev)) && link) {
5238 /* Cancel scheduled suspend requests. */
5239 pm_runtime_resume(netdev->dev.parent);
5240
5241 e1000e_enable_receives(adapter);
5242 goto link_up;
5243 }
5244
5245 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5246 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5247 e1000_update_mng_vlan(adapter);
5248
5249 if (link) {
5250 if (!netif_carrier_ok(netdev)) {
5251 bool txb2b = true;
5252
5253 /* Cancel scheduled suspend requests. */
5254 pm_runtime_resume(netdev->dev.parent);
5255
5256 /* Checking if MAC is in DMoff state*/
5257 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
5258 pcim_state = er32(STATUS);
5259 while (pcim_state & E1000_STATUS_PCIM_STATE) {
5260 if (tries++ == dmoff_exit_timeout) {
5261 e_dbg("Error in exiting dmoff\n");
5262 break;
5263 }
5264 usleep_range(10000, 20000);
5265 pcim_state = er32(STATUS);
5266
5267 /* Checking if MAC exited DMoff state */
5268 if (!(pcim_state & E1000_STATUS_PCIM_STATE))
5269 e1000_phy_hw_reset(&adapter->hw);
5270 }
5271 }
5272
5273 /* update snapshot of PHY registers on LSC */
5274 e1000_phy_read_status(adapter);
5275 mac->ops.get_link_up_info(&adapter->hw,
5276 &adapter->link_speed,
5277 &adapter->link_duplex);
5278 e1000_print_link_info(adapter);
5279
5280 /* check if SmartSpeed worked */
5281 e1000e_check_downshift(hw);
5282 if (phy->speed_downgraded)
5283 netdev_warn(netdev,
5284 "Link Speed was downgraded by SmartSpeed\n");
5285
5286 /* On supported PHYs, check for duplex mismatch only
5287 * if link has autonegotiated at 10/100 half
5288 */
5289 if ((hw->phy.type == e1000_phy_igp_3 ||
5290 hw->phy.type == e1000_phy_bm) &&
5291 hw->mac.autoneg &&
5292 (adapter->link_speed == SPEED_10 ||
5293 adapter->link_speed == SPEED_100) &&
5294 (adapter->link_duplex == HALF_DUPLEX)) {
5295 u16 autoneg_exp;
5296
5297 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
5298
5299 if (!(autoneg_exp & EXPANSION_NWAY))
5300 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5301 }
5302
5303 /* adjust timeout factor according to speed/duplex */
5304 adapter->tx_timeout_factor = 1;
5305 switch (adapter->link_speed) {
5306 case SPEED_10:
5307 txb2b = false;
5308 adapter->tx_timeout_factor = 16;
5309 break;
5310 case SPEED_100:
5311 txb2b = false;
5312 adapter->tx_timeout_factor = 10;
5313 break;
5314 }
5315
5316 /* workaround: re-program speed mode bit after
5317 * link-up event
5318 */
5319 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5320 !txb2b) {
5321 u32 tarc0;
5322
5323 tarc0 = er32(TARC(0));
5324 tarc0 &= ~SPEED_MODE_BIT;
5325 ew32(TARC(0), tarc0);
5326 }
5327
5328 /* enable transmits in the hardware, need to do this
5329 * after setting TARC(0)
5330 */
5331 tctl = er32(TCTL);
5332 tctl |= E1000_TCTL_EN;
5333 ew32(TCTL, tctl);
5334
5335 /* Perform any post-link-up configuration before
5336 * reporting link up.
5337 */
5338 if (phy->ops.cfg_on_link_up)
5339 phy->ops.cfg_on_link_up(hw);
5340
5341 netif_wake_queue(netdev);
5342 netif_carrier_on(netdev);
5343
5344 if (!test_bit(__E1000_DOWN, &adapter->state))
5345 mod_timer(&adapter->phy_info_timer,
5346 round_jiffies(jiffies + 2 * HZ));
5347 }
5348 } else {
5349 if (netif_carrier_ok(netdev)) {
5350 adapter->link_speed = 0;
5351 adapter->link_duplex = 0;
5352 /* Link status message must follow this format */
5353 netdev_info(netdev, "NIC Link is Down\n");
5354 netif_carrier_off(netdev);
5355 netif_stop_queue(netdev);
5356 if (!test_bit(__E1000_DOWN, &adapter->state))
5357 mod_timer(&adapter->phy_info_timer,
5358 round_jiffies(jiffies + 2 * HZ));
5359
5360 /* 8000ES2LAN requires a Rx packet buffer work-around
5361 * on link down event; reset the controller to flush
5362 * the Rx packet buffer.
5363 */
5364 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
5365 adapter->flags |= FLAG_RESTART_NOW;
5366 else
5367 pm_schedule_suspend(netdev->dev.parent,
5368 LINK_TIMEOUT);
5369 }
5370 }
5371
5372 link_up:
5373 spin_lock(&adapter->stats64_lock);
5374 e1000e_update_stats(adapter);
5375
5376 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5377 adapter->tpt_old = adapter->stats.tpt;
5378 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5379 adapter->colc_old = adapter->stats.colc;
5380
5381 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5382 adapter->gorc_old = adapter->stats.gorc;
5383 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5384 adapter->gotc_old = adapter->stats.gotc;
5385 spin_unlock(&adapter->stats64_lock);
5386
5387 /* If the link is lost the controller stops DMA, but
5388 * if there is queued Tx work it cannot be done. So
5389 * reset the controller to flush the Tx packet buffers.
5390 */
5391 if (!netif_carrier_ok(netdev) &&
5392 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5393 adapter->flags |= FLAG_RESTART_NOW;
5394
5395 /* If reset is necessary, do it outside of interrupt context. */
5396 if (adapter->flags & FLAG_RESTART_NOW) {
5397 schedule_work(&adapter->reset_task);
5398 /* return immediately since reset is imminent */
5399 return;
5400 }
5401
5402 e1000e_update_adaptive(&adapter->hw);
5403
5404 /* Simple mode for Interrupt Throttle Rate (ITR) */
5405 if (adapter->itr_setting == 4) {
5406 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5407 * Total asymmetrical Tx or Rx gets ITR=8000;
5408 * everyone else is between 2000-8000.
5409 */
5410 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5411 u32 dif = (adapter->gotc > adapter->gorc ?
5412 adapter->gotc - adapter->gorc :
5413 adapter->gorc - adapter->gotc) / 10000;
5414 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5415
5416 e1000e_write_itr(adapter, itr);
5417 }
5418
5419 /* Cause software interrupt to ensure Rx ring is cleaned */
5420 if (adapter->msix_entries)
5421 ew32(ICS, adapter->rx_ring->ims_val);
5422 else
5423 ew32(ICS, E1000_ICS_RXDMT0);
5424
5425 /* flush pending descriptors to memory before detecting Tx hang */
5426 e1000e_flush_descriptors(adapter);
5427
5428 /* Force detection of hung controller every watchdog period */
5429 adapter->detect_tx_hung = true;
5430
5431 /* With 82571 controllers, LAA may be overwritten due to controller
5432 * reset from the other port. Set the appropriate LAA in RAR[0]
5433 */
5434 if (e1000e_get_laa_state_82571(hw))
5435 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
5436
5437 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5438 e1000e_check_82574_phy_workaround(adapter);
5439
5440 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5441 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5442 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5443 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5444 er32(RXSTMPH);
5445 adapter->rx_hwtstamp_cleared++;
5446 } else {
5447 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5448 }
5449 }
5450
5451 /* Reset the timer */
5452 if (!test_bit(__E1000_DOWN, &adapter->state))
5453 mod_timer(&adapter->watchdog_timer,
5454 round_jiffies(jiffies + 2 * HZ));
5455 }
5456
5457 #define E1000_TX_FLAGS_CSUM 0x00000001
5458 #define E1000_TX_FLAGS_VLAN 0x00000002
5459 #define E1000_TX_FLAGS_TSO 0x00000004
5460 #define E1000_TX_FLAGS_IPV4 0x00000008
5461 #define E1000_TX_FLAGS_NO_FCS 0x00000010
5462 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5463 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5464 #define E1000_TX_FLAGS_VLAN_SHIFT 16
5465
e1000_tso(struct e1000_ring * tx_ring,struct sk_buff * skb,__be16 protocol)5466 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5467 __be16 protocol)
5468 {
5469 struct e1000_context_desc *context_desc;
5470 struct e1000_buffer *buffer_info;
5471 unsigned int i;
5472 u32 cmd_length = 0;
5473 u16 ipcse = 0, mss;
5474 u8 ipcss, ipcso, tucss, tucso, hdr_len;
5475 int err;
5476
5477 if (!skb_is_gso(skb))
5478 return 0;
5479
5480 err = skb_cow_head(skb, 0);
5481 if (err < 0)
5482 return err;
5483
5484 hdr_len = skb_tcp_all_headers(skb);
5485 mss = skb_shinfo(skb)->gso_size;
5486 if (protocol == htons(ETH_P_IP)) {
5487 struct iphdr *iph = ip_hdr(skb);
5488 iph->tot_len = 0;
5489 iph->check = 0;
5490 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5491 0, IPPROTO_TCP, 0);
5492 cmd_length = E1000_TXD_CMD_IP;
5493 ipcse = skb_transport_offset(skb) - 1;
5494 } else if (skb_is_gso_v6(skb)) {
5495 tcp_v6_gso_csum_prep(skb);
5496 ipcse = 0;
5497 }
5498 ipcss = skb_network_offset(skb);
5499 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5500 tucss = skb_transport_offset(skb);
5501 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5502
5503 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5504 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5505
5506 i = tx_ring->next_to_use;
5507 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5508 buffer_info = &tx_ring->buffer_info[i];
5509
5510 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5511 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5512 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5513 context_desc->upper_setup.tcp_fields.tucss = tucss;
5514 context_desc->upper_setup.tcp_fields.tucso = tucso;
5515 context_desc->upper_setup.tcp_fields.tucse = 0;
5516 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5517 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5518 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5519
5520 buffer_info->time_stamp = jiffies;
5521 buffer_info->next_to_watch = i;
5522
5523 i++;
5524 if (i == tx_ring->count)
5525 i = 0;
5526 tx_ring->next_to_use = i;
5527
5528 return 1;
5529 }
5530
e1000_tx_csum(struct e1000_ring * tx_ring,struct sk_buff * skb,__be16 protocol)5531 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5532 __be16 protocol)
5533 {
5534 struct e1000_adapter *adapter = tx_ring->adapter;
5535 struct e1000_context_desc *context_desc;
5536 struct e1000_buffer *buffer_info;
5537 unsigned int i;
5538 u8 css;
5539 u32 cmd_len = E1000_TXD_CMD_DEXT;
5540
5541 if (skb->ip_summed != CHECKSUM_PARTIAL)
5542 return false;
5543
5544 switch (protocol) {
5545 case cpu_to_be16(ETH_P_IP):
5546 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5547 cmd_len |= E1000_TXD_CMD_TCP;
5548 break;
5549 case cpu_to_be16(ETH_P_IPV6):
5550 /* XXX not handling all IPV6 headers */
5551 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5552 cmd_len |= E1000_TXD_CMD_TCP;
5553 break;
5554 default:
5555 if (unlikely(net_ratelimit()))
5556 e_warn("checksum_partial proto=%x!\n",
5557 be16_to_cpu(protocol));
5558 break;
5559 }
5560
5561 css = skb_checksum_start_offset(skb);
5562
5563 i = tx_ring->next_to_use;
5564 buffer_info = &tx_ring->buffer_info[i];
5565 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5566
5567 context_desc->lower_setup.ip_config = 0;
5568 context_desc->upper_setup.tcp_fields.tucss = css;
5569 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
5570 context_desc->upper_setup.tcp_fields.tucse = 0;
5571 context_desc->tcp_seg_setup.data = 0;
5572 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5573
5574 buffer_info->time_stamp = jiffies;
5575 buffer_info->next_to_watch = i;
5576
5577 i++;
5578 if (i == tx_ring->count)
5579 i = 0;
5580 tx_ring->next_to_use = i;
5581
5582 return true;
5583 }
5584
e1000_tx_map(struct e1000_ring * tx_ring,struct sk_buff * skb,unsigned int first,unsigned int max_per_txd,unsigned int nr_frags)5585 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5586 unsigned int first, unsigned int max_per_txd,
5587 unsigned int nr_frags)
5588 {
5589 struct e1000_adapter *adapter = tx_ring->adapter;
5590 struct pci_dev *pdev = adapter->pdev;
5591 struct e1000_buffer *buffer_info;
5592 unsigned int len = skb_headlen(skb);
5593 unsigned int offset = 0, size, count = 0, i;
5594 unsigned int f, bytecount, segs;
5595
5596 i = tx_ring->next_to_use;
5597
5598 while (len) {
5599 buffer_info = &tx_ring->buffer_info[i];
5600 size = min(len, max_per_txd);
5601
5602 buffer_info->length = size;
5603 buffer_info->time_stamp = jiffies;
5604 buffer_info->next_to_watch = i;
5605 buffer_info->dma = dma_map_single(&pdev->dev,
5606 skb->data + offset,
5607 size, DMA_TO_DEVICE);
5608 buffer_info->mapped_as_page = false;
5609 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5610 goto dma_error;
5611
5612 len -= size;
5613 offset += size;
5614 count++;
5615
5616 if (len) {
5617 i++;
5618 if (i == tx_ring->count)
5619 i = 0;
5620 }
5621 }
5622
5623 for (f = 0; f < nr_frags; f++) {
5624 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
5625
5626 len = skb_frag_size(frag);
5627 offset = 0;
5628
5629 while (len) {
5630 i++;
5631 if (i == tx_ring->count)
5632 i = 0;
5633
5634 buffer_info = &tx_ring->buffer_info[i];
5635 size = min(len, max_per_txd);
5636
5637 buffer_info->length = size;
5638 buffer_info->time_stamp = jiffies;
5639 buffer_info->next_to_watch = i;
5640 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5641 offset, size,
5642 DMA_TO_DEVICE);
5643 buffer_info->mapped_as_page = true;
5644 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5645 goto dma_error;
5646
5647 len -= size;
5648 offset += size;
5649 count++;
5650 }
5651 }
5652
5653 segs = skb_shinfo(skb)->gso_segs ? : 1;
5654 /* multiply data chunks by size of headers */
5655 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5656
5657 tx_ring->buffer_info[i].skb = skb;
5658 tx_ring->buffer_info[i].segs = segs;
5659 tx_ring->buffer_info[i].bytecount = bytecount;
5660 tx_ring->buffer_info[first].next_to_watch = i;
5661
5662 return count;
5663
5664 dma_error:
5665 dev_err(&pdev->dev, "Tx DMA map failed\n");
5666 buffer_info->dma = 0;
5667
5668 while (count--) {
5669 if (i == 0)
5670 i += tx_ring->count;
5671 i--;
5672 buffer_info = &tx_ring->buffer_info[i];
5673 e1000_put_txbuf(tx_ring, buffer_info, true);
5674 }
5675
5676 return 0;
5677 }
5678
e1000_tx_queue(struct e1000_ring * tx_ring,int tx_flags,int count)5679 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5680 {
5681 struct e1000_adapter *adapter = tx_ring->adapter;
5682 struct e1000_tx_desc *tx_desc = NULL;
5683 struct e1000_buffer *buffer_info;
5684 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5685 unsigned int i;
5686
5687 if (tx_flags & E1000_TX_FLAGS_TSO) {
5688 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5689 E1000_TXD_CMD_TSE;
5690 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5691
5692 if (tx_flags & E1000_TX_FLAGS_IPV4)
5693 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5694 }
5695
5696 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5697 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5698 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5699 }
5700
5701 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5702 txd_lower |= E1000_TXD_CMD_VLE;
5703 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5704 }
5705
5706 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5707 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5708
5709 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5710 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5711 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5712 }
5713
5714 i = tx_ring->next_to_use;
5715
5716 do {
5717 buffer_info = &tx_ring->buffer_info[i];
5718 tx_desc = E1000_TX_DESC(*tx_ring, i);
5719 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5720 tx_desc->lower.data = cpu_to_le32(txd_lower |
5721 buffer_info->length);
5722 tx_desc->upper.data = cpu_to_le32(txd_upper);
5723
5724 i++;
5725 if (i == tx_ring->count)
5726 i = 0;
5727 } while (--count > 0);
5728
5729 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5730
5731 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5732 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5733 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5734
5735 /* Force memory writes to complete before letting h/w
5736 * know there are new descriptors to fetch. (Only
5737 * applicable for weak-ordered memory model archs,
5738 * such as IA-64).
5739 */
5740 wmb();
5741
5742 tx_ring->next_to_use = i;
5743 }
5744
5745 #define MINIMUM_DHCP_PACKET_SIZE 282
e1000_transfer_dhcp_info(struct e1000_adapter * adapter,struct sk_buff * skb)5746 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5747 struct sk_buff *skb)
5748 {
5749 struct e1000_hw *hw = &adapter->hw;
5750 u16 length, offset;
5751
5752 if (skb_vlan_tag_present(skb) &&
5753 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5754 (adapter->hw.mng_cookie.status &
5755 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5756 return 0;
5757
5758 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5759 return 0;
5760
5761 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
5762 return 0;
5763
5764 {
5765 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
5766 struct udphdr *udp;
5767
5768 if (ip->protocol != IPPROTO_UDP)
5769 return 0;
5770
5771 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5772 if (ntohs(udp->dest) != 67)
5773 return 0;
5774
5775 offset = (u8 *)udp + 8 - skb->data;
5776 length = skb->len - offset;
5777 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5778 }
5779
5780 return 0;
5781 }
5782
__e1000_maybe_stop_tx(struct e1000_ring * tx_ring,int size)5783 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5784 {
5785 struct e1000_adapter *adapter = tx_ring->adapter;
5786
5787 netif_stop_queue(adapter->netdev);
5788 /* Herbert's original patch had:
5789 * smp_mb__after_netif_stop_queue();
5790 * but since that doesn't exist yet, just open code it.
5791 */
5792 smp_mb();
5793
5794 /* We need to check again in a case another CPU has just
5795 * made room available.
5796 */
5797 if (e1000_desc_unused(tx_ring) < size)
5798 return -EBUSY;
5799
5800 /* A reprieve! */
5801 netif_start_queue(adapter->netdev);
5802 ++adapter->restart_queue;
5803 return 0;
5804 }
5805
e1000_maybe_stop_tx(struct e1000_ring * tx_ring,int size)5806 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5807 {
5808 BUG_ON(size > tx_ring->count);
5809
5810 if (e1000_desc_unused(tx_ring) >= size)
5811 return 0;
5812 return __e1000_maybe_stop_tx(tx_ring, size);
5813 }
5814
e1000_xmit_frame(struct sk_buff * skb,struct net_device * netdev)5815 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5816 struct net_device *netdev)
5817 {
5818 struct e1000_adapter *adapter = netdev_priv(netdev);
5819 struct e1000_ring *tx_ring = adapter->tx_ring;
5820 unsigned int first;
5821 unsigned int tx_flags = 0;
5822 unsigned int len = skb_headlen(skb);
5823 unsigned int nr_frags;
5824 unsigned int mss;
5825 int count = 0;
5826 int tso;
5827 unsigned int f;
5828 __be16 protocol = vlan_get_protocol(skb);
5829
5830 if (test_bit(__E1000_DOWN, &adapter->state)) {
5831 dev_kfree_skb_any(skb);
5832 return NETDEV_TX_OK;
5833 }
5834
5835 if (skb->len <= 0) {
5836 dev_kfree_skb_any(skb);
5837 return NETDEV_TX_OK;
5838 }
5839
5840 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5841 * pad skb in order to meet this minimum size requirement
5842 */
5843 if (skb_put_padto(skb, 17))
5844 return NETDEV_TX_OK;
5845
5846 mss = skb_shinfo(skb)->gso_size;
5847 if (mss) {
5848 u8 hdr_len;
5849
5850 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5851 * points to just header, pull a few bytes of payload from
5852 * frags into skb->data
5853 */
5854 hdr_len = skb_tcp_all_headers(skb);
5855 /* we do this workaround for ES2LAN, but it is un-necessary,
5856 * avoiding it could save a lot of cycles
5857 */
5858 if (skb->data_len && (hdr_len == len)) {
5859 unsigned int pull_size;
5860
5861 pull_size = min_t(unsigned int, 4, skb->data_len);
5862 if (!__pskb_pull_tail(skb, pull_size)) {
5863 e_err("__pskb_pull_tail failed.\n");
5864 dev_kfree_skb_any(skb);
5865 return NETDEV_TX_OK;
5866 }
5867 len = skb_headlen(skb);
5868 }
5869 }
5870
5871 /* reserve a descriptor for the offload context */
5872 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5873 count++;
5874 count++;
5875
5876 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5877
5878 nr_frags = skb_shinfo(skb)->nr_frags;
5879 for (f = 0; f < nr_frags; f++)
5880 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5881 adapter->tx_fifo_limit);
5882
5883 if (adapter->hw.mac.tx_pkt_filtering)
5884 e1000_transfer_dhcp_info(adapter, skb);
5885
5886 /* need: count + 2 desc gap to keep tail from touching
5887 * head, otherwise try next time
5888 */
5889 if (e1000_maybe_stop_tx(tx_ring, count + 2))
5890 return NETDEV_TX_BUSY;
5891
5892 if (skb_vlan_tag_present(skb)) {
5893 tx_flags |= E1000_TX_FLAGS_VLAN;
5894 tx_flags |= (skb_vlan_tag_get(skb) <<
5895 E1000_TX_FLAGS_VLAN_SHIFT);
5896 }
5897
5898 first = tx_ring->next_to_use;
5899
5900 tso = e1000_tso(tx_ring, skb, protocol);
5901 if (tso < 0) {
5902 dev_kfree_skb_any(skb);
5903 return NETDEV_TX_OK;
5904 }
5905
5906 if (tso)
5907 tx_flags |= E1000_TX_FLAGS_TSO;
5908 else if (e1000_tx_csum(tx_ring, skb, protocol))
5909 tx_flags |= E1000_TX_FLAGS_CSUM;
5910
5911 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5912 * 82571 hardware supports TSO capabilities for IPv6 as well...
5913 * no longer assume, we must.
5914 */
5915 if (protocol == htons(ETH_P_IP))
5916 tx_flags |= E1000_TX_FLAGS_IPV4;
5917
5918 if (unlikely(skb->no_fcs))
5919 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5920
5921 /* if count is 0 then mapping error has occurred */
5922 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5923 nr_frags);
5924 if (count) {
5925 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5926 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
5927 if (!adapter->tx_hwtstamp_skb) {
5928 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5929 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5930 adapter->tx_hwtstamp_skb = skb_get(skb);
5931 adapter->tx_hwtstamp_start = jiffies;
5932 schedule_work(&adapter->tx_hwtstamp_work);
5933 } else {
5934 adapter->tx_hwtstamp_skipped++;
5935 }
5936 }
5937
5938 skb_tx_timestamp(skb);
5939
5940 netdev_sent_queue(netdev, skb->len);
5941 e1000_tx_queue(tx_ring, tx_flags, count);
5942 /* Make sure there is space in the ring for the next send. */
5943 e1000_maybe_stop_tx(tx_ring,
5944 ((MAX_SKB_FRAGS + 1) *
5945 DIV_ROUND_UP(PAGE_SIZE,
5946 adapter->tx_fifo_limit) + 4));
5947
5948 if (!netdev_xmit_more() ||
5949 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5950 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5951 e1000e_update_tdt_wa(tx_ring,
5952 tx_ring->next_to_use);
5953 else
5954 writel(tx_ring->next_to_use, tx_ring->tail);
5955 }
5956 } else {
5957 dev_kfree_skb_any(skb);
5958 tx_ring->buffer_info[first].time_stamp = 0;
5959 tx_ring->next_to_use = first;
5960 }
5961
5962 return NETDEV_TX_OK;
5963 }
5964
5965 /**
5966 * e1000_tx_timeout - Respond to a Tx Hang
5967 * @netdev: network interface device structure
5968 * @txqueue: index of the hung queue (unused)
5969 **/
e1000_tx_timeout(struct net_device * netdev,unsigned int __always_unused txqueue)5970 static void e1000_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
5971 {
5972 struct e1000_adapter *adapter = netdev_priv(netdev);
5973
5974 /* Do the reset outside of interrupt context */
5975 adapter->tx_timeout_count++;
5976 schedule_work(&adapter->reset_task);
5977 }
5978
e1000_reset_task(struct work_struct * work)5979 static void e1000_reset_task(struct work_struct *work)
5980 {
5981 struct e1000_adapter *adapter;
5982 adapter = container_of(work, struct e1000_adapter, reset_task);
5983
5984 rtnl_lock();
5985 /* don't run the task if already down */
5986 if (test_bit(__E1000_DOWN, &adapter->state)) {
5987 rtnl_unlock();
5988 return;
5989 }
5990
5991 if (!(adapter->flags & FLAG_RESTART_NOW)) {
5992 e1000e_dump(adapter);
5993 e_err("Reset adapter unexpectedly\n");
5994 }
5995 e1000e_reinit_locked(adapter);
5996 rtnl_unlock();
5997 }
5998
5999 /**
6000 * e1000e_get_stats64 - Get System Network Statistics
6001 * @netdev: network interface device structure
6002 * @stats: rtnl_link_stats64 pointer
6003 *
6004 * Returns the address of the device statistics structure.
6005 **/
e1000e_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)6006 void e1000e_get_stats64(struct net_device *netdev,
6007 struct rtnl_link_stats64 *stats)
6008 {
6009 struct e1000_adapter *adapter = netdev_priv(netdev);
6010
6011 spin_lock(&adapter->stats64_lock);
6012 e1000e_update_stats(adapter);
6013 /* Fill out the OS statistics structure */
6014 stats->rx_bytes = adapter->stats.gorc;
6015 stats->rx_packets = adapter->stats.gprc;
6016 stats->tx_bytes = adapter->stats.gotc;
6017 stats->tx_packets = adapter->stats.gptc;
6018 stats->multicast = adapter->stats.mprc;
6019 stats->collisions = adapter->stats.colc;
6020
6021 /* Rx Errors */
6022
6023 /* RLEC on some newer hardware can be incorrect so build
6024 * our own version based on RUC and ROC
6025 */
6026 stats->rx_errors = adapter->stats.rxerrc +
6027 adapter->stats.crcerrs + adapter->stats.algnerrc +
6028 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
6029 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
6030 stats->rx_crc_errors = adapter->stats.crcerrs;
6031 stats->rx_frame_errors = adapter->stats.algnerrc;
6032 stats->rx_missed_errors = adapter->stats.mpc;
6033
6034 /* Tx Errors */
6035 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
6036 stats->tx_aborted_errors = adapter->stats.ecol;
6037 stats->tx_window_errors = adapter->stats.latecol;
6038 stats->tx_carrier_errors = adapter->stats.tncrs;
6039
6040 /* Tx Dropped needs to be maintained elsewhere */
6041
6042 spin_unlock(&adapter->stats64_lock);
6043 }
6044
6045 /**
6046 * e1000_change_mtu - Change the Maximum Transfer Unit
6047 * @netdev: network interface device structure
6048 * @new_mtu: new value for maximum frame size
6049 *
6050 * Returns 0 on success, negative on failure
6051 **/
e1000_change_mtu(struct net_device * netdev,int new_mtu)6052 static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
6053 {
6054 struct e1000_adapter *adapter = netdev_priv(netdev);
6055 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6056
6057 /* Jumbo frame support */
6058 if ((new_mtu > ETH_DATA_LEN) &&
6059 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
6060 e_err("Jumbo Frames not supported.\n");
6061 return -EINVAL;
6062 }
6063
6064 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6065 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
6066 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
6067 (new_mtu > ETH_DATA_LEN)) {
6068 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
6069 return -EINVAL;
6070 }
6071
6072 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
6073 usleep_range(1000, 1100);
6074 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
6075 adapter->max_frame_size = max_frame;
6076 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6077 netdev->mtu, new_mtu);
6078 WRITE_ONCE(netdev->mtu, new_mtu);
6079
6080 pm_runtime_get_sync(netdev->dev.parent);
6081
6082 if (netif_running(netdev))
6083 e1000e_down(adapter, true);
6084
6085 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6086 * means we reserve 2 more, this pushes us to allocate from the next
6087 * larger slab size.
6088 * i.e. RXBUFFER_2048 --> size-4096 slab
6089 * However with the new *_jumbo_rx* routines, jumbo receives will use
6090 * fragmented skbs
6091 */
6092
6093 if (max_frame <= 2048)
6094 adapter->rx_buffer_len = 2048;
6095 else
6096 adapter->rx_buffer_len = 4096;
6097
6098 /* adjust allocation if LPE protects us, and we aren't using SBP */
6099 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
6100 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
6101
6102 if (netif_running(netdev))
6103 e1000e_up(adapter);
6104 else
6105 e1000e_reset(adapter);
6106
6107 pm_runtime_put_sync(netdev->dev.parent);
6108
6109 clear_bit(__E1000_RESETTING, &adapter->state);
6110
6111 return 0;
6112 }
6113
e1000_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)6114 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6115 {
6116 struct e1000_adapter *adapter = netdev_priv(netdev);
6117 struct mii_ioctl_data *data = if_mii(ifr);
6118
6119 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6120 return -EOPNOTSUPP;
6121
6122 switch (cmd) {
6123 case SIOCGMIIPHY:
6124 data->phy_id = adapter->hw.phy.addr;
6125 break;
6126 case SIOCGMIIREG:
6127 e1000_phy_read_status(adapter);
6128
6129 switch (data->reg_num & 0x1F) {
6130 case MII_BMCR:
6131 data->val_out = adapter->phy_regs.bmcr;
6132 break;
6133 case MII_BMSR:
6134 data->val_out = adapter->phy_regs.bmsr;
6135 break;
6136 case MII_PHYSID1:
6137 data->val_out = (adapter->hw.phy.id >> 16);
6138 break;
6139 case MII_PHYSID2:
6140 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6141 break;
6142 case MII_ADVERTISE:
6143 data->val_out = adapter->phy_regs.advertise;
6144 break;
6145 case MII_LPA:
6146 data->val_out = adapter->phy_regs.lpa;
6147 break;
6148 case MII_EXPANSION:
6149 data->val_out = adapter->phy_regs.expansion;
6150 break;
6151 case MII_CTRL1000:
6152 data->val_out = adapter->phy_regs.ctrl1000;
6153 break;
6154 case MII_STAT1000:
6155 data->val_out = adapter->phy_regs.stat1000;
6156 break;
6157 case MII_ESTATUS:
6158 data->val_out = adapter->phy_regs.estatus;
6159 break;
6160 default:
6161 return -EIO;
6162 }
6163 break;
6164 case SIOCSMIIREG:
6165 default:
6166 return -EOPNOTSUPP;
6167 }
6168 return 0;
6169 }
6170
6171 /**
6172 * e1000e_hwtstamp_set - control hardware time stamping
6173 * @netdev: network interface device structure
6174 * @config: timestamp configuration
6175 * @extack: netlink extended ACK report
6176 *
6177 * Outgoing time stamping can be enabled and disabled. Play nice and
6178 * disable it when requested, although it shouldn't cause any overhead
6179 * when no packet needs it. At most one packet in the queue may be
6180 * marked for time stamping, otherwise it would be impossible to tell
6181 * for sure to which packet the hardware time stamp belongs.
6182 *
6183 * Incoming time stamping has to be configured via the hardware filters.
6184 * Not all combinations are supported, in particular event type has to be
6185 * specified. Matching the kind of event packet is not supported, with the
6186 * exception of "all V2 events regardless of level 2 or 4".
6187 **/
e1000e_hwtstamp_set(struct net_device * netdev,struct kernel_hwtstamp_config * config,struct netlink_ext_ack * extack)6188 static int e1000e_hwtstamp_set(struct net_device *netdev,
6189 struct kernel_hwtstamp_config *config,
6190 struct netlink_ext_ack *extack)
6191 {
6192 struct e1000_adapter *adapter = netdev_priv(netdev);
6193 int ret_val;
6194
6195 ret_val = e1000e_config_hwtstamp(adapter, config, extack);
6196 if (ret_val)
6197 return ret_val;
6198
6199 switch (config->rx_filter) {
6200 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6201 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6202 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6203 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6204 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6205 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6206 /* With V2 type filters which specify a Sync or Delay Request,
6207 * Path Delay Request/Response messages are also time stamped
6208 * by hardware so notify the caller the requested packets plus
6209 * some others are time stamped.
6210 */
6211 config->rx_filter = HWTSTAMP_FILTER_SOME;
6212 break;
6213 default:
6214 break;
6215 }
6216
6217 return 0;
6218 }
6219
e1000e_hwtstamp_get(struct net_device * netdev,struct kernel_hwtstamp_config * kernel_config)6220 static int e1000e_hwtstamp_get(struct net_device *netdev,
6221 struct kernel_hwtstamp_config *kernel_config)
6222 {
6223 struct e1000_adapter *adapter = netdev_priv(netdev);
6224
6225 *kernel_config = adapter->hwtstamp_config;
6226
6227 return 0;
6228 }
6229
e1000_init_phy_wakeup(struct e1000_adapter * adapter,u32 wufc)6230 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6231 {
6232 struct e1000_hw *hw = &adapter->hw;
6233 u32 i, mac_reg, wuc;
6234 u16 phy_reg, wuc_enable;
6235 int retval;
6236
6237 /* copy MAC RARs to PHY RARs */
6238 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
6239
6240 retval = hw->phy.ops.acquire(hw);
6241 if (retval) {
6242 e_err("Could not acquire PHY\n");
6243 return retval;
6244 }
6245
6246 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6247 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6248 if (retval)
6249 goto release;
6250
6251 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6252 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6253 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
6254 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6255 (u16)(mac_reg & 0xFFFF));
6256 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6257 (u16)((mac_reg >> 16) & 0xFFFF));
6258 }
6259
6260 /* configure PHY Rx Control register */
6261 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
6262 mac_reg = er32(RCTL);
6263 if (mac_reg & E1000_RCTL_UPE)
6264 phy_reg |= BM_RCTL_UPE;
6265 if (mac_reg & E1000_RCTL_MPE)
6266 phy_reg |= BM_RCTL_MPE;
6267 phy_reg &= ~(BM_RCTL_MO_MASK);
6268 if (mac_reg & E1000_RCTL_MO_3)
6269 phy_reg |= (FIELD_GET(E1000_RCTL_MO_3, mac_reg)
6270 << BM_RCTL_MO_SHIFT);
6271 if (mac_reg & E1000_RCTL_BAM)
6272 phy_reg |= BM_RCTL_BAM;
6273 if (mac_reg & E1000_RCTL_PMCF)
6274 phy_reg |= BM_RCTL_PMCF;
6275 mac_reg = er32(CTRL);
6276 if (mac_reg & E1000_CTRL_RFCE)
6277 phy_reg |= BM_RCTL_RFCE;
6278 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
6279
6280 wuc = E1000_WUC_PME_EN;
6281 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6282 wuc |= E1000_WUC_APME;
6283
6284 /* enable PHY wakeup in MAC register */
6285 ew32(WUFC, wufc);
6286 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6287 E1000_WUC_PME_STATUS | wuc));
6288
6289 /* configure and enable PHY wakeup in PHY registers */
6290 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
6291 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
6292
6293 /* activate PHY wakeup */
6294 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6295 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6296 if (retval)
6297 e_err("Could not set PHY Host Wakeup bit\n");
6298 release:
6299 hw->phy.ops.release(hw);
6300
6301 return retval;
6302 }
6303
e1000e_flush_lpic(struct pci_dev * pdev)6304 static void e1000e_flush_lpic(struct pci_dev *pdev)
6305 {
6306 struct net_device *netdev = pci_get_drvdata(pdev);
6307 struct e1000_adapter *adapter = netdev_priv(netdev);
6308 struct e1000_hw *hw = &adapter->hw;
6309 u32 ret_val;
6310
6311 pm_runtime_get_sync(netdev->dev.parent);
6312
6313 ret_val = hw->phy.ops.acquire(hw);
6314 if (ret_val)
6315 goto fl_out;
6316
6317 pr_info("EEE TX LPI TIMER: %08X\n",
6318 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6319
6320 hw->phy.ops.release(hw);
6321
6322 fl_out:
6323 pm_runtime_put_sync(netdev->dev.parent);
6324 }
6325
6326 /* S0ix implementation */
e1000e_s0ix_entry_flow(struct e1000_adapter * adapter)6327 static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)
6328 {
6329 struct e1000_hw *hw = &adapter->hw;
6330 u32 mac_data;
6331 u16 phy_data;
6332
6333 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6334 hw->mac.type >= e1000_pch_adp) {
6335 /* Request ME configure the device for S0ix */
6336 mac_data = er32(H2ME);
6337 mac_data |= E1000_H2ME_START_DPG;
6338 mac_data &= ~E1000_H2ME_EXIT_DPG;
6339 trace_e1000e_trace_mac_register(mac_data);
6340 ew32(H2ME, mac_data);
6341 } else {
6342 /* Request driver configure the device to S0ix */
6343 /* Disable the periodic inband message,
6344 * don't request PCIe clock in K1 page770_17[10:9] = 10b
6345 */
6346 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6347 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ;
6348 phy_data |= BIT(10);
6349 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6350
6351 /* Make sure we don't exit K1 every time a new packet arrives
6352 * 772_29[5] = 1 CS_Mode_Stay_In_K1
6353 */
6354 e1e_rphy(hw, I217_CGFREG, &phy_data);
6355 phy_data |= BIT(5);
6356 e1e_wphy(hw, I217_CGFREG, phy_data);
6357
6358 /* Change the MAC/PHY interface to SMBus
6359 * Force the SMBus in PHY page769_23[0] = 1
6360 * Force the SMBus in MAC CTRL_EXT[11] = 1
6361 */
6362 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6363 phy_data |= CV_SMB_CTRL_FORCE_SMBUS;
6364 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6365 mac_data = er32(CTRL_EXT);
6366 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS;
6367 ew32(CTRL_EXT, mac_data);
6368
6369 /* DFT control: PHY bit: page769_20[0] = 1
6370 * page769_20[7] - PHY PLL stop
6371 * page769_20[8] - PHY go to the electrical idle
6372 * page769_20[9] - PHY serdes disable
6373 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
6374 */
6375 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data);
6376 phy_data |= BIT(0);
6377 phy_data |= BIT(7);
6378 phy_data |= BIT(8);
6379 phy_data |= BIT(9);
6380 e1e_wphy(hw, I82579_DFT_CTRL, phy_data);
6381
6382 mac_data = er32(EXTCNF_CTRL);
6383 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
6384 ew32(EXTCNF_CTRL, mac_data);
6385
6386 /* Disable disconnected cable conditioning for Power Gating */
6387 mac_data = er32(DPGFR);
6388 mac_data |= BIT(2);
6389 ew32(DPGFR, mac_data);
6390
6391 /* Enable the Dynamic Clock Gating in the DMA and MAC */
6392 mac_data = er32(CTRL_EXT);
6393 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;
6394 ew32(CTRL_EXT, mac_data);
6395 }
6396
6397 /* Enable the Dynamic Power Gating in the MAC */
6398 mac_data = er32(FEXTNVM7);
6399 mac_data |= BIT(22);
6400 ew32(FEXTNVM7, mac_data);
6401
6402 /* Don't wake from dynamic Power Gating with clock request */
6403 mac_data = er32(FEXTNVM12);
6404 mac_data |= BIT(12);
6405 ew32(FEXTNVM12, mac_data);
6406
6407 /* Ungate PGCB clock */
6408 mac_data = er32(FEXTNVM9);
6409 mac_data &= ~BIT(28);
6410 ew32(FEXTNVM9, mac_data);
6411
6412 /* Enable K1 off to enable mPHY Power Gating */
6413 mac_data = er32(FEXTNVM6);
6414 mac_data |= BIT(31);
6415 ew32(FEXTNVM6, mac_data);
6416
6417 /* Enable mPHY power gating for any link and speed */
6418 mac_data = er32(FEXTNVM8);
6419 mac_data |= BIT(9);
6420 ew32(FEXTNVM8, mac_data);
6421
6422 /* No MAC DPG gating SLP_S0 in modern standby
6423 * Switch the logic of the lanphypc to use PMC counter
6424 */
6425 mac_data = er32(FEXTNVM5);
6426 mac_data |= BIT(7);
6427 ew32(FEXTNVM5, mac_data);
6428
6429 /* Disable the time synchronization clock */
6430 mac_data = er32(FEXTNVM7);
6431 mac_data |= BIT(31);
6432 mac_data &= ~BIT(0);
6433 ew32(FEXTNVM7, mac_data);
6434
6435 /* Dynamic Power Gating Enable */
6436 mac_data = er32(CTRL_EXT);
6437 mac_data |= BIT(3);
6438 ew32(CTRL_EXT, mac_data);
6439
6440 /* Check MAC Tx/Rx packet buffer pointers.
6441 * Reset MAC Tx/Rx packet buffer pointers to suppress any
6442 * pending traffic indication that would prevent power gating.
6443 */
6444 mac_data = er32(TDFH);
6445 if (mac_data)
6446 ew32(TDFH, 0);
6447 mac_data = er32(TDFT);
6448 if (mac_data)
6449 ew32(TDFT, 0);
6450 mac_data = er32(TDFHS);
6451 if (mac_data)
6452 ew32(TDFHS, 0);
6453 mac_data = er32(TDFTS);
6454 if (mac_data)
6455 ew32(TDFTS, 0);
6456 mac_data = er32(TDFPC);
6457 if (mac_data)
6458 ew32(TDFPC, 0);
6459 mac_data = er32(RDFH);
6460 if (mac_data)
6461 ew32(RDFH, 0);
6462 mac_data = er32(RDFT);
6463 if (mac_data)
6464 ew32(RDFT, 0);
6465 mac_data = er32(RDFHS);
6466 if (mac_data)
6467 ew32(RDFHS, 0);
6468 mac_data = er32(RDFTS);
6469 if (mac_data)
6470 ew32(RDFTS, 0);
6471 mac_data = er32(RDFPC);
6472 if (mac_data)
6473 ew32(RDFPC, 0);
6474 }
6475
e1000e_s0ix_exit_flow(struct e1000_adapter * adapter)6476 static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)
6477 {
6478 struct e1000_hw *hw = &adapter->hw;
6479 bool firmware_bug = false;
6480 u32 mac_data;
6481 u16 phy_data;
6482 u32 i = 0;
6483
6484 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6485 hw->mac.type >= e1000_pch_adp) {
6486 /* Keep the GPT clock enabled for CSME */
6487 mac_data = er32(FEXTNVM);
6488 mac_data |= BIT(3);
6489 ew32(FEXTNVM, mac_data);
6490 /* Request ME unconfigure the device from S0ix */
6491 mac_data = er32(H2ME);
6492 mac_data &= ~E1000_H2ME_START_DPG;
6493 mac_data |= E1000_H2ME_EXIT_DPG;
6494 trace_e1000e_trace_mac_register(mac_data);
6495 ew32(H2ME, mac_data);
6496
6497 /* Poll up to 2.5 seconds for ME to unconfigure DPG.
6498 * If this takes more than 1 second, show a warning indicating a
6499 * firmware bug
6500 */
6501 while (!(er32(EXFWSM) & E1000_EXFWSM_DPG_EXIT_DONE)) {
6502 if (i > 100 && !firmware_bug)
6503 firmware_bug = true;
6504
6505 if (i++ == 250) {
6506 e_dbg("Timeout (firmware bug): %d msec\n",
6507 i * 10);
6508 break;
6509 }
6510
6511 usleep_range(10000, 11000);
6512 }
6513 if (firmware_bug)
6514 e_warn("DPG_EXIT_DONE took %d msec. This is a firmware bug\n",
6515 i * 10);
6516 else
6517 e_dbg("DPG_EXIT_DONE cleared after %d msec\n", i * 10);
6518 } else {
6519 /* Request driver unconfigure the device from S0ix */
6520
6521 /* Cancel disable disconnected cable conditioning
6522 * for Power Gating
6523 */
6524 mac_data = er32(DPGFR);
6525 mac_data &= ~BIT(2);
6526 ew32(DPGFR, mac_data);
6527
6528 /* Disable the Dynamic Clock Gating in the DMA and MAC */
6529 mac_data = er32(CTRL_EXT);
6530 mac_data &= 0xFFF7FFFF;
6531 ew32(CTRL_EXT, mac_data);
6532
6533 /* Enable the periodic inband message,
6534 * Request PCIe clock in K1 page770_17[10:9] =01b
6535 */
6536 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6537 phy_data &= 0xFBFF;
6538 phy_data |= HV_PM_CTRL_K1_CLK_REQ;
6539 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6540
6541 /* Return back configuration
6542 * 772_29[5] = 0 CS_Mode_Stay_In_K1
6543 */
6544 e1e_rphy(hw, I217_CGFREG, &phy_data);
6545 phy_data &= 0xFFDF;
6546 e1e_wphy(hw, I217_CGFREG, phy_data);
6547
6548 /* Change the MAC/PHY interface to Kumeran
6549 * Unforce the SMBus in PHY page769_23[0] = 0
6550 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
6551 */
6552 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6553 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS;
6554 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6555 mac_data = er32(CTRL_EXT);
6556 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS;
6557 ew32(CTRL_EXT, mac_data);
6558 }
6559
6560 /* Disable Dynamic Power Gating */
6561 mac_data = er32(CTRL_EXT);
6562 mac_data &= 0xFFFFFFF7;
6563 ew32(CTRL_EXT, mac_data);
6564
6565 /* Enable the time synchronization clock */
6566 mac_data = er32(FEXTNVM7);
6567 mac_data &= ~BIT(31);
6568 mac_data |= BIT(0);
6569 ew32(FEXTNVM7, mac_data);
6570
6571 /* Disable the Dynamic Power Gating in the MAC */
6572 mac_data = er32(FEXTNVM7);
6573 mac_data &= 0xFFBFFFFF;
6574 ew32(FEXTNVM7, mac_data);
6575
6576 /* Disable mPHY power gating for any link and speed */
6577 mac_data = er32(FEXTNVM8);
6578 mac_data &= ~BIT(9);
6579 ew32(FEXTNVM8, mac_data);
6580
6581 /* Disable K1 off */
6582 mac_data = er32(FEXTNVM6);
6583 mac_data &= ~BIT(31);
6584 ew32(FEXTNVM6, mac_data);
6585
6586 /* Disable Ungate PGCB clock */
6587 mac_data = er32(FEXTNVM9);
6588 mac_data |= BIT(28);
6589 ew32(FEXTNVM9, mac_data);
6590
6591 /* Cancel not waking from dynamic
6592 * Power Gating with clock request
6593 */
6594 mac_data = er32(FEXTNVM12);
6595 mac_data &= ~BIT(12);
6596 ew32(FEXTNVM12, mac_data);
6597
6598 /* Revert the lanphypc logic to use the internal Gbe counter
6599 * and not the PMC counter
6600 */
6601 mac_data = er32(FEXTNVM5);
6602 mac_data &= 0xFFFFFF7F;
6603 ew32(FEXTNVM5, mac_data);
6604 }
6605
e1000e_pm_freeze(struct device * dev)6606 static int e1000e_pm_freeze(struct device *dev)
6607 {
6608 struct net_device *netdev = dev_get_drvdata(dev);
6609 struct e1000_adapter *adapter = netdev_priv(netdev);
6610 bool present;
6611
6612 rtnl_lock();
6613
6614 present = netif_device_present(netdev);
6615 netif_device_detach(netdev);
6616
6617 if (present && netif_running(netdev)) {
6618 int count = E1000_CHECK_RESET_COUNT;
6619
6620 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6621 usleep_range(10000, 11000);
6622
6623 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6624
6625 /* Quiesce the device without resetting the hardware */
6626 e1000e_down(adapter, false);
6627 e1000_free_irq(adapter);
6628 }
6629 rtnl_unlock();
6630
6631 e1000e_reset_interrupt_capability(adapter);
6632
6633 /* Allow time for pending master requests to run */
6634 e1000e_disable_pcie_master(&adapter->hw);
6635
6636 return 0;
6637 }
6638
__e1000_shutdown(struct pci_dev * pdev,bool runtime)6639 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6640 {
6641 struct net_device *netdev = pci_get_drvdata(pdev);
6642 struct e1000_adapter *adapter = netdev_priv(netdev);
6643 struct e1000_hw *hw = &adapter->hw;
6644 u32 ctrl, ctrl_ext, rctl, status, wufc;
6645 int retval = 0;
6646
6647 /* Runtime suspend should only enable wakeup for link changes */
6648 if (runtime)
6649 wufc = E1000_WUFC_LNKC;
6650 else if (device_may_wakeup(&pdev->dev))
6651 wufc = adapter->wol;
6652 else
6653 wufc = 0;
6654
6655 status = er32(STATUS);
6656 if (status & E1000_STATUS_LU)
6657 wufc &= ~E1000_WUFC_LNKC;
6658
6659 if (wufc) {
6660 e1000_setup_rctl(adapter);
6661 e1000e_set_rx_mode(netdev);
6662
6663 /* turn on all-multi mode if wake on multicast is enabled */
6664 if (wufc & E1000_WUFC_MC) {
6665 rctl = er32(RCTL);
6666 rctl |= E1000_RCTL_MPE;
6667 ew32(RCTL, rctl);
6668 }
6669
6670 ctrl = er32(CTRL);
6671 ctrl |= E1000_CTRL_ADVD3WUC;
6672 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6673 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
6674 ew32(CTRL, ctrl);
6675
6676 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6677 adapter->hw.phy.media_type ==
6678 e1000_media_type_internal_serdes) {
6679 /* keep the laser running in D3 */
6680 ctrl_ext = er32(CTRL_EXT);
6681 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
6682 ew32(CTRL_EXT, ctrl_ext);
6683 }
6684
6685 if (!runtime)
6686 e1000e_power_up_phy(adapter);
6687
6688 if (adapter->flags & FLAG_IS_ICH)
6689 e1000_suspend_workarounds_ich8lan(&adapter->hw);
6690
6691 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6692 /* enable wakeup by the PHY */
6693 retval = e1000_init_phy_wakeup(adapter, wufc);
6694 if (retval) {
6695 e_err("Failed to enable wakeup\n");
6696 goto skip_phy_configurations;
6697 }
6698 } else {
6699 /* enable wakeup by the MAC */
6700 ew32(WUFC, wufc);
6701 ew32(WUC, E1000_WUC_PME_EN);
6702 }
6703 } else {
6704 ew32(WUC, 0);
6705 ew32(WUFC, 0);
6706
6707 e1000_power_down_phy(adapter);
6708 }
6709
6710 if (adapter->hw.phy.type == e1000_phy_igp_3) {
6711 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6712 } else if (hw->mac.type >= e1000_pch_lpt) {
6713 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) {
6714 /* ULP does not support wake from unicast, multicast
6715 * or broadcast.
6716 */
6717 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6718 if (retval) {
6719 e_err("Failed to enable ULP\n");
6720 goto skip_phy_configurations;
6721 }
6722 }
6723 }
6724
6725 /* Ensure that the appropriate bits are set in LPI_CTRL
6726 * for EEE in Sx
6727 */
6728 if ((hw->phy.type >= e1000_phy_i217) &&
6729 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6730 u16 lpi_ctrl = 0;
6731
6732 retval = hw->phy.ops.acquire(hw);
6733 if (!retval) {
6734 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6735 &lpi_ctrl);
6736 if (!retval) {
6737 if (adapter->eee_advert &
6738 hw->dev_spec.ich8lan.eee_lp_ability &
6739 I82579_EEE_100_SUPPORTED)
6740 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6741 if (adapter->eee_advert &
6742 hw->dev_spec.ich8lan.eee_lp_ability &
6743 I82579_EEE_1000_SUPPORTED)
6744 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6745
6746 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6747 lpi_ctrl);
6748 }
6749 }
6750 hw->phy.ops.release(hw);
6751 }
6752
6753 skip_phy_configurations:
6754 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6755 * would have already happened in close and is redundant.
6756 */
6757 e1000e_release_hw_control(adapter);
6758
6759 pci_clear_master(pdev);
6760
6761 /* The pci-e switch on some quad port adapters will report a
6762 * correctable error when the MAC transitions from D0 to D3. To
6763 * prevent this we need to mask off the correctable errors on the
6764 * downstream port of the pci-e switch.
6765 *
6766 * We don't have the associated upstream bridge while assigning
6767 * the PCI device into guest. For example, the KVM on power is
6768 * one of the cases.
6769 */
6770 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6771 struct pci_dev *us_dev = pdev->bus->self;
6772 u16 devctl;
6773
6774 if (!us_dev)
6775 return 0;
6776
6777 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6778 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6779 (devctl & ~PCI_EXP_DEVCTL_CERE));
6780
6781 pci_save_state(pdev);
6782 pci_prepare_to_sleep(pdev);
6783
6784 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
6785 }
6786
6787 return 0;
6788 }
6789
6790 /**
6791 * __e1000e_disable_aspm - Disable ASPM states
6792 * @pdev: pointer to PCI device struct
6793 * @state: bit-mask of ASPM states to disable
6794 * @locked: indication if this context holds pci_bus_sem locked.
6795 *
6796 * Some devices *must* have certain ASPM states disabled per hardware errata.
6797 **/
__e1000e_disable_aspm(struct pci_dev * pdev,u16 state,int locked)6798 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6799 {
6800 struct pci_dev *parent = pdev->bus->self;
6801 u16 aspm_dis_mask = 0;
6802 u16 pdev_aspmc, parent_aspmc;
6803
6804 switch (state) {
6805 case PCIE_LINK_STATE_L0S:
6806 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6807 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6808 fallthrough; /* can't have L1 without L0s */
6809 case PCIE_LINK_STATE_L1:
6810 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6811 break;
6812 default:
6813 return;
6814 }
6815
6816 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6817 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6818
6819 if (parent) {
6820 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6821 &parent_aspmc);
6822 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6823 }
6824
6825 /* Nothing to do if the ASPM states to be disabled already are */
6826 if (!(pdev_aspmc & aspm_dis_mask) &&
6827 (!parent || !(parent_aspmc & aspm_dis_mask)))
6828 return;
6829
6830 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6831 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6832 "L0s" : "",
6833 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6834 "L1" : "");
6835
6836 #ifdef CONFIG_PCIEASPM
6837 if (locked)
6838 pci_disable_link_state_locked(pdev, state);
6839 else
6840 pci_disable_link_state(pdev, state);
6841
6842 /* Double-check ASPM control. If not disabled by the above, the
6843 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6844 * not enabled); override by writing PCI config space directly.
6845 */
6846 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6847 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6848
6849 if (!(aspm_dis_mask & pdev_aspmc))
6850 return;
6851 #endif
6852
6853 /* Both device and parent should have the same ASPM setting.
6854 * Disable ASPM in downstream component first and then upstream.
6855 */
6856 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6857
6858 if (parent)
6859 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6860 aspm_dis_mask);
6861 }
6862
6863 /**
6864 * e1000e_disable_aspm - Disable ASPM states.
6865 * @pdev: pointer to PCI device struct
6866 * @state: bit-mask of ASPM states to disable
6867 *
6868 * This function acquires the pci_bus_sem!
6869 * Some devices *must* have certain ASPM states disabled per hardware errata.
6870 **/
e1000e_disable_aspm(struct pci_dev * pdev,u16 state)6871 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6872 {
6873 __e1000e_disable_aspm(pdev, state, 0);
6874 }
6875
6876 /**
6877 * e1000e_disable_aspm_locked - Disable ASPM states.
6878 * @pdev: pointer to PCI device struct
6879 * @state: bit-mask of ASPM states to disable
6880 *
6881 * This function must be called with pci_bus_sem acquired!
6882 * Some devices *must* have certain ASPM states disabled per hardware errata.
6883 **/
e1000e_disable_aspm_locked(struct pci_dev * pdev,u16 state)6884 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6885 {
6886 __e1000e_disable_aspm(pdev, state, 1);
6887 }
6888
e1000e_pm_thaw(struct device * dev)6889 static int e1000e_pm_thaw(struct device *dev)
6890 {
6891 struct net_device *netdev = dev_get_drvdata(dev);
6892 struct e1000_adapter *adapter = netdev_priv(netdev);
6893 int rc = 0;
6894
6895 e1000e_set_interrupt_capability(adapter);
6896
6897 rtnl_lock();
6898 if (netif_running(netdev)) {
6899 rc = e1000_request_irq(adapter);
6900 if (rc)
6901 goto err_irq;
6902
6903 e1000e_up(adapter);
6904 }
6905
6906 netif_device_attach(netdev);
6907 err_irq:
6908 rtnl_unlock();
6909
6910 return rc;
6911 }
6912
__e1000_resume(struct pci_dev * pdev)6913 static int __e1000_resume(struct pci_dev *pdev)
6914 {
6915 struct net_device *netdev = pci_get_drvdata(pdev);
6916 struct e1000_adapter *adapter = netdev_priv(netdev);
6917 struct e1000_hw *hw = &adapter->hw;
6918 u16 aspm_disable_flag = 0;
6919
6920 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6921 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6922 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6923 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6924 if (aspm_disable_flag)
6925 e1000e_disable_aspm(pdev, aspm_disable_flag);
6926
6927 pci_set_master(pdev);
6928
6929 if (hw->mac.type >= e1000_pch2lan)
6930 e1000_resume_workarounds_pchlan(&adapter->hw);
6931
6932 e1000e_power_up_phy(adapter);
6933
6934 /* report the system wakeup cause from S3/S4 */
6935 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6936 u16 phy_data;
6937
6938 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6939 if (phy_data) {
6940 e_info("PHY Wakeup cause - %s\n",
6941 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6942 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6943 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6944 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6945 phy_data & E1000_WUS_LNKC ?
6946 "Link Status Change" : "other");
6947 }
6948 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6949 } else {
6950 u32 wus = er32(WUS);
6951
6952 if (wus) {
6953 e_info("MAC Wakeup cause - %s\n",
6954 wus & E1000_WUS_EX ? "Unicast Packet" :
6955 wus & E1000_WUS_MC ? "Multicast Packet" :
6956 wus & E1000_WUS_BC ? "Broadcast Packet" :
6957 wus & E1000_WUS_MAG ? "Magic Packet" :
6958 wus & E1000_WUS_LNKC ? "Link Status Change" :
6959 "other");
6960 }
6961 ew32(WUS, ~0);
6962 }
6963
6964 e1000e_reset(adapter);
6965
6966 e1000_init_manageability_pt(adapter);
6967
6968 /* If the controller has AMT, do not set DRV_LOAD until the interface
6969 * is up. For all other cases, let the f/w know that the h/w is now
6970 * under the control of the driver.
6971 */
6972 if (!(adapter->flags & FLAG_HAS_AMT))
6973 e1000e_get_hw_control(adapter);
6974
6975 return 0;
6976 }
6977
e1000e_pm_prepare(struct device * dev)6978 static int e1000e_pm_prepare(struct device *dev)
6979 {
6980 return pm_runtime_suspended(dev) &&
6981 pm_suspend_via_firmware();
6982 }
6983
e1000e_pm_suspend(struct device * dev)6984 static int e1000e_pm_suspend(struct device *dev)
6985 {
6986 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6987 struct e1000_adapter *adapter = netdev_priv(netdev);
6988 struct pci_dev *pdev = to_pci_dev(dev);
6989 int rc;
6990
6991 e1000e_flush_lpic(pdev);
6992
6993 e1000e_pm_freeze(dev);
6994
6995 rc = __e1000_shutdown(pdev, false);
6996 if (!rc) {
6997 /* Introduce S0ix implementation */
6998 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
6999 e1000e_s0ix_entry_flow(adapter);
7000 }
7001
7002 return 0;
7003 }
7004
e1000e_pm_resume(struct device * dev)7005 static int e1000e_pm_resume(struct device *dev)
7006 {
7007 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
7008 struct e1000_adapter *adapter = netdev_priv(netdev);
7009 struct pci_dev *pdev = to_pci_dev(dev);
7010 int rc;
7011
7012 /* Introduce S0ix implementation */
7013 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
7014 e1000e_s0ix_exit_flow(adapter);
7015
7016 rc = __e1000_resume(pdev);
7017 if (rc)
7018 return rc;
7019
7020 return e1000e_pm_thaw(dev);
7021 }
7022
e1000e_pm_runtime_idle(struct device * dev)7023 static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev)
7024 {
7025 struct net_device *netdev = dev_get_drvdata(dev);
7026 struct e1000_adapter *adapter = netdev_priv(netdev);
7027 u16 eee_lp;
7028
7029 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
7030
7031 if (!e1000e_has_link(adapter)) {
7032 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
7033 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
7034 }
7035
7036 return -EBUSY;
7037 }
7038
e1000e_pm_runtime_resume(struct device * dev)7039 static int e1000e_pm_runtime_resume(struct device *dev)
7040 {
7041 struct pci_dev *pdev = to_pci_dev(dev);
7042 struct net_device *netdev = pci_get_drvdata(pdev);
7043 struct e1000_adapter *adapter = netdev_priv(netdev);
7044 int rc;
7045
7046 pdev->pme_poll = true;
7047
7048 rc = __e1000_resume(pdev);
7049 if (rc)
7050 return rc;
7051
7052 if (netdev->flags & IFF_UP)
7053 e1000e_up(adapter);
7054
7055 return rc;
7056 }
7057
e1000e_pm_runtime_suspend(struct device * dev)7058 static int e1000e_pm_runtime_suspend(struct device *dev)
7059 {
7060 struct pci_dev *pdev = to_pci_dev(dev);
7061 struct net_device *netdev = pci_get_drvdata(pdev);
7062 struct e1000_adapter *adapter = netdev_priv(netdev);
7063
7064 if (netdev->flags & IFF_UP) {
7065 int count = E1000_CHECK_RESET_COUNT;
7066
7067 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
7068 usleep_range(10000, 11000);
7069
7070 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
7071
7072 /* Down the device without resetting the hardware */
7073 e1000e_down(adapter, false);
7074 }
7075
7076 if (__e1000_shutdown(pdev, true)) {
7077 e1000e_pm_runtime_resume(dev);
7078 return -EBUSY;
7079 }
7080
7081 return 0;
7082 }
7083
e1000_shutdown(struct pci_dev * pdev)7084 static void e1000_shutdown(struct pci_dev *pdev)
7085 {
7086 e1000e_flush_lpic(pdev);
7087
7088 e1000e_pm_freeze(&pdev->dev);
7089
7090 __e1000_shutdown(pdev, false);
7091 }
7092
7093 #ifdef CONFIG_NET_POLL_CONTROLLER
7094
e1000_intr_msix(int __always_unused irq,void * data)7095 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
7096 {
7097 struct net_device *netdev = data;
7098 struct e1000_adapter *adapter = netdev_priv(netdev);
7099
7100 if (adapter->msix_entries) {
7101 int vector, msix_irq;
7102
7103 vector = 0;
7104 msix_irq = adapter->msix_entries[vector].vector;
7105 if (disable_hardirq(msix_irq))
7106 e1000_intr_msix_rx(msix_irq, netdev);
7107 enable_irq(msix_irq);
7108
7109 vector++;
7110 msix_irq = adapter->msix_entries[vector].vector;
7111 if (disable_hardirq(msix_irq))
7112 e1000_intr_msix_tx(msix_irq, netdev);
7113 enable_irq(msix_irq);
7114
7115 vector++;
7116 msix_irq = adapter->msix_entries[vector].vector;
7117 if (disable_hardirq(msix_irq))
7118 e1000_msix_other(msix_irq, netdev);
7119 enable_irq(msix_irq);
7120 }
7121
7122 return IRQ_HANDLED;
7123 }
7124
7125 /**
7126 * e1000_netpoll
7127 * @netdev: network interface device structure
7128 *
7129 * Polling 'interrupt' - used by things like netconsole to send skbs
7130 * without having to re-enable interrupts. It's not called while
7131 * the interrupt routine is executing.
7132 */
e1000_netpoll(struct net_device * netdev)7133 static void e1000_netpoll(struct net_device *netdev)
7134 {
7135 struct e1000_adapter *adapter = netdev_priv(netdev);
7136
7137 switch (adapter->int_mode) {
7138 case E1000E_INT_MODE_MSIX:
7139 e1000_intr_msix(adapter->pdev->irq, netdev);
7140 break;
7141 case E1000E_INT_MODE_MSI:
7142 if (disable_hardirq(adapter->pdev->irq))
7143 e1000_intr_msi(adapter->pdev->irq, netdev);
7144 enable_irq(adapter->pdev->irq);
7145 break;
7146 default: /* E1000E_INT_MODE_LEGACY */
7147 if (disable_hardirq(adapter->pdev->irq))
7148 e1000_intr(adapter->pdev->irq, netdev);
7149 enable_irq(adapter->pdev->irq);
7150 break;
7151 }
7152 }
7153 #endif
7154
7155 /**
7156 * e1000_io_error_detected - called when PCI error is detected
7157 * @pdev: Pointer to PCI device
7158 * @state: The current pci connection state
7159 *
7160 * This function is called after a PCI bus error affecting
7161 * this device has been detected.
7162 */
e1000_io_error_detected(struct pci_dev * pdev,pci_channel_state_t state)7163 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
7164 pci_channel_state_t state)
7165 {
7166 e1000e_pm_freeze(&pdev->dev);
7167
7168 if (state == pci_channel_io_perm_failure)
7169 return PCI_ERS_RESULT_DISCONNECT;
7170
7171 pci_disable_device(pdev);
7172
7173 /* Request a slot reset. */
7174 return PCI_ERS_RESULT_NEED_RESET;
7175 }
7176
7177 /**
7178 * e1000_io_slot_reset - called after the pci bus has been reset.
7179 * @pdev: Pointer to PCI device
7180 *
7181 * Restart the card from scratch, as if from a cold-boot. Implementation
7182 * resembles the first-half of the e1000e_pm_resume routine.
7183 */
e1000_io_slot_reset(struct pci_dev * pdev)7184 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
7185 {
7186 struct net_device *netdev = pci_get_drvdata(pdev);
7187 struct e1000_adapter *adapter = netdev_priv(netdev);
7188 struct e1000_hw *hw = &adapter->hw;
7189 u16 aspm_disable_flag = 0;
7190 int err;
7191 pci_ers_result_t result;
7192
7193 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
7194 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7195 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
7196 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7197 if (aspm_disable_flag)
7198 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
7199
7200 err = pci_enable_device_mem(pdev);
7201 if (err) {
7202 dev_err(&pdev->dev,
7203 "Cannot re-enable PCI device after reset.\n");
7204 result = PCI_ERS_RESULT_DISCONNECT;
7205 } else {
7206 pci_restore_state(pdev);
7207 pci_set_master(pdev);
7208
7209 pci_enable_wake(pdev, PCI_D3hot, 0);
7210 pci_enable_wake(pdev, PCI_D3cold, 0);
7211
7212 e1000e_reset(adapter);
7213 ew32(WUS, ~0);
7214 result = PCI_ERS_RESULT_RECOVERED;
7215 }
7216
7217 return result;
7218 }
7219
7220 /**
7221 * e1000_io_resume - called when traffic can start flowing again.
7222 * @pdev: Pointer to PCI device
7223 *
7224 * This callback is called when the error recovery driver tells us that
7225 * its OK to resume normal operation. Implementation resembles the
7226 * second-half of the e1000e_pm_resume routine.
7227 */
e1000_io_resume(struct pci_dev * pdev)7228 static void e1000_io_resume(struct pci_dev *pdev)
7229 {
7230 struct net_device *netdev = pci_get_drvdata(pdev);
7231 struct e1000_adapter *adapter = netdev_priv(netdev);
7232
7233 e1000_init_manageability_pt(adapter);
7234
7235 e1000e_pm_thaw(&pdev->dev);
7236
7237 /* If the controller has AMT, do not set DRV_LOAD until the interface
7238 * is up. For all other cases, let the f/w know that the h/w is now
7239 * under the control of the driver.
7240 */
7241 if (!(adapter->flags & FLAG_HAS_AMT))
7242 e1000e_get_hw_control(adapter);
7243 }
7244
e1000_print_device_info(struct e1000_adapter * adapter)7245 static void e1000_print_device_info(struct e1000_adapter *adapter)
7246 {
7247 struct e1000_hw *hw = &adapter->hw;
7248 struct net_device *netdev = adapter->netdev;
7249 u32 ret_val;
7250 u8 pba_str[E1000_PBANUM_LENGTH];
7251
7252 /* print bus type/speed/width info */
7253 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
7254 /* bus width */
7255 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
7256 "Width x1"),
7257 /* MAC address */
7258 netdev->dev_addr);
7259 e_info("Intel(R) PRO/%s Network Connection\n",
7260 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
7261 ret_val = e1000_read_pba_string_generic(hw, pba_str,
7262 E1000_PBANUM_LENGTH);
7263 if (ret_val)
7264 strscpy((char *)pba_str, "Unknown", sizeof(pba_str));
7265 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
7266 hw->mac.type, hw->phy.type, pba_str);
7267 }
7268
e1000_eeprom_checks(struct e1000_adapter * adapter)7269 static void e1000_eeprom_checks(struct e1000_adapter *adapter)
7270 {
7271 struct e1000_hw *hw = &adapter->hw;
7272 int ret_val;
7273 u16 buf = 0;
7274
7275 if (hw->mac.type != e1000_82573)
7276 return;
7277
7278 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
7279 le16_to_cpus(&buf);
7280 if (!ret_val && (!(buf & BIT(0)))) {
7281 /* Deep Smart Power Down (DSPD) */
7282 dev_warn(&adapter->pdev->dev,
7283 "Warning: detected DSPD enabled in EEPROM\n");
7284 }
7285 }
7286
e1000_fix_features(struct net_device * netdev,netdev_features_t features)7287 static netdev_features_t e1000_fix_features(struct net_device *netdev,
7288 netdev_features_t features)
7289 {
7290 struct e1000_adapter *adapter = netdev_priv(netdev);
7291 struct e1000_hw *hw = &adapter->hw;
7292
7293 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
7294 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
7295 features &= ~NETIF_F_RXFCS;
7296
7297 /* Since there is no support for separate Rx/Tx vlan accel
7298 * enable/disable make sure Tx flag is always in same state as Rx.
7299 */
7300 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7301 features |= NETIF_F_HW_VLAN_CTAG_TX;
7302 else
7303 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
7304
7305 return features;
7306 }
7307
e1000_set_features(struct net_device * netdev,netdev_features_t features)7308 static int e1000_set_features(struct net_device *netdev,
7309 netdev_features_t features)
7310 {
7311 struct e1000_adapter *adapter = netdev_priv(netdev);
7312 netdev_features_t changed = features ^ netdev->features;
7313
7314 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
7315 adapter->flags |= FLAG_TSO_FORCE;
7316
7317 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7318 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
7319 NETIF_F_RXALL)))
7320 return 0;
7321
7322 if (changed & NETIF_F_RXFCS) {
7323 if (features & NETIF_F_RXFCS) {
7324 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7325 } else {
7326 /* We need to take it back to defaults, which might mean
7327 * stripping is still disabled at the adapter level.
7328 */
7329 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
7330 adapter->flags2 |= FLAG2_CRC_STRIPPING;
7331 else
7332 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7333 }
7334 }
7335
7336 netdev->features = features;
7337
7338 if (netif_running(netdev))
7339 e1000e_reinit_locked(adapter);
7340 else
7341 e1000e_reset(adapter);
7342
7343 return 1;
7344 }
7345
7346 static const struct net_device_ops e1000e_netdev_ops = {
7347 .ndo_open = e1000e_open,
7348 .ndo_stop = e1000e_close,
7349 .ndo_start_xmit = e1000_xmit_frame,
7350 .ndo_get_stats64 = e1000e_get_stats64,
7351 .ndo_set_rx_mode = e1000e_set_rx_mode,
7352 .ndo_set_mac_address = e1000_set_mac,
7353 .ndo_change_mtu = e1000_change_mtu,
7354 .ndo_eth_ioctl = e1000_ioctl,
7355 .ndo_tx_timeout = e1000_tx_timeout,
7356 .ndo_validate_addr = eth_validate_addr,
7357
7358 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
7359 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
7360 #ifdef CONFIG_NET_POLL_CONTROLLER
7361 .ndo_poll_controller = e1000_netpoll,
7362 #endif
7363 .ndo_set_features = e1000_set_features,
7364 .ndo_fix_features = e1000_fix_features,
7365 .ndo_features_check = passthru_features_check,
7366 .ndo_hwtstamp_get = e1000e_hwtstamp_get,
7367 .ndo_hwtstamp_set = e1000e_hwtstamp_set,
7368 };
7369
7370 /**
7371 * e1000_probe - Device Initialization Routine
7372 * @pdev: PCI device information struct
7373 * @ent: entry in e1000_pci_tbl
7374 *
7375 * Returns 0 on success, negative on failure
7376 *
7377 * e1000_probe initializes an adapter identified by a pci_dev structure.
7378 * The OS initialization, configuring of the adapter private structure,
7379 * and a hardware reset occur.
7380 **/
e1000_probe(struct pci_dev * pdev,const struct pci_device_id * ent)7381 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7382 {
7383 struct net_device *netdev;
7384 struct e1000_adapter *adapter;
7385 struct e1000_hw *hw;
7386 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
7387 resource_size_t mmio_start, mmio_len;
7388 resource_size_t flash_start, flash_len;
7389 static int cards_found;
7390 u16 aspm_disable_flag = 0;
7391 u16 eeprom_data = 0;
7392 u16 eeprom_apme_mask = E1000_EEPROM_APME;
7393 int bars, i, err;
7394 s32 ret_val = 0;
7395
7396 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
7397 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7398 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
7399 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7400 if (aspm_disable_flag)
7401 e1000e_disable_aspm(pdev, aspm_disable_flag);
7402
7403 err = pci_enable_device_mem(pdev);
7404 if (err)
7405 return err;
7406
7407 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7408 if (err) {
7409 dev_err(&pdev->dev,
7410 "No usable DMA configuration, aborting\n");
7411 goto err_dma;
7412 }
7413
7414 bars = pci_select_bars(pdev, IORESOURCE_MEM);
7415 err = pci_request_selected_regions_exclusive(pdev, bars,
7416 e1000e_driver_name);
7417 if (err)
7418 goto err_pci_reg;
7419
7420 pci_set_master(pdev);
7421 /* PCI config space info */
7422 err = pci_save_state(pdev);
7423 if (err)
7424 goto err_alloc_etherdev;
7425
7426 err = -ENOMEM;
7427 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7428 if (!netdev)
7429 goto err_alloc_etherdev;
7430
7431 SET_NETDEV_DEV(netdev, &pdev->dev);
7432
7433 netdev->irq = pdev->irq;
7434
7435 pci_set_drvdata(pdev, netdev);
7436 adapter = netdev_priv(netdev);
7437 hw = &adapter->hw;
7438 adapter->netdev = netdev;
7439 adapter->pdev = pdev;
7440 adapter->ei = ei;
7441 adapter->pba = ei->pba;
7442 adapter->flags = ei->flags;
7443 adapter->flags2 = ei->flags2;
7444 adapter->hw.adapter = adapter;
7445 adapter->hw.mac.type = ei->mac;
7446 adapter->max_hw_frame_size = ei->max_hw_frame_size;
7447 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7448
7449 mmio_start = pci_resource_start(pdev, 0);
7450 mmio_len = pci_resource_len(pdev, 0);
7451
7452 err = -EIO;
7453 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7454 if (!adapter->hw.hw_addr)
7455 goto err_ioremap;
7456
7457 if ((adapter->flags & FLAG_HAS_FLASH) &&
7458 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7459 (hw->mac.type < e1000_pch_spt)) {
7460 flash_start = pci_resource_start(pdev, 1);
7461 flash_len = pci_resource_len(pdev, 1);
7462 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7463 if (!adapter->hw.flash_address)
7464 goto err_flashmap;
7465 }
7466
7467 /* Set default EEE advertisement */
7468 if (adapter->flags2 & FLAG2_HAS_EEE)
7469 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7470
7471 /* construct the net_device struct */
7472 netdev->netdev_ops = &e1000e_netdev_ops;
7473 e1000e_set_ethtool_ops(netdev);
7474 netdev->watchdog_timeo = 5 * HZ;
7475 netif_napi_add(netdev, &adapter->napi, e1000e_poll);
7476 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
7477
7478 netdev->mem_start = mmio_start;
7479 netdev->mem_end = mmio_start + mmio_len;
7480
7481 adapter->bd_number = cards_found++;
7482
7483 e1000e_check_options(adapter);
7484
7485 /* setup adapter struct */
7486 err = e1000_sw_init(adapter);
7487 if (err)
7488 goto err_sw_init;
7489
7490 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7491 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7492 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7493
7494 err = ei->get_variants(adapter);
7495 if (err)
7496 goto err_hw_init;
7497
7498 if ((adapter->flags & FLAG_IS_ICH) &&
7499 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7500 (hw->mac.type < e1000_pch_spt))
7501 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7502
7503 hw->mac.ops.get_bus_info(&adapter->hw);
7504
7505 adapter->hw.phy.autoneg_wait_to_complete = 0;
7506
7507 /* Copper options */
7508 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
7509 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7510 adapter->hw.phy.disable_polarity_correction = 0;
7511 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7512 }
7513
7514 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
7515 dev_info(&pdev->dev,
7516 "PHY reset is blocked due to SOL/IDER session.\n");
7517
7518 /* Set initial default active device features */
7519 netdev->features = (NETIF_F_SG |
7520 NETIF_F_HW_VLAN_CTAG_RX |
7521 NETIF_F_HW_VLAN_CTAG_TX |
7522 NETIF_F_TSO |
7523 NETIF_F_TSO6 |
7524 NETIF_F_RXHASH |
7525 NETIF_F_RXCSUM |
7526 NETIF_F_HW_CSUM);
7527
7528 /* disable TSO for pcie and 10/100 speeds to avoid
7529 * some hardware issues and for i219 to fix transfer
7530 * speed being capped at 60%
7531 */
7532 if (!(adapter->flags & FLAG_TSO_FORCE)) {
7533 switch (adapter->link_speed) {
7534 case SPEED_10:
7535 case SPEED_100:
7536 e_info("10/100 speed: disabling TSO\n");
7537 netdev->features &= ~NETIF_F_TSO;
7538 netdev->features &= ~NETIF_F_TSO6;
7539 break;
7540 case SPEED_1000:
7541 netdev->features |= NETIF_F_TSO;
7542 netdev->features |= NETIF_F_TSO6;
7543 break;
7544 default:
7545 /* oops */
7546 break;
7547 }
7548 if (hw->mac.type == e1000_pch_spt) {
7549 netdev->features &= ~NETIF_F_TSO;
7550 netdev->features &= ~NETIF_F_TSO6;
7551 }
7552 }
7553
7554 /* Set user-changeable features (subset of all device features) */
7555 netdev->hw_features = netdev->features;
7556 netdev->hw_features |= NETIF_F_RXFCS;
7557 netdev->priv_flags |= IFF_SUPP_NOFCS;
7558 netdev->hw_features |= NETIF_F_RXALL;
7559
7560 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
7561 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7562
7563 netdev->vlan_features |= (NETIF_F_SG |
7564 NETIF_F_TSO |
7565 NETIF_F_TSO6 |
7566 NETIF_F_HW_CSUM);
7567
7568 netdev->priv_flags |= IFF_UNICAST_FLT;
7569
7570 netdev->features |= NETIF_F_HIGHDMA;
7571 netdev->vlan_features |= NETIF_F_HIGHDMA;
7572
7573 /* MTU range: 68 - max_hw_frame_size */
7574 netdev->min_mtu = ETH_MIN_MTU;
7575 netdev->max_mtu = adapter->max_hw_frame_size -
7576 (VLAN_ETH_HLEN + ETH_FCS_LEN);
7577
7578 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7579 adapter->flags |= FLAG_MNG_PT_ENABLED;
7580
7581 /* before reading the NVM, reset the controller to
7582 * put the device in a known good starting state
7583 */
7584 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7585
7586 /* systems with ASPM and others may see the checksum fail on the first
7587 * attempt. Let's give it a few tries
7588 */
7589 for (i = 0;; i++) {
7590 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7591 break;
7592 if (i == 2) {
7593 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
7594 err = -EIO;
7595 goto err_eeprom;
7596 }
7597 }
7598
7599 e1000_eeprom_checks(adapter);
7600
7601 /* copy the MAC address */
7602 if (e1000e_read_mac_addr(&adapter->hw))
7603 dev_err(&pdev->dev,
7604 "NVM Read Error while reading MAC address\n");
7605
7606 eth_hw_addr_set(netdev, adapter->hw.mac.addr);
7607
7608 if (!is_valid_ether_addr(netdev->dev_addr)) {
7609 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
7610 netdev->dev_addr);
7611 err = -EIO;
7612 goto err_eeprom;
7613 }
7614
7615 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0);
7616 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0);
7617
7618 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7619 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
7620 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7621 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
7622 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
7623
7624 /* Initialize link parameters. User can change them with ethtool */
7625 adapter->hw.mac.autoneg = 1;
7626 adapter->fc_autoneg = true;
7627 adapter->hw.fc.requested_mode = e1000_fc_default;
7628 adapter->hw.fc.current_mode = e1000_fc_default;
7629 adapter->hw.phy.autoneg_advertised = 0x2f;
7630
7631 /* Initial Wake on LAN setting - If APM wake is enabled in
7632 * the EEPROM, enable the ACPI Magic Packet filter
7633 */
7634 if (adapter->flags & FLAG_APME_IN_WUC) {
7635 /* APME bit in EEPROM is mapped to WUC.APME */
7636 eeprom_data = er32(WUC);
7637 eeprom_apme_mask = E1000_WUC_APME;
7638 if ((hw->mac.type > e1000_ich10lan) &&
7639 (eeprom_data & E1000_WUC_PHY_WAKE))
7640 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
7641 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7642 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7643 (adapter->hw.bus.func == 1))
7644 ret_val = e1000_read_nvm(&adapter->hw,
7645 NVM_INIT_CONTROL3_PORT_B,
7646 1, &eeprom_data);
7647 else
7648 ret_val = e1000_read_nvm(&adapter->hw,
7649 NVM_INIT_CONTROL3_PORT_A,
7650 1, &eeprom_data);
7651 }
7652
7653 /* fetch WoL from EEPROM */
7654 if (ret_val)
7655 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
7656 else if (eeprom_data & eeprom_apme_mask)
7657 adapter->eeprom_wol |= E1000_WUFC_MAG;
7658
7659 /* now that we have the eeprom settings, apply the special cases
7660 * where the eeprom may be wrong or the board simply won't support
7661 * wake on lan on a particular port
7662 */
7663 if (!(adapter->flags & FLAG_HAS_WOL))
7664 adapter->eeprom_wol = 0;
7665
7666 /* initialize the wol settings based on the eeprom settings */
7667 adapter->wol = adapter->eeprom_wol;
7668
7669 /* make sure adapter isn't asleep if manageability is enabled */
7670 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7671 (hw->mac.ops.check_mng_mode(hw)))
7672 device_wakeup_enable(&pdev->dev);
7673
7674 /* save off EEPROM version number */
7675 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7676
7677 if (ret_val) {
7678 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
7679 adapter->eeprom_vers = 0;
7680 }
7681
7682 /* init PTP hardware clock */
7683 e1000e_ptp_init(adapter);
7684
7685 /* disable K1 by default on known problematic systems */
7686 if (hw->mac.type >= e1000_pch_mtp && dmi_check_system(disable_k1_list))
7687 adapter->flags2 |= FLAG2_DISABLE_K1;
7688
7689 /* reset the hardware with the new settings */
7690 e1000e_reset(adapter);
7691
7692 /* If the controller has AMT, do not set DRV_LOAD until the interface
7693 * is up. For all other cases, let the f/w know that the h/w is now
7694 * under the control of the driver.
7695 */
7696 if (!(adapter->flags & FLAG_HAS_AMT))
7697 e1000e_get_hw_control(adapter);
7698
7699 if (hw->mac.type >= e1000_pch_cnp)
7700 adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS;
7701
7702 strscpy(netdev->name, "eth%d", sizeof(netdev->name));
7703 err = register_netdev(netdev);
7704 if (err)
7705 goto err_register;
7706
7707 /* carrier off reporting is important to ethtool even BEFORE open */
7708 netif_carrier_off(netdev);
7709
7710 e1000_print_device_info(adapter);
7711
7712 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_SMART_PREPARE);
7713
7714 if (pci_dev_run_wake(pdev))
7715 pm_runtime_put_noidle(&pdev->dev);
7716
7717 return 0;
7718
7719 err_register:
7720 if (!(adapter->flags & FLAG_HAS_AMT))
7721 e1000e_release_hw_control(adapter);
7722 e1000e_ptp_remove(adapter);
7723 err_eeprom:
7724 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
7725 e1000_phy_hw_reset(&adapter->hw);
7726 err_hw_init:
7727 kfree(adapter->tx_ring);
7728 kfree(adapter->rx_ring);
7729 err_sw_init:
7730 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
7731 iounmap(adapter->hw.flash_address);
7732 e1000e_reset_interrupt_capability(adapter);
7733 err_flashmap:
7734 iounmap(adapter->hw.hw_addr);
7735 err_ioremap:
7736 free_netdev(netdev);
7737 err_alloc_etherdev:
7738 pci_release_mem_regions(pdev);
7739 err_pci_reg:
7740 err_dma:
7741 pci_disable_device(pdev);
7742 return err;
7743 }
7744
7745 /**
7746 * e1000_remove - Device Removal Routine
7747 * @pdev: PCI device information struct
7748 *
7749 * e1000_remove is called by the PCI subsystem to alert the driver
7750 * that it should release a PCI device. This could be caused by a
7751 * Hot-Plug event, or because the driver is going to be removed from
7752 * memory.
7753 **/
e1000_remove(struct pci_dev * pdev)7754 static void e1000_remove(struct pci_dev *pdev)
7755 {
7756 struct net_device *netdev = pci_get_drvdata(pdev);
7757 struct e1000_adapter *adapter = netdev_priv(netdev);
7758
7759 e1000e_ptp_remove(adapter);
7760
7761 /* The timers may be rescheduled, so explicitly disable them
7762 * from being rescheduled.
7763 */
7764 set_bit(__E1000_DOWN, &adapter->state);
7765 timer_delete_sync(&adapter->watchdog_timer);
7766 timer_delete_sync(&adapter->phy_info_timer);
7767
7768 cancel_work_sync(&adapter->reset_task);
7769 cancel_work_sync(&adapter->watchdog_task);
7770 cancel_work_sync(&adapter->downshift_task);
7771 cancel_work_sync(&adapter->update_phy_task);
7772 cancel_work_sync(&adapter->print_hang_task);
7773
7774 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7775 cancel_work_sync(&adapter->tx_hwtstamp_work);
7776 if (adapter->tx_hwtstamp_skb) {
7777 dev_consume_skb_any(adapter->tx_hwtstamp_skb);
7778 adapter->tx_hwtstamp_skb = NULL;
7779 }
7780 }
7781
7782 unregister_netdev(netdev);
7783
7784 if (pci_dev_run_wake(pdev))
7785 pm_runtime_get_noresume(&pdev->dev);
7786
7787 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7788 * would have already happened in close and is redundant.
7789 */
7790 e1000e_release_hw_control(adapter);
7791
7792 e1000e_reset_interrupt_capability(adapter);
7793 kfree(adapter->tx_ring);
7794 kfree(adapter->rx_ring);
7795
7796 iounmap(adapter->hw.hw_addr);
7797 if ((adapter->hw.flash_address) &&
7798 (adapter->hw.mac.type < e1000_pch_spt))
7799 iounmap(adapter->hw.flash_address);
7800 pci_release_mem_regions(pdev);
7801
7802 free_netdev(netdev);
7803
7804 pci_disable_device(pdev);
7805 }
7806
7807 /* PCI Error Recovery (ERS) */
7808 static const struct pci_error_handlers e1000_err_handler = {
7809 .error_detected = e1000_io_error_detected,
7810 .slot_reset = e1000_io_slot_reset,
7811 .resume = e1000_io_resume,
7812 };
7813
7814 static const struct pci_device_id e1000_pci_tbl[] = {
7815 {
7816 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER),
7817 .driver_data = board_82571,
7818 }, {
7819 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER),
7820 .driver_data = board_82571,
7821 }, {
7822 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER),
7823 .driver_data = board_82571,
7824 }, {
7825 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7826 .driver_data = board_82571,
7827 }, {
7828 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER),
7829 .driver_data = board_82571,
7830 }, {
7831 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES),
7832 .driver_data = board_82571,
7833 }, {
7834 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL),
7835 .driver_data = board_82571,
7836 }, {
7837 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD),
7838 .driver_data = board_82571,
7839 }, {
7840 PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER),
7841 .driver_data = board_82571,
7842 },
7843
7844 {
7845 PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI),
7846 .driver_data = board_82572,
7847 }, {
7848 PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER),
7849 .driver_data = board_82572,
7850 }, {
7851 PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER),
7852 .driver_data = board_82572,
7853 }, {
7854 PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES),
7855 .driver_data = board_82572,
7856 },
7857
7858 {
7859 PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E),
7860 .driver_data = board_82573,
7861 }, {
7862 PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT),
7863 .driver_data = board_82573,
7864 }, {
7865 PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L),
7866 .driver_data = board_82573,
7867 },
7868
7869 {
7870 PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L),
7871 .driver_data = board_82574,
7872 }, {
7873 PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA),
7874 .driver_data = board_82574,
7875 }, {
7876 PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V),
7877 .driver_data = board_82583,
7878 },
7879
7880 {
7881 PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7882 .driver_data = board_80003es2lan,
7883 }, {
7884 PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7885 .driver_data = board_80003es2lan,
7886 }, {
7887 PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7888 .driver_data = board_80003es2lan,
7889 }, {
7890 PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7891 .driver_data = board_80003es2lan,
7892 },
7893
7894 {
7895 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE),
7896 .driver_data = board_ich8lan,
7897 }, {
7898 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G),
7899 .driver_data = board_ich8lan,
7900 }, {
7901 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT),
7902 .driver_data = board_ich8lan,
7903 }, {
7904 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT),
7905 .driver_data = board_ich8lan,
7906 }, {
7907 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C),
7908 .driver_data = board_ich8lan,
7909 }, {
7910 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M),
7911 .driver_data = board_ich8lan,
7912 }, {
7913 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT),
7914 .driver_data = board_ich8lan,
7915 }, {
7916 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3),
7917 .driver_data = board_ich8lan,
7918 },
7919
7920 {
7921 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE),
7922 .driver_data = board_ich9lan,
7923 }, {
7924 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G),
7925 .driver_data = board_ich9lan,
7926 }, {
7927 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT),
7928 .driver_data = board_ich9lan,
7929 }, {
7930 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT),
7931 .driver_data = board_ich9lan,
7932 }, {
7933 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C),
7934 .driver_data = board_ich9lan,
7935 }, {
7936 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM),
7937 .driver_data = board_ich9lan,
7938 }, {
7939 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M),
7940 .driver_data = board_ich9lan,
7941 }, {
7942 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT),
7943 .driver_data = board_ich9lan,
7944 }, {
7945 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V),
7946 .driver_data = board_ich9lan
7947 },
7948
7949 {
7950 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM),
7951 .driver_data = board_ich9lan,
7952 }, {
7953 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF),
7954 .driver_data = board_ich9lan,
7955 }, {
7956 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V),
7957 .driver_data = board_ich9lan,
7958 },
7959
7960 {
7961 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM),
7962 .driver_data = board_ich10lan,
7963 }, {
7964 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF),
7965 .driver_data = board_ich10lan,
7966 }, {
7967 PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V),
7968 .driver_data = board_ich10lan,
7969 },
7970
7971 {
7972 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM),
7973 .driver_data = board_pchlan,
7974 }, {
7975 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC),
7976 .driver_data = board_pchlan,
7977 }, {
7978 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM),
7979 .driver_data = board_pchlan,
7980 }, {
7981 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC),
7982 .driver_data = board_pchlan
7983 },
7984
7985 {
7986 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM),
7987 .driver_data = board_pch2lan,
7988 }, {
7989 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V),
7990 .driver_data = board_pch2lan
7991 },
7992
7993 {
7994 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM),
7995 .driver_data = board_pch_lpt,
7996 }, {
7997 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V),
7998 .driver_data = board_pch_lpt,
7999 }, {
8000 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM),
8001 .driver_data = board_pch_lpt,
8002 }, {
8003 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V),
8004 .driver_data = board_pch_lpt,
8005 }, {
8006 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2),
8007 .driver_data = board_pch_lpt,
8008 }, {
8009 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2),
8010 .driver_data = board_pch_lpt,
8011 }, {
8012 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3),
8013 .driver_data = board_pch_lpt,
8014 }, {
8015 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3),
8016 .driver_data = board_pch_lpt,
8017 }, {
8018 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM),
8019 .driver_data = board_pch_spt,
8020 }, {
8021 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V),
8022 .driver_data = board_pch_spt,
8023 }, {
8024 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2),
8025 .driver_data = board_pch_spt,
8026 }, {
8027 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2),
8028 .driver_data = board_pch_spt,
8029 }, {
8030 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3),
8031 .driver_data = board_pch_spt,
8032 }, {
8033 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4),
8034 .driver_data = board_pch_spt,
8035 }, {
8036 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4),
8037 .driver_data = board_pch_spt,
8038 }, {
8039 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5),
8040 .driver_data = board_pch_spt,
8041 }, {
8042 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5),
8043 .driver_data = board_pch_spt,
8044 }, {
8045 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6),
8046 .driver_data = board_pch_cnp,
8047 }, {
8048 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6),
8049 .driver_data = board_pch_cnp,
8050 }, {
8051 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7),
8052 .driver_data = board_pch_cnp,
8053 }, {
8054 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7),
8055 .driver_data = board_pch_cnp,
8056 }, {
8057 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8),
8058 .driver_data = board_pch_cnp,
8059 }, {
8060 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8),
8061 .driver_data = board_pch_cnp,
8062 }, {
8063 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9),
8064 .driver_data = board_pch_cnp,
8065 }, {
8066 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9),
8067 .driver_data = board_pch_cnp,
8068 }, {
8069 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10),
8070 .driver_data = board_pch_cnp,
8071 }, {
8072 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10),
8073 .driver_data = board_pch_cnp,
8074 }, {
8075 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11),
8076 .driver_data = board_pch_cnp,
8077 }, {
8078 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11),
8079 .driver_data = board_pch_cnp,
8080 }, {
8081 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12),
8082 .driver_data = board_pch_spt,
8083 }, {
8084 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12),
8085 .driver_data = board_pch_spt,
8086 }, {
8087 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13),
8088 .driver_data = board_pch_tgp,
8089 }, {
8090 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13),
8091 .driver_data = board_pch_tgp,
8092 }, {
8093 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14),
8094 .driver_data = board_pch_tgp,
8095 }, {
8096 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14),
8097 .driver_data = board_pch_tgp,
8098 }, {
8099 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15),
8100 .driver_data = board_pch_tgp,
8101 }, {
8102 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15),
8103 .driver_data = board_pch_tgp,
8104 }, {
8105 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23),
8106 .driver_data = board_pch_adp,
8107 }, {
8108 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23),
8109 .driver_data = board_pch_adp,
8110 }, {
8111 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16),
8112 .driver_data = board_pch_adp,
8113 }, {
8114 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16),
8115 .driver_data = board_pch_adp,
8116 }, {
8117 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17),
8118 .driver_data = board_pch_adp,
8119 }, {
8120 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17),
8121 .driver_data = board_pch_adp,
8122 }, {
8123 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22),
8124 .driver_data = board_pch_adp,
8125 }, {
8126 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22),
8127 .driver_data = board_pch_adp,
8128 }, {
8129 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM19),
8130 .driver_data = board_pch_adp,
8131 }, {
8132 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V19),
8133 .driver_data = board_pch_adp,
8134 }, {
8135 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18),
8136 .driver_data = board_pch_mtp,
8137 }, {
8138 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18),
8139 .driver_data = board_pch_mtp,
8140 }, {
8141 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20),
8142 .driver_data = board_pch_mtp,
8143 }, {
8144 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20),
8145 .driver_data = board_pch_mtp,
8146 }, {
8147 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21),
8148 .driver_data = board_pch_mtp,
8149 }, {
8150 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21),
8151 .driver_data = board_pch_mtp,
8152 }, {
8153 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_LM24),
8154 .driver_data = board_pch_mtp,
8155 }, {
8156 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_V24),
8157 .driver_data = board_pch_mtp,
8158 }, {
8159 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM25),
8160 .driver_data = board_pch_ptp,
8161 }, {
8162 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V25),
8163 .driver_data = board_pch_ptp,
8164 }, {
8165 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM27),
8166 .driver_data = board_pch_ptp,
8167 }, {
8168 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V27),
8169 .driver_data = board_pch_ptp,
8170 }, {
8171 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_LM29),
8172 .driver_data = board_pch_ptp,
8173 }, {
8174 PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_V29),
8175 .driver_data = board_pch_ptp
8176 },
8177
8178 { } /* terminate list */
8179 };
8180 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
8181
8182 static const struct dev_pm_ops e1000e_pm_ops = {
8183 .prepare = e1000e_pm_prepare,
8184 .suspend = e1000e_pm_suspend,
8185 .resume = e1000e_pm_resume,
8186 .freeze = e1000e_pm_freeze,
8187 .thaw = e1000e_pm_thaw,
8188 .poweroff = e1000e_pm_suspend,
8189 .restore = e1000e_pm_resume,
8190 RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
8191 e1000e_pm_runtime_idle)
8192 };
8193
8194 /* PCI Device API Driver */
8195 static struct pci_driver e1000_driver = {
8196 .name = e1000e_driver_name,
8197 .id_table = e1000_pci_tbl,
8198 .probe = e1000_probe,
8199 .remove = e1000_remove,
8200 .driver.pm = pm_ptr(&e1000e_pm_ops),
8201 .shutdown = e1000_shutdown,
8202 .err_handler = &e1000_err_handler
8203 };
8204
8205 /**
8206 * e1000_init_module - Driver Registration Routine
8207 *
8208 * e1000_init_module is the first routine called when the driver is
8209 * loaded. All it does is register with the PCI subsystem.
8210 **/
e1000_init_module(void)8211 static int __init e1000_init_module(void)
8212 {
8213 pr_info("Intel(R) PRO/1000 Network Driver\n");
8214 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
8215
8216 return pci_register_driver(&e1000_driver);
8217 }
8218 module_init(e1000_init_module);
8219
8220 /**
8221 * e1000_exit_module - Driver Exit Cleanup Routine
8222 *
8223 * e1000_exit_module is called just before the driver is removed
8224 * from memory.
8225 **/
e1000_exit_module(void)8226 static void __exit e1000_exit_module(void)
8227 {
8228 pci_unregister_driver(&e1000_driver);
8229 }
8230 module_exit(e1000_exit_module);
8231
8232 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
8233 MODULE_LICENSE("GPL v2");
8234
8235 /* netdev.c */
8236