1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
4 * stmmac XGMAC support.
5 */
6
7 #include <linux/iopoll.h>
8 #include "stmmac.h"
9 #include "dwxgmac2.h"
10
dwxgmac2_dma_reset(void __iomem * ioaddr)11 static int dwxgmac2_dma_reset(void __iomem *ioaddr)
12 {
13 u32 value = readl(ioaddr + XGMAC_DMA_MODE);
14
15 /* DMA SW reset */
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE);
17
18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value,
19 !(value & XGMAC_SWR), 0, 100000);
20 }
21
dwxgmac2_dma_init(void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg)22 static void dwxgmac2_dma_init(void __iomem *ioaddr,
23 struct stmmac_dma_cfg *dma_cfg)
24 {
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
26
27 if (dma_cfg->aal)
28 value |= XGMAC_AAL;
29
30 if (dma_cfg->eame)
31 value |= XGMAC_EAME;
32
33 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
34 }
35
dwxgmac2_dma_init_chan(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,u32 chan)36 static void dwxgmac2_dma_init_chan(struct stmmac_priv *priv,
37 void __iomem *ioaddr,
38 struct stmmac_dma_cfg *dma_cfg, u32 chan)
39 {
40 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));
41
42 if (dma_cfg->pblx8)
43 value |= XGMAC_PBLx8;
44
45 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
46 writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
47 }
48
dwxgmac2_dma_init_rx_chan(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,dma_addr_t phy,u32 chan)49 static void dwxgmac2_dma_init_rx_chan(struct stmmac_priv *priv,
50 void __iomem *ioaddr,
51 struct stmmac_dma_cfg *dma_cfg,
52 dma_addr_t phy, u32 chan)
53 {
54 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
55 u32 value;
56
57 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
58 value &= ~XGMAC_RxPBL;
59 value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL;
60 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
61
62 writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan));
63 writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
64 }
65
dwxgmac2_dma_init_tx_chan(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,dma_addr_t phy,u32 chan)66 static void dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv,
67 void __iomem *ioaddr,
68 struct stmmac_dma_cfg *dma_cfg,
69 dma_addr_t phy, u32 chan)
70 {
71 u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
72 u32 value;
73
74 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
75 value &= ~XGMAC_TxPBL;
76 value |= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL;
77 value |= XGMAC_OSP;
78 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
79
80 writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan));
81 writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
82 }
83
dwxgmac2_dma_axi(void __iomem * ioaddr,struct stmmac_axi * axi)84 static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
85 {
86 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
87 int i;
88
89 if (axi->axi_lpi_en)
90 value |= XGMAC_EN_LPI;
91 if (axi->axi_xit_frm)
92 value |= XGMAC_LPI_XIT_PKT;
93
94 value &= ~XGMAC_WR_OSR_LMT;
95 value |= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) &
96 XGMAC_WR_OSR_LMT;
97
98 value &= ~XGMAC_RD_OSR_LMT;
99 value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) &
100 XGMAC_RD_OSR_LMT;
101
102 if (!axi->axi_fb)
103 value |= XGMAC_UNDEF;
104
105 value &= ~XGMAC_BLEN;
106 for (i = 0; i < AXI_BLEN; i++) {
107 switch (axi->axi_blen[i]) {
108 case 256:
109 value |= XGMAC_BLEN256;
110 break;
111 case 128:
112 value |= XGMAC_BLEN128;
113 break;
114 case 64:
115 value |= XGMAC_BLEN64;
116 break;
117 case 32:
118 value |= XGMAC_BLEN32;
119 break;
120 case 16:
121 value |= XGMAC_BLEN16;
122 break;
123 case 8:
124 value |= XGMAC_BLEN8;
125 break;
126 case 4:
127 value |= XGMAC_BLEN4;
128 break;
129 }
130 }
131
132 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
133 writel(XGMAC_TDPS, ioaddr + XGMAC_TX_EDMA_CTRL);
134 writel(XGMAC_RDPS, ioaddr + XGMAC_RX_EDMA_CTRL);
135 }
136
dwxgmac2_dma_dump_regs(struct stmmac_priv * priv,void __iomem * ioaddr,u32 * reg_space)137 static void dwxgmac2_dma_dump_regs(struct stmmac_priv *priv,
138 void __iomem *ioaddr, u32 *reg_space)
139 {
140 int i;
141
142 for (i = (XGMAC_DMA_MODE / 4); i < XGMAC_REGSIZE; i++)
143 reg_space[i] = readl(ioaddr + i * 4);
144 }
145
dwxgmac2_dma_rx_mode(struct stmmac_priv * priv,void __iomem * ioaddr,int mode,u32 channel,int fifosz,u8 qmode)146 static void dwxgmac2_dma_rx_mode(struct stmmac_priv *priv, void __iomem *ioaddr,
147 int mode, u32 channel, int fifosz, u8 qmode)
148 {
149 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
150 unsigned int rqs = fifosz / 256 - 1;
151
152 if (mode == SF_DMA_MODE) {
153 value |= XGMAC_RSF;
154 } else {
155 value &= ~XGMAC_RSF;
156 value &= ~XGMAC_RTC;
157
158 if (mode <= 64)
159 value |= 0x0 << XGMAC_RTC_SHIFT;
160 else if (mode <= 96)
161 value |= 0x2 << XGMAC_RTC_SHIFT;
162 else
163 value |= 0x3 << XGMAC_RTC_SHIFT;
164 }
165
166 value &= ~XGMAC_RQS;
167 value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS;
168
169 if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
170 u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
171 unsigned int rfd, rfa;
172
173 value |= XGMAC_EHFC;
174
175 /* Set Threshold for Activating Flow Control to min 2 frames,
176 * i.e. 1500 * 2 = 3000 bytes.
177 *
178 * Set Threshold for Deactivating Flow Control to min 1 frame,
179 * i.e. 1500 bytes.
180 */
181 switch (fifosz) {
182 case 4096:
183 /* This violates the above formula because of FIFO size
184 * limit therefore overflow may occur in spite of this.
185 */
186 rfd = 0x03; /* Full-2.5K */
187 rfa = 0x01; /* Full-1.5K */
188 break;
189
190 default:
191 rfd = 0x07; /* Full-4.5K */
192 rfa = 0x04; /* Full-3K */
193 break;
194 }
195
196 flow &= ~XGMAC_RFD;
197 flow |= rfd << XGMAC_RFD_SHIFT;
198
199 flow &= ~XGMAC_RFA;
200 flow |= rfa << XGMAC_RFA_SHIFT;
201
202 writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
203 }
204
205 writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
206 }
207
dwxgmac2_dma_tx_mode(struct stmmac_priv * priv,void __iomem * ioaddr,int mode,u32 channel,int fifosz,u8 qmode)208 static void dwxgmac2_dma_tx_mode(struct stmmac_priv *priv, void __iomem *ioaddr,
209 int mode, u32 channel, int fifosz, u8 qmode)
210 {
211 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
212 unsigned int tqs = fifosz / 256 - 1;
213
214 if (mode == SF_DMA_MODE) {
215 value |= XGMAC_TSF;
216 } else {
217 value &= ~XGMAC_TSF;
218 value &= ~XGMAC_TTC;
219
220 if (mode <= 64)
221 value |= 0x0 << XGMAC_TTC_SHIFT;
222 else if (mode <= 96)
223 value |= 0x2 << XGMAC_TTC_SHIFT;
224 else if (mode <= 128)
225 value |= 0x3 << XGMAC_TTC_SHIFT;
226 else if (mode <= 192)
227 value |= 0x4 << XGMAC_TTC_SHIFT;
228 else if (mode <= 256)
229 value |= 0x5 << XGMAC_TTC_SHIFT;
230 else if (mode <= 384)
231 value |= 0x6 << XGMAC_TTC_SHIFT;
232 else
233 value |= 0x7 << XGMAC_TTC_SHIFT;
234 }
235
236 /* Use static TC to Queue mapping */
237 value |= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP;
238
239 value &= ~XGMAC_TXQEN;
240 if (qmode != MTL_QUEUE_AVB)
241 value |= 0x2 << XGMAC_TXQEN_SHIFT;
242 else
243 value |= 0x1 << XGMAC_TXQEN_SHIFT;
244
245 value &= ~XGMAC_TQS;
246 value |= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS;
247
248 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
249 }
250
dwxgmac2_enable_dma_irq(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan,bool rx,bool tx)251 static void dwxgmac2_enable_dma_irq(struct stmmac_priv *priv,
252 void __iomem *ioaddr, u32 chan,
253 bool rx, bool tx)
254 {
255 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
256
257 if (rx)
258 value |= XGMAC_DMA_INT_DEFAULT_RX;
259 if (tx)
260 value |= XGMAC_DMA_INT_DEFAULT_TX;
261
262 writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
263 }
264
dwxgmac2_disable_dma_irq(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan,bool rx,bool tx)265 static void dwxgmac2_disable_dma_irq(struct stmmac_priv *priv,
266 void __iomem *ioaddr, u32 chan,
267 bool rx, bool tx)
268 {
269 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
270
271 if (rx)
272 value &= ~XGMAC_DMA_INT_DEFAULT_RX;
273 if (tx)
274 value &= ~XGMAC_DMA_INT_DEFAULT_TX;
275
276 writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
277 }
278
dwxgmac2_dma_start_tx(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan)279 static void dwxgmac2_dma_start_tx(struct stmmac_priv *priv,
280 void __iomem *ioaddr, u32 chan)
281 {
282 u32 value;
283
284 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
285 value |= XGMAC_TXST;
286 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
287
288 value = readl(ioaddr + XGMAC_TX_CONFIG);
289 value |= XGMAC_CONFIG_TE;
290 writel(value, ioaddr + XGMAC_TX_CONFIG);
291 }
292
dwxgmac2_dma_stop_tx(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan)293 static void dwxgmac2_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
294 u32 chan)
295 {
296 u32 value;
297
298 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
299 value &= ~XGMAC_TXST;
300 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
301
302 value = readl(ioaddr + XGMAC_TX_CONFIG);
303 value &= ~XGMAC_CONFIG_TE;
304 writel(value, ioaddr + XGMAC_TX_CONFIG);
305 }
306
dwxgmac2_dma_start_rx(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan)307 static void dwxgmac2_dma_start_rx(struct stmmac_priv *priv,
308 void __iomem *ioaddr, u32 chan)
309 {
310 u32 value;
311
312 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
313 value |= XGMAC_RXST;
314 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
315
316 value = readl(ioaddr + XGMAC_RX_CONFIG);
317 value |= XGMAC_CONFIG_RE;
318 writel(value, ioaddr + XGMAC_RX_CONFIG);
319 }
320
dwxgmac2_dma_stop_rx(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan)321 static void dwxgmac2_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
322 u32 chan)
323 {
324 u32 value;
325
326 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
327 value &= ~XGMAC_RXST;
328 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
329 }
330
dwxgmac2_dma_interrupt(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_extra_stats * x,u32 chan,u32 dir)331 static int dwxgmac2_dma_interrupt(struct stmmac_priv *priv,
332 void __iomem *ioaddr,
333 struct stmmac_extra_stats *x, u32 chan,
334 u32 dir)
335 {
336 struct stmmac_pcpu_stats *stats = this_cpu_ptr(priv->xstats.pcpu_stats);
337 u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan));
338 u32 intr_en = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
339 int ret = 0;
340
341 if (dir == DMA_DIR_RX)
342 intr_status &= XGMAC_DMA_STATUS_MSK_RX;
343 else if (dir == DMA_DIR_TX)
344 intr_status &= XGMAC_DMA_STATUS_MSK_TX;
345
346 /* ABNORMAL interrupts */
347 if (unlikely(intr_status & XGMAC_AIS)) {
348 if (unlikely(intr_status & XGMAC_RBU)) {
349 x->rx_buf_unav_irq++;
350 ret |= handle_rx;
351 }
352 if (unlikely(intr_status & XGMAC_TPS)) {
353 x->tx_process_stopped_irq++;
354 ret |= tx_hard_error;
355 }
356 if (unlikely(intr_status & XGMAC_FBE)) {
357 x->fatal_bus_error_irq++;
358 ret |= tx_hard_error;
359 }
360 }
361
362 /* TX/RX NORMAL interrupts */
363 if (likely(intr_status & XGMAC_RI)) {
364 u64_stats_update_begin(&stats->syncp);
365 u64_stats_inc(&stats->rx_normal_irq_n[chan]);
366 u64_stats_update_end(&stats->syncp);
367 ret |= handle_rx;
368 }
369 if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) {
370 u64_stats_update_begin(&stats->syncp);
371 u64_stats_inc(&stats->tx_normal_irq_n[chan]);
372 u64_stats_update_end(&stats->syncp);
373 ret |= handle_tx;
374 }
375
376 /* Clear interrupts */
377 writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan));
378
379 return ret;
380 }
381
dwxgmac2_get_hw_feature(void __iomem * ioaddr,struct dma_features * dma_cap)382 static int dwxgmac2_get_hw_feature(void __iomem *ioaddr,
383 struct dma_features *dma_cap)
384 {
385 struct stmmac_priv *priv;
386 u32 hw_cap;
387
388 priv = container_of(dma_cap, struct stmmac_priv, dma_cap);
389
390 /* MAC HW feature 0 */
391 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0);
392 dma_cap->edma = (hw_cap & XGMAC_HWFEAT_EDMA) >> 31;
393 dma_cap->ediffc = (hw_cap & XGMAC_HWFEAT_EDIFFC) >> 30;
394 dma_cap->vxn = (hw_cap & XGMAC_HWFEAT_VXN) >> 29;
395 dma_cap->vlins = (hw_cap & XGMAC_HWFEAT_SAVLANINS) >> 27;
396 dma_cap->tssrc = (hw_cap & XGMAC_HWFEAT_TSSTSSEL) >> 25;
397 dma_cap->multi_addr = (hw_cap & XGMAC_HWFEAT_ADDMACADRSEL) >> 18;
398 dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16;
399 dma_cap->tx_coe = (hw_cap & XGMAC_HWFEAT_TXCOESEL) >> 14;
400 dma_cap->eee = (hw_cap & XGMAC_HWFEAT_EEESEL) >> 13;
401 dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12;
402 dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11;
403 dma_cap->av &= !((hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10);
404 dma_cap->arpoffsel = (hw_cap & XGMAC_HWFEAT_ARPOFFSEL) >> 9;
405 dma_cap->rmon = (hw_cap & XGMAC_HWFEAT_MMCSEL) >> 8;
406 dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7;
407 dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6;
408 dma_cap->sma_mdio = (hw_cap & XGMAC_HWFEAT_SMASEL) >> 5;
409 dma_cap->vlhash = (hw_cap & XGMAC_HWFEAT_VLHASH) >> 4;
410 dma_cap->half_duplex = (hw_cap & XGMAC_HWFEAT_HDSEL) >> 3;
411 dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1;
412 if (dma_cap->mbps_1000 && priv->synopsys_id >= DWXGMAC_CORE_2_20)
413 dma_cap->mbps_10_100 = 1;
414
415 /* MAC HW feature 1 */
416 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);
417 dma_cap->l3l4fnum = (hw_cap & XGMAC_HWFEAT_L3L4FNUM) >> 27;
418 /* If L3L4FNUM < 8, then the number of L3L4 filters supported by
419 * XGMAC is equal to L3L4FNUM. From L3L4FNUM >= 8 the number of
420 * L3L4 filters goes on like 8, 16, 32, ... Current maximum of
421 * L3L4FNUM = 10.
422 */
423 if (dma_cap->l3l4fnum >= 8 && dma_cap->l3l4fnum <= 10)
424 dma_cap->l3l4fnum = 8 << (dma_cap->l3l4fnum - 8);
425 else if (dma_cap->l3l4fnum > 10)
426 dma_cap->l3l4fnum = 32;
427
428 dma_cap->hash_tb_sz = (hw_cap & XGMAC_HWFEAT_HASHTBLSZ) >> 24;
429 dma_cap->numtc = ((hw_cap & XGMAC_HWFEAT_NUMTC) >> 21) + 1;
430 dma_cap->rssen = (hw_cap & XGMAC_HWFEAT_RSSEN) >> 20;
431 dma_cap->dbgmem = (hw_cap & XGMAC_HWFEAT_DBGMEMA) >> 19;
432 dma_cap->tsoen = (hw_cap & XGMAC_HWFEAT_TSOEN) >> 18;
433 dma_cap->sphen = (hw_cap & XGMAC_HWFEAT_SPHEN) >> 17;
434 dma_cap->dcben = (hw_cap & XGMAC_HWFEAT_DCBEN) >> 16;
435
436 dma_cap->addr64 = (hw_cap & XGMAC_HWFEAT_ADDR64) >> 14;
437 switch (dma_cap->addr64) {
438 case 0:
439 dma_cap->addr64 = 32;
440 break;
441 case 1:
442 dma_cap->addr64 = 40;
443 break;
444 case 2:
445 dma_cap->addr64 = 48;
446 break;
447 default:
448 dma_cap->addr64 = 32;
449 break;
450 }
451
452 dma_cap->advthword = (hw_cap & XGMAC_HWFEAT_ADVTHWORD) >> 13;
453 dma_cap->ptoen = (hw_cap & XGMAC_HWFEAT_PTOEN) >> 12;
454 dma_cap->osten = (hw_cap & XGMAC_HWFEAT_OSTEN) >> 11;
455 dma_cap->tx_fifo_size =
456 128 << ((hw_cap & XGMAC_HWFEAT_TXFIFOSIZE) >> 6);
457 dma_cap->pfcen = (hw_cap & XGMAC_HWFEAT_PFCEN) >> 5;
458 dma_cap->rx_fifo_size =
459 128 << ((hw_cap & XGMAC_HWFEAT_RXFIFOSIZE) >> 0);
460
461 /* MAC HW feature 2 */
462 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
463 dma_cap->aux_snapshot_n = (hw_cap & XGMAC_HWFEAT_AUXSNAPNUM) >> 28;
464 dma_cap->pps_out_num = (hw_cap & XGMAC_HWFEAT_PPSOUTNUM) >> 24;
465 dma_cap->number_tx_channel =
466 ((hw_cap & XGMAC_HWFEAT_TXCHCNT) >> 18) + 1;
467 dma_cap->number_rx_channel =
468 ((hw_cap & XGMAC_HWFEAT_RXCHCNT) >> 12) + 1;
469 dma_cap->number_tx_queues =
470 ((hw_cap & XGMAC_HWFEAT_TXQCNT) >> 6) + 1;
471 dma_cap->number_rx_queues =
472 ((hw_cap & XGMAC_HWFEAT_RXQCNT) >> 0) + 1;
473
474 /* MAC HW feature 3 */
475 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3);
476 dma_cap->tbs_ch_num = ((hw_cap & XGMAC_HWFEAT_TBSCH) >> 28) + 1;
477 dma_cap->tbssel = (hw_cap & XGMAC_HWFEAT_TBSSEL) >> 27;
478 dma_cap->fpesel = (hw_cap & XGMAC_HWFEAT_FPESEL) >> 26;
479 dma_cap->sgfsel = (hw_cap & XGMAC_HWFEAT_SGFSEL) >> 25;
480 dma_cap->estwid = (hw_cap & XGMAC_HWFEAT_ESTWID) >> 23;
481 dma_cap->estdep = (hw_cap & XGMAC_HWFEAT_ESTDEP) >> 20;
482 dma_cap->estsel = (hw_cap & XGMAC_HWFEAT_ESTSEL) >> 19;
483 dma_cap->ttsfd = (hw_cap & XGMAC_HWFEAT_TTSFD) >> 16;
484 dma_cap->asp = (hw_cap & XGMAC_HWFEAT_ASP) >> 14;
485 dma_cap->dvlan = (hw_cap & XGMAC_HWFEAT_DVLAN) >> 13;
486 dma_cap->frpes = (hw_cap & XGMAC_HWFEAT_FRPES) >> 11;
487 dma_cap->frpbs = (hw_cap & XGMAC_HWFEAT_FRPPB) >> 9;
488 dma_cap->pou_ost_en = (hw_cap & XGMAC_HWFEAT_POUOST) >> 8;
489 dma_cap->frppipe_num = ((hw_cap & XGMAC_HWFEAT_FRPPIPE) >> 5) + 1;
490 dma_cap->cbtisel = (hw_cap & XGMAC_HWFEAT_CBTISEL) >> 4;
491 dma_cap->frpsel = (hw_cap & XGMAC_HWFEAT_FRPSEL) >> 3;
492 dma_cap->nrvf_num = (hw_cap & XGMAC_HWFEAT_NRVF) >> 0;
493
494 /* MAC HW feature 4 */
495 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE4);
496 dma_cap->asp |= (hw_cap & XGMAC_HWFEAT_EASP) >> 2;
497 dma_cap->pcsel = (hw_cap & XGMAC_HWFEAT_PCSEL) >> 0;
498
499 return 0;
500 }
501
dwxgmac2_rx_watchdog(struct stmmac_priv * priv,void __iomem * ioaddr,u32 riwt,u32 queue)502 static void dwxgmac2_rx_watchdog(struct stmmac_priv *priv, void __iomem *ioaddr,
503 u32 riwt, u32 queue)
504 {
505 writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(queue));
506 }
507
dwxgmac2_set_rx_ring_len(struct stmmac_priv * priv,void __iomem * ioaddr,u32 len,u32 chan)508 static void dwxgmac2_set_rx_ring_len(struct stmmac_priv *priv,
509 void __iomem *ioaddr, u32 len, u32 chan)
510 {
511 writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan));
512 }
513
dwxgmac2_set_tx_ring_len(struct stmmac_priv * priv,void __iomem * ioaddr,u32 len,u32 chan)514 static void dwxgmac2_set_tx_ring_len(struct stmmac_priv *priv,
515 void __iomem *ioaddr, u32 len, u32 chan)
516 {
517 writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan));
518 }
519
dwxgmac2_set_rx_tail_ptr(struct stmmac_priv * priv,void __iomem * ioaddr,u32 ptr,u32 chan)520 static void dwxgmac2_set_rx_tail_ptr(struct stmmac_priv *priv,
521 void __iomem *ioaddr, u32 ptr, u32 chan)
522 {
523 writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan));
524 }
525
dwxgmac2_set_tx_tail_ptr(struct stmmac_priv * priv,void __iomem * ioaddr,u32 ptr,u32 chan)526 static void dwxgmac2_set_tx_tail_ptr(struct stmmac_priv *priv,
527 void __iomem *ioaddr, u32 ptr, u32 chan)
528 {
529 writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan));
530 }
531
dwxgmac2_enable_tso(struct stmmac_priv * priv,void __iomem * ioaddr,bool en,u32 chan)532 static void dwxgmac2_enable_tso(struct stmmac_priv *priv, void __iomem *ioaddr,
533 bool en, u32 chan)
534 {
535 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
536
537 if (en)
538 value |= XGMAC_TSE;
539 else
540 value &= ~XGMAC_TSE;
541
542 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
543 }
544
dwxgmac2_qmode(struct stmmac_priv * priv,void __iomem * ioaddr,u32 channel,u8 qmode)545 static void dwxgmac2_qmode(struct stmmac_priv *priv, void __iomem *ioaddr,
546 u32 channel, u8 qmode)
547 {
548 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
549 u32 flow = readl(ioaddr + XGMAC_RX_FLOW_CTRL);
550
551 value &= ~XGMAC_TXQEN;
552 if (qmode != MTL_QUEUE_AVB) {
553 value |= 0x2 << XGMAC_TXQEN_SHIFT;
554 writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel));
555 } else {
556 value |= 0x1 << XGMAC_TXQEN_SHIFT;
557 writel(flow & (~XGMAC_RFE), ioaddr + XGMAC_RX_FLOW_CTRL);
558 }
559
560 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
561 }
562
dwxgmac2_set_bfsize(struct stmmac_priv * priv,void __iomem * ioaddr,int bfsize,u32 chan)563 static void dwxgmac2_set_bfsize(struct stmmac_priv *priv, void __iomem *ioaddr,
564 int bfsize, u32 chan)
565 {
566 u32 value;
567
568 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
569 value &= ~XGMAC_RBSZ;
570 value |= bfsize << XGMAC_RBSZ_SHIFT;
571 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
572 }
573
dwxgmac2_enable_sph(struct stmmac_priv * priv,void __iomem * ioaddr,bool en,u32 chan)574 static void dwxgmac2_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr,
575 bool en, u32 chan)
576 {
577 u32 value = readl(ioaddr + XGMAC_RX_CONFIG);
578
579 value &= ~XGMAC_CONFIG_HDSMS;
580 value |= XGMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */
581 writel(value, ioaddr + XGMAC_RX_CONFIG);
582
583 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));
584 if (en)
585 value |= XGMAC_SPH;
586 else
587 value &= ~XGMAC_SPH;
588 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
589 }
590
dwxgmac2_enable_tbs(struct stmmac_priv * priv,void __iomem * ioaddr,bool en,u32 chan)591 static int dwxgmac2_enable_tbs(struct stmmac_priv *priv, void __iomem *ioaddr,
592 bool en, u32 chan)
593 {
594 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
595
596 if (en)
597 value |= XGMAC_EDSE;
598 else
599 value &= ~XGMAC_EDSE;
600
601 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
602
603 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)) & XGMAC_EDSE;
604 if (en && !value)
605 return -EIO;
606
607 writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL0);
608 writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL1);
609 writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL2);
610 writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL3);
611 return 0;
612 }
613
614 const struct stmmac_dma_ops dwxgmac210_dma_ops = {
615 .reset = dwxgmac2_dma_reset,
616 .init = dwxgmac2_dma_init,
617 .init_chan = dwxgmac2_dma_init_chan,
618 .init_rx_chan = dwxgmac2_dma_init_rx_chan,
619 .init_tx_chan = dwxgmac2_dma_init_tx_chan,
620 .axi = dwxgmac2_dma_axi,
621 .dump_regs = dwxgmac2_dma_dump_regs,
622 .dma_rx_mode = dwxgmac2_dma_rx_mode,
623 .dma_tx_mode = dwxgmac2_dma_tx_mode,
624 .enable_dma_irq = dwxgmac2_enable_dma_irq,
625 .disable_dma_irq = dwxgmac2_disable_dma_irq,
626 .start_tx = dwxgmac2_dma_start_tx,
627 .stop_tx = dwxgmac2_dma_stop_tx,
628 .start_rx = dwxgmac2_dma_start_rx,
629 .stop_rx = dwxgmac2_dma_stop_rx,
630 .dma_interrupt = dwxgmac2_dma_interrupt,
631 .get_hw_feature = dwxgmac2_get_hw_feature,
632 .rx_watchdog = dwxgmac2_rx_watchdog,
633 .set_rx_ring_len = dwxgmac2_set_rx_ring_len,
634 .set_tx_ring_len = dwxgmac2_set_tx_ring_len,
635 .set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,
636 .set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,
637 .enable_tso = dwxgmac2_enable_tso,
638 .qmode = dwxgmac2_qmode,
639 .set_bfsize = dwxgmac2_set_bfsize,
640 .enable_sph = dwxgmac2_enable_sph,
641 .enable_tbs = dwxgmac2_enable_tbs,
642 };
643