1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4 * DWC Ether MAC version 4.xx has been used for developing this code.
5 *
6 * This contains the functions to handle the dma.
7 *
8 * Copyright (C) 2015 STMicroelectronics Ltd
9 *
10 * Author: Alexandre Torgue <alexandre.torgue@st.com>
11 */
12
13 #include <linux/io.h>
14 #include "dwmac4.h"
15 #include "dwmac4_dma.h"
16 #include "stmmac.h"
17
dwmac4_dma_axi(void __iomem * ioaddr,struct stmmac_axi * axi)18 static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
19 {
20 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
21
22 pr_info("dwmac4: Master AXI performs %s burst length\n",
23 (value & DMA_SYS_BUS_FB) ? "fixed" : "any");
24
25 if (axi->axi_lpi_en)
26 value |= DMA_AXI_EN_LPI;
27 if (axi->axi_xit_frm)
28 value |= DMA_AXI_LPI_XIT_FRM;
29
30 value = u32_replace_bits(value, axi->axi_wr_osr_lmt,
31 DMA_AXI_WR_OSR_LMT);
32 value = u32_replace_bits(value, axi->axi_rd_osr_lmt,
33 DMA_AXI_RD_OSR_LMT);
34
35 /* Depending on the UNDEF bit the Master AXI will perform any burst
36 * length according to the BLEN programmed (by default all BLEN are
37 * set). Note that the UNDEF bit is readonly, and is the inverse of
38 * Bus Mode bit 16.
39 */
40 value = (value & ~DMA_AXI_BLEN_MASK) | axi->axi_blen_regval;
41
42 writel(value, ioaddr + DMA_SYS_BUS_MODE);
43 }
44
dwmac4_dma_init_rx_chan(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,dma_addr_t dma_rx_phy,u32 chan)45 static void dwmac4_dma_init_rx_chan(struct stmmac_priv *priv,
46 void __iomem *ioaddr,
47 struct stmmac_dma_cfg *dma_cfg,
48 dma_addr_t dma_rx_phy, u32 chan)
49 {
50 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
51 u32 value;
52 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
53
54 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
55 value = value | FIELD_PREP(DMA_CHAN_RX_CTRL_RXPBL_MASK, rxpbl);
56 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
57
58 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
59 writel(upper_32_bits(dma_rx_phy),
60 ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(dwmac4_addrs, chan));
61
62 writel(lower_32_bits(dma_rx_phy),
63 ioaddr + DMA_CHAN_RX_BASE_ADDR(dwmac4_addrs, chan));
64 }
65
dwmac4_dma_init_tx_chan(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,dma_addr_t dma_tx_phy,u32 chan)66 static void dwmac4_dma_init_tx_chan(struct stmmac_priv *priv,
67 void __iomem *ioaddr,
68 struct stmmac_dma_cfg *dma_cfg,
69 dma_addr_t dma_tx_phy, u32 chan)
70 {
71 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
72 u32 value;
73 u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
74
75 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
76 value = value | FIELD_PREP(DMA_CHAN_TX_CTRL_TXPBL_MASK, txpbl);
77
78 /* Enable OSP to get best performance */
79 value |= DMA_CONTROL_OSP;
80
81 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
82
83 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
84 writel(upper_32_bits(dma_tx_phy),
85 ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(dwmac4_addrs, chan));
86
87 writel(lower_32_bits(dma_tx_phy),
88 ioaddr + DMA_CHAN_TX_BASE_ADDR(dwmac4_addrs, chan));
89 }
90
dwmac4_dma_init_channel(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,u32 chan)91 static void dwmac4_dma_init_channel(struct stmmac_priv *priv,
92 void __iomem *ioaddr,
93 struct stmmac_dma_cfg *dma_cfg, u32 chan)
94 {
95 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
96 u32 value;
97
98 /* common channel control register config */
99 value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
100 if (dma_cfg->pblx8)
101 value = value | DMA_CHAN_CTRL_PBLX8;
102 writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
103
104 /* Mask interrupts by writing to CSR7 */
105 writel(DMA_CHAN_INTR_DEFAULT_MASK,
106 ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
107 }
108
dwmac4_dma_deinit_channel(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan)109 static void dwmac4_dma_deinit_channel(struct stmmac_priv *priv,
110 void __iomem *ioaddr, u32 chan)
111 {
112 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
113 u32 value;
114
115 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
116 value &= ~DMA_CHAN_INTR_DEFAULT_MASK;
117 writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
118 }
119
dwmac410_dma_init_channel(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,u32 chan)120 static void dwmac410_dma_init_channel(struct stmmac_priv *priv,
121 void __iomem *ioaddr,
122 struct stmmac_dma_cfg *dma_cfg, u32 chan)
123 {
124 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
125 u32 value;
126
127 /* common channel control register config */
128 value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
129 if (dma_cfg->pblx8)
130 value = value | DMA_CHAN_CTRL_PBLX8;
131
132 writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
133
134 /* Mask interrupts by writing to CSR7 */
135 writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,
136 ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
137 }
138
dwmac410_dma_deinit_channel(struct stmmac_priv * priv,void __iomem * ioaddr,u32 chan)139 static void dwmac410_dma_deinit_channel(struct stmmac_priv *priv,
140 void __iomem *ioaddr, u32 chan)
141 {
142 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
143 u32 value;
144
145 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
146 value &= ~DMA_CHAN_INTR_DEFAULT_MASK_4_10;
147 writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
148 }
149
dwmac4_dma_init(void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg)150 static void dwmac4_dma_init(void __iomem *ioaddr,
151 struct stmmac_dma_cfg *dma_cfg)
152 {
153 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
154
155 /* Set the Fixed burst mode */
156 if (dma_cfg->fixed_burst)
157 value |= DMA_SYS_BUS_FB;
158
159 /* Mixed Burst has no effect when fb is set */
160 if (dma_cfg->mixed_burst)
161 value |= DMA_SYS_BUS_MB;
162
163 if (dma_cfg->aal)
164 value |= DMA_SYS_BUS_AAL;
165
166 if (dma_cfg->eame)
167 value |= DMA_SYS_BUS_EAME;
168
169 writel(value, ioaddr + DMA_SYS_BUS_MODE);
170
171 value = readl(ioaddr + DMA_BUS_MODE);
172
173 if (dma_cfg->multi_msi_en)
174 value = u32_replace_bits(value, DMA_BUS_MODE_INTM_MODE1,
175 DMA_BUS_MODE_INTM_MASK);
176
177 if (dma_cfg->dche)
178 value |= DMA_BUS_MODE_DCHE;
179
180 writel(value, ioaddr + DMA_BUS_MODE);
181
182 }
183
_dwmac4_dump_dma_regs(struct stmmac_priv * priv,void __iomem * ioaddr,u32 channel,u32 * reg_space)184 static void _dwmac4_dump_dma_regs(struct stmmac_priv *priv,
185 void __iomem *ioaddr, u32 channel,
186 u32 *reg_space)
187 {
188 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
189 const struct dwmac4_addrs *default_addrs = NULL;
190
191 /* Purposely save the registers in the "normal" layout, regardless of
192 * platform modifications, to keep reg_space size constant
193 */
194 reg_space[DMA_CHAN_CONTROL(default_addrs, channel) / 4] =
195 readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, channel));
196 reg_space[DMA_CHAN_TX_CONTROL(default_addrs, channel) / 4] =
197 readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, channel));
198 reg_space[DMA_CHAN_RX_CONTROL(default_addrs, channel) / 4] =
199 readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, channel));
200 reg_space[DMA_CHAN_TX_BASE_ADDR_HI(default_addrs, channel) / 4] =
201 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(dwmac4_addrs, channel));
202 reg_space[DMA_CHAN_TX_BASE_ADDR(default_addrs, channel) / 4] =
203 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(dwmac4_addrs, channel));
204 reg_space[DMA_CHAN_RX_BASE_ADDR_HI(default_addrs, channel) / 4] =
205 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(dwmac4_addrs, channel));
206 reg_space[DMA_CHAN_RX_BASE_ADDR(default_addrs, channel) / 4] =
207 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(dwmac4_addrs, channel));
208 reg_space[DMA_CHAN_TX_END_ADDR(default_addrs, channel) / 4] =
209 readl(ioaddr + DMA_CHAN_TX_END_ADDR(dwmac4_addrs, channel));
210 reg_space[DMA_CHAN_RX_END_ADDR(default_addrs, channel) / 4] =
211 readl(ioaddr + DMA_CHAN_RX_END_ADDR(dwmac4_addrs, channel));
212 reg_space[DMA_CHAN_TX_RING_LEN(default_addrs, channel) / 4] =
213 readl(ioaddr + DMA_CHAN_TX_RING_LEN(dwmac4_addrs, channel));
214 reg_space[DMA_CHAN_RX_RING_LEN(default_addrs, channel) / 4] =
215 readl(ioaddr + DMA_CHAN_RX_RING_LEN(dwmac4_addrs, channel));
216 reg_space[DMA_CHAN_INTR_ENA(default_addrs, channel) / 4] =
217 readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, channel));
218 reg_space[DMA_CHAN_RX_WATCHDOG(default_addrs, channel) / 4] =
219 readl(ioaddr + DMA_CHAN_RX_WATCHDOG(dwmac4_addrs, channel));
220 reg_space[DMA_CHAN_SLOT_CTRL_STATUS(default_addrs, channel) / 4] =
221 readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(dwmac4_addrs, channel));
222 reg_space[DMA_CHAN_CUR_TX_DESC(default_addrs, channel) / 4] =
223 readl(ioaddr + DMA_CHAN_CUR_TX_DESC(dwmac4_addrs, channel));
224 reg_space[DMA_CHAN_CUR_RX_DESC(default_addrs, channel) / 4] =
225 readl(ioaddr + DMA_CHAN_CUR_RX_DESC(dwmac4_addrs, channel));
226 reg_space[DMA_CHAN_CUR_TX_BUF_ADDR_HI(default_addrs, channel) / 4] =
227 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR_HI(dwmac4_addrs, channel));
228 reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(default_addrs, channel) / 4] =
229 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(dwmac4_addrs, channel));
230 reg_space[DMA_CHAN_CUR_RX_BUF_ADDR_HI(default_addrs, channel) / 4] =
231 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR_HI(dwmac4_addrs, channel));
232 reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(default_addrs, channel) / 4] =
233 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(dwmac4_addrs, channel));
234 reg_space[DMA_CHAN_STATUS(default_addrs, channel) / 4] =
235 readl(ioaddr + DMA_CHAN_STATUS(dwmac4_addrs, channel));
236 }
237
dwmac4_dump_dma_regs(struct stmmac_priv * priv,void __iomem * ioaddr,u32 * reg_space)238 static void dwmac4_dump_dma_regs(struct stmmac_priv *priv, void __iomem *ioaddr,
239 u32 *reg_space)
240 {
241 int i;
242
243 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
244 _dwmac4_dump_dma_regs(priv, ioaddr, i, reg_space);
245 }
246
dwmac4_rx_watchdog(struct stmmac_priv * priv,void __iomem * ioaddr,u32 riwt,u32 queue)247 static void dwmac4_rx_watchdog(struct stmmac_priv *priv, void __iomem *ioaddr,
248 u32 riwt, u32 queue)
249 {
250 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
251
252 writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(dwmac4_addrs, queue));
253 }
254
dwmac4_dma_rx_chan_op_mode(struct stmmac_priv * priv,void __iomem * ioaddr,int mode,u32 channel,int fifosz,u8 qmode)255 static void dwmac4_dma_rx_chan_op_mode(struct stmmac_priv *priv,
256 void __iomem *ioaddr, int mode,
257 u32 channel, int fifosz, u8 qmode)
258 {
259 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
260 unsigned int rqs = fifosz / 256 - 1;
261 u32 mtl_rx_op;
262
263 mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(dwmac4_addrs, channel));
264
265 mtl_rx_op |= MTL_OP_MODE_DIS_TCP_EF;
266
267 if (mode == SF_DMA_MODE) {
268 pr_debug("GMAC: enable RX store and forward mode\n");
269 mtl_rx_op |= MTL_OP_MODE_RSF;
270 } else {
271 pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);
272 mtl_rx_op &= ~MTL_OP_MODE_RSF;
273 mtl_rx_op &= ~MTL_OP_MODE_RTC_MASK;
274 if (mode <= 32)
275 mtl_rx_op |= MTL_OP_MODE_RTC_32;
276 else if (mode <= 64)
277 mtl_rx_op |= MTL_OP_MODE_RTC_64;
278 else if (mode <= 96)
279 mtl_rx_op |= MTL_OP_MODE_RTC_96;
280 else
281 mtl_rx_op |= MTL_OP_MODE_RTC_128;
282 }
283
284 mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK;
285 mtl_rx_op |= FIELD_PREP(MTL_OP_MODE_RQS_MASK, rqs);
286
287 /* Enable flow control only if each channel gets 4 KiB or more FIFO and
288 * only if channel is not an AVB channel.
289 */
290 if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
291 unsigned int rfd, rfa;
292
293 mtl_rx_op |= MTL_OP_MODE_EHFC;
294
295 /* Set Threshold for Activating Flow Control to min 2 frames,
296 * i.e. 1500 * 2 = 3000 bytes.
297 *
298 * Set Threshold for Deactivating Flow Control to min 1 frame,
299 * i.e. 1500 bytes.
300 */
301 switch (fifosz) {
302 case 4096:
303 /* This violates the above formula because of FIFO size
304 * limit therefore overflow may occur in spite of this.
305 */
306 rfd = 0x03; /* Full-2.5K */
307 rfa = 0x01; /* Full-1.5K */
308 break;
309
310 default:
311 rfd = 0x07; /* Full-4.5K */
312 rfa = 0x04; /* Full-3K */
313 break;
314 }
315
316 mtl_rx_op = u32_replace_bits(mtl_rx_op, rfd,
317 MTL_OP_MODE_RFD_MASK);
318 mtl_rx_op = u32_replace_bits(mtl_rx_op, rfa,
319 MTL_OP_MODE_RFA_MASK);
320 }
321
322 writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(dwmac4_addrs, channel));
323 }
324
dwmac4_dma_tx_chan_op_mode(struct stmmac_priv * priv,void __iomem * ioaddr,int mode,u32 channel,int fifosz,u8 qmode)325 static void dwmac4_dma_tx_chan_op_mode(struct stmmac_priv *priv,
326 void __iomem *ioaddr, int mode,
327 u32 channel, int fifosz, u8 qmode)
328 {
329 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
330 u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs,
331 channel));
332 unsigned int tqs = fifosz / 256 - 1;
333
334 if (mode == SF_DMA_MODE) {
335 pr_debug("GMAC: enable TX store and forward mode\n");
336 /* Transmit COE type 2 cannot be done in cut-through mode. */
337 mtl_tx_op |= MTL_OP_MODE_TSF;
338 } else {
339 pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);
340 mtl_tx_op &= ~MTL_OP_MODE_TSF;
341 mtl_tx_op &= ~MTL_OP_MODE_TTC_MASK;
342 /* Set the transmit threshold */
343 if (mode <= 32)
344 mtl_tx_op |= MTL_OP_MODE_TTC_32;
345 else if (mode <= 64)
346 mtl_tx_op |= MTL_OP_MODE_TTC_64;
347 else if (mode <= 96)
348 mtl_tx_op |= MTL_OP_MODE_TTC_96;
349 else if (mode <= 128)
350 mtl_tx_op |= MTL_OP_MODE_TTC_128;
351 else if (mode <= 192)
352 mtl_tx_op |= MTL_OP_MODE_TTC_192;
353 else if (mode <= 256)
354 mtl_tx_op |= MTL_OP_MODE_TTC_256;
355 else if (mode <= 384)
356 mtl_tx_op |= MTL_OP_MODE_TTC_384;
357 else
358 mtl_tx_op |= MTL_OP_MODE_TTC_512;
359 }
360 /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
361 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
362 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
363 * with reset values: TXQEN off, TQS 256 bytes.
364 *
365 * TXQEN must be written for multi-channel operation and TQS must
366 * reflect the available fifo size per queue (total fifo size / number
367 * of enabled queues).
368 */
369 mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
370 if (qmode != MTL_QUEUE_AVB)
371 mtl_tx_op |= MTL_OP_MODE_TXQEN;
372 else
373 mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;
374
375 mtl_tx_op = u32_replace_bits(mtl_tx_op, tqs, MTL_OP_MODE_TQS_MASK);
376
377 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));
378 }
379
dwmac4_get_hw_feature(void __iomem * ioaddr,struct dma_features * dma_cap)380 static int dwmac4_get_hw_feature(void __iomem *ioaddr,
381 struct dma_features *dma_cap)
382 {
383 u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
384
385 /* MAC HW feature0 */
386 dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
387 dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
388 dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
389 dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
390 dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
391 dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
392 dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
393 dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;
394 dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;
395 /* MMC */
396 dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;
397 /* IEEE 1588-2008 */
398 dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;
399 /* 802.3az - Energy-Efficient Ethernet (EEE) */
400 dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;
401 /* TX and RX csum */
402 dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
403 dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
404 dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;
405 dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9;
406
407 dma_cap->actphyif = FIELD_GET(DMA_HW_FEAT_ACTPHYIF, hw_cap);
408
409 /* MAC HW feature1 */
410 hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
411 dma_cap->l3l4fnum = (hw_cap & GMAC_HW_FEAT_L3L4FNUM) >> 27;
412 dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;
413 dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
414 dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
415 dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17;
416 dma_cap->dcben = (hw_cap & GMAC_HW_FEAT_DCBEN) >> 16;
417
418 dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14;
419 switch (dma_cap->addr64) {
420 case 0:
421 dma_cap->addr64 = 32;
422 break;
423 case 1:
424 dma_cap->addr64 = 40;
425 break;
426 case 2:
427 dma_cap->addr64 = 48;
428 break;
429 default:
430 dma_cap->addr64 = 32;
431 break;
432 }
433
434 /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by
435 * shifting and store the sizes in bytes.
436 */
437 dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6);
438 dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0);
439 /* MAC HW feature2 */
440 hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);
441 /* TX and RX number of channels */
442 dma_cap->number_rx_channel =
443 ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
444 dma_cap->number_tx_channel =
445 ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
446 /* TX and RX number of queues */
447 dma_cap->number_rx_queues =
448 ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1;
449 dma_cap->number_tx_queues =
450 ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1;
451 /* PPS output */
452 dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24;
453
454 /* IEEE 1588-2002 */
455 dma_cap->time_stamp = 0;
456 /* Number of Auxiliary Snapshot Inputs */
457 dma_cap->aux_snapshot_n = (hw_cap & GMAC_HW_FEAT_AUXSNAPNUM) >> 28;
458
459 /* MAC HW feature3 */
460 hw_cap = readl(ioaddr + GMAC_HW_FEATURE3);
461
462 /* 5.10 Features */
463 dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;
464 dma_cap->tbssel = (hw_cap & GMAC_HW_FEAT_TBSSEL) >> 27;
465 dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26;
466 dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20;
467 dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17;
468 dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16;
469 dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;
470 dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;
471 dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;
472 dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5;
473
474 return 0;
475 }
476
477 /* Enable/disable TSO feature and set MSS */
dwmac4_enable_tso(struct stmmac_priv * priv,void __iomem * ioaddr,bool en,u32 chan)478 static void dwmac4_enable_tso(struct stmmac_priv *priv, void __iomem *ioaddr,
479 bool en, u32 chan)
480 {
481 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
482 u32 value;
483
484 if (en) {
485 /* enable TSO */
486 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
487 writel(value | DMA_CONTROL_TSE,
488 ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
489 } else {
490 /* enable TSO */
491 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
492 writel(value & ~DMA_CONTROL_TSE,
493 ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
494 }
495 }
496
dwmac4_qmode(struct stmmac_priv * priv,void __iomem * ioaddr,u32 channel,u8 qmode)497 static void dwmac4_qmode(struct stmmac_priv *priv, void __iomem *ioaddr,
498 u32 channel, u8 qmode)
499 {
500 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
501 u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs,
502 channel));
503
504 mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
505 if (qmode != MTL_QUEUE_AVB)
506 mtl_tx_op |= MTL_OP_MODE_TXQEN;
507 else
508 mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;
509
510 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));
511 }
512
dwmac4_set_bfsize(struct stmmac_priv * priv,void __iomem * ioaddr,int bfsize,u32 chan)513 static void dwmac4_set_bfsize(struct stmmac_priv *priv, void __iomem *ioaddr,
514 int bfsize, u32 chan)
515 {
516 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
517 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
518
519 value = u32_replace_bits(value, bfsize, DMA_RBSZ_MASK);
520
521 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
522 }
523
dwmac4_enable_sph(struct stmmac_priv * priv,void __iomem * ioaddr,bool en,u32 chan)524 static void dwmac4_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr,
525 bool en, u32 chan)
526 {
527 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
528 u32 value = readl(ioaddr + GMAC_EXT_CONFIG);
529
530 value &= ~GMAC_CONFIG_HDSMS;
531 value |= GMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */
532 writel(value, ioaddr + GMAC_EXT_CONFIG);
533
534 value = readl(ioaddr + GMAC_EXT_CFG1);
535 value |= GMAC_CONFIG1_SPLM(1); /* Split mode set to L2OFST */
536 value |= GMAC_CONFIG1_SAVE_EN; /* Enable Split AV mode */
537 writel(value, ioaddr + GMAC_EXT_CFG1);
538
539 value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
540 if (en)
541 value |= DMA_CONTROL_SPH;
542 else
543 value &= ~DMA_CONTROL_SPH;
544 writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
545 }
546
dwmac4_enable_tbs(struct stmmac_priv * priv,void __iomem * ioaddr,bool en,u32 chan)547 static int dwmac4_enable_tbs(struct stmmac_priv *priv, void __iomem *ioaddr,
548 bool en, u32 chan)
549 {
550 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
551 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
552
553 if (en)
554 value |= DMA_CONTROL_EDSE;
555 else
556 value &= ~DMA_CONTROL_EDSE;
557
558 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
559
560 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs,
561 chan)) & DMA_CONTROL_EDSE;
562 if (en && !value)
563 return -EIO;
564
565 writel(DMA_TBS_DEF_FTOS, ioaddr + DMA_TBS_CTRL);
566 return 0;
567 }
568
569 const struct stmmac_dma_ops dwmac4_dma_ops = {
570 .reset = dwmac4_dma_reset,
571 .init = dwmac4_dma_init,
572 .init_chan = dwmac4_dma_init_channel,
573 .deinit_chan = dwmac4_dma_deinit_channel,
574 .init_rx_chan = dwmac4_dma_init_rx_chan,
575 .init_tx_chan = dwmac4_dma_init_tx_chan,
576 .axi = dwmac4_dma_axi,
577 .dump_regs = dwmac4_dump_dma_regs,
578 .dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
579 .dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
580 .enable_dma_irq = dwmac4_enable_dma_irq,
581 .disable_dma_irq = dwmac4_disable_dma_irq,
582 .start_tx = dwmac4_dma_start_tx,
583 .stop_tx = dwmac4_dma_stop_tx,
584 .start_rx = dwmac4_dma_start_rx,
585 .stop_rx = dwmac4_dma_stop_rx,
586 .dma_interrupt = dwmac4_dma_interrupt,
587 .get_hw_feature = dwmac4_get_hw_feature,
588 .rx_watchdog = dwmac4_rx_watchdog,
589 .set_rx_ring_len = dwmac4_set_rx_ring_len,
590 .set_tx_ring_len = dwmac4_set_tx_ring_len,
591 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
592 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
593 .enable_tso = dwmac4_enable_tso,
594 .qmode = dwmac4_qmode,
595 .set_bfsize = dwmac4_set_bfsize,
596 .enable_sph = dwmac4_enable_sph,
597 };
598
599 const struct stmmac_dma_ops dwmac410_dma_ops = {
600 .reset = dwmac4_dma_reset,
601 .init = dwmac4_dma_init,
602 .init_chan = dwmac410_dma_init_channel,
603 .deinit_chan = dwmac410_dma_deinit_channel,
604 .init_rx_chan = dwmac4_dma_init_rx_chan,
605 .init_tx_chan = dwmac4_dma_init_tx_chan,
606 .axi = dwmac4_dma_axi,
607 .dump_regs = dwmac4_dump_dma_regs,
608 .dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
609 .dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
610 .enable_dma_irq = dwmac4_enable_dma_irq,
611 .disable_dma_irq = dwmac4_disable_dma_irq,
612 .start_tx = dwmac4_dma_start_tx,
613 .stop_tx = dwmac4_dma_stop_tx,
614 .start_rx = dwmac4_dma_start_rx,
615 .stop_rx = dwmac4_dma_stop_rx,
616 .dma_interrupt = dwmac4_dma_interrupt,
617 .get_hw_feature = dwmac4_get_hw_feature,
618 .rx_watchdog = dwmac4_rx_watchdog,
619 .set_rx_ring_len = dwmac4_set_rx_ring_len,
620 .set_tx_ring_len = dwmac4_set_tx_ring_len,
621 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
622 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
623 .enable_tso = dwmac4_enable_tso,
624 .qmode = dwmac4_qmode,
625 .set_bfsize = dwmac4_set_bfsize,
626 .enable_sph = dwmac4_enable_sph,
627 .enable_tbs = dwmac4_enable_tbs,
628 };
629