1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 4 * DWC Ether MAC version 4.00 has been used for developing this code. 5 * 6 * This only implements the mac core functions for this chip. 7 * 8 * Copyright (C) 2015 STMicroelectronics Ltd 9 * 10 * Author: Alexandre Torgue <alexandre.torgue@st.com> 11 */ 12 13 #include <linux/crc32.h> 14 #include <linux/slab.h> 15 #include <linux/ethtool.h> 16 #include <linux/io.h> 17 #include <linux/iopoll.h> 18 #include "stmmac.h" 19 #include "stmmac_fpe.h" 20 #include "stmmac_pcs.h" 21 #include "stmmac_vlan.h" 22 #include "dwmac4.h" 23 #include "dwmac5.h" 24 25 static const struct stmmac_pcs_info dwmac4_pcs_info = { 26 .pcs_offset = GMAC_PCS_BASE, 27 .rgsmii_offset = GMAC_PHYIF_CONTROL_STATUS, 28 .rgsmii_status_mask = GMAC_PHYIF_CTRLSTATUS_RSGMII_MASK, 29 .int_mask = GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE, 30 }; 31 32 static int dwmac4_pcs_init(struct stmmac_priv *priv) 33 { 34 if (!priv->dma_cap.pcs) 35 return 0; 36 37 return stmmac_integrated_pcs_init(priv, &dwmac4_pcs_info); 38 } 39 40 static void dwmac4_core_init(struct mac_device_info *hw, 41 struct net_device *dev) 42 { 43 struct stmmac_priv *priv = netdev_priv(dev); 44 void __iomem *ioaddr = hw->pcsr; 45 unsigned long clk_rate; 46 u32 value; 47 48 value = readl(ioaddr + GMAC_CONFIG); 49 writel(value | GMAC_CORE_INIT, ioaddr + GMAC_CONFIG); 50 51 /* Configure LPI 1us counter to number of CSR clock ticks in 1us - 1. 52 * Platforms with firmware-managed clocks may not expose the CSR clock 53 * to linux, in which case there's no meaningful value to program. 54 */ 55 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 56 if (clk_rate >= 1000000) 57 writel((clk_rate / 1000000) - 1, 58 ioaddr + GMAC4_MAC_ONEUS_TIC_COUNTER); 59 60 /* Enable GMAC interrupts */ 61 writel(GMAC_INT_DEFAULT_ENABLE, ioaddr + GMAC_INT_EN); 62 63 if (GMAC_INT_DEFAULT_ENABLE & GMAC_INT_TSIE) 64 init_waitqueue_head(&priv->tstamp_busy_wait); 65 } 66 67 static void dwmac4_irq_modify(struct mac_device_info *hw, u32 disable, 68 u32 enable) 69 { 70 void __iomem *int_mask = hw->pcsr + GMAC_INT_EN; 71 unsigned long flags; 72 u32 value; 73 74 spin_lock_irqsave(&hw->irq_ctrl_lock, flags); 75 value = readl(int_mask) & ~disable; 76 value |= enable; 77 writel(value, int_mask); 78 spin_unlock_irqrestore(&hw->irq_ctrl_lock, flags); 79 } 80 81 static void dwmac4_update_caps(struct stmmac_priv *priv) 82 { 83 if (priv->plat->tx_queues_to_use > 1) 84 priv->hw->link.caps &= ~(MAC_10HD | MAC_100HD | MAC_1000HD); 85 else 86 priv->hw->link.caps |= (MAC_10HD | MAC_100HD | MAC_1000HD); 87 } 88 89 static void dwmac4_rx_queue_enable(struct mac_device_info *hw, 90 u8 mode, u32 queue) 91 { 92 void __iomem *ioaddr = hw->pcsr; 93 u32 value = readl(ioaddr + GMAC_RXQ_CTRL0); 94 95 value &= GMAC_RX_QUEUE_CLEAR(queue); 96 if (mode == MTL_QUEUE_AVB) 97 value |= GMAC_RX_AV_QUEUE_ENABLE(queue); 98 else if (mode == MTL_QUEUE_DCB) 99 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue); 100 101 writel(value, ioaddr + GMAC_RXQ_CTRL0); 102 } 103 104 static void dwmac4_rx_queue_priority(struct mac_device_info *hw, 105 u32 prio, u32 queue) 106 { 107 void __iomem *ioaddr = hw->pcsr; 108 u32 clear_mask = 0; 109 u32 ctrl2, ctrl3; 110 int i; 111 112 ctrl2 = readl(ioaddr + GMAC_RXQ_CTRL2); 113 ctrl3 = readl(ioaddr + GMAC_RXQ_CTRL3); 114 115 /* The software must ensure that the same priority 116 * is not mapped to multiple Rx queues 117 */ 118 for (i = 0; i < 4; i++) 119 clear_mask |= ((prio << GMAC_RXQCTRL_PSRQX_SHIFT(i)) & 120 GMAC_RXQCTRL_PSRQX_MASK(i)); 121 122 ctrl2 &= ~clear_mask; 123 ctrl3 &= ~clear_mask; 124 125 /* First assign new priorities to a queue, then 126 * clear them from others queues 127 */ 128 if (queue < 4) { 129 ctrl2 |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) & 130 GMAC_RXQCTRL_PSRQX_MASK(queue); 131 132 writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2); 133 writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3); 134 } else { 135 queue -= 4; 136 137 ctrl3 |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) & 138 GMAC_RXQCTRL_PSRQX_MASK(queue); 139 140 writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3); 141 writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2); 142 } 143 } 144 145 static void dwmac4_tx_queue_priority(struct mac_device_info *hw, 146 u32 prio, u32 queue) 147 { 148 void __iomem *ioaddr = hw->pcsr; 149 u32 base_register; 150 u32 value; 151 152 base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1; 153 if (queue >= 4) 154 queue -= 4; 155 156 value = readl(ioaddr + base_register); 157 158 value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue); 159 value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) & 160 GMAC_TXQCTRL_PSTQX_MASK(queue); 161 162 writel(value, ioaddr + base_register); 163 } 164 165 static void dwmac4_rx_queue_routing(struct mac_device_info *hw, 166 u8 packet, u32 queue) 167 { 168 void __iomem *ioaddr = hw->pcsr; 169 u32 value; 170 171 static const struct stmmac_rx_routing route_possibilities[] = { 172 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT }, 173 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT }, 174 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT }, 175 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT }, 176 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT }, 177 }; 178 179 value = readl(ioaddr + GMAC_RXQ_CTRL1); 180 181 /* routing configuration */ 182 value &= ~route_possibilities[packet - 1].reg_mask; 183 value |= (queue << route_possibilities[packet-1].reg_shift) & 184 route_possibilities[packet - 1].reg_mask; 185 186 /* some packets require extra ops */ 187 if (packet == PACKET_AVCPQ) { 188 value &= ~GMAC_RXQCTRL_TACPQE; 189 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT; 190 } else if (packet == PACKET_MCBCQ) { 191 value &= ~GMAC_RXQCTRL_MCBCQEN; 192 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT; 193 } 194 195 writel(value, ioaddr + GMAC_RXQ_CTRL1); 196 } 197 198 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw, 199 u32 rx_alg) 200 { 201 void __iomem *ioaddr = hw->pcsr; 202 u32 value = readl(ioaddr + MTL_OPERATION_MODE); 203 204 value &= ~MTL_OPERATION_RAA; 205 switch (rx_alg) { 206 case MTL_RX_ALGORITHM_SP: 207 value |= MTL_OPERATION_RAA_SP; 208 break; 209 case MTL_RX_ALGORITHM_WSP: 210 value |= MTL_OPERATION_RAA_WSP; 211 break; 212 default: 213 break; 214 } 215 216 writel(value, ioaddr + MTL_OPERATION_MODE); 217 } 218 219 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw, 220 u32 tx_alg) 221 { 222 void __iomem *ioaddr = hw->pcsr; 223 u32 value = readl(ioaddr + MTL_OPERATION_MODE); 224 225 value &= ~MTL_OPERATION_SCHALG_MASK; 226 switch (tx_alg) { 227 case MTL_TX_ALGORITHM_WRR: 228 value |= MTL_OPERATION_SCHALG_WRR; 229 break; 230 case MTL_TX_ALGORITHM_WFQ: 231 value |= MTL_OPERATION_SCHALG_WFQ; 232 break; 233 case MTL_TX_ALGORITHM_DWRR: 234 value |= MTL_OPERATION_SCHALG_DWRR; 235 break; 236 case MTL_TX_ALGORITHM_SP: 237 value |= MTL_OPERATION_SCHALG_SP; 238 break; 239 default: 240 break; 241 } 242 243 writel(value, ioaddr + MTL_OPERATION_MODE); 244 } 245 246 static void dwmac4_set_mtl_tx_queue_weight(struct stmmac_priv *priv, 247 struct mac_device_info *hw, 248 u32 weight, u32 queue) 249 { 250 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 251 void __iomem *ioaddr = hw->pcsr; 252 u32 value = readl(ioaddr + mtl_txqx_weight_base_addr(dwmac4_addrs, 253 queue)); 254 255 value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK; 256 value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK; 257 writel(value, ioaddr + mtl_txqx_weight_base_addr(dwmac4_addrs, queue)); 258 } 259 260 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan) 261 { 262 void __iomem *ioaddr = hw->pcsr; 263 u32 value; 264 265 if (queue < 4) { 266 value = readl(ioaddr + MTL_RXQ_DMA_MAP0); 267 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue); 268 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue); 269 writel(value, ioaddr + MTL_RXQ_DMA_MAP0); 270 } else { 271 value = readl(ioaddr + MTL_RXQ_DMA_MAP1); 272 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue - 4); 273 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue - 4); 274 writel(value, ioaddr + MTL_RXQ_DMA_MAP1); 275 } 276 } 277 278 static void dwmac4_config_cbs(struct stmmac_priv *priv, 279 struct mac_device_info *hw, 280 u32 send_slope, u32 idle_slope, 281 u32 high_credit, u32 low_credit, u32 queue) 282 { 283 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 284 void __iomem *ioaddr = hw->pcsr; 285 u32 value; 286 287 pr_debug("Queue %d configured as AVB. Parameters:\n", queue); 288 pr_debug("\tsend_slope: 0x%08x\n", send_slope); 289 pr_debug("\tidle_slope: 0x%08x\n", idle_slope); 290 pr_debug("\thigh_credit: 0x%08x\n", high_credit); 291 pr_debug("\tlow_credit: 0x%08x\n", low_credit); 292 293 /* enable AV algorithm */ 294 value = readl(ioaddr + mtl_etsx_ctrl_base_addr(dwmac4_addrs, queue)); 295 value |= MTL_ETS_CTRL_AVALG; 296 value |= MTL_ETS_CTRL_CC; 297 writel(value, ioaddr + mtl_etsx_ctrl_base_addr(dwmac4_addrs, queue)); 298 299 /* configure send slope */ 300 value = readl(ioaddr + mtl_send_slp_credx_base_addr(dwmac4_addrs, 301 queue)); 302 value &= ~MTL_SEND_SLP_CRED_SSC_MASK; 303 value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK; 304 writel(value, ioaddr + mtl_send_slp_credx_base_addr(dwmac4_addrs, 305 queue)); 306 307 /* configure idle slope (same register as tx weight) */ 308 dwmac4_set_mtl_tx_queue_weight(priv, hw, idle_slope, queue); 309 310 /* configure high credit */ 311 value = readl(ioaddr + mtl_high_credx_base_addr(dwmac4_addrs, queue)); 312 value &= ~MTL_HIGH_CRED_HC_MASK; 313 value |= high_credit & MTL_HIGH_CRED_HC_MASK; 314 writel(value, ioaddr + mtl_high_credx_base_addr(dwmac4_addrs, queue)); 315 316 /* configure high credit */ 317 value = readl(ioaddr + mtl_low_credx_base_addr(dwmac4_addrs, queue)); 318 value &= ~MTL_HIGH_CRED_LC_MASK; 319 value |= low_credit & MTL_HIGH_CRED_LC_MASK; 320 writel(value, ioaddr + mtl_low_credx_base_addr(dwmac4_addrs, queue)); 321 } 322 323 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space) 324 { 325 void __iomem *ioaddr = hw->pcsr; 326 int i; 327 328 for (i = 0; i < GMAC_REG_NUM; i++) 329 reg_space[i] = readl(ioaddr + i * 4); 330 } 331 332 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw) 333 { 334 void __iomem *ioaddr = hw->pcsr; 335 u32 value = readl(ioaddr + GMAC_CONFIG); 336 337 if (hw->rx_csum) 338 value |= GMAC_CONFIG_IPC; 339 else 340 value &= ~GMAC_CONFIG_IPC; 341 342 writel(value, ioaddr + GMAC_CONFIG); 343 344 value = readl(ioaddr + GMAC_CONFIG); 345 346 return !!(value & GMAC_CONFIG_IPC); 347 } 348 349 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode) 350 { 351 void __iomem *ioaddr = hw->pcsr; 352 unsigned int pmt = 0; 353 u32 config; 354 355 if (mode & WAKE_MAGIC) { 356 pr_debug("GMAC: WOL Magic frame\n"); 357 pmt |= power_down | magic_pkt_en; 358 } 359 if (mode & WAKE_UCAST) { 360 pr_debug("GMAC: WOL on global unicast\n"); 361 pmt |= power_down | global_unicast | wake_up_frame_en; 362 } 363 364 if (pmt) { 365 /* The receiver must be enabled for WOL before powering down */ 366 config = readl(ioaddr + GMAC_CONFIG); 367 config |= GMAC_CONFIG_RE; 368 writel(config, ioaddr + GMAC_CONFIG); 369 } 370 writel(pmt, ioaddr + GMAC_PMT); 371 } 372 373 /** 374 * dwmac4_umac_addr_slot - Get the UC filter slot for the Nth MAC address 375 * @hw: The MAC device info 376 * @reg_n: The MAC address's index in the UC list 377 * 378 * On dwmac4 the slots available for Unicast MAC filtering are configured when 379 * integrating the IP. 380 * 381 * - Slot 0 is always available, used to store the primary MAC address 382 * - From 1 to 31, the number of implemented slots is set in hw->multi_addr 383 * - From 32 to 63, the range is available if hw->additional_32_addr 384 * is set 385 * - From 64 to 127, the range is available if hw->additional_64_addr is set 386 * 387 * All the ranges can be configured independently (e.g. 64 -> 127 can be 388 * available, but not 32 -> 63) 389 * 390 * Returns: The physical slot index in the UC filter 391 */ 392 static unsigned int dwmac4_umac_addr_slot(struct mac_device_info *hw, 393 unsigned int reg_n) 394 { 395 unsigned int empty_slots = 0; 396 397 /* reg_n is in the 1-31 bank : 1 to 1 mapping */ 398 if (reg_n < (hw->multi_addr + 1)) 399 return reg_n; 400 401 /* Gap between the last address in the 1->31 range and the next slot */ 402 if (hw->additional_32_addr) 403 empty_slots = 32 - (hw->multi_addr + 1); 404 else if (hw->additional_64_addr) 405 empty_slots = 64 - (hw->multi_addr + 1); 406 407 return reg_n + empty_slots; 408 } 409 410 static void dwmac4_set_umac_addr(struct mac_device_info *hw, 411 const unsigned char *addr, unsigned int reg_n) 412 { 413 void __iomem *ioaddr = hw->pcsr; 414 unsigned int slot; 415 416 slot = dwmac4_umac_addr_slot(hw, reg_n); 417 stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(slot), 418 GMAC_ADDR_LOW(slot)); 419 } 420 421 static void dwmac4_get_umac_addr(struct mac_device_info *hw, 422 unsigned char *addr, unsigned int reg_n) 423 { 424 void __iomem *ioaddr = hw->pcsr; 425 unsigned int slot; 426 427 slot = dwmac4_umac_addr_slot(hw, reg_n); 428 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(slot), 429 GMAC_ADDR_LOW(slot)); 430 } 431 432 static int dwmac4_set_lpi_mode(struct mac_device_info *hw, 433 enum stmmac_lpi_mode mode, 434 bool en_tx_lpi_clockgating, u32 et) 435 { 436 void __iomem *ioaddr = hw->pcsr; 437 u32 value, mask; 438 439 if (mode == STMMAC_LPI_DISABLE) { 440 value = 0; 441 } else { 442 value = LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA; 443 444 if (mode == STMMAC_LPI_TIMER) { 445 /* Return ERANGE if the timer is larger than the 446 * register field. 447 */ 448 if (et > STMMAC_ET_MAX) 449 return -ERANGE; 450 451 /* Set the hardware LPI entry timer */ 452 writel(et, ioaddr + GMAC4_LPI_ENTRY_TIMER); 453 454 /* Interpret a zero LPI entry timer to mean 455 * immediate entry into LPI mode. 456 */ 457 if (et) 458 value |= LPI_CTRL_STATUS_LPIATE; 459 } 460 461 if (en_tx_lpi_clockgating) 462 value |= LPI_CTRL_STATUS_LPITCSE; 463 } 464 465 mask = LPI_CTRL_STATUS_LPIATE | LPI_CTRL_STATUS_LPIEN | 466 LPI_CTRL_STATUS_LPITXA | LPI_CTRL_STATUS_LPITCSE; 467 468 value |= readl(ioaddr + GMAC4_LPI_CTRL_STATUS) & ~mask; 469 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS); 470 471 return 0; 472 } 473 474 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link) 475 { 476 void __iomem *ioaddr = hw->pcsr; 477 u32 value; 478 479 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS); 480 481 if (link) 482 value |= LPI_CTRL_STATUS_PLS; 483 else 484 value &= ~LPI_CTRL_STATUS_PLS; 485 486 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS); 487 } 488 489 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw) 490 { 491 void __iomem *ioaddr = hw->pcsr; 492 int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16); 493 494 /* Program the timers in the LPI timer control register: 495 * LS: minimum time (ms) for which the link 496 * status from PHY should be ok before transmitting 497 * the LPI pattern. 498 * TW: minimum time (us) for which the core waits 499 * after it has stopped transmitting the LPI pattern. 500 */ 501 writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL); 502 } 503 504 static void dwmac4_set_filter(struct mac_device_info *hw, 505 struct net_device *dev) 506 { 507 void __iomem *ioaddr = (void __iomem *)dev->base_addr; 508 int numhashregs = (hw->multicast_filter_bins >> 5); 509 int mcbitslog2 = hw->mcast_bits_log2; 510 unsigned int value; 511 u32 mc_filter[8]; 512 int i; 513 514 memset(mc_filter, 0, sizeof(mc_filter)); 515 516 value = readl(ioaddr + GMAC_PACKET_FILTER); 517 value &= ~GMAC_PACKET_FILTER_HMC; 518 value &= ~GMAC_PACKET_FILTER_HPF; 519 value &= ~GMAC_PACKET_FILTER_PCF; 520 value &= ~GMAC_PACKET_FILTER_PM; 521 value &= ~GMAC_PACKET_FILTER_PR; 522 value &= ~GMAC_PACKET_FILTER_RA; 523 if (dev->flags & IFF_PROMISC) { 524 /* VLAN Tag Filter Fail Packets Queuing */ 525 if (hw->vlan_fail_q_en) { 526 value = readl(ioaddr + GMAC_RXQ_CTRL4); 527 value &= ~GMAC_RXQCTRL_VFFQ_MASK; 528 value |= GMAC_RXQCTRL_VFFQE | 529 (hw->vlan_fail_q << GMAC_RXQCTRL_VFFQ_SHIFT); 530 writel(value, ioaddr + GMAC_RXQ_CTRL4); 531 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_RA; 532 } else { 533 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_PCF; 534 } 535 536 } else if ((dev->flags & IFF_ALLMULTI) || 537 (netdev_mc_count(dev) > hw->multicast_filter_bins)) { 538 /* Pass all multi */ 539 value |= GMAC_PACKET_FILTER_PM; 540 /* Set all the bits of the HASH tab */ 541 memset(mc_filter, 0xff, sizeof(mc_filter)); 542 } else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) { 543 struct netdev_hw_addr *ha; 544 545 /* Hash filter for multicast */ 546 value |= GMAC_PACKET_FILTER_HMC; 547 548 netdev_for_each_mc_addr(ha, dev) { 549 /* The upper n bits of the calculated CRC are used to 550 * index the contents of the hash table. The number of 551 * bits used depends on the hardware configuration 552 * selected at core configuration time. 553 */ 554 u32 bit_nr = bitrev32(~crc32_le(~0, ha->addr, 555 ETH_ALEN)) >> (32 - mcbitslog2); 556 /* The most significant bit determines the register to 557 * use (H/L) while the other 5 bits determine the bit 558 * within the register. 559 */ 560 mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1f)); 561 } 562 } 563 564 for (i = 0; i < numhashregs; i++) 565 writel(mc_filter[i], ioaddr + GMAC_HASH_TAB(i)); 566 567 value |= GMAC_PACKET_FILTER_HPF; 568 569 /* Handle multiple unicast addresses */ 570 if (netdev_uc_count(dev) + 1 > hw->unicast_filter_entries) { 571 value |= GMAC_PACKET_FILTER_PR; 572 } else { 573 struct netdev_hw_addr *ha; 574 int reg = 1; 575 576 netdev_for_each_uc_addr(ha, dev) { 577 dwmac4_set_umac_addr(hw, ha->addr, reg); 578 reg++; 579 } 580 581 while (reg < hw->unicast_filter_entries) { 582 unsigned int slot = dwmac4_umac_addr_slot(hw, reg); 583 584 writel(0, ioaddr + GMAC_ADDR_HIGH(slot)); 585 writel(0, ioaddr + GMAC_ADDR_LOW(slot)); 586 reg++; 587 } 588 } 589 590 /* VLAN filtering */ 591 if (dev->flags & IFF_PROMISC && !hw->vlan_fail_q_en) 592 value &= ~GMAC_PACKET_FILTER_VTFE; 593 else if (dev->features & NETIF_F_HW_VLAN_CTAG_FILTER) 594 value |= GMAC_PACKET_FILTER_VTFE; 595 596 writel(value, ioaddr + GMAC_PACKET_FILTER); 597 } 598 599 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex, 600 unsigned int fc, unsigned int pause_time, 601 u8 tx_cnt) 602 { 603 void __iomem *ioaddr = hw->pcsr; 604 unsigned int flow = 0; 605 u8 queue; 606 607 pr_debug("GMAC Flow-Control:\n"); 608 if (fc & FLOW_RX) { 609 pr_debug("\tReceive Flow-Control ON\n"); 610 flow |= GMAC_RX_FLOW_CTRL_RFE; 611 } else { 612 pr_debug("\tReceive Flow-Control OFF\n"); 613 } 614 writel(flow, ioaddr + GMAC_RX_FLOW_CTRL); 615 616 if (fc & FLOW_TX) { 617 pr_debug("\tTransmit Flow-Control ON\n"); 618 619 if (duplex) 620 pr_debug("\tduplex mode: PAUSE %d\n", pause_time); 621 622 for (queue = 0; queue < tx_cnt; queue++) { 623 flow = GMAC_TX_FLOW_CTRL_TFE; 624 625 if (duplex) 626 flow |= FIELD_PREP(GMAC_TX_FLOW_CTRL_PT_MASK, 627 pause_time); 628 629 writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue)); 630 } 631 } else { 632 for (queue = 0; queue < tx_cnt; queue++) 633 writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue)); 634 } 635 } 636 637 static void dwmac4_ctrl_ane(struct stmmac_priv *priv, bool ane, bool srgmi_ral) 638 { 639 dwmac_ctrl_ane(priv->ioaddr, GMAC_PCS_BASE, ane, srgmi_ral); 640 } 641 642 static int dwmac4_irq_mtl_status(struct stmmac_priv *priv, 643 struct mac_device_info *hw, u32 chan) 644 { 645 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 646 void __iomem *ioaddr = hw->pcsr; 647 u32 mtl_int_qx_status; 648 int ret = 0; 649 650 mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS); 651 652 /* Check MTL Interrupt */ 653 if (mtl_int_qx_status & MTL_INT_QX(chan)) { 654 /* read Queue x Interrupt status */ 655 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(dwmac4_addrs, 656 chan)); 657 658 if (status & MTL_RX_OVERFLOW_INT) { 659 /* clear Interrupt */ 660 writel(status | MTL_RX_OVERFLOW_INT, 661 ioaddr + MTL_CHAN_INT_CTRL(dwmac4_addrs, chan)); 662 ret = CORE_IRQ_MTL_RX_OVERFLOW; 663 } 664 } 665 666 return ret; 667 } 668 669 static int dwmac4_irq_status(struct stmmac_priv *priv, 670 struct stmmac_extra_stats *x) 671 { 672 void __iomem *ioaddr = priv->hw->pcsr; 673 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS); 674 u32 intr_enable = readl(ioaddr + GMAC_INT_EN); 675 int ret = 0; 676 677 /* Discard disabled bits */ 678 intr_status &= intr_enable; 679 680 /* Not used events (e.g. MMC interrupts) are not handled. */ 681 if ((intr_status & mmc_tx_irq)) 682 x->mmc_tx_irq_n++; 683 if (unlikely(intr_status & mmc_rx_irq)) 684 x->mmc_rx_irq_n++; 685 if (unlikely(intr_status & mmc_rx_csum_offload_irq)) 686 x->mmc_rx_csum_offload_irq_n++; 687 /* Clear the PMT bits 5 and 6 by reading the PMT status reg */ 688 if (unlikely(intr_status & pmt_irq)) { 689 readl(ioaddr + GMAC_PMT); 690 x->irq_receive_pmt_irq_n++; 691 } 692 693 /* MAC tx/rx EEE LPI entry/exit interrupts */ 694 if (intr_status & lpi_irq) { 695 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */ 696 u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS); 697 698 if (status & LPI_CTRL_STATUS_TLPIEN) { 699 ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE; 700 x->irq_tx_path_in_lpi_mode_n++; 701 } 702 if (status & LPI_CTRL_STATUS_TLPIEX) { 703 ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE; 704 x->irq_tx_path_exit_lpi_mode_n++; 705 } 706 if (status & LPI_CTRL_STATUS_RLPIEN) 707 x->irq_rx_path_in_lpi_mode_n++; 708 if (status & LPI_CTRL_STATUS_RLPIEX) 709 x->irq_rx_path_exit_lpi_mode_n++; 710 } 711 712 if (intr_status & (PCS_ANE_IRQ | PCS_LINK_IRQ)) 713 stmmac_integrated_pcs_irq(priv, intr_status, x); 714 715 return ret; 716 } 717 718 static void dwmac4_debug(struct stmmac_priv *priv, void __iomem *ioaddr, 719 struct stmmac_extra_stats *x, 720 u32 rx_queues, u32 tx_queues) 721 { 722 const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs; 723 u32 value; 724 u32 queue; 725 726 for (queue = 0; queue < tx_queues; queue++) { 727 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(dwmac4_addrs, queue)); 728 729 if (value & MTL_DEBUG_TXSTSFSTS) 730 x->mtl_tx_status_fifo_full++; 731 if (value & MTL_DEBUG_TXFSTS) 732 x->mtl_tx_fifo_not_empty++; 733 if (value & MTL_DEBUG_TWCSTS) 734 x->mmtl_fifo_ctrl++; 735 if (value & MTL_DEBUG_TRCSTS_MASK) { 736 u32 trcsts = FIELD_GET(MTL_DEBUG_TRCSTS_MASK, value); 737 738 if (trcsts == MTL_DEBUG_TRCSTS_WRITE) 739 x->mtl_tx_fifo_read_ctrl_write++; 740 else if (trcsts == MTL_DEBUG_TRCSTS_TXW) 741 x->mtl_tx_fifo_read_ctrl_wait++; 742 else if (trcsts == MTL_DEBUG_TRCSTS_READ) 743 x->mtl_tx_fifo_read_ctrl_read++; 744 else 745 x->mtl_tx_fifo_read_ctrl_idle++; 746 } 747 if (value & MTL_DEBUG_TXPAUSED) 748 x->mac_tx_in_pause++; 749 } 750 751 for (queue = 0; queue < rx_queues; queue++) { 752 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(dwmac4_addrs, queue)); 753 754 if (value & MTL_DEBUG_RXFSTS_MASK) { 755 u32 rxfsts = FIELD_GET(MTL_DEBUG_RXFSTS_MASK, value); 756 757 if (rxfsts == MTL_DEBUG_RXFSTS_FULL) 758 x->mtl_rx_fifo_fill_level_full++; 759 else if (rxfsts == MTL_DEBUG_RXFSTS_AT) 760 x->mtl_rx_fifo_fill_above_thresh++; 761 else if (rxfsts == MTL_DEBUG_RXFSTS_BT) 762 x->mtl_rx_fifo_fill_below_thresh++; 763 else 764 x->mtl_rx_fifo_fill_level_empty++; 765 } 766 if (value & MTL_DEBUG_RRCSTS_MASK) { 767 u32 rrcsts = FIELD_GET(MTL_DEBUG_RRCSTS_MASK, value); 768 769 if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH) 770 x->mtl_rx_fifo_read_ctrl_flush++; 771 else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT) 772 x->mtl_rx_fifo_read_ctrl_read_data++; 773 else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA) 774 x->mtl_rx_fifo_read_ctrl_status++; 775 else 776 x->mtl_rx_fifo_read_ctrl_idle++; 777 } 778 if (value & MTL_DEBUG_RWCSTS) 779 x->mtl_rx_fifo_ctrl_active++; 780 } 781 782 /* GMAC debug */ 783 value = readl(ioaddr + GMAC_DEBUG); 784 785 if (value & GMAC_DEBUG_TFCSTS_MASK) { 786 u32 tfcsts = FIELD_GET(GMAC_DEBUG_TFCSTS_MASK, value); 787 788 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER) 789 x->mac_tx_frame_ctrl_xfer++; 790 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE) 791 x->mac_tx_frame_ctrl_pause++; 792 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT) 793 x->mac_tx_frame_ctrl_wait++; 794 else 795 x->mac_tx_frame_ctrl_idle++; 796 } 797 if (value & GMAC_DEBUG_TPESTS) 798 x->mac_gmii_tx_proto_engine++; 799 if (value & GMAC_DEBUG_RFCFCSTS_MASK) 800 x->mac_rx_frame_ctrl_fifo = FIELD_GET(GMAC_DEBUG_RFCFCSTS_MASK, 801 value); 802 if (value & GMAC_DEBUG_RPESTS) 803 x->mac_gmii_rx_proto_engine++; 804 } 805 806 static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable) 807 { 808 u32 value = readl(ioaddr + GMAC_CONFIG); 809 810 if (enable) 811 value |= GMAC_CONFIG_LM; 812 else 813 value &= ~GMAC_CONFIG_LM; 814 815 writel(value, ioaddr + GMAC_CONFIG); 816 } 817 818 static void dwmac4_sarc_configure(void __iomem *ioaddr, int val) 819 { 820 u32 value = readl(ioaddr + GMAC_CONFIG); 821 822 value = u32_replace_bits(value, val, GMAC_CONFIG_SARC); 823 824 writel(value, ioaddr + GMAC_CONFIG); 825 } 826 827 static int dwmac4_config_l3_filter(struct mac_device_info *hw, u32 filter_no, 828 bool en, bool ipv6, bool sa, bool inv, 829 u32 match) 830 { 831 void __iomem *ioaddr = hw->pcsr; 832 u32 value; 833 834 value = readl(ioaddr + GMAC_PACKET_FILTER); 835 value |= GMAC_PACKET_FILTER_IPFE; 836 writel(value, ioaddr + GMAC_PACKET_FILTER); 837 838 value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no)); 839 840 /* For IPv6 not both SA/DA filters can be active */ 841 if (ipv6) { 842 value |= GMAC_L3PEN0; 843 value &= ~(GMAC_L3SAM0 | GMAC_L3SAIM0); 844 value &= ~(GMAC_L3DAM0 | GMAC_L3DAIM0); 845 if (sa) { 846 value |= GMAC_L3SAM0; 847 if (inv) 848 value |= GMAC_L3SAIM0; 849 } else { 850 value |= GMAC_L3DAM0; 851 if (inv) 852 value |= GMAC_L3DAIM0; 853 } 854 } else { 855 value &= ~GMAC_L3PEN0; 856 if (sa) { 857 value |= GMAC_L3SAM0; 858 if (inv) 859 value |= GMAC_L3SAIM0; 860 } else { 861 value |= GMAC_L3DAM0; 862 if (inv) 863 value |= GMAC_L3DAIM0; 864 } 865 } 866 867 writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no)); 868 869 if (sa) { 870 writel(match, ioaddr + GMAC_L3_ADDR0(filter_no)); 871 } else { 872 writel(match, ioaddr + GMAC_L3_ADDR1(filter_no)); 873 } 874 875 if (!en) 876 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no)); 877 878 return 0; 879 } 880 881 static int dwmac4_config_l4_filter(struct mac_device_info *hw, u32 filter_no, 882 bool en, bool udp, bool sa, bool inv, 883 u32 match) 884 { 885 void __iomem *ioaddr = hw->pcsr; 886 u32 value; 887 888 value = readl(ioaddr + GMAC_PACKET_FILTER); 889 value |= GMAC_PACKET_FILTER_IPFE; 890 writel(value, ioaddr + GMAC_PACKET_FILTER); 891 892 value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no)); 893 if (udp) { 894 value |= GMAC_L4PEN0; 895 } else { 896 value &= ~GMAC_L4PEN0; 897 } 898 899 value &= ~(GMAC_L4SPM0 | GMAC_L4SPIM0); 900 value &= ~(GMAC_L4DPM0 | GMAC_L4DPIM0); 901 if (sa) { 902 value |= GMAC_L4SPM0; 903 if (inv) 904 value |= GMAC_L4SPIM0; 905 } else { 906 value |= GMAC_L4DPM0; 907 if (inv) 908 value |= GMAC_L4DPIM0; 909 } 910 911 writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no)); 912 913 if (sa) { 914 value = FIELD_PREP(GMAC_L4SP0, match); 915 } else { 916 value = FIELD_PREP(GMAC_L4DP0, match); 917 } 918 919 writel(value, ioaddr + GMAC_L4_ADDR(filter_no)); 920 921 if (!en) 922 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no)); 923 924 return 0; 925 } 926 927 const struct stmmac_ops dwmac4_ops = { 928 .pcs_init = dwmac4_pcs_init, 929 .core_init = dwmac4_core_init, 930 .irq_modify = dwmac4_irq_modify, 931 .update_caps = dwmac4_update_caps, 932 .set_mac = stmmac_set_mac, 933 .rx_ipc = dwmac4_rx_ipc_enable, 934 .rx_queue_enable = dwmac4_rx_queue_enable, 935 .rx_queue_prio = dwmac4_rx_queue_priority, 936 .tx_queue_prio = dwmac4_tx_queue_priority, 937 .rx_queue_routing = dwmac4_rx_queue_routing, 938 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms, 939 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms, 940 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight, 941 .map_mtl_to_dma = dwmac4_map_mtl_dma, 942 .config_cbs = dwmac4_config_cbs, 943 .dump_regs = dwmac4_dump_regs, 944 .host_irq_status = dwmac4_irq_status, 945 .host_mtl_irq_status = dwmac4_irq_mtl_status, 946 .flow_ctrl = dwmac4_flow_ctrl, 947 .pmt = dwmac4_pmt, 948 .set_umac_addr = dwmac4_set_umac_addr, 949 .get_umac_addr = dwmac4_get_umac_addr, 950 .set_lpi_mode = dwmac4_set_lpi_mode, 951 .set_eee_timer = dwmac4_set_eee_timer, 952 .set_eee_pls = dwmac4_set_eee_pls, 953 .pcs_ctrl_ane = dwmac4_ctrl_ane, 954 .debug = dwmac4_debug, 955 .set_filter = dwmac4_set_filter, 956 .set_mac_loopback = dwmac4_set_mac_loopback, 957 .sarc_configure = dwmac4_sarc_configure, 958 .config_l3_filter = dwmac4_config_l3_filter, 959 .config_l4_filter = dwmac4_config_l4_filter, 960 }; 961 962 const struct stmmac_ops dwmac410_ops = { 963 .pcs_init = dwmac4_pcs_init, 964 .core_init = dwmac4_core_init, 965 .irq_modify = dwmac4_irq_modify, 966 .update_caps = dwmac4_update_caps, 967 .set_mac = stmmac_dwmac4_set_mac, 968 .rx_ipc = dwmac4_rx_ipc_enable, 969 .rx_queue_enable = dwmac4_rx_queue_enable, 970 .rx_queue_prio = dwmac4_rx_queue_priority, 971 .tx_queue_prio = dwmac4_tx_queue_priority, 972 .rx_queue_routing = dwmac4_rx_queue_routing, 973 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms, 974 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms, 975 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight, 976 .map_mtl_to_dma = dwmac4_map_mtl_dma, 977 .config_cbs = dwmac4_config_cbs, 978 .dump_regs = dwmac4_dump_regs, 979 .host_irq_status = dwmac4_irq_status, 980 .host_mtl_irq_status = dwmac4_irq_mtl_status, 981 .flow_ctrl = dwmac4_flow_ctrl, 982 .pmt = dwmac4_pmt, 983 .set_umac_addr = dwmac4_set_umac_addr, 984 .get_umac_addr = dwmac4_get_umac_addr, 985 .set_lpi_mode = dwmac4_set_lpi_mode, 986 .set_eee_timer = dwmac4_set_eee_timer, 987 .set_eee_pls = dwmac4_set_eee_pls, 988 .pcs_ctrl_ane = dwmac4_ctrl_ane, 989 .debug = dwmac4_debug, 990 .set_filter = dwmac4_set_filter, 991 .flex_pps_config = dwmac5_flex_pps_config, 992 .set_mac_loopback = dwmac4_set_mac_loopback, 993 .sarc_configure = dwmac4_sarc_configure, 994 .config_l3_filter = dwmac4_config_l3_filter, 995 .config_l4_filter = dwmac4_config_l4_filter, 996 .fpe_map_preemption_class = dwmac5_fpe_map_preemption_class, 997 }; 998 999 const struct stmmac_ops dwmac510_ops = { 1000 .pcs_init = dwmac4_pcs_init, 1001 .core_init = dwmac4_core_init, 1002 .irq_modify = dwmac4_irq_modify, 1003 .update_caps = dwmac4_update_caps, 1004 .set_mac = stmmac_dwmac4_set_mac, 1005 .rx_ipc = dwmac4_rx_ipc_enable, 1006 .rx_queue_enable = dwmac4_rx_queue_enable, 1007 .rx_queue_prio = dwmac4_rx_queue_priority, 1008 .tx_queue_prio = dwmac4_tx_queue_priority, 1009 .rx_queue_routing = dwmac4_rx_queue_routing, 1010 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms, 1011 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms, 1012 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight, 1013 .map_mtl_to_dma = dwmac4_map_mtl_dma, 1014 .config_cbs = dwmac4_config_cbs, 1015 .dump_regs = dwmac4_dump_regs, 1016 .host_irq_status = dwmac4_irq_status, 1017 .host_mtl_irq_status = dwmac4_irq_mtl_status, 1018 .flow_ctrl = dwmac4_flow_ctrl, 1019 .pmt = dwmac4_pmt, 1020 .set_umac_addr = dwmac4_set_umac_addr, 1021 .get_umac_addr = dwmac4_get_umac_addr, 1022 .set_lpi_mode = dwmac4_set_lpi_mode, 1023 .set_eee_timer = dwmac4_set_eee_timer, 1024 .set_eee_pls = dwmac4_set_eee_pls, 1025 .pcs_ctrl_ane = dwmac4_ctrl_ane, 1026 .debug = dwmac4_debug, 1027 .set_filter = dwmac4_set_filter, 1028 .safety_feat_config = dwmac5_safety_feat_config, 1029 .safety_feat_irq_status = dwmac5_safety_feat_irq_status, 1030 .safety_feat_dump = dwmac5_safety_feat_dump, 1031 .rxp_config = dwmac5_rxp_config, 1032 .flex_pps_config = dwmac5_flex_pps_config, 1033 .set_mac_loopback = dwmac4_set_mac_loopback, 1034 .sarc_configure = dwmac4_sarc_configure, 1035 .config_l3_filter = dwmac4_config_l3_filter, 1036 .config_l4_filter = dwmac4_config_l4_filter, 1037 .fpe_map_preemption_class = dwmac5_fpe_map_preemption_class, 1038 }; 1039 1040 int dwmac4_setup(struct stmmac_priv *priv) 1041 { 1042 struct mac_device_info *mac = priv->hw; 1043 1044 dev_info(priv->device, "\tDWMAC4/5\n"); 1045 1046 priv->dev->priv_flags |= IFF_UNICAST_FLT; 1047 mac->pcsr = priv->ioaddr; 1048 mac->multicast_filter_bins = priv->plat->multicast_filter_bins; 1049 mac->unicast_filter_entries = priv->plat->unicast_filter_entries; 1050 mac->mcast_bits_log2 = 0; 1051 1052 if (mac->multicast_filter_bins) 1053 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins); 1054 1055 mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1056 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 1057 mac->link.duplex = GMAC_CONFIG_DM; 1058 mac->link.speed10 = GMAC_CONFIG_PS; 1059 mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS; 1060 mac->link.speed1000 = 0; 1061 mac->link.speed2500 = GMAC_CONFIG_FES; 1062 mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS; 1063 mac->mii.addr = GMAC_MDIO_ADDR; 1064 mac->mii.data = GMAC_MDIO_DATA; 1065 mac->mii.addr_mask = GENMASK_U32(25, 21); 1066 mac->mii.reg_mask = GENMASK_U32(20, 16); 1067 mac->mii.clk_csr_mask = GENMASK_U32(11, 8); 1068 mac->num_vlan = stmmac_get_num_vlan(priv->ioaddr); 1069 1070 return 0; 1071 } 1072