1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
5 developing this code.
6
7 This contains the functions to handle the dma.
8
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
10
11
12 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
13 *******************************************************************************/
14
15 #include <linux/io.h>
16 #include "dwmac1000.h"
17 #include "dwmac_dma.h"
18
dwmac1000_dma_axi(void __iomem * ioaddr,struct stmmac_axi * axi)19 static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
20 {
21 u32 value = readl(ioaddr + DMA_AXI_BUS_MODE);
22 int i;
23
24 pr_info("dwmac1000: Master AXI performs %s burst length\n",
25 !(value & DMA_AXI_UNDEF) ? "fixed" : "any");
26
27 if (axi->axi_lpi_en)
28 value |= DMA_AXI_EN_LPI;
29 if (axi->axi_xit_frm)
30 value |= DMA_AXI_LPI_XIT_FRM;
31
32 value &= ~DMA_AXI_WR_OSR_LMT;
33 value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) <<
34 DMA_AXI_WR_OSR_LMT_SHIFT;
35
36 value &= ~DMA_AXI_RD_OSR_LMT;
37 value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) <<
38 DMA_AXI_RD_OSR_LMT_SHIFT;
39
40 /* Depending on the UNDEF bit the Master AXI will perform any burst
41 * length according to the BLEN programmed (by default all BLEN are
42 * set).
43 */
44 for (i = 0; i < AXI_BLEN; i++) {
45 switch (axi->axi_blen[i]) {
46 case 256:
47 value |= DMA_AXI_BLEN256;
48 break;
49 case 128:
50 value |= DMA_AXI_BLEN128;
51 break;
52 case 64:
53 value |= DMA_AXI_BLEN64;
54 break;
55 case 32:
56 value |= DMA_AXI_BLEN32;
57 break;
58 case 16:
59 value |= DMA_AXI_BLEN16;
60 break;
61 case 8:
62 value |= DMA_AXI_BLEN8;
63 break;
64 case 4:
65 value |= DMA_AXI_BLEN4;
66 break;
67 }
68 }
69
70 writel(value, ioaddr + DMA_AXI_BUS_MODE);
71 }
72
dwmac1000_dma_init_channel(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,u32 chan)73 static void dwmac1000_dma_init_channel(struct stmmac_priv *priv,
74 void __iomem *ioaddr,
75 struct stmmac_dma_cfg *dma_cfg, u32 chan)
76 {
77 int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
78 int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
79 u32 value;
80
81 value = readl(ioaddr + DMA_CHAN_BUS_MODE(chan));
82
83 /* Set the DMA PBL (Programmable Burst Length) mode.
84 *
85 * Note: before stmmac core 3.50 this mode bit was 4xPBL, and
86 * post 3.5 mode bit acts as 8*PBL.
87 */
88 if (dma_cfg->pblx8)
89 value |= DMA_BUS_MODE_MAXPBL;
90 value |= DMA_BUS_MODE_USP;
91 value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK);
92 value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT);
93 value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
94
95 /* Set the Fixed burst mode */
96 if (dma_cfg->fixed_burst)
97 value |= DMA_BUS_MODE_FB;
98
99 /* Mixed Burst has no effect when fb is set */
100 if (dma_cfg->mixed_burst)
101 value |= DMA_BUS_MODE_MB;
102
103 if (dma_cfg->atds)
104 value |= DMA_BUS_MODE_ATDS;
105
106 if (dma_cfg->aal)
107 value |= DMA_BUS_MODE_AAL;
108
109 writel(value, ioaddr + DMA_CHAN_BUS_MODE(chan));
110
111 /* Mask interrupts by writing to CSR7 */
112 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(chan));
113 }
114
dwmac1000_dma_init_rx(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,dma_addr_t dma_rx_phy,u32 chan)115 static void dwmac1000_dma_init_rx(struct stmmac_priv *priv,
116 void __iomem *ioaddr,
117 struct stmmac_dma_cfg *dma_cfg,
118 dma_addr_t dma_rx_phy, u32 chan)
119 {
120 /* RX descriptor base address list must be written into DMA CSR3 */
121 writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RCV_BASE_ADDR(chan));
122 }
123
dwmac1000_dma_init_tx(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,dma_addr_t dma_tx_phy,u32 chan)124 static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
125 void __iomem *ioaddr,
126 struct stmmac_dma_cfg *dma_cfg,
127 dma_addr_t dma_tx_phy, u32 chan)
128 {
129 /* TX descriptor base address list must be written into DMA CSR4 */
130 writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
131 }
132
dwmac1000_configure_fc(u32 csr6,int rxfifosz)133 static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
134 {
135 csr6 &= ~DMA_CONTROL_RFA_MASK;
136 csr6 &= ~DMA_CONTROL_RFD_MASK;
137
138 /* Leave flow control disabled if receive fifo size is less than
139 * 4K or 0. Otherwise, send XOFF when fifo is 1K less than full,
140 * and send XON when 2K less than full.
141 */
142 if (rxfifosz < 4096) {
143 csr6 &= ~DMA_CONTROL_EFC;
144 pr_debug("GMAC: disabling flow control, rxfifo too small(%d)\n",
145 rxfifosz);
146 } else {
147 csr6 |= DMA_CONTROL_EFC;
148 csr6 |= RFA_FULL_MINUS_1K;
149 csr6 |= RFD_FULL_MINUS_2K;
150 }
151 return csr6;
152 }
153
dwmac1000_dma_operation_mode_rx(struct stmmac_priv * priv,void __iomem * ioaddr,int mode,u32 channel,int fifosz,u8 qmode)154 static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv,
155 void __iomem *ioaddr, int mode,
156 u32 channel, int fifosz, u8 qmode)
157 {
158 u32 csr6 = readl(ioaddr + DMA_CHAN_CONTROL(channel));
159
160 if (mode == SF_DMA_MODE) {
161 pr_debug("GMAC: enable RX store and forward mode\n");
162 csr6 |= DMA_CONTROL_RSF;
163 } else {
164 pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);
165 csr6 &= ~DMA_CONTROL_RSF;
166 csr6 &= DMA_CONTROL_TC_RX_MASK;
167 if (mode <= 32)
168 csr6 |= DMA_CONTROL_RTC_32;
169 else if (mode <= 64)
170 csr6 |= DMA_CONTROL_RTC_64;
171 else if (mode <= 96)
172 csr6 |= DMA_CONTROL_RTC_96;
173 else
174 csr6 |= DMA_CONTROL_RTC_128;
175 }
176
177 /* Configure flow control based on rx fifo size */
178 csr6 = dwmac1000_configure_fc(csr6, fifosz);
179
180 writel(csr6, ioaddr + DMA_CHAN_CONTROL(channel));
181 }
182
dwmac1000_dma_operation_mode_tx(struct stmmac_priv * priv,void __iomem * ioaddr,int mode,u32 channel,int fifosz,u8 qmode)183 static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv,
184 void __iomem *ioaddr, int mode,
185 u32 channel, int fifosz, u8 qmode)
186 {
187 u32 csr6 = readl(ioaddr + DMA_CHAN_CONTROL(channel));
188
189 if (mode == SF_DMA_MODE) {
190 pr_debug("GMAC: enable TX store and forward mode\n");
191 /* Transmit COE type 2 cannot be done in cut-through mode. */
192 csr6 |= DMA_CONTROL_TSF;
193 /* Operating on second frame increase the performance
194 * especially when transmit store-and-forward is used.
195 */
196 csr6 |= DMA_CONTROL_OSF;
197 } else {
198 pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);
199 csr6 &= ~DMA_CONTROL_TSF;
200 csr6 &= DMA_CONTROL_TC_TX_MASK;
201 /* Set the transmit threshold */
202 if (mode <= 32)
203 csr6 |= DMA_CONTROL_TTC_32;
204 else if (mode <= 64)
205 csr6 |= DMA_CONTROL_TTC_64;
206 else if (mode <= 128)
207 csr6 |= DMA_CONTROL_TTC_128;
208 else if (mode <= 192)
209 csr6 |= DMA_CONTROL_TTC_192;
210 else
211 csr6 |= DMA_CONTROL_TTC_256;
212 }
213
214 writel(csr6, ioaddr + DMA_CHAN_CONTROL(channel));
215 }
216
dwmac1000_dump_dma_regs(struct stmmac_priv * priv,void __iomem * ioaddr,u32 * reg_space)217 static void dwmac1000_dump_dma_regs(struct stmmac_priv *priv,
218 void __iomem *ioaddr, u32 *reg_space)
219 {
220 int i;
221
222 for (i = 0; i < NUM_DWMAC1000_DMA_REGS; i++)
223 if ((i < 12) || (i > 17))
224 reg_space[DMA_BUS_MODE / 4 + i] =
225 readl(ioaddr + DMA_BUS_MODE + i * 4);
226 }
227
dwmac1000_get_hw_feature(void __iomem * ioaddr,struct dma_features * dma_cap)228 static int dwmac1000_get_hw_feature(void __iomem *ioaddr,
229 struct dma_features *dma_cap)
230 {
231 u32 hw_cap = readl(ioaddr + DMA_HW_FEATURE);
232
233 if (!hw_cap) {
234 /* 0x00000000 is the value read on old hardware that does not
235 * implement this register
236 */
237 return -EOPNOTSUPP;
238 }
239
240 dma_cap->mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
241 dma_cap->mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
242 dma_cap->half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
243 dma_cap->hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
244 dma_cap->multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
245 dma_cap->pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
246 dma_cap->sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
247 dma_cap->pmt_remote_wake_up = (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
248 dma_cap->pmt_magic_frame = (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
249 /* MMC */
250 dma_cap->rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
251 /* IEEE 1588-2002 */
252 dma_cap->time_stamp =
253 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
254 /* IEEE 1588-2008 */
255 dma_cap->atime_stamp = (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
256 /* 802.3az - Energy-Efficient Ethernet (EEE) */
257 dma_cap->eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
258 dma_cap->av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
259 /* TX and RX csum */
260 dma_cap->tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
261 dma_cap->rx_coe_type1 = (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
262 dma_cap->rx_coe_type2 = (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
263 dma_cap->rxfifo_over_2048 = (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
264 /* TX and RX number of channels */
265 dma_cap->number_rx_channel = (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
266 dma_cap->number_tx_channel = (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
267 /* Alternate (enhanced) DESC mode */
268 dma_cap->enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
269
270 return 0;
271 }
272
dwmac1000_rx_watchdog(struct stmmac_priv * priv,void __iomem * ioaddr,u32 riwt,u32 queue)273 static void dwmac1000_rx_watchdog(struct stmmac_priv *priv,
274 void __iomem *ioaddr, u32 riwt, u32 queue)
275 {
276 writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(queue));
277 }
278
279 const struct stmmac_dma_ops dwmac1000_dma_ops = {
280 .reset = dwmac_dma_reset,
281 .init_chan = dwmac1000_dma_init_channel,
282 .init_rx_chan = dwmac1000_dma_init_rx,
283 .init_tx_chan = dwmac1000_dma_init_tx,
284 .axi = dwmac1000_dma_axi,
285 .dump_regs = dwmac1000_dump_dma_regs,
286 .dma_rx_mode = dwmac1000_dma_operation_mode_rx,
287 .dma_tx_mode = dwmac1000_dma_operation_mode_tx,
288 .enable_dma_transmission = dwmac_enable_dma_transmission,
289 .enable_dma_irq = dwmac_enable_dma_irq,
290 .disable_dma_irq = dwmac_disable_dma_irq,
291 .start_tx = dwmac_dma_start_tx,
292 .stop_tx = dwmac_dma_stop_tx,
293 .start_rx = dwmac_dma_start_rx,
294 .stop_rx = dwmac_dma_stop_rx,
295 .dma_interrupt = dwmac_dma_interrupt,
296 .get_hw_feature = dwmac1000_get_hw_feature,
297 .rx_watchdog = dwmac1000_rx_watchdog,
298 };
299 EXPORT_SYMBOL_GPL(dwmac1000_dma_ops);
300