1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller
4 *
5 * Copyright (C) 2018 Synaptics Incorporated
6 *
7 * Author: Jisheng Zhang <jszhang@kernel.org>
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/arm-smccc.h>
12 #include <linux/bitfield.h>
13 #include <linux/clk.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/iopoll.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/reset.h>
23 #include <linux/sizes.h>
24
25 #include "sdhci-pltfm.h"
26 #include "cqhci.h"
27
28 #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16)
29
30 /* DWCMSHC specific Mode Select value */
31 #define DWCMSHC_CTRL_HS400 0x7
32
33 /* DWC IP vendor area 1 pointer */
34 #define DWCMSHC_P_VENDOR_AREA1 0xe8
35 #define DWCMSHC_AREA1_MASK GENMASK(11, 0)
36 /* Offset inside the vendor area 1 */
37 #define DWCMSHC_HOST_CTRL3 0x8
38 #define DWCMSHC_EMMC_CONTROL 0x2c
39 #define DWCMSHC_CARD_IS_EMMC BIT(0)
40 #define DWCMSHC_ENHANCED_STROBE BIT(8)
41 #define DWCMSHC_EMMC_ATCTRL 0x40
42 /* Tuning and auto-tuning fields in AT_CTRL_R control register */
43 #define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */
44 #define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */
45 #define AT_CTRL_SWIN_TH_EN BIT(2) /* sampling window threshold enable */
46 #define AT_CTRL_RPT_TUNE_ERR BIT(3) /* enable reporting framing errors */
47 #define AT_CTRL_SW_TUNE_EN BIT(4) /* enable software managed tuning */
48 #define AT_CTRL_WIN_EDGE_SEL_MASK GENMASK(11, 8) /* bits [11:8] */
49 #define AT_CTRL_WIN_EDGE_SEL 0xf /* sampling window edge select */
50 #define AT_CTRL_TUNE_CLK_STOP_EN BIT(16) /* clocks stopped during phase code change */
51 #define AT_CTRL_PRE_CHANGE_DLY_MASK GENMASK(18, 17) /* bits [18:17] */
52 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */
53 #define AT_CTRL_POST_CHANGE_DLY_MASK GENMASK(20, 19) /* bits [20:19] */
54 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */
55 #define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */
56 #define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */
57
58 /* DWC IP vendor area 2 pointer */
59 #define DWCMSHC_P_VENDOR_AREA2 0xea
60
61 /* Sophgo CV18XX specific Registers */
62 #define CV18XX_SDHCI_MSHC_CTRL 0x00
63 #define CV18XX_EMMC_FUNC_EN BIT(0)
64 #define CV18XX_LATANCY_1T BIT(1)
65 #define CV18XX_SDHCI_PHY_TX_RX_DLY 0x40
66 #define CV18XX_PHY_TX_DLY_MSK GENMASK(6, 0)
67 #define CV18XX_PHY_TX_SRC_MSK GENMASK(9, 8)
68 #define CV18XX_PHY_TX_SRC_INVERT_CLK_TX 0x1
69 #define CV18XX_PHY_RX_DLY_MSK GENMASK(22, 16)
70 #define CV18XX_PHY_RX_SRC_MSK GENMASK(25, 24)
71 #define CV18XX_PHY_RX_SRC_INVERT_RX_CLK 0x1
72 #define CV18XX_SDHCI_PHY_CONFIG 0x4c
73 #define CV18XX_PHY_TX_BPS BIT(0)
74
75 #define CV18XX_TUNE_MAX 128
76 #define CV18XX_TUNE_STEP 1
77 #define CV18XX_RETRY_TUNING_MAX 50
78
79 /* Rockchip specific Registers */
80 #define DWCMSHC_EMMC_DLL_CTRL 0x800
81 #define DWCMSHC_EMMC_DLL_RXCLK 0x804
82 #define DWCMSHC_EMMC_DLL_TXCLK 0x808
83 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c
84 #define DECMSHC_EMMC_DLL_CMDOUT 0x810
85 #define DWCMSHC_EMMC_DLL_STATUS0 0x840
86 #define DWCMSHC_EMMC_DLL_START BIT(0)
87 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
88 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
89 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
90 #define DWCMSHC_EMMC_DLL_START_POINT 16
91 #define DWCMSHC_EMMC_DLL_INC 8
92 #define DWCMSHC_EMMC_DLL_BYPASS BIT(24)
93 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
94 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10
95 #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA
96 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
97 #define DLL_STRBIN_TAPNUM_DEFAULT 0x8
98 #define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
99 #define DLL_STRBIN_DELAY_NUM_SEL BIT(26)
100 #define DLL_STRBIN_DELAY_NUM_OFFSET 16
101 #define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16
102 #define DLL_RXCLK_NO_INVERTER 1
103 #define DLL_RXCLK_INVERTER 0
104 #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
105 #define DLL_RXCLK_ORI_GATE BIT(31)
106 #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
107 #define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
108 #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
109
110 #define DLL_LOCK_WO_TMOUT(x) \
111 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
112 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
113
114 /* PHY register area pointer */
115 #define DWC_MSHC_PTR_PHY_R 0x300
116
117 /* PHY general configuration */
118 #define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00)
119 #define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */
120 #define PHY_CNFG_PHY_PWRGOOD_MASK BIT_MASK(1) /* bit [1] */
121 #define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */
122 #define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */
123 #define PHY_CNFG_PAD_SP_SG2042 0x09 /* PMOS TX drive strength for SG2042 */
124 #define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */
125 #define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */
126 #define PHY_CNFG_PAD_SN_SG2042 0x08 /* NMOS TX drive strength for SG2042 */
127
128 /* PHY command/response pad settings */
129 #define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04)
130
131 /* PHY data pad settings */
132 #define PHY_DATAPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x06)
133
134 /* PHY clock pad settings */
135 #define PHY_CLKPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x08)
136
137 /* PHY strobe pad settings */
138 #define PHY_STBPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0a)
139
140 /* PHY reset pad settings */
141 #define PHY_RSTNPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0c)
142
143 /* Bitfields are common for all pad settings */
144 #define PHY_PAD_RXSEL_1V8 0x1 /* Receiver type select for 1.8V */
145 #define PHY_PAD_RXSEL_3V3 0x2 /* Receiver type select for 3.3V */
146
147 #define PHY_PAD_WEAKPULL_MASK GENMASK(4, 3) /* bits [4:3] */
148 #define PHY_PAD_WEAKPULL_PULLUP 0x1 /* Weak pull up enabled */
149 #define PHY_PAD_WEAKPULL_PULLDOWN 0x2 /* Weak pull down enabled */
150
151 #define PHY_PAD_TXSLEW_CTRL_P_MASK GENMASK(8, 5) /* bits [8:5] */
152 #define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */
153 #define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */
154 #define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */
155 #define PHY_PAD_TXSLEW_CTRL_N_SG2042 0x2 /* Slew control for N-Type pad TX for SG2042 */
156
157 /* PHY CLK delay line settings */
158 #define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d)
159 #define PHY_SDCLKDL_CNFG_EXTDLY_EN BIT(0)
160 #define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC */
161
162 /* PHY CLK delay line delay code */
163 #define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e)
164 #define PHY_SDCLKDL_DC_INITIAL 0x40 /* initial delay code */
165 #define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */
166 #define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */
167
168 #define PHY_SMPLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x20)
169 #define PHY_SMPLDL_CNFG_BYPASS_EN BIT(1)
170
171 /* PHY drift_cclk_rx delay line configuration setting */
172 #define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21)
173 #define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */
174 #define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */
175 #define PHY_ATDL_CNFG_INPSEL_SG2042 0x2 /* delay line input source for SG2042 */
176
177 /* PHY DLL control settings */
178 #define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24)
179 #define PHY_DLL_CTRL_DISABLE 0x0 /* PHY DLL is enabled */
180 #define PHY_DLL_CTRL_ENABLE 0x1 /* PHY DLL is disabled */
181
182 /* PHY DLL configuration register 1 */
183 #define PHY_DLL_CNFG1_R (DWC_MSHC_PTR_PHY_R + 0x25)
184 #define PHY_DLL_CNFG1_SLVDLY_MASK GENMASK(5, 4) /* bits [5:4] */
185 #define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */
186 #define PHY_DLL_CNFG1_WAITCYCLE 0x5 /* DLL wait cycle input */
187
188 /* PHY DLL configuration register 2 */
189 #define PHY_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_R + 0x26)
190 #define PHY_DLL_CNFG2_JUMPSTEP 0xa /* DLL jump step input */
191
192 /* PHY DLL master and slave delay line configuration settings */
193 #define PHY_DLLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x28)
194 #define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */
195 #define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */
196
197 #define FLAG_IO_FIXED_1V8 BIT(0)
198
199 #define BOUNDARY_OK(addr, len) \
200 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
201
202 #define DWCMSHC_SDHCI_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
203 SDHCI_TRNS_BLK_CNT_EN | \
204 SDHCI_TRNS_DMA)
205
206 /* SMC call for BlueField-3 eMMC RST_N */
207 #define BLUEFIELD_SMC_SET_EMMC_RST_N 0x82000007
208
209 enum dwcmshc_rk_type {
210 DWCMSHC_RK3568,
211 DWCMSHC_RK3588,
212 };
213
214 struct rk35xx_priv {
215 struct reset_control *reset;
216 enum dwcmshc_rk_type devtype;
217 u8 txclk_tapnum;
218 };
219
220 #define DWCMSHC_MAX_OTHER_CLKS 3
221
222 struct dwcmshc_priv {
223 struct clk *bus_clk;
224 int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA1 reg */
225 int vendor_specific_area2; /* P_VENDOR_SPECIFIC_AREA2 reg */
226
227 int num_other_clks;
228 struct clk_bulk_data other_clks[DWCMSHC_MAX_OTHER_CLKS];
229
230 void *priv; /* pointer to SoC private stuff */
231 u16 delay_line;
232 u16 flags;
233 };
234
235 struct dwcmshc_pltfm_data {
236 const struct sdhci_pltfm_data pdata;
237 int (*init)(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv);
238 void (*postinit)(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv);
239 };
240
dwcmshc_get_enable_other_clks(struct device * dev,struct dwcmshc_priv * priv,int num_clks,const char * const clk_ids[])241 static int dwcmshc_get_enable_other_clks(struct device *dev,
242 struct dwcmshc_priv *priv,
243 int num_clks,
244 const char * const clk_ids[])
245 {
246 int err;
247
248 if (num_clks > DWCMSHC_MAX_OTHER_CLKS)
249 return -EINVAL;
250
251 for (int i = 0; i < num_clks; i++)
252 priv->other_clks[i].id = clk_ids[i];
253
254 err = devm_clk_bulk_get_optional(dev, num_clks, priv->other_clks);
255 if (err) {
256 dev_err(dev, "failed to get clocks %d\n", err);
257 return err;
258 }
259
260 err = clk_bulk_prepare_enable(num_clks, priv->other_clks);
261 if (err)
262 dev_err(dev, "failed to enable clocks %d\n", err);
263
264 priv->num_other_clks = num_clks;
265
266 return err;
267 }
268
269 /*
270 * If DMA addr spans 128MB boundary, we split the DMA transfer into two
271 * so that each DMA transfer doesn't exceed the boundary.
272 */
dwcmshc_adma_write_desc(struct sdhci_host * host,void ** desc,dma_addr_t addr,int len,unsigned int cmd)273 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
274 dma_addr_t addr, int len, unsigned int cmd)
275 {
276 int tmplen, offset;
277
278 if (likely(!len || BOUNDARY_OK(addr, len))) {
279 sdhci_adma_write_desc(host, desc, addr, len, cmd);
280 return;
281 }
282
283 offset = addr & (SZ_128M - 1);
284 tmplen = SZ_128M - offset;
285 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
286
287 addr += tmplen;
288 len -= tmplen;
289 sdhci_adma_write_desc(host, desc, addr, len, cmd);
290 }
291
dwcmshc_get_max_clock(struct sdhci_host * host)292 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
293 {
294 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
295
296 if (pltfm_host->clk)
297 return sdhci_pltfm_clk_get_max_clock(host);
298 else
299 return pltfm_host->clock;
300 }
301
rk35xx_get_max_clock(struct sdhci_host * host)302 static unsigned int rk35xx_get_max_clock(struct sdhci_host *host)
303 {
304 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
305
306 return clk_round_rate(pltfm_host->clk, ULONG_MAX);
307 }
308
dwcmshc_check_auto_cmd23(struct mmc_host * mmc,struct mmc_request * mrq)309 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
310 struct mmc_request *mrq)
311 {
312 struct sdhci_host *host = mmc_priv(mmc);
313
314 /*
315 * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit
316 * block count register which doesn't support stuff bits of
317 * CMD23 argument on dwcmsch host controller.
318 */
319 if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF))
320 host->flags &= ~SDHCI_AUTO_CMD23;
321 else
322 host->flags |= SDHCI_AUTO_CMD23;
323 }
324
dwcmshc_request(struct mmc_host * mmc,struct mmc_request * mrq)325 static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq)
326 {
327 dwcmshc_check_auto_cmd23(mmc, mrq);
328
329 sdhci_request(mmc, mrq);
330 }
331
dwcmshc_phy_init(struct sdhci_host * host)332 static void dwcmshc_phy_init(struct sdhci_host *host)
333 {
334 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
335 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
336 u32 rxsel = PHY_PAD_RXSEL_3V3;
337 u32 val;
338
339 if (priv->flags & FLAG_IO_FIXED_1V8 ||
340 host->mmc->ios.timing & MMC_SIGNAL_VOLTAGE_180)
341 rxsel = PHY_PAD_RXSEL_1V8;
342
343 /* deassert phy reset & set tx drive strength */
344 val = PHY_CNFG_RSTN_DEASSERT;
345 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP);
346 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN);
347 sdhci_writel(host, val, PHY_CNFG_R);
348
349 /* disable delay line */
350 sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R);
351
352 /* set delay line */
353 sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R);
354 sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R);
355
356 /* enable delay lane */
357 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
358 val &= ~(PHY_SDCLKDL_CNFG_UPDATE);
359 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
360
361 /* configure phy pads */
362 val = rxsel;
363 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);
364 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
365 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
366 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
367 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
368 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
369
370 val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
371 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
372 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
373
374 val = rxsel;
375 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);
376 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
377 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
378 sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
379
380 /* enable data strobe mode */
381 if (rxsel == PHY_PAD_RXSEL_1V8) {
382 u8 sel = FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_CNFG_SLV_INPSEL);
383
384 sdhci_writeb(host, sel, PHY_DLLDL_CNFG_R);
385 }
386
387 /* enable phy dll */
388 sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R);
389
390 }
391
th1520_sdhci_set_phy(struct sdhci_host * host)392 static void th1520_sdhci_set_phy(struct sdhci_host *host)
393 {
394 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
395 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
396 u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
397 u16 emmc_ctrl;
398
399 dwcmshc_phy_init(host);
400
401 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {
402 emmc_ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
403 emmc_ctrl |= DWCMSHC_CARD_IS_EMMC;
404 sdhci_writew(host, emmc_ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
405 }
406
407 sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) |
408 PHY_DLL_CNFG1_WAITCYCLE, PHY_DLL_CNFG1_R);
409 }
410
dwcmshc_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)411 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
412 unsigned int timing)
413 {
414 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
415 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
416 u16 ctrl, ctrl_2;
417
418 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
419 /* Select Bus Speed Mode for host */
420 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
421 if ((timing == MMC_TIMING_MMC_HS200) ||
422 (timing == MMC_TIMING_UHS_SDR104))
423 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
424 else if (timing == MMC_TIMING_UHS_SDR12)
425 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
426 else if ((timing == MMC_TIMING_UHS_SDR25) ||
427 (timing == MMC_TIMING_MMC_HS))
428 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
429 else if (timing == MMC_TIMING_UHS_SDR50)
430 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
431 else if ((timing == MMC_TIMING_UHS_DDR50) ||
432 (timing == MMC_TIMING_MMC_DDR52))
433 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
434 else if (timing == MMC_TIMING_MMC_HS400) {
435 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
436 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
437 ctrl |= DWCMSHC_CARD_IS_EMMC;
438 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
439
440 ctrl_2 |= DWCMSHC_CTRL_HS400;
441 }
442
443 if (priv->flags & FLAG_IO_FIXED_1V8)
444 ctrl_2 |= SDHCI_CTRL_VDD_180;
445 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
446 }
447
th1520_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)448 static void th1520_set_uhs_signaling(struct sdhci_host *host,
449 unsigned int timing)
450 {
451 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
452 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
453
454 dwcmshc_set_uhs_signaling(host, timing);
455 if (timing == MMC_TIMING_MMC_HS400)
456 priv->delay_line = PHY_SDCLKDL_DC_HS400;
457 else
458 sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R);
459 th1520_sdhci_set_phy(host);
460 }
461
dwcmshc_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)462 static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc,
463 struct mmc_ios *ios)
464 {
465 u32 vendor;
466 struct sdhci_host *host = mmc_priv(mmc);
467 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
468 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
469 int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL;
470
471 vendor = sdhci_readl(host, reg);
472 if (ios->enhanced_strobe)
473 vendor |= DWCMSHC_ENHANCED_STROBE;
474 else
475 vendor &= ~DWCMSHC_ENHANCED_STROBE;
476
477 sdhci_writel(host, vendor, reg);
478 }
479
dwcmshc_execute_tuning(struct mmc_host * mmc,u32 opcode)480 static int dwcmshc_execute_tuning(struct mmc_host *mmc, u32 opcode)
481 {
482 int err = sdhci_execute_tuning(mmc, opcode);
483 struct sdhci_host *host = mmc_priv(mmc);
484
485 if (err)
486 return err;
487
488 /*
489 * Tuning can leave the IP in an active state (Buffer Read Enable bit
490 * set) which prevents the entry to low power states (i.e. S0i3). Data
491 * reset will clear it.
492 */
493 sdhci_reset(host, SDHCI_RESET_DATA);
494
495 return 0;
496 }
497
dwcmshc_cqe_irq_handler(struct sdhci_host * host,u32 intmask)498 static u32 dwcmshc_cqe_irq_handler(struct sdhci_host *host, u32 intmask)
499 {
500 int cmd_error = 0;
501 int data_error = 0;
502
503 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
504 return intmask;
505
506 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
507
508 return 0;
509 }
510
dwcmshc_sdhci_cqe_enable(struct mmc_host * mmc)511 static void dwcmshc_sdhci_cqe_enable(struct mmc_host *mmc)
512 {
513 struct sdhci_host *host = mmc_priv(mmc);
514 u8 ctrl;
515
516 sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
517
518 sdhci_cqe_enable(mmc);
519
520 /*
521 * The "DesignWare Cores Mobile Storage Host Controller
522 * DWC_mshc / DWC_mshc_lite Databook" says:
523 * when Host Version 4 Enable" is 1 in Host Control 2 register,
524 * SDHCI_CTRL_ADMA32 bit means ADMA2 is selected.
525 * Selection of 32-bit/64-bit System Addressing:
526 * either 32-bit or 64-bit system addressing is selected by
527 * 64-bit Addressing bit in Host Control 2 register.
528 *
529 * On the other hand the "DesignWare Cores Mobile Storage Host
530 * Controller DWC_mshc / DWC_mshc_lite User Guide" says, that we have to
531 * set DMA_SEL to ADMA2 _only_ mode in the Host Control 2 register.
532 */
533 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
534 ctrl &= ~SDHCI_CTRL_DMA_MASK;
535 ctrl |= SDHCI_CTRL_ADMA32;
536 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
537 }
538
dwcmshc_set_tran_desc(struct cqhci_host * cq_host,u8 ** desc,dma_addr_t addr,int len,bool end,bool dma64)539 static void dwcmshc_set_tran_desc(struct cqhci_host *cq_host, u8 **desc,
540 dma_addr_t addr, int len, bool end, bool dma64)
541 {
542 int tmplen, offset;
543
544 if (likely(!len || BOUNDARY_OK(addr, len))) {
545 cqhci_set_tran_desc(*desc, addr, len, end, dma64);
546 return;
547 }
548
549 offset = addr & (SZ_128M - 1);
550 tmplen = SZ_128M - offset;
551 cqhci_set_tran_desc(*desc, addr, tmplen, false, dma64);
552
553 addr += tmplen;
554 len -= tmplen;
555 *desc += cq_host->trans_desc_len;
556 cqhci_set_tran_desc(*desc, addr, len, end, dma64);
557 }
558
dwcmshc_cqhci_dumpregs(struct mmc_host * mmc)559 static void dwcmshc_cqhci_dumpregs(struct mmc_host *mmc)
560 {
561 sdhci_dumpregs(mmc_priv(mmc));
562 }
563
dwcmshc_rk3568_set_clock(struct sdhci_host * host,unsigned int clock)564 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
565 {
566 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
567 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
568 struct rk35xx_priv *priv = dwc_priv->priv;
569 u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
570 u32 extra, reg;
571 int err;
572
573 host->mmc->actual_clock = 0;
574
575 if (clock == 0) {
576 /* Disable interface clock at initial state. */
577 sdhci_set_clock(host, clock);
578 return;
579 }
580
581 /* Rockchip platform only support 375KHz for identify mode */
582 if (clock <= 400000)
583 clock = 375000;
584
585 err = clk_set_rate(pltfm_host->clk, clock);
586 if (err)
587 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
588
589 sdhci_set_clock(host, clock);
590
591 /* Disable cmd conflict check */
592 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
593 extra = sdhci_readl(host, reg);
594 extra &= ~BIT(0);
595 sdhci_writel(host, extra, reg);
596
597 if (clock <= 52000000) {
598 /*
599 * Disable DLL and reset both of sample and drive clock.
600 * The bypass bit and start bit need to be set if DLL is not locked.
601 */
602 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
603 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
604 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
605 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
606 /*
607 * Before switching to hs400es mode, the driver will enable
608 * enhanced strobe first. PHY needs to configure the parameters
609 * of enhanced strobe first.
610 */
611 extra = DWCMSHC_EMMC_DLL_DLYENA |
612 DLL_STRBIN_DELAY_NUM_SEL |
613 DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
614 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
615 return;
616 }
617
618 /* Reset DLL */
619 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
620 udelay(1);
621 sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
622
623 /*
624 * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but
625 * we must set it in higher speed mode.
626 */
627 extra = DWCMSHC_EMMC_DLL_DLYENA;
628 if (priv->devtype == DWCMSHC_RK3568)
629 extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
630 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
631
632 /* Init DLL settings */
633 extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT |
634 0x2 << DWCMSHC_EMMC_DLL_INC |
635 DWCMSHC_EMMC_DLL_START;
636 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
637 err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
638 extra, DLL_LOCK_WO_TMOUT(extra), 1,
639 500 * USEC_PER_MSEC);
640 if (err) {
641 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
642 return;
643 }
644
645 extra = 0x1 << 16 | /* tune clock stop en */
646 0x3 << 17 | /* pre-change delay */
647 0x3 << 19; /* post-change delay */
648 sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
649
650 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
651 host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
652 txclk_tapnum = priv->txclk_tapnum;
653
654 if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
655 txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES;
656
657 extra = DLL_CMDOUT_SRC_CLK_NEG |
658 DLL_CMDOUT_EN_SRC_CLK_NEG |
659 DWCMSHC_EMMC_DLL_DLYENA |
660 DLL_CMDOUT_TAPNUM_90_DEGREES |
661 DLL_CMDOUT_TAPNUM_FROM_SW;
662 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
663 }
664
665 extra = DWCMSHC_EMMC_DLL_DLYENA |
666 DLL_TXCLK_TAPNUM_FROM_SW |
667 DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL |
668 txclk_tapnum;
669 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
670
671 extra = DWCMSHC_EMMC_DLL_DLYENA |
672 DLL_STRBIN_TAPNUM_DEFAULT |
673 DLL_STRBIN_TAPNUM_FROM_SW;
674 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
675 }
676
rk35xx_sdhci_reset(struct sdhci_host * host,u8 mask)677 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
678 {
679 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
680 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
681 struct rk35xx_priv *priv = dwc_priv->priv;
682
683 if (mask & SDHCI_RESET_ALL && priv->reset) {
684 reset_control_assert(priv->reset);
685 udelay(1);
686 reset_control_deassert(priv->reset);
687 }
688
689 sdhci_reset(host, mask);
690 }
691
dwcmshc_rk35xx_init(struct device * dev,struct sdhci_host * host,struct dwcmshc_priv * dwc_priv)692 static int dwcmshc_rk35xx_init(struct device *dev, struct sdhci_host *host,
693 struct dwcmshc_priv *dwc_priv)
694 {
695 static const char * const clk_ids[] = {"axi", "block", "timer"};
696 struct rk35xx_priv *priv;
697 int err;
698
699 priv = devm_kzalloc(dev, sizeof(struct rk35xx_priv), GFP_KERNEL);
700 if (!priv)
701 return -ENOMEM;
702
703 if (of_device_is_compatible(dev->of_node, "rockchip,rk3588-dwcmshc"))
704 priv->devtype = DWCMSHC_RK3588;
705 else
706 priv->devtype = DWCMSHC_RK3568;
707
708 priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
709 if (IS_ERR(priv->reset)) {
710 err = PTR_ERR(priv->reset);
711 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
712 return err;
713 }
714
715 err = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv,
716 ARRAY_SIZE(clk_ids), clk_ids);
717 if (err)
718 return err;
719
720 if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
721 &priv->txclk_tapnum))
722 priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
723
724 /* Disable cmd conflict check */
725 sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
726 /* Reset previous settings */
727 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
728 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
729
730 dwc_priv->priv = priv;
731
732 return 0;
733 }
734
dwcmshc_rk35xx_postinit(struct sdhci_host * host,struct dwcmshc_priv * dwc_priv)735 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
736 {
737 /*
738 * Don't support highspeed bus mode with low clk speed as we
739 * cannot use DLL for this condition.
740 */
741 if (host->mmc->f_max <= 52000000) {
742 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",
743 host->mmc->f_max);
744 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);
745 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);
746 }
747 }
748
dwcmshc_rk3576_postinit(struct sdhci_host * host,struct dwcmshc_priv * dwc_priv)749 static void dwcmshc_rk3576_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
750 {
751 struct device *dev = mmc_dev(host->mmc);
752 int ret;
753
754 /*
755 * This works around the design of the RK3576's power domains, which
756 * makes the PD_NVM power domain, which the sdhci controller on the
757 * RK3576 is in, never come back the same way once it's run-time
758 * suspended once. This can happen during early kernel boot if no driver
759 * is using either PD_NVM or its child power domain PD_SDGMAC for a
760 * short moment, leading to it being turned off to save power. By
761 * keeping it on, sdhci suspending won't lead to PD_NVM becoming a
762 * candidate for getting turned off.
763 */
764 ret = dev_pm_genpd_rpm_always_on(dev, true);
765 if (ret && ret != -EOPNOTSUPP)
766 dev_warn(dev, "failed to set PD rpm always on, SoC may hang later: %pe\n",
767 ERR_PTR(ret));
768
769 dwcmshc_rk35xx_postinit(host, dwc_priv);
770 }
771
th1520_execute_tuning(struct sdhci_host * host,u32 opcode)772 static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode)
773 {
774 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
775 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
776 u32 val = 0;
777
778 if (host->flags & SDHCI_HS400_TUNING)
779 return 0;
780
781 sdhci_writeb(host, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL),
782 PHY_ATDL_CNFG_R);
783 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
784
785 /*
786 * configure tuning settings:
787 * - center phase select code driven in block gap interval
788 * - disable reporting of framing errors
789 * - disable software managed tuning
790 * - disable user selection of sampling window edges,
791 * instead tuning calculated edges are used
792 */
793 val &= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN |
794 FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK, AT_CTRL_WIN_EDGE_SEL));
795
796 /*
797 * configure tuning settings:
798 * - enable auto-tuning
799 * - enable sampling window threshold
800 * - stop clocks during phase code change
801 * - set max latency in cycles between tx and rx clocks
802 * - set max latency in cycles to switch output phase
803 * - set max sampling window threshold value
804 */
805 val |= AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN;
806 val |= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY);
807 val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY);
808 val |= FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL);
809
810 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
811 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
812
813 /* perform tuning */
814 sdhci_start_tuning(host);
815 host->tuning_loop_count = 128;
816 host->tuning_err = __sdhci_execute_tuning(host, opcode);
817 if (host->tuning_err) {
818 /* disable auto-tuning upon tuning error */
819 val &= ~AT_CTRL_AT_EN;
820 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
821 dev_err(mmc_dev(host->mmc), "tuning failed: %d\n", host->tuning_err);
822 return -EIO;
823 }
824 sdhci_end_tuning(host);
825
826 return 0;
827 }
828
th1520_sdhci_reset(struct sdhci_host * host,u8 mask)829 static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask)
830 {
831 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
832 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
833 u16 ctrl_2;
834
835 sdhci_reset(host, mask);
836
837 /* The T-Head 1520 SoC does not comply with the SDHCI specification
838 * regarding the "Software Reset for CMD line should clear 'Command
839 * Complete' in the Normal Interrupt Status Register." Clear the bit
840 * here to compensate for this quirk.
841 */
842 if (mask & SDHCI_RESET_CMD)
843 sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
844
845 if (priv->flags & FLAG_IO_FIXED_1V8) {
846 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
847 if (!(ctrl_2 & SDHCI_CTRL_VDD_180)) {
848 ctrl_2 |= SDHCI_CTRL_VDD_180;
849 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
850 }
851 }
852 }
853
th1520_init(struct device * dev,struct sdhci_host * host,struct dwcmshc_priv * dwc_priv)854 static int th1520_init(struct device *dev,
855 struct sdhci_host *host,
856 struct dwcmshc_priv *dwc_priv)
857 {
858 dwc_priv->delay_line = PHY_SDCLKDL_DC_DEFAULT;
859
860 if (device_property_read_bool(dev, "mmc-ddr-1_8v") ||
861 device_property_read_bool(dev, "mmc-hs200-1_8v") ||
862 device_property_read_bool(dev, "mmc-hs400-1_8v"))
863 dwc_priv->flags |= FLAG_IO_FIXED_1V8;
864 else
865 dwc_priv->flags &= ~FLAG_IO_FIXED_1V8;
866
867 /*
868 * start_signal_voltage_switch() will try 3.3V first
869 * then 1.8V. Use SDHCI_SIGNALING_180 rather than
870 * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V
871 * in sdhci_start_signal_voltage_switch().
872 */
873 if (dwc_priv->flags & FLAG_IO_FIXED_1V8) {
874 host->flags &= ~SDHCI_SIGNALING_330;
875 host->flags |= SDHCI_SIGNALING_180;
876 }
877
878 sdhci_enable_v4_mode(host);
879
880 return 0;
881 }
882
cv18xx_sdhci_reset(struct sdhci_host * host,u8 mask)883 static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask)
884 {
885 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
886 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
887 u32 val, emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
888
889 sdhci_reset(host, mask);
890
891 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {
892 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
893 val |= CV18XX_EMMC_FUNC_EN;
894 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
895 }
896
897 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
898 val |= CV18XX_LATANCY_1T;
899 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
900
901 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);
902 val |= CV18XX_PHY_TX_BPS;
903 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);
904
905 val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) |
906 FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) |
907 FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, 0) |
908 FIELD_PREP(CV18XX_PHY_RX_SRC_MSK, CV18XX_PHY_RX_SRC_INVERT_RX_CLK));
909 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY);
910 }
911
cv18xx_sdhci_set_tap(struct sdhci_host * host,int tap)912 static void cv18xx_sdhci_set_tap(struct sdhci_host *host, int tap)
913 {
914 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
915 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
916 u16 clk;
917 u32 val;
918
919 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
920 clk &= ~SDHCI_CLOCK_CARD_EN;
921 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
922
923 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
924 val &= ~CV18XX_LATANCY_1T;
925 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
926
927 val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) |
928 FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) |
929 FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, tap));
930 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY);
931
932 sdhci_writel(host, 0, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);
933
934 clk |= SDHCI_CLOCK_CARD_EN;
935 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
936 usleep_range(1000, 2000);
937 }
938
cv18xx_retry_tuning(struct mmc_host * mmc,u32 opcode,int * cmd_error)939 static int cv18xx_retry_tuning(struct mmc_host *mmc, u32 opcode, int *cmd_error)
940 {
941 int ret, retry = 0;
942
943 while (retry < CV18XX_RETRY_TUNING_MAX) {
944 ret = mmc_send_tuning(mmc, opcode, NULL);
945 if (ret)
946 return ret;
947 retry++;
948 }
949
950 return 0;
951 }
952
cv18xx_sdhci_post_tuning(struct sdhci_host * host)953 static void cv18xx_sdhci_post_tuning(struct sdhci_host *host)
954 {
955 u32 val;
956
957 val = sdhci_readl(host, SDHCI_INT_STATUS);
958 val |= SDHCI_INT_DATA_AVAIL;
959 sdhci_writel(host, val, SDHCI_INT_STATUS);
960
961 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
962 }
963
cv18xx_sdhci_execute_tuning(struct sdhci_host * host,u32 opcode)964 static int cv18xx_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
965 {
966 int min, max, avg, ret;
967 int win_length, target_min, target_max, target_win_length;
968
969 min = max = 0;
970 target_win_length = 0;
971
972 sdhci_reset_tuning(host);
973
974 while (max < CV18XX_TUNE_MAX) {
975 /* find the mininum delay first which can pass tuning */
976 while (min < CV18XX_TUNE_MAX) {
977 cv18xx_sdhci_set_tap(host, min);
978 if (!cv18xx_retry_tuning(host->mmc, opcode, NULL))
979 break;
980 min += CV18XX_TUNE_STEP;
981 }
982
983 /* find the maxinum delay which can not pass tuning */
984 max = min + CV18XX_TUNE_STEP;
985 while (max < CV18XX_TUNE_MAX) {
986 cv18xx_sdhci_set_tap(host, max);
987 if (cv18xx_retry_tuning(host->mmc, opcode, NULL)) {
988 max -= CV18XX_TUNE_STEP;
989 break;
990 }
991 max += CV18XX_TUNE_STEP;
992 }
993
994 win_length = max - min + 1;
995 /* get the largest pass window */
996 if (win_length > target_win_length) {
997 target_win_length = win_length;
998 target_min = min;
999 target_max = max;
1000 }
1001
1002 /* continue to find the next pass window */
1003 min = max + CV18XX_TUNE_STEP;
1004 }
1005
1006 cv18xx_sdhci_post_tuning(host);
1007
1008 /* use average delay to get the best timing */
1009 avg = (target_min + target_max) / 2;
1010 cv18xx_sdhci_set_tap(host, avg);
1011 ret = mmc_send_tuning(host->mmc, opcode, NULL);
1012
1013 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1014 ret ? "failed" : "passed", avg, ret);
1015
1016 return ret;
1017 }
1018
sg2042_sdhci_phy_init(struct sdhci_host * host)1019 static inline void sg2042_sdhci_phy_init(struct sdhci_host *host)
1020 {
1021 u32 val;
1022
1023 /* Asset phy reset & set tx drive strength */
1024 val = sdhci_readl(host, PHY_CNFG_R);
1025 val &= ~PHY_CNFG_RSTN_DEASSERT;
1026 val |= FIELD_PREP(PHY_CNFG_PHY_PWRGOOD_MASK, 1);
1027 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP_SG2042);
1028 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN_SG2042);
1029 sdhci_writel(host, val, PHY_CNFG_R);
1030
1031 /* Configure phy pads */
1032 val = PHY_PAD_RXSEL_3V3;
1033 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);
1034 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
1035 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042);
1036 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
1037 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
1038 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
1039
1040 val = PHY_PAD_RXSEL_3V3;
1041 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
1042 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042);
1043 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
1044
1045 val = PHY_PAD_RXSEL_3V3;
1046 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);
1047 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
1048 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042);
1049 sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
1050
1051 /* Configure delay line */
1052 /* Enable fixed delay */
1053 sdhci_writeb(host, PHY_SDCLKDL_CNFG_EXTDLY_EN, PHY_SDCLKDL_CNFG_R);
1054 /*
1055 * Set delay line.
1056 * Its recommended that bit UPDATE_DC[4] is 1 when SDCLKDL_DC is being written.
1057 * Ensure UPDATE_DC[4] is '0' when not updating code.
1058 */
1059 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
1060 val |= PHY_SDCLKDL_CNFG_UPDATE;
1061 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
1062 /* Add 10 * 70ps = 0.7ns for output delay */
1063 sdhci_writeb(host, 10, PHY_SDCLKDL_DC_R);
1064 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
1065 val &= ~(PHY_SDCLKDL_CNFG_UPDATE);
1066 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
1067
1068 /* Set SMPLDL_CNFG, Bypass */
1069 sdhci_writeb(host, PHY_SMPLDL_CNFG_BYPASS_EN, PHY_SMPLDL_CNFG_R);
1070
1071 /* Set ATDL_CNFG, tuning clk not use for init */
1072 val = FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL_SG2042);
1073 sdhci_writeb(host, val, PHY_ATDL_CNFG_R);
1074
1075 /* Deasset phy reset */
1076 val = sdhci_readl(host, PHY_CNFG_R);
1077 val |= PHY_CNFG_RSTN_DEASSERT;
1078 sdhci_writel(host, val, PHY_CNFG_R);
1079 }
1080
sg2042_sdhci_reset(struct sdhci_host * host,u8 mask)1081 static void sg2042_sdhci_reset(struct sdhci_host *host, u8 mask)
1082 {
1083 sdhci_reset(host, mask);
1084
1085 if (mask & SDHCI_RESET_ALL)
1086 sg2042_sdhci_phy_init(host);
1087 }
1088
sg2042_init(struct device * dev,struct sdhci_host * host,struct dwcmshc_priv * dwc_priv)1089 static int sg2042_init(struct device *dev, struct sdhci_host *host,
1090 struct dwcmshc_priv *dwc_priv)
1091 {
1092 static const char * const clk_ids[] = {"timer"};
1093
1094 return dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv,
1095 ARRAY_SIZE(clk_ids), clk_ids);
1096 }
1097
1098 static const struct sdhci_ops sdhci_dwcmshc_ops = {
1099 .set_clock = sdhci_set_clock,
1100 .set_bus_width = sdhci_set_bus_width,
1101 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
1102 .get_max_clock = dwcmshc_get_max_clock,
1103 .reset = sdhci_reset,
1104 .adma_write_desc = dwcmshc_adma_write_desc,
1105 .irq = dwcmshc_cqe_irq_handler,
1106 };
1107
1108 #ifdef CONFIG_ACPI
dwcmshc_bf3_hw_reset(struct sdhci_host * host)1109 static void dwcmshc_bf3_hw_reset(struct sdhci_host *host)
1110 {
1111 struct arm_smccc_res res = { 0 };
1112
1113 arm_smccc_smc(BLUEFIELD_SMC_SET_EMMC_RST_N, 0, 0, 0, 0, 0, 0, 0, &res);
1114
1115 if (res.a0)
1116 pr_err("%s: RST_N failed.\n", mmc_hostname(host->mmc));
1117 }
1118
1119 static const struct sdhci_ops sdhci_dwcmshc_bf3_ops = {
1120 .set_clock = sdhci_set_clock,
1121 .set_bus_width = sdhci_set_bus_width,
1122 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
1123 .get_max_clock = dwcmshc_get_max_clock,
1124 .reset = sdhci_reset,
1125 .adma_write_desc = dwcmshc_adma_write_desc,
1126 .irq = dwcmshc_cqe_irq_handler,
1127 .hw_reset = dwcmshc_bf3_hw_reset,
1128 };
1129 #endif
1130
1131 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {
1132 .set_clock = dwcmshc_rk3568_set_clock,
1133 .set_bus_width = sdhci_set_bus_width,
1134 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
1135 .get_max_clock = rk35xx_get_max_clock,
1136 .reset = rk35xx_sdhci_reset,
1137 .adma_write_desc = dwcmshc_adma_write_desc,
1138 .irq = dwcmshc_cqe_irq_handler,
1139 };
1140
1141 static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = {
1142 .set_clock = sdhci_set_clock,
1143 .set_bus_width = sdhci_set_bus_width,
1144 .set_uhs_signaling = th1520_set_uhs_signaling,
1145 .get_max_clock = dwcmshc_get_max_clock,
1146 .reset = th1520_sdhci_reset,
1147 .adma_write_desc = dwcmshc_adma_write_desc,
1148 .voltage_switch = dwcmshc_phy_init,
1149 .platform_execute_tuning = th1520_execute_tuning,
1150 };
1151
1152 static const struct sdhci_ops sdhci_dwcmshc_cv18xx_ops = {
1153 .set_clock = sdhci_set_clock,
1154 .set_bus_width = sdhci_set_bus_width,
1155 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
1156 .get_max_clock = dwcmshc_get_max_clock,
1157 .reset = cv18xx_sdhci_reset,
1158 .adma_write_desc = dwcmshc_adma_write_desc,
1159 .platform_execute_tuning = cv18xx_sdhci_execute_tuning,
1160 };
1161
1162 static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = {
1163 .set_clock = sdhci_set_clock,
1164 .set_bus_width = sdhci_set_bus_width,
1165 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
1166 .get_max_clock = dwcmshc_get_max_clock,
1167 .reset = sg2042_sdhci_reset,
1168 .adma_write_desc = dwcmshc_adma_write_desc,
1169 .platform_execute_tuning = th1520_execute_tuning,
1170 };
1171
1172 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata = {
1173 .pdata = {
1174 .ops = &sdhci_dwcmshc_ops,
1175 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1176 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1177 },
1178 };
1179
1180 #ifdef CONFIG_ACPI
1181 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_bf3_pdata = {
1182 .pdata = {
1183 .ops = &sdhci_dwcmshc_bf3_ops,
1184 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1185 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1186 SDHCI_QUIRK2_ACMD23_BROKEN,
1187 },
1188 };
1189 #endif
1190
1191 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {
1192 .pdata = {
1193 .ops = &sdhci_dwcmshc_rk35xx_ops,
1194 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1195 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
1196 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1197 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
1198 },
1199 .init = dwcmshc_rk35xx_init,
1200 .postinit = dwcmshc_rk35xx_postinit,
1201 };
1202
1203 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk3576_pdata = {
1204 .pdata = {
1205 .ops = &sdhci_dwcmshc_rk35xx_ops,
1206 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1207 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
1208 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1209 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
1210 },
1211 .init = dwcmshc_rk35xx_init,
1212 .postinit = dwcmshc_rk3576_postinit,
1213 };
1214
1215 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_th1520_pdata = {
1216 .pdata = {
1217 .ops = &sdhci_dwcmshc_th1520_ops,
1218 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1219 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1220 },
1221 .init = th1520_init,
1222 };
1223
1224 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_cv18xx_pdata = {
1225 .pdata = {
1226 .ops = &sdhci_dwcmshc_cv18xx_ops,
1227 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1228 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1229 },
1230 };
1231
1232 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = {
1233 .pdata = {
1234 .ops = &sdhci_dwcmshc_sg2042_ops,
1235 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1236 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1237 },
1238 .init = sg2042_init,
1239 };
1240
1241 static const struct cqhci_host_ops dwcmshc_cqhci_ops = {
1242 .enable = dwcmshc_sdhci_cqe_enable,
1243 .disable = sdhci_cqe_disable,
1244 .dumpregs = dwcmshc_cqhci_dumpregs,
1245 .set_tran_desc = dwcmshc_set_tran_desc,
1246 };
1247
dwcmshc_cqhci_init(struct sdhci_host * host,struct platform_device * pdev)1248 static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device *pdev)
1249 {
1250 struct cqhci_host *cq_host;
1251 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1252 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
1253 bool dma64 = false;
1254 u16 clk;
1255 int err;
1256
1257 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1258 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1259 if (!cq_host) {
1260 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: not enough memory\n");
1261 goto dsbl_cqe_caps;
1262 }
1263
1264 /*
1265 * For dwcmshc host controller we have to enable internal clock
1266 * before access to some registers from Vendor Specific Area 2.
1267 */
1268 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1269 clk |= SDHCI_CLOCK_INT_EN;
1270 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1271 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1272 if (!(clk & SDHCI_CLOCK_INT_EN)) {
1273 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: internal clock enable error\n");
1274 goto free_cq_host;
1275 }
1276
1277 cq_host->mmio = host->ioaddr + priv->vendor_specific_area2;
1278 cq_host->ops = &dwcmshc_cqhci_ops;
1279
1280 /* Enable using of 128-bit task descriptors */
1281 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1282 if (dma64) {
1283 dev_dbg(mmc_dev(host->mmc), "128-bit task descriptors\n");
1284 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1285 }
1286 err = cqhci_init(cq_host, host->mmc, dma64);
1287 if (err) {
1288 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: error %d\n", err);
1289 goto int_clock_disable;
1290 }
1291
1292 dev_dbg(mmc_dev(host->mmc), "CQE init done\n");
1293
1294 return;
1295
1296 int_clock_disable:
1297 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1298 clk &= ~SDHCI_CLOCK_INT_EN;
1299 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1300
1301 free_cq_host:
1302 devm_kfree(&pdev->dev, cq_host);
1303
1304 dsbl_cqe_caps:
1305 host->mmc->caps2 &= ~(MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD);
1306 }
1307
1308 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
1309 {
1310 .compatible = "rockchip,rk3588-dwcmshc",
1311 .data = &sdhci_dwcmshc_rk35xx_pdata,
1312 },
1313 {
1314 .compatible = "rockchip,rk3576-dwcmshc",
1315 .data = &sdhci_dwcmshc_rk3576_pdata,
1316 },
1317 {
1318 .compatible = "rockchip,rk3568-dwcmshc",
1319 .data = &sdhci_dwcmshc_rk35xx_pdata,
1320 },
1321 {
1322 .compatible = "snps,dwcmshc-sdhci",
1323 .data = &sdhci_dwcmshc_pdata,
1324 },
1325 {
1326 .compatible = "sophgo,cv1800b-dwcmshc",
1327 .data = &sdhci_dwcmshc_cv18xx_pdata,
1328 },
1329 {
1330 .compatible = "sophgo,sg2002-dwcmshc",
1331 .data = &sdhci_dwcmshc_cv18xx_pdata,
1332 },
1333 {
1334 .compatible = "thead,th1520-dwcmshc",
1335 .data = &sdhci_dwcmshc_th1520_pdata,
1336 },
1337 {
1338 .compatible = "sophgo,sg2042-dwcmshc",
1339 .data = &sdhci_dwcmshc_sg2042_pdata,
1340 },
1341 {},
1342 };
1343 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
1344
1345 #ifdef CONFIG_ACPI
1346 static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {
1347 {
1348 .id = "MLNXBF30",
1349 .driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata,
1350 },
1351 {}
1352 };
1353 MODULE_DEVICE_TABLE(acpi, sdhci_dwcmshc_acpi_ids);
1354 #endif
1355
dwcmshc_probe(struct platform_device * pdev)1356 static int dwcmshc_probe(struct platform_device *pdev)
1357 {
1358 struct device *dev = &pdev->dev;
1359 struct sdhci_pltfm_host *pltfm_host;
1360 struct sdhci_host *host;
1361 struct dwcmshc_priv *priv;
1362 const struct dwcmshc_pltfm_data *pltfm_data;
1363 int err;
1364 u32 extra, caps;
1365
1366 pltfm_data = device_get_match_data(&pdev->dev);
1367 if (!pltfm_data) {
1368 dev_err(&pdev->dev, "Error: No device match data found\n");
1369 return -ENODEV;
1370 }
1371
1372 host = sdhci_pltfm_init(pdev, &pltfm_data->pdata,
1373 sizeof(struct dwcmshc_priv));
1374 if (IS_ERR(host))
1375 return PTR_ERR(host);
1376
1377 /*
1378 * extra adma table cnt for cross 128M boundary handling.
1379 */
1380 extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
1381 if (extra > SDHCI_MAX_SEGS)
1382 extra = SDHCI_MAX_SEGS;
1383 host->adma_table_cnt += extra;
1384
1385 pltfm_host = sdhci_priv(host);
1386 priv = sdhci_pltfm_priv(pltfm_host);
1387
1388 if (dev->of_node) {
1389 pltfm_host->clk = devm_clk_get(dev, "core");
1390 if (IS_ERR(pltfm_host->clk)) {
1391 err = PTR_ERR(pltfm_host->clk);
1392 dev_err(dev, "failed to get core clk: %d\n", err);
1393 goto free_pltfm;
1394 }
1395 err = clk_prepare_enable(pltfm_host->clk);
1396 if (err)
1397 goto free_pltfm;
1398
1399 priv->bus_clk = devm_clk_get(dev, "bus");
1400 if (!IS_ERR(priv->bus_clk))
1401 clk_prepare_enable(priv->bus_clk);
1402 }
1403
1404 err = mmc_of_parse(host->mmc);
1405 if (err)
1406 goto err_clk;
1407
1408 sdhci_get_of_property(pdev);
1409
1410 priv->vendor_specific_area1 =
1411 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;
1412
1413 host->mmc_host_ops.request = dwcmshc_request;
1414 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
1415 host->mmc_host_ops.execute_tuning = dwcmshc_execute_tuning;
1416
1417 if (pltfm_data->init) {
1418 err = pltfm_data->init(&pdev->dev, host, priv);
1419 if (err)
1420 goto err_clk;
1421 }
1422
1423 #ifdef CONFIG_ACPI
1424 if (pltfm_data == &sdhci_dwcmshc_bf3_pdata)
1425 sdhci_enable_v4_mode(host);
1426 #endif
1427
1428 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
1429 if (caps & SDHCI_CAN_64BIT_V4)
1430 sdhci_enable_v4_mode(host);
1431
1432 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1433
1434 pm_runtime_get_noresume(dev);
1435 pm_runtime_set_active(dev);
1436 pm_runtime_enable(dev);
1437
1438 err = sdhci_setup_host(host);
1439 if (err)
1440 goto err_rpm;
1441
1442 /* Setup Command Queue Engine if enabled */
1443 if (device_property_read_bool(&pdev->dev, "supports-cqe")) {
1444 priv->vendor_specific_area2 =
1445 sdhci_readw(host, DWCMSHC_P_VENDOR_AREA2);
1446
1447 dwcmshc_cqhci_init(host, pdev);
1448 }
1449
1450 if (pltfm_data->postinit)
1451 pltfm_data->postinit(host, priv);
1452
1453 err = __sdhci_add_host(host);
1454 if (err)
1455 goto err_setup_host;
1456
1457 pm_runtime_put(dev);
1458
1459 return 0;
1460
1461 err_setup_host:
1462 sdhci_cleanup_host(host);
1463 err_rpm:
1464 pm_runtime_disable(dev);
1465 pm_runtime_put_noidle(dev);
1466 err_clk:
1467 clk_disable_unprepare(pltfm_host->clk);
1468 clk_disable_unprepare(priv->bus_clk);
1469 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks);
1470 free_pltfm:
1471 sdhci_pltfm_free(pdev);
1472 return err;
1473 }
1474
dwcmshc_disable_card_clk(struct sdhci_host * host)1475 static void dwcmshc_disable_card_clk(struct sdhci_host *host)
1476 {
1477 u16 ctrl;
1478
1479 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1480 if (ctrl & SDHCI_CLOCK_CARD_EN) {
1481 ctrl &= ~SDHCI_CLOCK_CARD_EN;
1482 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
1483 }
1484 }
1485
dwcmshc_remove(struct platform_device * pdev)1486 static void dwcmshc_remove(struct platform_device *pdev)
1487 {
1488 struct sdhci_host *host = platform_get_drvdata(pdev);
1489 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1490 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
1491
1492 pm_runtime_get_sync(&pdev->dev);
1493 pm_runtime_disable(&pdev->dev);
1494 pm_runtime_put_noidle(&pdev->dev);
1495
1496 sdhci_remove_host(host, 0);
1497
1498 dwcmshc_disable_card_clk(host);
1499
1500 clk_disable_unprepare(pltfm_host->clk);
1501 clk_disable_unprepare(priv->bus_clk);
1502 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks);
1503 sdhci_pltfm_free(pdev);
1504 }
1505
1506 #ifdef CONFIG_PM_SLEEP
dwcmshc_suspend(struct device * dev)1507 static int dwcmshc_suspend(struct device *dev)
1508 {
1509 struct sdhci_host *host = dev_get_drvdata(dev);
1510 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1511 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
1512 int ret;
1513
1514 pm_runtime_resume(dev);
1515
1516 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1517 ret = cqhci_suspend(host->mmc);
1518 if (ret)
1519 return ret;
1520 }
1521
1522 ret = sdhci_suspend_host(host);
1523 if (ret)
1524 return ret;
1525
1526 clk_disable_unprepare(pltfm_host->clk);
1527 if (!IS_ERR(priv->bus_clk))
1528 clk_disable_unprepare(priv->bus_clk);
1529
1530 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks);
1531
1532 return ret;
1533 }
1534
dwcmshc_resume(struct device * dev)1535 static int dwcmshc_resume(struct device *dev)
1536 {
1537 struct sdhci_host *host = dev_get_drvdata(dev);
1538 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1539 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
1540 int ret;
1541
1542 ret = clk_prepare_enable(pltfm_host->clk);
1543 if (ret)
1544 return ret;
1545
1546 if (!IS_ERR(priv->bus_clk)) {
1547 ret = clk_prepare_enable(priv->bus_clk);
1548 if (ret)
1549 goto disable_clk;
1550 }
1551
1552 ret = clk_bulk_prepare_enable(priv->num_other_clks, priv->other_clks);
1553 if (ret)
1554 goto disable_bus_clk;
1555
1556 ret = sdhci_resume_host(host);
1557 if (ret)
1558 goto disable_other_clks;
1559
1560 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1561 ret = cqhci_resume(host->mmc);
1562 if (ret)
1563 goto disable_other_clks;
1564 }
1565
1566 return 0;
1567
1568 disable_other_clks:
1569 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks);
1570 disable_bus_clk:
1571 if (!IS_ERR(priv->bus_clk))
1572 clk_disable_unprepare(priv->bus_clk);
1573 disable_clk:
1574 clk_disable_unprepare(pltfm_host->clk);
1575 return ret;
1576 }
1577 #endif
1578
1579 #ifdef CONFIG_PM
1580
dwcmshc_enable_card_clk(struct sdhci_host * host)1581 static void dwcmshc_enable_card_clk(struct sdhci_host *host)
1582 {
1583 u16 ctrl;
1584
1585 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1586 if ((ctrl & SDHCI_CLOCK_INT_EN) && !(ctrl & SDHCI_CLOCK_CARD_EN)) {
1587 ctrl |= SDHCI_CLOCK_CARD_EN;
1588 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
1589 }
1590 }
1591
dwcmshc_runtime_suspend(struct device * dev)1592 static int dwcmshc_runtime_suspend(struct device *dev)
1593 {
1594 struct sdhci_host *host = dev_get_drvdata(dev);
1595
1596 dwcmshc_disable_card_clk(host);
1597
1598 return 0;
1599 }
1600
dwcmshc_runtime_resume(struct device * dev)1601 static int dwcmshc_runtime_resume(struct device *dev)
1602 {
1603 struct sdhci_host *host = dev_get_drvdata(dev);
1604
1605 dwcmshc_enable_card_clk(host);
1606
1607 return 0;
1608 }
1609
1610 #endif
1611
1612 static const struct dev_pm_ops dwcmshc_pmops = {
1613 SET_SYSTEM_SLEEP_PM_OPS(dwcmshc_suspend, dwcmshc_resume)
1614 SET_RUNTIME_PM_OPS(dwcmshc_runtime_suspend,
1615 dwcmshc_runtime_resume, NULL)
1616 };
1617
1618 static struct platform_driver sdhci_dwcmshc_driver = {
1619 .driver = {
1620 .name = "sdhci-dwcmshc",
1621 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1622 .of_match_table = sdhci_dwcmshc_dt_ids,
1623 .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
1624 .pm = &dwcmshc_pmops,
1625 },
1626 .probe = dwcmshc_probe,
1627 .remove = dwcmshc_remove,
1628 };
1629 module_platform_driver(sdhci_dwcmshc_driver);
1630
1631 MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC");
1632 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
1633 MODULE_LICENSE("GPL v2");
1634