1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2011 Jamie Iles
4 *
5 * All enquiries to support@picochip.com
6 */
7 #include <linux/acpi.h>
8 #include <linux/clk.h>
9 #include <linux/err.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/gpio/generic.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/ioport.h>
16 #include <linux/irq.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/property.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23
24 #include "gpiolib-acpi.h"
25
26 #define GPIO_SWPORTA_DR 0x00
27 #define GPIO_SWPORTA_DDR 0x04
28 #define GPIO_SWPORTB_DR 0x0c
29 #define GPIO_SWPORTB_DDR 0x10
30 #define GPIO_SWPORTC_DR 0x18
31 #define GPIO_SWPORTC_DDR 0x1c
32 #define GPIO_SWPORTD_DR 0x24
33 #define GPIO_SWPORTD_DDR 0x28
34 #define GPIO_INTEN 0x30
35 #define GPIO_INTMASK 0x34
36 #define GPIO_INTTYPE_LEVEL 0x38
37 #define GPIO_INT_POLARITY 0x3c
38 #define GPIO_INTSTATUS 0x40
39 #define GPIO_PORTA_DEBOUNCE 0x48
40 #define GPIO_PORTA_EOI 0x4c
41 #define GPIO_EXT_PORTA 0x50
42 #define GPIO_EXT_PORTB 0x54
43 #define GPIO_EXT_PORTC 0x58
44 #define GPIO_EXT_PORTD 0x5c
45
46 #define DWAPB_DRIVER_NAME "gpio-dwapb"
47 #define DWAPB_MAX_PORTS 4
48 #define DWAPB_MAX_GPIOS 32
49
50 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
51 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
52 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
53
54 #define GPIO_REG_OFFSET_V1 0
55 #define GPIO_REG_OFFSET_V2 1
56 #define GPIO_REG_OFFSET_MASK BIT(0)
57
58 #define GPIO_INTMASK_V2 0x44
59 #define GPIO_INTTYPE_LEVEL_V2 0x34
60 #define GPIO_INT_POLARITY_V2 0x38
61 #define GPIO_INTSTATUS_V2 0x3c
62 #define GPIO_PORTA_EOI_V2 0x40
63
64 #define DWAPB_NR_CLOCKS 2
65
66 struct dwapb_gpio;
67
68 struct dwapb_port_property {
69 struct fwnode_handle *fwnode;
70 unsigned int idx;
71 unsigned int ngpio;
72 unsigned int gpio_base;
73 int irq[DWAPB_MAX_GPIOS];
74 };
75
76 struct dwapb_platform_data {
77 unsigned int nports;
78 struct dwapb_port_property properties[] __counted_by(nports);
79 };
80
81 /* Store GPIO context across system-wide suspend/resume transitions */
82 struct dwapb_context {
83 u32 data;
84 u32 dir;
85 u32 ext;
86 u32 int_en;
87 u32 int_mask;
88 u32 int_type;
89 u32 int_pol;
90 u32 int_deb;
91 u32 wake_en;
92 };
93
94 struct dwapb_gpio_port_irqchip {
95 unsigned int nr_irqs;
96 unsigned int irq[DWAPB_MAX_GPIOS];
97 };
98
99 struct dwapb_gpio_port {
100 struct gpio_generic_chip chip;
101 struct dwapb_gpio_port_irqchip *pirq;
102 struct dwapb_gpio *gpio;
103 struct dwapb_context *ctx;
104 unsigned int idx;
105 };
106
to_dwapb_gpio(struct gpio_chip * gc)107 static inline struct dwapb_gpio *to_dwapb_gpio(struct gpio_chip *gc)
108 {
109 return container_of(to_gpio_generic_chip(gc),
110 struct dwapb_gpio_port, chip)->gpio;
111 }
112
113 struct dwapb_gpio {
114 struct device *dev;
115 void __iomem *regs;
116 unsigned int nr_ports;
117 unsigned int flags;
118 struct reset_control *rst;
119 struct clk_bulk_data clks[DWAPB_NR_CLOCKS];
120 bool clocks_on_for_wake;
121 struct dwapb_gpio_port ports[] __counted_by(nr_ports);
122 };
123
gpio_reg_v2_convert(unsigned int offset)124 static inline u32 gpio_reg_v2_convert(unsigned int offset)
125 {
126 switch (offset) {
127 case GPIO_INTMASK:
128 return GPIO_INTMASK_V2;
129 case GPIO_INTTYPE_LEVEL:
130 return GPIO_INTTYPE_LEVEL_V2;
131 case GPIO_INT_POLARITY:
132 return GPIO_INT_POLARITY_V2;
133 case GPIO_INTSTATUS:
134 return GPIO_INTSTATUS_V2;
135 case GPIO_PORTA_EOI:
136 return GPIO_PORTA_EOI_V2;
137 }
138
139 return offset;
140 }
141
gpio_reg_convert(struct dwapb_gpio * gpio,unsigned int offset)142 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
143 {
144 if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2)
145 return gpio_reg_v2_convert(offset);
146
147 return offset;
148 }
149
dwapb_read(struct dwapb_gpio * gpio,unsigned int offset)150 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
151 {
152 struct gpio_generic_chip *chip = &gpio->ports[0].chip;
153 void __iomem *reg_base = gpio->regs;
154
155 return gpio_generic_read_reg(chip, reg_base + gpio_reg_convert(gpio, offset));
156 }
157
dwapb_write(struct dwapb_gpio * gpio,unsigned int offset,u32 val)158 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
159 u32 val)
160 {
161 struct gpio_generic_chip *chip = &gpio->ports[0].chip;
162 void __iomem *reg_base = gpio->regs;
163
164 gpio_generic_write_reg(chip, reg_base + gpio_reg_convert(gpio, offset), val);
165 }
166
dwapb_offs_to_port(struct dwapb_gpio * gpio,unsigned int offs)167 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
168 {
169 struct dwapb_gpio_port *port;
170 int i;
171
172 for (i = 0; i < gpio->nr_ports; i++) {
173 port = &gpio->ports[i];
174 if (port->idx == offs / DWAPB_MAX_GPIOS)
175 return port;
176 }
177
178 return NULL;
179 }
180
dwapb_toggle_trigger(struct dwapb_gpio * gpio,unsigned int offs)181 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
182 {
183 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
184 struct gpio_chip *gc;
185 u32 pol;
186 int val;
187
188 if (!port)
189 return;
190 gc = &port->chip.gc;
191
192 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
193 /* Just read the current value right out of the data register */
194 val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
195 if (val)
196 pol &= ~BIT(offs);
197 else
198 pol |= BIT(offs);
199
200 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
201 }
202
dwapb_irq_init_hw(struct gpio_chip * gc)203 static int dwapb_irq_init_hw(struct gpio_chip *gc)
204 {
205 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
206
207 /*
208 * GPIO interrupts may retain stale state across warm reboots when
209 * peripherals stay powered. Force a known-safe state before the GPIO
210 * irqchip and irq domain are set up.
211 */
212 dwapb_write(gpio, GPIO_INTEN, 0);
213 dwapb_write(gpio, GPIO_INTMASK, 0xffffffff);
214 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
215
216 return 0;
217 }
218
dwapb_do_irq(struct dwapb_gpio * gpio)219 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
220 {
221 struct gpio_generic_chip *gen_gc = &gpio->ports[0].chip;
222 unsigned long irq_status;
223 irq_hw_number_t hwirq;
224
225 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
226 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
227 int gpio_irq = irq_find_mapping(gen_gc->gc.irq.domain, hwirq);
228 u32 irq_type = irq_get_trigger_type(gpio_irq);
229
230 generic_handle_irq(gpio_irq);
231
232 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
233 dwapb_toggle_trigger(gpio, hwirq);
234 }
235
236 return irq_status;
237 }
238
dwapb_irq_handler(struct irq_desc * desc)239 static void dwapb_irq_handler(struct irq_desc *desc)
240 {
241 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
242 struct irq_chip *chip = irq_desc_get_chip(desc);
243
244 chained_irq_enter(chip, desc);
245 dwapb_do_irq(gpio);
246 chained_irq_exit(chip, desc);
247 }
248
dwapb_irq_handler_mfd(int irq,void * dev_id)249 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
250 {
251 return IRQ_RETVAL(dwapb_do_irq(dev_id));
252 }
253
dwapb_irq_ack(struct irq_data * d)254 static void dwapb_irq_ack(struct irq_data *d)
255 {
256 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
257 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
258 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
259 u32 val = BIT(irqd_to_hwirq(d));
260
261 guard(gpio_generic_lock_irqsave)(gen_gc);
262
263 dwapb_write(gpio, GPIO_PORTA_EOI, val);
264 }
265
dwapb_irq_mask(struct irq_data * d)266 static void dwapb_irq_mask(struct irq_data *d)
267 {
268 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
269 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
270 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
271 irq_hw_number_t hwirq = irqd_to_hwirq(d);
272 u32 val;
273
274 scoped_guard(gpio_generic_lock_irqsave, gen_gc) {
275 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
276 dwapb_write(gpio, GPIO_INTMASK, val);
277 }
278
279 gpiochip_disable_irq(gc, hwirq);
280 }
281
dwapb_irq_unmask(struct irq_data * d)282 static void dwapb_irq_unmask(struct irq_data *d)
283 {
284 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
285 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
286 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
287 irq_hw_number_t hwirq = irqd_to_hwirq(d);
288 u32 val;
289
290 gpiochip_enable_irq(gc, hwirq);
291
292 guard(gpio_generic_lock_irqsave)(gen_gc);
293
294 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
295 dwapb_write(gpio, GPIO_INTMASK, val);
296 }
297
dwapb_irq_enable(struct irq_data * d)298 static void dwapb_irq_enable(struct irq_data *d)
299 {
300 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
301 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
302 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
303 irq_hw_number_t hwirq = irqd_to_hwirq(d);
304 u32 val;
305
306 guard(gpio_generic_lock_irqsave)(gen_gc);
307
308 val = dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq);
309 dwapb_write(gpio, GPIO_INTEN, val);
310 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
311 dwapb_write(gpio, GPIO_INTMASK, val);
312 }
313
dwapb_irq_disable(struct irq_data * d)314 static void dwapb_irq_disable(struct irq_data *d)
315 {
316 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
317 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
318 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
319 irq_hw_number_t hwirq = irqd_to_hwirq(d);
320 u32 val;
321
322 guard(gpio_generic_lock_irqsave)(gen_gc);
323
324 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
325 dwapb_write(gpio, GPIO_INTMASK, val);
326 val = dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq);
327 dwapb_write(gpio, GPIO_INTEN, val);
328 }
329
dwapb_irq_set_type(struct irq_data * d,u32 type)330 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
331 {
332 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
333 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
334 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
335 irq_hw_number_t bit = irqd_to_hwirq(d);
336 unsigned long level, polarity;
337
338 guard(gpio_generic_lock_irqsave)(gen_gc);
339
340 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
341 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
342
343 switch (type) {
344 case IRQ_TYPE_EDGE_BOTH:
345 level |= BIT(bit);
346 dwapb_toggle_trigger(gpio, bit);
347 break;
348 case IRQ_TYPE_EDGE_RISING:
349 level |= BIT(bit);
350 polarity |= BIT(bit);
351 break;
352 case IRQ_TYPE_EDGE_FALLING:
353 level |= BIT(bit);
354 polarity &= ~BIT(bit);
355 break;
356 case IRQ_TYPE_LEVEL_HIGH:
357 level &= ~BIT(bit);
358 polarity |= BIT(bit);
359 break;
360 case IRQ_TYPE_LEVEL_LOW:
361 level &= ~BIT(bit);
362 polarity &= ~BIT(bit);
363 break;
364 }
365
366 if (type & IRQ_TYPE_LEVEL_MASK)
367 irq_set_handler_locked(d, handle_level_irq);
368 else if (type & IRQ_TYPE_EDGE_BOTH)
369 irq_set_handler_locked(d, handle_edge_irq);
370
371 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
372 if (type != IRQ_TYPE_EDGE_BOTH)
373 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
374
375 return 0;
376 }
377
dwapb_irq_set_wake(struct irq_data * d,unsigned int enable)378 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
379 {
380 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
381 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
382 struct dwapb_context *ctx = gpio->ports[0].ctx;
383 irq_hw_number_t bit = irqd_to_hwirq(d);
384 u32 wake_en = ctx->wake_en;
385
386 if (enable)
387 wake_en |= BIT(bit);
388 else
389 wake_en &= ~BIT(bit);
390
391 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
392 if (d->parent_data && !!ctx->wake_en != !!wake_en) {
393 int err;
394
395 err = irq_chip_set_wake_parent(d, enable);
396 if (err)
397 return err;
398 }
399 #endif
400
401 ctx->wake_en = wake_en;
402
403 return 0;
404 }
405
406 static const struct irq_chip dwapb_irq_chip = {
407 .name = DWAPB_DRIVER_NAME,
408 .irq_ack = dwapb_irq_ack,
409 .irq_mask = dwapb_irq_mask,
410 .irq_unmask = dwapb_irq_unmask,
411 .irq_set_type = dwapb_irq_set_type,
412 .irq_enable = dwapb_irq_enable,
413 .irq_disable = dwapb_irq_disable,
414 .irq_set_wake = pm_sleep_ptr(dwapb_irq_set_wake),
415 .flags = IRQCHIP_IMMUTABLE,
416 GPIOCHIP_IRQ_RESOURCE_HELPERS,
417 };
418
dwapb_gpio_set_debounce(struct gpio_chip * gc,unsigned offset,unsigned debounce)419 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
420 unsigned offset, unsigned debounce)
421 {
422 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
423 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
424 struct dwapb_gpio *gpio = port->gpio;
425 unsigned long val_deb;
426 unsigned long mask = BIT(offset);
427
428 guard(gpio_generic_lock_irqsave)(gen_gc);
429
430 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
431 if (debounce)
432 val_deb |= mask;
433 else
434 val_deb &= ~mask;
435 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
436
437 return 0;
438 }
439
dwapb_gpio_set_config(struct gpio_chip * gc,unsigned offset,unsigned long config)440 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
441 unsigned long config)
442 {
443 u32 debounce;
444
445 if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) {
446 debounce = pinconf_to_config_argument(config);
447 return dwapb_gpio_set_debounce(gc, offset, debounce);
448 }
449
450 return gpiochip_generic_config(gc, offset, config);
451 }
452
dwapb_convert_irqs(struct dwapb_gpio_port_irqchip * pirq,struct dwapb_port_property * pp)453 static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
454 struct dwapb_port_property *pp)
455 {
456 int i;
457
458 /* Group all available IRQs into an array of parental IRQs. */
459 for (i = 0; i < pp->ngpio; ++i) {
460 if (!pp->irq[i])
461 continue;
462
463 pirq->irq[pirq->nr_irqs++] = pp->irq[i];
464 }
465
466 return pirq->nr_irqs ? 0 : -ENOENT;
467 }
468
dwapb_configure_irqs(struct dwapb_gpio * gpio,struct dwapb_gpio_port * port,struct dwapb_port_property * pp)469 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
470 struct dwapb_gpio_port *port,
471 struct dwapb_port_property *pp)
472 {
473 struct dwapb_gpio_port_irqchip *pirq;
474 struct gpio_chip *gc = &port->chip.gc;
475 struct gpio_irq_chip *girq;
476 int err;
477
478 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
479 if (!pirq)
480 return;
481
482 if (dwapb_convert_irqs(pirq, pp)) {
483 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
484 goto err_kfree_pirq;
485 }
486
487 girq = &gc->irq;
488 girq->handler = handle_bad_irq;
489 girq->default_type = IRQ_TYPE_NONE;
490 girq->init_hw = dwapb_irq_init_hw;
491
492 port->pirq = pirq;
493
494 /*
495 * Intel ACPI-based platforms mostly have the DesignWare APB GPIO
496 * IRQ lane shared between several devices. In that case the parental
497 * IRQ has to be handled in the shared way so to be properly delivered
498 * to all the connected devices.
499 */
500 if (has_acpi_companion(gpio->dev)) {
501 girq->num_parents = 0;
502 girq->parents = NULL;
503 girq->parent_handler = NULL;
504
505 err = devm_request_irq(gpio->dev, pp->irq[0],
506 dwapb_irq_handler_mfd,
507 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
508 if (err) {
509 dev_err(gpio->dev, "error requesting IRQ\n");
510 goto err_kfree_pirq;
511 }
512 } else {
513 girq->num_parents = pirq->nr_irqs;
514 girq->parents = pirq->irq;
515 girq->parent_handler_data = gpio;
516 girq->parent_handler = dwapb_irq_handler;
517 }
518
519 gpio_irq_chip_set_chip(girq, &dwapb_irq_chip);
520
521 return;
522
523 err_kfree_pirq:
524 devm_kfree(gpio->dev, pirq);
525 }
526
dwapb_gpio_add_port(struct dwapb_gpio * gpio,struct dwapb_port_property * pp,unsigned int offs)527 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
528 struct dwapb_port_property *pp,
529 unsigned int offs)
530 {
531 struct gpio_generic_chip_config config;
532 struct dwapb_gpio_port *port;
533 void __iomem *dat, *set, *dirout;
534 int err;
535
536 port = &gpio->ports[offs];
537 port->gpio = gpio;
538 port->idx = pp->idx;
539
540 #ifdef CONFIG_PM_SLEEP
541 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
542 if (!port->ctx)
543 return -ENOMEM;
544 #endif
545
546 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
547 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
548 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
549
550 config = (struct gpio_generic_chip_config) {
551 .dev = gpio->dev,
552 .sz = 4,
553 .dat = dat,
554 .set = set,
555 .dirout = dirout,
556 };
557
558 /* This registers 32 GPIO lines per port */
559 err = gpio_generic_chip_init(&port->chip, &config);
560 if (err) {
561 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
562 port->idx);
563 return err;
564 }
565
566 port->chip.gc.fwnode = pp->fwnode;
567 port->chip.gc.ngpio = pp->ngpio;
568 port->chip.gc.base = pp->gpio_base;
569 port->chip.gc.request = gpiochip_generic_request;
570 port->chip.gc.free = gpiochip_generic_free;
571
572 /* Only port A support debounce */
573 if (pp->idx == 0)
574 port->chip.gc.set_config = dwapb_gpio_set_config;
575 else
576 port->chip.gc.set_config = gpiochip_generic_config;
577
578 /* Only port A can provide interrupts in all configurations of the IP */
579 if (pp->idx == 0)
580 dwapb_configure_irqs(gpio, port, pp);
581
582 err = devm_gpiochip_add_data(gpio->dev, &port->chip.gc, port);
583 if (err) {
584 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
585 port->idx);
586 return err;
587 }
588
589 return 0;
590 }
591
dwapb_get_irq(struct device * dev,struct fwnode_handle * fwnode,struct dwapb_port_property * pp)592 static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
593 struct dwapb_port_property *pp)
594 {
595 int irq, j;
596
597 for (j = 0; j < pp->ngpio; j++) {
598 if (has_acpi_companion(dev))
599 irq = platform_get_irq_optional(to_platform_device(dev), j);
600 else
601 irq = fwnode_irq_get(fwnode, j);
602 if (irq > 0)
603 pp->irq[j] = irq;
604 }
605 }
606
dwapb_gpio_get_pdata(struct device * dev)607 static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
608 {
609 struct dwapb_platform_data *pdata;
610 struct dwapb_port_property *pp;
611 int nports;
612 int i;
613
614 nports = device_get_child_node_count(dev);
615 if (nports == 0)
616 return ERR_PTR(-ENODEV);
617
618 pdata = devm_kzalloc(dev, struct_size(pdata, properties, nports), GFP_KERNEL);
619 if (!pdata)
620 return ERR_PTR(-ENOMEM);
621
622 pdata->nports = nports;
623
624 i = 0;
625 device_for_each_child_node_scoped(dev, fwnode) {
626 pp = &pdata->properties[i++];
627 pp->fwnode = fwnode;
628
629 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
630 pp->idx >= DWAPB_MAX_PORTS) {
631 dev_err(dev,
632 "missing/invalid port index for port%d\n", i);
633 return ERR_PTR(-EINVAL);
634 }
635
636 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
637 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
638 dev_info(dev,
639 "failed to get number of gpios for port%d\n",
640 i);
641 pp->ngpio = DWAPB_MAX_GPIOS;
642 }
643
644 pp->gpio_base = -1;
645
646 /* For internal use only, new platforms mustn't exercise this */
647 if (is_software_node(fwnode))
648 fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base);
649
650 /*
651 * Only port A can provide interrupts in all configurations of
652 * the IP.
653 */
654 if (pp->idx == 0)
655 dwapb_get_irq(dev, fwnode, pp);
656 }
657
658 return pdata;
659 }
660
dwapb_assert_reset(void * data)661 static void dwapb_assert_reset(void *data)
662 {
663 struct dwapb_gpio *gpio = data;
664
665 reset_control_assert(gpio->rst);
666 }
667
dwapb_get_reset(struct dwapb_gpio * gpio)668 static int dwapb_get_reset(struct dwapb_gpio *gpio)
669 {
670 int err;
671
672 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
673 if (IS_ERR(gpio->rst))
674 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),
675 "Cannot get reset descriptor\n");
676
677 err = reset_control_deassert(gpio->rst);
678 if (err) {
679 dev_err(gpio->dev, "Cannot deassert reset lane\n");
680 return err;
681 }
682
683 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
684 }
685
dwapb_disable_clks(void * data)686 static void dwapb_disable_clks(void *data)
687 {
688 struct dwapb_gpio *gpio = data;
689
690 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
691 }
692
dwapb_get_clks(struct dwapb_gpio * gpio)693 static int dwapb_get_clks(struct dwapb_gpio *gpio)
694 {
695 int err;
696
697 /* Optional bus and debounce clocks */
698 gpio->clks[0].id = "bus";
699 gpio->clks[1].id = "db";
700 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
701 gpio->clks);
702 if (err)
703 return dev_err_probe(gpio->dev, err,
704 "Cannot get APB/Debounce clocks\n");
705
706 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
707 if (err) {
708 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
709 return err;
710 }
711
712 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
713 }
714
715 static const struct of_device_id dwapb_of_match[] = {
716 { .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1},
717 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
718 { /* Sentinel */ }
719 };
720 MODULE_DEVICE_TABLE(of, dwapb_of_match);
721
722 static const struct acpi_device_id dwapb_acpi_match[] = {
723 {"HISI0181", GPIO_REG_OFFSET_V1},
724 {"APMC0D07", GPIO_REG_OFFSET_V1},
725 {"APMC0D81", GPIO_REG_OFFSET_V2},
726 {"FUJI200A", GPIO_REG_OFFSET_V1},
727 {"LECA0001", GPIO_REG_OFFSET_V1},
728 { }
729 };
730 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
731
dwapb_gpio_probe(struct platform_device * pdev)732 static int dwapb_gpio_probe(struct platform_device *pdev)
733 {
734 unsigned int i;
735 struct dwapb_gpio *gpio;
736 int err;
737 struct dwapb_platform_data *pdata;
738 struct device *dev = &pdev->dev;
739
740 pdata = dwapb_gpio_get_pdata(dev);
741 if (IS_ERR(pdata))
742 return PTR_ERR(pdata);
743
744 gpio = devm_kzalloc(&pdev->dev, struct_size(gpio, ports, pdata->nports), GFP_KERNEL);
745 if (!gpio)
746 return -ENOMEM;
747
748 gpio->nr_ports = pdata->nports;
749 gpio->dev = &pdev->dev;
750
751 err = dwapb_get_reset(gpio);
752 if (err)
753 return err;
754
755 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
756 if (IS_ERR(gpio->regs))
757 return PTR_ERR(gpio->regs);
758
759 err = dwapb_get_clks(gpio);
760 if (err)
761 return err;
762
763 gpio->flags = (uintptr_t)device_get_match_data(dev);
764
765 for (i = 0; i < gpio->nr_ports; i++) {
766 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
767 if (err)
768 return err;
769 }
770
771 platform_set_drvdata(pdev, gpio);
772
773 return 0;
774 }
775
dwapb_gpio_suspend(struct device * dev)776 static int dwapb_gpio_suspend(struct device *dev)
777 {
778 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
779 struct gpio_generic_chip *gen_gc = &gpio->ports[0].chip;
780 int i;
781
782 scoped_guard(gpio_generic_lock_irqsave, gen_gc) {
783 gpio->clocks_on_for_wake = false;
784
785 for (i = 0; i < gpio->nr_ports; i++) {
786 unsigned int offset;
787 unsigned int idx = gpio->ports[i].idx;
788 struct dwapb_context *ctx = gpio->ports[i].ctx;
789
790 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
791 ctx->dir = dwapb_read(gpio, offset);
792
793 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
794 ctx->data = dwapb_read(gpio, offset);
795
796 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
797 ctx->ext = dwapb_read(gpio, offset);
798
799 /* Only port A can provide interrupts */
800 if (idx == 0) {
801 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
802 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
803 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
804 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
805 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
806 }
807 }
808 }
809
810 return 0;
811 }
812
dwapb_gpio_suspend_noirq(struct device * dev)813 static int dwapb_gpio_suspend_noirq(struct device *dev)
814 {
815 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
816 struct gpio_generic_chip *gen_gc = &gpio->ports[0].chip;
817 bool wake_enabled = false;
818 int i;
819
820 scoped_guard(gpio_generic_lock_irqsave, gen_gc) {
821 for (i = 0; i < gpio->nr_ports; i++) {
822 unsigned int idx = gpio->ports[i].idx;
823 struct dwapb_context *ctx = gpio->ports[i].ctx;
824
825 if (idx == 0) {
826 wake_enabled = ctx->wake_en;
827 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
828 break;
829 }
830 }
831
832 gpio->clocks_on_for_wake = wake_enabled;
833 }
834
835 if (wake_enabled) {
836 device_set_wakeup_path(dev);
837 return 0;
838 }
839
840 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
841
842 return 0;
843 }
844
dwapb_gpio_resume_noirq(struct device * dev)845 static int dwapb_gpio_resume_noirq(struct device *dev)
846 {
847 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
848 int err;
849
850 if (gpio->clocks_on_for_wake)
851 return 0;
852
853 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
854 if (err)
855 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
856
857 return err;
858 }
859
dwapb_gpio_resume(struct device * dev)860 static int dwapb_gpio_resume(struct device *dev)
861 {
862 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
863 struct gpio_chip *gc = &gpio->ports[0].chip.gc;
864 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
865 int i;
866
867 guard(gpio_generic_lock_irqsave)(gen_gc);
868
869 for (i = 0; i < gpio->nr_ports; i++) {
870 unsigned int offset;
871 unsigned int idx = gpio->ports[i].idx;
872 struct dwapb_context *ctx = gpio->ports[i].ctx;
873
874 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
875 dwapb_write(gpio, offset, ctx->data);
876
877 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
878 dwapb_write(gpio, offset, ctx->dir);
879
880 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
881 dwapb_write(gpio, offset, ctx->ext);
882
883 /* Only port A can provide interrupts */
884 if (idx == 0) {
885 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
886 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
887 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
888 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
889 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
890
891 /* Clear out spurious interrupts */
892 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
893 }
894 }
895
896 return 0;
897 }
898
899 static const struct dev_pm_ops dwapb_gpio_pm_ops = {
900 SYSTEM_SLEEP_PM_OPS(dwapb_gpio_suspend, dwapb_gpio_resume)
901 NOIRQ_SYSTEM_SLEEP_PM_OPS(dwapb_gpio_suspend_noirq,
902 dwapb_gpio_resume_noirq)
903 };
904
905 static struct platform_driver dwapb_gpio_driver = {
906 .driver = {
907 .name = DWAPB_DRIVER_NAME,
908 .pm = pm_sleep_ptr(&dwapb_gpio_pm_ops),
909 .of_match_table = dwapb_of_match,
910 .acpi_match_table = dwapb_acpi_match,
911 },
912 .probe = dwapb_gpio_probe,
913 };
914
915 module_platform_driver(dwapb_gpio_driver);
916
917 MODULE_LICENSE("GPL");
918 MODULE_AUTHOR("Jamie Iles");
919 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
920 MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);
921