1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>
9 */
10
11 #include <linux/align.h>
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dma/edma.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/ioport.h>
18 #include <linux/of.h>
19 #include <linux/of_address.h>
20 #include <linux/pcie-dwc.h>
21 #include <linux/platform_device.h>
22 #include <linux/sizes.h>
23 #include <linux/types.h>
24
25 #include "../../pci.h"
26 #include "pcie-designware.h"
27
28 static const char * const dw_pcie_app_clks[DW_PCIE_NUM_APP_CLKS] = {
29 [DW_PCIE_DBI_CLK] = "dbi",
30 [DW_PCIE_MSTR_CLK] = "mstr",
31 [DW_PCIE_SLV_CLK] = "slv",
32 };
33
34 static const char * const dw_pcie_core_clks[DW_PCIE_NUM_CORE_CLKS] = {
35 [DW_PCIE_PIPE_CLK] = "pipe",
36 [DW_PCIE_CORE_CLK] = "core",
37 [DW_PCIE_AUX_CLK] = "aux",
38 [DW_PCIE_REF_CLK] = "ref",
39 };
40
41 static const char * const dw_pcie_app_rsts[DW_PCIE_NUM_APP_RSTS] = {
42 [DW_PCIE_DBI_RST] = "dbi",
43 [DW_PCIE_MSTR_RST] = "mstr",
44 [DW_PCIE_SLV_RST] = "slv",
45 };
46
47 static const char * const dw_pcie_core_rsts[DW_PCIE_NUM_CORE_RSTS] = {
48 [DW_PCIE_NON_STICKY_RST] = "non-sticky",
49 [DW_PCIE_STICKY_RST] = "sticky",
50 [DW_PCIE_CORE_RST] = "core",
51 [DW_PCIE_PIPE_RST] = "pipe",
52 [DW_PCIE_PHY_RST] = "phy",
53 [DW_PCIE_HOT_RST] = "hot",
54 [DW_PCIE_PWR_RST] = "pwr",
55 };
56
57 static const struct dwc_pcie_vsec_id dwc_pcie_ptm_vsec_ids[] = {
58 { .vendor_id = PCI_VENDOR_ID_QCOM, /* EP */
59 .vsec_id = 0x03, .vsec_rev = 0x1 },
60 { .vendor_id = PCI_VENDOR_ID_QCOM, /* RC */
61 .vsec_id = 0x04, .vsec_rev = 0x1 },
62 { }
63 };
64
dw_pcie_get_clocks(struct dw_pcie * pci)65 static int dw_pcie_get_clocks(struct dw_pcie *pci)
66 {
67 int i, ret;
68
69 for (i = 0; i < DW_PCIE_NUM_APP_CLKS; i++)
70 pci->app_clks[i].id = dw_pcie_app_clks[i];
71
72 for (i = 0; i < DW_PCIE_NUM_CORE_CLKS; i++)
73 pci->core_clks[i].id = dw_pcie_core_clks[i];
74
75 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS,
76 pci->app_clks);
77 if (ret)
78 return ret;
79
80 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS,
81 pci->core_clks);
82 }
83
dw_pcie_get_resets(struct dw_pcie * pci)84 static int dw_pcie_get_resets(struct dw_pcie *pci)
85 {
86 int i, ret;
87
88 for (i = 0; i < DW_PCIE_NUM_APP_RSTS; i++)
89 pci->app_rsts[i].id = dw_pcie_app_rsts[i];
90
91 for (i = 0; i < DW_PCIE_NUM_CORE_RSTS; i++)
92 pci->core_rsts[i].id = dw_pcie_core_rsts[i];
93
94 ret = devm_reset_control_bulk_get_optional_shared(pci->dev,
95 DW_PCIE_NUM_APP_RSTS,
96 pci->app_rsts);
97 if (ret)
98 return ret;
99
100 ret = devm_reset_control_bulk_get_optional_exclusive(pci->dev,
101 DW_PCIE_NUM_CORE_RSTS,
102 pci->core_rsts);
103 if (ret)
104 return ret;
105
106 pci->pe_rst = devm_gpiod_get_optional(pci->dev, "reset", GPIOD_OUT_HIGH);
107 if (IS_ERR(pci->pe_rst))
108 return PTR_ERR(pci->pe_rst);
109
110 return 0;
111 }
112
dw_pcie_get_resources(struct dw_pcie * pci)113 int dw_pcie_get_resources(struct dw_pcie *pci)
114 {
115 struct platform_device *pdev = to_platform_device(pci->dev);
116 struct device_node *np = dev_of_node(pci->dev);
117 struct resource *res;
118 int ret;
119
120 if (!pci->dbi_base) {
121 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
122 pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res);
123 if (IS_ERR(pci->dbi_base))
124 return PTR_ERR(pci->dbi_base);
125 pci->dbi_phys_addr = res->start;
126 }
127
128 /* DBI2 is mainly useful for the endpoint controller */
129 if (!pci->dbi_base2) {
130 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
131 if (res) {
132 pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res);
133 if (IS_ERR(pci->dbi_base2))
134 return PTR_ERR(pci->dbi_base2);
135 } else {
136 pci->dbi_base2 = pci->dbi_base + SZ_4K;
137 }
138 }
139
140 /* For non-unrolled iATU/eDMA platforms this range will be ignored */
141 if (!pci->atu_base) {
142 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
143 if (res) {
144 pci->atu_size = resource_size(res);
145 pci->atu_base = devm_ioremap_resource(pci->dev, res);
146 if (IS_ERR(pci->atu_base))
147 return PTR_ERR(pci->atu_base);
148 pci->atu_phys_addr = res->start;
149 } else {
150 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
151 }
152 }
153
154 /* Set a default value suitable for at most 8 in and 8 out windows */
155 if (!pci->atu_size)
156 pci->atu_size = SZ_4K;
157
158 /* eDMA region can be mapped to a custom base address */
159 if (!pci->edma.reg_base) {
160 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
161 if (res) {
162 pci->edma.reg_base = devm_ioremap_resource(pci->dev, res);
163 if (IS_ERR(pci->edma.reg_base))
164 return PTR_ERR(pci->edma.reg_base);
165 } else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) {
166 pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET;
167 }
168 }
169
170 /* ELBI is an optional resource */
171 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
172 if (res) {
173 pci->elbi_base = devm_ioremap_resource(pci->dev, res);
174 if (IS_ERR(pci->elbi_base))
175 return PTR_ERR(pci->elbi_base);
176 }
177
178 /* LLDD is supposed to manually switch the clocks and resets state */
179 if (dw_pcie_cap_is(pci, REQ_RES)) {
180 ret = dw_pcie_get_clocks(pci);
181 if (ret)
182 return ret;
183
184 ret = dw_pcie_get_resets(pci);
185 if (ret)
186 return ret;
187 }
188
189 if (pci->max_link_speed < 1)
190 pci->max_link_speed = of_pci_get_max_link_speed(np);
191
192 of_property_read_u32(np, "num-lanes", &pci->num_lanes);
193
194 if (of_property_read_bool(np, "snps,enable-cdm-check"))
195 dw_pcie_cap_set(pci, CDM_CHECK);
196
197 return 0;
198 }
199
dw_pcie_version_detect(struct dw_pcie * pci)200 void dw_pcie_version_detect(struct dw_pcie *pci)
201 {
202 u32 ver;
203
204 /* The content of the CSR is zero on DWC PCIe older than v4.70a */
205 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_NUMBER);
206 if (!ver)
207 return;
208
209 if (pci->version && pci->version != ver)
210 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n",
211 pci->version, ver);
212 else
213 pci->version = ver;
214
215 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_TYPE);
216
217 if (pci->type && pci->type != ver)
218 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n",
219 pci->type, ver);
220 else
221 pci->type = ver;
222 }
223
dw_pcie_find_capability(struct dw_pcie * pci,u8 cap)224 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
225 {
226 return PCI_FIND_NEXT_CAP(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap,
227 pci);
228 }
229 EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
230
dw_pcie_find_ext_capability(struct dw_pcie * pci,u8 cap)231 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
232 {
233 return PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, 0, cap, pci);
234 }
235 EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
236
__dw_pcie_find_vsec_capability(struct dw_pcie * pci,u16 vendor_id,u16 vsec_id)237 static u16 __dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id,
238 u16 vsec_id)
239 {
240 u16 vsec = 0;
241 u32 header;
242
243 if (vendor_id != dw_pcie_readw_dbi(pci, PCI_VENDOR_ID))
244 return 0;
245
246 while ((vsec = PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, vsec,
247 PCI_EXT_CAP_ID_VNDR, pci))) {
248 header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER);
249 if (PCI_VNDR_HEADER_ID(header) == vsec_id)
250 return vsec;
251 }
252
253 return 0;
254 }
255
dw_pcie_find_vsec_capability(struct dw_pcie * pci,const struct dwc_pcie_vsec_id * vsec_ids)256 static u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci,
257 const struct dwc_pcie_vsec_id *vsec_ids)
258 {
259 const struct dwc_pcie_vsec_id *vid;
260 u16 vsec;
261 u32 header;
262
263 for (vid = vsec_ids; vid->vendor_id; vid++) {
264 vsec = __dw_pcie_find_vsec_capability(pci, vid->vendor_id,
265 vid->vsec_id);
266 if (vsec) {
267 header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER);
268 if (PCI_VNDR_HEADER_REV(header) == vid->vsec_rev)
269 return vsec;
270 }
271 }
272
273 return 0;
274 }
275
dw_pcie_find_rasdes_capability(struct dw_pcie * pci)276 u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci)
277 {
278 return dw_pcie_find_vsec_capability(pci, dwc_pcie_rasdes_vsec_ids);
279 }
280 EXPORT_SYMBOL_GPL(dw_pcie_find_rasdes_capability);
281
dw_pcie_find_ptm_capability(struct dw_pcie * pci)282 u16 dw_pcie_find_ptm_capability(struct dw_pcie *pci)
283 {
284 return dw_pcie_find_vsec_capability(pci, dwc_pcie_ptm_vsec_ids);
285 }
286 EXPORT_SYMBOL_GPL(dw_pcie_find_ptm_capability);
287
dw_pcie_read(void __iomem * addr,int size,u32 * val)288 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
289 {
290 if (!IS_ALIGNED((uintptr_t)addr, size)) {
291 *val = 0;
292 return PCIBIOS_BAD_REGISTER_NUMBER;
293 }
294
295 if (size == 4) {
296 *val = readl(addr);
297 } else if (size == 2) {
298 *val = readw(addr);
299 } else if (size == 1) {
300 *val = readb(addr);
301 } else {
302 *val = 0;
303 return PCIBIOS_BAD_REGISTER_NUMBER;
304 }
305
306 return PCIBIOS_SUCCESSFUL;
307 }
308 EXPORT_SYMBOL_GPL(dw_pcie_read);
309
dw_pcie_write(void __iomem * addr,int size,u32 val)310 int dw_pcie_write(void __iomem *addr, int size, u32 val)
311 {
312 if (!IS_ALIGNED((uintptr_t)addr, size))
313 return PCIBIOS_BAD_REGISTER_NUMBER;
314
315 if (size == 4)
316 writel(val, addr);
317 else if (size == 2)
318 writew(val, addr);
319 else if (size == 1)
320 writeb(val, addr);
321 else
322 return PCIBIOS_BAD_REGISTER_NUMBER;
323
324 return PCIBIOS_SUCCESSFUL;
325 }
326 EXPORT_SYMBOL_GPL(dw_pcie_write);
327
dw_pcie_read_dbi(struct dw_pcie * pci,u32 reg,size_t size)328 u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size)
329 {
330 int ret;
331 u32 val;
332
333 if (pci->ops && pci->ops->read_dbi)
334 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size);
335
336 ret = dw_pcie_read(pci->dbi_base + reg, size, &val);
337 if (ret)
338 dev_err(pci->dev, "Read DBI address failed\n");
339
340 return val;
341 }
342 EXPORT_SYMBOL_GPL(dw_pcie_read_dbi);
343
dw_pcie_write_dbi(struct dw_pcie * pci,u32 reg,size_t size,u32 val)344 void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
345 {
346 int ret;
347
348 if (pci->ops && pci->ops->write_dbi) {
349 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val);
350 return;
351 }
352
353 ret = dw_pcie_write(pci->dbi_base + reg, size, val);
354 if (ret)
355 dev_err(pci->dev, "Write DBI address failed\n");
356 }
357 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi);
358
dw_pcie_write_dbi2(struct dw_pcie * pci,u32 reg,size_t size,u32 val)359 void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
360 {
361 int ret;
362
363 if (pci->ops && pci->ops->write_dbi2) {
364 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val);
365 return;
366 }
367
368 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
369 if (ret)
370 dev_err(pci->dev, "write DBI address failed\n");
371 }
372 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi2);
373
dw_pcie_select_atu(struct dw_pcie * pci,u32 dir,u32 index)374 static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir,
375 u32 index)
376 {
377 if (dw_pcie_cap_is(pci, IATU_UNROLL))
378 return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index);
379
380 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, dir | index);
381 return pci->atu_base;
382 }
383
dw_pcie_readl_atu(struct dw_pcie * pci,u32 dir,u32 index,u32 reg)384 static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 dir, u32 index, u32 reg)
385 {
386 void __iomem *base;
387 int ret;
388 u32 val;
389
390 base = dw_pcie_select_atu(pci, dir, index);
391
392 if (pci->ops && pci->ops->read_dbi)
393 return pci->ops->read_dbi(pci, base, reg, 4);
394
395 ret = dw_pcie_read(base + reg, 4, &val);
396 if (ret)
397 dev_err(pci->dev, "Read ATU address failed\n");
398
399 return val;
400 }
401
dw_pcie_writel_atu(struct dw_pcie * pci,u32 dir,u32 index,u32 reg,u32 val)402 static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 dir, u32 index,
403 u32 reg, u32 val)
404 {
405 void __iomem *base;
406 int ret;
407
408 base = dw_pcie_select_atu(pci, dir, index);
409
410 if (pci->ops && pci->ops->write_dbi) {
411 pci->ops->write_dbi(pci, base, reg, 4, val);
412 return;
413 }
414
415 ret = dw_pcie_write(base + reg, 4, val);
416 if (ret)
417 dev_err(pci->dev, "Write ATU address failed\n");
418 }
419
dw_pcie_readl_atu_ob(struct dw_pcie * pci,u32 index,u32 reg)420 static inline u32 dw_pcie_readl_atu_ob(struct dw_pcie *pci, u32 index, u32 reg)
421 {
422 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg);
423 }
424
dw_pcie_writel_atu_ob(struct dw_pcie * pci,u32 index,u32 reg,u32 val)425 static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg,
426 u32 val)
427 {
428 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg, val);
429 }
430
dw_pcie_enable_ecrc(u32 val)431 static inline u32 dw_pcie_enable_ecrc(u32 val)
432 {
433 /*
434 * DesignWare core version 4.90A has a design issue where the 'TD'
435 * bit in the Control register-1 of the ATU outbound region acts
436 * like an override for the ECRC setting, i.e., the presence of TLP
437 * Digest (ECRC) in the outgoing TLPs is solely determined by this
438 * bit. This is contrary to the PCIe spec which says that the
439 * enablement of the ECRC is solely determined by the AER
440 * registers.
441 *
442 * Because of this, even when the ECRC is enabled through AER
443 * registers, the transactions going through ATU won't have TLP
444 * Digest as there is no way the PCI core AER code could program
445 * the TD bit which is specific to the DesignWare core.
446 *
447 * The best way to handle this scenario is to program the TD bit
448 * always. It affects only the traffic from root port to downstream
449 * devices.
450 *
451 * At this point,
452 * When ECRC is enabled in AER registers, everything works normally
453 * When ECRC is NOT enabled in AER registers, then,
454 * on Root Port:- TLP Digest (DWord size) gets appended to each packet
455 * even through it is not required. Since downstream
456 * TLPs are mostly for configuration accesses and BAR
457 * accesses, they are not in critical path and won't
458 * have much negative effect on the performance.
459 * on End Point:- TLP Digest is received for some/all the packets coming
460 * from the root port. TLP Digest is ignored because,
461 * as per the PCIe Spec r5.0 v1.0 section 2.2.3
462 * "TLP Digest Rules", when an endpoint receives TLP
463 * Digest when its ECRC check functionality is disabled
464 * in AER registers, received TLP Digest is just ignored.
465 * Since there is no issue or error reported either side, best way to
466 * handle the scenario is to program TD bit by default.
467 */
468
469 return val | PCIE_ATU_TD;
470 }
471
dw_pcie_prog_outbound_atu(struct dw_pcie * pci,const struct dw_pcie_ob_atu_cfg * atu)472 int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
473 const struct dw_pcie_ob_atu_cfg *atu)
474 {
475 u64 parent_bus_addr = atu->parent_bus_addr;
476 u32 retries, val;
477 u64 limit_addr;
478
479 limit_addr = parent_bus_addr + atu->size - 1;
480
481 if ((limit_addr & ~pci->region_limit) != (parent_bus_addr & ~pci->region_limit) ||
482 !IS_ALIGNED(parent_bus_addr, pci->region_align) ||
483 !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
484 return -EINVAL;
485 }
486
487 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
488 lower_32_bits(parent_bus_addr));
489 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE,
490 upper_32_bits(parent_bus_addr));
491
492 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT,
493 lower_32_bits(limit_addr));
494 if (dw_pcie_ver_is_ge(pci, 460A))
495 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT,
496 upper_32_bits(limit_addr));
497
498 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET,
499 lower_32_bits(atu->pci_addr));
500 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
501 upper_32_bits(atu->pci_addr));
502
503 val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
504 if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) &&
505 dw_pcie_ver_is_ge(pci, 460A))
506 val |= PCIE_ATU_INCREASE_REGION_SIZE;
507 if (dw_pcie_ver_is(pci, 490A))
508 val = dw_pcie_enable_ecrc(val);
509 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
510
511 val = PCIE_ATU_ENABLE | atu->ctrl2;
512 if (atu->type == PCIE_ATU_TYPE_MSG) {
513 /* The data-less messages only for now */
514 val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
515 }
516 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
517
518 /*
519 * Make sure ATU enable takes effect before any subsequent config
520 * and I/O accesses.
521 */
522 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
523 val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2);
524 if (val & PCIE_ATU_ENABLE)
525 return 0;
526
527 mdelay(LINK_WAIT_IATU);
528 }
529
530 dev_err(pci->dev, "Outbound iATU is not being enabled\n");
531
532 return -ETIMEDOUT;
533 }
534
dw_pcie_readl_atu_ib(struct dw_pcie * pci,u32 index,u32 reg)535 static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg)
536 {
537 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg);
538 }
539
dw_pcie_writel_atu_ib(struct dw_pcie * pci,u32 index,u32 reg,u32 val)540 static inline void dw_pcie_writel_atu_ib(struct dw_pcie *pci, u32 index, u32 reg,
541 u32 val)
542 {
543 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg, val);
544 }
545
dw_pcie_prog_inbound_atu(struct dw_pcie * pci,int index,int type,u64 parent_bus_addr,u64 pci_addr,u64 size)546 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
547 u64 parent_bus_addr, u64 pci_addr, u64 size)
548 {
549 u64 limit_addr = pci_addr + size - 1;
550 u32 retries, val;
551
552 if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) ||
553 !IS_ALIGNED(parent_bus_addr, pci->region_align) ||
554 !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
555 return -EINVAL;
556 }
557
558 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_BASE,
559 lower_32_bits(pci_addr));
560 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_BASE,
561 upper_32_bits(pci_addr));
562
563 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LIMIT,
564 lower_32_bits(limit_addr));
565 if (dw_pcie_ver_is_ge(pci, 460A))
566 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_LIMIT,
567 upper_32_bits(limit_addr));
568
569 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET,
570 lower_32_bits(parent_bus_addr));
571 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET,
572 upper_32_bits(parent_bus_addr));
573
574 val = type;
575 if (upper_32_bits(limit_addr) > upper_32_bits(pci_addr) &&
576 dw_pcie_ver_is_ge(pci, 460A))
577 val |= PCIE_ATU_INCREASE_REGION_SIZE;
578 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, val);
579 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
580
581 /*
582 * Make sure ATU enable takes effect before any subsequent config
583 * and I/O accesses.
584 */
585 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
586 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2);
587 if (val & PCIE_ATU_ENABLE)
588 return 0;
589
590 mdelay(LINK_WAIT_IATU);
591 }
592
593 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
594
595 return -ETIMEDOUT;
596 }
597
dw_pcie_prog_ep_inbound_atu(struct dw_pcie * pci,u8 func_no,int index,int type,u64 parent_bus_addr,u8 bar,size_t size)598 int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
599 int type, u64 parent_bus_addr, u8 bar, size_t size)
600 {
601 u32 retries, val;
602
603 if (!IS_ALIGNED(parent_bus_addr, pci->region_align) ||
604 !IS_ALIGNED(parent_bus_addr, size))
605 return -EINVAL;
606
607 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET,
608 lower_32_bits(parent_bus_addr));
609 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET,
610 upper_32_bits(parent_bus_addr));
611
612 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, type |
613 PCIE_ATU_FUNC_NUM(func_no));
614 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2,
615 PCIE_ATU_ENABLE | PCIE_ATU_FUNC_NUM_MATCH_EN |
616 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
617
618 /*
619 * Make sure ATU enable takes effect before any subsequent config
620 * and I/O accesses.
621 */
622 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
623 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2);
624 if (val & PCIE_ATU_ENABLE)
625 return 0;
626
627 mdelay(LINK_WAIT_IATU);
628 }
629
630 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
631
632 return -ETIMEDOUT;
633 }
634
dw_pcie_disable_atu(struct dw_pcie * pci,u32 dir,int index)635 void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index)
636 {
637 dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0);
638 }
639
dw_pcie_wait_for_link(struct dw_pcie * pci)640 int dw_pcie_wait_for_link(struct dw_pcie *pci)
641 {
642 u32 offset, val;
643 int retries;
644
645 /* Check if the link is up or not */
646 for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {
647 if (dw_pcie_link_up(pci))
648 break;
649
650 msleep(PCIE_LINK_WAIT_SLEEP_MS);
651 }
652
653 if (retries >= PCIE_LINK_WAIT_MAX_RETRIES) {
654 dev_info(pci->dev, "Phy link never came up\n");
655 return -ETIMEDOUT;
656 }
657
658 /*
659 * As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link
660 * speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms
661 * after Link training completes before sending a Configuration Request.
662 */
663 if (pci->max_link_speed > 2)
664 msleep(PCIE_RESET_CONFIG_WAIT_MS);
665
666 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
667 val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
668
669 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n",
670 FIELD_GET(PCI_EXP_LNKSTA_CLS, val),
671 FIELD_GET(PCI_EXP_LNKSTA_NLW, val));
672
673 return 0;
674 }
675 EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link);
676
dw_pcie_link_up(struct dw_pcie * pci)677 bool dw_pcie_link_up(struct dw_pcie *pci)
678 {
679 u32 val;
680
681 if (pci->ops && pci->ops->link_up)
682 return pci->ops->link_up(pci);
683
684 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1);
685 return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
686 (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
687 }
688 EXPORT_SYMBOL_GPL(dw_pcie_link_up);
689
dw_pcie_upconfig_setup(struct dw_pcie * pci)690 void dw_pcie_upconfig_setup(struct dw_pcie *pci)
691 {
692 u32 val;
693
694 val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL);
695 val |= PORT_MLTI_UPCFG_SUPPORT;
696 dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val);
697 }
698 EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
699
dw_pcie_link_set_max_speed(struct dw_pcie * pci)700 static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)
701 {
702 u32 cap, ctrl2, link_speed;
703 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
704
705 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
706
707 /*
708 * Even if the platform doesn't want to limit the maximum link speed,
709 * just cache the hardware default value so that the vendor drivers can
710 * use it to do any link specific configuration.
711 */
712 if (pci->max_link_speed < 1) {
713 pci->max_link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
714 return;
715 }
716
717 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
718 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
719
720 switch (pcie_link_speed[pci->max_link_speed]) {
721 case PCIE_SPEED_2_5GT:
722 link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
723 break;
724 case PCIE_SPEED_5_0GT:
725 link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
726 break;
727 case PCIE_SPEED_8_0GT:
728 link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;
729 break;
730 case PCIE_SPEED_16_0GT:
731 link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT;
732 break;
733 default:
734 /* Use hardware capability */
735 link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
736 ctrl2 &= ~PCI_EXP_LNKCTL2_HASD;
737 break;
738 }
739
740 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);
741
742 cap &= ~((u32)PCI_EXP_LNKCAP_SLS);
743 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed);
744
745 }
746
dw_pcie_link_get_max_link_width(struct dw_pcie * pci)747 int dw_pcie_link_get_max_link_width(struct dw_pcie *pci)
748 {
749 u8 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
750 u32 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
751
752 return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap);
753 }
754
dw_pcie_link_set_max_link_width(struct dw_pcie * pci,u32 num_lanes)755 static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
756 {
757 u32 lnkcap, lwsc, plc;
758 u8 cap;
759
760 if (!num_lanes)
761 return;
762
763 /* Set the number of lanes */
764 plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
765 plc &= ~PORT_LINK_FAST_LINK_MODE;
766 plc &= ~PORT_LINK_MODE_MASK;
767
768 /* Set link width speed control register */
769 lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
770 lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK;
771 lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES;
772 switch (num_lanes) {
773 case 1:
774 plc |= PORT_LINK_MODE_1_LANES;
775 break;
776 case 2:
777 plc |= PORT_LINK_MODE_2_LANES;
778 break;
779 case 4:
780 plc |= PORT_LINK_MODE_4_LANES;
781 break;
782 case 8:
783 plc |= PORT_LINK_MODE_8_LANES;
784 break;
785 case 16:
786 plc |= PORT_LINK_MODE_16_LANES;
787 break;
788 default:
789 dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
790 return;
791 }
792 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
793 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
794
795 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
796 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
797 lnkcap &= ~PCI_EXP_LNKCAP_MLW;
798 lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
799 dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
800 }
801
dw_pcie_iatu_detect(struct dw_pcie * pci)802 void dw_pcie_iatu_detect(struct dw_pcie *pci)
803 {
804 int max_region, ob, ib;
805 u32 val, min, dir;
806 u64 max;
807
808 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
809 if (val == 0xFFFFFFFF) {
810 dw_pcie_cap_set(pci, IATU_UNROLL);
811
812 max_region = min((int)pci->atu_size / 512, 256);
813 } else {
814 pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE;
815 pci->atu_size = PCIE_ATU_VIEWPORT_SIZE;
816
817 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF);
818 max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1;
819 }
820
821 for (ob = 0; ob < max_region; ob++) {
822 dw_pcie_writel_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET, 0x11110000);
823 val = dw_pcie_readl_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET);
824 if (val != 0x11110000)
825 break;
826 }
827
828 for (ib = 0; ib < max_region; ib++) {
829 dw_pcie_writel_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET, 0x11110000);
830 val = dw_pcie_readl_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET);
831 if (val != 0x11110000)
832 break;
833 }
834
835 if (ob) {
836 dir = PCIE_ATU_REGION_DIR_OB;
837 } else if (ib) {
838 dir = PCIE_ATU_REGION_DIR_IB;
839 } else {
840 dev_err(pci->dev, "No iATU regions found\n");
841 return;
842 }
843
844 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_LIMIT, 0x0);
845 min = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_LIMIT);
846
847 if (dw_pcie_ver_is_ge(pci, 460A)) {
848 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT, 0xFFFFFFFF);
849 max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT);
850 } else {
851 max = 0;
852 }
853
854 pci->num_ob_windows = ob;
855 pci->num_ib_windows = ib;
856 pci->region_align = 1 << fls(min);
857 pci->region_limit = (max << 32) | (SZ_4G - 1);
858
859 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n",
860 dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F",
861 pci->num_ob_windows, pci->num_ib_windows,
862 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G);
863 }
864
dw_pcie_readl_dma(struct dw_pcie * pci,u32 reg)865 static u32 dw_pcie_readl_dma(struct dw_pcie *pci, u32 reg)
866 {
867 u32 val = 0;
868 int ret;
869
870 if (pci->ops && pci->ops->read_dbi)
871 return pci->ops->read_dbi(pci, pci->edma.reg_base, reg, 4);
872
873 ret = dw_pcie_read(pci->edma.reg_base + reg, 4, &val);
874 if (ret)
875 dev_err(pci->dev, "Read DMA address failed\n");
876
877 return val;
878 }
879
dw_pcie_edma_irq_vector(struct device * dev,unsigned int nr)880 static int dw_pcie_edma_irq_vector(struct device *dev, unsigned int nr)
881 {
882 struct platform_device *pdev = to_platform_device(dev);
883 char name[6];
884 int ret;
885
886 if (nr >= EDMA_MAX_WR_CH + EDMA_MAX_RD_CH)
887 return -EINVAL;
888
889 ret = platform_get_irq_byname_optional(pdev, "dma");
890 if (ret > 0)
891 return ret;
892
893 snprintf(name, sizeof(name), "dma%u", nr);
894
895 return platform_get_irq_byname_optional(pdev, name);
896 }
897
898 static struct dw_edma_plat_ops dw_pcie_edma_ops = {
899 .irq_vector = dw_pcie_edma_irq_vector,
900 };
901
dw_pcie_edma_init_data(struct dw_pcie * pci)902 static void dw_pcie_edma_init_data(struct dw_pcie *pci)
903 {
904 pci->edma.dev = pci->dev;
905
906 if (!pci->edma.ops)
907 pci->edma.ops = &dw_pcie_edma_ops;
908
909 pci->edma.flags |= DW_EDMA_CHIP_LOCAL;
910 }
911
dw_pcie_edma_find_mf(struct dw_pcie * pci)912 static int dw_pcie_edma_find_mf(struct dw_pcie *pci)
913 {
914 u32 val;
915
916 /*
917 * Bail out finding the mapping format if it is already set by the glue
918 * driver. Also ensure that the edma.reg_base is pointing to a valid
919 * memory region.
920 */
921 if (pci->edma.mf != EDMA_MF_EDMA_LEGACY)
922 return pci->edma.reg_base ? 0 : -ENODEV;
923
924 /*
925 * Indirect eDMA CSRs access has been completely removed since v5.40a
926 * thus no space is now reserved for the eDMA channels viewport and
927 * former DMA CTRL register is no longer fixed to FFs.
928 */
929 if (dw_pcie_ver_is_ge(pci, 540A))
930 val = 0xFFFFFFFF;
931 else
932 val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
933
934 if (val == 0xFFFFFFFF && pci->edma.reg_base) {
935 pci->edma.mf = EDMA_MF_EDMA_UNROLL;
936 } else if (val != 0xFFFFFFFF) {
937 pci->edma.mf = EDMA_MF_EDMA_LEGACY;
938
939 pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE;
940 } else {
941 return -ENODEV;
942 }
943
944 return 0;
945 }
946
dw_pcie_edma_find_channels(struct dw_pcie * pci)947 static int dw_pcie_edma_find_channels(struct dw_pcie *pci)
948 {
949 u32 val;
950
951 /*
952 * Autodetect the read/write channels count only for non-HDMA platforms.
953 * HDMA platforms with native CSR mapping doesn't support autodetect,
954 * so the glue drivers should've passed the valid count already. If not,
955 * the below sanity check will catch it.
956 */
957 if (pci->edma.mf != EDMA_MF_HDMA_NATIVE) {
958 val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL);
959
960 pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val);
961 pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val);
962 }
963
964 /* Sanity check the channels count if the mapping was incorrect */
965 if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH ||
966 !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH)
967 return -EINVAL;
968
969 return 0;
970 }
971
dw_pcie_edma_find_chip(struct dw_pcie * pci)972 static int dw_pcie_edma_find_chip(struct dw_pcie *pci)
973 {
974 int ret;
975
976 dw_pcie_edma_init_data(pci);
977
978 ret = dw_pcie_edma_find_mf(pci);
979 if (ret)
980 return ret;
981
982 return dw_pcie_edma_find_channels(pci);
983 }
984
dw_pcie_edma_irq_verify(struct dw_pcie * pci)985 static int dw_pcie_edma_irq_verify(struct dw_pcie *pci)
986 {
987 struct platform_device *pdev = to_platform_device(pci->dev);
988 u16 ch_cnt = pci->edma.ll_wr_cnt + pci->edma.ll_rd_cnt;
989 char name[15];
990 int ret;
991
992 if (pci->edma.nr_irqs > 1)
993 return pci->edma.nr_irqs != ch_cnt ? -EINVAL : 0;
994
995 ret = platform_get_irq_byname_optional(pdev, "dma");
996 if (ret > 0) {
997 pci->edma.nr_irqs = 1;
998 return 0;
999 }
1000
1001 for (; pci->edma.nr_irqs < ch_cnt; pci->edma.nr_irqs++) {
1002 snprintf(name, sizeof(name), "dma%d", pci->edma.nr_irqs);
1003
1004 ret = platform_get_irq_byname_optional(pdev, name);
1005 if (ret <= 0)
1006 return -EINVAL;
1007 }
1008
1009 return 0;
1010 }
1011
dw_pcie_edma_ll_alloc(struct dw_pcie * pci)1012 static int dw_pcie_edma_ll_alloc(struct dw_pcie *pci)
1013 {
1014 struct dw_edma_region *ll;
1015 dma_addr_t paddr;
1016 int i;
1017
1018 for (i = 0; i < pci->edma.ll_wr_cnt; i++) {
1019 ll = &pci->edma.ll_region_wr[i];
1020 ll->sz = DMA_LLP_MEM_SIZE;
1021 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz,
1022 &paddr, GFP_KERNEL);
1023 if (!ll->vaddr.mem)
1024 return -ENOMEM;
1025
1026 ll->paddr = paddr;
1027 }
1028
1029 for (i = 0; i < pci->edma.ll_rd_cnt; i++) {
1030 ll = &pci->edma.ll_region_rd[i];
1031 ll->sz = DMA_LLP_MEM_SIZE;
1032 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz,
1033 &paddr, GFP_KERNEL);
1034 if (!ll->vaddr.mem)
1035 return -ENOMEM;
1036
1037 ll->paddr = paddr;
1038 }
1039
1040 return 0;
1041 }
1042
dw_pcie_edma_detect(struct dw_pcie * pci)1043 int dw_pcie_edma_detect(struct dw_pcie *pci)
1044 {
1045 int ret;
1046
1047 /* Don't fail if no eDMA was found (for the backward compatibility) */
1048 ret = dw_pcie_edma_find_chip(pci);
1049 if (ret)
1050 return 0;
1051
1052 /* Don't fail on the IRQs verification (for the backward compatibility) */
1053 ret = dw_pcie_edma_irq_verify(pci);
1054 if (ret) {
1055 dev_err(pci->dev, "Invalid eDMA IRQs found\n");
1056 return 0;
1057 }
1058
1059 ret = dw_pcie_edma_ll_alloc(pci);
1060 if (ret) {
1061 dev_err(pci->dev, "Couldn't allocate LLP memory\n");
1062 return ret;
1063 }
1064
1065 /* Don't fail if the DW eDMA driver can't find the device */
1066 ret = dw_edma_probe(&pci->edma);
1067 if (ret && ret != -ENODEV) {
1068 dev_err(pci->dev, "Couldn't register eDMA device\n");
1069 return ret;
1070 }
1071
1072 dev_info(pci->dev, "eDMA: unroll %s, %hu wr, %hu rd\n",
1073 pci->edma.mf == EDMA_MF_EDMA_UNROLL ? "T" : "F",
1074 pci->edma.ll_wr_cnt, pci->edma.ll_rd_cnt);
1075
1076 return 0;
1077 }
1078
dw_pcie_edma_remove(struct dw_pcie * pci)1079 void dw_pcie_edma_remove(struct dw_pcie *pci)
1080 {
1081 dw_edma_remove(&pci->edma);
1082 }
1083
dw_pcie_setup(struct dw_pcie * pci)1084 void dw_pcie_setup(struct dw_pcie *pci)
1085 {
1086 u32 val;
1087
1088 dw_pcie_link_set_max_speed(pci);
1089
1090 /* Configure Gen1 N_FTS */
1091 if (pci->n_fts[0]) {
1092 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
1093 val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK);
1094 val |= PORT_AFR_N_FTS(pci->n_fts[0]);
1095 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]);
1096 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
1097 }
1098
1099 /* Configure Gen2+ N_FTS */
1100 if (pci->n_fts[1]) {
1101 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
1102 val &= ~PORT_LOGIC_N_FTS_MASK;
1103 val |= pci->n_fts[1];
1104 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
1105 }
1106
1107 if (dw_pcie_cap_is(pci, CDM_CHECK)) {
1108 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
1109 val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
1110 PCIE_PL_CHK_REG_CHK_REG_START;
1111 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
1112 }
1113
1114 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
1115 val &= ~PORT_LINK_FAST_LINK_MODE;
1116 val |= PORT_LINK_DLL_LINK_EN;
1117 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
1118
1119 dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
1120 }
1121
dw_pcie_parent_bus_offset(struct dw_pcie * pci,const char * reg_name,resource_size_t cpu_phys_addr)1122 resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
1123 const char *reg_name,
1124 resource_size_t cpu_phys_addr)
1125 {
1126 struct device *dev = pci->dev;
1127 struct device_node *np = dev->of_node;
1128 int index;
1129 u64 reg_addr, fixup_addr;
1130 u64 (*fixup)(struct dw_pcie *pcie, u64 cpu_addr);
1131
1132 /* Look up reg_name address on parent bus */
1133 index = of_property_match_string(np, "reg-names", reg_name);
1134
1135 if (index < 0) {
1136 dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name);
1137 return 0;
1138 }
1139
1140 of_property_read_reg(np, index, ®_addr, NULL);
1141
1142 fixup = pci->ops ? pci->ops->cpu_addr_fixup : NULL;
1143 if (fixup) {
1144 fixup_addr = fixup(pci, cpu_phys_addr);
1145 if (reg_addr == fixup_addr) {
1146 dev_info(dev, "%s reg[%d] %#010llx == %#010llx == fixup(cpu %#010llx); %ps is redundant with this devicetree\n",
1147 reg_name, index, reg_addr, fixup_addr,
1148 (unsigned long long) cpu_phys_addr, fixup);
1149 } else {
1150 dev_warn(dev, "%s reg[%d] %#010llx != %#010llx == fixup(cpu %#010llx); devicetree is broken\n",
1151 reg_name, index, reg_addr, fixup_addr,
1152 (unsigned long long) cpu_phys_addr);
1153 reg_addr = fixup_addr;
1154 }
1155
1156 return cpu_phys_addr - reg_addr;
1157 }
1158
1159 if (pci->use_parent_dt_ranges) {
1160
1161 /*
1162 * This platform once had a fixup, presumably because it
1163 * translates between CPU and PCI controller addresses.
1164 * Log a note if devicetree didn't describe a translation.
1165 */
1166 if (reg_addr == cpu_phys_addr)
1167 dev_info(dev, "%s reg[%d] %#010llx == cpu %#010llx\n; no fixup was ever needed for this devicetree\n",
1168 reg_name, index, reg_addr,
1169 (unsigned long long) cpu_phys_addr);
1170 } else {
1171 if (reg_addr != cpu_phys_addr) {
1172 dev_warn(dev, "%s reg[%d] %#010llx != cpu %#010llx; no fixup and devicetree \"ranges\" is broken, assuming no translation\n",
1173 reg_name, index, reg_addr,
1174 (unsigned long long) cpu_phys_addr);
1175 return 0;
1176 }
1177 }
1178
1179 return cpu_phys_addr - reg_addr;
1180 }
1181