1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare PCIe host controller driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 */ 10 11 #include <linux/align.h> 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/dma/edma.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/ioport.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/pcie-dwc.h> 21 #include <linux/platform_device.h> 22 #include <linux/sizes.h> 23 #include <linux/types.h> 24 25 #include "../../pci.h" 26 #include "pcie-designware.h" 27 28 static const char * const dw_pcie_app_clks[DW_PCIE_NUM_APP_CLKS] = { 29 [DW_PCIE_DBI_CLK] = "dbi", 30 [DW_PCIE_MSTR_CLK] = "mstr", 31 [DW_PCIE_SLV_CLK] = "slv", 32 }; 33 34 static const char * const dw_pcie_core_clks[DW_PCIE_NUM_CORE_CLKS] = { 35 [DW_PCIE_PIPE_CLK] = "pipe", 36 [DW_PCIE_CORE_CLK] = "core", 37 [DW_PCIE_AUX_CLK] = "aux", 38 [DW_PCIE_REF_CLK] = "ref", 39 }; 40 41 static const char * const dw_pcie_app_rsts[DW_PCIE_NUM_APP_RSTS] = { 42 [DW_PCIE_DBI_RST] = "dbi", 43 [DW_PCIE_MSTR_RST] = "mstr", 44 [DW_PCIE_SLV_RST] = "slv", 45 }; 46 47 static const char * const dw_pcie_core_rsts[DW_PCIE_NUM_CORE_RSTS] = { 48 [DW_PCIE_NON_STICKY_RST] = "non-sticky", 49 [DW_PCIE_STICKY_RST] = "sticky", 50 [DW_PCIE_CORE_RST] = "core", 51 [DW_PCIE_PIPE_RST] = "pipe", 52 [DW_PCIE_PHY_RST] = "phy", 53 [DW_PCIE_HOT_RST] = "hot", 54 [DW_PCIE_PWR_RST] = "pwr", 55 }; 56 57 static const struct dwc_pcie_vsec_id dwc_pcie_ptm_vsec_ids[] = { 58 { .vendor_id = PCI_VENDOR_ID_QCOM, /* EP */ 59 .vsec_id = 0x03, .vsec_rev = 0x1 }, 60 { .vendor_id = PCI_VENDOR_ID_QCOM, /* RC */ 61 .vsec_id = 0x04, .vsec_rev = 0x1 }, 62 { } 63 }; 64 65 static int dw_pcie_get_clocks(struct dw_pcie *pci) 66 { 67 int i, ret; 68 69 for (i = 0; i < DW_PCIE_NUM_APP_CLKS; i++) 70 pci->app_clks[i].id = dw_pcie_app_clks[i]; 71 72 for (i = 0; i < DW_PCIE_NUM_CORE_CLKS; i++) 73 pci->core_clks[i].id = dw_pcie_core_clks[i]; 74 75 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS, 76 pci->app_clks); 77 if (ret) 78 return ret; 79 80 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS, 81 pci->core_clks); 82 } 83 84 static int dw_pcie_get_resets(struct dw_pcie *pci) 85 { 86 int i, ret; 87 88 for (i = 0; i < DW_PCIE_NUM_APP_RSTS; i++) 89 pci->app_rsts[i].id = dw_pcie_app_rsts[i]; 90 91 for (i = 0; i < DW_PCIE_NUM_CORE_RSTS; i++) 92 pci->core_rsts[i].id = dw_pcie_core_rsts[i]; 93 94 ret = devm_reset_control_bulk_get_optional_shared(pci->dev, 95 DW_PCIE_NUM_APP_RSTS, 96 pci->app_rsts); 97 if (ret) 98 return ret; 99 100 ret = devm_reset_control_bulk_get_optional_exclusive(pci->dev, 101 DW_PCIE_NUM_CORE_RSTS, 102 pci->core_rsts); 103 if (ret) 104 return ret; 105 106 pci->pe_rst = devm_gpiod_get_optional(pci->dev, "reset", GPIOD_OUT_HIGH); 107 if (IS_ERR(pci->pe_rst)) 108 return PTR_ERR(pci->pe_rst); 109 110 return 0; 111 } 112 113 int dw_pcie_get_resources(struct dw_pcie *pci) 114 { 115 struct platform_device *pdev = to_platform_device(pci->dev); 116 struct device_node *np = dev_of_node(pci->dev); 117 struct resource *res; 118 int ret; 119 120 if (!pci->dbi_base) { 121 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 122 pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); 123 if (IS_ERR(pci->dbi_base)) 124 return PTR_ERR(pci->dbi_base); 125 pci->dbi_phys_addr = res->start; 126 } 127 128 /* DBI2 is mainly useful for the endpoint controller */ 129 if (!pci->dbi_base2) { 130 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); 131 if (res) { 132 pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res); 133 if (IS_ERR(pci->dbi_base2)) 134 return PTR_ERR(pci->dbi_base2); 135 } else { 136 pci->dbi_base2 = pci->dbi_base + SZ_4K; 137 } 138 } 139 140 /* For non-unrolled iATU/eDMA platforms this range will be ignored */ 141 if (!pci->atu_base) { 142 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); 143 if (res) { 144 pci->atu_size = resource_size(res); 145 pci->atu_base = devm_ioremap_resource(pci->dev, res); 146 if (IS_ERR(pci->atu_base)) 147 return PTR_ERR(pci->atu_base); 148 pci->atu_phys_addr = res->start; 149 } else { 150 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; 151 } 152 } 153 154 /* Set a default value suitable for at most 8 in and 8 out windows */ 155 if (!pci->atu_size) 156 pci->atu_size = SZ_4K; 157 158 /* eDMA region can be mapped to a custom base address */ 159 if (!pci->edma.reg_base) { 160 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); 161 if (res) { 162 pci->edma.reg_base = devm_ioremap_resource(pci->dev, res); 163 if (IS_ERR(pci->edma.reg_base)) 164 return PTR_ERR(pci->edma.reg_base); 165 } else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) { 166 pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET; 167 } 168 } 169 170 /* ELBI is an optional resource */ 171 if (!pci->elbi_base) { 172 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); 173 if (res) { 174 pci->elbi_base = devm_ioremap_resource(pci->dev, res); 175 if (IS_ERR(pci->elbi_base)) 176 return PTR_ERR(pci->elbi_base); 177 } 178 } 179 180 /* LLDD is supposed to manually switch the clocks and resets state */ 181 if (dw_pcie_cap_is(pci, REQ_RES)) { 182 ret = dw_pcie_get_clocks(pci); 183 if (ret) 184 return ret; 185 186 ret = dw_pcie_get_resets(pci); 187 if (ret) 188 return ret; 189 } 190 191 if (pci->max_link_speed < 1) 192 pci->max_link_speed = of_pci_get_max_link_speed(np); 193 194 of_property_read_u32(np, "num-lanes", &pci->num_lanes); 195 196 if (of_property_read_bool(np, "snps,enable-cdm-check")) 197 dw_pcie_cap_set(pci, CDM_CHECK); 198 199 return 0; 200 } 201 202 void dw_pcie_version_detect(struct dw_pcie *pci) 203 { 204 u32 ver; 205 206 /* The content of the CSR is zero on DWC PCIe older than v4.70a */ 207 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_NUMBER); 208 if (!ver) 209 return; 210 211 if (pci->version && pci->version != ver) 212 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n", 213 pci->version, ver); 214 else 215 pci->version = ver; 216 217 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_TYPE); 218 219 if (pci->type && pci->type != ver) 220 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n", 221 pci->type, ver); 222 else 223 pci->type = ver; 224 } 225 226 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) 227 { 228 return PCI_FIND_NEXT_CAP(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap, 229 pci); 230 } 231 EXPORT_SYMBOL_GPL(dw_pcie_find_capability); 232 233 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) 234 { 235 return PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, 0, cap, pci); 236 } 237 EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); 238 239 static u16 __dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id, 240 u16 vsec_id) 241 { 242 u16 vsec = 0; 243 u32 header; 244 245 if (vendor_id != dw_pcie_readw_dbi(pci, PCI_VENDOR_ID)) 246 return 0; 247 248 while ((vsec = PCI_FIND_NEXT_EXT_CAP(dw_pcie_read_cfg, vsec, 249 PCI_EXT_CAP_ID_VNDR, pci))) { 250 header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); 251 if (PCI_VNDR_HEADER_ID(header) == vsec_id) 252 return vsec; 253 } 254 255 return 0; 256 } 257 258 static u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, 259 const struct dwc_pcie_vsec_id *vsec_ids) 260 { 261 const struct dwc_pcie_vsec_id *vid; 262 u16 vsec; 263 u32 header; 264 265 for (vid = vsec_ids; vid->vendor_id; vid++) { 266 vsec = __dw_pcie_find_vsec_capability(pci, vid->vendor_id, 267 vid->vsec_id); 268 if (vsec) { 269 header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); 270 if (PCI_VNDR_HEADER_REV(header) == vid->vsec_rev) 271 return vsec; 272 } 273 } 274 275 return 0; 276 } 277 278 u16 dw_pcie_find_rasdes_capability(struct dw_pcie *pci) 279 { 280 return dw_pcie_find_vsec_capability(pci, dwc_pcie_rasdes_vsec_ids); 281 } 282 EXPORT_SYMBOL_GPL(dw_pcie_find_rasdes_capability); 283 284 u16 dw_pcie_find_ptm_capability(struct dw_pcie *pci) 285 { 286 return dw_pcie_find_vsec_capability(pci, dwc_pcie_ptm_vsec_ids); 287 } 288 EXPORT_SYMBOL_GPL(dw_pcie_find_ptm_capability); 289 290 int dw_pcie_read(void __iomem *addr, int size, u32 *val) 291 { 292 if (!IS_ALIGNED((uintptr_t)addr, size)) { 293 *val = 0; 294 return PCIBIOS_BAD_REGISTER_NUMBER; 295 } 296 297 if (size == 4) { 298 *val = readl(addr); 299 } else if (size == 2) { 300 *val = readw(addr); 301 } else if (size == 1) { 302 *val = readb(addr); 303 } else { 304 *val = 0; 305 return PCIBIOS_BAD_REGISTER_NUMBER; 306 } 307 308 return PCIBIOS_SUCCESSFUL; 309 } 310 EXPORT_SYMBOL_GPL(dw_pcie_read); 311 312 int dw_pcie_write(void __iomem *addr, int size, u32 val) 313 { 314 if (!IS_ALIGNED((uintptr_t)addr, size)) 315 return PCIBIOS_BAD_REGISTER_NUMBER; 316 317 if (size == 4) 318 writel(val, addr); 319 else if (size == 2) 320 writew(val, addr); 321 else if (size == 1) 322 writeb(val, addr); 323 else 324 return PCIBIOS_BAD_REGISTER_NUMBER; 325 326 return PCIBIOS_SUCCESSFUL; 327 } 328 EXPORT_SYMBOL_GPL(dw_pcie_write); 329 330 u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size) 331 { 332 int ret; 333 u32 val; 334 335 if (pci->ops && pci->ops->read_dbi) 336 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); 337 338 ret = dw_pcie_read(pci->dbi_base + reg, size, &val); 339 if (ret) 340 dev_err(pci->dev, "Read DBI address failed\n"); 341 342 return val; 343 } 344 EXPORT_SYMBOL_GPL(dw_pcie_read_dbi); 345 346 void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) 347 { 348 int ret; 349 350 if (pci->ops && pci->ops->write_dbi) { 351 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); 352 return; 353 } 354 355 ret = dw_pcie_write(pci->dbi_base + reg, size, val); 356 if (ret) 357 dev_err(pci->dev, "Write DBI address failed\n"); 358 } 359 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi); 360 361 void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) 362 { 363 int ret; 364 365 if (pci->ops && pci->ops->write_dbi2) { 366 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); 367 return; 368 } 369 370 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); 371 if (ret) 372 dev_err(pci->dev, "write DBI address failed\n"); 373 } 374 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi2); 375 376 static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir, 377 u32 index) 378 { 379 if (dw_pcie_cap_is(pci, IATU_UNROLL)) 380 return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index); 381 382 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, dir | index); 383 return pci->atu_base; 384 } 385 386 static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 dir, u32 index, u32 reg) 387 { 388 void __iomem *base; 389 int ret; 390 u32 val; 391 392 base = dw_pcie_select_atu(pci, dir, index); 393 394 if (pci->ops && pci->ops->read_dbi) 395 return pci->ops->read_dbi(pci, base, reg, 4); 396 397 ret = dw_pcie_read(base + reg, 4, &val); 398 if (ret) 399 dev_err(pci->dev, "Read ATU address failed\n"); 400 401 return val; 402 } 403 404 static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 dir, u32 index, 405 u32 reg, u32 val) 406 { 407 void __iomem *base; 408 int ret; 409 410 base = dw_pcie_select_atu(pci, dir, index); 411 412 if (pci->ops && pci->ops->write_dbi) { 413 pci->ops->write_dbi(pci, base, reg, 4, val); 414 return; 415 } 416 417 ret = dw_pcie_write(base + reg, 4, val); 418 if (ret) 419 dev_err(pci->dev, "Write ATU address failed\n"); 420 } 421 422 static inline u32 dw_pcie_readl_atu_ob(struct dw_pcie *pci, u32 index, u32 reg) 423 { 424 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg); 425 } 426 427 static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg, 428 u32 val) 429 { 430 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg, val); 431 } 432 433 static inline u32 dw_pcie_enable_ecrc(u32 val) 434 { 435 /* 436 * DesignWare core version 4.90A has a design issue where the 'TD' 437 * bit in the Control register-1 of the ATU outbound region acts 438 * like an override for the ECRC setting, i.e., the presence of TLP 439 * Digest (ECRC) in the outgoing TLPs is solely determined by this 440 * bit. This is contrary to the PCIe spec which says that the 441 * enablement of the ECRC is solely determined by the AER 442 * registers. 443 * 444 * Because of this, even when the ECRC is enabled through AER 445 * registers, the transactions going through ATU won't have TLP 446 * Digest as there is no way the PCI core AER code could program 447 * the TD bit which is specific to the DesignWare core. 448 * 449 * The best way to handle this scenario is to program the TD bit 450 * always. It affects only the traffic from root port to downstream 451 * devices. 452 * 453 * At this point, 454 * When ECRC is enabled in AER registers, everything works normally 455 * When ECRC is NOT enabled in AER registers, then, 456 * on Root Port:- TLP Digest (DWord size) gets appended to each packet 457 * even through it is not required. Since downstream 458 * TLPs are mostly for configuration accesses and BAR 459 * accesses, they are not in critical path and won't 460 * have much negative effect on the performance. 461 * on End Point:- TLP Digest is received for some/all the packets coming 462 * from the root port. TLP Digest is ignored because, 463 * as per the PCIe Spec r5.0 v1.0 section 2.2.3 464 * "TLP Digest Rules", when an endpoint receives TLP 465 * Digest when its ECRC check functionality is disabled 466 * in AER registers, received TLP Digest is just ignored. 467 * Since there is no issue or error reported either side, best way to 468 * handle the scenario is to program TD bit by default. 469 */ 470 471 return val | PCIE_ATU_TD; 472 } 473 474 int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, 475 const struct dw_pcie_ob_atu_cfg *atu) 476 { 477 u64 parent_bus_addr = atu->parent_bus_addr; 478 u32 retries, val; 479 u64 limit_addr; 480 481 limit_addr = parent_bus_addr + atu->size - 1; 482 483 if ((limit_addr & ~pci->region_limit) != (parent_bus_addr & ~pci->region_limit) || 484 !IS_ALIGNED(parent_bus_addr, pci->region_align) || 485 !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) { 486 return -EINVAL; 487 } 488 489 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE, 490 lower_32_bits(parent_bus_addr)); 491 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE, 492 upper_32_bits(parent_bus_addr)); 493 494 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT, 495 lower_32_bits(limit_addr)); 496 if (dw_pcie_ver_is_ge(pci, 460A)) 497 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT, 498 upper_32_bits(limit_addr)); 499 500 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET, 501 lower_32_bits(atu->pci_addr)); 502 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET, 503 upper_32_bits(atu->pci_addr)); 504 505 val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no); 506 if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) && 507 dw_pcie_ver_is_ge(pci, 460A)) 508 val |= PCIE_ATU_INCREASE_REGION_SIZE; 509 if (dw_pcie_ver_is(pci, 490A)) 510 val = dw_pcie_enable_ecrc(val); 511 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); 512 513 val = PCIE_ATU_ENABLE | atu->ctrl2; 514 if (atu->type == PCIE_ATU_TYPE_MSG) { 515 /* The data-less messages only for now */ 516 val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code; 517 } 518 dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val); 519 520 /* 521 * Make sure ATU enable takes effect before any subsequent config 522 * and I/O accesses. 523 */ 524 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 525 val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2); 526 if (val & PCIE_ATU_ENABLE) 527 return 0; 528 529 mdelay(LINK_WAIT_IATU); 530 } 531 532 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); 533 534 return -ETIMEDOUT; 535 } 536 537 static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg) 538 { 539 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg); 540 } 541 542 static inline void dw_pcie_writel_atu_ib(struct dw_pcie *pci, u32 index, u32 reg, 543 u32 val) 544 { 545 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg, val); 546 } 547 548 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, 549 u64 parent_bus_addr, u64 pci_addr, u64 size) 550 { 551 u64 limit_addr = pci_addr + size - 1; 552 u32 retries, val; 553 554 if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) || 555 !IS_ALIGNED(parent_bus_addr, pci->region_align) || 556 !IS_ALIGNED(pci_addr, pci->region_align) || !size) { 557 return -EINVAL; 558 } 559 560 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_BASE, 561 lower_32_bits(pci_addr)); 562 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_BASE, 563 upper_32_bits(pci_addr)); 564 565 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LIMIT, 566 lower_32_bits(limit_addr)); 567 if (dw_pcie_ver_is_ge(pci, 460A)) 568 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_LIMIT, 569 upper_32_bits(limit_addr)); 570 571 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, 572 lower_32_bits(parent_bus_addr)); 573 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET, 574 upper_32_bits(parent_bus_addr)); 575 576 val = type; 577 if (upper_32_bits(limit_addr) > upper_32_bits(pci_addr) && 578 dw_pcie_ver_is_ge(pci, 460A)) 579 val |= PCIE_ATU_INCREASE_REGION_SIZE; 580 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, val); 581 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); 582 583 /* 584 * Make sure ATU enable takes effect before any subsequent config 585 * and I/O accesses. 586 */ 587 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 588 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2); 589 if (val & PCIE_ATU_ENABLE) 590 return 0; 591 592 mdelay(LINK_WAIT_IATU); 593 } 594 595 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); 596 597 return -ETIMEDOUT; 598 } 599 600 int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, 601 int type, u64 parent_bus_addr, u8 bar, size_t size) 602 { 603 u32 retries, val; 604 605 if (!IS_ALIGNED(parent_bus_addr, pci->region_align) || 606 !IS_ALIGNED(parent_bus_addr, size)) 607 return -EINVAL; 608 609 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, 610 lower_32_bits(parent_bus_addr)); 611 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET, 612 upper_32_bits(parent_bus_addr)); 613 614 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, type | 615 PCIE_ATU_FUNC_NUM(func_no)); 616 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, 617 PCIE_ATU_ENABLE | PCIE_ATU_FUNC_NUM_MATCH_EN | 618 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8)); 619 620 /* 621 * Make sure ATU enable takes effect before any subsequent config 622 * and I/O accesses. 623 */ 624 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 625 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2); 626 if (val & PCIE_ATU_ENABLE) 627 return 0; 628 629 mdelay(LINK_WAIT_IATU); 630 } 631 632 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); 633 634 return -ETIMEDOUT; 635 } 636 637 void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index) 638 { 639 dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0); 640 } 641 642 int dw_pcie_wait_for_link(struct dw_pcie *pci) 643 { 644 u32 offset, val; 645 int retries; 646 647 /* Check if the link is up or not */ 648 for (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { 649 if (dw_pcie_link_up(pci)) 650 break; 651 652 msleep(PCIE_LINK_WAIT_SLEEP_MS); 653 } 654 655 if (retries >= PCIE_LINK_WAIT_MAX_RETRIES) { 656 dev_info(pci->dev, "Phy link never came up\n"); 657 return -ETIMEDOUT; 658 } 659 660 /* 661 * As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link 662 * speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms 663 * after Link training completes before sending a Configuration Request. 664 */ 665 if (pci->max_link_speed > 2) 666 msleep(PCIE_RESET_CONFIG_WAIT_MS); 667 668 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 669 val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); 670 671 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", 672 FIELD_GET(PCI_EXP_LNKSTA_CLS, val), 673 FIELD_GET(PCI_EXP_LNKSTA_NLW, val)); 674 675 return 0; 676 } 677 EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link); 678 679 bool dw_pcie_link_up(struct dw_pcie *pci) 680 { 681 u32 val; 682 683 if (pci->ops && pci->ops->link_up) 684 return pci->ops->link_up(pci); 685 686 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1); 687 return ((val & PCIE_PORT_DEBUG1_LINK_UP) && 688 (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING))); 689 } 690 EXPORT_SYMBOL_GPL(dw_pcie_link_up); 691 692 void dw_pcie_upconfig_setup(struct dw_pcie *pci) 693 { 694 u32 val; 695 696 val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL); 697 val |= PORT_MLTI_UPCFG_SUPPORT; 698 dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val); 699 } 700 EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); 701 702 static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) 703 { 704 u32 cap, ctrl2, link_speed; 705 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 706 707 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 708 709 /* 710 * Even if the platform doesn't want to limit the maximum link speed, 711 * just cache the hardware default value so that the vendor drivers can 712 * use it to do any link specific configuration. 713 */ 714 if (pci->max_link_speed < 1) { 715 pci->max_link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); 716 return; 717 } 718 719 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2); 720 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS; 721 722 switch (pcie_link_speed[pci->max_link_speed]) { 723 case PCIE_SPEED_2_5GT: 724 link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT; 725 break; 726 case PCIE_SPEED_5_0GT: 727 link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT; 728 break; 729 case PCIE_SPEED_8_0GT: 730 link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT; 731 break; 732 case PCIE_SPEED_16_0GT: 733 link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT; 734 break; 735 default: 736 /* Use hardware capability */ 737 link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); 738 ctrl2 &= ~PCI_EXP_LNKCTL2_HASD; 739 break; 740 } 741 742 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed); 743 744 cap &= ~((u32)PCI_EXP_LNKCAP_SLS); 745 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed); 746 747 } 748 749 int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) 750 { 751 u8 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 752 u32 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); 753 754 return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); 755 } 756 757 static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) 758 { 759 u32 lnkcap, lwsc, plc; 760 u8 cap; 761 762 if (!num_lanes) 763 return; 764 765 /* Set the number of lanes */ 766 plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); 767 plc &= ~PORT_LINK_FAST_LINK_MODE; 768 plc &= ~PORT_LINK_MODE_MASK; 769 770 /* Set link width speed control register */ 771 lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 772 lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK; 773 lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES; 774 switch (num_lanes) { 775 case 1: 776 plc |= PORT_LINK_MODE_1_LANES; 777 break; 778 case 2: 779 plc |= PORT_LINK_MODE_2_LANES; 780 break; 781 case 4: 782 plc |= PORT_LINK_MODE_4_LANES; 783 break; 784 case 8: 785 plc |= PORT_LINK_MODE_8_LANES; 786 break; 787 case 16: 788 plc |= PORT_LINK_MODE_16_LANES; 789 break; 790 default: 791 dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes); 792 return; 793 } 794 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc); 795 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc); 796 797 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 798 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); 799 lnkcap &= ~PCI_EXP_LNKCAP_MLW; 800 lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes); 801 dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); 802 } 803 804 void dw_pcie_iatu_detect(struct dw_pcie *pci) 805 { 806 int max_region, ob, ib; 807 u32 val, min, dir; 808 u64 max; 809 810 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); 811 if (val == 0xFFFFFFFF) { 812 dw_pcie_cap_set(pci, IATU_UNROLL); 813 814 max_region = min((int)pci->atu_size / 512, 256); 815 } else { 816 pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE; 817 pci->atu_size = PCIE_ATU_VIEWPORT_SIZE; 818 819 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF); 820 max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1; 821 } 822 823 for (ob = 0; ob < max_region; ob++) { 824 dw_pcie_writel_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET, 0x11110000); 825 val = dw_pcie_readl_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET); 826 if (val != 0x11110000) 827 break; 828 } 829 830 for (ib = 0; ib < max_region; ib++) { 831 dw_pcie_writel_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET, 0x11110000); 832 val = dw_pcie_readl_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET); 833 if (val != 0x11110000) 834 break; 835 } 836 837 if (ob) { 838 dir = PCIE_ATU_REGION_DIR_OB; 839 } else if (ib) { 840 dir = PCIE_ATU_REGION_DIR_IB; 841 } else { 842 dev_err(pci->dev, "No iATU regions found\n"); 843 return; 844 } 845 846 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_LIMIT, 0x0); 847 min = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_LIMIT); 848 849 if (dw_pcie_ver_is_ge(pci, 460A)) { 850 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT, 0xFFFFFFFF); 851 max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT); 852 } else { 853 max = 0; 854 } 855 856 pci->num_ob_windows = ob; 857 pci->num_ib_windows = ib; 858 pci->region_align = 1 << fls(min); 859 pci->region_limit = (max << 32) | (SZ_4G - 1); 860 861 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n", 862 dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F", 863 pci->num_ob_windows, pci->num_ib_windows, 864 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G); 865 } 866 867 static u32 dw_pcie_readl_dma(struct dw_pcie *pci, u32 reg) 868 { 869 u32 val = 0; 870 int ret; 871 872 if (pci->ops && pci->ops->read_dbi) 873 return pci->ops->read_dbi(pci, pci->edma.reg_base, reg, 4); 874 875 ret = dw_pcie_read(pci->edma.reg_base + reg, 4, &val); 876 if (ret) 877 dev_err(pci->dev, "Read DMA address failed\n"); 878 879 return val; 880 } 881 882 static int dw_pcie_edma_irq_vector(struct device *dev, unsigned int nr) 883 { 884 struct platform_device *pdev = to_platform_device(dev); 885 char name[6]; 886 int ret; 887 888 if (nr >= EDMA_MAX_WR_CH + EDMA_MAX_RD_CH) 889 return -EINVAL; 890 891 ret = platform_get_irq_byname_optional(pdev, "dma"); 892 if (ret > 0) 893 return ret; 894 895 snprintf(name, sizeof(name), "dma%u", nr); 896 897 return platform_get_irq_byname_optional(pdev, name); 898 } 899 900 static struct dw_edma_plat_ops dw_pcie_edma_ops = { 901 .irq_vector = dw_pcie_edma_irq_vector, 902 }; 903 904 static void dw_pcie_edma_init_data(struct dw_pcie *pci) 905 { 906 pci->edma.dev = pci->dev; 907 908 if (!pci->edma.ops) 909 pci->edma.ops = &dw_pcie_edma_ops; 910 911 pci->edma.flags |= DW_EDMA_CHIP_LOCAL; 912 } 913 914 static int dw_pcie_edma_find_mf(struct dw_pcie *pci) 915 { 916 u32 val; 917 918 /* 919 * Bail out finding the mapping format if it is already set by the glue 920 * driver. Also ensure that the edma.reg_base is pointing to a valid 921 * memory region. 922 */ 923 if (pci->edma.mf != EDMA_MF_EDMA_LEGACY) 924 return pci->edma.reg_base ? 0 : -ENODEV; 925 926 /* 927 * Indirect eDMA CSRs access has been completely removed since v5.40a 928 * thus no space is now reserved for the eDMA channels viewport and 929 * former DMA CTRL register is no longer fixed to FFs. 930 */ 931 if (dw_pcie_ver_is_ge(pci, 540A)) 932 val = 0xFFFFFFFF; 933 else 934 val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); 935 936 if (val == 0xFFFFFFFF && pci->edma.reg_base) { 937 pci->edma.mf = EDMA_MF_EDMA_UNROLL; 938 } else if (val != 0xFFFFFFFF) { 939 pci->edma.mf = EDMA_MF_EDMA_LEGACY; 940 941 pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE; 942 } else { 943 return -ENODEV; 944 } 945 946 return 0; 947 } 948 949 static int dw_pcie_edma_find_channels(struct dw_pcie *pci) 950 { 951 u32 val; 952 953 /* 954 * Autodetect the read/write channels count only for non-HDMA platforms. 955 * HDMA platforms with native CSR mapping doesn't support autodetect, 956 * so the glue drivers should've passed the valid count already. If not, 957 * the below sanity check will catch it. 958 */ 959 if (pci->edma.mf != EDMA_MF_HDMA_NATIVE) { 960 val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); 961 962 pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); 963 pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); 964 } 965 966 /* Sanity check the channels count if the mapping was incorrect */ 967 if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH || 968 !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH) 969 return -EINVAL; 970 971 return 0; 972 } 973 974 static int dw_pcie_edma_find_chip(struct dw_pcie *pci) 975 { 976 int ret; 977 978 dw_pcie_edma_init_data(pci); 979 980 ret = dw_pcie_edma_find_mf(pci); 981 if (ret) 982 return ret; 983 984 return dw_pcie_edma_find_channels(pci); 985 } 986 987 static int dw_pcie_edma_irq_verify(struct dw_pcie *pci) 988 { 989 struct platform_device *pdev = to_platform_device(pci->dev); 990 u16 ch_cnt = pci->edma.ll_wr_cnt + pci->edma.ll_rd_cnt; 991 char name[15]; 992 int ret; 993 994 if (pci->edma.nr_irqs > 1) 995 return pci->edma.nr_irqs != ch_cnt ? -EINVAL : 0; 996 997 ret = platform_get_irq_byname_optional(pdev, "dma"); 998 if (ret > 0) { 999 pci->edma.nr_irqs = 1; 1000 return 0; 1001 } 1002 1003 for (; pci->edma.nr_irqs < ch_cnt; pci->edma.nr_irqs++) { 1004 snprintf(name, sizeof(name), "dma%d", pci->edma.nr_irqs); 1005 1006 ret = platform_get_irq_byname_optional(pdev, name); 1007 if (ret <= 0) 1008 return -EINVAL; 1009 } 1010 1011 return 0; 1012 } 1013 1014 static int dw_pcie_edma_ll_alloc(struct dw_pcie *pci) 1015 { 1016 struct dw_edma_region *ll; 1017 dma_addr_t paddr; 1018 int i; 1019 1020 for (i = 0; i < pci->edma.ll_wr_cnt; i++) { 1021 ll = &pci->edma.ll_region_wr[i]; 1022 ll->sz = DMA_LLP_MEM_SIZE; 1023 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, 1024 &paddr, GFP_KERNEL); 1025 if (!ll->vaddr.mem) 1026 return -ENOMEM; 1027 1028 ll->paddr = paddr; 1029 } 1030 1031 for (i = 0; i < pci->edma.ll_rd_cnt; i++) { 1032 ll = &pci->edma.ll_region_rd[i]; 1033 ll->sz = DMA_LLP_MEM_SIZE; 1034 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, 1035 &paddr, GFP_KERNEL); 1036 if (!ll->vaddr.mem) 1037 return -ENOMEM; 1038 1039 ll->paddr = paddr; 1040 } 1041 1042 return 0; 1043 } 1044 1045 int dw_pcie_edma_detect(struct dw_pcie *pci) 1046 { 1047 int ret; 1048 1049 /* Don't fail if no eDMA was found (for the backward compatibility) */ 1050 ret = dw_pcie_edma_find_chip(pci); 1051 if (ret) 1052 return 0; 1053 1054 /* Don't fail on the IRQs verification (for the backward compatibility) */ 1055 ret = dw_pcie_edma_irq_verify(pci); 1056 if (ret) { 1057 dev_err(pci->dev, "Invalid eDMA IRQs found\n"); 1058 return 0; 1059 } 1060 1061 ret = dw_pcie_edma_ll_alloc(pci); 1062 if (ret) { 1063 dev_err(pci->dev, "Couldn't allocate LLP memory\n"); 1064 return ret; 1065 } 1066 1067 /* Don't fail if the DW eDMA driver can't find the device */ 1068 ret = dw_edma_probe(&pci->edma); 1069 if (ret && ret != -ENODEV) { 1070 dev_err(pci->dev, "Couldn't register eDMA device\n"); 1071 return ret; 1072 } 1073 1074 dev_info(pci->dev, "eDMA: unroll %s, %hu wr, %hu rd\n", 1075 pci->edma.mf == EDMA_MF_EDMA_UNROLL ? "T" : "F", 1076 pci->edma.ll_wr_cnt, pci->edma.ll_rd_cnt); 1077 1078 return 0; 1079 } 1080 1081 void dw_pcie_edma_remove(struct dw_pcie *pci) 1082 { 1083 dw_edma_remove(&pci->edma); 1084 } 1085 1086 void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *pci) 1087 { 1088 u16 l1ss; 1089 u32 l1ss_cap; 1090 1091 if (pci->l1ss_support) 1092 return; 1093 1094 l1ss = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); 1095 if (!l1ss) 1096 return; 1097 1098 /* 1099 * Unless the driver claims "l1ss_support", don't advertise L1 PM 1100 * Substates because they require CLKREQ# and possibly other 1101 * device-specific configuration. 1102 */ 1103 l1ss_cap = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP); 1104 l1ss_cap &= ~(PCI_L1SS_CAP_PCIPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_1 | 1105 PCI_L1SS_CAP_PCIPM_L1_2 | PCI_L1SS_CAP_ASPM_L1_2 | 1106 PCI_L1SS_CAP_L1_PM_SS); 1107 dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, l1ss_cap); 1108 } 1109 1110 void dw_pcie_setup(struct dw_pcie *pci) 1111 { 1112 u32 val; 1113 1114 dw_pcie_link_set_max_speed(pci); 1115 1116 /* Configure Gen1 N_FTS */ 1117 if (pci->n_fts[0]) { 1118 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); 1119 val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK); 1120 val |= PORT_AFR_N_FTS(pci->n_fts[0]); 1121 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]); 1122 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); 1123 } 1124 1125 /* Configure Gen2+ N_FTS */ 1126 if (pci->n_fts[1]) { 1127 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 1128 val &= ~PORT_LOGIC_N_FTS_MASK; 1129 val |= pci->n_fts[1]; 1130 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 1131 } 1132 1133 if (dw_pcie_cap_is(pci, CDM_CHECK)) { 1134 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); 1135 val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | 1136 PCIE_PL_CHK_REG_CHK_REG_START; 1137 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); 1138 } 1139 1140 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); 1141 val &= ~PORT_LINK_FAST_LINK_MODE; 1142 val |= PORT_LINK_DLL_LINK_EN; 1143 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); 1144 1145 dw_pcie_link_set_max_link_width(pci, pci->num_lanes); 1146 } 1147 1148 resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci, 1149 const char *reg_name, 1150 resource_size_t cpu_phys_addr) 1151 { 1152 struct device *dev = pci->dev; 1153 struct device_node *np = dev->of_node; 1154 int index; 1155 u64 reg_addr, fixup_addr; 1156 u64 (*fixup)(struct dw_pcie *pcie, u64 cpu_addr); 1157 1158 /* Look up reg_name address on parent bus */ 1159 index = of_property_match_string(np, "reg-names", reg_name); 1160 1161 if (index < 0) { 1162 dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name); 1163 return 0; 1164 } 1165 1166 of_property_read_reg(np, index, ®_addr, NULL); 1167 1168 fixup = pci->ops ? pci->ops->cpu_addr_fixup : NULL; 1169 if (fixup) { 1170 fixup_addr = fixup(pci, cpu_phys_addr); 1171 if (reg_addr == fixup_addr) { 1172 dev_info(dev, "%s reg[%d] %#010llx == %#010llx == fixup(cpu %#010llx); %ps is redundant with this devicetree\n", 1173 reg_name, index, reg_addr, fixup_addr, 1174 (unsigned long long) cpu_phys_addr, fixup); 1175 } else { 1176 dev_warn(dev, "%s reg[%d] %#010llx != %#010llx == fixup(cpu %#010llx); devicetree is broken\n", 1177 reg_name, index, reg_addr, fixup_addr, 1178 (unsigned long long) cpu_phys_addr); 1179 reg_addr = fixup_addr; 1180 } 1181 1182 return cpu_phys_addr - reg_addr; 1183 } 1184 1185 if (pci->use_parent_dt_ranges) { 1186 1187 /* 1188 * This platform once had a fixup, presumably because it 1189 * translates between CPU and PCI controller addresses. 1190 * Log a note if devicetree didn't describe a translation. 1191 */ 1192 if (reg_addr == cpu_phys_addr) 1193 dev_info(dev, "%s reg[%d] %#010llx == cpu %#010llx\n; no fixup was ever needed for this devicetree\n", 1194 reg_name, index, reg_addr, 1195 (unsigned long long) cpu_phys_addr); 1196 } else { 1197 if (reg_addr != cpu_phys_addr) { 1198 dev_warn(dev, "%s reg[%d] %#010llx != cpu %#010llx; no fixup and devicetree \"ranges\" is broken, assuming no translation\n", 1199 reg_name, index, reg_addr, 1200 (unsigned long long) cpu_phys_addr); 1201 return 0; 1202 } 1203 } 1204 1205 return cpu_phys_addr - reg_addr; 1206 } 1207