1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2024 Collabora Ltd. 5 * 6 * Author: Algea Cao <algea.cao@rock-chips.com> 7 * Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> 8 */ 9 #include <linux/completion.h> 10 #include <linux/hdmi.h> 11 #include <linux/export.h> 12 #include <linux/i2c.h> 13 #include <linux/irq.h> 14 #include <linux/minmax.h> 15 #include <linux/module.h> 16 #include <linux/mutex.h> 17 #include <linux/of.h> 18 #include <linux/workqueue.h> 19 20 #include <drm/bridge/dw_hdmi_qp.h> 21 #include <drm/display/drm_hdmi_helper.h> 22 #include <drm/display/drm_hdmi_cec_helper.h> 23 #include <drm/display/drm_hdmi_state_helper.h> 24 #include <drm/drm_atomic.h> 25 #include <drm/drm_atomic_helper.h> 26 #include <drm/drm_bridge.h> 27 #include <drm/drm_connector.h> 28 #include <drm/drm_edid.h> 29 #include <drm/drm_modes.h> 30 #include <drm/drm_print.h> 31 32 #include <media/cec.h> 33 34 #include <sound/hdmi-codec.h> 35 36 #include "dw-hdmi-qp.h" 37 38 #define DDC_CI_ADDR 0x37 39 #define DDC_SEGMENT_ADDR 0x30 40 41 #define SCRAMB_POLL_DELAY_MS 3000 42 43 /* 44 * Unless otherwise noted, entries in this table are 100% optimization. 45 * Values can be obtained from dw_hdmi_qp_compute_n() but that function is 46 * slow so we pre-compute values we expect to see. 47 * 48 * The values for TMDS 25175, 25200, 27000, 54000, 74250 and 148500 kHz are 49 * the recommended N values specified in the Audio chapter of the HDMI 50 * specification. 51 */ 52 static const struct dw_hdmi_audio_tmds_n { 53 unsigned long tmds; 54 unsigned int n_32k; 55 unsigned int n_44k1; 56 unsigned int n_48k; 57 } common_tmds_n_table[] = { 58 { .tmds = 25175000, .n_32k = 4576, .n_44k1 = 7007, .n_48k = 6864, }, 59 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 60 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 61 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, }, 62 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, }, 63 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 64 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 65 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 66 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 67 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 68 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 69 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 70 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 71 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 72 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, }, 73 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 74 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, }, 75 { .tmds = 73250000, .n_32k = 11648, .n_44k1 = 14112, .n_48k = 6144, }, 76 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 77 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, }, 78 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 79 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 80 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 81 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 82 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 83 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 84 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 85 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 86 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 87 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 88 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, }, 89 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 90 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 91 { .tmds = 146250000, .n_32k = 11648, .n_44k1 = 6272, .n_48k = 6144, }, 92 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 93 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 94 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 95 96 /* For 297 MHz+ HDMI spec have some other rule for setting N */ 97 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, }, 98 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240,}, 99 100 /* End of table */ 101 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, }, 102 }; 103 104 /* 105 * These are the CTS values as recommended in the Audio chapter of the HDMI 106 * specification. 107 */ 108 static const struct dw_hdmi_audio_tmds_cts { 109 unsigned long tmds; 110 unsigned int cts_32k; 111 unsigned int cts_44k1; 112 unsigned int cts_48k; 113 } common_tmds_cts_table[] = { 114 { .tmds = 25175000, .cts_32k = 28125, .cts_44k1 = 31250, .cts_48k = 28125, }, 115 { .tmds = 25200000, .cts_32k = 25200, .cts_44k1 = 28000, .cts_48k = 25200, }, 116 { .tmds = 27000000, .cts_32k = 27000, .cts_44k1 = 30000, .cts_48k = 27000, }, 117 { .tmds = 54000000, .cts_32k = 54000, .cts_44k1 = 60000, .cts_48k = 54000, }, 118 { .tmds = 74250000, .cts_32k = 74250, .cts_44k1 = 82500, .cts_48k = 74250, }, 119 { .tmds = 148500000, .cts_32k = 148500, .cts_44k1 = 165000, .cts_48k = 148500, }, 120 121 /* End of table */ 122 { .tmds = 0, .cts_32k = 0, .cts_44k1 = 0, .cts_48k = 0, }, 123 }; 124 125 struct dw_hdmi_qp_i2c { 126 struct i2c_adapter adap; 127 128 struct mutex lock; /* used to serialize data transfers */ 129 struct completion cmp; 130 u8 stat; 131 132 u8 slave_reg; 133 bool is_regaddr; 134 bool is_segment; 135 }; 136 137 #ifdef CONFIG_DRM_DW_HDMI_QP_CEC 138 struct dw_hdmi_qp_cec { 139 struct drm_connector *connector; 140 int irq; 141 u32 addresses; 142 struct cec_msg rx_msg; 143 u8 tx_status; 144 bool tx_done; 145 bool rx_done; 146 }; 147 #endif 148 149 struct dw_hdmi_qp { 150 struct drm_bridge bridge; 151 152 struct device *dev; 153 struct dw_hdmi_qp_i2c *i2c; 154 155 #ifdef CONFIG_DRM_DW_HDMI_QP_CEC 156 struct dw_hdmi_qp_cec *cec; 157 #endif 158 159 struct { 160 const struct dw_hdmi_qp_phy_ops *ops; 161 void *data; 162 } phy; 163 164 unsigned long ref_clk_rate; 165 struct regmap *regm; 166 int main_irq; 167 168 unsigned long tmds_char_rate; 169 bool no_hpd; 170 }; 171 172 static void dw_hdmi_qp_write(struct dw_hdmi_qp *hdmi, unsigned int val, 173 int offset) 174 { 175 regmap_write(hdmi->regm, offset, val); 176 } 177 178 static unsigned int dw_hdmi_qp_read(struct dw_hdmi_qp *hdmi, int offset) 179 { 180 unsigned int val = 0; 181 182 regmap_read(hdmi->regm, offset, &val); 183 184 return val; 185 } 186 187 static void dw_hdmi_qp_mod(struct dw_hdmi_qp *hdmi, unsigned int data, 188 unsigned int mask, unsigned int reg) 189 { 190 regmap_update_bits(hdmi->regm, reg, mask, data); 191 } 192 193 static struct dw_hdmi_qp *dw_hdmi_qp_from_bridge(struct drm_bridge *bridge) 194 { 195 return container_of(bridge, struct dw_hdmi_qp, bridge); 196 } 197 198 static void dw_hdmi_qp_set_cts_n(struct dw_hdmi_qp *hdmi, unsigned int cts, 199 unsigned int n) 200 { 201 /* Set N */ 202 dw_hdmi_qp_mod(hdmi, n, AUDPKT_ACR_N_VALUE, AUDPKT_ACR_CONTROL0); 203 204 /* Set CTS */ 205 if (cts) 206 dw_hdmi_qp_mod(hdmi, AUDPKT_ACR_CTS_OVR_EN, AUDPKT_ACR_CTS_OVR_EN_MSK, 207 AUDPKT_ACR_CONTROL1); 208 else 209 dw_hdmi_qp_mod(hdmi, 0, AUDPKT_ACR_CTS_OVR_EN_MSK, 210 AUDPKT_ACR_CONTROL1); 211 212 dw_hdmi_qp_mod(hdmi, AUDPKT_ACR_CTS_OVR_VAL(cts), AUDPKT_ACR_CTS_OVR_VAL_MSK, 213 AUDPKT_ACR_CONTROL1); 214 } 215 216 static int dw_hdmi_qp_match_tmds_n_table(struct dw_hdmi_qp *hdmi, 217 unsigned long pixel_clk, 218 unsigned long freq) 219 { 220 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL; 221 int i; 222 223 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) { 224 if (pixel_clk == common_tmds_n_table[i].tmds) { 225 tmds_n = &common_tmds_n_table[i]; 226 break; 227 } 228 } 229 230 if (!tmds_n) 231 return -ENOENT; 232 233 switch (freq) { 234 case 32000: 235 return tmds_n->n_32k; 236 case 44100: 237 case 88200: 238 case 176400: 239 return (freq / 44100) * tmds_n->n_44k1; 240 case 48000: 241 case 96000: 242 case 192000: 243 return (freq / 48000) * tmds_n->n_48k; 244 default: 245 return -ENOENT; 246 } 247 } 248 249 static u32 dw_hdmi_qp_audio_math_diff(unsigned int freq, unsigned int n, 250 unsigned int pixel_clk) 251 { 252 u64 cts = mul_u32_u32(pixel_clk, n); 253 254 return do_div(cts, 128 * freq); 255 } 256 257 static unsigned int dw_hdmi_qp_compute_n(struct dw_hdmi_qp *hdmi, 258 unsigned long pixel_clk, 259 unsigned long freq) 260 { 261 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500); 262 unsigned int max_n = (128 * freq) / 300; 263 unsigned int ideal_n = (128 * freq) / 1000; 264 unsigned int best_n_distance = ideal_n; 265 unsigned int best_n = 0; 266 u64 best_diff = U64_MAX; 267 int n; 268 269 /* If the ideal N could satisfy the audio math, then just take it */ 270 if (dw_hdmi_qp_audio_math_diff(freq, ideal_n, pixel_clk) == 0) 271 return ideal_n; 272 273 for (n = min_n; n <= max_n; n++) { 274 u64 diff = dw_hdmi_qp_audio_math_diff(freq, n, pixel_clk); 275 276 if (diff < best_diff || 277 (diff == best_diff && abs(n - ideal_n) < best_n_distance)) { 278 best_n = n; 279 best_diff = diff; 280 best_n_distance = abs(best_n - ideal_n); 281 } 282 283 /* 284 * The best N already satisfy the audio math, and also be 285 * the closest value to ideal N, so just cut the loop. 286 */ 287 if (best_diff == 0 && (abs(n - ideal_n) > best_n_distance)) 288 break; 289 } 290 291 return best_n; 292 } 293 294 static unsigned int dw_hdmi_qp_find_n(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk, 295 unsigned long sample_rate) 296 { 297 int n = dw_hdmi_qp_match_tmds_n_table(hdmi, pixel_clk, sample_rate); 298 299 if (n > 0) 300 return n; 301 302 dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n", 303 pixel_clk); 304 305 return dw_hdmi_qp_compute_n(hdmi, pixel_clk, sample_rate); 306 } 307 308 static unsigned int dw_hdmi_qp_find_cts(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk, 309 unsigned long sample_rate) 310 { 311 const struct dw_hdmi_audio_tmds_cts *tmds_cts = NULL; 312 int i; 313 314 for (i = 0; common_tmds_cts_table[i].tmds != 0; i++) { 315 if (pixel_clk == common_tmds_cts_table[i].tmds) { 316 tmds_cts = &common_tmds_cts_table[i]; 317 break; 318 } 319 } 320 321 if (!tmds_cts) 322 return 0; 323 324 switch (sample_rate) { 325 case 32000: 326 return tmds_cts->cts_32k; 327 case 44100: 328 case 88200: 329 case 176400: 330 return tmds_cts->cts_44k1; 331 case 48000: 332 case 96000: 333 case 192000: 334 return tmds_cts->cts_48k; 335 default: 336 return -ENOENT; 337 } 338 } 339 340 static void dw_hdmi_qp_set_audio_interface(struct dw_hdmi_qp *hdmi, 341 struct hdmi_codec_daifmt *fmt, 342 struct hdmi_codec_params *hparms) 343 { 344 u32 conf0 = 0; 345 346 /* Reset the audio data path of the AVP */ 347 dw_hdmi_qp_write(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWINIT_P, GLOBAL_SWRESET_REQUEST); 348 349 /* Disable AUDS, ACR, AUDI */ 350 dw_hdmi_qp_mod(hdmi, 0, 351 PKTSCHED_ACR_TX_EN | PKTSCHED_AUDS_TX_EN | PKTSCHED_AUDI_TX_EN, 352 PKTSCHED_PKT_EN); 353 354 /* Clear the audio FIFO */ 355 dw_hdmi_qp_write(hdmi, AUDIO_FIFO_CLR_P, AUDIO_INTERFACE_CONTROL0); 356 357 /* Select I2S interface as the audio source */ 358 dw_hdmi_qp_mod(hdmi, AUD_IF_I2S, AUD_IF_SEL_MSK, AUDIO_INTERFACE_CONFIG0); 359 360 /* Enable the active i2s lanes */ 361 switch (hparms->channels) { 362 case 7 ... 8: 363 conf0 |= I2S_LINES_EN(3); 364 fallthrough; 365 case 5 ... 6: 366 conf0 |= I2S_LINES_EN(2); 367 fallthrough; 368 case 3 ... 4: 369 conf0 |= I2S_LINES_EN(1); 370 fallthrough; 371 default: 372 conf0 |= I2S_LINES_EN(0); 373 break; 374 } 375 376 dw_hdmi_qp_mod(hdmi, conf0, I2S_LINES_EN_MSK, AUDIO_INTERFACE_CONFIG0); 377 378 /* 379 * Enable bpcuv generated internally for L-PCM, or received 380 * from stream for NLPCM/HBR. 381 */ 382 switch (fmt->bit_fmt) { 383 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE: 384 conf0 = (hparms->channels == 8) ? AUD_HBR : AUD_ASP; 385 conf0 |= I2S_BPCUV_RCV_EN; 386 break; 387 default: 388 conf0 = AUD_ASP | I2S_BPCUV_RCV_DIS; 389 break; 390 } 391 392 dw_hdmi_qp_mod(hdmi, conf0, I2S_BPCUV_RCV_MSK | AUD_FORMAT_MSK, 393 AUDIO_INTERFACE_CONFIG0); 394 395 /* Enable audio FIFO auto clear when overflow */ 396 dw_hdmi_qp_mod(hdmi, AUD_FIFO_INIT_ON_OVF_EN, AUD_FIFO_INIT_ON_OVF_MSK, 397 AUDIO_INTERFACE_CONFIG0); 398 } 399 400 /* 401 * When transmitting IEC60958 linear PCM audio, these registers allow to 402 * configure the channel status information of all the channel status 403 * bits in the IEC60958 frame. For the moment this configuration is only 404 * used when the I2S audio interface, General Purpose Audio (GPA), 405 * or AHB audio DMA (AHBAUDDMA) interface is active 406 * (for S/PDIF interface this information comes from the stream). 407 */ 408 static void dw_hdmi_qp_set_channel_status(struct dw_hdmi_qp *hdmi, 409 u8 *channel_status, bool ref2stream) 410 { 411 /* 412 * AUDPKT_CHSTATUS_OVR0: { RSV, RSV, CS1, CS0 } 413 * AUDPKT_CHSTATUS_OVR1: { CS6, CS5, CS4, CS3 } 414 * 415 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 416 * CS0: | Mode | d | c | b | a | 417 * CS1: | Category Code | 418 * CS2: | Channel Number | Source Number | 419 * CS3: | Clock Accuracy | Sample Freq | 420 * CS4: | Ori Sample Freq | Word Length | 421 * CS5: | | CGMS-A | 422 * CS6~CS23: Reserved 423 * 424 * a: use of channel status block 425 * b: linear PCM identification: 0 for lpcm, 1 for nlpcm 426 * c: copyright information 427 * d: additional format information 428 */ 429 430 if (ref2stream) 431 channel_status[0] |= IEC958_AES0_NONAUDIO; 432 433 if ((dw_hdmi_qp_read(hdmi, AUDIO_INTERFACE_CONFIG0) & GENMASK(25, 24)) == AUD_HBR) { 434 /* fixup cs for HBR */ 435 channel_status[3] = (channel_status[3] & 0xf0) | IEC958_AES3_CON_FS_768000; 436 channel_status[4] = (channel_status[4] & 0x0f) | IEC958_AES4_CON_ORIGFS_NOTID; 437 } 438 439 dw_hdmi_qp_write(hdmi, channel_status[0] | (channel_status[1] << 8), 440 AUDPKT_CHSTATUS_OVR0); 441 442 regmap_bulk_write(hdmi->regm, AUDPKT_CHSTATUS_OVR1, &channel_status[3], 1); 443 444 if (ref2stream) 445 dw_hdmi_qp_mod(hdmi, 0, 446 AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK, 447 AUDPKT_CONTROL0); 448 else 449 dw_hdmi_qp_mod(hdmi, AUDPKT_PBIT_FORCE_EN | AUDPKT_CHSTATUS_OVR_EN, 450 AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK, 451 AUDPKT_CONTROL0); 452 } 453 454 static void dw_hdmi_qp_set_sample_rate(struct dw_hdmi_qp *hdmi, unsigned long long tmds_char_rate, 455 unsigned int sample_rate) 456 { 457 unsigned int n, cts; 458 459 n = dw_hdmi_qp_find_n(hdmi, tmds_char_rate, sample_rate); 460 cts = dw_hdmi_qp_find_cts(hdmi, tmds_char_rate, sample_rate); 461 462 dw_hdmi_qp_set_cts_n(hdmi, cts, n); 463 } 464 465 static int dw_hdmi_qp_audio_enable(struct drm_bridge *bridge, 466 struct drm_connector *connector) 467 { 468 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 469 470 if (hdmi->tmds_char_rate) 471 dw_hdmi_qp_mod(hdmi, 0, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE); 472 473 return 0; 474 } 475 476 static int dw_hdmi_qp_audio_prepare(struct drm_bridge *bridge, 477 struct drm_connector *connector, 478 struct hdmi_codec_daifmt *fmt, 479 struct hdmi_codec_params *hparms) 480 { 481 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 482 bool ref2stream = false; 483 484 if (!hdmi->tmds_char_rate) 485 return -ENODEV; 486 487 if (fmt->bit_clk_provider | fmt->frame_clk_provider) { 488 dev_err(hdmi->dev, "unsupported clock settings\n"); 489 return -EINVAL; 490 } 491 492 if (fmt->bit_fmt == SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE) 493 ref2stream = true; 494 495 dw_hdmi_qp_set_audio_interface(hdmi, fmt, hparms); 496 dw_hdmi_qp_set_sample_rate(hdmi, hdmi->tmds_char_rate, hparms->sample_rate); 497 dw_hdmi_qp_set_channel_status(hdmi, hparms->iec.status, ref2stream); 498 drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, &hparms->cea); 499 500 return 0; 501 } 502 503 static void dw_hdmi_qp_audio_disable_regs(struct dw_hdmi_qp *hdmi) 504 { 505 /* 506 * Keep ACR, AUDI, AUDS packet always on to make SINK device 507 * active for better compatibility and user experience. 508 * 509 * This also fix POP sound on some SINK devices which wakeup 510 * from suspend to active. 511 */ 512 dw_hdmi_qp_mod(hdmi, I2S_BPCUV_RCV_DIS, I2S_BPCUV_RCV_MSK, 513 AUDIO_INTERFACE_CONFIG0); 514 dw_hdmi_qp_mod(hdmi, AUDPKT_PBIT_FORCE_EN | AUDPKT_CHSTATUS_OVR_EN, 515 AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK, 516 AUDPKT_CONTROL0); 517 518 dw_hdmi_qp_mod(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, 519 AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE); 520 } 521 522 static void dw_hdmi_qp_audio_disable(struct drm_bridge *bridge, 523 struct drm_connector *connector) 524 { 525 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 526 527 drm_atomic_helper_connector_hdmi_clear_audio_infoframe(connector); 528 529 if (hdmi->tmds_char_rate) 530 dw_hdmi_qp_audio_disable_regs(hdmi); 531 } 532 533 static int dw_hdmi_qp_i2c_read(struct dw_hdmi_qp *hdmi, 534 unsigned char *buf, unsigned int length) 535 { 536 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; 537 int stat; 538 539 if (!i2c->is_regaddr) { 540 dev_dbg(hdmi->dev, "set read register address to 0\n"); 541 i2c->slave_reg = 0x00; 542 i2c->is_regaddr = true; 543 } 544 545 while (length--) { 546 reinit_completion(&i2c->cmp); 547 548 dw_hdmi_qp_mod(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, 549 I2CM_INTERFACE_CONTROL0); 550 551 if (i2c->is_segment) 552 dw_hdmi_qp_mod(hdmi, I2CM_EXT_READ, I2CM_WR_MASK, 553 I2CM_INTERFACE_CONTROL0); 554 else 555 dw_hdmi_qp_mod(hdmi, I2CM_FM_READ, I2CM_WR_MASK, 556 I2CM_INTERFACE_CONTROL0); 557 558 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 559 if (!stat) { 560 if (hdmi->no_hpd) 561 dev_dbg_ratelimited(hdmi->dev, 562 "i2c read timed out\n"); 563 else 564 dev_err(hdmi->dev, "i2c read timed out\n"); 565 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); 566 return -EAGAIN; 567 } 568 569 /* Check for error condition on the bus */ 570 if (i2c->stat & I2CM_NACK_RCVD_IRQ) { 571 if (hdmi->no_hpd) 572 dev_dbg_ratelimited(hdmi->dev, 573 "i2c read error\n"); 574 else 575 dev_err(hdmi->dev, "i2c read error\n"); 576 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); 577 return -EIO; 578 } 579 580 *buf++ = dw_hdmi_qp_read(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff; 581 dw_hdmi_qp_mod(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); 582 } 583 584 i2c->is_segment = false; 585 586 return 0; 587 } 588 589 static int dw_hdmi_qp_i2c_write(struct dw_hdmi_qp *hdmi, 590 unsigned char *buf, unsigned int length) 591 { 592 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; 593 int stat; 594 595 if (!i2c->is_regaddr) { 596 /* Use the first write byte as register address */ 597 i2c->slave_reg = buf[0]; 598 length--; 599 buf++; 600 i2c->is_regaddr = true; 601 } 602 603 while (length--) { 604 reinit_completion(&i2c->cmp); 605 606 dw_hdmi_qp_write(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3); 607 dw_hdmi_qp_mod(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, 608 I2CM_INTERFACE_CONTROL0); 609 dw_hdmi_qp_mod(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK, 610 I2CM_INTERFACE_CONTROL0); 611 612 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 613 if (!stat) { 614 dev_err(hdmi->dev, "i2c write time out!\n"); 615 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); 616 return -EAGAIN; 617 } 618 619 /* Check for error condition on the bus */ 620 if (i2c->stat & I2CM_NACK_RCVD_IRQ) { 621 dev_err(hdmi->dev, "i2c write nack!\n"); 622 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); 623 return -EIO; 624 } 625 626 dw_hdmi_qp_mod(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); 627 } 628 629 return 0; 630 } 631 632 static int dw_hdmi_qp_i2c_xfer(struct i2c_adapter *adap, 633 struct i2c_msg *msgs, int num) 634 { 635 struct dw_hdmi_qp *hdmi = i2c_get_adapdata(adap); 636 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; 637 u8 addr = msgs[0].addr; 638 int i, ret = 0; 639 640 if (addr == DDC_CI_ADDR) 641 /* 642 * The internal I2C controller does not support the multi-byte 643 * read and write operations needed for DDC/CI. 644 * FIXME: Blacklist the DDC/CI address until we filter out 645 * unsupported I2C operations. 646 */ 647 return -EOPNOTSUPP; 648 649 for (i = 0; i < num; i++) { 650 if (msgs[i].len == 0) { 651 dev_err(hdmi->dev, 652 "unsupported transfer %d/%d, no data\n", 653 i + 1, num); 654 return -EOPNOTSUPP; 655 } 656 } 657 658 guard(mutex)(&i2c->lock); 659 660 /* Unmute DONE and ERROR interrupts */ 661 dw_hdmi_qp_mod(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, 662 I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, 663 MAINUNIT_1_INT_MASK_N); 664 665 /* Set slave device address taken from the first I2C message */ 666 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) 667 addr = DDC_ADDR; 668 669 dw_hdmi_qp_mod(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0); 670 671 /* Set slave device register address on transfer */ 672 i2c->is_regaddr = false; 673 674 /* Set segment pointer for I2C extended read mode operation */ 675 i2c->is_segment = false; 676 677 for (i = 0; i < num; i++) { 678 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 679 i2c->is_segment = true; 680 dw_hdmi_qp_mod(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR, 681 I2CM_INTERFACE_CONTROL1); 682 dw_hdmi_qp_mod(hdmi, *msgs[i].buf << 7, I2CM_SEG_PTR, 683 I2CM_INTERFACE_CONTROL1); 684 } else { 685 if (msgs[i].flags & I2C_M_RD) 686 ret = dw_hdmi_qp_i2c_read(hdmi, msgs[i].buf, 687 msgs[i].len); 688 else 689 ret = dw_hdmi_qp_i2c_write(hdmi, msgs[i].buf, 690 msgs[i].len); 691 } 692 if (ret < 0) 693 break; 694 } 695 696 if (!ret) 697 ret = num; 698 699 /* Mute DONE and ERROR interrupts */ 700 dw_hdmi_qp_mod(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N, 701 MAINUNIT_1_INT_MASK_N); 702 703 return ret; 704 } 705 706 static u32 dw_hdmi_qp_i2c_func(struct i2c_adapter *adapter) 707 { 708 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 709 } 710 711 static const struct i2c_algorithm dw_hdmi_qp_algorithm = { 712 .master_xfer = dw_hdmi_qp_i2c_xfer, 713 .functionality = dw_hdmi_qp_i2c_func, 714 }; 715 716 static struct i2c_adapter *dw_hdmi_qp_i2c_adapter(struct dw_hdmi_qp *hdmi) 717 { 718 struct dw_hdmi_qp_i2c *i2c; 719 struct i2c_adapter *adap; 720 int ret; 721 722 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 723 if (!i2c) 724 return ERR_PTR(-ENOMEM); 725 726 mutex_init(&i2c->lock); 727 init_completion(&i2c->cmp); 728 729 adap = &i2c->adap; 730 adap->owner = THIS_MODULE; 731 adap->dev.parent = hdmi->dev; 732 adap->algo = &dw_hdmi_qp_algorithm; 733 strscpy(adap->name, "DesignWare HDMI QP", sizeof(adap->name)); 734 735 i2c_set_adapdata(adap, hdmi); 736 737 ret = devm_i2c_add_adapter(hdmi->dev, adap); 738 if (ret) { 739 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 740 devm_kfree(hdmi->dev, i2c); 741 return ERR_PTR(ret); 742 } 743 744 hdmi->i2c = i2c; 745 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 746 747 return adap; 748 } 749 750 static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge, 751 struct drm_atomic_commit *state) 752 { 753 struct dw_hdmi_qp *hdmi = bridge->driver_private; 754 struct drm_connector_state *conn_state; 755 struct drm_connector *connector; 756 unsigned int op_mode; 757 758 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 759 if (WARN_ON(!connector)) 760 return; 761 762 conn_state = drm_atomic_get_new_connector_state(state, connector); 763 if (WARN_ON(!conn_state)) 764 return; 765 766 if (connector->display_info.is_hdmi) { 767 dev_dbg(hdmi->dev, "%s mode=HDMI %s rate=%llu bpc=%u\n", __func__, 768 drm_hdmi_connector_get_output_format_name(conn_state->hdmi.output_format), 769 conn_state->hdmi.tmds_char_rate, conn_state->hdmi.output_bpc); 770 op_mode = 0; 771 hdmi->tmds_char_rate = conn_state->hdmi.tmds_char_rate; 772 } else { 773 dev_dbg(hdmi->dev, "%s mode=DVI\n", __func__); 774 op_mode = OPMODE_DVI; 775 } 776 777 hdmi->phy.ops->init(hdmi, hdmi->phy.data); 778 779 dw_hdmi_qp_mod(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0); 780 dw_hdmi_qp_mod(hdmi, op_mode, OPMODE_DVI, LINK_CONFIG0); 781 782 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 783 } 784 785 static void dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge *bridge, 786 struct drm_atomic_commit *state) 787 { 788 struct dw_hdmi_qp *hdmi = bridge->driver_private; 789 790 hdmi->tmds_char_rate = 0; 791 792 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 793 } 794 795 static enum drm_connector_status 796 dw_hdmi_qp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 797 { 798 struct dw_hdmi_qp *hdmi = bridge->driver_private; 799 const struct drm_edid *drm_edid; 800 801 if (hdmi->no_hpd) { 802 drm_edid = drm_edid_read_ddc(connector, bridge->ddc); 803 if (drm_edid) 804 return connector_status_connected; 805 else 806 return connector_status_disconnected; 807 } 808 809 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 810 } 811 812 static const struct drm_edid * 813 dw_hdmi_qp_bridge_edid_read(struct drm_bridge *bridge, 814 struct drm_connector *connector) 815 { 816 struct dw_hdmi_qp *hdmi = bridge->driver_private; 817 const struct drm_edid *drm_edid; 818 819 drm_edid = drm_edid_read_ddc(connector, bridge->ddc); 820 if (!drm_edid) 821 dev_dbg(hdmi->dev, "failed to get edid\n"); 822 823 return drm_edid; 824 } 825 826 static enum drm_mode_status 827 dw_hdmi_qp_bridge_tmds_char_rate_valid(const struct drm_bridge *bridge, 828 const struct drm_display_mode *mode, 829 unsigned long long rate) 830 { 831 struct dw_hdmi_qp *hdmi = bridge->driver_private; 832 833 /* 834 * TODO: when hdmi->no_hpd is 1 we must not support modes that 835 * require scrambling, including every mode with a clock above 836 * HDMI_1_3_TMDS_CHAR_RATE_MAX_HZ. 837 */ 838 if (rate > HDMI_1_3_TMDS_CHAR_RATE_MAX_HZ) { 839 dev_dbg(hdmi->dev, "Unsupported TMDS char rate: %lld\n", rate); 840 return MODE_CLOCK_HIGH; 841 } 842 843 return MODE_OK; 844 } 845 846 static int dw_hdmi_qp_bridge_clear_avi_infoframe(struct drm_bridge *bridge) 847 { 848 struct dw_hdmi_qp *hdmi = bridge->driver_private; 849 850 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, 851 PKTSCHED_PKT_EN); 852 853 return 0; 854 } 855 856 static int dw_hdmi_qp_bridge_clear_hdmi_infoframe(struct drm_bridge *bridge) 857 { 858 struct dw_hdmi_qp *hdmi = bridge->driver_private; 859 860 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_VSI_TX_EN, PKTSCHED_PKT_EN); 861 862 return 0; 863 } 864 865 static int dw_hdmi_qp_bridge_clear_hdr_drm_infoframe(struct drm_bridge *bridge) 866 { 867 struct dw_hdmi_qp *hdmi = bridge->driver_private; 868 869 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN); 870 871 return 0; 872 } 873 874 static int dw_hdmi_qp_bridge_clear_spd_infoframe(struct drm_bridge *bridge) 875 { 876 struct dw_hdmi_qp *hdmi = bridge->driver_private; 877 878 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_SPDI_TX_EN, PKTSCHED_PKT_EN); 879 880 return 0; 881 } 882 883 static int dw_hdmi_qp_bridge_clear_audio_infoframe(struct drm_bridge *bridge) 884 { 885 struct dw_hdmi_qp *hdmi = bridge->driver_private; 886 887 dw_hdmi_qp_mod(hdmi, 0, 888 PKTSCHED_ACR_TX_EN | 889 PKTSCHED_AUDS_TX_EN | 890 PKTSCHED_AUDI_TX_EN, 891 PKTSCHED_PKT_EN); 892 893 return 0; 894 } 895 896 static void dw_hdmi_qp_write_pkt(struct dw_hdmi_qp *hdmi, const u8 *buffer, 897 size_t start, size_t len, unsigned int reg) 898 { 899 u32 val = 0; 900 size_t i; 901 902 for (i = start; i < start + len; i++) 903 val |= buffer[i] << ((i % 4) * BITS_PER_BYTE); 904 905 dw_hdmi_qp_write(hdmi, val, reg); 906 } 907 908 static void dw_hdmi_qp_write_infoframe(struct dw_hdmi_qp *hdmi, const u8 *buffer, 909 size_t len, unsigned int reg) 910 { 911 size_t i; 912 913 /* InfoFrame packet header */ 914 dw_hdmi_qp_write_pkt(hdmi, buffer, 1, 2, reg); 915 916 /* InfoFrame packet body */ 917 for (i = 0; i < len - 3; i += 4) 918 dw_hdmi_qp_write_pkt(hdmi, buffer + 3, i, min(len - i - 3, 4), 919 reg + i + 4); 920 } 921 922 static int dw_hdmi_qp_bridge_write_avi_infoframe(struct drm_bridge *bridge, 923 const u8 *buffer, size_t len) 924 { 925 struct dw_hdmi_qp *hdmi = bridge->driver_private; 926 927 dw_hdmi_qp_bridge_clear_avi_infoframe(bridge); 928 929 dw_hdmi_qp_write_infoframe(hdmi, buffer, len, PKT_AVI_CONTENTS0); 930 931 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1); 932 dw_hdmi_qp_mod(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, 933 PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, PKTSCHED_PKT_EN); 934 935 return 0; 936 } 937 938 static int dw_hdmi_qp_bridge_write_hdmi_infoframe(struct drm_bridge *bridge, 939 const u8 *buffer, size_t len) 940 { 941 struct dw_hdmi_qp *hdmi = bridge->driver_private; 942 943 dw_hdmi_qp_bridge_clear_hdmi_infoframe(bridge); 944 945 dw_hdmi_qp_write_infoframe(hdmi, buffer, len, PKT_VSI_CONTENTS0); 946 947 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_VSI_FIELDRATE, PKTSCHED_PKT_CONFIG1); 948 dw_hdmi_qp_mod(hdmi, PKTSCHED_VSI_TX_EN, PKTSCHED_VSI_TX_EN, 949 PKTSCHED_PKT_EN); 950 951 return 0; 952 } 953 954 static int dw_hdmi_qp_bridge_write_hdr_drm_infoframe(struct drm_bridge *bridge, 955 const u8 *buffer, size_t len) 956 { 957 struct dw_hdmi_qp *hdmi = bridge->driver_private; 958 959 dw_hdmi_qp_bridge_clear_hdr_drm_infoframe(bridge); 960 961 dw_hdmi_qp_write_infoframe(hdmi, buffer, len, PKT_DRMI_CONTENTS0); 962 963 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_FIELDRATE, PKTSCHED_PKT_CONFIG1); 964 dw_hdmi_qp_mod(hdmi, PKTSCHED_DRMI_TX_EN, PKTSCHED_DRMI_TX_EN, 965 PKTSCHED_PKT_EN); 966 967 return 0; 968 } 969 970 static int dw_hdmi_qp_bridge_write_spd_infoframe(struct drm_bridge *bridge, 971 const u8 *buffer, size_t len) 972 { 973 struct dw_hdmi_qp *hdmi = bridge->driver_private; 974 975 dw_hdmi_qp_bridge_clear_spd_infoframe(bridge); 976 977 dw_hdmi_qp_write_infoframe(hdmi, buffer, len, PKT_SPDI_CONTENTS0); 978 979 dw_hdmi_qp_mod(hdmi, PKTSCHED_SPDI_TX_EN, PKTSCHED_SPDI_TX_EN, 980 PKTSCHED_PKT_EN); 981 982 return 0; 983 } 984 985 static int dw_hdmi_qp_bridge_write_audio_infoframe(struct drm_bridge *bridge, 986 const u8 *buffer, size_t len) 987 { 988 struct dw_hdmi_qp *hdmi = bridge->driver_private; 989 990 dw_hdmi_qp_bridge_clear_audio_infoframe(bridge); 991 992 /* 993 * AUDI_CONTENTS0: { RSV, HB2, HB1, RSV } 994 * AUDI_CONTENTS1: { PB3, PB2, PB1, PB0 } 995 * AUDI_CONTENTS2: { PB7, PB6, PB5, PB4 } 996 * 997 * PB0: CheckSum 998 * PB1: | CT3 | CT2 | CT1 | CT0 | F13 | CC2 | CC1 | CC0 | 999 * PB2: | F27 | F26 | F25 | SF2 | SF1 | SF0 | SS1 | SS0 | 1000 * PB3: | F37 | F36 | F35 | F34 | F33 | F32 | F31 | F30 | 1001 * PB4: | CA7 | CA6 | CA5 | CA4 | CA3 | CA2 | CA1 | CA0 | 1002 * PB5: | DM_INH | LSV3 | LSV2 | LSV1 | LSV0 | F52 | F51 | F50 | 1003 * PB6~PB10: Reserved 1004 */ 1005 dw_hdmi_qp_write_infoframe(hdmi, buffer, len, PKT_AUDI_CONTENTS0); 1006 1007 /* Enable ACR, AUDI, AMD */ 1008 dw_hdmi_qp_mod(hdmi, 1009 PKTSCHED_ACR_TX_EN | PKTSCHED_AUDI_TX_EN | PKTSCHED_AMD_TX_EN, 1010 PKTSCHED_ACR_TX_EN | PKTSCHED_AUDI_TX_EN | PKTSCHED_AMD_TX_EN, 1011 PKTSCHED_PKT_EN); 1012 1013 /* Enable AUDS */ 1014 dw_hdmi_qp_mod(hdmi, PKTSCHED_AUDS_TX_EN, PKTSCHED_AUDS_TX_EN, PKTSCHED_PKT_EN); 1015 1016 return 0; 1017 } 1018 1019 #ifdef CONFIG_DRM_DW_HDMI_QP_CEC 1020 static irqreturn_t dw_hdmi_qp_cec_hardirq(int irq, void *dev_id) 1021 { 1022 struct dw_hdmi_qp *hdmi = dev_id; 1023 struct dw_hdmi_qp_cec *cec = hdmi->cec; 1024 irqreturn_t ret = IRQ_HANDLED; 1025 u32 stat; 1026 1027 stat = dw_hdmi_qp_read(hdmi, CEC_INT_STATUS); 1028 if (stat == 0) 1029 return IRQ_NONE; 1030 1031 dw_hdmi_qp_write(hdmi, stat, CEC_INT_CLEAR); 1032 1033 if (stat & CEC_STAT_LINE_ERR) { 1034 cec->tx_status = CEC_TX_STATUS_ERROR; 1035 cec->tx_done = true; 1036 ret = IRQ_WAKE_THREAD; 1037 } else if (stat & CEC_STAT_DONE) { 1038 cec->tx_status = CEC_TX_STATUS_OK; 1039 cec->tx_done = true; 1040 ret = IRQ_WAKE_THREAD; 1041 } else if (stat & CEC_STAT_NACK) { 1042 cec->tx_status = CEC_TX_STATUS_NACK; 1043 cec->tx_done = true; 1044 ret = IRQ_WAKE_THREAD; 1045 } 1046 1047 if (stat & CEC_STAT_EOM) { 1048 unsigned int len, i, val; 1049 1050 val = dw_hdmi_qp_read(hdmi, CEC_RX_COUNT_STATUS); 1051 len = (val & 0xf) + 1; 1052 1053 if (len > sizeof(cec->rx_msg.msg)) 1054 len = sizeof(cec->rx_msg.msg); 1055 1056 for (i = 0; i < 4; i++) { 1057 val = dw_hdmi_qp_read(hdmi, CEC_RX_DATA3_0 + i * 4); 1058 cec->rx_msg.msg[i * 4] = val & 0xff; 1059 cec->rx_msg.msg[i * 4 + 1] = (val >> 8) & 0xff; 1060 cec->rx_msg.msg[i * 4 + 2] = (val >> 16) & 0xff; 1061 cec->rx_msg.msg[i * 4 + 3] = (val >> 24) & 0xff; 1062 } 1063 1064 dw_hdmi_qp_write(hdmi, 1, CEC_LOCK_CONTROL); 1065 1066 cec->rx_msg.len = len; 1067 cec->rx_done = true; 1068 1069 ret = IRQ_WAKE_THREAD; 1070 } 1071 1072 return ret; 1073 } 1074 1075 static irqreturn_t dw_hdmi_qp_cec_thread(int irq, void *dev_id) 1076 { 1077 struct dw_hdmi_qp *hdmi = dev_id; 1078 struct dw_hdmi_qp_cec *cec = hdmi->cec; 1079 1080 if (cec->tx_done) { 1081 cec->tx_done = false; 1082 drm_connector_hdmi_cec_transmit_attempt_done(cec->connector, 1083 cec->tx_status); 1084 } 1085 1086 if (cec->rx_done) { 1087 cec->rx_done = false; 1088 drm_connector_hdmi_cec_received_msg(cec->connector, &cec->rx_msg); 1089 } 1090 1091 return IRQ_HANDLED; 1092 } 1093 1094 static int dw_hdmi_qp_cec_init(struct drm_bridge *bridge, 1095 struct drm_connector *connector) 1096 { 1097 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 1098 struct dw_hdmi_qp_cec *cec = hdmi->cec; 1099 1100 cec->connector = connector; 1101 1102 dw_hdmi_qp_write(hdmi, 0, CEC_TX_COUNT); 1103 dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); 1104 dw_hdmi_qp_write(hdmi, 0, CEC_INT_MASK_N); 1105 1106 return devm_request_threaded_irq(hdmi->dev, cec->irq, 1107 dw_hdmi_qp_cec_hardirq, 1108 dw_hdmi_qp_cec_thread, IRQF_SHARED, 1109 dev_name(hdmi->dev), hdmi); 1110 } 1111 1112 static int dw_hdmi_qp_cec_log_addr(struct drm_bridge *bridge, u8 logical_addr) 1113 { 1114 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 1115 struct dw_hdmi_qp_cec *cec = hdmi->cec; 1116 1117 if (logical_addr == CEC_LOG_ADDR_INVALID) 1118 cec->addresses = 0; 1119 else 1120 cec->addresses |= BIT(logical_addr) | CEC_ADDR_BROADCAST; 1121 1122 dw_hdmi_qp_write(hdmi, cec->addresses, CEC_ADDR); 1123 1124 return 0; 1125 } 1126 1127 static int dw_hdmi_qp_cec_enable(struct drm_bridge *bridge, bool enable) 1128 { 1129 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 1130 unsigned int irqs; 1131 u32 swdisable; 1132 1133 if (!enable) { 1134 dw_hdmi_qp_write(hdmi, 0, CEC_INT_MASK_N); 1135 dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); 1136 1137 swdisable = dw_hdmi_qp_read(hdmi, GLOBAL_SWDISABLE); 1138 swdisable = swdisable | CEC_SWDISABLE; 1139 dw_hdmi_qp_write(hdmi, swdisable, GLOBAL_SWDISABLE); 1140 } else { 1141 swdisable = dw_hdmi_qp_read(hdmi, GLOBAL_SWDISABLE); 1142 swdisable = swdisable & ~CEC_SWDISABLE; 1143 dw_hdmi_qp_write(hdmi, swdisable, GLOBAL_SWDISABLE); 1144 1145 dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); 1146 dw_hdmi_qp_write(hdmi, 1, CEC_LOCK_CONTROL); 1147 1148 dw_hdmi_qp_cec_log_addr(bridge, CEC_LOG_ADDR_INVALID); 1149 1150 irqs = CEC_STAT_LINE_ERR | CEC_STAT_NACK | CEC_STAT_EOM | 1151 CEC_STAT_DONE; 1152 dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); 1153 dw_hdmi_qp_write(hdmi, irqs, CEC_INT_MASK_N); 1154 } 1155 1156 return 0; 1157 } 1158 1159 static int dw_hdmi_qp_cec_transmit(struct drm_bridge *bridge, u8 attempts, 1160 u32 signal_free_time, struct cec_msg *msg) 1161 { 1162 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 1163 unsigned int i; 1164 u32 val; 1165 1166 for (i = 0; i < msg->len; i++) { 1167 if (!(i % 4)) 1168 val = msg->msg[i]; 1169 if ((i % 4) == 1) 1170 val |= msg->msg[i] << 8; 1171 if ((i % 4) == 2) 1172 val |= msg->msg[i] << 16; 1173 if ((i % 4) == 3) 1174 val |= msg->msg[i] << 24; 1175 1176 if (i == (msg->len - 1) || (i % 4) == 3) 1177 dw_hdmi_qp_write(hdmi, val, CEC_TX_DATA3_0 + (i / 4) * 4); 1178 } 1179 1180 dw_hdmi_qp_write(hdmi, msg->len - 1, CEC_TX_COUNT); 1181 dw_hdmi_qp_write(hdmi, CEC_CTRL_START, CEC_TX_CONTROL); 1182 1183 return 0; 1184 } 1185 #else 1186 #define dw_hdmi_qp_cec_init NULL 1187 #define dw_hdmi_qp_cec_enable NULL 1188 #define dw_hdmi_qp_cec_log_addr NULL 1189 #define dw_hdmi_qp_cec_transmit NULL 1190 #endif /* CONFIG_DRM_DW_HDMI_QP_CEC */ 1191 1192 static const struct drm_bridge_funcs dw_hdmi_qp_bridge_funcs = { 1193 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1194 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1195 .atomic_reset = drm_atomic_helper_bridge_reset, 1196 .atomic_enable = dw_hdmi_qp_bridge_atomic_enable, 1197 .atomic_disable = dw_hdmi_qp_bridge_atomic_disable, 1198 .detect = dw_hdmi_qp_bridge_detect, 1199 .edid_read = dw_hdmi_qp_bridge_edid_read, 1200 .hdmi_tmds_char_rate_valid = dw_hdmi_qp_bridge_tmds_char_rate_valid, 1201 .hdmi_clear_avi_infoframe = dw_hdmi_qp_bridge_clear_avi_infoframe, 1202 .hdmi_write_avi_infoframe = dw_hdmi_qp_bridge_write_avi_infoframe, 1203 .hdmi_clear_hdmi_infoframe = dw_hdmi_qp_bridge_clear_hdmi_infoframe, 1204 .hdmi_write_hdmi_infoframe = dw_hdmi_qp_bridge_write_hdmi_infoframe, 1205 .hdmi_clear_hdr_drm_infoframe = dw_hdmi_qp_bridge_clear_hdr_drm_infoframe, 1206 .hdmi_write_hdr_drm_infoframe = dw_hdmi_qp_bridge_write_hdr_drm_infoframe, 1207 .hdmi_clear_spd_infoframe = dw_hdmi_qp_bridge_clear_spd_infoframe, 1208 .hdmi_write_spd_infoframe = dw_hdmi_qp_bridge_write_spd_infoframe, 1209 .hdmi_clear_audio_infoframe = dw_hdmi_qp_bridge_clear_audio_infoframe, 1210 .hdmi_write_audio_infoframe = dw_hdmi_qp_bridge_write_audio_infoframe, 1211 .hdmi_audio_startup = dw_hdmi_qp_audio_enable, 1212 .hdmi_audio_shutdown = dw_hdmi_qp_audio_disable, 1213 .hdmi_audio_prepare = dw_hdmi_qp_audio_prepare, 1214 .hdmi_cec_init = dw_hdmi_qp_cec_init, 1215 .hdmi_cec_enable = dw_hdmi_qp_cec_enable, 1216 .hdmi_cec_log_addr = dw_hdmi_qp_cec_log_addr, 1217 .hdmi_cec_transmit = dw_hdmi_qp_cec_transmit, 1218 }; 1219 1220 static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id) 1221 { 1222 struct dw_hdmi_qp *hdmi = dev_id; 1223 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; 1224 u32 stat; 1225 1226 stat = dw_hdmi_qp_read(hdmi, MAINUNIT_1_INT_STATUS); 1227 1228 i2c->stat = stat & (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | 1229 I2CM_NACK_RCVD_IRQ); 1230 1231 if (i2c->stat) { 1232 dw_hdmi_qp_write(hdmi, i2c->stat, MAINUNIT_1_INT_CLEAR); 1233 complete(&i2c->cmp); 1234 } 1235 1236 if (stat) 1237 return IRQ_HANDLED; 1238 1239 return IRQ_NONE; 1240 } 1241 1242 static const struct regmap_config dw_hdmi_qp_regmap_config = { 1243 .reg_bits = 32, 1244 .val_bits = 32, 1245 .reg_stride = 4, 1246 .max_register = EARCRX_1_INT_FORCE, 1247 }; 1248 1249 static void dw_hdmi_qp_init_hw(struct dw_hdmi_qp *hdmi) 1250 { 1251 dw_hdmi_qp_write(hdmi, 0, MAINUNIT_0_INT_MASK_N); 1252 dw_hdmi_qp_write(hdmi, 0, MAINUNIT_1_INT_MASK_N); 1253 dw_hdmi_qp_write(hdmi, hdmi->ref_clk_rate, TIMER_BASE_CONFIG0); 1254 1255 /* Software reset */ 1256 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); 1257 dw_hdmi_qp_write(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); 1258 dw_hdmi_qp_mod(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); 1259 1260 /* Clear DONE and ERROR interrupts */ 1261 dw_hdmi_qp_write(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR, 1262 MAINUNIT_1_INT_CLEAR); 1263 1264 if (hdmi->phy.ops->setup_hpd) 1265 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 1266 } 1267 1268 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, 1269 struct drm_encoder *encoder, 1270 const struct dw_hdmi_qp_plat_data *plat_data) 1271 { 1272 struct device *dev = &pdev->dev; 1273 struct dw_hdmi_qp *hdmi; 1274 void __iomem *regs; 1275 int ret; 1276 1277 if (!plat_data->phy_ops || !plat_data->phy_ops->init || 1278 !plat_data->phy_ops->disable || !plat_data->phy_ops->read_hpd) { 1279 dev_err(dev, "Missing platform PHY ops\n"); 1280 return ERR_PTR(-ENODEV); 1281 } 1282 1283 hdmi = devm_drm_bridge_alloc(dev, struct dw_hdmi_qp, bridge, 1284 &dw_hdmi_qp_bridge_funcs); 1285 if (IS_ERR(hdmi)) 1286 return ERR_CAST(hdmi); 1287 1288 hdmi->dev = dev; 1289 1290 regs = devm_platform_ioremap_resource(pdev, 0); 1291 if (IS_ERR(regs)) 1292 return ERR_CAST(regs); 1293 1294 hdmi->regm = devm_regmap_init_mmio(dev, regs, &dw_hdmi_qp_regmap_config); 1295 if (IS_ERR(hdmi->regm)) { 1296 dev_err(dev, "Failed to configure regmap\n"); 1297 return ERR_CAST(hdmi->regm); 1298 } 1299 1300 hdmi->phy.ops = plat_data->phy_ops; 1301 hdmi->phy.data = plat_data->phy_data; 1302 1303 if (plat_data->ref_clk_rate) { 1304 hdmi->ref_clk_rate = plat_data->ref_clk_rate; 1305 } else { 1306 hdmi->ref_clk_rate = 428571429; 1307 dev_warn(dev, "Set ref_clk_rate to vendor default\n"); 1308 } 1309 1310 dw_hdmi_qp_init_hw(hdmi); 1311 1312 hdmi->main_irq = plat_data->main_irq; 1313 ret = devm_request_threaded_irq(dev, plat_data->main_irq, 1314 dw_hdmi_qp_main_hardirq, NULL, 1315 IRQF_SHARED, dev_name(dev), hdmi); 1316 if (ret) 1317 return ERR_PTR(ret); 1318 1319 hdmi->no_hpd = device_property_read_bool(dev, "no-hpd"); 1320 1321 hdmi->bridge.driver_private = hdmi; 1322 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | 1323 DRM_BRIDGE_OP_EDID | 1324 DRM_BRIDGE_OP_HDMI | 1325 DRM_BRIDGE_OP_HDMI_AUDIO | 1326 DRM_BRIDGE_OP_HDMI_HDR_DRM_INFOFRAME | 1327 DRM_BRIDGE_OP_HDMI_SPD_INFOFRAME; 1328 if (!hdmi->no_hpd) 1329 hdmi->bridge.ops |= DRM_BRIDGE_OP_HPD; 1330 hdmi->bridge.of_node = pdev->dev.of_node; 1331 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 1332 hdmi->bridge.vendor = "Synopsys"; 1333 hdmi->bridge.product = "DW HDMI QP TX"; 1334 1335 if (plat_data->supported_formats) 1336 hdmi->bridge.supported_formats = plat_data->supported_formats; 1337 1338 if (plat_data->max_bpc) 1339 hdmi->bridge.max_bpc = plat_data->max_bpc; 1340 1341 hdmi->bridge.ddc = dw_hdmi_qp_i2c_adapter(hdmi); 1342 if (IS_ERR(hdmi->bridge.ddc)) 1343 return ERR_CAST(hdmi->bridge.ddc); 1344 1345 hdmi->bridge.hdmi_audio_max_i2s_playback_channels = 8; 1346 hdmi->bridge.hdmi_audio_dev = dev; 1347 hdmi->bridge.hdmi_audio_dai_port = 1; 1348 1349 #ifdef CONFIG_DRM_DW_HDMI_QP_CEC 1350 if (plat_data->cec_irq) { 1351 hdmi->bridge.ops |= DRM_BRIDGE_OP_HDMI_CEC_ADAPTER; 1352 hdmi->bridge.hdmi_cec_dev = dev; 1353 hdmi->bridge.hdmi_cec_adapter_name = dev_name(dev); 1354 1355 hdmi->cec = devm_kzalloc(hdmi->dev, sizeof(*hdmi->cec), GFP_KERNEL); 1356 if (!hdmi->cec) 1357 return ERR_PTR(-ENOMEM); 1358 1359 hdmi->cec->irq = plat_data->cec_irq; 1360 } else { 1361 dev_warn(dev, "Disabled CEC support due to missing IRQ\n"); 1362 } 1363 #endif 1364 1365 ret = devm_drm_bridge_add(dev, &hdmi->bridge); 1366 if (ret) 1367 return ERR_PTR(ret); 1368 1369 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 1370 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 1371 if (ret) 1372 return ERR_PTR(ret); 1373 1374 return hdmi; 1375 } 1376 EXPORT_SYMBOL_GPL(dw_hdmi_qp_bind); 1377 1378 void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi) 1379 { 1380 disable_irq(hdmi->main_irq); 1381 } 1382 EXPORT_SYMBOL_GPL(dw_hdmi_qp_suspend); 1383 1384 void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi) 1385 { 1386 dw_hdmi_qp_init_hw(hdmi); 1387 enable_irq(hdmi->main_irq); 1388 } 1389 EXPORT_SYMBOL_GPL(dw_hdmi_qp_resume); 1390 1391 MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>"); 1392 MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@collabora.com>"); 1393 MODULE_DESCRIPTION("DW HDMI QP transmitter library"); 1394 MODULE_LICENSE("GPL"); 1395