1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * DW100 Hardware dewarper 4 * 5 * Copyright 2022 NXP 6 * Author: Xavier Roumegue (xavier.roumegue@oss.nxp.com) 7 * 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/debugfs.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/irqreturn.h> 15 #include <linux/minmax.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 21 #include <media/v4l2-ctrls.h> 22 #include <media/v4l2-device.h> 23 #include <media/v4l2-event.h> 24 #include <media/v4l2-ioctl.h> 25 #include <media/v4l2-mem2mem.h> 26 #include <media/videobuf2-dma-contig.h> 27 28 #include <uapi/linux/dw100.h> 29 30 #include "dw100_regs.h" 31 32 #define DRV_NAME "dw100" 33 34 #define DW100_MIN_W 176u 35 #define DW100_MIN_H 144u 36 #define DW100_MAX_W 4096u 37 #define DW100_MAX_H 3072u 38 #define DW100_ALIGN_W 3 39 #define DW100_ALIGN_H 3 40 41 #define DW100_BLOCK_SIZE 16 42 43 #define DW100_DEF_W 640u 44 #define DW100_DEF_H 480u 45 #define DW100_DEF_LUT_W (DIV_ROUND_UP(DW100_DEF_W, DW100_BLOCK_SIZE) + 1) 46 #define DW100_DEF_LUT_H (DIV_ROUND_UP(DW100_DEF_H, DW100_BLOCK_SIZE) + 1) 47 48 /* 49 * 16 controls have been reserved for this driver for future extension, but 50 * let's limit the related driver allocation to the effective number of controls 51 * in use. 52 */ 53 #define DW100_MAX_CTRLS 1 54 #define DW100_CTRL_DEWARPING_MAP 0 55 56 enum { 57 DW100_QUEUE_SRC = 0, 58 DW100_QUEUE_DST = 1, 59 }; 60 61 enum { 62 DW100_FMT_CAPTURE = BIT(0), 63 DW100_FMT_OUTPUT = BIT(1), 64 }; 65 66 struct dw100_device { 67 struct platform_device *pdev; 68 struct v4l2_m2m_dev *m2m_dev; 69 struct v4l2_device v4l2_dev; 70 struct video_device vfd; 71 struct media_device mdev; 72 /* Video device lock */ 73 struct mutex vfd_mutex; 74 void __iomem *mmio; 75 struct clk_bulk_data *clks; 76 int num_clks; 77 struct dentry *debugfs_root; 78 bool frame_failed; 79 }; 80 81 struct dw100_q_data { 82 struct v4l2_pix_format_mplane pix_fmt; 83 unsigned int sequence; 84 const struct dw100_fmt *fmt; 85 struct v4l2_rect crop; 86 }; 87 88 struct dw100_ctx { 89 struct v4l2_fh fh; 90 struct dw100_device *dw_dev; 91 struct v4l2_ctrl_handler hdl; 92 struct v4l2_ctrl *ctrls[DW100_MAX_CTRLS]; 93 /* per context m2m queue lock */ 94 struct mutex vq_mutex; 95 96 /* Look Up Table for pixel remapping */ 97 unsigned int *map; 98 dma_addr_t map_dma; 99 size_t map_size; 100 unsigned int map_width; 101 unsigned int map_height; 102 bool user_map_is_set; 103 bool user_map_is_dirty; 104 105 /* Source and destination queue data */ 106 struct dw100_q_data q_data[2]; 107 }; 108 109 static const struct v4l2_frmsize_stepwise dw100_frmsize_stepwise = { 110 .min_width = DW100_MIN_W, 111 .min_height = DW100_MIN_H, 112 .max_width = DW100_MAX_W, 113 .max_height = DW100_MAX_H, 114 .step_width = 1UL << DW100_ALIGN_W, 115 .step_height = 1UL << DW100_ALIGN_H, 116 }; 117 118 static const struct dw100_fmt { 119 u32 fourcc; 120 u32 types; 121 u32 reg_format; 122 bool reg_swap_uv; 123 } formats[] = { 124 { 125 .fourcc = V4L2_PIX_FMT_NV16, 126 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, 127 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP, 128 .reg_swap_uv = false, 129 }, { 130 .fourcc = V4L2_PIX_FMT_NV16M, 131 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, 132 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP, 133 .reg_swap_uv = false, 134 }, { 135 .fourcc = V4L2_PIX_FMT_NV61, 136 .types = DW100_FMT_CAPTURE, 137 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP, 138 .reg_swap_uv = true, 139 }, { 140 .fourcc = V4L2_PIX_FMT_NV61M, 141 .types = DW100_FMT_CAPTURE, 142 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP, 143 .reg_swap_uv = true, 144 }, { 145 .fourcc = V4L2_PIX_FMT_YUYV, 146 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, 147 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED, 148 .reg_swap_uv = false, 149 }, { 150 .fourcc = V4L2_PIX_FMT_UYVY, 151 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, 152 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED, 153 .reg_swap_uv = true, 154 }, { 155 .fourcc = V4L2_PIX_FMT_NV12, 156 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, 157 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP, 158 .reg_swap_uv = false, 159 }, { 160 .fourcc = V4L2_PIX_FMT_NV12M, 161 .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, 162 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP, 163 .reg_swap_uv = false, 164 }, { 165 .fourcc = V4L2_PIX_FMT_NV21, 166 .types = DW100_FMT_CAPTURE, 167 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP, 168 .reg_swap_uv = true, 169 }, { 170 .fourcc = V4L2_PIX_FMT_NV21M, 171 .types = DW100_FMT_CAPTURE, 172 .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP, 173 .reg_swap_uv = true, 174 }, 175 }; 176 177 static inline int to_dw100_fmt_type(enum v4l2_buf_type type) 178 { 179 if (V4L2_TYPE_IS_OUTPUT(type)) 180 return DW100_FMT_OUTPUT; 181 else 182 return DW100_FMT_CAPTURE; 183 } 184 185 static const struct dw100_fmt *dw100_find_pixel_format(u32 pixel_format, 186 int fmt_type) 187 { 188 unsigned int i; 189 190 for (i = 0; i < ARRAY_SIZE(formats); i++) { 191 const struct dw100_fmt *fmt = &formats[i]; 192 193 if (fmt->fourcc == pixel_format && fmt->types & fmt_type) 194 return fmt; 195 } 196 197 return NULL; 198 } 199 200 static const struct dw100_fmt *dw100_find_format(struct v4l2_format *f) 201 { 202 return dw100_find_pixel_format(f->fmt.pix_mp.pixelformat, 203 to_dw100_fmt_type(f->type)); 204 } 205 206 static inline u32 dw100_read(struct dw100_device *dw_dev, u32 reg) 207 { 208 return readl(dw_dev->mmio + reg); 209 } 210 211 static inline void dw100_write(struct dw100_device *dw_dev, u32 reg, u32 val) 212 { 213 writel(val, dw_dev->mmio + reg); 214 } 215 216 static inline int dw100_dump_regs(struct seq_file *m) 217 { 218 struct dw100_device *dw_dev = m->private; 219 #define __DECLARE_REG(x) { #x, x } 220 unsigned int i; 221 static const struct reg_desc { 222 const char * const name; 223 unsigned int addr; 224 } dw100_regs[] = { 225 __DECLARE_REG(DW100_DEWARP_ID), 226 __DECLARE_REG(DW100_DEWARP_CTRL), 227 __DECLARE_REG(DW100_MAP_LUT_ADDR), 228 __DECLARE_REG(DW100_MAP_LUT_SIZE), 229 __DECLARE_REG(DW100_MAP_LUT_ADDR2), 230 __DECLARE_REG(DW100_MAP_LUT_SIZE2), 231 __DECLARE_REG(DW100_SRC_IMG_Y_BASE), 232 __DECLARE_REG(DW100_SRC_IMG_UV_BASE), 233 __DECLARE_REG(DW100_SRC_IMG_SIZE), 234 __DECLARE_REG(DW100_SRC_IMG_STRIDE), 235 __DECLARE_REG(DW100_DST_IMG_Y_BASE), 236 __DECLARE_REG(DW100_DST_IMG_UV_BASE), 237 __DECLARE_REG(DW100_DST_IMG_SIZE), 238 __DECLARE_REG(DW100_DST_IMG_STRIDE), 239 __DECLARE_REG(DW100_DST_IMG_Y_SIZE1), 240 __DECLARE_REG(DW100_DST_IMG_UV_SIZE1), 241 __DECLARE_REG(DW100_SRC_IMG_Y_BASE2), 242 __DECLARE_REG(DW100_SRC_IMG_UV_BASE2), 243 __DECLARE_REG(DW100_SRC_IMG_SIZE2), 244 __DECLARE_REG(DW100_SRC_IMG_STRIDE2), 245 __DECLARE_REG(DW100_DST_IMG_Y_BASE2), 246 __DECLARE_REG(DW100_DST_IMG_UV_BASE2), 247 __DECLARE_REG(DW100_DST_IMG_SIZE2), 248 __DECLARE_REG(DW100_DST_IMG_STRIDE2), 249 __DECLARE_REG(DW100_DST_IMG_Y_SIZE2), 250 __DECLARE_REG(DW100_DST_IMG_UV_SIZE2), 251 __DECLARE_REG(DW100_SWAP_CONTROL), 252 __DECLARE_REG(DW100_VERTICAL_SPLIT_LINE), 253 __DECLARE_REG(DW100_HORIZON_SPLIT_LINE), 254 __DECLARE_REG(DW100_SCALE_FACTOR), 255 __DECLARE_REG(DW100_ROI_START), 256 __DECLARE_REG(DW100_BOUNDARY_PIXEL), 257 __DECLARE_REG(DW100_INTERRUPT_STATUS), 258 __DECLARE_REG(DW100_BUS_CTRL), 259 __DECLARE_REG(DW100_BUS_CTRL1), 260 __DECLARE_REG(DW100_BUS_TIME_OUT_CYCLE), 261 }; 262 263 for (i = 0; i < ARRAY_SIZE(dw100_regs); i++) 264 seq_printf(m, "%s: %#x\n", dw100_regs[i].name, 265 dw100_read(dw_dev, dw100_regs[i].addr)); 266 267 return 0; 268 } 269 270 static inline struct dw100_ctx *dw100_file2ctx(struct file *file) 271 { 272 return container_of(file_to_v4l2_fh(file), struct dw100_ctx, fh); 273 } 274 275 static struct dw100_q_data *dw100_get_q_data(struct dw100_ctx *ctx, 276 enum v4l2_buf_type type) 277 { 278 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) 279 return &ctx->q_data[DW100_QUEUE_SRC]; 280 else 281 return &ctx->q_data[DW100_QUEUE_DST]; 282 } 283 284 static u32 dw100_get_n_vertices_from_length(u32 length) 285 { 286 return DIV_ROUND_UP(length, DW100_BLOCK_SIZE) + 1; 287 } 288 289 static u16 dw100_map_convert_to_uq12_4(u32 a) 290 { 291 return (u16)((a & 0xfff) << 4); 292 } 293 294 static u32 dw100_map_format_coordinates(u16 xq, u16 yq) 295 { 296 return (u32)((yq << 16) | xq); 297 } 298 299 static void dw100_update_mapping(struct dw100_ctx *ctx) 300 { 301 struct v4l2_ctrl *ctrl = ctx->ctrls[DW100_CTRL_DEWARPING_MAP]; 302 303 if (!ctx->user_map_is_dirty) 304 return; 305 306 memcpy(ctx->map, ctrl->p_cur.p_u32, ctx->map_size); 307 ctx->user_map_is_dirty = false; 308 } 309 310 /* 311 * Create the dewarp map used by the hardware from the V4L2 control values which 312 * have been initialized with an identity map or set by the application. 313 */ 314 static int dw100_create_mapping(struct dw100_ctx *ctx) 315 { 316 if (ctx->map) 317 dma_free_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size, 318 ctx->map, ctx->map_dma); 319 320 ctx->map = dma_alloc_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size, 321 &ctx->map_dma, GFP_KERNEL); 322 323 if (!ctx->map) 324 return -ENOMEM; 325 326 ctx->user_map_is_dirty = true; 327 dw100_update_mapping(ctx); 328 329 dev_dbg(&ctx->dw_dev->pdev->dev, 330 "%ux%u %s mapping created (d:%pad-c:%p) for stream %ux%u->%ux%u\n", 331 ctx->map_width, ctx->map_height, 332 ctx->user_map_is_set ? "user" : "identity", 333 &ctx->map_dma, ctx->map, 334 ctx->q_data[DW100_QUEUE_SRC].pix_fmt.width, 335 ctx->q_data[DW100_QUEUE_DST].pix_fmt.height, 336 ctx->q_data[DW100_QUEUE_SRC].pix_fmt.width, 337 ctx->q_data[DW100_QUEUE_DST].pix_fmt.height); 338 339 return 0; 340 } 341 342 static void dw100_destroy_mapping(struct dw100_ctx *ctx) 343 { 344 if (ctx->map) { 345 dma_free_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size, 346 ctx->map, ctx->map_dma); 347 ctx->map = NULL; 348 } 349 } 350 351 static int dw100_s_ctrl(struct v4l2_ctrl *ctrl) 352 { 353 struct dw100_ctx *ctx = 354 container_of(ctrl->handler, struct dw100_ctx, hdl); 355 356 switch (ctrl->id) { 357 case V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP: 358 ctx->user_map_is_set = true; 359 ctx->user_map_is_dirty = true; 360 break; 361 } 362 363 return 0; 364 } 365 366 static const struct v4l2_ctrl_ops dw100_ctrl_ops = { 367 .s_ctrl = dw100_s_ctrl, 368 }; 369 370 /* 371 * Initialize the dewarping map with an identity mapping. 372 * 373 * A 16 pixels cell size grid is mapped on the destination image. 374 * The last cells width/height might be lesser than 16 if the destination image 375 * width/height is not divisible by 16. This dewarping grid map specifies the 376 * source image pixel location (x, y) on each grid intersection point. 377 * Bilinear interpolation is used to compute inner cell points locations. 378 * 379 * The coordinates are saved in UQ12.4 fixed point format. 380 */ 381 static void dw100_ctrl_dewarping_map_init(const struct v4l2_ctrl *ctrl, 382 u32 from_idx, 383 union v4l2_ctrl_ptr ptr) 384 { 385 struct dw100_ctx *ctx = 386 container_of(ctrl->handler, struct dw100_ctx, hdl); 387 388 u32 sw, sh, mw, mh, idx; 389 u16 qx, qy, qdx, qdy, qsh, qsw; 390 u32 *map = ctrl->p_cur.p_u32; 391 392 sw = ctx->q_data[DW100_QUEUE_SRC].pix_fmt.width; 393 sh = ctx->q_data[DW100_QUEUE_SRC].pix_fmt.height; 394 395 mw = ctrl->dims[0]; 396 mh = ctrl->dims[1]; 397 398 qsw = dw100_map_convert_to_uq12_4(sw); 399 qsh = dw100_map_convert_to_uq12_4(sh); 400 qdx = qsw / (mw - 1); 401 qdy = qsh / (mh - 1); 402 403 ctx->map_width = mw; 404 ctx->map_height = mh; 405 ctx->map_size = mh * mw * sizeof(u32); 406 407 for (idx = from_idx; idx < ctrl->elems; idx++) { 408 qy = min_t(u32, (idx / mw) * qdy, qsh); 409 qx = min_t(u32, (idx % mw) * qdx, qsw); 410 map[idx] = dw100_map_format_coordinates(qx, qy); 411 } 412 413 ctx->user_map_is_set = false; 414 ctx->user_map_is_dirty = true; 415 } 416 417 static const struct v4l2_ctrl_type_ops dw100_ctrl_type_ops = { 418 .init = dw100_ctrl_dewarping_map_init, 419 .validate = v4l2_ctrl_type_op_validate, 420 .log = v4l2_ctrl_type_op_log, 421 .equal = v4l2_ctrl_type_op_equal, 422 }; 423 424 static const struct v4l2_ctrl_config controls[] = { 425 [DW100_CTRL_DEWARPING_MAP] = { 426 .ops = &dw100_ctrl_ops, 427 .type_ops = &dw100_ctrl_type_ops, 428 .id = V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP, 429 .name = "Dewarping Vertex Map", 430 .type = V4L2_CTRL_TYPE_U32, 431 .min = 0x00000000, 432 .max = 0xffffffff, 433 .step = 1, 434 .def = 0, 435 .dims = { DW100_DEF_LUT_W, DW100_DEF_LUT_H }, 436 }, 437 }; 438 439 static int dw100_queue_setup(struct vb2_queue *vq, 440 unsigned int *nbuffers, unsigned int *nplanes, 441 unsigned int sizes[], struct device *alloc_devs[]) 442 { 443 struct dw100_ctx *ctx = vb2_get_drv_priv(vq); 444 const struct v4l2_pix_format_mplane *format; 445 unsigned int i; 446 447 format = &dw100_get_q_data(ctx, vq->type)->pix_fmt; 448 449 if (*nplanes) { 450 if (*nplanes != format->num_planes) 451 return -EINVAL; 452 453 for (i = 0; i < *nplanes; ++i) { 454 if (sizes[i] < format->plane_fmt[i].sizeimage) 455 return -EINVAL; 456 } 457 458 return 0; 459 } 460 461 *nplanes = format->num_planes; 462 463 for (i = 0; i < format->num_planes; ++i) 464 sizes[i] = format->plane_fmt[i].sizeimage; 465 466 return 0; 467 } 468 469 static int dw100_buf_out_validate(struct vb2_buffer *vb) 470 { 471 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 472 473 vbuf->field = V4L2_FIELD_NONE; 474 475 return 0; 476 } 477 478 static int dw100_buf_prepare(struct vb2_buffer *vb) 479 { 480 unsigned int i; 481 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 482 struct dw100_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 483 struct dw100_device *dw_dev = ctx->dw_dev; 484 const struct v4l2_pix_format_mplane *pix_fmt = 485 &dw100_get_q_data(ctx, vb->vb2_queue->type)->pix_fmt; 486 487 if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) { 488 if (vbuf->field != V4L2_FIELD_NONE) { 489 dev_dbg(&dw_dev->pdev->dev, "%x field isn't supported\n", 490 vbuf->field); 491 return -EINVAL; 492 } 493 } 494 495 for (i = 0; i < pix_fmt->num_planes; i++) { 496 unsigned long size = pix_fmt->plane_fmt[i].sizeimage; 497 498 if (vb2_plane_size(vb, i) < size) { 499 dev_dbg(&dw_dev->pdev->dev, 500 "User buffer too small (%lu < %lu)\n", 501 vb2_plane_size(vb, i), size); 502 return -EINVAL; 503 } 504 505 vb2_set_plane_payload(vb, i, size); 506 } 507 508 return 0; 509 } 510 511 static void dw100_buf_queue(struct vb2_buffer *vb) 512 { 513 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 514 struct dw100_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 515 516 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); 517 } 518 519 static void dw100_buf_request_complete(struct vb2_buffer *vb) 520 { 521 struct dw100_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 522 523 v4l2_ctrl_request_complete(vb->req_obj.req, &ctx->hdl); 524 } 525 526 static void dw100_return_all_buffers(struct vb2_queue *q, 527 enum vb2_buffer_state state) 528 { 529 struct dw100_ctx *ctx = vb2_get_drv_priv(q); 530 struct vb2_v4l2_buffer *vbuf; 531 532 for (;;) { 533 if (V4L2_TYPE_IS_OUTPUT(q->type)) 534 vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); 535 else 536 vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); 537 if (!vbuf) 538 return; 539 v4l2_m2m_buf_done(vbuf, state); 540 } 541 } 542 543 static int dw100_start_streaming(struct vb2_queue *q, unsigned int count) 544 { 545 struct dw100_ctx *ctx = vb2_get_drv_priv(q); 546 struct dw100_q_data *q_data = dw100_get_q_data(ctx, q->type); 547 int ret; 548 549 q_data->sequence = 0; 550 551 ret = dw100_create_mapping(ctx); 552 if (ret) 553 goto err; 554 555 ret = pm_runtime_resume_and_get(&ctx->dw_dev->pdev->dev); 556 if (ret) { 557 dw100_destroy_mapping(ctx); 558 goto err; 559 } 560 561 return 0; 562 err: 563 dw100_return_all_buffers(q, VB2_BUF_STATE_QUEUED); 564 return ret; 565 } 566 567 static void dw100_stop_streaming(struct vb2_queue *q) 568 { 569 struct dw100_ctx *ctx = vb2_get_drv_priv(q); 570 571 dw100_return_all_buffers(q, VB2_BUF_STATE_ERROR); 572 573 pm_runtime_put_sync(&ctx->dw_dev->pdev->dev); 574 575 dw100_destroy_mapping(ctx); 576 } 577 578 static const struct vb2_ops dw100_qops = { 579 .queue_setup = dw100_queue_setup, 580 .buf_out_validate = dw100_buf_out_validate, 581 .buf_prepare = dw100_buf_prepare, 582 .buf_queue = dw100_buf_queue, 583 .start_streaming = dw100_start_streaming, 584 .stop_streaming = dw100_stop_streaming, 585 .buf_request_complete = dw100_buf_request_complete, 586 }; 587 588 static int dw100_m2m_queue_init(void *priv, struct vb2_queue *src_vq, 589 struct vb2_queue *dst_vq) 590 { 591 struct dw100_ctx *ctx = priv; 592 int ret; 593 594 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 595 src_vq->io_modes = VB2_MMAP | VB2_DMABUF; 596 src_vq->drv_priv = ctx; 597 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); 598 src_vq->ops = &dw100_qops; 599 src_vq->mem_ops = &vb2_dma_contig_memops; 600 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 601 src_vq->lock = &ctx->vq_mutex; 602 src_vq->dev = ctx->dw_dev->v4l2_dev.dev; 603 src_vq->supports_requests = true; 604 605 ret = vb2_queue_init(src_vq); 606 if (ret) 607 return ret; 608 609 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 610 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; 611 dst_vq->drv_priv = ctx; 612 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); 613 dst_vq->ops = &dw100_qops; 614 dst_vq->mem_ops = &vb2_dma_contig_memops; 615 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 616 dst_vq->lock = &ctx->vq_mutex; 617 dst_vq->dev = ctx->dw_dev->v4l2_dev.dev; 618 619 return vb2_queue_init(dst_vq); 620 } 621 622 static int dw100_open(struct file *file) 623 { 624 struct dw100_device *dw_dev = video_drvdata(file); 625 struct dw100_ctx *ctx; 626 struct v4l2_ctrl_handler *hdl; 627 struct v4l2_pix_format_mplane *pix_fmt; 628 int ret, i; 629 630 ctx = kzalloc_obj(*ctx); 631 if (!ctx) 632 return -ENOMEM; 633 634 mutex_init(&ctx->vq_mutex); 635 v4l2_fh_init(&ctx->fh, video_devdata(file)); 636 ctx->dw_dev = dw_dev; 637 638 ctx->q_data[DW100_QUEUE_SRC].fmt = &formats[0]; 639 640 pix_fmt = &ctx->q_data[DW100_QUEUE_SRC].pix_fmt; 641 pix_fmt->field = V4L2_FIELD_NONE; 642 pix_fmt->colorspace = V4L2_COLORSPACE_REC709; 643 pix_fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix_fmt->colorspace); 644 pix_fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(pix_fmt->colorspace); 645 pix_fmt->quantization = 646 V4L2_MAP_QUANTIZATION_DEFAULT(false, pix_fmt->colorspace, 647 pix_fmt->ycbcr_enc); 648 649 v4l2_fill_pixfmt_mp(pix_fmt, formats[0].fourcc, DW100_DEF_W, DW100_DEF_H); 650 651 ctx->q_data[DW100_QUEUE_SRC].crop.top = 0; 652 ctx->q_data[DW100_QUEUE_SRC].crop.left = 0; 653 ctx->q_data[DW100_QUEUE_SRC].crop.width = DW100_DEF_W; 654 ctx->q_data[DW100_QUEUE_SRC].crop.height = DW100_DEF_H; 655 656 ctx->q_data[DW100_QUEUE_DST] = ctx->q_data[DW100_QUEUE_SRC]; 657 658 hdl = &ctx->hdl; 659 v4l2_ctrl_handler_init(hdl, ARRAY_SIZE(controls)); 660 for (i = 0; i < ARRAY_SIZE(controls); i++) { 661 ctx->ctrls[i] = v4l2_ctrl_new_custom(hdl, &controls[i], NULL); 662 if (hdl->error) { 663 dev_err(&ctx->dw_dev->pdev->dev, 664 "Adding control (%d) failed\n", i); 665 ret = hdl->error; 666 goto err; 667 } 668 } 669 ctx->fh.ctrl_handler = hdl; 670 671 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dw_dev->m2m_dev, 672 ctx, &dw100_m2m_queue_init); 673 674 if (IS_ERR(ctx->fh.m2m_ctx)) { 675 ret = PTR_ERR(ctx->fh.m2m_ctx); 676 goto err; 677 } 678 679 v4l2_fh_add(&ctx->fh, file); 680 681 return 0; 682 683 err: 684 v4l2_ctrl_handler_free(hdl); 685 v4l2_fh_exit(&ctx->fh); 686 mutex_destroy(&ctx->vq_mutex); 687 kfree(ctx); 688 689 return ret; 690 } 691 692 static int dw100_release(struct file *file) 693 { 694 struct dw100_ctx *ctx = dw100_file2ctx(file); 695 696 v4l2_fh_del(&ctx->fh, file); 697 v4l2_fh_exit(&ctx->fh); 698 v4l2_ctrl_handler_free(&ctx->hdl); 699 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); 700 mutex_destroy(&ctx->vq_mutex); 701 kfree(ctx); 702 703 return 0; 704 } 705 706 static const struct v4l2_file_operations dw100_fops = { 707 .owner = THIS_MODULE, 708 .open = dw100_open, 709 .release = dw100_release, 710 .poll = v4l2_m2m_fop_poll, 711 .unlocked_ioctl = video_ioctl2, 712 .mmap = v4l2_m2m_fop_mmap, 713 }; 714 715 static int dw100_querycap(struct file *file, void *priv, 716 struct v4l2_capability *cap) 717 { 718 strscpy(cap->driver, DRV_NAME, sizeof(cap->driver)); 719 strscpy(cap->card, "DW100 dewarper", sizeof(cap->card)); 720 721 return 0; 722 } 723 724 static int dw100_enum_fmt_vid(struct file *file, void *priv, 725 struct v4l2_fmtdesc *f) 726 { 727 int i, num = 0; 728 729 for (i = 0; i < ARRAY_SIZE(formats); i++) { 730 if (formats[i].types & to_dw100_fmt_type(f->type)) { 731 if (num == f->index) { 732 f->pixelformat = formats[i].fourcc; 733 return 0; 734 } 735 ++num; 736 } 737 } 738 739 return -EINVAL; 740 } 741 742 static int dw100_enum_framesizes(struct file *file, void *priv, 743 struct v4l2_frmsizeenum *fsize) 744 { 745 const struct dw100_fmt *fmt; 746 747 if (fsize->index) 748 return -EINVAL; 749 750 fmt = dw100_find_pixel_format(fsize->pixel_format, 751 DW100_FMT_OUTPUT | DW100_FMT_CAPTURE); 752 if (!fmt) 753 return -EINVAL; 754 755 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; 756 fsize->stepwise = dw100_frmsize_stepwise; 757 758 return 0; 759 } 760 761 static int dw100_g_fmt_vid(struct file *file, void *priv, struct v4l2_format *f) 762 { 763 struct dw100_ctx *ctx = dw100_file2ctx(file); 764 struct dw100_q_data *q_data; 765 766 q_data = dw100_get_q_data(ctx, f->type); 767 768 f->fmt.pix_mp = q_data->pix_fmt; 769 770 return 0; 771 } 772 773 static int dw100_try_fmt(struct file *file, struct v4l2_format *f) 774 { 775 struct dw100_ctx *ctx = dw100_file2ctx(file); 776 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp; 777 const struct dw100_fmt *fmt; 778 779 fmt = dw100_find_format(f); 780 if (!fmt) { 781 fmt = &formats[0]; 782 pix->pixelformat = fmt->fourcc; 783 } 784 785 v4l2_apply_frmsize_constraints(&pix->width, &pix->height, 786 &dw100_frmsize_stepwise); 787 788 v4l2_fill_pixfmt_mp(pix, fmt->fourcc, pix->width, pix->height); 789 790 pix->field = V4L2_FIELD_NONE; 791 792 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { 793 if (pix->colorspace == V4L2_COLORSPACE_DEFAULT) 794 pix->colorspace = V4L2_COLORSPACE_REC709; 795 if (pix->xfer_func == V4L2_XFER_FUNC_DEFAULT) 796 pix->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix->colorspace); 797 if (pix->ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT) 798 pix->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(pix->colorspace); 799 if (pix->quantization == V4L2_QUANTIZATION_DEFAULT) 800 pix->quantization = 801 V4L2_MAP_QUANTIZATION_DEFAULT(false, 802 pix->colorspace, 803 pix->ycbcr_enc); 804 } else { 805 /* 806 * The DW100 can't perform colorspace conversion, the colorspace 807 * on the capture queue must be identical to the output queue. 808 */ 809 const struct dw100_q_data *q_data = 810 dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 811 812 pix->colorspace = q_data->pix_fmt.colorspace; 813 pix->xfer_func = q_data->pix_fmt.xfer_func; 814 pix->ycbcr_enc = q_data->pix_fmt.ycbcr_enc; 815 pix->quantization = q_data->pix_fmt.quantization; 816 } 817 818 return 0; 819 } 820 821 static int dw100_s_fmt(struct dw100_ctx *ctx, struct v4l2_format *f) 822 { 823 struct dw100_q_data *q_data; 824 struct vb2_queue *vq; 825 826 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); 827 828 q_data = dw100_get_q_data(ctx, f->type); 829 if (!q_data) 830 return -EINVAL; 831 832 if (vb2_is_busy(vq)) { 833 dev_dbg(&ctx->dw_dev->pdev->dev, "%s queue busy\n", __func__); 834 return -EBUSY; 835 } 836 837 q_data->fmt = dw100_find_format(f); 838 q_data->pix_fmt = f->fmt.pix_mp; 839 q_data->crop.top = 0; 840 q_data->crop.left = 0; 841 q_data->crop.width = f->fmt.pix_mp.width; 842 q_data->crop.height = f->fmt.pix_mp.height; 843 844 /* Propagate buffers encoding */ 845 846 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { 847 struct dw100_q_data *dst_q_data = 848 dw100_get_q_data(ctx, 849 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 850 851 dst_q_data->pix_fmt.colorspace = q_data->pix_fmt.colorspace; 852 dst_q_data->pix_fmt.ycbcr_enc = q_data->pix_fmt.ycbcr_enc; 853 dst_q_data->pix_fmt.quantization = q_data->pix_fmt.quantization; 854 dst_q_data->pix_fmt.xfer_func = q_data->pix_fmt.xfer_func; 855 } 856 857 dev_dbg(&ctx->dw_dev->pdev->dev, 858 "Setting format for type %u, wxh: %ux%u, fmt: %p4cc\n", 859 f->type, q_data->pix_fmt.width, q_data->pix_fmt.height, 860 &q_data->pix_fmt.pixelformat); 861 862 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { 863 int ret; 864 u32 dims[V4L2_CTRL_MAX_DIMS] = {}; 865 struct v4l2_ctrl *ctrl = ctx->ctrls[DW100_CTRL_DEWARPING_MAP]; 866 867 dims[0] = dw100_get_n_vertices_from_length(q_data->pix_fmt.width); 868 dims[1] = dw100_get_n_vertices_from_length(q_data->pix_fmt.height); 869 870 ret = v4l2_ctrl_modify_dimensions(ctrl, dims); 871 872 if (ret) { 873 dev_err(&ctx->dw_dev->pdev->dev, 874 "Modifying LUT dimensions failed with error %d\n", 875 ret); 876 return ret; 877 } 878 } 879 880 return 0; 881 } 882 883 static int dw100_try_fmt_vid_cap(struct file *file, void *priv, 884 struct v4l2_format *f) 885 { 886 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) 887 return -EINVAL; 888 889 return dw100_try_fmt(file, f); 890 } 891 892 static int dw100_s_fmt_vid_cap(struct file *file, void *priv, 893 struct v4l2_format *f) 894 { 895 struct dw100_ctx *ctx = dw100_file2ctx(file); 896 int ret; 897 898 ret = dw100_try_fmt_vid_cap(file, priv, f); 899 if (ret) 900 return ret; 901 902 ret = dw100_s_fmt(ctx, f); 903 if (ret) 904 return ret; 905 906 return 0; 907 } 908 909 static int dw100_try_fmt_vid_out(struct file *file, void *priv, 910 struct v4l2_format *f) 911 { 912 if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) 913 return -EINVAL; 914 915 return dw100_try_fmt(file, f); 916 } 917 918 static int dw100_s_fmt_vid_out(struct file *file, void *priv, 919 struct v4l2_format *f) 920 { 921 struct dw100_ctx *ctx = dw100_file2ctx(file); 922 int ret; 923 924 ret = dw100_try_fmt_vid_out(file, priv, f); 925 if (ret) 926 return ret; 927 928 ret = dw100_s_fmt(ctx, f); 929 if (ret) 930 return ret; 931 932 return 0; 933 } 934 935 static int dw100_g_selection(struct file *file, void *fh, 936 struct v4l2_selection *sel) 937 { 938 struct dw100_ctx *ctx = dw100_file2ctx(file); 939 struct dw100_q_data *src_q_data; 940 941 if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) 942 return -EINVAL; 943 944 src_q_data = dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 945 946 switch (sel->target) { 947 case V4L2_SEL_TGT_CROP_DEFAULT: 948 case V4L2_SEL_TGT_CROP_BOUNDS: 949 sel->r.top = 0; 950 sel->r.left = 0; 951 sel->r.width = src_q_data->pix_fmt.width; 952 sel->r.height = src_q_data->pix_fmt.height; 953 break; 954 case V4L2_SEL_TGT_CROP: 955 sel->r.top = src_q_data->crop.top; 956 sel->r.left = src_q_data->crop.left; 957 sel->r.width = src_q_data->crop.width; 958 sel->r.height = src_q_data->crop.height; 959 break; 960 default: 961 return -EINVAL; 962 } 963 964 return 0; 965 } 966 967 static int dw100_s_selection(struct file *file, void *fh, 968 struct v4l2_selection *sel) 969 { 970 struct dw100_ctx *ctx = dw100_file2ctx(file); 971 struct dw100_q_data *src_q_data; 972 u32 qscalex, qscaley, qscale; 973 int x, y, w, h; 974 unsigned int wframe, hframe; 975 976 if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) 977 return -EINVAL; 978 979 src_q_data = dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 980 981 dev_dbg(&ctx->dw_dev->pdev->dev, 982 ">>> Buffer Type: %u Target: %u Rect: (%d,%d)/%ux%u\n", 983 sel->type, sel->target, 984 sel->r.left, sel->r.top, sel->r.width, sel->r.height); 985 986 switch (sel->target) { 987 case V4L2_SEL_TGT_CROP: 988 wframe = src_q_data->pix_fmt.width; 989 hframe = src_q_data->pix_fmt.height; 990 991 sel->r.top = clamp_t(int, sel->r.top, 0, hframe - DW100_MIN_H); 992 sel->r.left = clamp_t(int, sel->r.left, 0, wframe - DW100_MIN_W); 993 sel->r.height = 994 clamp(sel->r.height, DW100_MIN_H, hframe - sel->r.top); 995 sel->r.width = 996 clamp(sel->r.width, DW100_MIN_W, wframe - sel->r.left); 997 998 /* UQ16.16 for float operations */ 999 qscalex = (sel->r.width << 16) / wframe; 1000 qscaley = (sel->r.height << 16) / hframe; 1001 y = sel->r.top; 1002 x = sel->r.left; 1003 if (qscalex == qscaley) { 1004 qscale = qscalex; 1005 } else { 1006 switch (sel->flags) { 1007 case 0: 1008 qscale = (qscalex + qscaley) / 2; 1009 break; 1010 case V4L2_SEL_FLAG_GE: 1011 qscale = max(qscaley, qscalex); 1012 break; 1013 case V4L2_SEL_FLAG_LE: 1014 qscale = min(qscaley, qscalex); 1015 break; 1016 case V4L2_SEL_FLAG_LE | V4L2_SEL_FLAG_GE: 1017 return -ERANGE; 1018 default: 1019 return -EINVAL; 1020 } 1021 } 1022 1023 w = (u32)((((u64)wframe << 16) * qscale) >> 32); 1024 h = (u32)((((u64)hframe << 16) * qscale) >> 32); 1025 x = x + (sel->r.width - w) / 2; 1026 y = y + (sel->r.height - h) / 2; 1027 x = min(wframe - w, (unsigned int)max(0, x)); 1028 y = min(hframe - h, (unsigned int)max(0, y)); 1029 1030 sel->r.top = y; 1031 sel->r.left = x; 1032 sel->r.width = w; 1033 sel->r.height = h; 1034 1035 src_q_data->crop.top = sel->r.top; 1036 src_q_data->crop.left = sel->r.left; 1037 src_q_data->crop.width = sel->r.width; 1038 src_q_data->crop.height = sel->r.height; 1039 break; 1040 1041 default: 1042 return -EINVAL; 1043 } 1044 1045 dev_dbg(&ctx->dw_dev->pdev->dev, 1046 "<<< Buffer Type: %u Target: %u Rect: (%d,%d)/%ux%u\n", 1047 sel->type, sel->target, 1048 sel->r.left, sel->r.top, sel->r.width, sel->r.height); 1049 1050 return 0; 1051 } 1052 1053 static const struct v4l2_ioctl_ops dw100_ioctl_ops = { 1054 .vidioc_querycap = dw100_querycap, 1055 1056 .vidioc_enum_fmt_vid_cap = dw100_enum_fmt_vid, 1057 .vidioc_enum_framesizes = dw100_enum_framesizes, 1058 .vidioc_g_fmt_vid_cap_mplane = dw100_g_fmt_vid, 1059 .vidioc_try_fmt_vid_cap_mplane = dw100_try_fmt_vid_cap, 1060 .vidioc_s_fmt_vid_cap_mplane = dw100_s_fmt_vid_cap, 1061 1062 .vidioc_enum_fmt_vid_out = dw100_enum_fmt_vid, 1063 .vidioc_g_fmt_vid_out_mplane = dw100_g_fmt_vid, 1064 .vidioc_try_fmt_vid_out_mplane = dw100_try_fmt_vid_out, 1065 .vidioc_s_fmt_vid_out_mplane = dw100_s_fmt_vid_out, 1066 1067 .vidioc_g_selection = dw100_g_selection, 1068 .vidioc_s_selection = dw100_s_selection, 1069 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, 1070 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, 1071 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, 1072 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, 1073 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, 1074 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, 1075 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, 1076 1077 .vidioc_streamon = v4l2_m2m_ioctl_streamon, 1078 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, 1079 1080 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1081 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1082 }; 1083 1084 static void dw100_job_finish(struct dw100_device *dw_dev, bool with_error) 1085 { 1086 struct dw100_ctx *curr_ctx; 1087 enum vb2_buffer_state buf_state; 1088 1089 curr_ctx = v4l2_m2m_get_curr_priv(dw_dev->m2m_dev); 1090 1091 if (!curr_ctx) { 1092 dev_err(&dw_dev->pdev->dev, 1093 "Instance released before the end of transaction\n"); 1094 return; 1095 } 1096 1097 if (likely(!with_error)) 1098 buf_state = VB2_BUF_STATE_DONE; 1099 else 1100 buf_state = VB2_BUF_STATE_ERROR; 1101 1102 dev_dbg(&dw_dev->pdev->dev, "Finishing transaction with%s error(s)\n", 1103 with_error ? "" : "out"); 1104 1105 v4l2_m2m_buf_done_and_job_finish(dw_dev->m2m_dev, curr_ctx->fh.m2m_ctx, 1106 buf_state); 1107 } 1108 1109 static void dw100_hw_reset(struct dw100_device *dw_dev) 1110 { 1111 u32 val; 1112 1113 val = dw100_read(dw_dev, DW100_DEWARP_CTRL); 1114 val |= DW100_DEWARP_CTRL_ENABLE; 1115 val |= DW100_DEWARP_CTRL_SOFT_RESET; 1116 dw100_write(dw_dev, DW100_DEWARP_CTRL, val); 1117 val &= ~DW100_DEWARP_CTRL_SOFT_RESET; 1118 dw100_write(dw_dev, DW100_DEWARP_CTRL, val); 1119 } 1120 1121 static void _dw100_hw_set_master_bus_enable(struct dw100_device *dw_dev, 1122 unsigned int enable) 1123 { 1124 u32 val; 1125 1126 dev_dbg(&dw_dev->pdev->dev, "%sable master bus\n", 1127 enable ? "En" : "Dis"); 1128 1129 val = dw100_read(dw_dev, DW100_BUS_CTRL); 1130 1131 if (enable) 1132 val |= DW100_BUS_CTRL_AXI_MASTER_ENABLE; 1133 else 1134 val &= ~DW100_BUS_CTRL_AXI_MASTER_ENABLE; 1135 1136 dw100_write(dw_dev, DW100_BUS_CTRL, val); 1137 } 1138 1139 static void dw100_hw_master_bus_enable(struct dw100_device *dw_dev) 1140 { 1141 _dw100_hw_set_master_bus_enable(dw_dev, 1); 1142 } 1143 1144 static void dw100_hw_master_bus_disable(struct dw100_device *dw_dev) 1145 { 1146 _dw100_hw_set_master_bus_enable(dw_dev, 0); 1147 } 1148 1149 static void dw100_hw_dewarp_start(struct dw100_device *dw_dev) 1150 { 1151 u32 val; 1152 1153 val = dw100_read(dw_dev, DW100_DEWARP_CTRL); 1154 1155 dev_dbg(&dw_dev->pdev->dev, "Starting Hardware CTRL:0x%08x\n", val); 1156 dw100_write(dw_dev, DW100_DEWARP_CTRL, val | DW100_DEWARP_CTRL_START); 1157 dw100_write(dw_dev, DW100_DEWARP_CTRL, val); 1158 } 1159 1160 static void dw100_hw_init_ctrl(struct dw100_device *dw_dev) 1161 { 1162 u32 val; 1163 /* 1164 * Input format YUV422_SP 1165 * Output format YUV422_SP 1166 * No hardware handshake (SW) 1167 * No automatic double src buffering (Single) 1168 * No automatic double dst buffering (Single) 1169 * No Black Line 1170 * Prefetch image pixel traversal 1171 */ 1172 1173 val = DW100_DEWARP_CTRL_ENABLE 1174 /* Valid only for auto prefetch mode*/ 1175 | DW100_DEWARP_CTRL_PREFETCH_THRESHOLD(32); 1176 1177 /* 1178 * Calculation mode required to support any scaling factor, 1179 * but x4 slower than traversal mode. 1180 * 1181 * DW100_DEWARP_CTRL_PREFETCH_MODE_TRAVERSAL 1182 * DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION 1183 * DW100_DEWARP_CTRL_PREFETCH_MODE_AUTO 1184 * 1185 * TODO: Find heuristics requiring calculation mode 1186 */ 1187 val |= DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION; 1188 1189 dw100_write(dw_dev, DW100_DEWARP_CTRL, val); 1190 } 1191 1192 static void dw100_hw_set_pixel_boundary(struct dw100_device *dw_dev) 1193 { 1194 u32 val; 1195 1196 val = DW100_BOUNDARY_PIXEL_V(128) 1197 | DW100_BOUNDARY_PIXEL_U(128) 1198 | DW100_BOUNDARY_PIXEL_Y(0); 1199 1200 dw100_write(dw_dev, DW100_BOUNDARY_PIXEL, val); 1201 } 1202 1203 static void dw100_hw_set_scale(struct dw100_device *dw_dev, u8 scale) 1204 { 1205 dev_dbg(&dw_dev->pdev->dev, "Setting scale factor to %u\n", scale); 1206 1207 dw100_write(dw_dev, DW100_SCALE_FACTOR, scale); 1208 } 1209 1210 static void dw100_hw_set_roi(struct dw100_device *dw_dev, u32 x, u32 y) 1211 { 1212 u32 val; 1213 1214 dev_dbg(&dw_dev->pdev->dev, "Setting ROI region to %u.%u\n", x, y); 1215 1216 val = DW100_ROI_START_X(x) | DW100_ROI_START_Y(y); 1217 1218 dw100_write(dw_dev, DW100_ROI_START, val); 1219 } 1220 1221 static void dw100_hw_set_src_crop(struct dw100_device *dw_dev, 1222 const struct dw100_q_data *src_q_data, 1223 const struct dw100_q_data *dst_q_data) 1224 { 1225 const struct v4l2_rect *rect = &src_q_data->crop; 1226 u32 src_scale, qscale, left_scale, top_scale; 1227 1228 /* HW Scale is UQ1.7 encoded */ 1229 src_scale = (rect->width << 7) / src_q_data->pix_fmt.width; 1230 dw100_hw_set_scale(dw_dev, src_scale); 1231 1232 qscale = (dst_q_data->pix_fmt.width << 7) / src_q_data->pix_fmt.width; 1233 1234 left_scale = ((rect->left << 7) * qscale) >> 14; 1235 top_scale = ((rect->top << 7) * qscale) >> 14; 1236 1237 dw100_hw_set_roi(dw_dev, left_scale, top_scale); 1238 } 1239 1240 static void dw100_hw_set_source(struct dw100_device *dw_dev, 1241 const struct dw100_q_data *q_data, 1242 struct vb2_buffer *buffer) 1243 { 1244 u32 width, height, stride, fourcc, val; 1245 const struct dw100_fmt *fmt = q_data->fmt; 1246 dma_addr_t addr_y = vb2_dma_contig_plane_dma_addr(buffer, 0); 1247 dma_addr_t addr_uv; 1248 1249 width = q_data->pix_fmt.width; 1250 height = q_data->pix_fmt.height; 1251 stride = q_data->pix_fmt.plane_fmt[0].bytesperline; 1252 fourcc = q_data->fmt->fourcc; 1253 1254 if (q_data->pix_fmt.num_planes == 2) 1255 addr_uv = vb2_dma_contig_plane_dma_addr(buffer, 1); 1256 else 1257 addr_uv = addr_y + (stride * height); 1258 1259 dev_dbg(&dw_dev->pdev->dev, 1260 "Set HW source registers for %ux%u - stride %u, pixfmt: %p4cc, dma:%pad\n", 1261 width, height, stride, &fourcc, &addr_y); 1262 1263 /* Pixel Format */ 1264 val = dw100_read(dw_dev, DW100_DEWARP_CTRL); 1265 1266 val &= ~DW100_DEWARP_CTRL_INPUT_FORMAT_MASK; 1267 val |= DW100_DEWARP_CTRL_INPUT_FORMAT(fmt->reg_format); 1268 1269 dw100_write(dw_dev, DW100_DEWARP_CTRL, val); 1270 1271 /* Swap */ 1272 val = dw100_read(dw_dev, DW100_SWAP_CONTROL); 1273 1274 val &= ~DW100_SWAP_CONTROL_SRC_MASK; 1275 /* 1276 * Data swapping is performed only on Y plane for source image. 1277 */ 1278 if (fmt->reg_swap_uv && 1279 fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED) 1280 val |= DW100_SWAP_CONTROL_SRC(DW100_SWAP_CONTROL_Y 1281 (DW100_SWAP_CONTROL_BYTE)); 1282 1283 dw100_write(dw_dev, DW100_SWAP_CONTROL, val); 1284 1285 /* Image resolution */ 1286 dw100_write(dw_dev, DW100_SRC_IMG_SIZE, 1287 DW100_IMG_SIZE_WIDTH(width) | DW100_IMG_SIZE_HEIGHT(height)); 1288 1289 dw100_write(dw_dev, DW100_SRC_IMG_STRIDE, stride); 1290 1291 /* Buffers */ 1292 dw100_write(dw_dev, DW100_SRC_IMG_Y_BASE, DW100_IMG_Y_BASE(addr_y)); 1293 dw100_write(dw_dev, DW100_SRC_IMG_UV_BASE, DW100_IMG_UV_BASE(addr_uv)); 1294 } 1295 1296 static void dw100_hw_set_destination(struct dw100_device *dw_dev, 1297 const struct dw100_q_data *q_data, 1298 const struct dw100_fmt *ifmt, 1299 struct vb2_buffer *buffer) 1300 { 1301 u32 width, height, stride, fourcc, val, size_y, size_uv; 1302 const struct dw100_fmt *fmt = q_data->fmt; 1303 dma_addr_t addr_y, addr_uv; 1304 1305 width = q_data->pix_fmt.width; 1306 height = q_data->pix_fmt.height; 1307 stride = q_data->pix_fmt.plane_fmt[0].bytesperline; 1308 fourcc = fmt->fourcc; 1309 1310 addr_y = vb2_dma_contig_plane_dma_addr(buffer, 0); 1311 size_y = q_data->pix_fmt.plane_fmt[0].sizeimage; 1312 1313 if (q_data->pix_fmt.num_planes == 2) { 1314 addr_uv = vb2_dma_contig_plane_dma_addr(buffer, 1); 1315 size_uv = q_data->pix_fmt.plane_fmt[1].sizeimage; 1316 } else { 1317 addr_uv = addr_y + ALIGN(stride * height, 16); 1318 size_uv = size_y; 1319 if (fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV420_SP) 1320 size_uv /= 2; 1321 } 1322 1323 dev_dbg(&dw_dev->pdev->dev, 1324 "Set HW destination registers for %ux%u - stride %u, pixfmt: %p4cc, dma:%pad\n", 1325 width, height, stride, &fourcc, &addr_y); 1326 1327 /* Pixel Format */ 1328 val = dw100_read(dw_dev, DW100_DEWARP_CTRL); 1329 1330 val &= ~DW100_DEWARP_CTRL_OUTPUT_FORMAT_MASK; 1331 val |= DW100_DEWARP_CTRL_OUTPUT_FORMAT(fmt->reg_format); 1332 1333 dw100_write(dw_dev, DW100_DEWARP_CTRL, val); 1334 1335 /* Swap */ 1336 val = dw100_read(dw_dev, DW100_SWAP_CONTROL); 1337 1338 val &= ~DW100_SWAP_CONTROL_DST_MASK; 1339 1340 /* 1341 * Avoid to swap twice 1342 */ 1343 if (fmt->reg_swap_uv ^ 1344 (ifmt->reg_swap_uv && ifmt->reg_format != 1345 DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED)) { 1346 if (fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED) 1347 val |= DW100_SWAP_CONTROL_DST(DW100_SWAP_CONTROL_Y 1348 (DW100_SWAP_CONTROL_BYTE)); 1349 else 1350 val |= DW100_SWAP_CONTROL_DST(DW100_SWAP_CONTROL_UV 1351 (DW100_SWAP_CONTROL_BYTE)); 1352 } 1353 1354 dw100_write(dw_dev, DW100_SWAP_CONTROL, val); 1355 1356 /* Image resolution */ 1357 dw100_write(dw_dev, DW100_DST_IMG_SIZE, 1358 DW100_IMG_SIZE_WIDTH(width) | DW100_IMG_SIZE_HEIGHT(height)); 1359 dw100_write(dw_dev, DW100_DST_IMG_STRIDE, stride); 1360 dw100_write(dw_dev, DW100_DST_IMG_Y_BASE, DW100_IMG_Y_BASE(addr_y)); 1361 dw100_write(dw_dev, DW100_DST_IMG_UV_BASE, DW100_IMG_UV_BASE(addr_uv)); 1362 dw100_write(dw_dev, DW100_DST_IMG_Y_SIZE1, DW100_DST_IMG_Y_SIZE(size_y)); 1363 dw100_write(dw_dev, DW100_DST_IMG_UV_SIZE1, 1364 DW100_DST_IMG_UV_SIZE(size_uv)); 1365 } 1366 1367 static void dw100_hw_set_mapping(struct dw100_device *dw_dev, dma_addr_t addr, 1368 u32 width, u32 height) 1369 { 1370 dev_dbg(&dw_dev->pdev->dev, 1371 "Set HW mapping registers for %ux%u addr:%pad", 1372 width, height, &addr); 1373 1374 dw100_write(dw_dev, DW100_MAP_LUT_ADDR, DW100_MAP_LUT_ADDR_ADDR(addr)); 1375 dw100_write(dw_dev, DW100_MAP_LUT_SIZE, DW100_MAP_LUT_SIZE_WIDTH(width) 1376 | DW100_MAP_LUT_SIZE_HEIGHT(height)); 1377 } 1378 1379 static void dw100_hw_clear_irq(struct dw100_device *dw_dev, unsigned int irq) 1380 { 1381 dw100_write(dw_dev, DW100_INTERRUPT_STATUS, 1382 DW100_INTERRUPT_STATUS_INT_CLEAR(irq)); 1383 } 1384 1385 static void dw100_hw_enable_irq(struct dw100_device *dw_dev) 1386 { 1387 dw100_write(dw_dev, DW100_INTERRUPT_STATUS, 1388 DW100_INTERRUPT_STATUS_INT_ENABLE_MASK); 1389 } 1390 1391 static void dw100_hw_disable_irq(struct dw100_device *dw_dev) 1392 { 1393 dw100_write(dw_dev, DW100_INTERRUPT_STATUS, 0); 1394 } 1395 1396 static u32 dw_hw_get_pending_irqs(struct dw100_device *dw_dev) 1397 { 1398 u32 val; 1399 1400 val = dw100_read(dw_dev, DW100_INTERRUPT_STATUS); 1401 1402 return DW100_INTERRUPT_STATUS_INT_STATUS(val); 1403 } 1404 1405 static irqreturn_t dw100_irq_handler(int irq, void *dev_id) 1406 { 1407 struct dw100_device *dw_dev = dev_id; 1408 u32 pending_irqs, err_irqs, frame_done_irq; 1409 1410 dw_dev->frame_failed = true; 1411 1412 pending_irqs = dw_hw_get_pending_irqs(dw_dev); 1413 frame_done_irq = pending_irqs & DW100_INTERRUPT_STATUS_INT_FRAME_DONE; 1414 err_irqs = DW100_INTERRUPT_STATUS_INT_ERR_STATUS(pending_irqs); 1415 1416 if (frame_done_irq) { 1417 dev_dbg(&dw_dev->pdev->dev, "Frame done interrupt\n"); 1418 dw_dev->frame_failed = false; 1419 err_irqs &= ~DW100_INTERRUPT_STATUS_INT_ERR_STATUS 1420 (DW100_INTERRUPT_STATUS_INT_ERR_FRAME_DONE); 1421 } 1422 1423 if (err_irqs) 1424 dev_err(&dw_dev->pdev->dev, "Interrupt error: %#x\n", err_irqs); 1425 1426 dw100_hw_disable_irq(dw_dev); 1427 dw100_hw_master_bus_disable(dw_dev); 1428 dw100_hw_clear_irq(dw_dev, pending_irqs | 1429 DW100_INTERRUPT_STATUS_INT_ERR_TIME_OUT); 1430 1431 return IRQ_WAKE_THREAD; 1432 } 1433 1434 static irqreturn_t dw100_irq_thread_fn(int irq, void *dev_id) 1435 { 1436 struct dw100_device *dw_dev = dev_id; 1437 1438 dw100_job_finish(dw_dev, dw_dev->frame_failed); 1439 1440 return IRQ_HANDLED; 1441 } 1442 1443 static void dw100_device_run(void *priv) 1444 { 1445 struct dw100_ctx *ctx = priv; 1446 struct dw100_device *dw_dev = ctx->dw_dev; 1447 struct vb2_v4l2_buffer *src_buf, *dst_buf; 1448 1449 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); 1450 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); 1451 1452 v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req, 1453 &ctx->hdl); 1454 1455 if (src_buf->vb2_buf.req_obj.req) 1456 dw100_update_mapping(ctx); 1457 else if (ctx->user_map_is_dirty) 1458 dev_warn_once(&dw_dev->pdev->dev, 1459 "V4L2 requests are required to update the vertex map dynamically\n"); 1460 1461 /* 1462 * As the hardware does not update any volatile controls, we can 1463 * complete control handling before starting the dewarper. 1464 */ 1465 v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req, 1466 &ctx->hdl); 1467 1468 src_buf->sequence = 1469 dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)->sequence++; 1470 dst_buf->sequence = 1471 dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)->sequence++; 1472 1473 dev_dbg(&dw_dev->pdev->dev, 1474 "Starting queues %p->%p, sequence %u->%u\n", 1475 v4l2_m2m_get_vq(ctx->fh.m2m_ctx, 1476 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE), 1477 v4l2_m2m_get_vq(ctx->fh.m2m_ctx, 1478 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE), 1479 src_buf->sequence, dst_buf->sequence); 1480 1481 v4l2_m2m_buf_copy_metadata(src_buf, dst_buf); 1482 1483 /* Now, let's deal with hardware ... */ 1484 dw100_hw_master_bus_disable(dw_dev); 1485 dw100_hw_init_ctrl(dw_dev); 1486 dw100_hw_set_pixel_boundary(dw_dev); 1487 dw100_hw_set_src_crop(dw_dev, &ctx->q_data[DW100_QUEUE_SRC], 1488 &ctx->q_data[DW100_QUEUE_DST]); 1489 dw100_hw_set_source(dw_dev, &ctx->q_data[DW100_QUEUE_SRC], 1490 &src_buf->vb2_buf); 1491 dw100_hw_set_destination(dw_dev, &ctx->q_data[DW100_QUEUE_DST], 1492 ctx->q_data[DW100_QUEUE_SRC].fmt, 1493 &dst_buf->vb2_buf); 1494 dw100_hw_set_mapping(dw_dev, ctx->map_dma, 1495 ctx->map_width, ctx->map_height); 1496 dw100_hw_enable_irq(dw_dev); 1497 dw100_hw_dewarp_start(dw_dev); 1498 1499 /* Enable Bus */ 1500 dw100_hw_master_bus_enable(dw_dev); 1501 } 1502 1503 static const struct v4l2_m2m_ops dw100_m2m_ops = { 1504 .device_run = dw100_device_run, 1505 }; 1506 1507 static const struct media_device_ops dw100_m2m_media_ops = { 1508 .req_validate = vb2_request_validate, 1509 .req_queue = v4l2_m2m_request_queue, 1510 }; 1511 1512 static struct video_device *dw100_init_video_device(struct dw100_device *dw_dev) 1513 { 1514 struct video_device *vfd = &dw_dev->vfd; 1515 1516 vfd->vfl_dir = VFL_DIR_M2M; 1517 vfd->fops = &dw100_fops; 1518 vfd->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING; 1519 vfd->ioctl_ops = &dw100_ioctl_ops; 1520 vfd->minor = -1; 1521 vfd->release = video_device_release_empty; 1522 vfd->v4l2_dev = &dw_dev->v4l2_dev; 1523 vfd->lock = &dw_dev->vfd_mutex; 1524 1525 strscpy(vfd->name, DRV_NAME, sizeof(vfd->name)); 1526 mutex_init(vfd->lock); 1527 video_set_drvdata(vfd, dw_dev); 1528 1529 return vfd; 1530 } 1531 1532 static int dw100_dump_regs_show(struct seq_file *m, void *private) 1533 { 1534 struct dw100_device *dw_dev = m->private; 1535 int ret; 1536 1537 ret = pm_runtime_resume_and_get(&dw_dev->pdev->dev); 1538 if (ret < 0) 1539 return ret; 1540 1541 ret = dw100_dump_regs(m); 1542 1543 pm_runtime_put_sync(&dw_dev->pdev->dev); 1544 1545 return ret; 1546 } 1547 DEFINE_SHOW_ATTRIBUTE(dw100_dump_regs); 1548 1549 static void dw100_debugfs_init(struct dw100_device *dw_dev) 1550 { 1551 dw_dev->debugfs_root = 1552 debugfs_create_dir(dev_name(&dw_dev->pdev->dev), NULL); 1553 1554 debugfs_create_file("dump_regs", 0600, dw_dev->debugfs_root, dw_dev, 1555 &dw100_dump_regs_fops); 1556 } 1557 1558 static void dw100_debugfs_exit(struct dw100_device *dw_dev) 1559 { 1560 debugfs_remove_recursive(dw_dev->debugfs_root); 1561 } 1562 1563 static int dw100_probe(struct platform_device *pdev) 1564 { 1565 struct dw100_device *dw_dev; 1566 struct video_device *vfd; 1567 int ret, irq; 1568 1569 dw_dev = devm_kzalloc(&pdev->dev, sizeof(*dw_dev), GFP_KERNEL); 1570 if (!dw_dev) 1571 return -ENOMEM; 1572 dw_dev->pdev = pdev; 1573 1574 ret = devm_clk_bulk_get_all(&pdev->dev, &dw_dev->clks); 1575 if (ret < 0) { 1576 dev_err(&pdev->dev, "Unable to get clocks: %d\n", ret); 1577 return ret; 1578 } 1579 dw_dev->num_clks = ret; 1580 1581 dw_dev->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 1582 if (IS_ERR(dw_dev->mmio)) 1583 return PTR_ERR(dw_dev->mmio); 1584 1585 irq = platform_get_irq(pdev, 0); 1586 if (irq < 0) 1587 return irq; 1588 1589 platform_set_drvdata(pdev, dw_dev); 1590 1591 pm_runtime_enable(&pdev->dev); 1592 ret = pm_runtime_resume_and_get(&pdev->dev); 1593 if (ret < 0) { 1594 dev_err(&pdev->dev, "Unable to resume the device: %d\n", ret); 1595 goto err_pm; 1596 } 1597 1598 pm_runtime_put_sync(&pdev->dev); 1599 1600 ret = devm_request_threaded_irq(&pdev->dev, irq, dw100_irq_handler, 1601 dw100_irq_thread_fn, 0, 1602 dev_name(&pdev->dev), dw_dev); 1603 if (ret < 0) { 1604 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); 1605 goto err_pm; 1606 } 1607 1608 ret = v4l2_device_register(&pdev->dev, &dw_dev->v4l2_dev); 1609 if (ret) 1610 goto err_pm; 1611 1612 vfd = dw100_init_video_device(dw_dev); 1613 1614 dw_dev->m2m_dev = v4l2_m2m_init(&dw100_m2m_ops); 1615 if (IS_ERR(dw_dev->m2m_dev)) { 1616 dev_err(&pdev->dev, "Failed to init mem2mem device\n"); 1617 ret = PTR_ERR(dw_dev->m2m_dev); 1618 goto err_v4l2; 1619 } 1620 1621 dw_dev->mdev.dev = &pdev->dev; 1622 strscpy(dw_dev->mdev.model, "dw100", sizeof(dw_dev->mdev.model)); 1623 media_device_init(&dw_dev->mdev); 1624 dw_dev->mdev.ops = &dw100_m2m_media_ops; 1625 dw_dev->v4l2_dev.mdev = &dw_dev->mdev; 1626 1627 ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1); 1628 if (ret) { 1629 dev_err(&pdev->dev, "Failed to register video device\n"); 1630 goto err_m2m; 1631 } 1632 1633 ret = v4l2_m2m_register_media_controller(dw_dev->m2m_dev, vfd, 1634 MEDIA_ENT_F_PROC_VIDEO_SCALER); 1635 if (ret) { 1636 dev_err(&pdev->dev, "Failed to init mem2mem media controller\n"); 1637 goto error_v4l2; 1638 } 1639 1640 ret = media_device_register(&dw_dev->mdev); 1641 if (ret) { 1642 dev_err(&pdev->dev, "Failed to register mem2mem media device\n"); 1643 goto error_m2m_mc; 1644 } 1645 1646 dw100_debugfs_init(dw_dev); 1647 1648 dev_info(&pdev->dev, 1649 "dw100 v4l2 m2m registered as /dev/video%u\n", vfd->num); 1650 1651 return 0; 1652 1653 error_m2m_mc: 1654 v4l2_m2m_unregister_media_controller(dw_dev->m2m_dev); 1655 error_v4l2: 1656 video_unregister_device(vfd); 1657 err_m2m: 1658 media_device_cleanup(&dw_dev->mdev); 1659 v4l2_m2m_release(dw_dev->m2m_dev); 1660 err_v4l2: 1661 v4l2_device_unregister(&dw_dev->v4l2_dev); 1662 err_pm: 1663 pm_runtime_disable(&pdev->dev); 1664 1665 return ret; 1666 } 1667 1668 static void dw100_remove(struct platform_device *pdev) 1669 { 1670 struct dw100_device *dw_dev = platform_get_drvdata(pdev); 1671 1672 dw100_debugfs_exit(dw_dev); 1673 1674 pm_runtime_disable(&pdev->dev); 1675 1676 media_device_unregister(&dw_dev->mdev); 1677 v4l2_m2m_unregister_media_controller(dw_dev->m2m_dev); 1678 media_device_cleanup(&dw_dev->mdev); 1679 1680 video_unregister_device(&dw_dev->vfd); 1681 mutex_destroy(dw_dev->vfd.lock); 1682 v4l2_m2m_release(dw_dev->m2m_dev); 1683 v4l2_device_unregister(&dw_dev->v4l2_dev); 1684 } 1685 1686 static int __maybe_unused dw100_runtime_suspend(struct device *dev) 1687 { 1688 struct dw100_device *dw_dev = dev_get_drvdata(dev); 1689 1690 clk_bulk_disable_unprepare(dw_dev->num_clks, dw_dev->clks); 1691 1692 return 0; 1693 } 1694 1695 static int __maybe_unused dw100_runtime_resume(struct device *dev) 1696 { 1697 int ret; 1698 struct dw100_device *dw_dev = dev_get_drvdata(dev); 1699 1700 ret = clk_bulk_prepare_enable(dw_dev->num_clks, dw_dev->clks); 1701 1702 if (ret) 1703 return ret; 1704 1705 dw100_hw_reset(dw_dev); 1706 1707 return 0; 1708 } 1709 1710 static const struct dev_pm_ops dw100_pm = { 1711 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1712 pm_runtime_force_resume) 1713 SET_RUNTIME_PM_OPS(dw100_runtime_suspend, 1714 dw100_runtime_resume, NULL) 1715 }; 1716 1717 static const struct of_device_id dw100_dt_ids[] = { 1718 { .compatible = "nxp,imx8mp-dw100", .data = NULL }, 1719 { }, 1720 }; 1721 MODULE_DEVICE_TABLE(of, dw100_dt_ids); 1722 1723 static struct platform_driver dw100_driver = { 1724 .probe = dw100_probe, 1725 .remove = dw100_remove, 1726 .driver = { 1727 .name = DRV_NAME, 1728 .pm = &dw100_pm, 1729 .of_match_table = dw100_dt_ids, 1730 }, 1731 }; 1732 1733 module_platform_driver(dw100_driver); 1734 1735 MODULE_DESCRIPTION("DW100 Hardware dewarper"); 1736 MODULE_AUTHOR("Xavier Roumegue <Xavier.Roumegue@oss.nxp.com>"); 1737 MODULE_LICENSE("GPL"); 1738