1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // aw88395_device.c -- AW88395 function for ALSA Audio Driver
4 //
5 // Copyright (c) 2022-2023 AWINIC Technology CO., LTD
6 //
7 // Author: Bruce zhao <zhaolei@awinic.com>
8 // Author: Ben Yi <yijiangtao@awinic.com>
9 //
10
11 #include <linux/crc32.h>
12 #include <linux/i2c.h>
13 #include <linux/minmax.h>
14 #include <linux/regmap.h>
15 #include "aw88395_device.h"
16 #include "aw88395_reg.h"
17
aw_dev_dsp_write_16bit(struct aw_device * aw_dev,unsigned short dsp_addr,unsigned int dsp_data)18 static int aw_dev_dsp_write_16bit(struct aw_device *aw_dev,
19 unsigned short dsp_addr, unsigned int dsp_data)
20 {
21 int ret;
22
23 ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, dsp_addr);
24 if (ret) {
25 dev_err(aw_dev->dev, "%s write addr error, ret=%d", __func__, ret);
26 return ret;
27 }
28
29 ret = regmap_write(aw_dev->regmap, AW88395_DSPMDAT_REG, (u16)dsp_data);
30 if (ret) {
31 dev_err(aw_dev->dev, "%s write data error, ret=%d", __func__, ret);
32 return ret;
33 }
34
35 return 0;
36 }
37
aw_dev_dsp_write_32bit(struct aw_device * aw_dev,unsigned short dsp_addr,unsigned int dsp_data)38 static int aw_dev_dsp_write_32bit(struct aw_device *aw_dev,
39 unsigned short dsp_addr, unsigned int dsp_data)
40 {
41 u16 temp_data;
42 int ret;
43
44 ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, dsp_addr);
45 if (ret) {
46 dev_err(aw_dev->dev, "%s write addr error, ret=%d", __func__, ret);
47 return ret;
48 }
49
50 temp_data = dsp_data & AW88395_DSP_16_DATA_MASK;
51 ret = regmap_write(aw_dev->regmap, AW88395_DSPMDAT_REG, (u16)temp_data);
52 if (ret) {
53 dev_err(aw_dev->dev, "%s write datal error, ret=%d", __func__, ret);
54 return ret;
55 }
56
57 temp_data = dsp_data >> 16;
58 ret = regmap_write(aw_dev->regmap, AW88395_DSPMDAT_REG, (u16)temp_data);
59 if (ret) {
60 dev_err(aw_dev->dev, "%s write datah error, ret=%d", __func__, ret);
61 return ret;
62 }
63
64 return 0;
65 }
66
aw_dev_dsp_write(struct aw_device * aw_dev,unsigned short dsp_addr,unsigned int dsp_data,unsigned char data_type)67 static int aw_dev_dsp_write(struct aw_device *aw_dev,
68 unsigned short dsp_addr, unsigned int dsp_data, unsigned char data_type)
69 {
70 u32 reg_value;
71 int ret;
72
73 mutex_lock(&aw_dev->dsp_lock);
74 switch (data_type) {
75 case AW88395_DSP_16_DATA:
76 ret = aw_dev_dsp_write_16bit(aw_dev, dsp_addr, dsp_data);
77 if (ret)
78 dev_err(aw_dev->dev, "write dsp_addr[0x%x] 16-bit dsp_data[0x%x] failed",
79 (u32)dsp_addr, dsp_data);
80 break;
81 case AW88395_DSP_32_DATA:
82 ret = aw_dev_dsp_write_32bit(aw_dev, dsp_addr, dsp_data);
83 if (ret)
84 dev_err(aw_dev->dev, "write dsp_addr[0x%x] 32-bit dsp_data[0x%x] failed",
85 (u32)dsp_addr, dsp_data);
86 break;
87 default:
88 dev_err(aw_dev->dev, "data type[%d] unsupported", data_type);
89 ret = -EINVAL;
90 break;
91 }
92
93 /* clear dsp chip select state*/
94 if (regmap_read(aw_dev->regmap, AW88395_ID_REG, ®_value))
95 dev_err(aw_dev->dev, "%s fail to clear chip state. Err=%d\n", __func__, ret);
96 mutex_unlock(&aw_dev->dsp_lock);
97
98 return ret;
99 }
100
aw_dev_dsp_read_16bit(struct aw_device * aw_dev,unsigned short dsp_addr,unsigned int * dsp_data)101 static int aw_dev_dsp_read_16bit(struct aw_device *aw_dev,
102 unsigned short dsp_addr, unsigned int *dsp_data)
103 {
104 unsigned int temp_data;
105 int ret;
106
107 ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, dsp_addr);
108 if (ret) {
109 dev_err(aw_dev->dev, "%s write error, ret=%d", __func__, ret);
110 return ret;
111 }
112
113 ret = regmap_read(aw_dev->regmap, AW88395_DSPMDAT_REG, &temp_data);
114 if (ret) {
115 dev_err(aw_dev->dev, "%s read error, ret=%d", __func__, ret);
116 return ret;
117 }
118 *dsp_data = temp_data;
119
120 return 0;
121 }
122
aw_dev_dsp_read_32bit(struct aw_device * aw_dev,unsigned short dsp_addr,unsigned int * dsp_data)123 static int aw_dev_dsp_read_32bit(struct aw_device *aw_dev,
124 unsigned short dsp_addr, unsigned int *dsp_data)
125 {
126 unsigned int temp_data;
127 int ret;
128
129 ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, dsp_addr);
130 if (ret) {
131 dev_err(aw_dev->dev, "%s write error, ret=%d", __func__, ret);
132 return ret;
133 }
134
135 ret = regmap_read(aw_dev->regmap, AW88395_DSPMDAT_REG, &temp_data);
136 if (ret) {
137 dev_err(aw_dev->dev, "%s read error, ret=%d", __func__, ret);
138 return ret;
139 }
140 *dsp_data = temp_data;
141
142 ret = regmap_read(aw_dev->regmap, AW88395_DSPMDAT_REG, &temp_data);
143 if (ret) {
144 dev_err(aw_dev->dev, "%s read error, ret=%d", __func__, ret);
145 return ret;
146 }
147 *dsp_data |= (temp_data << 16);
148
149 return 0;
150 }
151
aw_dev_dsp_read(struct aw_device * aw_dev,unsigned short dsp_addr,unsigned int * dsp_data,unsigned char data_type)152 static int aw_dev_dsp_read(struct aw_device *aw_dev,
153 unsigned short dsp_addr, unsigned int *dsp_data, unsigned char data_type)
154 {
155 u32 reg_value;
156 int ret;
157
158 mutex_lock(&aw_dev->dsp_lock);
159 switch (data_type) {
160 case AW88395_DSP_16_DATA:
161 ret = aw_dev_dsp_read_16bit(aw_dev, dsp_addr, dsp_data);
162 if (ret)
163 dev_err(aw_dev->dev, "read dsp_addr[0x%x] 16-bit dsp_data[0x%x] failed",
164 (u32)dsp_addr, *dsp_data);
165 break;
166 case AW88395_DSP_32_DATA:
167 ret = aw_dev_dsp_read_32bit(aw_dev, dsp_addr, dsp_data);
168 if (ret)
169 dev_err(aw_dev->dev, "read dsp_addr[0x%x] 32r-bit dsp_data[0x%x] failed",
170 (u32)dsp_addr, *dsp_data);
171 break;
172 default:
173 dev_err(aw_dev->dev, "data type[%d] unsupported", data_type);
174 ret = -EINVAL;
175 break;
176 }
177
178 /* clear dsp chip select state*/
179 if (regmap_read(aw_dev->regmap, AW88395_ID_REG, ®_value))
180 dev_err(aw_dev->dev, "%s fail to clear chip state. Err=%d\n", __func__, ret);
181 mutex_unlock(&aw_dev->dsp_lock);
182
183 return ret;
184 }
185
186
aw_dev_read_chipid(struct aw_device * aw_dev,u16 * chip_id)187 static int aw_dev_read_chipid(struct aw_device *aw_dev, u16 *chip_id)
188 {
189 int reg_val;
190 int ret;
191
192 ret = regmap_read(aw_dev->regmap, AW88395_CHIP_ID_REG, ®_val);
193 if (ret) {
194 dev_err(aw_dev->dev, "%s read chipid error. ret = %d", __func__, ret);
195 return ret;
196 }
197
198 dev_info(aw_dev->dev, "chip id = %x\n", reg_val);
199 *chip_id = reg_val;
200
201 return 0;
202 }
203
reg_val_to_db(unsigned int value)204 static unsigned int reg_val_to_db(unsigned int value)
205 {
206 return (((value >> AW88395_VOL_6DB_START) * AW88395_VOLUME_STEP_DB) +
207 ((value & 0x3f) % AW88395_VOLUME_STEP_DB));
208 }
209
db_to_reg_val(unsigned short value)210 static unsigned short db_to_reg_val(unsigned short value)
211 {
212 return (((value / AW88395_VOLUME_STEP_DB) << AW88395_VOL_6DB_START) +
213 (value % AW88395_VOLUME_STEP_DB));
214 }
215
aw_dev_dsp_fw_check(struct aw_device * aw_dev)216 static int aw_dev_dsp_fw_check(struct aw_device *aw_dev)
217 {
218 struct aw_sec_data_desc *dsp_fw_desc;
219 struct aw_prof_desc *set_prof_desc;
220 u16 base_addr = AW88395_DSP_FW_ADDR;
221 u16 addr = base_addr;
222 u32 dsp_val;
223 u16 bin_val;
224 int ret, i;
225
226 ret = aw88395_dev_get_prof_data(aw_dev, aw_dev->prof_cur, &set_prof_desc);
227 if (ret)
228 return ret;
229
230 /* update reg */
231 dsp_fw_desc = &set_prof_desc->sec_desc[AW88395_DATA_TYPE_DSP_FW];
232
233 for (i = 0; i < AW88395_FW_CHECK_PART; i++) {
234 ret = aw_dev_dsp_read(aw_dev, addr, &dsp_val, AW88395_DSP_16_DATA);
235 if (ret) {
236 dev_err(aw_dev->dev, "dsp read failed");
237 return ret;
238 }
239
240 bin_val = be16_to_cpup((void *)&dsp_fw_desc->data[2 * (addr - base_addr)]);
241
242 if (dsp_val != bin_val) {
243 dev_err(aw_dev->dev, "fw check failed, addr[0x%x], read[0x%x] != bindata[0x%x]",
244 addr, dsp_val, bin_val);
245 return -EINVAL;
246 }
247
248 addr += (dsp_fw_desc->len / 2) / AW88395_FW_CHECK_PART;
249 if ((addr - base_addr) > dsp_fw_desc->len) {
250 dev_err(aw_dev->dev, "fw check failed, addr[0x%x] too large", addr);
251 return -EINVAL;
252 }
253 }
254
255 return 0;
256 }
257
aw_dev_set_volume(struct aw_device * aw_dev,unsigned int value)258 static int aw_dev_set_volume(struct aw_device *aw_dev, unsigned int value)
259 {
260 struct aw_volume_desc *vol_desc = &aw_dev->volume_desc;
261 unsigned int reg_value;
262 u16 real_value, volume;
263 int ret;
264
265 volume = min((value + vol_desc->init_volume), (unsigned int)AW88395_MUTE_VOL);
266 real_value = db_to_reg_val(volume);
267
268 /* cal real value */
269 ret = regmap_read(aw_dev->regmap, AW88395_SYSCTRL2_REG, ®_value);
270 if (ret)
271 return ret;
272
273 dev_dbg(aw_dev->dev, "value 0x%x , reg:0x%x", value, real_value);
274
275 /* [15 : 6] volume */
276 real_value = (real_value << AW88395_VOL_START_BIT) | (reg_value & AW88395_VOL_MASK);
277
278 /* write value */
279 ret = regmap_write(aw_dev->regmap, AW88395_SYSCTRL2_REG, real_value);
280
281 return ret;
282 }
283
aw88395_dev_set_volume(struct aw_device * aw_dev,unsigned short set_vol)284 void aw88395_dev_set_volume(struct aw_device *aw_dev, unsigned short set_vol)
285 {
286 int ret;
287
288 ret = aw_dev_set_volume(aw_dev, set_vol);
289 if (ret)
290 dev_dbg(aw_dev->dev, "set volume failed");
291 }
292 EXPORT_SYMBOL_GPL(aw88395_dev_set_volume);
293
aw_dev_fade_in(struct aw_device * aw_dev)294 static void aw_dev_fade_in(struct aw_device *aw_dev)
295 {
296 struct aw_volume_desc *desc = &aw_dev->volume_desc;
297 u16 fade_in_vol = desc->ctl_volume;
298 int fade_step = aw_dev->fade_step;
299 int i;
300
301 if (fade_step == 0 || aw_dev->fade_in_time == 0) {
302 aw_dev_set_volume(aw_dev, fade_in_vol);
303 return;
304 }
305
306 for (i = AW88395_MUTE_VOL; i >= fade_in_vol; i -= fade_step) {
307 aw_dev_set_volume(aw_dev, i);
308 usleep_range(aw_dev->fade_in_time, aw_dev->fade_in_time + 10);
309 }
310
311 if (i != fade_in_vol)
312 aw_dev_set_volume(aw_dev, fade_in_vol);
313 }
314
aw_dev_fade_out(struct aw_device * aw_dev)315 static void aw_dev_fade_out(struct aw_device *aw_dev)
316 {
317 struct aw_volume_desc *desc = &aw_dev->volume_desc;
318 int fade_step = aw_dev->fade_step;
319 int i;
320
321 if (fade_step == 0 || aw_dev->fade_out_time == 0) {
322 aw_dev_set_volume(aw_dev, AW88395_MUTE_VOL);
323 return;
324 }
325
326 for (i = desc->ctl_volume; i <= AW88395_MUTE_VOL; i += fade_step) {
327 aw_dev_set_volume(aw_dev, i);
328 usleep_range(aw_dev->fade_out_time, aw_dev->fade_out_time + 10);
329 }
330
331 if (i != AW88395_MUTE_VOL) {
332 aw_dev_set_volume(aw_dev, AW88395_MUTE_VOL);
333 usleep_range(aw_dev->fade_out_time, aw_dev->fade_out_time + 10);
334 }
335 }
336
aw_dev_modify_dsp_cfg(struct aw_device * aw_dev,unsigned int addr,unsigned int dsp_data,unsigned char data_type)337 static int aw_dev_modify_dsp_cfg(struct aw_device *aw_dev,
338 unsigned int addr, unsigned int dsp_data, unsigned char data_type)
339 {
340 struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg;
341 unsigned int addr_offset;
342 __le16 data1;
343 __le32 data2;
344
345 dev_dbg(aw_dev->dev, "addr:0x%x, dsp_data:0x%x", addr, dsp_data);
346
347 addr_offset = (addr - AW88395_DSP_CFG_ADDR) * 2;
348 if (addr_offset > crc_dsp_cfg->len) {
349 dev_err(aw_dev->dev, "addr_offset[%d] > crc_dsp_cfg->len[%d]",
350 addr_offset, crc_dsp_cfg->len);
351 return -EINVAL;
352 }
353 switch (data_type) {
354 case AW88395_DSP_16_DATA:
355 data1 = cpu_to_le16((u16)dsp_data);
356 memcpy(crc_dsp_cfg->data + addr_offset, (u8 *)&data1, 2);
357 break;
358 case AW88395_DSP_32_DATA:
359 data2 = cpu_to_le32(dsp_data);
360 memcpy(crc_dsp_cfg->data + addr_offset, (u8 *)&data2, 4);
361 break;
362 default:
363 dev_err(aw_dev->dev, "data type[%d] unsupported", data_type);
364 return -EINVAL;
365 }
366
367 return 0;
368 }
369
aw_dev_dsp_set_cali_re(struct aw_device * aw_dev)370 static int aw_dev_dsp_set_cali_re(struct aw_device *aw_dev)
371 {
372 u32 cali_re;
373 int ret;
374
375 cali_re = AW88395_SHOW_RE_TO_DSP_RE((aw_dev->cali_desc.cali_re +
376 aw_dev->cali_desc.ra), AW88395_DSP_RE_SHIFT);
377
378 /* set cali re to device */
379 ret = aw_dev_dsp_write(aw_dev,
380 AW88395_DSP_REG_CFG_ADPZ_RE, cali_re, AW88395_DSP_32_DATA);
381 if (ret) {
382 dev_err(aw_dev->dev, "set cali re error");
383 return ret;
384 }
385
386 ret = aw_dev_modify_dsp_cfg(aw_dev, AW88395_DSP_REG_CFG_ADPZ_RE,
387 cali_re, AW88395_DSP_32_DATA);
388 if (ret)
389 dev_err(aw_dev->dev, "modify dsp cfg failed");
390
391 return ret;
392 }
393
aw_dev_i2s_tx_enable(struct aw_device * aw_dev,bool flag)394 static void aw_dev_i2s_tx_enable(struct aw_device *aw_dev, bool flag)
395 {
396 int ret;
397
398 if (flag) {
399 ret = regmap_update_bits(aw_dev->regmap, AW88395_I2SCFG1_REG,
400 ~AW88395_I2STXEN_MASK, AW88395_I2STXEN_ENABLE_VALUE);
401 } else {
402 ret = regmap_update_bits(aw_dev->regmap, AW88395_I2SCFG1_REG,
403 ~AW88395_I2STXEN_MASK, AW88395_I2STXEN_DISABLE_VALUE);
404 }
405
406 if (ret)
407 dev_dbg(aw_dev->dev, "%s failed", __func__);
408 }
409
aw_dev_dsp_set_crc32(struct aw_device * aw_dev)410 static int aw_dev_dsp_set_crc32(struct aw_device *aw_dev)
411 {
412 struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg;
413 u32 crc_value, crc_data_len;
414
415 /* get crc data len */
416 crc_data_len = (AW88395_DSP_REG_CRC_ADDR - AW88395_DSP_CFG_ADDR) * 2;
417 if (crc_data_len > crc_dsp_cfg->len) {
418 dev_err(aw_dev->dev, "crc data len :%d > cfg_data len:%d",
419 crc_data_len, crc_dsp_cfg->len);
420 return -EINVAL;
421 }
422
423 if (crc_data_len & 0x11) {
424 dev_err(aw_dev->dev, "The crc data len :%d unsupport", crc_data_len);
425 return -EINVAL;
426 }
427
428 crc_value = crc32c(0xFFFFFFFF, crc_dsp_cfg->data, crc_data_len) ^ 0xFFFFFFFF;
429
430 return aw_dev_dsp_write(aw_dev, AW88395_DSP_REG_CRC_ADDR, crc_value,
431 AW88395_DSP_32_DATA);
432 }
433
aw_dev_dsp_check_crc_enable(struct aw_device * aw_dev,bool flag)434 static void aw_dev_dsp_check_crc_enable(struct aw_device *aw_dev, bool flag)
435 {
436 int ret;
437
438 if (flag) {
439 ret = regmap_update_bits(aw_dev->regmap, AW88395_HAGCCFG7_REG,
440 ~AW88395_AGC_DSP_CTL_MASK, AW88395_AGC_DSP_CTL_ENABLE_VALUE);
441 } else {
442 ret = regmap_update_bits(aw_dev->regmap, AW88395_HAGCCFG7_REG,
443 ~AW88395_AGC_DSP_CTL_MASK, AW88395_AGC_DSP_CTL_DISABLE_VALUE);
444 }
445 if (ret)
446 dev_dbg(aw_dev->dev, "%s failed", __func__);
447 }
448
aw_dev_dsp_check_st(struct aw_device * aw_dev)449 static int aw_dev_dsp_check_st(struct aw_device *aw_dev)
450 {
451 unsigned int reg_val;
452 int ret;
453 int i;
454
455 for (i = 0; i < AW88395_DSP_ST_CHECK_MAX; i++) {
456 ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, ®_val);
457 if (ret) {
458 dev_err(aw_dev->dev, "read reg0x%x failed", AW88395_SYSST_REG);
459 continue;
460 }
461
462 if ((reg_val & (~AW88395_DSPS_MASK)) != AW88395_DSPS_NORMAL_VALUE) {
463 dev_err(aw_dev->dev, "check dsp st fail,reg_val:0x%04x", reg_val);
464 ret = -EPERM;
465 continue;
466 } else {
467 dev_dbg(aw_dev->dev, "dsp st check ok, reg_val:0x%04x", reg_val);
468 return 0;
469 }
470 }
471
472 return ret;
473 }
474
aw_dev_dsp_enable(struct aw_device * aw_dev,bool is_enable)475 static void aw_dev_dsp_enable(struct aw_device *aw_dev, bool is_enable)
476 {
477 int ret;
478
479 if (is_enable) {
480 ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
481 ~AW88395_DSPBY_MASK, AW88395_DSPBY_WORKING_VALUE);
482 if (ret)
483 dev_dbg(aw_dev->dev, "enable dsp failed");
484 } else {
485 ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
486 ~AW88395_DSPBY_MASK, AW88395_DSPBY_BYPASS_VALUE);
487 if (ret)
488 dev_dbg(aw_dev->dev, "disable dsp failed");
489 }
490 }
491
aw_dev_dsp_check_crc32(struct aw_device * aw_dev)492 static int aw_dev_dsp_check_crc32(struct aw_device *aw_dev)
493 {
494 int ret;
495
496 if (aw_dev->dsp_cfg == AW88395_DEV_DSP_BYPASS) {
497 dev_info(aw_dev->dev, "dsp bypass");
498 return 0;
499 }
500
501 ret = aw_dev_dsp_set_crc32(aw_dev);
502 if (ret) {
503 dev_err(aw_dev->dev, "set dsp crc32 failed");
504 return ret;
505 }
506
507 aw_dev_dsp_check_crc_enable(aw_dev, true);
508
509 /* dsp enable */
510 aw_dev_dsp_enable(aw_dev, true);
511 usleep_range(AW88395_5000_US, AW88395_5000_US + 100);
512
513 ret = aw_dev_dsp_check_st(aw_dev);
514 if (ret) {
515 dev_err(aw_dev->dev, "check crc32 fail");
516 } else {
517 aw_dev_dsp_check_crc_enable(aw_dev, false);
518 aw_dev->dsp_crc_st = AW88395_DSP_CRC_OK;
519 }
520
521 return ret;
522 }
523
aw_dev_pwd(struct aw_device * aw_dev,bool pwd)524 static void aw_dev_pwd(struct aw_device *aw_dev, bool pwd)
525 {
526 int ret;
527
528 if (pwd) {
529 ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
530 ~AW88395_PWDN_MASK, AW88395_PWDN_POWER_DOWN_VALUE);
531 } else {
532 ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
533 ~AW88395_PWDN_MASK, AW88395_PWDN_WORKING_VALUE);
534 }
535 if (ret)
536 dev_dbg(aw_dev->dev, "%s failed", __func__);
537 }
538
aw_dev_amppd(struct aw_device * aw_dev,bool amppd)539 static void aw_dev_amppd(struct aw_device *aw_dev, bool amppd)
540 {
541 int ret;
542
543 if (amppd) {
544 ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
545 ~AW88395_AMPPD_MASK, AW88395_AMPPD_POWER_DOWN_VALUE);
546 } else {
547 ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
548 ~AW88395_AMPPD_MASK, AW88395_AMPPD_WORKING_VALUE);
549 }
550 if (ret)
551 dev_dbg(aw_dev->dev, "%s failed", __func__);
552 }
553
aw88395_dev_mute(struct aw_device * aw_dev,bool is_mute)554 void aw88395_dev_mute(struct aw_device *aw_dev, bool is_mute)
555 {
556 int ret;
557
558 if (is_mute) {
559 aw_dev_fade_out(aw_dev);
560 ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
561 ~AW88395_HMUTE_MASK, AW88395_HMUTE_ENABLE_VALUE);
562 } else {
563 ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
564 ~AW88395_HMUTE_MASK, AW88395_HMUTE_DISABLE_VALUE);
565 aw_dev_fade_in(aw_dev);
566 }
567
568 if (ret)
569 dev_dbg(aw_dev->dev, "%s failed", __func__);
570 }
571 EXPORT_SYMBOL_GPL(aw88395_dev_mute);
572
aw_dev_get_icalk(struct aw_device * aw_dev,int16_t * icalk)573 static int aw_dev_get_icalk(struct aw_device *aw_dev, int16_t *icalk)
574 {
575 unsigned int reg_val;
576 u16 reg_icalk;
577 int ret;
578
579 ret = regmap_read(aw_dev->regmap, AW88395_EFRM2_REG, ®_val);
580 if (ret)
581 return ret;
582
583 reg_icalk = reg_val & (~AW88395_EF_ISN_GESLP_MASK);
584
585 if (reg_icalk & (~AW88395_EF_ISN_GESLP_SIGN_MASK))
586 reg_icalk = reg_icalk | AW88395_EF_ISN_GESLP_SIGN_NEG;
587
588 *icalk = (int16_t)reg_icalk;
589
590 return ret;
591 }
592
aw_dev_get_vcalk(struct aw_device * aw_dev,int16_t * vcalk)593 static int aw_dev_get_vcalk(struct aw_device *aw_dev, int16_t *vcalk)
594 {
595 unsigned int reg_val;
596 u16 reg_vcalk;
597 int ret;
598
599 ret = regmap_read(aw_dev->regmap, AW88395_EFRH_REG, ®_val);
600 if (ret)
601 return ret;
602
603 reg_val = reg_val >> AW88395_EF_VSENSE_GAIN_SHIFT;
604
605 reg_vcalk = (u16)reg_val & (~AW88395_EF_VSN_GESLP_MASK);
606
607 if (reg_vcalk & (~AW88395_EF_VSN_GESLP_SIGN_MASK))
608 reg_vcalk = reg_vcalk | AW88395_EF_VSN_GESLP_SIGN_NEG;
609
610 *vcalk = (int16_t)reg_vcalk;
611
612 return ret;
613 }
614
aw_dev_get_vcalk_dac(struct aw_device * aw_dev,int16_t * vcalk)615 static int aw_dev_get_vcalk_dac(struct aw_device *aw_dev, int16_t *vcalk)
616 {
617 unsigned int reg_val;
618 u16 reg_vcalk;
619 int ret;
620
621 ret = regmap_read(aw_dev->regmap, AW88395_EFRM2_REG, ®_val);
622 if (ret)
623 return ret;
624
625 reg_vcalk = reg_val >> AW88395_EF_DAC_GESLP_SHIFT;
626
627 if (reg_vcalk & AW88395_EF_DAC_GESLP_SIGN_MASK)
628 reg_vcalk = reg_vcalk | AW88395_EF_DAC_GESLP_SIGN_NEG;
629
630 *vcalk = (int16_t)reg_vcalk;
631
632 return ret;
633 }
634
aw_dev_vsense_select(struct aw_device * aw_dev,int * vsense_select)635 static int aw_dev_vsense_select(struct aw_device *aw_dev, int *vsense_select)
636 {
637 unsigned int vsense_reg_val;
638 int ret;
639
640 ret = regmap_read(aw_dev->regmap, AW88395_I2SCFG3_REG, &vsense_reg_val);
641 if (ret) {
642 dev_err(aw_dev->dev, "read vsense_reg_val failed");
643 return ret;
644 }
645 dev_dbg(aw_dev->dev, "vsense_reg = 0x%x", vsense_reg_val);
646
647 if (vsense_reg_val & (~AW88395_VDSEL_MASK)) {
648 *vsense_select = AW88395_DEV_VDSEL_VSENSE;
649 dev_dbg(aw_dev->dev, "vsense outside");
650 } else {
651 *vsense_select = AW88395_DEV_VDSEL_DAC;
652 dev_dbg(aw_dev->dev, "vsense inside");
653 }
654
655 return 0;
656 }
657
aw_dev_set_vcalb(struct aw_device * aw_dev)658 static int aw_dev_set_vcalb(struct aw_device *aw_dev)
659 {
660 int16_t icalk_val, vcalk_val;
661 int icalk, vsense_select;
662 u32 vcalb_adj, reg_val;
663 int vcalb, vcalk;
664 int ret;
665
666 ret = aw_dev_dsp_read(aw_dev, AW88395_DSP_REG_VCALB, &vcalb_adj, AW88395_DSP_16_DATA);
667 if (ret) {
668 dev_err(aw_dev->dev, "read vcalb_adj failed");
669 return ret;
670 }
671
672 ret = aw_dev_vsense_select(aw_dev, &vsense_select);
673 if (ret)
674 return ret;
675 dev_dbg(aw_dev->dev, "vsense_select = %d", vsense_select);
676
677 ret = aw_dev_get_icalk(aw_dev, &icalk_val);
678 if (ret)
679 return ret;
680 icalk = AW88395_CABL_BASE_VALUE + AW88395_ICABLK_FACTOR * icalk_val;
681
682 switch (vsense_select) {
683 case AW88395_DEV_VDSEL_VSENSE:
684 ret = aw_dev_get_vcalk(aw_dev, &vcalk_val);
685 if (ret)
686 return ret;
687 vcalk = AW88395_CABL_BASE_VALUE + AW88395_VCABLK_FACTOR * vcalk_val;
688 vcalb = AW88395_VCAL_FACTOR * AW88395_VSCAL_FACTOR /
689 AW88395_ISCAL_FACTOR * icalk / vcalk * vcalb_adj;
690
691 dev_dbg(aw_dev->dev, "vcalk_factor=%d, vscal_factor=%d, icalk=%d, vcalk=%d",
692 AW88395_VCABLK_FACTOR, AW88395_VSCAL_FACTOR, icalk, vcalk);
693 break;
694 case AW88395_DEV_VDSEL_DAC:
695 ret = aw_dev_get_vcalk_dac(aw_dev, &vcalk_val);
696 if (ret)
697 return ret;
698 vcalk = AW88395_CABL_BASE_VALUE + AW88395_VCABLK_FACTOR_DAC * vcalk_val;
699 vcalb = AW88395_VCAL_FACTOR * AW88395_VSCAL_FACTOR_DAC /
700 AW88395_ISCAL_FACTOR * icalk / vcalk * vcalb_adj;
701
702 dev_dbg(aw_dev->dev, "vcalk_dac_factor=%d, vscal_dac_factor=%d, icalk=%d, vcalk=%d",
703 AW88395_VCABLK_FACTOR_DAC,
704 AW88395_VSCAL_FACTOR_DAC, icalk, vcalk);
705 break;
706 default:
707 dev_err(aw_dev->dev, "unsupported vsense status");
708 return -EINVAL;
709 }
710
711 if ((vcalk == 0) || (AW88395_ISCAL_FACTOR == 0)) {
712 dev_err(aw_dev->dev, "vcalk:%d or desc->iscal_factor:%d unsupported",
713 vcalk, AW88395_ISCAL_FACTOR);
714 return -EINVAL;
715 }
716
717 vcalb = vcalb >> AW88395_VCALB_ADJ_FACTOR;
718 reg_val = (u32)vcalb;
719
720 dev_dbg(aw_dev->dev, "vcalb=%d, reg_val=0x%x, vcalb_adj =0x%x",
721 vcalb, reg_val, vcalb_adj);
722
723 ret = aw_dev_dsp_write(aw_dev, AW88395_DSP_REG_VCALB, reg_val, AW88395_DSP_16_DATA);
724 if (ret) {
725 dev_err(aw_dev->dev, "write vcalb failed");
726 return ret;
727 }
728
729 ret = aw_dev_modify_dsp_cfg(aw_dev, AW88395_DSP_REG_VCALB,
730 (u32)reg_val, AW88395_DSP_16_DATA);
731 if (ret)
732 dev_err(aw_dev->dev, "modify dsp cfg failed");
733
734 return ret;
735 }
736
aw_dev_get_cali_f0_delay(struct aw_device * aw_dev)737 static int aw_dev_get_cali_f0_delay(struct aw_device *aw_dev)
738 {
739 struct aw_cali_delay_desc *desc = &aw_dev->cali_delay_desc;
740 u32 cali_delay;
741 int ret;
742
743 ret = aw_dev_dsp_read(aw_dev,
744 AW88395_DSP_CALI_F0_DELAY, &cali_delay, AW88395_DSP_16_DATA);
745 if (ret)
746 dev_err(aw_dev->dev, "read cali delay failed, ret=%d", ret);
747 else
748 desc->delay = AW88395_CALI_DELAY_CACL(cali_delay);
749
750 dev_dbg(aw_dev->dev, "read cali delay: %d ms", desc->delay);
751
752 return ret;
753 }
754
aw_dev_get_int_status(struct aw_device * aw_dev,unsigned short * int_status)755 static void aw_dev_get_int_status(struct aw_device *aw_dev, unsigned short *int_status)
756 {
757 unsigned int reg_val;
758 int ret;
759
760 ret = regmap_read(aw_dev->regmap, AW88395_SYSINT_REG, ®_val);
761 if (ret)
762 dev_err(aw_dev->dev, "read interrupt reg fail, ret=%d", ret);
763 else
764 *int_status = reg_val;
765
766 dev_dbg(aw_dev->dev, "read interrupt reg = 0x%04x", *int_status);
767 }
768
aw_dev_clear_int_status(struct aw_device * aw_dev)769 static void aw_dev_clear_int_status(struct aw_device *aw_dev)
770 {
771 u16 int_status;
772
773 /* read int status and clear */
774 aw_dev_get_int_status(aw_dev, &int_status);
775 /* make sure int status is clear */
776 aw_dev_get_int_status(aw_dev, &int_status);
777 if (int_status)
778 dev_info(aw_dev->dev, "int status(%d) is not cleaned.\n", int_status);
779 }
780
aw_dev_get_iis_status(struct aw_device * aw_dev)781 static int aw_dev_get_iis_status(struct aw_device *aw_dev)
782 {
783 unsigned int reg_val;
784 int ret;
785
786 ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, ®_val);
787 if (ret)
788 return -EIO;
789 if ((reg_val & AW88395_BIT_PLL_CHECK) != AW88395_BIT_PLL_CHECK) {
790 dev_err(aw_dev->dev, "check pll lock fail,reg_val:0x%04x", reg_val);
791 return -EINVAL;
792 }
793
794 return 0;
795 }
796
aw_dev_check_mode1_pll(struct aw_device * aw_dev)797 static int aw_dev_check_mode1_pll(struct aw_device *aw_dev)
798 {
799 int ret, i;
800
801 for (i = 0; i < AW88395_DEV_SYSST_CHECK_MAX; i++) {
802 ret = aw_dev_get_iis_status(aw_dev);
803 if (ret < 0) {
804 dev_err(aw_dev->dev, "mode1 iis signal check error");
805 usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
806 } else {
807 return 0;
808 }
809 }
810
811 return -EPERM;
812 }
813
aw_dev_check_mode2_pll(struct aw_device * aw_dev)814 static int aw_dev_check_mode2_pll(struct aw_device *aw_dev)
815 {
816 unsigned int reg_val;
817 int ret, i;
818
819 ret = regmap_read(aw_dev->regmap, AW88395_PLLCTRL1_REG, ®_val);
820 if (ret)
821 return ret;
822
823 reg_val &= (~AW88395_CCO_MUX_MASK);
824 if (reg_val == AW88395_CCO_MUX_DIVIDED_VALUE) {
825 dev_dbg(aw_dev->dev, "CCO_MUX is already divider");
826 return -EPERM;
827 }
828
829 /* change mode2 */
830 ret = regmap_update_bits(aw_dev->regmap, AW88395_PLLCTRL1_REG,
831 ~AW88395_CCO_MUX_MASK, AW88395_CCO_MUX_DIVIDED_VALUE);
832 if (ret)
833 return ret;
834
835 for (i = 0; i < AW88395_DEV_SYSST_CHECK_MAX; i++) {
836 ret = aw_dev_get_iis_status(aw_dev);
837 if (ret) {
838 dev_err(aw_dev->dev, "mode2 iis signal check error");
839 usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
840 } else {
841 break;
842 }
843 }
844
845 /* change mode1 */
846 ret = regmap_update_bits(aw_dev->regmap, AW88395_PLLCTRL1_REG,
847 ~AW88395_CCO_MUX_MASK, AW88395_CCO_MUX_BYPASS_VALUE);
848 if (ret == 0) {
849 usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
850 for (i = 0; i < AW88395_DEV_SYSST_CHECK_MAX; i++) {
851 ret = aw_dev_check_mode1_pll(aw_dev);
852 if (ret < 0) {
853 dev_err(aw_dev->dev, "mode2 switch to mode1, iis signal check error");
854 usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
855 } else {
856 break;
857 }
858 }
859 }
860
861 return ret;
862 }
863
aw_dev_check_syspll(struct aw_device * aw_dev)864 static int aw_dev_check_syspll(struct aw_device *aw_dev)
865 {
866 int ret;
867
868 ret = aw_dev_check_mode1_pll(aw_dev);
869 if (ret) {
870 dev_dbg(aw_dev->dev, "mode1 check iis failed try switch to mode2 check");
871 ret = aw_dev_check_mode2_pll(aw_dev);
872 if (ret) {
873 dev_err(aw_dev->dev, "mode2 check iis failed");
874 return ret;
875 }
876 }
877
878 return ret;
879 }
880
aw_dev_check_sysst(struct aw_device * aw_dev)881 static int aw_dev_check_sysst(struct aw_device *aw_dev)
882 {
883 unsigned int check_val;
884 unsigned int reg_val;
885 int ret, i;
886
887 for (i = 0; i < AW88395_DEV_SYSST_CHECK_MAX; i++) {
888 ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, ®_val);
889 if (ret)
890 return ret;
891
892 check_val = reg_val & (~AW88395_BIT_SYSST_CHECK_MASK)
893 & AW88395_BIT_SYSST_CHECK;
894 if (check_val != AW88395_BIT_SYSST_CHECK) {
895 dev_err(aw_dev->dev, "check sysst fail, cnt=%d, reg_val=0x%04x, check:0x%x",
896 i, reg_val, AW88395_BIT_SYSST_CHECK);
897 usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
898 } else {
899 return 0;
900 }
901 }
902
903 return -EPERM;
904 }
905
aw_dev_check_sysint(struct aw_device * aw_dev)906 static int aw_dev_check_sysint(struct aw_device *aw_dev)
907 {
908 u16 reg_val;
909
910 aw_dev_get_int_status(aw_dev, ®_val);
911
912 if (reg_val & AW88395_BIT_SYSINT_CHECK) {
913 dev_err(aw_dev->dev, "pa stop check fail:0x%04x", reg_val);
914 return -EINVAL;
915 }
916
917 return 0;
918 }
919
aw_dev_get_cur_mode_st(struct aw_device * aw_dev)920 static void aw_dev_get_cur_mode_st(struct aw_device *aw_dev)
921 {
922 struct aw_profctrl_desc *profctrl_desc = &aw_dev->profctrl_desc;
923 unsigned int reg_val;
924 int ret;
925
926 ret = regmap_read(aw_dev->regmap, AW88395_SYSCTRL_REG, ®_val);
927 if (ret) {
928 dev_dbg(aw_dev->dev, "%s failed", __func__);
929 return;
930 }
931 if ((reg_val & (~AW88395_RCV_MODE_MASK)) == AW88395_RCV_MODE_RECEIVER_VALUE)
932 profctrl_desc->cur_mode = AW88395_RCV_MODE;
933 else
934 profctrl_desc->cur_mode = AW88395_NOT_RCV_MODE;
935 }
936
aw_dev_get_dsp_config(struct aw_device * aw_dev,unsigned char * dsp_cfg)937 static void aw_dev_get_dsp_config(struct aw_device *aw_dev, unsigned char *dsp_cfg)
938 {
939 unsigned int reg_val = 0;
940 int ret;
941
942 ret = regmap_read(aw_dev->regmap, AW88395_SYSCTRL_REG, ®_val);
943 if (ret) {
944 dev_dbg(aw_dev->dev, "%s failed", __func__);
945 return;
946 }
947 if (reg_val & (~AW88395_DSPBY_MASK))
948 *dsp_cfg = AW88395_DEV_DSP_BYPASS;
949 else
950 *dsp_cfg = AW88395_DEV_DSP_WORK;
951 }
952
aw_dev_select_memclk(struct aw_device * aw_dev,unsigned char flag)953 static void aw_dev_select_memclk(struct aw_device *aw_dev, unsigned char flag)
954 {
955 int ret;
956
957 switch (flag) {
958 case AW88395_DEV_MEMCLK_PLL:
959 ret = regmap_update_bits(aw_dev->regmap, AW88395_DBGCTRL_REG,
960 ~AW88395_MEM_CLKSEL_MASK,
961 AW88395_MEM_CLKSEL_DAP_HCLK_VALUE);
962 if (ret)
963 dev_err(aw_dev->dev, "memclk select pll failed");
964 break;
965 case AW88395_DEV_MEMCLK_OSC:
966 ret = regmap_update_bits(aw_dev->regmap, AW88395_DBGCTRL_REG,
967 ~AW88395_MEM_CLKSEL_MASK,
968 AW88395_MEM_CLKSEL_OSC_CLK_VALUE);
969 if (ret)
970 dev_err(aw_dev->dev, "memclk select OSC failed");
971 break;
972 default:
973 dev_err(aw_dev->dev, "unknown memclk config, flag=0x%x", flag);
974 break;
975 }
976 }
977
aw_dev_get_dsp_status(struct aw_device * aw_dev)978 static int aw_dev_get_dsp_status(struct aw_device *aw_dev)
979 {
980 unsigned int reg_val;
981 int ret;
982
983 ret = regmap_read(aw_dev->regmap, AW88395_WDT_REG, ®_val);
984 if (ret)
985 return ret;
986 if (!(reg_val & (~AW88395_WDT_CNT_MASK)))
987 ret = -EPERM;
988
989 return ret;
990 }
991
aw_dev_get_vmax(struct aw_device * aw_dev,unsigned int * vmax)992 static int aw_dev_get_vmax(struct aw_device *aw_dev, unsigned int *vmax)
993 {
994 return aw_dev_dsp_read(aw_dev, AW88395_DSP_REG_VMAX, vmax, AW88395_DSP_16_DATA);
995 }
996
aw_dev_update_reg_container(struct aw_device * aw_dev,unsigned char * data,unsigned int len)997 static int aw_dev_update_reg_container(struct aw_device *aw_dev,
998 unsigned char *data, unsigned int len)
999 {
1000 struct aw_volume_desc *vol_desc = &aw_dev->volume_desc;
1001 unsigned int read_val;
1002 int16_t *reg_data;
1003 int data_len;
1004 u16 read_vol;
1005 u16 reg_val;
1006 u8 reg_addr;
1007 int i, ret;
1008
1009 reg_data = (int16_t *)data;
1010 data_len = len >> 1;
1011
1012 if (data_len & 0x1) {
1013 dev_err(aw_dev->dev, "data len:%d unsupported", data_len);
1014 return -EINVAL;
1015 }
1016
1017 for (i = 0; i < data_len; i += 2) {
1018 reg_addr = reg_data[i];
1019 reg_val = reg_data[i + 1];
1020
1021 if (reg_addr == AW88395_SYSCTRL_REG) {
1022 ret = regmap_read(aw_dev->regmap, reg_addr, &read_val);
1023 if (ret)
1024 break;
1025 read_val &= (~AW88395_HMUTE_MASK);
1026 reg_val &= AW88395_HMUTE_MASK;
1027 reg_val |= read_val;
1028 }
1029 if (reg_addr == AW88395_HAGCCFG7_REG)
1030 reg_val &= AW88395_AGC_DSP_CTL_MASK;
1031
1032 if (reg_addr == AW88395_I2SCFG1_REG) {
1033 /* close tx */
1034 reg_val &= AW88395_I2STXEN_MASK;
1035 reg_val |= AW88395_I2STXEN_DISABLE_VALUE;
1036 }
1037
1038 if (reg_addr == AW88395_SYSCTRL2_REG) {
1039 read_vol = (reg_val & (~AW88395_VOL_MASK)) >>
1040 AW88395_VOL_START_BIT;
1041 aw_dev->volume_desc.init_volume =
1042 reg_val_to_db(read_vol);
1043 }
1044 ret = regmap_write(aw_dev->regmap, reg_addr, reg_val);
1045 if (ret)
1046 break;
1047
1048 }
1049
1050 aw_dev_get_cur_mode_st(aw_dev);
1051
1052 if (aw_dev->prof_cur != aw_dev->prof_index) {
1053 /* clear control volume when PA change profile */
1054 vol_desc->ctl_volume = 0;
1055 } else {
1056 /* keep control volume when PA start with sync mode */
1057 aw_dev_set_volume(aw_dev, vol_desc->ctl_volume);
1058 }
1059
1060 aw_dev_get_dsp_config(aw_dev, &aw_dev->dsp_cfg);
1061
1062 return ret;
1063 }
1064
aw_dev_reg_update(struct aw_device * aw_dev,unsigned char * data,unsigned int len)1065 static int aw_dev_reg_update(struct aw_device *aw_dev,
1066 unsigned char *data, unsigned int len)
1067 {
1068 int ret;
1069
1070 if (!len || !data) {
1071 dev_err(aw_dev->dev, "reg data is null or len is 0");
1072 return -EINVAL;
1073 }
1074
1075 ret = aw_dev_update_reg_container(aw_dev, data, len);
1076 if (ret) {
1077 dev_err(aw_dev->dev, "reg update failed");
1078 return ret;
1079 }
1080
1081 return 0;
1082 }
1083
aw_dev_get_ra(struct aw_cali_desc * cali_desc)1084 static int aw_dev_get_ra(struct aw_cali_desc *cali_desc)
1085 {
1086 struct aw_device *aw_dev =
1087 container_of(cali_desc, struct aw_device, cali_desc);
1088 u32 dsp_ra;
1089 int ret;
1090
1091 ret = aw_dev_dsp_read(aw_dev, AW88395_DSP_REG_CFG_ADPZ_RA,
1092 &dsp_ra, AW88395_DSP_32_DATA);
1093 if (ret) {
1094 dev_err(aw_dev->dev, "read ra error");
1095 return ret;
1096 }
1097
1098 cali_desc->ra = AW88395_DSP_RE_TO_SHOW_RE(dsp_ra,
1099 AW88395_DSP_RE_SHIFT);
1100
1101 return ret;
1102 }
1103
aw_dev_dsp_update_container(struct aw_device * aw_dev,unsigned char * data,unsigned int len,unsigned short base)1104 static int aw_dev_dsp_update_container(struct aw_device *aw_dev,
1105 unsigned char *data, unsigned int len, unsigned short base)
1106 {
1107 int i, ret;
1108
1109 #ifdef AW88395_DSP_I2C_WRITES
1110 u32 tmp_len;
1111
1112 mutex_lock(&aw_dev->dsp_lock);
1113 ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, base);
1114 if (ret)
1115 goto error_operation;
1116
1117 for (i = 0; i < len; i += AW88395_MAX_RAM_WRITE_BYTE_SIZE) {
1118 tmp_len = min(len - i, AW88395_MAX_RAM_WRITE_BYTE_SIZE);
1119 ret = regmap_raw_write(aw_dev->regmap, AW88395_DSPMDAT_REG,
1120 &data[i], tmp_len);
1121 if (ret)
1122 goto error_operation;
1123 }
1124 mutex_unlock(&aw_dev->dsp_lock);
1125 #else
1126 __be16 reg_val;
1127
1128 mutex_lock(&aw_dev->dsp_lock);
1129 /* i2c write */
1130 ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, base);
1131 if (ret)
1132 goto error_operation;
1133 for (i = 0; i < len; i += 2) {
1134 reg_val = cpu_to_be16p((u16 *)(data + i));
1135 ret = regmap_write(aw_dev->regmap, AW88395_DSPMDAT_REG,
1136 (u16)reg_val);
1137 if (ret)
1138 goto error_operation;
1139 }
1140 mutex_unlock(&aw_dev->dsp_lock);
1141 #endif
1142
1143 return 0;
1144
1145 error_operation:
1146 mutex_unlock(&aw_dev->dsp_lock);
1147 return ret;
1148 }
1149
aw_dev_dsp_update_fw(struct aw_device * aw_dev,unsigned char * data,unsigned int len)1150 static int aw_dev_dsp_update_fw(struct aw_device *aw_dev,
1151 unsigned char *data, unsigned int len)
1152 {
1153
1154 dev_dbg(aw_dev->dev, "dsp firmware len:%d", len);
1155
1156 if (!len || !data) {
1157 dev_err(aw_dev->dev, "dsp firmware data is null or len is 0");
1158 return -EINVAL;
1159 }
1160 aw_dev_dsp_update_container(aw_dev, data, len, AW88395_DSP_FW_ADDR);
1161 aw_dev->dsp_fw_len = len;
1162
1163 return 0;
1164 }
1165
aw_dev_copy_to_crc_dsp_cfg(struct aw_device * aw_dev,unsigned char * data,unsigned int size)1166 static int aw_dev_copy_to_crc_dsp_cfg(struct aw_device *aw_dev,
1167 unsigned char *data, unsigned int size)
1168 {
1169 struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg;
1170
1171 if (!crc_dsp_cfg->data) {
1172 crc_dsp_cfg->data = devm_kzalloc(aw_dev->dev, size, GFP_KERNEL);
1173 if (!crc_dsp_cfg->data)
1174 return -ENOMEM;
1175 crc_dsp_cfg->len = size;
1176 } else if (crc_dsp_cfg->len < size) {
1177 devm_kfree(aw_dev->dev, crc_dsp_cfg->data);
1178 crc_dsp_cfg->data = devm_kzalloc(aw_dev->dev, size, GFP_KERNEL);
1179 if (!crc_dsp_cfg->data)
1180 return -ENOMEM;
1181 crc_dsp_cfg->len = size;
1182 }
1183 memcpy(crc_dsp_cfg->data, data, size);
1184 swab16_array((u16 *)crc_dsp_cfg->data, size >> 1);
1185
1186 return 0;
1187 }
1188
aw_dev_dsp_update_cfg(struct aw_device * aw_dev,unsigned char * data,unsigned int len)1189 static int aw_dev_dsp_update_cfg(struct aw_device *aw_dev,
1190 unsigned char *data, unsigned int len)
1191 {
1192 int ret;
1193
1194 dev_dbg(aw_dev->dev, "dsp config len:%d", len);
1195
1196 if (!len || !data) {
1197 dev_err(aw_dev->dev, "dsp config data is null or len is 0");
1198 return -EINVAL;
1199 }
1200
1201 aw_dev_dsp_update_container(aw_dev, data, len, AW88395_DSP_CFG_ADDR);
1202 aw_dev->dsp_cfg_len = len;
1203
1204 ret = aw_dev_copy_to_crc_dsp_cfg(aw_dev, data, len);
1205 if (ret)
1206 return ret;
1207
1208 ret = aw_dev_set_vcalb(aw_dev);
1209 if (ret)
1210 return ret;
1211 ret = aw_dev_get_ra(&aw_dev->cali_desc);
1212 if (ret)
1213 return ret;
1214 ret = aw_dev_get_cali_f0_delay(aw_dev);
1215 if (ret)
1216 return ret;
1217
1218 ret = aw_dev_get_vmax(aw_dev, &aw_dev->vmax_desc.init_vmax);
1219 if (ret) {
1220 dev_err(aw_dev->dev, "get vmax failed");
1221 return ret;
1222 }
1223 dev_dbg(aw_dev->dev, "get init vmax:0x%x", aw_dev->vmax_desc.init_vmax);
1224 aw_dev->dsp_crc_st = AW88395_DSP_CRC_NA;
1225
1226 return 0;
1227 }
1228
aw_dev_check_sram(struct aw_device * aw_dev)1229 static int aw_dev_check_sram(struct aw_device *aw_dev)
1230 {
1231 unsigned int reg_val;
1232
1233 mutex_lock(&aw_dev->dsp_lock);
1234 /* check the odd bits of reg 0x40 */
1235 regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, AW88395_DSP_ODD_NUM_BIT_TEST);
1236 regmap_read(aw_dev->regmap, AW88395_DSPMADD_REG, ®_val);
1237 if (reg_val != AW88395_DSP_ODD_NUM_BIT_TEST) {
1238 dev_err(aw_dev->dev, "check reg 0x40 odd bit failed, read[0x%x] != write[0x%x]",
1239 reg_val, AW88395_DSP_ODD_NUM_BIT_TEST);
1240 goto error;
1241 }
1242
1243 /* check the even bits of reg 0x40 */
1244 regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, AW88395_DSP_EVEN_NUM_BIT_TEST);
1245 regmap_read(aw_dev->regmap, AW88395_DSPMADD_REG, ®_val);
1246 if (reg_val != AW88395_DSP_EVEN_NUM_BIT_TEST) {
1247 dev_err(aw_dev->dev, "check reg 0x40 even bit failed, read[0x%x] != write[0x%x]",
1248 reg_val, AW88395_DSP_EVEN_NUM_BIT_TEST);
1249 goto error;
1250 }
1251
1252 /* check dsp_fw_base_addr */
1253 aw_dev_dsp_write_16bit(aw_dev, AW88395_DSP_FW_ADDR, AW88395_DSP_EVEN_NUM_BIT_TEST);
1254 aw_dev_dsp_read_16bit(aw_dev, AW88395_DSP_FW_ADDR, ®_val);
1255 if (reg_val != AW88395_DSP_EVEN_NUM_BIT_TEST) {
1256 dev_err(aw_dev->dev, "check dsp fw addr failed, read[0x%x] != write[0x%x]",
1257 reg_val, AW88395_DSP_EVEN_NUM_BIT_TEST);
1258 goto error;
1259 }
1260
1261 /* check dsp_cfg_base_addr */
1262 aw_dev_dsp_write_16bit(aw_dev, AW88395_DSP_CFG_ADDR, AW88395_DSP_ODD_NUM_BIT_TEST);
1263 aw_dev_dsp_read_16bit(aw_dev, AW88395_DSP_CFG_ADDR, ®_val);
1264 if (reg_val != AW88395_DSP_ODD_NUM_BIT_TEST) {
1265 dev_err(aw_dev->dev, "check dsp cfg failed, read[0x%x] != write[0x%x]",
1266 reg_val, AW88395_DSP_ODD_NUM_BIT_TEST);
1267 goto error;
1268 }
1269 mutex_unlock(&aw_dev->dsp_lock);
1270
1271 return 0;
1272
1273 error:
1274 mutex_unlock(&aw_dev->dsp_lock);
1275 return -EPERM;
1276 }
1277
aw88395_dev_fw_update(struct aw_device * aw_dev,bool up_dsp_fw_en,bool force_up_en)1278 int aw88395_dev_fw_update(struct aw_device *aw_dev, bool up_dsp_fw_en, bool force_up_en)
1279 {
1280 struct aw_prof_desc *prof_index_desc;
1281 struct aw_sec_data_desc *sec_desc;
1282 char *prof_name;
1283 int ret;
1284
1285 if ((aw_dev->prof_cur == aw_dev->prof_index) &&
1286 (force_up_en == AW88395_FORCE_UPDATE_OFF)) {
1287 dev_dbg(aw_dev->dev, "scene no change, not update");
1288 return 0;
1289 }
1290
1291 if (aw_dev->fw_status == AW88395_DEV_FW_FAILED) {
1292 dev_err(aw_dev->dev, "fw status[%d] error", aw_dev->fw_status);
1293 return -EPERM;
1294 }
1295
1296 ret = aw88395_dev_get_prof_name(aw_dev, aw_dev->prof_index, &prof_name);
1297 if (ret)
1298 return ret;
1299
1300 dev_dbg(aw_dev->dev, "start update %s", prof_name);
1301
1302 ret = aw88395_dev_get_prof_data(aw_dev, aw_dev->prof_index, &prof_index_desc);
1303 if (ret)
1304 return ret;
1305
1306 /* update reg */
1307 sec_desc = prof_index_desc->sec_desc;
1308 ret = aw_dev_reg_update(aw_dev, sec_desc[AW88395_DATA_TYPE_REG].data,
1309 sec_desc[AW88395_DATA_TYPE_REG].len);
1310 if (ret) {
1311 dev_err(aw_dev->dev, "update reg failed");
1312 return ret;
1313 }
1314
1315 aw88395_dev_mute(aw_dev, true);
1316
1317 if (aw_dev->dsp_cfg == AW88395_DEV_DSP_WORK)
1318 aw_dev_dsp_enable(aw_dev, false);
1319
1320 aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_OSC);
1321
1322 if (up_dsp_fw_en) {
1323 ret = aw_dev_check_sram(aw_dev);
1324 if (ret) {
1325 dev_err(aw_dev->dev, "check sram failed");
1326 goto error;
1327 }
1328
1329 /* update dsp firmware */
1330 dev_dbg(aw_dev->dev, "fw_ver: [%x]", prof_index_desc->fw_ver);
1331 ret = aw_dev_dsp_update_fw(aw_dev, sec_desc[AW88395_DATA_TYPE_DSP_FW].data,
1332 sec_desc[AW88395_DATA_TYPE_DSP_FW].len);
1333 if (ret) {
1334 dev_err(aw_dev->dev, "update dsp fw failed");
1335 goto error;
1336 }
1337 }
1338
1339 /* update dsp config */
1340 ret = aw_dev_dsp_update_cfg(aw_dev, sec_desc[AW88395_DATA_TYPE_DSP_CFG].data,
1341 sec_desc[AW88395_DATA_TYPE_DSP_CFG].len);
1342 if (ret) {
1343 dev_err(aw_dev->dev, "update dsp cfg failed");
1344 goto error;
1345 }
1346
1347 aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_PLL);
1348
1349 aw_dev->prof_cur = aw_dev->prof_index;
1350
1351 return 0;
1352
1353 error:
1354 aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_PLL);
1355 return ret;
1356 }
1357 EXPORT_SYMBOL_GPL(aw88395_dev_fw_update);
1358
aw_dev_dsp_check(struct aw_device * aw_dev)1359 static int aw_dev_dsp_check(struct aw_device *aw_dev)
1360 {
1361 int ret, i;
1362
1363 switch (aw_dev->dsp_cfg) {
1364 case AW88395_DEV_DSP_BYPASS:
1365 dev_dbg(aw_dev->dev, "dsp bypass");
1366 ret = 0;
1367 break;
1368 case AW88395_DEV_DSP_WORK:
1369 aw_dev_dsp_enable(aw_dev, false);
1370 aw_dev_dsp_enable(aw_dev, true);
1371 usleep_range(AW88395_1000_US, AW88395_1000_US + 10);
1372 for (i = 0; i < AW88395_DEV_DSP_CHECK_MAX; i++) {
1373 ret = aw_dev_get_dsp_status(aw_dev);
1374 if (ret) {
1375 dev_err(aw_dev->dev, "dsp wdt status error=%d", ret);
1376 usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
1377 }
1378 }
1379 break;
1380 default:
1381 dev_err(aw_dev->dev, "unknown dsp cfg=%d", aw_dev->dsp_cfg);
1382 ret = -EINVAL;
1383 break;
1384 }
1385
1386 return ret;
1387 }
1388
aw_dev_update_cali_re(struct aw_cali_desc * cali_desc)1389 static void aw_dev_update_cali_re(struct aw_cali_desc *cali_desc)
1390 {
1391 struct aw_device *aw_dev =
1392 container_of(cali_desc, struct aw_device, cali_desc);
1393 int ret;
1394
1395 if ((aw_dev->cali_desc.cali_re < AW88395_CALI_RE_MAX) &&
1396 (aw_dev->cali_desc.cali_re > AW88395_CALI_RE_MIN)) {
1397
1398 ret = aw_dev_dsp_set_cali_re(aw_dev);
1399 if (ret)
1400 dev_err(aw_dev->dev, "set cali re failed");
1401 }
1402 }
1403
aw88395_dev_start(struct aw_device * aw_dev)1404 int aw88395_dev_start(struct aw_device *aw_dev)
1405 {
1406 int ret;
1407
1408 if (aw_dev->status == AW88395_DEV_PW_ON) {
1409 dev_info(aw_dev->dev, "already power on");
1410 return 0;
1411 }
1412 /* power on */
1413 aw_dev_pwd(aw_dev, false);
1414 usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
1415
1416 ret = aw_dev_check_syspll(aw_dev);
1417 if (ret) {
1418 dev_err(aw_dev->dev, "pll check failed cannot start");
1419 goto pll_check_fail;
1420 }
1421
1422 /* amppd on */
1423 aw_dev_amppd(aw_dev, false);
1424 usleep_range(AW88395_1000_US, AW88395_1000_US + 50);
1425
1426 /* check i2s status */
1427 ret = aw_dev_check_sysst(aw_dev);
1428 if (ret) {
1429 dev_err(aw_dev->dev, "sysst check failed");
1430 goto sysst_check_fail;
1431 }
1432
1433 if (aw_dev->dsp_cfg == AW88395_DEV_DSP_WORK) {
1434 /* dsp bypass */
1435 aw_dev_dsp_enable(aw_dev, false);
1436 ret = aw_dev_dsp_fw_check(aw_dev);
1437 if (ret)
1438 goto dev_dsp_fw_check_fail;
1439
1440 aw_dev_update_cali_re(&aw_dev->cali_desc);
1441
1442 if (aw_dev->dsp_crc_st != AW88395_DSP_CRC_OK) {
1443 ret = aw_dev_dsp_check_crc32(aw_dev);
1444 if (ret) {
1445 dev_err(aw_dev->dev, "dsp crc check failed");
1446 goto crc_check_fail;
1447 }
1448 }
1449
1450 ret = aw_dev_dsp_check(aw_dev);
1451 if (ret) {
1452 dev_err(aw_dev->dev, "dsp status check failed");
1453 goto dsp_check_fail;
1454 }
1455 } else {
1456 dev_dbg(aw_dev->dev, "start pa with dsp bypass");
1457 }
1458
1459 /* enable tx feedback */
1460 aw_dev_i2s_tx_enable(aw_dev, true);
1461
1462 /* close mute */
1463 aw88395_dev_mute(aw_dev, false);
1464 /* clear inturrupt */
1465 aw_dev_clear_int_status(aw_dev);
1466 aw_dev->status = AW88395_DEV_PW_ON;
1467
1468 return 0;
1469
1470 dsp_check_fail:
1471 crc_check_fail:
1472 aw_dev_dsp_enable(aw_dev, false);
1473 dev_dsp_fw_check_fail:
1474 sysst_check_fail:
1475 aw_dev_clear_int_status(aw_dev);
1476 aw_dev_amppd(aw_dev, true);
1477 pll_check_fail:
1478 aw_dev_pwd(aw_dev, true);
1479 aw_dev->status = AW88395_DEV_PW_OFF;
1480
1481 return ret;
1482 }
1483 EXPORT_SYMBOL_GPL(aw88395_dev_start);
1484
aw88395_dev_stop(struct aw_device * aw_dev)1485 int aw88395_dev_stop(struct aw_device *aw_dev)
1486 {
1487 struct aw_sec_data_desc *dsp_cfg =
1488 &aw_dev->prof_info.prof_desc[aw_dev->prof_cur].sec_desc[AW88395_DATA_TYPE_DSP_CFG];
1489 struct aw_sec_data_desc *dsp_fw =
1490 &aw_dev->prof_info.prof_desc[aw_dev->prof_cur].sec_desc[AW88395_DATA_TYPE_DSP_FW];
1491 int int_st = 0;
1492 int ret;
1493
1494 if (aw_dev->status == AW88395_DEV_PW_OFF) {
1495 dev_info(aw_dev->dev, "already power off");
1496 return 0;
1497 }
1498
1499 aw_dev->status = AW88395_DEV_PW_OFF;
1500
1501 /* set mute */
1502 aw88395_dev_mute(aw_dev, true);
1503 usleep_range(AW88395_4000_US, AW88395_4000_US + 100);
1504
1505 /* close tx feedback */
1506 aw_dev_i2s_tx_enable(aw_dev, false);
1507 usleep_range(AW88395_1000_US, AW88395_1000_US + 100);
1508
1509 /* check sysint state */
1510 int_st = aw_dev_check_sysint(aw_dev);
1511
1512 /* close dsp */
1513 aw_dev_dsp_enable(aw_dev, false);
1514
1515 /* enable amppd */
1516 aw_dev_amppd(aw_dev, true);
1517
1518 if (int_st < 0) {
1519 /* system status anomaly */
1520 aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_OSC);
1521 ret = aw_dev_dsp_update_fw(aw_dev, dsp_fw->data, dsp_fw->len);
1522 if (ret)
1523 dev_err(aw_dev->dev, "update dsp fw failed");
1524 ret = aw_dev_dsp_update_cfg(aw_dev, dsp_cfg->data, dsp_cfg->len);
1525 if (ret)
1526 dev_err(aw_dev->dev, "update dsp cfg failed");
1527 aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_PLL);
1528 }
1529
1530 /* set power down */
1531 aw_dev_pwd(aw_dev, true);
1532
1533 return 0;
1534 }
1535 EXPORT_SYMBOL_GPL(aw88395_dev_stop);
1536
aw88395_dev_init(struct aw_device * aw_dev,struct aw_container * aw_cfg)1537 int aw88395_dev_init(struct aw_device *aw_dev, struct aw_container *aw_cfg)
1538 {
1539 int ret;
1540
1541 if ((!aw_dev) || (!aw_cfg)) {
1542 pr_err("aw_dev is NULL or aw_cfg is NULL");
1543 return -ENOMEM;
1544 }
1545 ret = aw88395_dev_cfg_load(aw_dev, aw_cfg);
1546 if (ret) {
1547 dev_err(aw_dev->dev, "aw_dev acf parse failed");
1548 return -EINVAL;
1549 }
1550 aw_dev->fade_in_time = AW88395_1000_US / 10;
1551 aw_dev->fade_out_time = AW88395_1000_US >> 1;
1552 aw_dev->prof_cur = aw_dev->prof_info.prof_desc[0].id;
1553 aw_dev->prof_index = aw_dev->prof_info.prof_desc[0].id;
1554
1555 ret = aw88395_dev_fw_update(aw_dev, AW88395_FORCE_UPDATE_ON, AW88395_DSP_FW_UPDATE_ON);
1556 if (ret) {
1557 dev_err(aw_dev->dev, "fw update failed ret = %d\n", ret);
1558 return ret;
1559 }
1560
1561 /* set mute */
1562 aw88395_dev_mute(aw_dev, true);
1563 usleep_range(AW88395_4000_US, AW88395_4000_US + 100);
1564
1565 /* close tx feedback */
1566 aw_dev_i2s_tx_enable(aw_dev, false);
1567 usleep_range(AW88395_1000_US, AW88395_1000_US + 100);
1568
1569 /* close dsp */
1570 aw_dev_dsp_enable(aw_dev, false);
1571 /* enable amppd */
1572 aw_dev_amppd(aw_dev, true);
1573 /* set power down */
1574 aw_dev_pwd(aw_dev, true);
1575
1576 return 0;
1577 }
1578 EXPORT_SYMBOL_GPL(aw88395_dev_init);
1579
aw88395_parse_channel_dt(struct aw_device * aw_dev)1580 static void aw88395_parse_channel_dt(struct aw_device *aw_dev)
1581 {
1582 struct device_node *np = aw_dev->dev->of_node;
1583 u32 channel_value;
1584 int ret;
1585
1586 ret = of_property_read_u32(np, "awinic,audio-channel", &channel_value);
1587 if (ret) {
1588 dev_dbg(aw_dev->dev,
1589 "read audio-channel failed,use default 0");
1590 aw_dev->channel = AW88395_DEV_DEFAULT_CH;
1591 return;
1592 }
1593
1594 dev_dbg(aw_dev->dev, "read audio-channel value is: %d",
1595 channel_value);
1596 aw_dev->channel = channel_value;
1597 }
1598
aw_dev_init(struct aw_device * aw_dev)1599 static int aw_dev_init(struct aw_device *aw_dev)
1600 {
1601 aw_dev->chip_id = AW88395_CHIP_ID;
1602 /* call aw device init func */
1603 aw_dev->acf = NULL;
1604 aw_dev->prof_info.prof_desc = NULL;
1605 aw_dev->prof_info.count = 0;
1606 aw_dev->prof_info.prof_type = AW88395_DEV_NONE_TYPE_ID;
1607 aw_dev->channel = 0;
1608 aw_dev->fw_status = AW88395_DEV_FW_FAILED;
1609
1610 aw_dev->fade_step = AW88395_VOLUME_STEP_DB;
1611 aw_dev->volume_desc.ctl_volume = AW88395_VOL_DEFAULT_VALUE;
1612 aw88395_parse_channel_dt(aw_dev);
1613
1614 return 0;
1615 }
1616
aw88395_dev_get_profile_count(struct aw_device * aw_dev)1617 int aw88395_dev_get_profile_count(struct aw_device *aw_dev)
1618 {
1619 return aw_dev->prof_info.count;
1620 }
1621 EXPORT_SYMBOL_GPL(aw88395_dev_get_profile_count);
1622
aw88395_dev_get_profile_index(struct aw_device * aw_dev)1623 int aw88395_dev_get_profile_index(struct aw_device *aw_dev)
1624 {
1625 return aw_dev->prof_index;
1626 }
1627 EXPORT_SYMBOL_GPL(aw88395_dev_get_profile_index);
1628
aw88395_dev_set_profile_index(struct aw_device * aw_dev,int index)1629 int aw88395_dev_set_profile_index(struct aw_device *aw_dev, int index)
1630 {
1631 /* check the index whether is valid */
1632 if ((index >= aw_dev->prof_info.count) || (index < 0))
1633 return -EINVAL;
1634 /* check the index whether change */
1635 if (aw_dev->prof_index == index)
1636 return -EINVAL;
1637
1638 aw_dev->prof_index = index;
1639 dev_dbg(aw_dev->dev, "set prof[%s]",
1640 aw_dev->prof_info.prof_name_list[aw_dev->prof_info.prof_desc[index].id]);
1641
1642 return 0;
1643 }
1644 EXPORT_SYMBOL_GPL(aw88395_dev_set_profile_index);
1645
aw88395_dev_get_prof_name(struct aw_device * aw_dev,int index,char ** prof_name)1646 int aw88395_dev_get_prof_name(struct aw_device *aw_dev, int index, char **prof_name)
1647 {
1648 struct aw_prof_info *prof_info = &aw_dev->prof_info;
1649 struct aw_prof_desc *prof_desc;
1650
1651 if ((index >= aw_dev->prof_info.count) || (index < 0)) {
1652 dev_err(aw_dev->dev, "index[%d] overflow count[%d]",
1653 index, aw_dev->prof_info.count);
1654 return -EINVAL;
1655 }
1656
1657 prof_desc = &aw_dev->prof_info.prof_desc[index];
1658
1659 *prof_name = prof_info->prof_name_list[prof_desc->id];
1660
1661 return 0;
1662 }
1663 EXPORT_SYMBOL_GPL(aw88395_dev_get_prof_name);
1664
aw88395_dev_get_prof_data(struct aw_device * aw_dev,int index,struct aw_prof_desc ** prof_desc)1665 int aw88395_dev_get_prof_data(struct aw_device *aw_dev, int index,
1666 struct aw_prof_desc **prof_desc)
1667 {
1668 if ((index >= aw_dev->prof_info.count) || (index < 0)) {
1669 dev_err(aw_dev->dev, "%s: index[%d] overflow count[%d]\n",
1670 __func__, index, aw_dev->prof_info.count);
1671 return -EINVAL;
1672 }
1673
1674 *prof_desc = &aw_dev->prof_info.prof_desc[index];
1675
1676 return 0;
1677 }
1678 EXPORT_SYMBOL_GPL(aw88395_dev_get_prof_data);
1679
aw88395_init(struct aw_device ** aw_dev,struct i2c_client * i2c,struct regmap * regmap)1680 int aw88395_init(struct aw_device **aw_dev, struct i2c_client *i2c, struct regmap *regmap)
1681 {
1682 u16 chip_id;
1683 int ret;
1684
1685 if (*aw_dev) {
1686 dev_info(&i2c->dev, "it should be initialized here.\n");
1687 } else {
1688 *aw_dev = devm_kzalloc(&i2c->dev, sizeof(struct aw_device), GFP_KERNEL);
1689 if (!(*aw_dev))
1690 return -ENOMEM;
1691 }
1692
1693 (*aw_dev)->i2c = i2c;
1694 (*aw_dev)->dev = &i2c->dev;
1695 (*aw_dev)->regmap = regmap;
1696 mutex_init(&(*aw_dev)->dsp_lock);
1697
1698 /* read chip id */
1699 ret = aw_dev_read_chipid((*aw_dev), &chip_id);
1700 if (ret) {
1701 dev_err(&i2c->dev, "dev_read_chipid failed ret=%d", ret);
1702 return ret;
1703 }
1704
1705 switch (chip_id) {
1706 case AW88395_CHIP_ID:
1707 ret = aw_dev_init((*aw_dev));
1708 break;
1709 default:
1710 ret = -EINVAL;
1711 dev_err((*aw_dev)->dev, "unsupported device");
1712 break;
1713 }
1714
1715 return ret;
1716 }
1717 EXPORT_SYMBOL_GPL(aw88395_init);
1718
1719 MODULE_DESCRIPTION("AW88395 device lib");
1720 MODULE_LICENSE("GPL v2");
1721