1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * DesignWare MIPI DSI Host Controller v1.02 driver 4 * 5 * Copyright (c) 2016 Linaro Limited. 6 * Copyright (c) 2014-2016 HiSilicon Limited. 7 * 8 * Author: 9 * Xinliang Liu <z.liuxinliang@hisilicon.com> 10 * Xinliang Liu <xinliang.liu@linaro.org> 11 * Xinwei Kong <kong.kongxinwei@hisilicon.com> 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/component.h> 16 #include <linux/delay.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_bridge.h> 22 #include <drm/drm_device.h> 23 #include <drm/drm_encoder.h> 24 #include <drm/drm_mipi_dsi.h> 25 #include <drm/drm_of.h> 26 #include <drm/drm_print.h> 27 #include <drm/drm_probe_helper.h> 28 29 #include "dw_dsi_reg.h" 30 31 #define MAX_TX_ESC_CLK 10 32 #define ROUND(x, y) ((x) / (y) + \ 33 ((x) % (y) * 10 / (y) >= 5 ? 1 : 0)) 34 #define PHY_REF_CLK_RATE 19200000 35 #define PHY_REF_CLK_PERIOD_PS (1000000000 / (PHY_REF_CLK_RATE / 1000)) 36 37 #define encoder_to_dsi(encoder) \ 38 container_of(encoder, struct dw_dsi, encoder) 39 #define host_to_dsi(host) \ 40 container_of(host, struct dw_dsi, host) 41 42 struct mipi_phy_params { 43 u32 clk_t_lpx; 44 u32 clk_t_hs_prepare; 45 u32 clk_t_hs_zero; 46 u32 clk_t_hs_trial; 47 u32 clk_t_wakeup; 48 u32 data_t_lpx; 49 u32 data_t_hs_prepare; 50 u32 data_t_hs_zero; 51 u32 data_t_hs_trial; 52 u32 data_t_ta_go; 53 u32 data_t_ta_get; 54 u32 data_t_wakeup; 55 u32 hstx_ckg_sel; 56 u32 pll_fbd_div5f; 57 u32 pll_fbd_div1f; 58 u32 pll_fbd_2p; 59 u32 pll_enbwt; 60 u32 pll_fbd_p; 61 u32 pll_fbd_s; 62 u32 pll_pre_div1p; 63 u32 pll_pre_p; 64 u32 pll_vco_750M; 65 u32 pll_lpf_rs; 66 u32 pll_lpf_cs; 67 u32 clklp2hs_time; 68 u32 clkhs2lp_time; 69 u32 lp2hs_time; 70 u32 hs2lp_time; 71 u32 clk_to_data_delay; 72 u32 data_to_clk_delay; 73 u32 lane_byte_clk_kHz; 74 u32 clk_division; 75 }; 76 77 struct dsi_hw_ctx { 78 void __iomem *base; 79 struct clk *pclk; 80 }; 81 82 struct dw_dsi { 83 struct drm_encoder encoder; 84 struct device *dev; 85 struct mipi_dsi_host host; 86 struct drm_display_mode cur_mode; 87 struct dsi_hw_ctx *ctx; 88 struct mipi_phy_params phy; 89 90 u32 lanes; 91 enum mipi_dsi_pixel_format format; 92 unsigned long mode_flags; 93 bool enable; 94 }; 95 96 struct dsi_data { 97 struct dw_dsi dsi; 98 struct dsi_hw_ctx ctx; 99 }; 100 101 struct dsi_phy_range { 102 u32 min_range_kHz; 103 u32 max_range_kHz; 104 u32 pll_vco_750M; 105 u32 hstx_ckg_sel; 106 }; 107 108 static const struct dsi_phy_range dphy_range_info[] = { 109 { 46875, 62500, 1, 7 }, 110 { 62500, 93750, 0, 7 }, 111 { 93750, 125000, 1, 6 }, 112 { 125000, 187500, 0, 6 }, 113 { 187500, 250000, 1, 5 }, 114 { 250000, 375000, 0, 5 }, 115 { 375000, 500000, 1, 4 }, 116 { 500000, 750000, 0, 4 }, 117 { 750000, 1000000, 1, 0 }, 118 { 1000000, 1500000, 0, 0 } 119 }; 120 121 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) 122 { 123 u32 ref_clk_ps = PHY_REF_CLK_PERIOD_PS; 124 u32 tmp_kHz = req_kHz; 125 u32 i = 0; 126 u32 q_pll = 1; 127 u32 m_pll = 0; 128 u32 n_pll = 0; 129 u32 r_pll = 1; 130 u32 m_n = 0; 131 u32 m_n_int = 0; 132 u32 f_kHz = 0; 133 u64 temp; 134 135 /* 136 * Find a rate >= req_kHz. 137 */ 138 do { 139 f_kHz = tmp_kHz; 140 141 for (i = 0; i < ARRAY_SIZE(dphy_range_info); i++) 142 if (f_kHz >= dphy_range_info[i].min_range_kHz && 143 f_kHz <= dphy_range_info[i].max_range_kHz) 144 break; 145 146 if (i == ARRAY_SIZE(dphy_range_info)) { 147 DRM_ERROR("%dkHz out of range\n", f_kHz); 148 return 0; 149 } 150 151 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; 152 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; 153 154 if (phy->hstx_ckg_sel <= 7 && 155 phy->hstx_ckg_sel >= 4) 156 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); 157 158 temp = f_kHz * (u64)q_pll * (u64)ref_clk_ps; 159 m_n_int = div64_u64_rem(temp, 1000000000, &temp); 160 m_n = div_u64(temp, 100000000); 161 162 if (m_n_int % 2 == 0) { 163 if (m_n * 6 >= 50) { 164 n_pll = 2; 165 m_pll = (m_n_int + 1) * n_pll; 166 } else if (m_n * 6 >= 30) { 167 n_pll = 3; 168 m_pll = m_n_int * n_pll + 2; 169 } else { 170 n_pll = 1; 171 m_pll = m_n_int * n_pll; 172 } 173 } else { 174 if (m_n * 6 >= 50) { 175 n_pll = 1; 176 m_pll = (m_n_int + 1) * n_pll; 177 } else if (m_n * 6 >= 30) { 178 n_pll = 1; 179 m_pll = (m_n_int + 1) * n_pll; 180 } else if (m_n * 6 >= 10) { 181 n_pll = 3; 182 m_pll = m_n_int * n_pll + 1; 183 } else { 184 n_pll = 2; 185 m_pll = m_n_int * n_pll; 186 } 187 } 188 189 if (n_pll == 1) { 190 phy->pll_fbd_p = 0; 191 phy->pll_pre_div1p = 1; 192 } else { 193 phy->pll_fbd_p = n_pll; 194 phy->pll_pre_div1p = 0; 195 } 196 197 if (phy->pll_fbd_2p <= 7 && phy->pll_fbd_2p >= 4) 198 r_pll = 0x10 >> (7 - phy->pll_fbd_2p); 199 200 if (m_pll == 2) { 201 phy->pll_pre_p = 0; 202 phy->pll_fbd_s = 0; 203 phy->pll_fbd_div1f = 0; 204 phy->pll_fbd_div5f = 1; 205 } else if (m_pll >= 2 * 2 * r_pll && m_pll <= 2 * 4 * r_pll) { 206 phy->pll_pre_p = m_pll / (2 * r_pll); 207 phy->pll_fbd_s = 0; 208 phy->pll_fbd_div1f = 1; 209 phy->pll_fbd_div5f = 0; 210 } else if (m_pll >= 2 * 5 * r_pll && m_pll <= 2 * 150 * r_pll) { 211 if (((m_pll / (2 * r_pll)) % 2) == 0) { 212 phy->pll_pre_p = 213 (m_pll / (2 * r_pll)) / 2 - 1; 214 phy->pll_fbd_s = 215 (m_pll / (2 * r_pll)) % 2 + 2; 216 } else { 217 phy->pll_pre_p = 218 (m_pll / (2 * r_pll)) / 2; 219 phy->pll_fbd_s = 220 (m_pll / (2 * r_pll)) % 2; 221 } 222 phy->pll_fbd_div1f = 0; 223 phy->pll_fbd_div5f = 0; 224 } else { 225 phy->pll_pre_p = 0; 226 phy->pll_fbd_s = 0; 227 phy->pll_fbd_div1f = 0; 228 phy->pll_fbd_div5f = 1; 229 } 230 231 f_kHz = div64_u64((u64)1000000000 * (u64)m_pll, 232 (u64)ref_clk_ps * (u64)n_pll * (u64)q_pll); 233 if (f_kHz >= req_kHz) 234 break; 235 236 tmp_kHz += 10; 237 238 } while (true); 239 240 return f_kHz; 241 } 242 243 static void dsi_get_phy_params(u32 phy_req_kHz, 244 struct mipi_phy_params *phy) 245 { 246 u32 ref_clk_ps = PHY_REF_CLK_PERIOD_PS; 247 u32 phy_rate_kHz; 248 u32 ui; 249 250 memset(phy, 0, sizeof(*phy)); 251 252 phy_rate_kHz = dsi_calc_phy_rate(phy_req_kHz, phy); 253 if (!phy_rate_kHz) 254 return; 255 256 ui = 1000000 / phy_rate_kHz; 257 258 phy->clk_t_lpx = ROUND(50, 8 * ui); 259 phy->clk_t_hs_prepare = ROUND(133, 16 * ui) - 1; 260 261 phy->clk_t_hs_zero = ROUND(262, 8 * ui); 262 phy->clk_t_hs_trial = 2 * (ROUND(60, 8 * ui) - 1); 263 phy->clk_t_wakeup = ROUND(1000000, (ref_clk_ps / 1000) - 1); 264 if (phy->clk_t_wakeup > 0xff) 265 phy->clk_t_wakeup = 0xff; 266 phy->data_t_wakeup = phy->clk_t_wakeup; 267 phy->data_t_lpx = phy->clk_t_lpx; 268 phy->data_t_hs_prepare = ROUND(125 + 10 * ui, 16 * ui) - 1; 269 phy->data_t_hs_zero = ROUND(105 + 6 * ui, 8 * ui); 270 phy->data_t_hs_trial = 2 * (ROUND(60 + 4 * ui, 8 * ui) - 1); 271 phy->data_t_ta_go = 3; 272 phy->data_t_ta_get = 4; 273 274 phy->pll_enbwt = 1; 275 phy->clklp2hs_time = ROUND(407, 8 * ui) + 12; 276 phy->clkhs2lp_time = ROUND(105 + 12 * ui, 8 * ui); 277 phy->lp2hs_time = ROUND(240 + 12 * ui, 8 * ui) + 1; 278 phy->hs2lp_time = phy->clkhs2lp_time; 279 phy->clk_to_data_delay = 1 + phy->clklp2hs_time; 280 phy->data_to_clk_delay = ROUND(60 + 52 * ui, 8 * ui) + 281 phy->clkhs2lp_time; 282 283 phy->lane_byte_clk_kHz = phy_rate_kHz / 8; 284 phy->clk_division = 285 DIV_ROUND_UP(phy->lane_byte_clk_kHz, MAX_TX_ESC_CLK); 286 } 287 288 static u32 dsi_get_dpi_color_coding(enum mipi_dsi_pixel_format format) 289 { 290 u32 val; 291 292 /* 293 * TODO: only support RGB888 now, to support more 294 */ 295 switch (format) { 296 case MIPI_DSI_FMT_RGB888: 297 val = DSI_24BITS_1; 298 break; 299 default: 300 val = DSI_24BITS_1; 301 break; 302 } 303 304 return val; 305 } 306 307 /* 308 * dsi phy reg write function 309 */ 310 static void dsi_phy_tst_set(void __iomem *base, u32 reg, u32 val) 311 { 312 u32 reg_write = 0x10000 + reg; 313 314 /* 315 * latch reg first 316 */ 317 writel(reg_write, base + PHY_TST_CTRL1); 318 writel(0x02, base + PHY_TST_CTRL0); 319 writel(0x00, base + PHY_TST_CTRL0); 320 321 /* 322 * then latch value 323 */ 324 writel(val, base + PHY_TST_CTRL1); 325 writel(0x02, base + PHY_TST_CTRL0); 326 writel(0x00, base + PHY_TST_CTRL0); 327 } 328 329 static void dsi_set_phy_timer(void __iomem *base, 330 struct mipi_phy_params *phy, 331 u32 lanes) 332 { 333 u32 val; 334 335 /* 336 * Set lane value and phy stop wait time. 337 */ 338 val = (lanes - 1) | (PHY_STOP_WAIT_TIME << 8); 339 writel(val, base + PHY_IF_CFG); 340 341 /* 342 * Set phy clk division. 343 */ 344 val = readl(base + CLKMGR_CFG) | phy->clk_division; 345 writel(val, base + CLKMGR_CFG); 346 347 /* 348 * Set lp and hs switching params. 349 */ 350 dw_update_bits(base + PHY_TMR_CFG, 24, MASK(8), phy->hs2lp_time); 351 dw_update_bits(base + PHY_TMR_CFG, 16, MASK(8), phy->lp2hs_time); 352 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10), 353 phy->clkhs2lp_time); 354 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10), 355 phy->clklp2hs_time); 356 dw_update_bits(base + CLK_DATA_TMR_CFG, 8, MASK(8), 357 phy->data_to_clk_delay); 358 dw_update_bits(base + CLK_DATA_TMR_CFG, 0, MASK(8), 359 phy->clk_to_data_delay); 360 } 361 362 static void dsi_set_mipi_phy(void __iomem *base, 363 struct mipi_phy_params *phy, 364 u32 lanes) 365 { 366 u32 delay_count; 367 u32 val; 368 u32 i; 369 370 /* phy timer setting */ 371 dsi_set_phy_timer(base, phy, lanes); 372 373 /* 374 * Reset to clean up phy tst params. 375 */ 376 writel(0, base + PHY_RSTZ); 377 writel(0, base + PHY_TST_CTRL0); 378 writel(1, base + PHY_TST_CTRL0); 379 writel(0, base + PHY_TST_CTRL0); 380 381 /* 382 * Clock lane timing control setting: TLPX, THS-PREPARE, 383 * THS-ZERO, THS-TRAIL, TWAKEUP. 384 */ 385 dsi_phy_tst_set(base, CLK_TLPX, phy->clk_t_lpx); 386 dsi_phy_tst_set(base, CLK_THS_PREPARE, phy->clk_t_hs_prepare); 387 dsi_phy_tst_set(base, CLK_THS_ZERO, phy->clk_t_hs_zero); 388 dsi_phy_tst_set(base, CLK_THS_TRAIL, phy->clk_t_hs_trial); 389 dsi_phy_tst_set(base, CLK_TWAKEUP, phy->clk_t_wakeup); 390 391 /* 392 * Data lane timing control setting: TLPX, THS-PREPARE, 393 * THS-ZERO, THS-TRAIL, TTA-GO, TTA-GET, TWAKEUP. 394 */ 395 for (i = 0; i < lanes; i++) { 396 dsi_phy_tst_set(base, DATA_TLPX(i), phy->data_t_lpx); 397 dsi_phy_tst_set(base, DATA_THS_PREPARE(i), 398 phy->data_t_hs_prepare); 399 dsi_phy_tst_set(base, DATA_THS_ZERO(i), phy->data_t_hs_zero); 400 dsi_phy_tst_set(base, DATA_THS_TRAIL(i), phy->data_t_hs_trial); 401 dsi_phy_tst_set(base, DATA_TTA_GO(i), phy->data_t_ta_go); 402 dsi_phy_tst_set(base, DATA_TTA_GET(i), phy->data_t_ta_get); 403 dsi_phy_tst_set(base, DATA_TWAKEUP(i), phy->data_t_wakeup); 404 } 405 406 /* 407 * physical configuration: I, pll I, pll II, pll III, 408 * pll IV, pll V. 409 */ 410 dsi_phy_tst_set(base, PHY_CFG_I, phy->hstx_ckg_sel); 411 val = (phy->pll_fbd_div5f << 5) + (phy->pll_fbd_div1f << 4) + 412 (phy->pll_fbd_2p << 1) + phy->pll_enbwt; 413 dsi_phy_tst_set(base, PHY_CFG_PLL_I, val); 414 dsi_phy_tst_set(base, PHY_CFG_PLL_II, phy->pll_fbd_p); 415 dsi_phy_tst_set(base, PHY_CFG_PLL_III, phy->pll_fbd_s); 416 val = (phy->pll_pre_div1p << 7) + phy->pll_pre_p; 417 dsi_phy_tst_set(base, PHY_CFG_PLL_IV, val); 418 val = (5 << 5) + (phy->pll_vco_750M << 4) + (phy->pll_lpf_rs << 2) + 419 phy->pll_lpf_cs; 420 dsi_phy_tst_set(base, PHY_CFG_PLL_V, val); 421 422 writel(PHY_ENABLECLK, base + PHY_RSTZ); 423 udelay(1); 424 writel(PHY_ENABLECLK | PHY_UNSHUTDOWNZ, base + PHY_RSTZ); 425 udelay(1); 426 writel(PHY_ENABLECLK | PHY_UNRSTZ | PHY_UNSHUTDOWNZ, base + PHY_RSTZ); 427 usleep_range(1000, 1500); 428 429 /* 430 * wait for phy's clock ready 431 */ 432 delay_count = 100; 433 while (delay_count) { 434 val = readl(base + PHY_STATUS); 435 if ((BIT(0) | BIT(2)) & val) 436 break; 437 438 udelay(1); 439 delay_count--; 440 } 441 442 if (!delay_count) 443 DRM_INFO("phylock and phystopstateclklane is not ready.\n"); 444 } 445 446 static void dsi_set_mode_timing(void __iomem *base, 447 u32 lane_byte_clk_kHz, 448 struct drm_display_mode *mode, 449 enum mipi_dsi_pixel_format format) 450 { 451 u32 hfp, hbp, hsw, vfp, vbp, vsw; 452 u32 hline_time; 453 u32 hsa_time; 454 u32 hbp_time; 455 u32 pixel_clk_kHz; 456 int htot, vtot; 457 u32 val; 458 u64 tmp; 459 460 val = dsi_get_dpi_color_coding(format); 461 writel(val, base + DPI_COLOR_CODING); 462 463 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 1 : 0) << 2; 464 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC ? 1 : 0) << 1; 465 writel(val, base + DPI_CFG_POL); 466 467 /* 468 * The DSI IP accepts vertical timing using lines as normal, 469 * but horizontal timing is a mixture of pixel-clocks for the 470 * active region and byte-lane clocks for the blanking-related 471 * timings. hfp is specified as the total hline_time in byte- 472 * lane clocks minus hsa, hbp and active. 473 */ 474 pixel_clk_kHz = mode->clock; 475 htot = mode->htotal; 476 vtot = mode->vtotal; 477 hfp = mode->hsync_start - mode->hdisplay; 478 hbp = mode->htotal - mode->hsync_end; 479 hsw = mode->hsync_end - mode->hsync_start; 480 vfp = mode->vsync_start - mode->vdisplay; 481 vbp = mode->vtotal - mode->vsync_end; 482 vsw = mode->vsync_end - mode->vsync_start; 483 if (vsw > 15) { 484 DRM_DEBUG_DRIVER("vsw exceeded 15\n"); 485 vsw = 15; 486 } 487 488 hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz; 489 hbp_time = (hbp * lane_byte_clk_kHz) / pixel_clk_kHz; 490 tmp = (u64)htot * (u64)lane_byte_clk_kHz; 491 hline_time = DIV_ROUND_UP_ULL(tmp, pixel_clk_kHz); 492 493 /* all specified in byte-lane clocks */ 494 writel(hsa_time, base + VID_HSA_TIME); 495 writel(hbp_time, base + VID_HBP_TIME); 496 writel(hline_time, base + VID_HLINE_TIME); 497 498 writel(vsw, base + VID_VSA_LINES); 499 writel(vbp, base + VID_VBP_LINES); 500 writel(vfp, base + VID_VFP_LINES); 501 writel(mode->vdisplay, base + VID_VACTIVE_LINES); 502 writel(mode->hdisplay, base + VID_PKT_SIZE); 503 504 DRM_DEBUG_DRIVER("htot=%d, hfp=%d, hbp=%d, hsw=%d\n", 505 htot, hfp, hbp, hsw); 506 DRM_DEBUG_DRIVER("vtol=%d, vfp=%d, vbp=%d, vsw=%d\n", 507 vtot, vfp, vbp, vsw); 508 DRM_DEBUG_DRIVER("hsa_time=%d, hbp_time=%d, hline_time=%d\n", 509 hsa_time, hbp_time, hline_time); 510 } 511 512 static void dsi_set_video_mode(void __iomem *base, unsigned long flags) 513 { 514 u32 val; 515 u32 mode_mask = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 516 MIPI_DSI_MODE_VIDEO_SYNC_PULSE; 517 u32 non_burst_sync_pulse = MIPI_DSI_MODE_VIDEO | 518 MIPI_DSI_MODE_VIDEO_SYNC_PULSE; 519 u32 non_burst_sync_event = MIPI_DSI_MODE_VIDEO; 520 521 /* 522 * choose video mode type 523 */ 524 if ((flags & mode_mask) == non_burst_sync_pulse) 525 val = DSI_NON_BURST_SYNC_PULSES; 526 else if ((flags & mode_mask) == non_burst_sync_event) 527 val = DSI_NON_BURST_SYNC_EVENTS; 528 else 529 val = DSI_BURST_SYNC_PULSES_1; 530 writel(val, base + VID_MODE_CFG); 531 532 writel(PHY_TXREQUESTCLKHS, base + LPCLK_CTRL); 533 writel(DSI_VIDEO_MODE, base + MODE_CFG); 534 } 535 536 static void dsi_mipi_init(struct dw_dsi *dsi) 537 { 538 struct dsi_hw_ctx *ctx = dsi->ctx; 539 struct mipi_phy_params *phy = &dsi->phy; 540 struct drm_display_mode *mode = &dsi->cur_mode; 541 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 542 void __iomem *base = ctx->base; 543 u32 dphy_req_kHz; 544 545 /* 546 * count phy params 547 */ 548 dphy_req_kHz = mode->clock * bpp / dsi->lanes; 549 dsi_get_phy_params(dphy_req_kHz, phy); 550 551 /* reset Core */ 552 writel(RESET, base + PWR_UP); 553 554 /* set dsi phy params */ 555 dsi_set_mipi_phy(base, phy, dsi->lanes); 556 557 /* set dsi mode timing */ 558 dsi_set_mode_timing(base, phy->lane_byte_clk_kHz, mode, dsi->format); 559 560 /* set dsi video mode */ 561 dsi_set_video_mode(base, dsi->mode_flags); 562 563 /* dsi wake up */ 564 writel(POWERUP, base + PWR_UP); 565 566 DRM_DEBUG_DRIVER("lanes=%d, pixel_clk=%d kHz, bytes_freq=%d kHz\n", 567 dsi->lanes, mode->clock, phy->lane_byte_clk_kHz); 568 } 569 570 static void dsi_encoder_disable(struct drm_encoder *encoder) 571 { 572 struct dw_dsi *dsi = encoder_to_dsi(encoder); 573 struct dsi_hw_ctx *ctx = dsi->ctx; 574 void __iomem *base = ctx->base; 575 576 if (!dsi->enable) 577 return; 578 579 writel(0, base + PWR_UP); 580 writel(0, base + LPCLK_CTRL); 581 writel(0, base + PHY_RSTZ); 582 clk_disable_unprepare(ctx->pclk); 583 584 dsi->enable = false; 585 } 586 587 static void dsi_encoder_enable(struct drm_encoder *encoder) 588 { 589 struct dw_dsi *dsi = encoder_to_dsi(encoder); 590 struct dsi_hw_ctx *ctx = dsi->ctx; 591 int ret; 592 593 if (dsi->enable) 594 return; 595 596 ret = clk_prepare_enable(ctx->pclk); 597 if (ret) { 598 DRM_ERROR("fail to enable pclk: %d\n", ret); 599 return; 600 } 601 602 dsi_mipi_init(dsi); 603 604 dsi->enable = true; 605 } 606 607 static enum drm_mode_status dsi_encoder_phy_mode_valid( 608 struct drm_encoder *encoder, 609 const struct drm_display_mode *mode) 610 { 611 struct dw_dsi *dsi = encoder_to_dsi(encoder); 612 struct mipi_phy_params phy; 613 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 614 u32 req_kHz, act_kHz, lane_byte_clk_kHz; 615 616 /* Calculate the lane byte clk using the adjusted mode clk */ 617 memset(&phy, 0, sizeof(phy)); 618 req_kHz = mode->clock * bpp / dsi->lanes; 619 act_kHz = dsi_calc_phy_rate(req_kHz, &phy); 620 lane_byte_clk_kHz = act_kHz / 8; 621 622 DRM_DEBUG_DRIVER("Checking mode %ix%i-%i@%i clock: %i...", 623 mode->hdisplay, mode->vdisplay, bpp, 624 drm_mode_vrefresh(mode), mode->clock); 625 626 /* 627 * Make sure the adjusted mode clock and the lane byte clk 628 * have a common denominator base frequency 629 */ 630 if (mode->clock/dsi->lanes == lane_byte_clk_kHz/3) { 631 DRM_DEBUG_DRIVER("OK!\n"); 632 return MODE_OK; 633 } 634 635 DRM_DEBUG_DRIVER("BAD!\n"); 636 return MODE_BAD; 637 } 638 639 static enum drm_mode_status dsi_encoder_mode_valid(struct drm_encoder *encoder, 640 const struct drm_display_mode *mode) 641 642 { 643 const struct drm_crtc_helper_funcs *crtc_funcs = NULL; 644 struct drm_crtc *crtc = NULL; 645 struct drm_display_mode adj_mode; 646 enum drm_mode_status ret; 647 648 /* 649 * The crtc might adjust the mode, so go through the 650 * possible crtcs (technically just one) and call 651 * mode_fixup to figure out the adjusted mode before we 652 * validate it. 653 */ 654 drm_for_each_crtc(crtc, encoder->dev) { 655 /* 656 * reset adj_mode to the mode value each time, 657 * so we don't adjust the mode twice 658 */ 659 drm_mode_init(&adj_mode, mode); 660 661 crtc_funcs = crtc->helper_private; 662 if (crtc_funcs && crtc_funcs->mode_fixup) 663 if (!crtc_funcs->mode_fixup(crtc, mode, &adj_mode)) 664 return MODE_BAD; 665 666 ret = dsi_encoder_phy_mode_valid(encoder, &adj_mode); 667 if (ret != MODE_OK) 668 return ret; 669 } 670 return MODE_OK; 671 } 672 673 static void dsi_encoder_mode_set(struct drm_encoder *encoder, 674 struct drm_display_mode *mode, 675 struct drm_display_mode *adj_mode) 676 { 677 struct dw_dsi *dsi = encoder_to_dsi(encoder); 678 679 drm_mode_copy(&dsi->cur_mode, adj_mode); 680 } 681 682 static int dsi_encoder_atomic_check(struct drm_encoder *encoder, 683 struct drm_crtc_state *crtc_state, 684 struct drm_connector_state *conn_state) 685 { 686 /* do nothing */ 687 return 0; 688 } 689 690 static const struct drm_encoder_funcs dw_encoder_funcs = { 691 .destroy = drm_encoder_cleanup, 692 }; 693 694 static const struct drm_encoder_helper_funcs dw_encoder_helper_funcs = { 695 .atomic_check = dsi_encoder_atomic_check, 696 .mode_valid = dsi_encoder_mode_valid, 697 .mode_set = dsi_encoder_mode_set, 698 .enable = dsi_encoder_enable, 699 .disable = dsi_encoder_disable 700 }; 701 702 static int dw_drm_encoder_init(struct device *dev, 703 struct drm_device *drm_dev, 704 struct drm_encoder *encoder) 705 { 706 int ret; 707 u32 crtc_mask = drm_of_find_possible_crtcs(drm_dev, dev->of_node); 708 709 if (!crtc_mask) { 710 DRM_ERROR("failed to find crtc mask\n"); 711 return -EINVAL; 712 } 713 714 encoder->possible_crtcs = crtc_mask; 715 ret = drm_encoder_init(drm_dev, encoder, &dw_encoder_funcs, 716 DRM_MODE_ENCODER_DSI, NULL); 717 if (ret) { 718 DRM_ERROR("failed to init dsi encoder\n"); 719 return ret; 720 } 721 722 drm_encoder_helper_add(encoder, &dw_encoder_helper_funcs); 723 724 return 0; 725 } 726 727 static const struct component_ops dsi_ops; 728 static int dsi_host_attach(struct mipi_dsi_host *host, 729 struct mipi_dsi_device *mdsi) 730 { 731 struct dw_dsi *dsi = host_to_dsi(host); 732 struct device *dev = host->dev; 733 int ret; 734 735 if (mdsi->lanes < 1 || mdsi->lanes > 4) { 736 DRM_ERROR("dsi device params invalid\n"); 737 return -EINVAL; 738 } 739 740 dsi->lanes = mdsi->lanes; 741 dsi->format = mdsi->format; 742 dsi->mode_flags = mdsi->mode_flags; 743 744 ret = component_add(dev, &dsi_ops); 745 if (ret) 746 return ret; 747 748 return 0; 749 } 750 751 static int dsi_host_detach(struct mipi_dsi_host *host, 752 struct mipi_dsi_device *mdsi) 753 { 754 struct device *dev = host->dev; 755 756 component_del(dev, &dsi_ops); 757 758 return 0; 759 } 760 761 static const struct mipi_dsi_host_ops dsi_host_ops = { 762 .attach = dsi_host_attach, 763 .detach = dsi_host_detach, 764 }; 765 766 static int dsi_host_init(struct device *dev, struct dw_dsi *dsi) 767 { 768 struct mipi_dsi_host *host = &dsi->host; 769 int ret; 770 771 host->dev = dev; 772 host->ops = &dsi_host_ops; 773 ret = mipi_dsi_host_register(host); 774 if (ret) { 775 DRM_ERROR("failed to register dsi host\n"); 776 return ret; 777 } 778 779 return 0; 780 } 781 782 static int dsi_bridge_init(struct drm_device *dev, struct dw_dsi *dsi) 783 { 784 struct drm_encoder *encoder = &dsi->encoder; 785 struct drm_bridge *bridge __free(drm_bridge_put) = NULL; 786 struct device_node *np = dsi->dev->of_node; 787 788 /* 789 * Get the endpoint node. In our case, dsi has one output port1 790 * to which the external HDMI bridge is connected. 791 */ 792 bridge = of_drm_get_bridge_by_endpoint(np, 1, 0); 793 if (IS_ERR(bridge)) 794 return PTR_ERR(bridge); 795 796 /* associate the bridge to dsi encoder */ 797 return drm_bridge_attach(encoder, bridge, NULL, 0); 798 } 799 800 static int dsi_bind(struct device *dev, struct device *master, void *data) 801 { 802 struct dsi_data *ddata = dev_get_drvdata(dev); 803 struct dw_dsi *dsi = &ddata->dsi; 804 struct drm_device *drm_dev = data; 805 int ret; 806 807 ret = dw_drm_encoder_init(dev, drm_dev, &dsi->encoder); 808 if (ret) 809 return ret; 810 811 ret = dsi_bridge_init(drm_dev, dsi); 812 if (ret) 813 return ret; 814 815 return 0; 816 } 817 818 static void dsi_unbind(struct device *dev, struct device *master, void *data) 819 { 820 /* do nothing */ 821 } 822 823 static const struct component_ops dsi_ops = { 824 .bind = dsi_bind, 825 .unbind = dsi_unbind, 826 }; 827 828 static int dsi_parse_dt(struct platform_device *pdev, struct dw_dsi *dsi) 829 { 830 struct dsi_hw_ctx *ctx = dsi->ctx; 831 832 ctx->pclk = devm_clk_get(&pdev->dev, "pclk"); 833 if (IS_ERR(ctx->pclk)) { 834 DRM_ERROR("failed to get pclk clock\n"); 835 return PTR_ERR(ctx->pclk); 836 } 837 838 ctx->base = devm_platform_ioremap_resource(pdev, 0); 839 if (IS_ERR(ctx->base)) { 840 DRM_ERROR("failed to remap dsi io region\n"); 841 return PTR_ERR(ctx->base); 842 } 843 844 return 0; 845 } 846 847 static int dsi_probe(struct platform_device *pdev) 848 { 849 struct dsi_data *data; 850 struct dw_dsi *dsi; 851 struct dsi_hw_ctx *ctx; 852 int ret; 853 854 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 855 if (!data) { 856 DRM_ERROR("failed to allocate dsi data.\n"); 857 return -ENOMEM; 858 } 859 dsi = &data->dsi; 860 ctx = &data->ctx; 861 dsi->ctx = ctx; 862 dsi->dev = &pdev->dev; 863 864 ret = dsi_parse_dt(pdev, dsi); 865 if (ret) 866 return ret; 867 868 platform_set_drvdata(pdev, data); 869 870 ret = dsi_host_init(&pdev->dev, dsi); 871 if (ret) 872 return ret; 873 874 return 0; 875 } 876 877 static void dsi_remove(struct platform_device *pdev) 878 { 879 struct dsi_data *data = platform_get_drvdata(pdev); 880 struct dw_dsi *dsi = &data->dsi; 881 882 mipi_dsi_host_unregister(&dsi->host); 883 } 884 885 static const struct of_device_id dsi_of_match[] = { 886 {.compatible = "hisilicon,hi6220-dsi"}, 887 { } 888 }; 889 MODULE_DEVICE_TABLE(of, dsi_of_match); 890 891 static struct platform_driver dsi_driver = { 892 .probe = dsi_probe, 893 .remove = dsi_remove, 894 .driver = { 895 .name = "dw-dsi", 896 .of_match_table = dsi_of_match, 897 }, 898 }; 899 900 module_platform_driver(dsi_driver); 901 902 MODULE_AUTHOR("Xinliang Liu <xinliang.liu@linaro.org>"); 903 MODULE_AUTHOR("Xinliang Liu <z.liuxinliang@hisilicon.com>"); 904 MODULE_AUTHOR("Xinwei Kong <kong.kongxinwei@hisilicon.com>"); 905 MODULE_DESCRIPTION("DesignWare MIPI DSI Host Controller v1.02 driver"); 906 MODULE_LICENSE("GPL v2"); 907