1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * TI SN65DSI83,84,85 driver
4 *
5 * Currently supported:
6 * - SN65DSI83
7 * = 1x Single-link DSI ~ 1x Single-link LVDS
8 * - Supported
9 * - Single-link LVDS mode tested
10 * - SN65DSI84
11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS
12 * - Supported
13 * - Dual-link LVDS mode tested
14 * - 2x Single-link LVDS mode unsupported
15 * (should be easy to add by someone who has the HW)
16 * - SN65DSI85
17 * = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS
18 * - Unsupported
19 * (should be easy to add by someone who has the HW)
20 *
21 * Copyright (C) 2021 Marek Vasut <marex@denx.de>
22 *
23 * Based on previous work of:
24 * Valentin Raevsky <valentin@compulab.co.il>
25 * Philippe Schenker <philippe.schenker@toradex.com>
26 */
27
28 #include <linux/bits.h>
29 #include <linux/clk.h>
30 #include <linux/gpio/consumer.h>
31 #include <linux/i2c.h>
32 #include <linux/media-bus-format.h>
33 #include <linux/module.h>
34 #include <linux/of.h>
35 #include <linux/of_graph.h>
36 #include <linux/regmap.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/timer.h>
39 #include <linux/workqueue.h>
40
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_bridge.h>
43 #include <drm/drm_bridge_helper.h>
44 #include <drm/drm_mipi_dsi.h>
45 #include <drm/drm_of.h>
46 #include <drm/drm_print.h>
47 #include <drm/drm_probe_helper.h>
48
49 /* ID registers */
50 #define REG_ID(n) (0x00 + (n))
51 /* Reset and clock registers */
52 #define REG_RC_RESET 0x09
53 #define REG_RC_RESET_SOFT_RESET BIT(0)
54 #define REG_RC_LVDS_PLL 0x0a
55 #define REG_RC_LVDS_PLL_PLL_EN_STAT BIT(7)
56 #define REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n) (((n) & 0x7) << 1)
57 #define REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY BIT(0)
58 #define REG_RC_DSI_CLK 0x0b
59 #define REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n) (((n) & 0x1f) << 3)
60 #define REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n) ((n) & 0x3)
61 #define REG_RC_PLL_EN 0x0d
62 #define REG_RC_PLL_EN_PLL_EN BIT(0)
63 /* DSI registers */
64 #define REG_DSI_LANE 0x10
65 #define REG_DSI_LANE_LEFT_RIGHT_PIXELS BIT(7) /* DSI85-only */
66 #define REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL 0 /* DSI85-only */
67 #define REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE BIT(6) /* DSI85-only */
68 #define REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE BIT(5)
69 #define REG_DSI_LANE_CHA_DSI_LANES(n) (((n) & 0x3) << 3)
70 #define REG_DSI_LANE_CHB_DSI_LANES(n) (((n) & 0x3) << 1)
71 #define REG_DSI_LANE_SOT_ERR_TOL_DIS BIT(0)
72 #define REG_DSI_EQ 0x11
73 #define REG_DSI_EQ_CHA_DSI_DATA_EQ(n) (((n) & 0x3) << 6)
74 #define REG_DSI_EQ_CHA_DSI_CLK_EQ(n) (((n) & 0x3) << 2)
75 #define REG_DSI_CLK 0x12
76 #define REG_DSI_CLK_CHA_DSI_CLK_RANGE(n) ((n) & 0xff)
77 /* LVDS registers */
78 #define REG_LVDS_FMT 0x18
79 #define REG_LVDS_FMT_DE_NEG_POLARITY BIT(7)
80 #define REG_LVDS_FMT_HS_NEG_POLARITY BIT(6)
81 #define REG_LVDS_FMT_VS_NEG_POLARITY BIT(5)
82 #define REG_LVDS_FMT_LVDS_LINK_CFG BIT(4) /* 0:AB 1:A-only */
83 #define REG_LVDS_FMT_CHA_24BPP_MODE BIT(3)
84 #define REG_LVDS_FMT_CHB_24BPP_MODE BIT(2)
85 #define REG_LVDS_FMT_CHA_24BPP_FORMAT1 BIT(1)
86 #define REG_LVDS_FMT_CHB_24BPP_FORMAT1 BIT(0)
87 #define REG_LVDS_VCOM 0x19
88 #define REG_LVDS_VCOM_CHA_LVDS_VOCM BIT(6)
89 #define REG_LVDS_VCOM_CHB_LVDS_VOCM BIT(4)
90 #define REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n) (((n) & 0x3) << 2)
91 #define REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n) ((n) & 0x3)
92 #define REG_LVDS_LANE 0x1a
93 #define REG_LVDS_LANE_EVEN_ODD_SWAP BIT(6)
94 #define REG_LVDS_LANE_CHA_REVERSE_LVDS BIT(5)
95 #define REG_LVDS_LANE_CHB_REVERSE_LVDS BIT(4)
96 #define REG_LVDS_LANE_CHA_LVDS_TERM BIT(1)
97 #define REG_LVDS_LANE_CHB_LVDS_TERM BIT(0)
98 #define REG_LVDS_CM 0x1b
99 #define REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n) (((n) & 0x3) << 4)
100 #define REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n) ((n) & 0x3)
101 /* Video registers */
102 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW 0x20
103 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH 0x21
104 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW 0x24
105 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x25
106 #define REG_VID_CHA_SYNC_DELAY_LOW 0x28
107 #define REG_VID_CHA_SYNC_DELAY_HIGH 0x29
108 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW 0x2c
109 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2d
110 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW 0x30
111 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31
112 #define REG_VID_CHA_HORIZONTAL_BACK_PORCH 0x34
113 #define REG_VID_CHA_VERTICAL_BACK_PORCH 0x36
114 #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38
115 #define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a
116 #define REG_VID_CHA_TEST_PATTERN 0x3c
117 /* IRQ registers */
118 #define REG_IRQ_GLOBAL 0xe0
119 #define REG_IRQ_GLOBAL_IRQ_EN BIT(0)
120 #define REG_IRQ_EN 0xe1
121 #define REG_IRQ_EN_CHA_SYNCH_ERR_EN BIT(7)
122 #define REG_IRQ_EN_CHA_CRC_ERR_EN BIT(6)
123 #define REG_IRQ_EN_CHA_UNC_ECC_ERR_EN BIT(5)
124 #define REG_IRQ_EN_CHA_COR_ECC_ERR_EN BIT(4)
125 #define REG_IRQ_EN_CHA_LLP_ERR_EN BIT(3)
126 #define REG_IRQ_EN_CHA_SOT_BIT_ERR_EN BIT(2)
127 #define REG_IRQ_EN_CHA_PLL_UNLOCK_EN BIT(0)
128 #define REG_IRQ_STAT 0xe5
129 #define REG_IRQ_STAT_CHA_SYNCH_ERR BIT(7)
130 #define REG_IRQ_STAT_CHA_CRC_ERR BIT(6)
131 #define REG_IRQ_STAT_CHA_UNC_ECC_ERR BIT(5)
132 #define REG_IRQ_STAT_CHA_COR_ECC_ERR BIT(4)
133 #define REG_IRQ_STAT_CHA_LLP_ERR BIT(3)
134 #define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2)
135 #define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0)
136
137 enum sn65dsi83_channel {
138 CHANNEL_A,
139 CHANNEL_B
140 };
141
142 enum sn65dsi83_lvds_term {
143 OHM_100,
144 OHM_200
145 };
146
147 enum sn65dsi83_model {
148 MODEL_SN65DSI83,
149 MODEL_SN65DSI84,
150 };
151
152 struct sn65dsi83 {
153 struct drm_bridge bridge;
154 struct device *dev;
155 struct regmap *regmap;
156 struct mipi_dsi_device *dsi;
157 struct drm_bridge *panel_bridge;
158 struct gpio_desc *enable_gpio;
159 struct regulator *vcc;
160 bool lvds_dual_link;
161 bool lvds_dual_link_even_odd_swap;
162 int lvds_vod_swing_conf[2];
163 int lvds_term_conf[2];
164 int irq;
165 struct delayed_work monitor_work;
166 struct work_struct reset_work;
167 };
168
169 static const struct regmap_range sn65dsi83_readable_ranges[] = {
170 regmap_reg_range(REG_ID(0), REG_ID(8)),
171 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK),
172 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN),
173 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK),
174 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM),
175 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
176 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH),
177 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
178 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH),
179 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW,
180 REG_VID_CHA_SYNC_DELAY_HIGH),
181 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
182 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH),
183 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
184 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH),
185 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH,
186 REG_VID_CHA_HORIZONTAL_BACK_PORCH),
187 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH,
188 REG_VID_CHA_VERTICAL_BACK_PORCH),
189 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
190 REG_VID_CHA_HORIZONTAL_FRONT_PORCH),
191 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH,
192 REG_VID_CHA_VERTICAL_FRONT_PORCH),
193 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN),
194 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN),
195 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
196 };
197
198 static const struct regmap_access_table sn65dsi83_readable_table = {
199 .yes_ranges = sn65dsi83_readable_ranges,
200 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges),
201 };
202
203 static const struct regmap_range sn65dsi83_writeable_ranges[] = {
204 regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK),
205 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN),
206 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK),
207 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM),
208 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
209 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH),
210 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
211 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH),
212 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW,
213 REG_VID_CHA_SYNC_DELAY_HIGH),
214 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
215 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH),
216 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
217 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH),
218 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH,
219 REG_VID_CHA_HORIZONTAL_BACK_PORCH),
220 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH,
221 REG_VID_CHA_VERTICAL_BACK_PORCH),
222 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
223 REG_VID_CHA_HORIZONTAL_FRONT_PORCH),
224 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH,
225 REG_VID_CHA_VERTICAL_FRONT_PORCH),
226 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN),
227 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN),
228 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
229 };
230
231 static const struct regmap_access_table sn65dsi83_writeable_table = {
232 .yes_ranges = sn65dsi83_writeable_ranges,
233 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges),
234 };
235
236 static const struct regmap_range sn65dsi83_volatile_ranges[] = {
237 regmap_reg_range(REG_RC_RESET, REG_RC_RESET),
238 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL),
239 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
240 };
241
242 static const struct regmap_access_table sn65dsi83_volatile_table = {
243 .yes_ranges = sn65dsi83_volatile_ranges,
244 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges),
245 };
246
247 static const struct regmap_config sn65dsi83_regmap_config = {
248 .reg_bits = 8,
249 .val_bits = 8,
250 .rd_table = &sn65dsi83_readable_table,
251 .wr_table = &sn65dsi83_writeable_table,
252 .volatile_table = &sn65dsi83_volatile_table,
253 .cache_type = REGCACHE_MAPLE,
254 .max_register = REG_IRQ_STAT,
255 };
256
257 static const int lvds_vod_swing_data_table[2][4][2] = {
258 { /* 100 Ohm */
259 { 180000, 313000 },
260 { 215000, 372000 },
261 { 250000, 430000 },
262 { 290000, 488000 },
263 },
264 { /* 200 Ohm */
265 { 150000, 261000 },
266 { 200000, 346000 },
267 { 250000, 428000 },
268 { 300000, 511000 },
269 },
270 };
271
272 static const int lvds_vod_swing_clock_table[2][4][2] = {
273 { /* 100 Ohm */
274 { 140000, 244000 },
275 { 168000, 290000 },
276 { 195000, 335000 },
277 { 226000, 381000 },
278 },
279 { /* 200 Ohm */
280 { 117000, 204000 },
281 { 156000, 270000 },
282 { 195000, 334000 },
283 { 234000, 399000 },
284 },
285 };
286
bridge_to_sn65dsi83(struct drm_bridge * bridge)287 static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge)
288 {
289 return container_of(bridge, struct sn65dsi83, bridge);
290 }
291
sn65dsi83_attach(struct drm_bridge * bridge,struct drm_encoder * encoder,enum drm_bridge_attach_flags flags)292 static int sn65dsi83_attach(struct drm_bridge *bridge,
293 struct drm_encoder *encoder,
294 enum drm_bridge_attach_flags flags)
295 {
296 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
297
298 return drm_bridge_attach(encoder, ctx->panel_bridge,
299 &ctx->bridge, flags);
300 }
301
sn65dsi83_detach(struct drm_bridge * bridge)302 static void sn65dsi83_detach(struct drm_bridge *bridge)
303 {
304 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
305
306 if (!ctx->dsi)
307 return;
308
309 ctx->dsi = NULL;
310 }
311
sn65dsi83_get_lvds_range(struct sn65dsi83 * ctx,const struct drm_display_mode * mode)312 static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx,
313 const struct drm_display_mode *mode)
314 {
315 /*
316 * The encoding of the LVDS_CLK_RANGE is as follows:
317 * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz
318 * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz
319 * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz
320 * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz
321 * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz
322 * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz
323 * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that
324 * the ends of the ranges are clamped to the supported range. Since
325 * sn65dsi83_mode_valid() already filters the valid modes and limits
326 * the clock to 25..154 MHz, the range calculation can be simplified
327 * as follows:
328 */
329 int mode_clock = mode->clock;
330
331 if (ctx->lvds_dual_link)
332 mode_clock /= 2;
333
334 return (mode_clock - 12500) / 25000;
335 }
336
sn65dsi83_get_dsi_range(struct sn65dsi83 * ctx,const struct drm_display_mode * mode)337 static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx,
338 const struct drm_display_mode *mode)
339 {
340 /*
341 * The encoding of the CHA_DSI_CLK_RANGE is as follows:
342 * 0x00 through 0x07 - Reserved
343 * 0x08 - 40 <= DSI_CLK < 45 MHz
344 * 0x09 - 45 <= DSI_CLK < 50 MHz
345 * ...
346 * 0x63 - 495 <= DSI_CLK < 500 MHz
347 * 0x64 - 500 MHz
348 * 0x65 through 0xFF - Reserved
349 * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz.
350 * The DSI clock are calculated as:
351 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2
352 * the 2 is there because the bus is DDR.
353 */
354 return clamp((unsigned int)mode->clock *
355 mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) /
356 ctx->dsi->lanes / 2, 40000U, 500000U) / 5000U;
357 }
358
sn65dsi83_get_dsi_div(struct sn65dsi83 * ctx)359 static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx)
360 {
361 /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */
362 unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format);
363
364 dsi_div /= ctx->dsi->lanes;
365
366 if (!ctx->lvds_dual_link)
367 dsi_div /= 2;
368
369 return dsi_div - 1;
370 }
371
sn65dsi83_reset_pipe(struct sn65dsi83 * sn65dsi83)372 static int sn65dsi83_reset_pipe(struct sn65dsi83 *sn65dsi83)
373 {
374 struct drm_modeset_acquire_ctx ctx;
375 int err;
376
377 /*
378 * Reset active outputs of the related CRTC.
379 *
380 * This way, drm core will reconfigure each components in the CRTC
381 * outputs path. In our case, this will force the previous component to
382 * go back in LP11 mode and so allow the reconfiguration of SN65DSI83
383 * bridge.
384 *
385 * Keep the lock during the whole operation to be atomic.
386 */
387
388 drm_modeset_acquire_init(&ctx, 0);
389
390 dev_warn(sn65dsi83->dev, "reset the pipe\n");
391
392 retry:
393 err = drm_bridge_helper_reset_crtc(&sn65dsi83->bridge, &ctx);
394 if (err == -EDEADLK) {
395 drm_modeset_backoff(&ctx);
396 goto retry;
397 }
398
399 drm_modeset_drop_locks(&ctx);
400 drm_modeset_acquire_fini(&ctx);
401
402 return 0;
403 }
404
sn65dsi83_reset_work(struct work_struct * ws)405 static void sn65dsi83_reset_work(struct work_struct *ws)
406 {
407 struct sn65dsi83 *ctx = container_of(ws, struct sn65dsi83, reset_work);
408 int ret;
409 int idx;
410
411 if (!drm_bridge_enter(&ctx->bridge, &idx))
412 return;
413
414 /* Reset the pipe */
415 ret = sn65dsi83_reset_pipe(ctx);
416 if (ret) {
417 dev_err(ctx->dev, "reset pipe failed %pe\n", ERR_PTR(ret));
418 return;
419 }
420 if (ctx->irq)
421 enable_irq(ctx->irq);
422
423 drm_bridge_exit(idx);
424 }
425
sn65dsi83_handle_errors(struct sn65dsi83 * ctx)426 static void sn65dsi83_handle_errors(struct sn65dsi83 *ctx)
427 {
428 unsigned int irq_stat;
429 int ret;
430 int idx;
431
432 if (!drm_bridge_enter(&ctx->bridge, &idx))
433 return;
434
435 /*
436 * Schedule a reset in case of:
437 * - the bridge doesn't answer
438 * - the bridge signals an error
439 */
440
441 ret = regmap_read(ctx->regmap, REG_IRQ_STAT, &irq_stat);
442
443 /*
444 * Some hardware (Toradex Verdin AM62) is known to report the
445 * PLL_UNLOCK error interrupt while working without visible
446 * problems. In lack of a reliable way to discriminate such cases
447 * from user-visible PLL_UNLOCK cases, ignore that bit entirely.
448 */
449 if (ret || irq_stat & ~REG_IRQ_STAT_CHA_PLL_UNLOCK) {
450 /*
451 * IRQ acknowledged is not always possible (the bridge can be in
452 * a state where it doesn't answer anymore). To prevent an
453 * interrupt storm, disable interrupt. The interrupt will be
454 * after the reset.
455 */
456 if (ctx->irq)
457 disable_irq_nosync(ctx->irq);
458
459 schedule_work(&ctx->reset_work);
460 }
461
462 drm_bridge_exit(idx);
463 }
464
sn65dsi83_monitor_work(struct work_struct * work)465 static void sn65dsi83_monitor_work(struct work_struct *work)
466 {
467 struct sn65dsi83 *ctx = container_of(to_delayed_work(work),
468 struct sn65dsi83, monitor_work);
469
470 sn65dsi83_handle_errors(ctx);
471
472 schedule_delayed_work(&ctx->monitor_work, msecs_to_jiffies(1000));
473 }
474
sn65dsi83_monitor_start(struct sn65dsi83 * ctx)475 static void sn65dsi83_monitor_start(struct sn65dsi83 *ctx)
476 {
477 schedule_delayed_work(&ctx->monitor_work, msecs_to_jiffies(1000));
478 }
479
sn65dsi83_monitor_stop(struct sn65dsi83 * ctx)480 static void sn65dsi83_monitor_stop(struct sn65dsi83 *ctx)
481 {
482 cancel_delayed_work_sync(&ctx->monitor_work);
483 }
484
485 /*
486 * Release resources taken by sn65dsi83_atomic_pre_enable().
487 *
488 * Invoked by sn65dsi83_atomic_disable() normally, or by devres after
489 * sn65dsi83_remove() in case this happens befora atomic_disable.
490 */
sn65dsi83_release_resources(void * data)491 static void sn65dsi83_release_resources(void *data)
492 {
493 struct sn65dsi83 *ctx = (struct sn65dsi83 *)data;
494 int ret;
495
496 if (ctx->irq) {
497 /* Disable irq */
498 regmap_write(ctx->regmap, REG_IRQ_EN, 0x0);
499 regmap_write(ctx->regmap, REG_IRQ_GLOBAL, 0x0);
500 } else {
501 /* Stop the polling task */
502 sn65dsi83_monitor_stop(ctx);
503 }
504
505 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */
506 gpiod_set_value_cansleep(ctx->enable_gpio, 0);
507 usleep_range(10000, 11000);
508
509 ret = regulator_disable(ctx->vcc);
510 if (ret)
511 dev_err(ctx->dev, "Failed to disable vcc: %d\n", ret);
512
513 regcache_mark_dirty(ctx->regmap);
514 }
515
sn65dsi83_atomic_pre_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)516 static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge,
517 struct drm_atomic_state *state)
518 {
519 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
520 const unsigned int dual_factor = ctx->lvds_dual_link ? 2 : 1;
521 const struct drm_bridge_state *bridge_state;
522 const struct drm_crtc_state *crtc_state;
523 const struct drm_display_mode *mode;
524 struct drm_connector *connector;
525 struct drm_crtc *crtc;
526 bool lvds_format_24bpp;
527 bool lvds_format_jeida;
528 unsigned int pval;
529 __le16 le16val;
530 u16 val;
531 int ret;
532 int idx;
533
534 if (!drm_bridge_enter(bridge, &idx))
535 return;
536
537 ret = regulator_enable(ctx->vcc);
538 if (ret) {
539 dev_err(ctx->dev, "Failed to enable vcc: %d\n", ret);
540 goto err_exit;
541 }
542
543 /* Deassert reset */
544 gpiod_set_value_cansleep(ctx->enable_gpio, 1);
545 usleep_range(10000, 11000);
546
547 /* Get the LVDS format from the bridge state. */
548 bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
549
550 switch (bridge_state->output_bus_cfg.format) {
551 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
552 lvds_format_24bpp = false;
553 lvds_format_jeida = true;
554 break;
555 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
556 lvds_format_24bpp = true;
557 lvds_format_jeida = true;
558 break;
559 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
560 lvds_format_24bpp = true;
561 lvds_format_jeida = false;
562 break;
563 default:
564 /*
565 * Some bridges still don't set the correct
566 * LVDS bus pixel format, use SPWG24 default
567 * format until those are fixed.
568 */
569 lvds_format_24bpp = true;
570 lvds_format_jeida = false;
571 dev_warn(ctx->dev,
572 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n",
573 bridge_state->output_bus_cfg.format);
574 break;
575 }
576
577 /*
578 * Retrieve the CRTC adjusted mode. This requires a little dance to go
579 * from the bridge to the encoder, to the connector and to the CRTC.
580 */
581 connector = drm_atomic_get_new_connector_for_encoder(state,
582 bridge->encoder);
583 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
584 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
585 mode = &crtc_state->adjusted_mode;
586
587 /* Clear reset, disable PLL */
588 regmap_write(ctx->regmap, REG_RC_RESET, 0x00);
589 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
590
591 /* Reference clock derived from DSI link clock. */
592 regmap_write(ctx->regmap, REG_RC_LVDS_PLL,
593 REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) |
594 REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY);
595 regmap_write(ctx->regmap, REG_DSI_CLK,
596 REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx, mode)));
597 regmap_write(ctx->regmap, REG_RC_DSI_CLK,
598 REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx)));
599
600 /* Set number of DSI lanes and LVDS link config. */
601 regmap_write(ctx->regmap, REG_DSI_LANE,
602 REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE |
603 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi->lanes - 1)) |
604 /* CHB is DSI85-only, set to default on DSI83/DSI84 */
605 REG_DSI_LANE_CHB_DSI_LANES(3));
606 /* No equalization. */
607 regmap_write(ctx->regmap, REG_DSI_EQ, 0x00);
608
609 /* Set up sync signal polarity. */
610 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ?
611 REG_LVDS_FMT_HS_NEG_POLARITY : 0) |
612 (mode->flags & DRM_MODE_FLAG_NVSYNC ?
613 REG_LVDS_FMT_VS_NEG_POLARITY : 0);
614 val |= bridge_state->output_bus_cfg.flags & DRM_BUS_FLAG_DE_LOW ?
615 REG_LVDS_FMT_DE_NEG_POLARITY : 0;
616
617 /* Set up bits-per-pixel, 18bpp or 24bpp. */
618 if (lvds_format_24bpp) {
619 val |= REG_LVDS_FMT_CHA_24BPP_MODE;
620 if (ctx->lvds_dual_link)
621 val |= REG_LVDS_FMT_CHB_24BPP_MODE;
622 }
623
624 /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */
625 if (lvds_format_jeida) {
626 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1;
627 if (ctx->lvds_dual_link)
628 val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1;
629 }
630
631 /* Set up LVDS output config (DSI84,DSI85) */
632 if (!ctx->lvds_dual_link)
633 val |= REG_LVDS_FMT_LVDS_LINK_CFG;
634
635 regmap_write(ctx->regmap, REG_LVDS_FMT, val);
636 regmap_write(ctx->regmap, REG_LVDS_VCOM,
637 REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_A]) |
638 REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_B]));
639 regmap_write(ctx->regmap, REG_LVDS_LANE,
640 (ctx->lvds_dual_link_even_odd_swap ?
641 REG_LVDS_LANE_EVEN_ODD_SWAP : 0) |
642 (ctx->lvds_term_conf[CHANNEL_A] ?
643 REG_LVDS_LANE_CHA_LVDS_TERM : 0) |
644 (ctx->lvds_term_conf[CHANNEL_B] ?
645 REG_LVDS_LANE_CHB_LVDS_TERM : 0));
646 regmap_write(ctx->regmap, REG_LVDS_CM, 0x00);
647
648 le16val = cpu_to_le16(mode->hdisplay);
649 regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
650 &le16val, 2);
651 le16val = cpu_to_le16(mode->vdisplay);
652 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
653 &le16val, 2);
654 /* 32 + 1 pixel clock to ensure proper operation */
655 le16val = cpu_to_le16(32 + 1);
656 regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2);
657 le16val = cpu_to_le16((mode->hsync_end - mode->hsync_start) / dual_factor);
658 regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
659 &le16val, 2);
660 le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start);
661 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
662 &le16val, 2);
663 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH,
664 (mode->htotal - mode->hsync_end) / dual_factor);
665 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH,
666 mode->vtotal - mode->vsync_end);
667 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
668 (mode->hsync_start - mode->hdisplay) / dual_factor);
669 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH,
670 mode->vsync_start - mode->vdisplay);
671 regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00);
672
673 /* Enable PLL */
674 regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN);
675 usleep_range(3000, 4000);
676 ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval,
677 pval & REG_RC_LVDS_PLL_PLL_EN_STAT,
678 1000, 100000);
679 if (ret) {
680 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret);
681 /* On failure, disable PLL again and exit. */
682 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
683 goto err_add_action;
684 }
685
686 /* Trigger reset after CSR register update. */
687 regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET);
688
689 /* Wait for 10ms after soft reset as specified in datasheet */
690 usleep_range(10000, 12000);
691
692 err_add_action:
693 devm_add_action(ctx->dev, sn65dsi83_release_resources, ctx);
694 err_exit:
695 drm_bridge_exit(idx);
696 }
697
sn65dsi83_atomic_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)698 static void sn65dsi83_atomic_enable(struct drm_bridge *bridge,
699 struct drm_atomic_state *state)
700 {
701 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
702 unsigned int pval;
703 int idx;
704
705 if (!drm_bridge_enter(bridge, &idx))
706 return;
707
708 /* Clear all errors that got asserted during initialization. */
709 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
710 regmap_write(ctx->regmap, REG_IRQ_STAT, pval);
711
712 /* Wait for 1ms and check for errors in status register */
713 usleep_range(1000, 1100);
714 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
715 if (pval)
716 dev_err(ctx->dev, "Unexpected link status 0x%02x\n", pval);
717
718 if (ctx->irq) {
719 /* Enable irq to detect errors */
720 regmap_write(ctx->regmap, REG_IRQ_GLOBAL, REG_IRQ_GLOBAL_IRQ_EN);
721 regmap_write(ctx->regmap, REG_IRQ_EN, 0xff & ~REG_IRQ_EN_CHA_PLL_UNLOCK_EN);
722 } else {
723 /* Use the polling task */
724 sn65dsi83_monitor_start(ctx);
725 }
726
727 drm_bridge_exit(idx);
728 }
729
sn65dsi83_atomic_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)730 static void sn65dsi83_atomic_disable(struct drm_bridge *bridge,
731 struct drm_atomic_state *state)
732 {
733 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
734 int idx;
735
736 if (!drm_bridge_enter(bridge, &idx))
737 return;
738
739 devm_release_action(ctx->dev, sn65dsi83_release_resources, ctx);
740
741 drm_bridge_exit(idx);
742 }
743
744 static enum drm_mode_status
sn65dsi83_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)745 sn65dsi83_mode_valid(struct drm_bridge *bridge,
746 const struct drm_display_info *info,
747 const struct drm_display_mode *mode)
748 {
749 /* LVDS output clock range 25..154 MHz */
750 if (mode->clock < 25000)
751 return MODE_CLOCK_LOW;
752 if (mode->clock > 154000)
753 return MODE_CLOCK_HIGH;
754
755 return MODE_OK;
756 }
757
758 #define MAX_INPUT_SEL_FORMATS 1
759
760 static u32 *
sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,u32 output_fmt,unsigned int * num_input_fmts)761 sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
762 struct drm_bridge_state *bridge_state,
763 struct drm_crtc_state *crtc_state,
764 struct drm_connector_state *conn_state,
765 u32 output_fmt,
766 unsigned int *num_input_fmts)
767 {
768 u32 *input_fmts;
769
770 *num_input_fmts = 0;
771
772 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
773 GFP_KERNEL);
774 if (!input_fmts)
775 return NULL;
776
777 /* This is the DSI-end bus format */
778 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
779 *num_input_fmts = 1;
780
781 return input_fmts;
782 }
783
784 static const struct drm_bridge_funcs sn65dsi83_funcs = {
785 .attach = sn65dsi83_attach,
786 .detach = sn65dsi83_detach,
787 .atomic_enable = sn65dsi83_atomic_enable,
788 .atomic_pre_enable = sn65dsi83_atomic_pre_enable,
789 .atomic_disable = sn65dsi83_atomic_disable,
790 .mode_valid = sn65dsi83_mode_valid,
791
792 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
793 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
794 .atomic_reset = drm_atomic_helper_bridge_reset,
795 .atomic_get_input_bus_fmts = sn65dsi83_atomic_get_input_bus_fmts,
796 };
797
sn65dsi83_select_lvds_vod_swing(struct device * dev,u32 lvds_vod_swing_data[2],u32 lvds_vod_swing_clk[2],u8 lvds_term)798 static int sn65dsi83_select_lvds_vod_swing(struct device *dev,
799 u32 lvds_vod_swing_data[2], u32 lvds_vod_swing_clk[2], u8 lvds_term)
800 {
801 int i;
802
803 for (i = 0; i <= 3; i++) {
804 if (lvds_vod_swing_data_table[lvds_term][i][0] >= lvds_vod_swing_data[0] &&
805 lvds_vod_swing_data_table[lvds_term][i][1] <= lvds_vod_swing_data[1] &&
806 lvds_vod_swing_clock_table[lvds_term][i][0] >= lvds_vod_swing_clk[0] &&
807 lvds_vod_swing_clock_table[lvds_term][i][1] <= lvds_vod_swing_clk[1])
808 return i;
809 }
810
811 dev_err(dev, "failed to find appropriate LVDS_VOD_SWING configuration\n");
812 return -EINVAL;
813 }
814
sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 * ctx,int channel)815 static int sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 *ctx, int channel)
816 {
817 struct device *dev = ctx->dev;
818 struct device_node *endpoint;
819 int endpoint_reg;
820 /* Set so the property can be freely selected if not defined */
821 u32 lvds_vod_swing_data[2] = { 0, 1000000 };
822 u32 lvds_vod_swing_clk[2] = { 0, 1000000 };
823 /* Set default near end terminataion to 200 Ohm */
824 u32 lvds_term = 200;
825 int lvds_vod_swing_conf;
826 int ret = 0;
827 int ret_data;
828 int ret_clock;
829
830 if (channel == CHANNEL_A)
831 endpoint_reg = 2;
832 else
833 endpoint_reg = 3;
834
835 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, endpoint_reg, -1);
836
837 of_property_read_u32(endpoint, "ti,lvds-termination-ohms", &lvds_term);
838 if (lvds_term == 100)
839 ctx->lvds_term_conf[channel] = OHM_100;
840 else if (lvds_term == 200)
841 ctx->lvds_term_conf[channel] = OHM_200;
842 else {
843 ret = -EINVAL;
844 goto exit;
845 }
846
847 ret_data = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-data-microvolt",
848 lvds_vod_swing_data, ARRAY_SIZE(lvds_vod_swing_data));
849 if (ret_data != 0 && ret_data != -EINVAL) {
850 ret = ret_data;
851 goto exit;
852 }
853
854 ret_clock = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-clock-microvolt",
855 lvds_vod_swing_clk, ARRAY_SIZE(lvds_vod_swing_clk));
856 if (ret_clock != 0 && ret_clock != -EINVAL) {
857 ret = ret_clock;
858 goto exit;
859 }
860
861 /* Use default value if both properties are NOT defined. */
862 if (ret_data == -EINVAL && ret_clock == -EINVAL)
863 lvds_vod_swing_conf = 0x1;
864
865 /* Use lookup table if any of the two properties is defined. */
866 if (!ret_data || !ret_clock) {
867 lvds_vod_swing_conf = sn65dsi83_select_lvds_vod_swing(dev, lvds_vod_swing_data,
868 lvds_vod_swing_clk, ctx->lvds_term_conf[channel]);
869 if (lvds_vod_swing_conf < 0) {
870 ret = lvds_vod_swing_conf;
871 goto exit;
872 }
873 }
874
875 ctx->lvds_vod_swing_conf[channel] = lvds_vod_swing_conf;
876 ret = 0;
877 exit:
878 of_node_put(endpoint);
879 return ret;
880 }
881
sn65dsi83_parse_dt(struct sn65dsi83 * ctx,enum sn65dsi83_model model)882 static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model)
883 {
884 struct drm_bridge *panel_bridge;
885 struct device *dev = ctx->dev;
886 int ret;
887
888 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_A);
889 if (ret < 0)
890 return ret;
891
892 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_B);
893 if (ret < 0)
894 return ret;
895
896 ctx->lvds_dual_link = false;
897 ctx->lvds_dual_link_even_odd_swap = false;
898 if (model != MODEL_SN65DSI83) {
899 struct device_node *port2, *port3;
900 int dual_link;
901
902 port2 = of_graph_get_port_by_id(dev->of_node, 2);
903 port3 = of_graph_get_port_by_id(dev->of_node, 3);
904 dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3);
905 of_node_put(port2);
906 of_node_put(port3);
907
908 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) {
909 ctx->lvds_dual_link = true;
910 /* Odd pixels to LVDS Channel A, even pixels to B */
911 ctx->lvds_dual_link_even_odd_swap = false;
912 } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
913 ctx->lvds_dual_link = true;
914 /* Even pixels to LVDS Channel A, odd pixels to B */
915 ctx->lvds_dual_link_even_odd_swap = true;
916 }
917 }
918
919 panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
920 if (IS_ERR(panel_bridge))
921 return dev_err_probe(dev, PTR_ERR(panel_bridge), "Failed to get panel bridge\n");
922
923 ctx->panel_bridge = panel_bridge;
924
925 ctx->vcc = devm_regulator_get(dev, "vcc");
926 if (IS_ERR(ctx->vcc))
927 return dev_err_probe(dev, PTR_ERR(ctx->vcc),
928 "Failed to get supply 'vcc'\n");
929
930 return 0;
931 }
932
sn65dsi83_host_attach(struct sn65dsi83 * ctx)933 static int sn65dsi83_host_attach(struct sn65dsi83 *ctx)
934 {
935 struct device *dev = ctx->dev;
936 struct device_node *host_node;
937 struct device_node *endpoint;
938 struct mipi_dsi_device *dsi;
939 struct mipi_dsi_host *host;
940 const struct mipi_dsi_device_info info = {
941 .type = "sn65dsi83",
942 .channel = 0,
943 .node = NULL,
944 };
945 int dsi_lanes, ret;
946
947 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
948 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4);
949 host_node = of_graph_get_remote_port_parent(endpoint);
950 host = of_find_mipi_dsi_host_by_node(host_node);
951 of_node_put(host_node);
952 of_node_put(endpoint);
953
954 if (!host)
955 return -EPROBE_DEFER;
956
957 if (dsi_lanes < 0)
958 return dsi_lanes;
959
960 dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
961 if (IS_ERR(dsi))
962 return dev_err_probe(dev, PTR_ERR(dsi),
963 "failed to create dsi device\n");
964
965 ctx->dsi = dsi;
966
967 dsi->lanes = dsi_lanes;
968 dsi->format = MIPI_DSI_FMT_RGB888;
969 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
970 MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP |
971 MIPI_DSI_MODE_VIDEO_NO_HSA | MIPI_DSI_MODE_NO_EOT_PACKET;
972
973 ret = devm_mipi_dsi_attach(dev, dsi);
974 if (ret < 0) {
975 dev_err(dev, "failed to attach dsi to host: %d\n", ret);
976 return ret;
977 }
978
979 return 0;
980 }
981
sn65dsi83_irq(int irq,void * data)982 static irqreturn_t sn65dsi83_irq(int irq, void *data)
983 {
984 struct sn65dsi83 *ctx = data;
985
986 sn65dsi83_handle_errors(ctx);
987 return IRQ_HANDLED;
988 }
989
sn65dsi83_probe(struct i2c_client * client)990 static int sn65dsi83_probe(struct i2c_client *client)
991 {
992 const struct i2c_device_id *id = i2c_client_get_device_id(client);
993 struct device *dev = &client->dev;
994 enum sn65dsi83_model model;
995 struct sn65dsi83 *ctx;
996 int ret;
997
998 ctx = devm_drm_bridge_alloc(dev, struct sn65dsi83, bridge, &sn65dsi83_funcs);
999 if (IS_ERR(ctx))
1000 return PTR_ERR(ctx);
1001
1002 ctx->dev = dev;
1003 INIT_WORK(&ctx->reset_work, sn65dsi83_reset_work);
1004 INIT_DELAYED_WORK(&ctx->monitor_work, sn65dsi83_monitor_work);
1005
1006 if (dev->of_node) {
1007 model = (enum sn65dsi83_model)(uintptr_t)
1008 of_device_get_match_data(dev);
1009 } else {
1010 model = id->driver_data;
1011 }
1012
1013 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */
1014 ctx->enable_gpio = devm_gpiod_get_optional(ctx->dev, "enable",
1015 GPIOD_OUT_LOW);
1016 if (IS_ERR(ctx->enable_gpio))
1017 return dev_err_probe(dev, PTR_ERR(ctx->enable_gpio), "failed to get enable GPIO\n");
1018
1019 usleep_range(10000, 11000);
1020
1021 ret = sn65dsi83_parse_dt(ctx, model);
1022 if (ret)
1023 return ret;
1024
1025 ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config);
1026 if (IS_ERR(ctx->regmap))
1027 return dev_err_probe(dev, PTR_ERR(ctx->regmap), "failed to get regmap\n");
1028
1029 if (client->irq) {
1030 ctx->irq = client->irq;
1031 ret = devm_request_threaded_irq(ctx->dev, ctx->irq, NULL, sn65dsi83_irq,
1032 IRQF_ONESHOT, dev_name(ctx->dev), ctx);
1033 if (ret)
1034 return dev_err_probe(dev, ret, "failed to request irq\n");
1035 }
1036
1037 dev_set_drvdata(dev, ctx);
1038 i2c_set_clientdata(client, ctx);
1039
1040 ctx->bridge.of_node = dev->of_node;
1041 ctx->bridge.pre_enable_prev_first = true;
1042 ctx->bridge.type = DRM_MODE_CONNECTOR_LVDS;
1043 drm_bridge_add(&ctx->bridge);
1044
1045 ret = sn65dsi83_host_attach(ctx);
1046 if (ret) {
1047 dev_err_probe(dev, ret, "failed to attach DSI host\n");
1048 goto err_remove_bridge;
1049 }
1050
1051 return 0;
1052
1053 err_remove_bridge:
1054 drm_bridge_remove(&ctx->bridge);
1055 return ret;
1056 }
1057
sn65dsi83_remove(struct i2c_client * client)1058 static void sn65dsi83_remove(struct i2c_client *client)
1059 {
1060 struct sn65dsi83 *ctx = i2c_get_clientdata(client);
1061
1062 drm_bridge_unplug(&ctx->bridge);
1063 }
1064
1065 static const struct i2c_device_id sn65dsi83_id[] = {
1066 { "ti,sn65dsi83", MODEL_SN65DSI83 },
1067 { "ti,sn65dsi84", MODEL_SN65DSI84 },
1068 {},
1069 };
1070 MODULE_DEVICE_TABLE(i2c, sn65dsi83_id);
1071
1072 static const struct of_device_id sn65dsi83_match_table[] = {
1073 { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 },
1074 { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 },
1075 {},
1076 };
1077 MODULE_DEVICE_TABLE(of, sn65dsi83_match_table);
1078
1079 static struct i2c_driver sn65dsi83_driver = {
1080 .probe = sn65dsi83_probe,
1081 .remove = sn65dsi83_remove,
1082 .id_table = sn65dsi83_id,
1083 .driver = {
1084 .name = "sn65dsi83",
1085 .of_match_table = sn65dsi83_match_table,
1086 },
1087 };
1088 module_i2c_driver(sn65dsi83_driver);
1089
1090 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1091 MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver");
1092 MODULE_LICENSE("GPL v2");
1093