1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include <drm/display/drm_dsc_helper.h>
6
7 #include "reg_helper.h"
8 #include "dcn401_dsc.h"
9 #include "dsc/dscc_types.h"
10 #include "dsc/rc_calc.h"
11
12 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);
13
14 /* Object I/F functions */
15 //static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
16 //static bool dsc401_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps);
17 static void dsc401_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz);
18
19 static const struct dsc_funcs dcn401_dsc_funcs = {
20 .dsc_read_state = dsc401_read_state,
21 .dsc_validate_stream = dsc401_validate_stream,
22 .dsc_set_config = dsc401_set_config,
23 .dsc_get_packed_pps = dsc2_get_packed_pps,
24 .dsc_enable = dsc401_enable,
25 .dsc_disable = dsc401_disable,
26 .dsc_disconnect = dsc401_disconnect,
27 .dsc_wait_disconnect_pending_clear = dsc401_wait_disconnect_pending_clear,
28 .dsc_get_single_enc_caps = dsc401_get_single_enc_caps,
29 };
30
31 /* Macro definitios for REG_SET macros*/
32 #define CTX \
33 dsc401->base.ctx
34
35 #define REG(reg)\
36 dsc401->dsc_regs->reg
37
38 #undef FN
39 #define FN(reg_name, field_name) \
40 dsc401->dsc_shift->field_name, dsc401->dsc_mask->field_name
41 #define DC_LOGGER \
42 dsc->ctx->logger
43
44
45 /* API functions (external or via structure->function_pointer) */
46
dsc401_construct(struct dcn401_dsc * dsc,struct dc_context * ctx,int inst,const struct dcn401_dsc_registers * dsc_regs,const struct dcn401_dsc_shift * dsc_shift,const struct dcn401_dsc_mask * dsc_mask)47 void dsc401_construct(struct dcn401_dsc *dsc,
48 struct dc_context *ctx,
49 int inst,
50 const struct dcn401_dsc_registers *dsc_regs,
51 const struct dcn401_dsc_shift *dsc_shift,
52 const struct dcn401_dsc_mask *dsc_mask)
53 {
54 dsc->base.ctx = ctx;
55 dsc->base.inst = inst;
56 dsc->base.funcs = &dcn401_dsc_funcs;
57
58 dsc->dsc_regs = dsc_regs;
59 dsc->dsc_shift = dsc_shift;
60 dsc->dsc_mask = dsc_mask;
61
62 dsc->max_image_width = 5184;
63 }
64
dsc401_get_single_enc_caps(struct dsc_enc_caps * dsc_enc_caps,unsigned int max_dscclk_khz)65 static void dsc401_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz)
66 {
67 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */
68
69 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;
70 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;
71 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;
72 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;
73
74 dsc_enc_caps->lb_bit_depth = 13;
75 dsc_enc_caps->is_block_pred_supported = true;
76
77 dsc_enc_caps->color_formats.bits.RGB = 1;
78 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
79 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;
80 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
81 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
82
83 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
84 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;
85 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;
86 dsc_enc_caps->max_total_throughput_mps = max_dscclk_khz * 3 / 1000;
87
88 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */
89 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */
90 }
91
92 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
93 * into a dcn_dsc_state struct.
94 */
dsc401_read_state(struct display_stream_compressor * dsc,struct dcn_dsc_state * s)95 void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)
96 {
97 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
98
99 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);
100 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);
101 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel);
102 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height);
103 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size);
104 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width);
105 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height);
106 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset);
107 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en,
108 DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source);
109 }
110
111
dsc401_validate_stream(struct display_stream_compressor * dsc,const struct dsc_config * dsc_cfg)112 bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
113 {
114 struct dsc_optc_config dsc_optc_cfg;
115 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
116
117 if (dsc_cfg->pic_width > dsc401->max_image_width)
118 return false;
119
120 return dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, &dsc_optc_cfg);
121 }
122
dsc401_set_config(struct display_stream_compressor * dsc,const struct dsc_config * dsc_cfg,struct dsc_optc_config * dsc_optc_cfg)123 void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
124 struct dsc_optc_config *dsc_optc_cfg)
125 {
126 bool is_config_ok;
127 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
128
129 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
130 dsc_config_log(dsc, dsc_cfg);
131 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, dsc_optc_cfg);
132 ASSERT(is_config_ok);
133 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
134 dsc_log_pps(dsc, &dsc401->reg_vals.pps);
135 dsc_write_to_registers(dsc, &dsc401->reg_vals);
136 }
137
dsc401_enable(struct display_stream_compressor * dsc,int opp_pipe)138 void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe)
139 {
140 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
141 int dsc_clock_en;
142 int dsc_fw_config;
143 int enabled_opp_pipe;
144
145 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
146
147 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
148 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
149 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
150 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
151 ASSERT(0);
152 }
153
154 REG_UPDATE(DSC_TOP_CONTROL,
155 DSC_CLOCK_EN, 1);
156
157 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,
158 DSCRM_DSC_FORWARD_EN, 1,
159 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe);
160 }
161
162
dsc401_disable(struct display_stream_compressor * dsc)163 void dsc401_disable(struct display_stream_compressor *dsc)
164 {
165 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
166 int dsc_clock_en;
167
168 DC_LOG_DSC("disable DSC %d", dsc->inst);
169
170 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
171 if (!dsc_clock_en) {
172 DC_LOG_DSC("DSC %d already disabled!", dsc->inst);
173 }
174
175 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
176 DSCRM_DSC_FORWARD_EN, 0);
177
178 REG_UPDATE(DSC_TOP_CONTROL,
179 DSC_CLOCK_EN, 0);
180 }
181
dsc401_wait_disconnect_pending_clear(struct display_stream_compressor * dsc)182 void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc)
183 {
184 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
185
186 REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, 0, 2, 50000);
187 }
188
dsc401_disconnect(struct display_stream_compressor * dsc)189 void dsc401_disconnect(struct display_stream_compressor *dsc)
190 {
191 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
192
193 DC_LOG_DSC("disconnect DSC %d", dsc->inst);
194
195 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
196 DSCRM_DSC_FORWARD_EN, 0);
197 }
198
dsc_write_to_registers(struct display_stream_compressor * dsc,const struct dsc_reg_values * reg_vals)199 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)
200 {
201 uint32_t temp_int;
202 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
203
204 REG_SET(DSC_DEBUG_CONTROL, 0,
205 DSC_DBG_EN, reg_vals->dsc_dbg_en);
206
207 // dsccif registers
208 REG_SET_2(DSCCIF_CONFIG0, 0,
209 //INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en,
210 //INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en,
211 //INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status,
212 INPUT_PIXEL_FORMAT, reg_vals->pixel_format,
213 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
214
215 /* REG_SET_2(DSCCIF_CONFIG1, 0,
216 PIC_WIDTH, reg_vals->pps.pic_width,
217 PIC_HEIGHT, reg_vals->pps.pic_height);
218 */
219 // dscc registers
220 if (dsc401->dsc_mask->ICH_RESET_AT_END_OF_LINE == 0) {
221 REG_SET_3(DSCC_CONFIG0, 0,
222 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1,
223 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en,
224 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);
225 } else {
226 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE,
227 reg_vals->ich_reset_at_eol, NUMBER_OF_SLICES_PER_LINE,
228 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN,
229 reg_vals->alternate_ich_encoding_en, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION,
230 reg_vals->num_slices_v - 1);
231 }
232
233 REG_SET(DSCC_CONFIG1, 0,
234 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size);
235 /*REG_SET_2(DSCC_CONFIG1, 0,
236 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size,
237 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/
238
239 REG_SET_4(DSCC_INTERRUPT_CONTROL0, 0,
240 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0, reg_vals->rc_buffer_model_overflow_int_en[0],
241 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1, reg_vals->rc_buffer_model_overflow_int_en[1],
242 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2, reg_vals->rc_buffer_model_overflow_int_en[2],
243 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3, reg_vals->rc_buffer_model_overflow_int_en[3]);
244
245 REG_SET_3(DSCC_PPS_CONFIG0, 0,
246 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor,
247 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth,
248 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
249
250 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
251 temp_int = reg_vals->bpp_x32;
252 else
253 temp_int = reg_vals->bpp_x32 >> 1;
254
255 REG_SET_7(DSCC_PPS_CONFIG1, 0,
256 BITS_PER_PIXEL, temp_int,
257 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422,
258 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB,
259 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable,
260 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422,
261 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420,
262 CHUNK_SIZE, reg_vals->pps.slice_chunk_size);
263
264 REG_SET_2(DSCC_PPS_CONFIG2, 0,
265 PIC_WIDTH, reg_vals->pps.pic_width,
266 PIC_HEIGHT, reg_vals->pps.pic_height);
267
268 REG_SET_2(DSCC_PPS_CONFIG3, 0,
269 SLICE_WIDTH, reg_vals->pps.slice_width,
270 SLICE_HEIGHT, reg_vals->pps.slice_height);
271
272 REG_SET(DSCC_PPS_CONFIG4, 0,
273 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay);
274
275 REG_SET_2(DSCC_PPS_CONFIG5, 0,
276 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value,
277 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval);
278
279 REG_SET_3(DSCC_PPS_CONFIG6, 0,
280 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval,
281 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset,
282 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset);
283
284 REG_SET_2(DSCC_PPS_CONFIG7, 0,
285 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset,
286 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset);
287
288 REG_SET_2(DSCC_PPS_CONFIG8, 0,
289 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset,
290 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj);
291
292 REG_SET_2(DSCC_PPS_CONFIG9, 0,
293 INITIAL_OFFSET, reg_vals->pps.initial_offset,
294 FINAL_OFFSET, reg_vals->pps.final_offset);
295
296 REG_SET_3(DSCC_PPS_CONFIG10, 0,
297 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp,
298 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp,
299 RC_MODEL_SIZE, reg_vals->pps.rc_model_size);
300
301 REG_SET_5(DSCC_PPS_CONFIG11, 0,
302 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor,
303 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0,
304 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1,
305 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low,
306 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high);
307
308 REG_SET_4(DSCC_PPS_CONFIG12, 0,
309 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0],
310 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1],
311 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2],
312 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]);
313
314 REG_SET_4(DSCC_PPS_CONFIG13, 0,
315 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4],
316 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5],
317 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6],
318 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]);
319
320 REG_SET_4(DSCC_PPS_CONFIG14, 0,
321 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8],
322 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9],
323 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10],
324 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]);
325
326 REG_SET_5(DSCC_PPS_CONFIG15, 0,
327 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12],
328 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13],
329 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp,
330 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp,
331 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);
332
333 REG_SET_6(DSCC_PPS_CONFIG16, 0,
334 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp,
335 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp,
336 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,
337 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp,
338 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp,
339 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);
340
341 REG_SET_6(DSCC_PPS_CONFIG17, 0,
342 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp,
343 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp,
344 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,
345 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp,
346 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp,
347 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);
348
349 REG_SET_6(DSCC_PPS_CONFIG18, 0,
350 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp,
351 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp,
352 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,
353 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp,
354 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp,
355 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);
356
357 REG_SET_6(DSCC_PPS_CONFIG19, 0,
358 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp,
359 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp,
360 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,
361 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp,
362 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp,
363 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset);
364
365 REG_SET_6(DSCC_PPS_CONFIG20, 0,
366 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp,
367 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp,
368 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset,
369 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp,
370 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp,
371 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset);
372
373 REG_SET_6(DSCC_PPS_CONFIG21, 0,
374 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp,
375 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp,
376 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset,
377 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp,
378 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp,
379 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset);
380
381 REG_SET_6(DSCC_PPS_CONFIG22, 0,
382 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp,
383 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp,
384 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset,
385 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp,
386 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp,
387 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);
388 }
389
dsc401_set_fgcg(struct dcn401_dsc * dsc401,bool enable)390 void dsc401_set_fgcg(struct dcn401_dsc *dsc401, bool enable)
391 {
392 REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable);
393 }
394