1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #include <drm/display/drm_dsc_helper.h> 6 7 #include "reg_helper.h" 8 #include "dcn401_dsc.h" 9 #include "dsc/dscc_types.h" 10 #include "dsc/rc_calc.h" 11 12 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals); 13 14 /* Object I/F functions */ 15 //static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz); 16 //static bool dsc401_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps); 17 static void dsc401_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz); 18 19 static const struct dsc_funcs dcn401_dsc_funcs = { 20 .dsc_read_state = dsc401_read_state, 21 .dsc_validate_stream = dsc401_validate_stream, 22 .dsc_set_config = dsc401_set_config, 23 .dsc_get_packed_pps = dsc2_get_packed_pps, 24 .dsc_enable = dsc401_enable, 25 .dsc_disable = dsc401_disable, 26 .dsc_disconnect = dsc401_disconnect, 27 .dsc_wait_disconnect_pending_clear = dsc401_wait_disconnect_pending_clear, 28 .dsc_get_single_enc_caps = dsc401_get_single_enc_caps, 29 .dsc_read_reg_state = dsc2_read_reg_state 30 }; 31 32 /* Macro definitios for REG_SET macros*/ 33 #define CTX \ 34 dsc401->base.ctx 35 36 #define REG(reg)\ 37 dsc401->dsc_regs->reg 38 39 #undef FN 40 #define FN(reg_name, field_name) \ 41 dsc401->dsc_shift->field_name, dsc401->dsc_mask->field_name 42 #define DC_LOGGER \ 43 dsc->ctx->logger 44 45 46 /* API functions (external or via structure->function_pointer) */ 47 48 void dsc401_construct(struct dcn401_dsc *dsc, 49 struct dc_context *ctx, 50 int inst, 51 const struct dcn401_dsc_registers *dsc_regs, 52 const struct dcn401_dsc_shift *dsc_shift, 53 const struct dcn401_dsc_mask *dsc_mask) 54 { 55 dsc->base.ctx = ctx; 56 dsc->base.inst = inst; 57 dsc->base.funcs = &dcn401_dsc_funcs; 58 59 dsc->dsc_regs = dsc_regs; 60 dsc->dsc_shift = dsc_shift; 61 dsc->dsc_mask = dsc_mask; 62 63 dsc->max_image_width = 5184; 64 } 65 66 static void dsc401_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz) 67 { 68 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */ 69 70 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1; 71 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1; 72 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1; 73 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1; 74 75 dsc_enc_caps->lb_bit_depth = 13; 76 dsc_enc_caps->is_block_pred_supported = true; 77 78 dsc_enc_caps->color_formats.bits.RGB = 1; 79 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; 80 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; 81 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; 82 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; 83 84 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; 85 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1; 86 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1; 87 dsc_enc_caps->max_total_throughput_mps = max_dscclk_khz * 3 / 1000; 88 89 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */ 90 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */ 91 } 92 93 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state 94 * into a dcn_dsc_state struct. 95 */ 96 void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s) 97 { 98 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); 99 100 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); 101 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); 102 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel); 103 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height); 104 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size); 105 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width); 106 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height); 107 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset); 108 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en, 109 DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source); 110 } 111 112 113 bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) 114 { 115 struct dsc_optc_config dsc_optc_cfg; 116 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); 117 118 if (dsc_cfg->pic_width > dsc401->max_image_width) 119 return false; 120 121 return dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, &dsc_optc_cfg); 122 } 123 124 void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 125 struct dsc_optc_config *dsc_optc_cfg) 126 { 127 bool is_config_ok; 128 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); 129 130 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst); 131 dsc_config_log(dsc, dsc_cfg); 132 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, dsc_optc_cfg); 133 ASSERT(is_config_ok); 134 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):"); 135 dsc_log_pps(dsc, &dsc401->reg_vals.pps); 136 dsc_write_to_registers(dsc, &dsc401->reg_vals); 137 } 138 139 void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe) 140 { 141 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); 142 int dsc_clock_en; 143 int dsc_fw_config; 144 int enabled_opp_pipe; 145 146 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe); 147 148 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 149 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); 150 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) { 151 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe); 152 ASSERT(0); 153 } 154 155 REG_UPDATE(DSC_TOP_CONTROL, 156 DSC_CLOCK_EN, 1); 157 158 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG, 159 DSCRM_DSC_FORWARD_EN, 1, 160 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe); 161 } 162 163 164 void dsc401_disable(struct display_stream_compressor *dsc) 165 { 166 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); 167 int dsc_clock_en; 168 169 DC_LOG_DSC("disable DSC %d", dsc->inst); 170 171 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 172 if (!dsc_clock_en) { 173 DC_LOG_DSC("DSC %d already disabled!", dsc->inst); 174 } 175 176 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, 177 DSCRM_DSC_FORWARD_EN, 0); 178 179 REG_UPDATE(DSC_TOP_CONTROL, 180 DSC_CLOCK_EN, 0); 181 } 182 183 void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc) 184 { 185 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); 186 187 REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, 0, 2, 50000); 188 } 189 190 void dsc401_disconnect(struct display_stream_compressor *dsc) 191 { 192 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); 193 194 DC_LOG_DSC("disconnect DSC %d", dsc->inst); 195 196 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, 197 DSCRM_DSC_FORWARD_EN, 0); 198 } 199 200 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals) 201 { 202 uint32_t temp_int; 203 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); 204 205 REG_SET(DSC_DEBUG_CONTROL, 0, 206 DSC_DBG_EN, reg_vals->dsc_dbg_en); 207 208 // dsccif registers 209 REG_SET_2(DSCCIF_CONFIG0, 0, 210 //INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en, 211 //INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en, 212 //INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status, 213 INPUT_PIXEL_FORMAT, reg_vals->pixel_format, 214 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 215 216 /* REG_SET_2(DSCCIF_CONFIG1, 0, 217 PIC_WIDTH, reg_vals->pps.pic_width, 218 PIC_HEIGHT, reg_vals->pps.pic_height); 219 */ 220 // dscc registers 221 if (dsc401->dsc_mask->ICH_RESET_AT_END_OF_LINE == 0) { 222 REG_SET_3(DSCC_CONFIG0, 0, 223 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, 224 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en, 225 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1); 226 } else { 227 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE, 228 reg_vals->ich_reset_at_eol, NUMBER_OF_SLICES_PER_LINE, 229 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN, 230 reg_vals->alternate_ich_encoding_en, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, 231 reg_vals->num_slices_v - 1); 232 } 233 234 REG_SET(DSCC_CONFIG1, 0, 235 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size); 236 /*REG_SET_2(DSCC_CONFIG1, 0, 237 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size, 238 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/ 239 240 REG_SET_4(DSCC_INTERRUPT_CONTROL0, 0, 241 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0, reg_vals->rc_buffer_model_overflow_int_en[0], 242 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1, reg_vals->rc_buffer_model_overflow_int_en[1], 243 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2, reg_vals->rc_buffer_model_overflow_int_en[2], 244 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3, reg_vals->rc_buffer_model_overflow_int_en[3]); 245 246 REG_SET_3(DSCC_PPS_CONFIG0, 0, 247 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor, 248 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth, 249 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 250 251 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 252 temp_int = reg_vals->bpp_x32; 253 else 254 temp_int = reg_vals->bpp_x32 >> 1; 255 256 REG_SET_7(DSCC_PPS_CONFIG1, 0, 257 BITS_PER_PIXEL, temp_int, 258 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422, 259 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB, 260 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable, 261 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422, 262 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420, 263 CHUNK_SIZE, reg_vals->pps.slice_chunk_size); 264 265 REG_SET_2(DSCC_PPS_CONFIG2, 0, 266 PIC_WIDTH, reg_vals->pps.pic_width, 267 PIC_HEIGHT, reg_vals->pps.pic_height); 268 269 REG_SET_2(DSCC_PPS_CONFIG3, 0, 270 SLICE_WIDTH, reg_vals->pps.slice_width, 271 SLICE_HEIGHT, reg_vals->pps.slice_height); 272 273 REG_SET(DSCC_PPS_CONFIG4, 0, 274 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay); 275 276 REG_SET_2(DSCC_PPS_CONFIG5, 0, 277 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value, 278 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval); 279 280 REG_SET_3(DSCC_PPS_CONFIG6, 0, 281 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval, 282 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset, 283 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset); 284 285 REG_SET_2(DSCC_PPS_CONFIG7, 0, 286 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset, 287 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset); 288 289 REG_SET_2(DSCC_PPS_CONFIG8, 0, 290 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset, 291 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj); 292 293 REG_SET_2(DSCC_PPS_CONFIG9, 0, 294 INITIAL_OFFSET, reg_vals->pps.initial_offset, 295 FINAL_OFFSET, reg_vals->pps.final_offset); 296 297 REG_SET_3(DSCC_PPS_CONFIG10, 0, 298 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp, 299 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp, 300 RC_MODEL_SIZE, reg_vals->pps.rc_model_size); 301 302 REG_SET_5(DSCC_PPS_CONFIG11, 0, 303 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor, 304 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0, 305 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1, 306 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low, 307 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high); 308 309 REG_SET_4(DSCC_PPS_CONFIG12, 0, 310 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0], 311 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1], 312 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2], 313 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]); 314 315 REG_SET_4(DSCC_PPS_CONFIG13, 0, 316 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4], 317 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5], 318 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6], 319 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]); 320 321 REG_SET_4(DSCC_PPS_CONFIG14, 0, 322 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8], 323 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9], 324 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10], 325 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]); 326 327 REG_SET_5(DSCC_PPS_CONFIG15, 0, 328 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12], 329 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13], 330 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, 331 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp, 332 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); 333 334 REG_SET_6(DSCC_PPS_CONFIG16, 0, 335 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, 336 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp, 337 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, 338 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, 339 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp, 340 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); 341 342 REG_SET_6(DSCC_PPS_CONFIG17, 0, 343 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp, 344 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp, 345 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, 346 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp, 347 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp, 348 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); 349 350 REG_SET_6(DSCC_PPS_CONFIG18, 0, 351 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp, 352 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp, 353 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, 354 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp, 355 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp, 356 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); 357 358 REG_SET_6(DSCC_PPS_CONFIG19, 0, 359 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp, 360 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp, 361 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, 362 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp, 363 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp, 364 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); 365 366 REG_SET_6(DSCC_PPS_CONFIG20, 0, 367 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp, 368 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp, 369 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, 370 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp, 371 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp, 372 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset); 373 374 REG_SET_6(DSCC_PPS_CONFIG21, 0, 375 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp, 376 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp, 377 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset, 378 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp, 379 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp, 380 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset); 381 382 REG_SET_6(DSCC_PPS_CONFIG22, 0, 383 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp, 384 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp, 385 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset, 386 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp, 387 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp, 388 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); 389 } 390 391 void dsc401_set_fgcg(struct dcn401_dsc *dsc401, bool enable) 392 { 393 REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable); 394 } 395