1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include <drm/display/drm_dsc_helper.h>
6
7 #include "reg_helper.h"
8 #include "dcn401_dsc.h"
9 #include "dsc/dscc_types.h"
10 #include "dsc/rc_calc.h"
11
12 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);
13
14 /* Object I/F functions */
15 //static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
16 //static bool dsc401_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps);
17 static void dsc401_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz);
18
19 static const struct dsc_funcs dcn401_dsc_funcs = {
20 .dsc_read_state = dsc401_read_state,
21 .dsc_validate_stream = dsc401_validate_stream,
22 .dsc_set_config = dsc401_set_config,
23 .dsc_get_packed_pps = dsc2_get_packed_pps,
24 .dsc_enable = dsc401_enable,
25 .dsc_disable = dsc401_disable,
26 .dsc_disconnect = dsc401_disconnect,
27 .dsc_wait_disconnect_pending_clear = dsc401_wait_disconnect_pending_clear,
28 .dsc_get_single_enc_caps = dsc401_get_single_enc_caps,
29 .dsc_read_reg_state = dsc2_read_reg_state
30 };
31
32 /* Macro definitios for REG_SET macros*/
33 #define CTX \
34 dsc401->base.ctx
35
36 #define REG(reg)\
37 dsc401->dsc_regs->reg
38
39 #undef FN
40 #define FN(reg_name, field_name) \
41 dsc401->dsc_shift->field_name, dsc401->dsc_mask->field_name
42 #define DC_LOGGER \
43 dsc->ctx->logger
44
45
46 /* API functions (external or via structure->function_pointer) */
47
dsc401_construct(struct dcn401_dsc * dsc,struct dc_context * ctx,int inst,const struct dcn401_dsc_registers * dsc_regs,const struct dcn401_dsc_shift * dsc_shift,const struct dcn401_dsc_mask * dsc_mask)48 void dsc401_construct(struct dcn401_dsc *dsc,
49 struct dc_context *ctx,
50 int inst,
51 const struct dcn401_dsc_registers *dsc_regs,
52 const struct dcn401_dsc_shift *dsc_shift,
53 const struct dcn401_dsc_mask *dsc_mask)
54 {
55 dsc->base.ctx = ctx;
56 dsc->base.inst = inst;
57 dsc->base.funcs = &dcn401_dsc_funcs;
58
59 dsc->dsc_regs = dsc_regs;
60 dsc->dsc_shift = dsc_shift;
61 dsc->dsc_mask = dsc_mask;
62
63 dsc->max_image_width = 5184;
64 }
65
dsc401_get_single_enc_caps(struct dsc_enc_caps * dsc_enc_caps,unsigned int max_dscclk_khz)66 static void dsc401_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz)
67 {
68 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */
69
70 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;
71 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;
72 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;
73 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;
74
75 dsc_enc_caps->lb_bit_depth = 13;
76 dsc_enc_caps->is_block_pred_supported = true;
77
78 dsc_enc_caps->color_formats.bits.RGB = 1;
79 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
80 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;
81 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;
82 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
83
84 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
85 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;
86 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;
87 dsc_enc_caps->max_total_throughput_mps = max_dscclk_khz * 3 / 1000;
88
89 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */
90 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */
91 }
92
93 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
94 * into a dcn_dsc_state struct.
95 */
dsc401_read_state(struct display_stream_compressor * dsc,struct dcn_dsc_state * s)96 void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)
97 {
98 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
99
100 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);
101 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);
102 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel);
103 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height);
104 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size);
105 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width);
106 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height);
107 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset);
108 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en,
109 DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source);
110 REG_GET(DSCC_PPS_CONFIG1, BLOCK_PRED_ENABLE, &s->dsc_block_pred_enable);
111 REG_GET(DSCC_PPS_CONFIG0, LINEBUF_DEPTH, &s->dsc_line_buf_depth);
112 REG_GET(DSCC_PPS_CONFIG0, DSC_VERSION_MINOR, &s->dsc_version_minor);
113 REG_GET(DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, &s->dsc_rc_buffer_size);
114 REG_GET(DSCC_PPS_CONFIG0, SIMPLE_422, &s->dsc_simple_422);
115 }
116
117
dsc401_validate_stream(struct display_stream_compressor * dsc,const struct dsc_config * dsc_cfg)118 bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
119 {
120 struct dsc_optc_config dsc_optc_cfg;
121 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
122
123 if (dsc_cfg->pic_width > dsc401->max_image_width)
124 return false;
125
126 return dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, &dsc_optc_cfg);
127 }
128
dsc401_set_config(struct display_stream_compressor * dsc,const struct dsc_config * dsc_cfg,struct dsc_optc_config * dsc_optc_cfg)129 void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
130 struct dsc_optc_config *dsc_optc_cfg)
131 {
132 bool is_config_ok;
133 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
134
135 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
136 dsc_config_log(dsc, dsc_cfg);
137 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, dsc_optc_cfg);
138 ASSERT(is_config_ok);
139 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
140 dsc_log_pps(dsc, &dsc401->reg_vals.pps);
141 dsc_write_to_registers(dsc, &dsc401->reg_vals);
142 }
143
dsc401_enable(struct display_stream_compressor * dsc,int opp_pipe)144 void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe)
145 {
146 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
147 int dsc_clock_en;
148 int dsc_fw_config;
149 int enabled_opp_pipe;
150
151 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
152
153 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
154 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
155 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
156 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
157 ASSERT(0);
158 }
159
160 REG_UPDATE(DSC_TOP_CONTROL,
161 DSC_CLOCK_EN, 1);
162
163 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,
164 DSCRM_DSC_FORWARD_EN, 1,
165 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe);
166 }
167
168
dsc401_disable(struct display_stream_compressor * dsc)169 void dsc401_disable(struct display_stream_compressor *dsc)
170 {
171 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
172 int dsc_clock_en;
173
174 DC_LOG_DSC("disable DSC %d", dsc->inst);
175
176 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
177 if (!dsc_clock_en) {
178 DC_LOG_DSC("DSC %d already disabled!", dsc->inst);
179 }
180
181 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
182 DSCRM_DSC_FORWARD_EN, 0);
183
184 REG_UPDATE(DSC_TOP_CONTROL,
185 DSC_CLOCK_EN, 0);
186 }
187
dsc401_wait_disconnect_pending_clear(struct display_stream_compressor * dsc)188 void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc)
189 {
190 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
191
192 REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, 0, 2, 50000);
193 }
194
dsc401_disconnect(struct display_stream_compressor * dsc)195 void dsc401_disconnect(struct display_stream_compressor *dsc)
196 {
197 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
198
199 DC_LOG_DSC("disconnect DSC %d", dsc->inst);
200
201 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
202 DSCRM_DSC_FORWARD_EN, 0);
203 }
204
dsc_write_to_registers(struct display_stream_compressor * dsc,const struct dsc_reg_values * reg_vals)205 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)
206 {
207 uint32_t temp_int;
208 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
209
210 REG_SET(DSC_DEBUG_CONTROL, 0,
211 DSC_DBG_EN, reg_vals->dsc_dbg_en);
212
213 // dsccif registers
214 REG_SET_2(DSCCIF_CONFIG0, 0,
215 //INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en,
216 //INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en,
217 //INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status,
218 INPUT_PIXEL_FORMAT, reg_vals->pixel_format,
219 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
220
221 /* REG_SET_2(DSCCIF_CONFIG1, 0,
222 PIC_WIDTH, reg_vals->pps.pic_width,
223 PIC_HEIGHT, reg_vals->pps.pic_height);
224 */
225 // dscc registers
226 if (dsc401->dsc_mask->ICH_RESET_AT_END_OF_LINE == 0) {
227 REG_SET_3(DSCC_CONFIG0, 0,
228 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1,
229 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en,
230 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);
231 } else {
232 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE,
233 reg_vals->ich_reset_at_eol, NUMBER_OF_SLICES_PER_LINE,
234 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN,
235 reg_vals->alternate_ich_encoding_en, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION,
236 reg_vals->num_slices_v - 1);
237 }
238
239 REG_SET(DSCC_CONFIG1, 0,
240 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size);
241 /*REG_SET_2(DSCC_CONFIG1, 0,
242 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size,
243 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/
244
245 REG_SET_4(DSCC_INTERRUPT_CONTROL0, 0,
246 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0, reg_vals->rc_buffer_model_overflow_int_en[0],
247 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1, reg_vals->rc_buffer_model_overflow_int_en[1],
248 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2, reg_vals->rc_buffer_model_overflow_int_en[2],
249 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3, reg_vals->rc_buffer_model_overflow_int_en[3]);
250
251 REG_SET_3(DSCC_PPS_CONFIG0, 0,
252 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor,
253 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth,
254 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
255
256 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
257 temp_int = reg_vals->bpp_x32;
258 else
259 temp_int = reg_vals->bpp_x32 >> 1;
260
261 REG_SET_7(DSCC_PPS_CONFIG1, 0,
262 BITS_PER_PIXEL, temp_int,
263 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422,
264 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB,
265 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable,
266 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422,
267 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420,
268 CHUNK_SIZE, reg_vals->pps.slice_chunk_size);
269
270 REG_SET_2(DSCC_PPS_CONFIG2, 0,
271 PIC_WIDTH, reg_vals->pps.pic_width,
272 PIC_HEIGHT, reg_vals->pps.pic_height);
273
274 REG_SET_2(DSCC_PPS_CONFIG3, 0,
275 SLICE_WIDTH, reg_vals->pps.slice_width,
276 SLICE_HEIGHT, reg_vals->pps.slice_height);
277
278 REG_SET(DSCC_PPS_CONFIG4, 0,
279 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay);
280
281 REG_SET_2(DSCC_PPS_CONFIG5, 0,
282 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value,
283 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval);
284
285 REG_SET_3(DSCC_PPS_CONFIG6, 0,
286 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval,
287 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset,
288 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset);
289
290 REG_SET_2(DSCC_PPS_CONFIG7, 0,
291 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset,
292 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset);
293
294 REG_SET_2(DSCC_PPS_CONFIG8, 0,
295 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset,
296 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj);
297
298 REG_SET_2(DSCC_PPS_CONFIG9, 0,
299 INITIAL_OFFSET, reg_vals->pps.initial_offset,
300 FINAL_OFFSET, reg_vals->pps.final_offset);
301
302 REG_SET_3(DSCC_PPS_CONFIG10, 0,
303 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp,
304 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp,
305 RC_MODEL_SIZE, reg_vals->pps.rc_model_size);
306
307 REG_SET_5(DSCC_PPS_CONFIG11, 0,
308 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor,
309 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0,
310 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1,
311 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low,
312 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high);
313
314 REG_SET_4(DSCC_PPS_CONFIG12, 0,
315 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0],
316 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1],
317 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2],
318 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]);
319
320 REG_SET_4(DSCC_PPS_CONFIG13, 0,
321 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4],
322 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5],
323 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6],
324 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]);
325
326 REG_SET_4(DSCC_PPS_CONFIG14, 0,
327 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8],
328 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9],
329 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10],
330 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]);
331
332 REG_SET_5(DSCC_PPS_CONFIG15, 0,
333 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12],
334 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13],
335 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp,
336 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp,
337 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);
338
339 REG_SET_6(DSCC_PPS_CONFIG16, 0,
340 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp,
341 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp,
342 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,
343 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp,
344 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp,
345 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);
346
347 REG_SET_6(DSCC_PPS_CONFIG17, 0,
348 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp,
349 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp,
350 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,
351 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp,
352 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp,
353 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);
354
355 REG_SET_6(DSCC_PPS_CONFIG18, 0,
356 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp,
357 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp,
358 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,
359 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp,
360 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp,
361 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);
362
363 REG_SET_6(DSCC_PPS_CONFIG19, 0,
364 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp,
365 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp,
366 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,
367 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp,
368 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp,
369 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset);
370
371 REG_SET_6(DSCC_PPS_CONFIG20, 0,
372 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp,
373 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp,
374 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset,
375 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp,
376 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp,
377 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset);
378
379 REG_SET_6(DSCC_PPS_CONFIG21, 0,
380 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp,
381 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp,
382 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset,
383 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp,
384 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp,
385 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset);
386
387 REG_SET_6(DSCC_PPS_CONFIG22, 0,
388 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp,
389 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp,
390 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset,
391 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp,
392 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp,
393 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);
394 }
395
dsc401_set_fgcg(struct dcn401_dsc * dsc401,bool enable)396 void dsc401_set_fgcg(struct dcn401_dsc *dsc401, bool enable)
397 {
398 REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable);
399 }
400