xref: /linux/include/linux/mfd/ucb1x00.h (revision 1ac731c529cd4d6adbce134754b51ff7d822b145)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  *  linux/include/mfd/ucb1x00.h
4  *
5  *  Copyright (C) 2001 Russell King, All Rights Reserved.
6  */
7 #ifndef UCB1200_H
8 #define UCB1200_H
9 
10 #include <linux/device.h>
11 #include <linux/mfd/mcp.h>
12 #include <linux/gpio.h>
13 #include <linux/gpio/driver.h>
14 #include <linux/mutex.h>
15 
16 #define UCB_IO_DATA	0x00
17 #define UCB_IO_DIR	0x01
18 
19 #define UCB_IO_0		(1 << 0)
20 #define UCB_IO_1		(1 << 1)
21 #define UCB_IO_2		(1 << 2)
22 #define UCB_IO_3		(1 << 3)
23 #define UCB_IO_4		(1 << 4)
24 #define UCB_IO_5		(1 << 5)
25 #define UCB_IO_6		(1 << 6)
26 #define UCB_IO_7		(1 << 7)
27 #define UCB_IO_8		(1 << 8)
28 #define UCB_IO_9		(1 << 9)
29 
30 #define UCB_IE_RIS	0x02
31 #define UCB_IE_FAL	0x03
32 #define UCB_IE_STATUS	0x04
33 #define UCB_IE_CLEAR	0x04
34 #define UCB_IE_ADC		(1 << 11)
35 #define UCB_IE_TSPX		(1 << 12)
36 #define UCB_IE_TSMX		(1 << 13)
37 #define UCB_IE_TCLIP		(1 << 14)
38 #define UCB_IE_ACLIP		(1 << 15)
39 
40 #define UCB_IRQ_TSPX		12
41 
42 #define UCB_TC_A	0x05
43 #define UCB_TC_A_LOOP		(1 << 7)	/* UCB1200 */
44 #define UCB_TC_A_AMPL		(1 << 7)	/* UCB1300 */
45 
46 #define UCB_TC_B	0x06
47 #define UCB_TC_B_VOICE_ENA	(1 << 3)
48 #define UCB_TC_B_CLIP		(1 << 4)
49 #define UCB_TC_B_ATT		(1 << 6)
50 #define UCB_TC_B_SIDE_ENA	(1 << 11)
51 #define UCB_TC_B_MUTE		(1 << 13)
52 #define UCB_TC_B_IN_ENA		(1 << 14)
53 #define UCB_TC_B_OUT_ENA	(1 << 15)
54 
55 #define UCB_AC_A	0x07
56 #define UCB_AC_B	0x08
57 #define UCB_AC_B_LOOP		(1 << 8)
58 #define UCB_AC_B_MUTE		(1 << 13)
59 #define UCB_AC_B_IN_ENA		(1 << 14)
60 #define UCB_AC_B_OUT_ENA	(1 << 15)
61 
62 #define UCB_TS_CR	0x09
63 #define UCB_TS_CR_TSMX_POW	(1 << 0)
64 #define UCB_TS_CR_TSPX_POW	(1 << 1)
65 #define UCB_TS_CR_TSMY_POW	(1 << 2)
66 #define UCB_TS_CR_TSPY_POW	(1 << 3)
67 #define UCB_TS_CR_TSMX_GND	(1 << 4)
68 #define UCB_TS_CR_TSPX_GND	(1 << 5)
69 #define UCB_TS_CR_TSMY_GND	(1 << 6)
70 #define UCB_TS_CR_TSPY_GND	(1 << 7)
71 #define UCB_TS_CR_MODE_INT	(0 << 8)
72 #define UCB_TS_CR_MODE_PRES	(1 << 8)
73 #define UCB_TS_CR_MODE_POS	(2 << 8)
74 #define UCB_TS_CR_BIAS_ENA	(1 << 11)
75 #define UCB_TS_CR_TSPX_LOW	(1 << 12)
76 #define UCB_TS_CR_TSMX_LOW	(1 << 13)
77 
78 #define UCB_ADC_CR	0x0a
79 #define UCB_ADC_SYNC_ENA	(1 << 0)
80 #define UCB_ADC_VREFBYP_CON	(1 << 1)
81 #define UCB_ADC_INP_TSPX	(0 << 2)
82 #define UCB_ADC_INP_TSMX	(1 << 2)
83 #define UCB_ADC_INP_TSPY	(2 << 2)
84 #define UCB_ADC_INP_TSMY	(3 << 2)
85 #define UCB_ADC_INP_AD0		(4 << 2)
86 #define UCB_ADC_INP_AD1		(5 << 2)
87 #define UCB_ADC_INP_AD2		(6 << 2)
88 #define UCB_ADC_INP_AD3		(7 << 2)
89 #define UCB_ADC_EXT_REF		(1 << 5)
90 #define UCB_ADC_START		(1 << 7)
91 #define UCB_ADC_ENA		(1 << 15)
92 
93 #define UCB_ADC_DATA	0x0b
94 #define UCB_ADC_DAT_VAL		(1 << 15)
95 #define UCB_ADC_DAT(x)		(((x) & 0x7fe0) >> 5)
96 
97 #define UCB_ID		0x0c
98 #define UCB_ID_1200		0x1004
99 #define UCB_ID_1300		0x1005
100 #define UCB_ID_TC35143          0x9712
101 
102 #define UCB_MODE	0x0d
103 #define UCB_MODE_DYN_VFLAG_ENA	(1 << 12)
104 #define UCB_MODE_AUD_OFF_CAN	(1 << 13)
105 
106 enum ucb1x00_reset {
107 	UCB_RST_PROBE,
108 	UCB_RST_RESUME,
109 	UCB_RST_SUSPEND,
110 	UCB_RST_REMOVE,
111 	UCB_RST_PROBE_FAIL,
112 };
113 
114 struct ucb1x00_plat_data {
115 	void			(*reset)(enum ucb1x00_reset);
116 	unsigned		irq_base;
117 	int			gpio_base;
118 	unsigned		can_wakeup;
119 };
120 
121 struct ucb1x00 {
122 	raw_spinlock_t		irq_lock;
123 	struct mcp		*mcp;
124 	unsigned int		irq;
125 	int			irq_base;
126 	struct mutex		adc_mutex;
127 	spinlock_t		io_lock;
128 	u16			id;
129 	u16			io_dir;
130 	u16			io_out;
131 	u16			adc_cr;
132 	u16			irq_fal_enbl;
133 	u16			irq_ris_enbl;
134 	u16			irq_mask;
135 	u16			irq_wake;
136 	struct device		dev;
137 	struct list_head	node;
138 	struct list_head	devs;
139 	struct gpio_chip 	gpio;
140 };
141 
142 struct ucb1x00_driver;
143 
144 struct ucb1x00_dev {
145 	struct list_head	dev_node;
146 	struct list_head	drv_node;
147 	struct ucb1x00		*ucb;
148 	struct ucb1x00_driver	*drv;
149 	void			*priv;
150 };
151 
152 struct ucb1x00_driver {
153 	struct list_head	node;
154 	struct list_head	devs;
155 	int	(*add)(struct ucb1x00_dev *dev);
156 	void	(*remove)(struct ucb1x00_dev *dev);
157 	int	(*suspend)(struct ucb1x00_dev *dev);
158 	int	(*resume)(struct ucb1x00_dev *dev);
159 };
160 
161 #define classdev_to_ucb1x00(cd)	container_of(cd, struct ucb1x00, dev)
162 
163 int ucb1x00_register_driver(struct ucb1x00_driver *);
164 void ucb1x00_unregister_driver(struct ucb1x00_driver *);
165 
166 /**
167  *	ucb1x00_clkrate - return the UCB1x00 SIB clock rate
168  *	@ucb: UCB1x00 structure describing chip
169  *
170  *	Return the SIB clock rate in Hz.
171  */
ucb1x00_clkrate(struct ucb1x00 * ucb)172 static inline unsigned int ucb1x00_clkrate(struct ucb1x00 *ucb)
173 {
174 	return mcp_get_sclk_rate(ucb->mcp);
175 }
176 
177 /**
178  *	ucb1x00_enable - enable the UCB1x00 SIB clock
179  *	@ucb: UCB1x00 structure describing chip
180  *
181  *	Enable the SIB clock.  This can be called multiple times.
182  */
ucb1x00_enable(struct ucb1x00 * ucb)183 static inline void ucb1x00_enable(struct ucb1x00 *ucb)
184 {
185 	mcp_enable(ucb->mcp);
186 }
187 
188 /**
189  *	ucb1x00_disable - disable the UCB1x00 SIB clock
190  *	@ucb: UCB1x00 structure describing chip
191  *
192  *	Disable the SIB clock.  The SIB clock will only be disabled
193  *	when the number of ucb1x00_enable calls match the number of
194  *	ucb1x00_disable calls.
195  */
ucb1x00_disable(struct ucb1x00 * ucb)196 static inline void ucb1x00_disable(struct ucb1x00 *ucb)
197 {
198 	mcp_disable(ucb->mcp);
199 }
200 
201 /**
202  *	ucb1x00_reg_write - write a UCB1x00 register
203  *	@ucb: UCB1x00 structure describing chip
204  *	@reg: UCB1x00 4-bit register index to write
205  *	@val: UCB1x00 16-bit value to write
206  *
207  *	Write the UCB1x00 register @reg with value @val.  The SIB
208  *	clock must be running for this function to return.
209  */
ucb1x00_reg_write(struct ucb1x00 * ucb,unsigned int reg,unsigned int val)210 static inline void ucb1x00_reg_write(struct ucb1x00 *ucb, unsigned int reg, unsigned int val)
211 {
212 	mcp_reg_write(ucb->mcp, reg, val);
213 }
214 
215 /**
216  *	ucb1x00_reg_read - read a UCB1x00 register
217  *	@ucb: UCB1x00 structure describing chip
218  *	@reg: UCB1x00 4-bit register index to write
219  *
220  *	Read the UCB1x00 register @reg and return its value.  The SIB
221  *	clock must be running for this function to return.
222  */
ucb1x00_reg_read(struct ucb1x00 * ucb,unsigned int reg)223 static inline unsigned int ucb1x00_reg_read(struct ucb1x00 *ucb, unsigned int reg)
224 {
225 	return mcp_reg_read(ucb->mcp, reg);
226 }
227 /**
228  *	ucb1x00_set_audio_divisor -
229  *	@ucb: UCB1x00 structure describing chip
230  *	@div: SIB clock divisor
231  */
ucb1x00_set_audio_divisor(struct ucb1x00 * ucb,unsigned int div)232 static inline void ucb1x00_set_audio_divisor(struct ucb1x00 *ucb, unsigned int div)
233 {
234 	mcp_set_audio_divisor(ucb->mcp, div);
235 }
236 
237 /**
238  *	ucb1x00_set_telecom_divisor -
239  *	@ucb: UCB1x00 structure describing chip
240  *	@div: SIB clock divisor
241  */
ucb1x00_set_telecom_divisor(struct ucb1x00 * ucb,unsigned int div)242 static inline void ucb1x00_set_telecom_divisor(struct ucb1x00 *ucb, unsigned int div)
243 {
244 	mcp_set_telecom_divisor(ucb->mcp, div);
245 }
246 
247 void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int, unsigned int);
248 void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int, unsigned int);
249 unsigned int ucb1x00_io_read(struct ucb1x00 *ucb);
250 
251 #define UCB_NOSYNC	(0)
252 #define UCB_SYNC	(1)
253 
254 unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync);
255 void ucb1x00_adc_enable(struct ucb1x00 *ucb);
256 void ucb1x00_adc_disable(struct ucb1x00 *ucb);
257 
258 #endif
259